From ec2ec07eb4c11ae047e738099a375a7da56992c1 Mon Sep 17 00:00:00 2001 From: "Travis F. Collins" Date: Wed, 4 Dec 2024 11:57:35 -0700 Subject: [PATCH] Add FFH demo version for ADRV9364 Signed-off-by: Travis F. Collins --- test/DemoTests.m | 12 +- .../+ccbob_lvds_hop/+rxtx/add_rx_tx_io.m | 201 +++++++++ .../+rxtx/hdlcoder_ref_design_customization.m | 18 + .../+ccbob_lvds_hop/+rxtx/plugin_board.m | 7 + .../+ccbob_lvds_hop/+rxtx/plugin_rd.m | 8 + .../ccbob_lvds_hop/fh_preprocess.tcl | 14 + .../ccbob_lvds_hop/system_top.v | 415 +++++++++++++++++ .../ccbob_lvds_hop/system_top_z7035.v | 419 ++++++++++++++++++ .../frequency-hopping/hdlworkflow_adrv9364.m | 172 +++++++ 9 files changed, 1265 insertions(+), 1 deletion(-) create mode 100644 trx_examples/targeting/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccbob_lvds_hop/+rxtx/add_rx_tx_io.m create mode 100644 trx_examples/targeting/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccbob_lvds_hop/+rxtx/hdlcoder_ref_design_customization.m create mode 100644 trx_examples/targeting/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccbob_lvds_hop/+rxtx/plugin_board.m create mode 100644 trx_examples/targeting/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccbob_lvds_hop/+rxtx/plugin_rd.m create mode 100644 trx_examples/targeting/frequency-hopping/ccbob_lvds_hop/fh_preprocess.tcl create mode 100644 trx_examples/targeting/frequency-hopping/ccbob_lvds_hop/system_top.v create mode 100644 trx_examples/targeting/frequency-hopping/ccbob_lvds_hop/system_top_z7035.v create mode 100644 trx_examples/targeting/frequency-hopping/hdlworkflow_adrv9364.m diff --git a/test/DemoTests.m b/test/DemoTests.m index fc56cf9f..a2dbe513 100644 --- a/test/DemoTests.m +++ b/test/DemoTests.m @@ -44,7 +44,17 @@ function buildHDLFrequencyHopper(testCase) if ~isempty(out) disp(out.message); end - % Check for BOOT.BIN + if exist('hdl_prj/vivado_ip_prj/boot/BOOT.BIN', 'file') ~= 2 + error('BOOT.BIN Failed'); + end + end + function buildHDLFrequencyHopperADRV9364(testCase) + testCase.setupVivado('2022.2'); + cd(fullfile(testCase.root,'trx_examples/targeting/frequency-hopping')); + hdlworkflow_adrv9364; + if ~isempty(out) + disp(out.message); + end if exist('hdl_prj/vivado_ip_prj/boot/BOOT.BIN', 'file') ~= 2 error('BOOT.BIN Failed'); end diff --git a/trx_examples/targeting/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccbob_lvds_hop/+rxtx/add_rx_tx_io.m b/trx_examples/targeting/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccbob_lvds_hop/+rxtx/add_rx_tx_io.m new file mode 100644 index 00000000..d69cab55 --- /dev/null +++ b/trx_examples/targeting/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccbob_lvds_hop/+rxtx/add_rx_tx_io.m @@ -0,0 +1,201 @@ +function add_rx_tx_io(hRD) + +% add AXI4 and AXI4-Lite slave interfaces +hRD.addAXI4SlaveInterface( ... + 'InterfaceConnection', 'axi_cpu_interconnect/M06_AXI', ... + 'BaseAddress', '0x43C00000', ... + 'MasterAddressSpace', 'sys_ps7/Data'); + +% % AGC control input for transceiver +% hRD.addInternalIOInterface( ... +% 'InterfaceID', 'Enable AGC', ... +% 'InterfaceType', 'OUT', ... +% 'PortName', 'en_agc', ... +% 'PortWidth', 1, ... +% 'InterfaceConnection', 'gpio_en_agc', ... +% 'IsRequired', false); + +% GPIO status output for transceiver +hRD.addInternalIOInterface( ... + 'InterfaceID', 'CTRL_STATUS', ... + 'InterfaceType', 'IN', ... + 'PortName', 'gpio_status', ... + 'PortWidth', 8, ... + 'InterfaceConnection', 'gpio_status', ... + 'IsRequired', false); + +% GPIO Control input for transceiver +hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 CTRL IN', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'gpio_ctl', ... + 'PortWidth', 4, ... + 'InterfaceConnection', 'gpio_ctl', ... + 'IsRequired', false); + +% DMA Ready signal +hRD.addInternalIOInterface( ... + 'InterfaceID', 'DMA Ready', ... + 'InterfaceType', 'IN', ... + 'PortName', 'dma_rdy', ... + 'PortWidth', 1, ... + 'InterfaceConnection', 'axi_ad9361_adc_dma/s_axis_ready', ... + 'IsRequired', false); + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% Rx Reference design interfaces +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data Valid OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'dut_data_valid', ... + 'PortWidth', 1, ... + 'InterfaceConnection', 'util_ad9361_adc_pack/fifo_wr_en', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 0 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'dut_data_0', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_adc_pack/fifo_wr_data_0', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 1 OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'dut_data_1', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_adc_pack/fifo_wr_data_1', ... + 'IsRequired', false); + +% hRD.addInternalIOInterface( ... +% 'InterfaceID', 'IP Data 2 OUT', ... +% 'InterfaceType', 'OUT', ... +% 'PortName', 'dut_data_2', ... +% 'PortWidth', 16, ... +% 'InterfaceConnection', 'util_ad9361_adc_pack/fifo_wr_data_2', ... +% 'IsRequired', false); + +% hRD.addInternalIOInterface( ... +% 'InterfaceID', 'IP Data 3 OUT', ... +% 'InterfaceType', 'OUT', ... +% 'PortName', 'dut_data_3', ... +% 'PortWidth', 16, ... +% 'InterfaceConnection', 'util_ad9361_adc_pack/fifo_wr_data_3', ... +% 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 ADC Data I0', ... + 'InterfaceType', 'IN', ... + 'PortName', 'sys_wfifo_0_dma_wdata', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_adc_fifo/dout_data_0', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 ADC Data Q0', ... + 'InterfaceType', 'IN', ... + 'PortName', 'sys_wfifo_1_dma_wdata', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_adc_fifo/dout_data_1', ... + 'IsRequired', false); + +% hRD.addInternalIOInterface( ... +% 'InterfaceID', 'AD9361 ADC Data I1', ... +% 'InterfaceType', 'IN', ... +% 'PortName', 'sys_wfifo_2_dma_wdata', ... +% 'PortWidth', 16, ... +% 'InterfaceConnection', 'util_ad9361_adc_fifo/dout_data_2', ... +% 'IsRequired', false); + +% hRD.addInternalIOInterface( ... +% 'InterfaceID', 'AD9361 ADC Data Q1', ... +% 'InterfaceType', 'IN', ... +% 'PortName', 'sys_wfifo_3_dma_wdata', ... +% 'PortWidth', 16, ... +% 'InterfaceConnection', 'util_ad9361_adc_fifo/dout_data_3', ... +% 'IsRequired', false); + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% Tx Reference design interfaces +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 DAC Data I0', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad9361_dac_data_i0', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad9361_dac_fifo/din_data_0', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'AD9361 DAC Data Q0', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'axi_ad9361_dac_data_q0', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'axi_ad9361_dac_fifo/din_data_1', ... + 'IsRequired', false); + +% hRD.addInternalIOInterface( ... +% 'InterfaceID', 'AD9361 DAC Data I1', ... +% 'InterfaceType', 'OUT', ... +% 'PortName', 'axi_ad9361_dac_data_i1', ... +% 'PortWidth', 16, ... +% 'InterfaceConnection', 'axi_ad9361_dac_fifo/din_data_2', ... +% 'IsRequired', false); + +% hRD.addInternalIOInterface( ... +% 'InterfaceID', 'AD9361 DAC Data Q1', ... +% 'InterfaceType', 'OUT', ... +% 'PortName', 'axi_ad9361_dac_data_q1', ... +% 'PortWidth', 16, ... +% 'InterfaceConnection', 'axi_ad9361_dac_fifo/din_data_3', ... +% 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 0 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'util_dac_unpack_dac_data_00', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_dac_upack/fifo_rd_data_0', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Data 1 IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'util_dac_unpack_dac_data_01', ... + 'PortWidth', 16, ... + 'InterfaceConnection', 'util_ad9361_dac_upack/fifo_rd_data_1', ... + 'IsRequired', false); + +% hRD.addInternalIOInterface( ... +% 'InterfaceID', 'IP Data 2 IN', ... +% 'InterfaceType', 'IN', ... +% 'PortName', 'util_dac_unpack_dac_data_02', ... +% 'PortWidth', 16, ... +% 'InterfaceConnection', 'util_ad9361_dac_upack/fifo_rd_data_2', ... +% 'IsRequired', false); + +% hRD.addInternalIOInterface( ... +% 'InterfaceID', 'IP Data 3 IN', ... +% 'InterfaceType', 'IN', ... +% 'PortName', 'util_dac_unpack_dac_data_03', ... +% 'PortWidth', 16, ... +% 'InterfaceConnection', 'util_ad9361_dac_upack/fifo_rd_data_3', ... +% 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Load Tx Data OUT', ... + 'InterfaceType', 'OUT', ... + 'PortName', 'util_dac_unpack_dac_valid_00', ... + 'PortWidth', 1, ... + 'InterfaceConnection', 'util_ad9361_dac_upack/din_valid_in_0', ... + 'IsRequired', false); + +hRD.addInternalIOInterface( ... + 'InterfaceID', 'IP Valid Tx Data IN', ... + 'InterfaceType', 'IN', ... + 'PortName', 'util_dac_unpack_upack_valid_00', ... + 'PortWidth', 1, ... + 'InterfaceConnection', 'util_ad9361_dac_upack/fifo_rd_valid', ... + 'IsRequired', false); \ No newline at end of file diff --git a/trx_examples/targeting/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccbob_lvds_hop/+rxtx/hdlcoder_ref_design_customization.m b/trx_examples/targeting/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccbob_lvds_hop/+rxtx/hdlcoder_ref_design_customization.m new file mode 100644 index 00000000..42358270 --- /dev/null +++ b/trx_examples/targeting/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccbob_lvds_hop/+rxtx/hdlcoder_ref_design_customization.m @@ -0,0 +1,18 @@ +function [rd, boardName] = hdlcoder_ref_design_customization +% Reference design plugin registration file +% 1. The registration file with this name inside of a board plugin folder +% will be picked up +% 2. Any registration file with this name on MATLAB path will also be picked up +% 3. The registration file returns a cell array pointing to the location of +% the reference design plugins +% 4. The registration file also returns its associated board name +% 5. Reference design plugin must be a package folder accessible from +% MATLAB path, and contains a reference design definition file + +rd = {'AnalogDevicesDemo.adrv9364z7020.ccbob_lvds_hop.rxtx.plugin_rd', ... + }; + +boardName = 'AnalogDevicesDemo adrv9364z7020 bob lvds hop (Rx & Tx)'; + +end + diff --git a/trx_examples/targeting/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccbob_lvds_hop/+rxtx/plugin_board.m b/trx_examples/targeting/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccbob_lvds_hop/+rxtx/plugin_board.m new file mode 100644 index 00000000..350900e4 --- /dev/null +++ b/trx_examples/targeting/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccbob_lvds_hop/+rxtx/plugin_board.m @@ -0,0 +1,7 @@ +function hP = plugin_board() +% Zynq Platform PCore +% Use Plugin API to create board plugin object + +% Call the common board definition function +hP = AnalogDevices.adrv9364z7020.common.plugin_board('bob lvds hop', 'Rx & Tx'); + diff --git a/trx_examples/targeting/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccbob_lvds_hop/+rxtx/plugin_rd.m b/trx_examples/targeting/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccbob_lvds_hop/+rxtx/plugin_rd.m new file mode 100644 index 00000000..f84da0c9 --- /dev/null +++ b/trx_examples/targeting/frequency-hopping/+AnalogDevicesDemo/+adrv9361z7035/+ccbob_lvds_hop/+rxtx/plugin_rd.m @@ -0,0 +1,8 @@ +function hRD = plugin_rd +% Reference design definition + +% Copyright 2014-2015 The MathWorks, Inc. + +% Call the common reference design definition function +hRD = AnalogDevicesDemo.adrv9364z7020.common.plugin_rd('ccbob_lvds_hop', 'Rx & Tx'); +AnalogDevicesDemo.adrv9364z7020.ccbob_lvds_hop.rxtx.add_rx_tx_io(hRD); \ No newline at end of file diff --git a/trx_examples/targeting/frequency-hopping/ccbob_lvds_hop/fh_preprocess.tcl b/trx_examples/targeting/frequency-hopping/ccbob_lvds_hop/fh_preprocess.tcl new file mode 100644 index 00000000..9ee84407 --- /dev/null +++ b/trx_examples/targeting/frequency-hopping/ccbob_lvds_hop/fh_preprocess.tcl @@ -0,0 +1,14 @@ +set ad_hdl_dir [pwd] + +#### Move files +file rename -force $ad_hdl_dir/hdl/vendor/AnalogDevices/vivado/scripts $ad_hdl_dir/scripts +file rename -force $ad_hdl_dir/hdl/vendor/AnalogDevices/vivado/projects $ad_hdl_dir/projects +file rename -force $ad_hdl_dir/hdl/vendor/AnalogDevices/vivado/library $ad_hdl_dir/library +file copy -force $ad_hdl_dir/trx_examples/targeting/frequency-hopping/ccbob_lvds_hop/system_top.v $ad_hdl_dir/projects/adrv9364z7020/ccbob_lvds/system_top.v +set f [open $ad_hdl_dir/projects/adrv9364z7020/ccbob_lvds/system_bd.tcl "a"] + +# To check +puts $f "create_bd_port -dir O gpio_en_agc" +puts $f "create_bd_port -from 0 -to 7 -dir I gpio_status" +puts $f "create_bd_port -from 0 -to 3 -dir O gpio_ctl" +close $f \ No newline at end of file diff --git a/trx_examples/targeting/frequency-hopping/ccbob_lvds_hop/system_top.v b/trx_examples/targeting/frequency-hopping/ccbob_lvds_hop/system_top.v new file mode 100644 index 00000000..2c6d1f79 --- /dev/null +++ b/trx_examples/targeting/frequency-hopping/ccbob_lvds_hop/system_top.v @@ -0,0 +1,415 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + output eth1_mdc, + inout eth1_mdio, + input eth1_rgmii_rxclk, + input eth1_rgmii_rxctl, + input [ 3:0] eth1_rgmii_rxdata, + output eth1_rgmii_txclk, + output eth1_rgmii_txctl, + output [ 3:0] eth1_rgmii_txdata, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + output hdmi_pd, + input hdmi_intn, + + output spdif, + input spdif_in, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + inout iic_scl, + inout iic_sda, + + inout [20:0] gpio_bd, + + output fan_pwm, + input fan_tach, + + input clk_0_p, + input clk_0_n, + input clk_1_p, + input clk_1_n, + output [53:0] gp_out, + input [53:0] gp_in, + + input gt_ref_clk_0_p, + input gt_ref_clk_0_n, + input gt_ref_clk_1_p, + input gt_ref_clk_1_n, + output [ 1:0] gt_tx_p, + output [ 1:0] gt_tx_n, + input [ 1:0] gt_rx_p, + input [ 1:0] gt_rx_n, + + output ad9517_csn, + output ad9517_clk, + output ad9517_mosi, + input ad9517_miso, + inout ad9517_pdn, + inout ad9517_ref_sel, + inout ad9517_ld, + inout ad9517_status, + + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, + + output enable, + output txnrx, + input clkout_in, + inout tdd_sync, + + inout gpio_rf0, + output gpio_rf1, + output gpio_rf2, + input gpio_rf3, + input gpio_rf4, + inout gpio_rf5, + inout gpio_clksel, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + output [ 3:0] gpio_ctl, + input [ 7:0] gpio_status, + + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso +); + + // internal signals + + wire [ 1:0] spi_csn_s; + wire spi_clk_s; + wire spi_mosi_s; + wire spi_miso_s; + wire sys_cpu_clk; + wire clk_0; + wire clk_1; + wire gt_ref_clk_1; + wire gt_ref_clk_0; + wire [63:0] gp_out_s; + wire [63:0] gp_in_s; + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire tdd_sync_i; + wire tdd_sync_o; + wire tdd_sync_t; + + // assignments + + assign fan_pwm = 1'b1; + assign hdmi_pd = 1'b0; + assign spi_csn = spi_csn_s[0]; + assign spi_clk = spi_clk_s; + assign spi_mosi = spi_mosi_s; + assign ad9517_csn = spi_csn_s[1]; + assign ad9517_clk = spi_clk_s; + assign ad9517_mosi = spi_mosi_s; + assign spi_miso_s = (~spi_csn_s[0] & spi_miso) | (~spi_csn_s[1] & ad9517_miso); + + // loopback signals + + assign gp_out[53:0] = gp_out_s[53:0]; + assign gp_in_s[63:54] = gp_out_s[63:54]; + assign gp_in_s[53:0] = gp_in[53:0]; + + // instantiations + + IBUFDS i_ibufds_clk_0 ( + .I (clk_0_p), + .IB (clk_0_n), + .O (clk_0)); + + IBUFDS i_ibufds_clk_1 ( + .I (clk_1_p), + .IB (clk_1_n), + .O (clk_1)); + + IBUFDS_GTE2 i_ibufds_gt_ref_clk_0 ( + .CEB (1'd0), + .I (gt_ref_clk_0_p), + .IB (gt_ref_clk_0_n), + .O (gt_ref_clk_0), + .ODIV2 ()); + + IBUFDS_GTE2 i_ibufds_gt_ref_clk_1 ( + .CEB (1'd0), + .I (gt_ref_clk_1_p), + .IB (gt_ref_clk_1_n), + .O (gt_ref_clk_1), + .ODIV2 ()); + + ad_iobuf #( + .DATA_WIDTH(1) + ) i_iobuf_tdd_sync ( + .dio_t (tdd_sync_t), + .dio_i (tdd_sync_o), + .dio_o (tdd_sync_i), + .dio_p (tdd_sync)); + + // board gpio - 31-0 + + assign gpio_i[31:21] = gpio_o[31:21]; + + ad_iobuf #( + .DATA_WIDTH(21) + ) i_iobuf_bd ( + .dio_t (gpio_t[20:0]), + .dio_i (gpio_o[20:0]), + .dio_o (gpio_i[20:0]), + .dio_p (gpio_bd)); + + // unused gpio - 63-61 + + assign gpio_i[63:61] = gpio_o[63:61]; + + // rf & ad9517 gpio - 60:56 + + ad_iobuf #( + .DATA_WIDTH(5) + ) i_iobuf ( + .dio_t (gpio_t[60:56]), + .dio_i (gpio_o[60:56]), + .dio_o (gpio_i[60:56]), + .dio_p ({ ad9517_pdn, // 60:60 + ad9517_ref_sel, // 59:59 + ad9517_ld, // 58:58 + ad9517_status, // 57:57 + gpio_rf0})); // 56:56 + + // unused gpio - 55:53 + + assign gpio_i[55:53] = gpio_o[55:53]; + + // rf & clock-select gpio - 52:51 + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iobuf_rf_1 ( + .dio_t (gpio_t[52:51]), + .dio_i (gpio_o[52:51]), + .dio_o (gpio_i[52:51]), + .dio_p ({ gpio_rf5, // 52:52 + gpio_clksel})); // 51:51 + + // unused gpio - 50:47 + + assign gpio_i[50:47] = gpio_o[50:47]; + + // ad9361 gpio - 46:32 + + // ad_iobuf #( + // .DATA_WIDTH(15) + // ) i_iobuf_ad9361 ( + // .dio_t (gpio_t[46:32]), + // .dio_i (gpio_o[46:32]), + // .dio_o (gpio_i[46:32]), + // .dio_p ({ gpio_resetb, // 46:46 + // gpio_sync, // 45:45 + // gpio_en_agc, // 44:44 + // gpio_ctl, // 43:40 + // gpio_status})); // 39:32 + + ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_ad9361 ( + .dio_t ({gpio_t[46:45]}), + .dio_i ({gpio_o[46:45]}), + .dio_o ({gpio_i[46:45]}), + .dio_p ({ gpio_resetb, // 46:46 + gpio_sync })); // 45:45 + + // ad9361 input protection + + ad_adl5904_rst i_adl5904_rst_a ( + .sys_cpu_clk (sys_cpu_clk), + .rf_peak_det_n (gpio_rf4), + .rf_peak_rst (gpio_rf2)); + + ad_adl5904_rst i_adl5904_rst_b ( + .sys_cpu_clk (sys_cpu_clk), + .rf_peak_det_n (gpio_rf3), + .rf_peak_rst (gpio_rf1)); + + // instantiations + + system_wrapper i_system_wrapper ( + .clk_0 (clk_0), + .clk_1 (clk_1), + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .eth1_intn (1'b1), + .eth1_mdio_mdc (eth1_mdc), + .eth1_mdio_mdio_io (eth1_mdio), + .eth1_rgmii_rd (eth1_rgmii_rxdata), + .eth1_rgmii_rx_ctl (eth1_rgmii_rxctl), + .eth1_rgmii_rxc (eth1_rgmii_rxclk), + .eth1_rgmii_td (eth1_rgmii_txdata), + .eth1_rgmii_tx_ctl (eth1_rgmii_txctl), + .eth1_rgmii_txc (eth1_rgmii_txclk), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gp_in_0 (gp_in_s[31:0]), + .gp_in_1 (gp_in_s[63:32]), + .gp_out_0 (gp_out_s[31:0]), + .gp_out_1 (gp_out_s[63:32]), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .gps_pps (1'b0), + .gt_ref_clk_0 (gt_ref_clk_0), + .gt_ref_clk_1 (gt_ref_clk_1), + .gt_rx_n (gt_rx_n), + .gt_rx_p (gt_rx_p), + .gt_tx_n (gt_tx_n), + .gt_tx_p (gt_tx_p), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .otg_vbusoc (1'b0), + .rx_clk_in_n (rx_clk_in_n), + .rx_clk_in_p (rx_clk_in_p), + .rx_data_in_n (rx_data_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_frame_in_p (rx_frame_in_p), + .spdif (spdif), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk_s), + .spi0_csn_0_o (spi_csn_s[0]), + .spi0_csn_1_o (spi_csn_s[1]), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso_s), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi_s), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .sys_cpu_clk_out (sys_cpu_clk), + .tdd_sync_i (tdd_sync_i), + .tdd_sync_o (tdd_sync_o), + .tdd_sync_t (tdd_sync_t), + .tx_clk_out_n (tx_clk_out_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_frame_out_p (tx_frame_out_p), + .txnrx (txnrx), + .up_enable (gpio_o[47]), + .up_txnrx (gpio_o[48])); + +endmodule diff --git a/trx_examples/targeting/frequency-hopping/ccbob_lvds_hop/system_top_z7035.v b/trx_examples/targeting/frequency-hopping/ccbob_lvds_hop/system_top_z7035.v new file mode 100644 index 00000000..45da2b64 --- /dev/null +++ b/trx_examples/targeting/frequency-hopping/ccbob_lvds_hop/system_top_z7035.v @@ -0,0 +1,419 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + output eth1_mdc, + inout eth1_mdio, + input eth1_rgmii_rxclk, + input eth1_rgmii_rxctl, + input [ 3:0] eth1_rgmii_rxdata, + output eth1_rgmii_txclk, + output eth1_rgmii_txctl, + output [ 3:0] eth1_rgmii_txdata, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + output hdmi_pd, + input hdmi_intn, + + output spdif, + input spdif_in, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + inout iic_scl, + inout iic_sda, + + inout [20:0] gpio_bd, + + output fan_pwm, + input fan_tach, + + input clk_0_p, + input clk_0_n, + input clk_1_p, + input clk_1_n, + output [53:0] gp_out, + input [53:0] gp_in, + + input gt_ref_clk_0_p, + input gt_ref_clk_0_n, + input gt_ref_clk_1_p, + input gt_ref_clk_1_n, + output [ 1:0] gt_tx_p, + output [ 1:0] gt_tx_n, + input [ 1:0] gt_rx_p, + input [ 1:0] gt_rx_n, + + output ad9517_csn, + output ad9517_clk, + output ad9517_mosi, + input ad9517_miso, + inout ad9517_pdn, + inout ad9517_ref_sel, + inout ad9517_ld, + inout ad9517_status, + + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, + + output enable, + output txnrx, + input clkout_in, + inout tdd_sync, + + inout gpio_rf0, + output gpio_rf1, + output gpio_rf2, + input gpio_rf3, + input gpio_rf4, + inout gpio_rf5, + inout gpio_clksel, + inout gpio_resetb, + inout gpio_sync, + output gpio_en_agc, + output [ 3:0] gpio_ctl, + input [ 7:0] gpio_status, + + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso); + + // internal signals + + wire [ 1:0] spi_csn_s; + wire spi_clk_s; + wire spi_mosi_s; + wire spi_miso_s; + wire sys_cpu_clk; + wire clk_0; + wire clk_1; + wire gt_ref_clk_1; + wire gt_ref_clk_0; + wire [63:0] gp_out_s; + wire [63:0] gp_in_s; + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire tdd_sync_i; + wire tdd_sync_o; + wire tdd_sync_t; + + // assignments + + assign fan_pwm = 1'b1; + assign hdmi_pd = 1'b0; + assign spi_csn = spi_csn_s[0]; + assign spi_clk = spi_clk_s; + assign spi_mosi = spi_mosi_s; + assign ad9517_csn = spi_csn_s[1]; + assign ad9517_clk = spi_clk_s; + assign ad9517_mosi = spi_mosi_s; + assign spi_miso_s = (~spi_csn_s[0] & spi_miso) | (~spi_csn_s[1] & ad9517_miso); + + // loopback signals + + assign gp_out[53:0] = gp_out_s[53:0]; + assign gp_in_s[63:54] = gp_out_s[63:54]; + assign gp_in_s[53:0] = gp_in[53:0]; + + // instantiations + + IBUFDS i_ibufds_clk_0 ( + .I (clk_0_p), + .IB (clk_0_n), + .O (clk_0)); + + IBUFDS i_ibufds_clk_1 ( + .I (clk_1_p), + .IB (clk_1_n), + .O (clk_1)); + + IBUFDS_GTE2 i_ibufds_gt_ref_clk_0 ( + .CEB (1'd0), + .I (gt_ref_clk_0_p), + .IB (gt_ref_clk_0_n), + .O (gt_ref_clk_0), + .ODIV2 ()); + + IBUFDS_GTE2 i_ibufds_gt_ref_clk_1 ( + .CEB (1'd0), + .I (gt_ref_clk_1_p), + .IB (gt_ref_clk_1_n), + .O (gt_ref_clk_1), + .ODIV2 ()); + + ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_tdd_sync ( + .dio_t (tdd_sync_t), + .dio_i (tdd_sync_o), + .dio_o (tdd_sync_i), + .dio_p (tdd_sync)); + + // board gpio - 31-0 + + assign gpio_i[31:21] = gpio_o[31:21]; + + ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_bd ( + .dio_t (gpio_t[20:0]), + .dio_i (gpio_o[20:0]), + .dio_o (gpio_i[20:0]), + .dio_p (gpio_bd)); + + // unused gpio - 63-61 + + assign gpio_i[63:61] = gpio_o[63:61]; + + // rf & ad9517 gpio - 60:56 + + ad_iobuf #(.DATA_WIDTH(5)) i_iobuf ( + .dio_t (gpio_t[60:56]), + .dio_i (gpio_o[60:56]), + .dio_o (gpio_i[60:56]), + .dio_p ({ ad9517_pdn, // 60:60 + ad9517_ref_sel, // 59:59 + ad9517_ld, // 58:58 + ad9517_status, // 57:57 + gpio_rf0})); // 56:56 + + // unused gpio - 55:53 + + assign gpio_i[55:53] = gpio_o[55:53]; + + // rf & clock-select gpio - 52:51 + + ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_rf_1 ( + .dio_t (gpio_t[52:51]), + .dio_i (gpio_o[52:51]), + .dio_o (gpio_i[52:51]), + .dio_p ({ gpio_rf5, // 52:52 + gpio_clksel})); // 51:51 + + // unused gpio - 50:47 + + assign gpio_i[50:47] = gpio_o[50:47]; + + // ad9361 gpio - 46:32 + +// ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_ad9361 ( +// .dio_t (gpio_t[46:32]), +// .dio_i (gpio_o[46:32]), +// .dio_o (gpio_i[46:32]), +// .dio_p ({ gpio_resetb, // 46:46 +// gpio_sync, // 45:45 +// gpio_en_agc, // 44:44 +// gpio_ctl, // 43:40 +// gpio_status})); // 39:32 + +// ad_iobuf #(.DATA_WIDTH(14)) i_iobuf_ad9361 ( +// .dio_t ({gpio_t[46:45], gpio_t[43:32]}), +// .dio_i ({gpio_o[46:45], gpio_o[43:32]}), +// .dio_o ({gpio_i[46:45], gpio_i[43:32]}), +// .dio_p ({ gpio_resetb, // 46:46 +// gpio_sync, // 45:45 +// gpio_ctl, // 43:40 +// gpio_status})); // 39:32 + + ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_ad9361 ( + .dio_t ({gpio_t[46:45]}), + .dio_i ({gpio_o[46:45]}), + .dio_o ({gpio_i[46:45]}), + .dio_p ({ gpio_resetb, // 46:46 + gpio_sync })); // 45:45 + + // ad9361 input protection + + ad_adl5904_rst i_adl5904_rst_a ( + .sys_cpu_clk (sys_cpu_clk), + .rf_peak_det_n (gpio_rf4), + .rf_peak_rst (gpio_rf2)); + + ad_adl5904_rst i_adl5904_rst_b ( + .sys_cpu_clk (sys_cpu_clk), + .rf_peak_det_n (gpio_rf3), + .rf_peak_rst (gpio_rf1)); + + // instantiations + + system_wrapper i_system_wrapper ( + .clk_0 (clk_0), + .clk_1 (clk_1), + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .eth1_intn (1'b1), + .eth1_mdio_mdc (eth1_mdc), + .eth1_mdio_mdio_io (eth1_mdio), + .eth1_rgmii_rd (eth1_rgmii_rxdata), + .eth1_rgmii_rx_ctl (eth1_rgmii_rxctl), + .eth1_rgmii_rxc (eth1_rgmii_rxclk), + .eth1_rgmii_td (eth1_rgmii_txdata), + .eth1_rgmii_tx_ctl (eth1_rgmii_txctl), + .eth1_rgmii_txc (eth1_rgmii_txclk), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gp_in_0 (gp_in_s[31:0]), + .gp_in_1 (gp_in_s[63:32]), + .gp_out_0 (gp_out_s[31:0]), + .gp_out_1 (gp_out_s[63:32]), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .gps_pps (1'b0), + .gt_ref_clk_0 (gt_ref_clk_0), + .gt_ref_clk_1 (gt_ref_clk_1), + .gt_rx_n (gt_rx_n), + .gt_rx_p (gt_rx_p), + .gt_tx_n (gt_tx_n), + .gt_tx_p (gt_tx_p), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .otg_vbusoc (1'b0), + .rx_clk_in_n (rx_clk_in_n), + .rx_clk_in_p (rx_clk_in_p), + .rx_data_in_n (rx_data_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_frame_in_p (rx_frame_in_p), + .spdif (spdif), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk_s), + .spi0_csn_0_o (spi_csn_s[0]), + .spi0_csn_1_o (spi_csn_s[1]), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso_s), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi_s), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .sys_cpu_clk_out (sys_cpu_clk), + .tdd_sync_i (tdd_sync_i), + .tdd_sync_o (tdd_sync_o), + .tdd_sync_t (tdd_sync_t), + .tx_clk_out_n (tx_clk_out_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_frame_out_p (tx_frame_out_p), + .txnrx (txnrx), + .up_enable (gpio_o[47]), + .up_txnrx (gpio_o[48]), + .gpio_en_agc (gpio_en_agc), + .gpio_status (gpio_status), + .gpio_ctl (gpio_ctl)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/trx_examples/targeting/frequency-hopping/hdlworkflow_adrv9364.m b/trx_examples/targeting/frequency-hopping/hdlworkflow_adrv9364.m new file mode 100644 index 00000000..c9fb1bfb --- /dev/null +++ b/trx_examples/targeting/frequency-hopping/hdlworkflow_adrv9364.m @@ -0,0 +1,172 @@ +%-------------------------------------------------------------------------- +% HDL Workflow Script +%-------------------------------------------------------------------------- + +%% Load the Model +load_system('frequency_hopping'); + +%% Restore the Model to default HDL parameters +%hdlrestoreparams('frequency_hopping/HDL_DUT'); + +%% Model HDL Parameters +%% Set Model 'frequency_hopping' HDL parameters +hdlset_param('frequency_hopping', 'HDLSubsystem', 'frequency_hopping/HDL_DUT'); +hdlset_param('frequency_hopping', 'ReferenceDesign', 'ADRV9364 CCBOB_LVDS_HOP (Rx & Tx)'); +hdlset_param('frequency_hopping', 'SynthesisTool', 'Xilinx Vivado'); +hdlset_param('frequency_hopping', 'SynthesisToolChipFamily', 'Zynq'); +hdlset_param('frequency_hopping', 'SynthesisToolDeviceName', 'xc7z020'); +hdlset_param('frequency_hopping', 'SynthesisToolPackageName', 'clg400'); +hdlset_param('frequency_hopping', 'SynthesisToolSpeedValue', '-1'); +hdlset_param('frequency_hopping', 'TargetDirectory', 'hdl_prj/hdlsrc'); +hdlset_param('frequency_hopping', 'TargetLanguage', 'Verilog'); +hdlset_param('frequency_hopping', 'TargetPlatform', 'AnalogDevices ADRV9364-Z7020 Frequency Hopping'); +hdlset_param('frequency_hopping', 'Workflow', 'IP Core Generation'); + +% Set SubSystem HDL parameters +hdlset_param('frequency_hopping/HDL_DUT', 'AXI4SlaveIDWidth', '12'); +hdlset_param('frequency_hopping/HDL_DUT', 'ProcessorFPGASynchronization', 'Free running'); + +% Set Inport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/inReal1', 'IOInterface', 'AD9361 ADC Data I0 [0:15]'); +hdlset_param('frequency_hopping/HDL_DUT/inReal1', 'IOInterfaceMapping', '[0:15]'); + +% Set Inport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/inImag1', 'IOInterface', 'AD9361 ADC Data Q0 [0:15]'); +hdlset_param('frequency_hopping/HDL_DUT/inImag1', 'IOInterfaceMapping', '[0:15]'); + +% Set Inport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/inReal', 'IOInterface', 'IP Data 0 IN [0:15]'); +hdlset_param('frequency_hopping/HDL_DUT/inReal', 'IOInterfaceMapping', '[0:15]'); + +% Set Inport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/inImag', 'IOInterface', 'IP Data 1 IN [0:15]'); +hdlset_param('frequency_hopping/HDL_DUT/inImag', 'IOInterfaceMapping', '[0:15]'); + +% Set Inport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/ctrl_out', 'IOInterface', 'CTRL_STATUS [0:7]'); +hdlset_param('frequency_hopping/HDL_DUT/ctrl_out', 'IOInterfaceMapping', '[0:7]'); + +% Set Inport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/dwell_samples', 'IOInterface', 'AXI4-Lite'); +hdlset_param('frequency_hopping/HDL_DUT/dwell_samples', 'IOInterfaceMapping', 'x"100"'); + +% Set Inport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/enableHopping', 'IOInterface', 'AXI4-Lite'); +hdlset_param('frequency_hopping/HDL_DUT/enableHopping', 'IOInterfaceMapping', 'x"104"'); + +% Set Inport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/TxDMAEnable', 'IOInterface', 'No Interface Specified'); +hdlset_param('frequency_hopping/HDL_DUT/TxDMAEnable', 'IOInterfaceMapping', ''); + +% Set Inport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/manual_profile', 'IOInterface', 'AXI4-Lite'); +hdlset_param('frequency_hopping/HDL_DUT/manual_profile', 'IOInterfaceMapping', 'x"120"'); + +% Set Inport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/use_manual', 'IOInterface', 'AXI4-Lite'); +hdlset_param('frequency_hopping/HDL_DUT/use_manual', 'IOInterfaceMapping', 'x"124"'); + +% Set Inport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/force_enable', 'IOInterface', 'AXI4-Lite'); +hdlset_param('frequency_hopping/HDL_DUT/force_enable', 'IOInterfaceMapping', 'x"108"'); + +% Set Outport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/outReal1', 'IOInterface', 'IP Data 0 OUT [0:15]'); +hdlset_param('frequency_hopping/HDL_DUT/outReal1', 'IOInterfaceMapping', '[0:15]'); + +% Set Outport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/outImag1', 'IOInterface', 'IP Data 1 OUT [0:15]'); +hdlset_param('frequency_hopping/HDL_DUT/outImag1', 'IOInterfaceMapping', '[0:15]'); + +% Set Outport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/outReal', 'IOInterface', 'AD9361 DAC Data I0 [0:15]'); +hdlset_param('frequency_hopping/HDL_DUT/outReal', 'IOInterfaceMapping', '[0:15]'); + +% Set Outport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/outImag', 'IOInterface', 'AD9361 DAC Data Q0 [0:15]'); +hdlset_param('frequency_hopping/HDL_DUT/outImag', 'IOInterfaceMapping', '[0:15]'); + +% Set Outport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/enable', 'IOInterface', 'IP Data Valid OUT'); +hdlset_param('frequency_hopping/HDL_DUT/enable', 'IOInterfaceMapping', '[0]'); + +% Set Outport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/ctrl_in', 'IOInterface', 'AD9361 CTRL IN [0:3]'); +hdlset_param('frequency_hopping/HDL_DUT/ctrl_in', 'IOInterfaceMapping', '[0:3]'); + +% Set Outport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/profile', 'IOInterface', 'AXI4-Lite'); +hdlset_param('frequency_hopping/HDL_DUT/profile', 'IOInterfaceMapping', 'x"10C"'); + +% Set Outport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/hop_delay', 'IOInterface', 'AXI4-Lite'); +hdlset_param('frequency_hopping/HDL_DUT/hop_delay', 'IOInterfaceMapping', 'x"110"'); + +% Set Outport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/pll_status', 'IOInterface', 'AXI4-Lite'); +hdlset_param('frequency_hopping/HDL_DUT/pll_status', 'IOInterfaceMapping', 'x"114"'); + +% Set Outport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/hop_count', 'IOInterface', 'AXI4-Lite'); +hdlset_param('frequency_hopping/HDL_DUT/hop_count', 'IOInterfaceMapping', 'x"118"'); + +% Set Outport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/state', 'IOInterface', 'AXI4-Lite'); +hdlset_param('frequency_hopping/HDL_DUT/state', 'IOInterfaceMapping', 'x"11C"'); + +% Set Outport HDL parameters +hdlset_param('frequency_hopping/HDL_DUT/pll_unlocks', 'IOInterface', 'AXI4-Lite'); +hdlset_param('frequency_hopping/HDL_DUT/pll_unlocks', 'IOInterfaceMapping', 'x"128"'); + + +%% Workflow Configuration Settings +% Construct the Workflow Configuration Object with default settings +hWC = hdlcoder.WorkflowConfig('SynthesisTool','Xilinx Vivado','TargetWorkflow','IP Core Generation'); + +% Specify the top level project directory +hWC.ProjectFolder = 'hdl_prj'; +hWC.ReferenceDesignToolVersion = '2022.2'; +hWC.IgnoreToolVersionMismatch = true; +hWC.AllowUnsupportedToolVersion = true; + +% Set Workflow tasks to run +hWC.RunTaskGenerateRTLCodeAndIPCore = true; +hWC.RunTaskCreateProject = true; +hWC.RunTaskGenerateSoftwareInterfaceModel = false; +hWC.RunTaskBuildFPGABitstream = true; +hWC.RunTaskProgramTargetDevice = false; + +% Set properties related to 'RunTaskGenerateRTLCodeAndIPCore' Task +hWC.IPCoreRepository = ''; +hWC.GenerateIPCoreReport = true; + +% Set properties related to 'RunTaskCreateProject' Task +hWC.Objective = hdlcoder.Objective.None; +hWC.AdditionalProjectCreationTclFiles = ''; +hWC.EnableIPCaching = false; + +% Set properties related to 'RunTaskGenerateSoftwareInterfaceModel' Task +hWC.OperatingSystem = 'Linux'; + +% Set properties related to 'RunTaskBuildFPGABitstream' Task +hWC.RunExternalBuild = false; +hWC.TclFileForSynthesisBuild = hdlcoder.BuildOption.Custom; +hWC.CustomBuildTclFile = '../../../hdl/vendor/AnalogDevices/vivado/projects/scripts/adi_build.tcl'; + +% Set properties related to 'RunTaskProgramTargetDevice' Task +hWC.ProgrammingMethod = hdlcoder.ProgrammingMethod.Download; + +% Validate the Workflow Configuration Object +hWC.validate; + +%% Run the workflow +try + hdlcoder.runWorkflow('frequency_hopping/HDL_DUT', hWC, 'Verbosity', 'on'); + bdclose('all'); + out = []; +catch ME + if exist('hdl_prj/vivado_ip_prj/boot/BOOT.BIN','file') + ME = []; + end + out = ME;%.identifier +end