diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/gcr_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/gcr_regs.h index 318bef56..38e9f2e2 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/gcr_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/gcr_regs.h @@ -681,75 +681,63 @@ typedef struct { * @brief BTLE LDO Control Register * @{ */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXEN_POS 0 /**< BTLELDOCTRL_LDOTXEN Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXEN_POS)) /**< BTLELDOCTRL_LDOTXEN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBEN_POS 0 /**< BTLELDOCTRL_LDOBBEN Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBEN_POS)) /**< BTLELDOCTRL_LDOBBEN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD_POS 1 /**< BTLELDOCTRL_LDOTXPULLD Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD_POS)) /**< BTLELDOCTRL_LDOTXPULLD Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBPULLD_POS 1 /**< BTLELDOCTRL_LDOBBPULLD Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBPULLD_POS)) /**< BTLELDOCTRL_LDOBBPULLD Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS 2 /**< BTLELDOCTRL_LDOTXVSEL Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS)) /**< BTLELDOCTRL_LDOTXVSEL Mask */ -#define MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_7 ((uint32_t)0x0UL) /**< BTLELDOCTRL_LDOTXVSEL_0_7 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDOTXVSEL_0_7 (MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_7 << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS) /**< BTLELDOCTRL_LDOTXVSEL_0_7 Setting */ -#define MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_85 ((uint32_t)0x1UL) /**< BTLELDOCTRL_LDOTXVSEL_0_85 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDOTXVSEL_0_85 (MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_85 << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS) /**< BTLELDOCTRL_LDOTXVSEL_0_85 Setting */ -#define MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_9 ((uint32_t)0x2UL) /**< BTLELDOCTRL_LDOTXVSEL_0_9 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDOTXVSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS) /**< BTLELDOCTRL_LDOTXVSEL_0_9 Setting */ -#define MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_1_1 ((uint32_t)0x3UL) /**< BTLELDOCTRL_LDOTXVSEL_1_1 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDOTXVSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS) /**< BTLELDOCTRL_LDOTXVSEL_1_1 Setting */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS 2 /**< BTLELDOCTRL_LDOBBVSEL Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS)) /**< BTLELDOCTRL_LDOBBVSEL Mask */ +#define MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_0_85 ((uint32_t)0x0UL) /**< BTLELDOCTRL_LDOBBVSEL_0_85 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_0_85 (MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_0_85 << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS) /**< BTLELDOCTRL_LDOBBVSEL_0_85 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_0_9 ((uint32_t)0x1UL) /**< BTLELDOCTRL_LDOBBVSEL_0_9 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS) /**< BTLELDOCTRL_LDOBBVSEL_0_9 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_1_0 ((uint32_t)0x2UL) /**< BTLELDOCTRL_LDOBBVSEL_1_0 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_1_0 (MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_1_0 << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS) /**< BTLELDOCTRL_LDOBBVSEL_1_0 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_1_1 ((uint32_t)0x3UL) /**< BTLELDOCTRL_LDOBBVSEL_1_1 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS) /**< BTLELDOCTRL_LDOBBVSEL_1_1 Setting */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL0_POS 2 /**< BTLELDOCTRL_LDOTXVSEL0 Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL0 ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL0_POS)) /**< BTLELDOCTRL_LDOTXVSEL0 Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFEN_POS 4 /**< BTLELDOCTRL_LDORFEN Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFEN_POS)) /**< BTLELDOCTRL_LDORFEN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL1_POS 3 /**< BTLELDOCTRL_LDOTXVSEL1 Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL1 ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL1_POS)) /**< BTLELDOCTRL_LDOTXVSEL1 Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFPULLD_POS 5 /**< BTLELDOCTRL_LDORFPULLD Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFPULLD_POS)) /**< BTLELDOCTRL_LDORFPULLD Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXEN_POS 4 /**< BTLELDOCTRL_LDORXEN Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXEN_POS)) /**< BTLELDOCTRL_LDORXEN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS 6 /**< BTLELDOCTRL_LDORFVSEL Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS)) /**< BTLELDOCTRL_LDORFVSEL Mask */ +#define MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_0_85 ((uint32_t)0x0UL) /**< BTLELDOCTRL_LDORFVSEL_0_85 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_0_85 (MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_0_85 << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS) /**< BTLELDOCTRL_LDORFVSEL_0_85 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_0_9 ((uint32_t)0x1UL) /**< BTLELDOCTRL_LDORFVSEL_0_9 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS) /**< BTLELDOCTRL_LDORFVSEL_0_9 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_1_0 ((uint32_t)0x2UL) /**< BTLELDOCTRL_LDORFVSEL_1_0 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_1_0 (MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_1_0 << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS) /**< BTLELDOCTRL_LDORFVSEL_1_0 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_1_1 ((uint32_t)0x3UL) /**< BTLELDOCTRL_LDORFVSEL_1_1 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS) /**< BTLELDOCTRL_LDORFVSEL_1_1 Setting */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXPULLD_POS 5 /**< BTLELDOCTRL_LDORXPULLD Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXPULLD_POS)) /**< BTLELDOCTRL_LDORXPULLD Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFBYP_POS 8 /**< BTLELDOCTRL_LDORFBYP Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFBYP_POS)) /**< BTLELDOCTRL_LDORFBYP Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS 6 /**< BTLELDOCTRL_LDORXVSEL Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS)) /**< BTLELDOCTRL_LDORXVSEL Mask */ -#define MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_7 ((uint32_t)0x0UL) /**< BTLELDOCTRL_LDORXVSEL_0_7 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDORXVSEL_0_7 (MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_7 << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS) /**< BTLELDOCTRL_LDORXVSEL_0_7 Setting */ -#define MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_85 ((uint32_t)0x1UL) /**< BTLELDOCTRL_LDORXVSEL_0_85 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDORXVSEL_0_85 (MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_85 << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS) /**< BTLELDOCTRL_LDORXVSEL_0_85 Setting */ -#define MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_9 ((uint32_t)0x2UL) /**< BTLELDOCTRL_LDORXVSEL_0_9 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDORXVSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS) /**< BTLELDOCTRL_LDORXVSEL_0_9 Setting */ -#define MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_1_1 ((uint32_t)0x3UL) /**< BTLELDOCTRL_LDORXVSEL_1_1 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDORXVSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS) /**< BTLELDOCTRL_LDORXVSEL_1_1 Setting */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFDISCH_POS 9 /**< BTLELDOCTRL_LDORFDISCH Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFDISCH_POS)) /**< BTLELDOCTRL_LDORFDISCH Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL0_POS 6 /**< BTLELDOCTRL_LDORXVSEL0 Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL0 ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL0_POS)) /**< BTLELDOCTRL_LDORXVSEL0 Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBBYP_POS 10 /**< BTLELDOCTRL_LDOBBBYP Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBBYP_POS)) /**< BTLELDOCTRL_LDOBBBYP Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL1_POS 7 /**< BTLELDOCTRL_LDORXVSEL1 Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL1 ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL1_POS)) /**< BTLELDOCTRL_LDORXVSEL1 Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBDISCH_POS 11 /**< BTLELDOCTRL_LDOBBDISCH Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBDISCH_POS)) /**< BTLELDOCTRL_LDOBBDISCH Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXBYP_POS 8 /**< BTLELDOCTRL_LDORXBYP Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXBYP_POS)) /**< BTLELDOCTRL_LDORXBYP Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBENDLY_POS 12 /**< BTLELDOCTRL_LDOBBENDLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBENDLY_POS)) /**< BTLELDOCTRL_LDOBBENDLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXDISCH_POS 9 /**< BTLELDOCTRL_LDORXDISCH Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXDISCH_POS)) /**< BTLELDOCTRL_LDORXDISCH Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFENDLY_POS 13 /**< BTLELDOCTRL_LDORFENDLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFENDLY_POS)) /**< BTLELDOCTRL_LDORFENDLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXBYP_POS 10 /**< BTLELDOCTRL_LDOTXBYP Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXBYP_POS)) /**< BTLELDOCTRL_LDOTXBYP Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFBYPENENDLY_POS 14 /**< BTLELDOCTRL_LDORFBYPENENDLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFBYPENENDLY_POS)) /**< BTLELDOCTRL_LDORFBYPENENDLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXDISCH_POS 11 /**< BTLELDOCTRL_LDOTXDISCH Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXDISCH_POS)) /**< BTLELDOCTRL_LDOTXDISCH Mask */ - -#define MXC_F_GCR_BTLELDOCTRL_LDOTXENDLY_POS 12 /**< BTLELDOCTRL_LDOTXENDLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXENDLY_POS)) /**< BTLELDOCTRL_LDOTXENDLY Mask */ - -#define MXC_F_GCR_BTLELDOCTRL_LDORXENDLY_POS 13 /**< BTLELDOCTRL_LDORXENDLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXENDLY_POS)) /**< BTLELDOCTRL_LDORXENDLY Mask */ - -#define MXC_F_GCR_BTLELDOCTRL_LDORXBYPENENDLY_POS 14 /**< BTLELDOCTRL_LDORXBYPENENDLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXBYPENENDLY_POS)) /**< BTLELDOCTRL_LDORXBYPENENDLY Mask */ - -#define MXC_F_GCR_BTLELDOCTRL_LDOTXBYPENENDLY_POS 15 /**< BTLELDOCTRL_LDOTXBYPENENDLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXBYPENENDLY_POS)) /**< BTLELDOCTRL_LDOTXBYPENENDLY Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBBYPENENDLY_POS 15 /**< BTLELDOCTRL_LDOBBBYPENENDLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBBYPENENDLY_POS)) /**< BTLELDOCTRL_LDOBBBYPENENDLY Mask */ /**@} end of group GCR_BTLELDOCTRL_Register */ @@ -762,11 +750,11 @@ typedef struct { #define MXC_F_GCR_BTLELDODLY_BYPDLYCNT_POS 0 /**< BTLELDODLY_BYPDLYCNT Position */ #define MXC_F_GCR_BTLELDODLY_BYPDLYCNT ((uint32_t)(0xFFUL << MXC_F_GCR_BTLELDODLY_BYPDLYCNT_POS)) /**< BTLELDODLY_BYPDLYCNT Mask */ -#define MXC_F_GCR_BTLELDODLY_LDORXDLYCNT_POS 8 /**< BTLELDODLY_LDORXDLYCNT Position */ -#define MXC_F_GCR_BTLELDODLY_LDORXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDORXDLYCNT_POS)) /**< BTLELDODLY_LDORXDLYCNT Mask */ +#define MXC_F_GCR_BTLELDODLY_LDOBBDLYCNT_POS 8 /**< BTLELDODLY_LDOBBDLYCNT Position */ +#define MXC_F_GCR_BTLELDODLY_LDOBBDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDOBBDLYCNT_POS)) /**< BTLELDODLY_LDOBBDLYCNT Mask */ -#define MXC_F_GCR_BTLELDODLY_LDOTXDLYCNT_POS 20 /**< BTLELDODLY_LDOTXDLYCNT Position */ -#define MXC_F_GCR_BTLELDODLY_LDOTXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDOTXDLYCNT_POS)) /**< BTLELDODLY_LDOTXDLYCNT Mask */ +#define MXC_F_GCR_BTLELDODLY_LDORFDLYCNT_POS 20 /**< BTLELDODLY_LDORFDLYCNT Position */ +#define MXC_F_GCR_BTLELDODLY_LDORFDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDORFDLYCNT_POS)) /**< BTLELDODLY_LDORFDLYCNT Mask */ /**@} end of group GCR_BTLELDODLY_Register */ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/max32655.svd b/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/max32655.svd index 7e1cd74e..e371f160 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/max32655.svd +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/max32655.svd @@ -3822,36 +3822,36 @@ <addressOffset>0x74</addressOffset> <fields> <field> - <name>LDOTXEN</name> - <description>LDOTX Enable.</description> + <name>LDOBBEN</name> + <description>LDOBB Enable.</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDOTXPULLD</name> - <description>LDOTX Pull Down.</description> + <name>LDOBBPULLD</name> + <description>LDOBB Pull Down.</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDOTXVSEL</name> - <description>LDOTX Voltage Setting.</description> + <name>LDOBBVSEL</name> + <description>LDOBB Voltage Setting.</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> <enumeratedValues> - <enumeratedValue> - <name>0_7</name> - <description>0.7V</description> - <value>0</value> - </enumeratedValue> <enumeratedValue> <name>0_85</name> <description>0.85V</description> - <value>1</value> + <value>0</value> </enumeratedValue> <enumeratedValue> <name>0_9</name> <description>0.9V</description> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>1_0</name> + <description>1.0V</description> <value>2</value> </enumeratedValue> <enumeratedValue> @@ -3862,36 +3862,36 @@ </enumeratedValues> </field> <field> - <name>LDORXEN</name> - <description>LDORX Enable.</description> + <name>LDORFEN</name> + <description>LDORF Enable.</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDORXPULLD</name> - <description>LDOrX Pull Down.</description> + <name>LDORFPULLD</name> + <description>LDORF Pull Down.</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDORXVSEL</name> - <description>LDORX Voltage Setting.</description> + <name>LDORFVSEL</name> + <description>LDORF Voltage Setting.</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> <enumeratedValues> - <enumeratedValue> - <name>0_7</name> - <description>0.7V</description> - <value>0</value> - </enumeratedValue> <enumeratedValue> <name>0_85</name> <description>0.85V</description> - <value>1</value> + <value>0</value> </enumeratedValue> <enumeratedValue> <name>0_9</name> <description>0.9V</description> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>1_0</name> + <description>1.0V</description> <value>2</value> </enumeratedValue> <enumeratedValue> @@ -3902,50 +3902,50 @@ </enumeratedValues> </field> <field> - <name>LDORXBYP</name> - <description>LDORX Bypass Enable.</description> + <name>LDORFBYP</name> + <description>LDORF Bypass Enable.</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDORXDISCH</name> - <description>LDORX Discharge.</description> + <name>LDORFDISCH</name> + <description>LDORF Discharge.</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDOTXBYP</name> - <description>LDOTX Bypass Enable.</description> + <name>LDOBBBYP</name> + <description>LDOBB Bypass Enable.</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDOTXDISCH</name> - <description>LDOTX Discharge.</description> + <name>LDOBBDISCH</name> + <description>LDOBB Discharge.</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDOTXENDLY</name> - <description>LDOTX Enable Delay.</description> + <name>LDOBBENDLY</name> + <description>LDOBB Enable Delay.</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDORXENDLY</name> - <description>LDORX Enable Delay.</description> + <name>LDORFENDLY</name> + <description>LDORF Enable Delay.</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDORXBYPENENDLY</name> - <description>LDORX Bypass Enable Delay.</description> + <name>LDORFBYPENENDLY</name> + <description>LDORF Bypass Enable Delay.</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDOTXBYPENENDLY</name> - <description>LDOTX Bypass Enable Delay.</description> + <name>LDOBBBYPENENDLY</name> + <description>LDOBB Bypass Enable Delay.</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> @@ -3963,14 +3963,14 @@ <bitWidth>8</bitWidth> </field> <field> - <name>LDORXDLYCNT</name> - <description>LDORX Delay Count.</description> + <name>LDOBBDLYCNT</name> + <description>LDOBB Delay Count.</description> <bitOffset>8</bitOffset> <bitWidth>9</bitWidth> </field> <field> - <name>LDOTXDLYCNT</name> - <description>LDOTX Delay Count.</description> + <name>LDORFDLYCNT</name> + <description>LDOBB Delay Count.</description> <bitOffset>20</bitOffset> <bitWidth>9</bitWidth> </field> @@ -9257,16 +9257,16 @@ <access>read-write</access> <fields> <field> - <name>TX</name> - <description>TX LDO trim value.</description> - <bitOffset>0</bitOffset> + <name>RF</name> + <description>RF LDO trim value.</description> + <bitOffset>16</bitOffset> <bitWidth>5</bitWidth> <access>read-write</access> </field> <field> - <name>RX</name> - <description>RX LDO trim value.</description> - <bitOffset>8</bitOffset> + <name>BB</name> + <description>BB LDO trim value.</description> + <bitOffset>24</bitOffset> <bitWidth>5</bitWidth> <access>read-write</access> </field> diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/sir_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/sir_regs.h index 9d58a97e..42173bc2 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/sir_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/sir_regs.h @@ -130,11 +130,11 @@ typedef struct { * @brief BTLE LDO Trim register. * @{ */ -#define MXC_F_SIR_BTLE_LDO_TRIM_TX_POS 0 /**< BTLE_LDO_TRIM_TX Position */ -#define MXC_F_SIR_BTLE_LDO_TRIM_TX ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_TX_POS)) /**< BTLE_LDO_TRIM_TX Mask */ +#define MXC_F_SIR_BTLE_LDO_TRIM_RF_POS 16 /**< BTLE_LDO_TRIM_RF Position */ +#define MXC_F_SIR_BTLE_LDO_TRIM_RF ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_RF_POS)) /**< BTLE_LDO_TRIM_RF Mask */ -#define MXC_F_SIR_BTLE_LDO_TRIM_RX_POS 8 /**< BTLE_LDO_TRIM_RX Position */ -#define MXC_F_SIR_BTLE_LDO_TRIM_RX ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_RX_POS)) /**< BTLE_LDO_TRIM_RX Mask */ +#define MXC_F_SIR_BTLE_LDO_TRIM_BB_POS 24 /**< BTLE_LDO_TRIM_BB Position */ +#define MXC_F_SIR_BTLE_LDO_TRIM_BB ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_BB_POS)) /**< BTLE_LDO_TRIM_BB Mask */ /**@} end of group SIR_BTLE_LDO_TRIM_Register */ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gcr_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gcr_regs.h index a91ec534..a79038e7 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gcr_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gcr_regs.h @@ -953,64 +953,64 @@ typedef struct { * @brief BTLE LDO Control Register * @{ */ -#define MXC_F_GCR_BTLE_LDOCR_LDOTXEN_POS 0 /**< BTLE_LDOCR_LDOTXEN Position */ -#define MXC_F_GCR_BTLE_LDOCR_LDOTXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXEN_POS)) /**< BTLE_LDOCR_LDOTXEN Mask */ - -#define MXC_F_GCR_BTLE_LDOCR_LDOTXOPULLD_POS 1 /**< BTLE_LDOCR_LDOTXOPULLD Position */ -#define MXC_F_GCR_BTLE_LDOCR_LDOTXOPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXOPULLD_POS)) /**< BTLE_LDOCR_LDOTXOPULLD Mask */ - -#define MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS 2 /**< BTLE_LDOCR_LDOTXVSEL Position */ -#define MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS)) /**< BTLE_LDOCR_LDOTXVSEL Mask */ -#define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_7 ((uint32_t)0x0UL) /**< BTLE_LDOCR_LDOTXVSEL_0_7 Value */ -#define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_0_7 (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_7 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS) /**< BTLE_LDOCR_LDOTXVSEL_0_7 Setting */ -#define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_85 ((uint32_t)0x1UL) /**< BTLE_LDOCR_LDOTXVSEL_0_85 Value */ -#define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_0_85 (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_85 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS) /**< BTLE_LDOCR_LDOTXVSEL_0_85 Setting */ -#define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_9 ((uint32_t)0x2UL) /**< BTLE_LDOCR_LDOTXVSEL_0_9 Value */ -#define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_0_9 (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_9 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS) /**< BTLE_LDOCR_LDOTXVSEL_0_9 Setting */ -#define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_1_1 ((uint32_t)0x3UL) /**< BTLE_LDOCR_LDOTXVSEL_1_1 Value */ -#define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_1_1 (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_1_1 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS) /**< BTLE_LDOCR_LDOTXVSEL_1_1 Setting */ - -#define MXC_F_GCR_BTLE_LDOCR_LDORXEN_POS 4 /**< BTLE_LDOCR_LDORXEN Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDORXEN_POS 0 /**< BTLE_LDOCR_LDORXEN Position */ #define MXC_F_GCR_BTLE_LDOCR_LDORXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXEN_POS)) /**< BTLE_LDOCR_LDORXEN Mask */ -#define MXC_F_GCR_BTLE_LDOCR_LDORXPULLD_POS 5 /**< BTLE_LDOCR_LDORXPULLD Position */ -#define MXC_F_GCR_BTLE_LDOCR_LDORXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXPULLD_POS)) /**< BTLE_LDOCR_LDORXPULLD Mask */ +#define MXC_F_GCR_BTLE_LDOCR_LDORXOPULLD_POS 1 /**< BTLE_LDOCR_LDORXOPULLD Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDORXOPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXOPULLD_POS)) /**< BTLE_LDOCR_LDORXOPULLD Mask */ -#define MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS 6 /**< BTLE_LDOCR_LDORXVSEL Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS 2 /**< BTLE_LDOCR_LDORXVSEL Position */ #define MXC_F_GCR_BTLE_LDOCR_LDORXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS)) /**< BTLE_LDOCR_LDORXVSEL Mask */ -#define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_7 ((uint32_t)0x0UL) /**< BTLE_LDOCR_LDORXVSEL_0_7 Value */ -#define MXC_S_GCR_BTLE_LDOCR_LDORXVSEL_0_7 (MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_7 << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS) /**< BTLE_LDOCR_LDORXVSEL_0_7 Setting */ -#define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_85 ((uint32_t)0x1UL) /**< BTLE_LDOCR_LDORXVSEL_0_85 Value */ +#define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_85 ((uint32_t)0x0UL) /**< BTLE_LDOCR_LDORXVSEL_0_85 Value */ #define MXC_S_GCR_BTLE_LDOCR_LDORXVSEL_0_85 (MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_85 << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS) /**< BTLE_LDOCR_LDORXVSEL_0_85 Setting */ -#define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_9 ((uint32_t)0x2UL) /**< BTLE_LDOCR_LDORXVSEL_0_9 Value */ +#define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_9 ((uint32_t)0x1UL) /**< BTLE_LDOCR_LDORXVSEL_0_9 Value */ #define MXC_S_GCR_BTLE_LDOCR_LDORXVSEL_0_9 (MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_9 << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS) /**< BTLE_LDOCR_LDORXVSEL_0_9 Setting */ +#define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_1_0 ((uint32_t)0x2UL) /**< BTLE_LDOCR_LDORXVSEL_1_0 Value */ +#define MXC_S_GCR_BTLE_LDOCR_LDORXVSEL_1_0 (MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_1_0 << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS) /**< BTLE_LDOCR_LDORXVSEL_1_0 Setting */ #define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_1_1 ((uint32_t)0x3UL) /**< BTLE_LDOCR_LDORXVSEL_1_1 Value */ #define MXC_S_GCR_BTLE_LDOCR_LDORXVSEL_1_1 (MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_1_1 << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS) /**< BTLE_LDOCR_LDORXVSEL_1_1 Setting */ -#define MXC_F_GCR_BTLE_LDOCR_LDORXBYP_POS 8 /**< BTLE_LDOCR_LDORXBYP Position */ -#define MXC_F_GCR_BTLE_LDOCR_LDORXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXBYP_POS)) /**< BTLE_LDOCR_LDORXBYP Mask */ +#define MXC_F_GCR_BTLE_LDOCR_LDOTXEN_POS 4 /**< BTLE_LDOCR_LDOTXEN Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDOTXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXEN_POS)) /**< BTLE_LDOCR_LDOTXEN Mask */ -#define MXC_F_GCR_BTLE_LDOCR_LDORXDISCH_POS 9 /**< BTLE_LDOCR_LDORXDISCH Position */ -#define MXC_F_GCR_BTLE_LDOCR_LDORXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXDISCH_POS)) /**< BTLE_LDOCR_LDORXDISCH Mask */ +#define MXC_F_GCR_BTLE_LDOCR_LDOTXPULLD_POS 5 /**< BTLE_LDOCR_LDOTXPULLD Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDOTXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXPULLD_POS)) /**< BTLE_LDOCR_LDOTXPULLD Mask */ + +#define MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS 6 /**< BTLE_LDOCR_LDOTXVSEL Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS)) /**< BTLE_LDOCR_LDOTXVSEL Mask */ +#define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_85 ((uint32_t)0x0UL) /**< BTLE_LDOCR_LDOTXVSEL_0_85 Value */ +#define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_0_85 (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_85 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS) /**< BTLE_LDOCR_LDOTXVSEL_0_85 Setting */ +#define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_9 ((uint32_t)0x1UL) /**< BTLE_LDOCR_LDOTXVSEL_0_9 Value */ +#define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_0_9 (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_9 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS) /**< BTLE_LDOCR_LDOTXVSEL_0_9 Setting */ +#define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_1_0 ((uint32_t)0x2UL) /**< BTLE_LDOCR_LDOTXVSEL_1_0 Value */ +#define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_1_0 (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_1_0 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS) /**< BTLE_LDOCR_LDOTXVSEL_1_0 Setting */ +#define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_1_1 ((uint32_t)0x3UL) /**< BTLE_LDOCR_LDOTXVSEL_1_1 Value */ +#define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_1_1 (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_1_1 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS) /**< BTLE_LDOCR_LDOTXVSEL_1_1 Setting */ -#define MXC_F_GCR_BTLE_LDOCR_LDOTXBYP_POS 10 /**< BTLE_LDOCR_LDOTXBYP Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDOTXBYP_POS 8 /**< BTLE_LDOCR_LDOTXBYP Position */ #define MXC_F_GCR_BTLE_LDOCR_LDOTXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXBYP_POS)) /**< BTLE_LDOCR_LDOTXBYP Mask */ -#define MXC_F_GCR_BTLE_LDOCR_LDOTXDISCH_POS 11 /**< BTLE_LDOCR_LDOTXDISCH Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDOTXDISCH_POS 9 /**< BTLE_LDOCR_LDOTXDISCH Position */ #define MXC_F_GCR_BTLE_LDOCR_LDOTXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXDISCH_POS)) /**< BTLE_LDOCR_LDOTXDISCH Mask */ -#define MXC_F_GCR_BTLE_LDOCR_LDOTXENDLY_POS 12 /**< BTLE_LDOCR_LDOTXENDLY Position */ -#define MXC_F_GCR_BTLE_LDOCR_LDOTXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXENDLY_POS)) /**< BTLE_LDOCR_LDOTXENDLY Mask */ +#define MXC_F_GCR_BTLE_LDOCR_LDORXBYP_POS 10 /**< BTLE_LDOCR_LDORXBYP Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDORXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXBYP_POS)) /**< BTLE_LDOCR_LDORXBYP Mask */ + +#define MXC_F_GCR_BTLE_LDOCR_LDORXDISCH_POS 11 /**< BTLE_LDOCR_LDORXDISCH Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDORXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXDISCH_POS)) /**< BTLE_LDOCR_LDORXDISCH Mask */ -#define MXC_F_GCR_BTLE_LDOCR_LDORXENDLY_POS 13 /**< BTLE_LDOCR_LDORXENDLY Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDORXENDLY_POS 12 /**< BTLE_LDOCR_LDORXENDLY Position */ #define MXC_F_GCR_BTLE_LDOCR_LDORXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXENDLY_POS)) /**< BTLE_LDOCR_LDORXENDLY Mask */ -#define MXC_F_GCR_BTLE_LDOCR_LDORXBYPENENDLY_POS 14 /**< BTLE_LDOCR_LDORXBYPENENDLY Position */ -#define MXC_F_GCR_BTLE_LDOCR_LDORXBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXBYPENENDLY_POS)) /**< BTLE_LDOCR_LDORXBYPENENDLY Mask */ +#define MXC_F_GCR_BTLE_LDOCR_LDOTXENDLY_POS 13 /**< BTLE_LDOCR_LDOTXENDLY Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDOTXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXENDLY_POS)) /**< BTLE_LDOCR_LDOTXENDLY Mask */ -#define MXC_F_GCR_BTLE_LDOCR_LDOTXBYPENENDLY_POS 15 /**< BTLE_LDOCR_LDOTXBYPENENDLY Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDOTXBYPENENDLY_POS 14 /**< BTLE_LDOCR_LDOTXBYPENENDLY Position */ #define MXC_F_GCR_BTLE_LDOCR_LDOTXBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXBYPENENDLY_POS)) /**< BTLE_LDOCR_LDOTXBYPENENDLY Mask */ +#define MXC_F_GCR_BTLE_LDOCR_LDORXBYPENENDLY_POS 15 /**< BTLE_LDOCR_LDORXBYPENENDLY Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDORXBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXBYPENENDLY_POS)) /**< BTLE_LDOCR_LDORXBYPENENDLY Mask */ + /**@} end of group GCR_BTLE_LDOCR_Register */ /** @@ -1022,12 +1022,12 @@ typedef struct { #define MXC_F_GCR_BTLE_LDODCR_BYPDLYCNT_POS 0 /**< BTLE_LDODCR_BYPDLYCNT Position */ #define MXC_F_GCR_BTLE_LDODCR_BYPDLYCNT ((uint32_t)(0xFFUL << MXC_F_GCR_BTLE_LDODCR_BYPDLYCNT_POS)) /**< BTLE_LDODCR_BYPDLYCNT Mask */ -#define MXC_F_GCR_BTLE_LDODCR_LDORXDLYCNT_POS 8 /**< BTLE_LDODCR_LDORXDLYCNT Position */ -#define MXC_F_GCR_BTLE_LDODCR_LDORXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLE_LDODCR_LDORXDLYCNT_POS)) /**< BTLE_LDODCR_LDORXDLYCNT Mask */ - -#define MXC_F_GCR_BTLE_LDODCR_LDOTXDLYCNT_POS 20 /**< BTLE_LDODCR_LDOTXDLYCNT Position */ +#define MXC_F_GCR_BTLE_LDODCR_LDOTXDLYCNT_POS 8 /**< BTLE_LDODCR_LDOTXDLYCNT Position */ #define MXC_F_GCR_BTLE_LDODCR_LDOTXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLE_LDODCR_LDOTXDLYCNT_POS)) /**< BTLE_LDODCR_LDOTXDLYCNT Mask */ +#define MXC_F_GCR_BTLE_LDODCR_LDORXDLYCNT_POS 20 /**< BTLE_LDODCR_LDORXDLYCNT Position */ +#define MXC_F_GCR_BTLE_LDODCR_LDORXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLE_LDODCR_LDORXDLYCNT_POS)) /**< BTLE_LDODCR_LDORXDLYCNT Mask */ + /**@} end of group GCR_BTLE_LDODCR_Register */ /** diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.svd b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.svd index ff0bf637..095e976e 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.svd +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.svd @@ -4099,8 +4099,8 @@ <addressOffset>0x74</addressOffset> <fields> <field> - <name>LDOTXEN</name> - <description>LDOTX Enable</description> + <name>LDORXEN</name> + <description>LDORX Enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <enumeratedValues> @@ -4117,8 +4117,8 @@ </enumeratedValues> </field> <field> - <name>LDOTXOPULLD</name> - <description>LDOTX PULL Disable</description> + <name>LDORXOPULLD</name> + <description>LDORX PULL Disable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <enumeratedValues> @@ -4135,24 +4135,24 @@ </enumeratedValues> </field> <field> - <name>LDOTXVSEL</name> - <description>LDOTX Voltage Setting</description> + <name>LDORXVSEL</name> + <description>LDORX Voltage Setting</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> <enumeratedValues> - <enumeratedValue> - <name>0_7</name> - <description>0.7V</description> - <value>0</value> - </enumeratedValue> <enumeratedValue> <name>0_85</name> <description>0.85V</description> - <value>1</value> + <value>0</value> </enumeratedValue> <enumeratedValue> <name>0_9</name> <description>0.9V</description> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>1_0</name> + <description>1.0V</description> <value>2</value> </enumeratedValue> <enumeratedValue> @@ -4163,8 +4163,8 @@ </enumeratedValues> </field> <field> - <name>LDORXEN</name> - <description>LDORX Enable</description> + <name>LDOTXEN</name> + <description>LDOTX Enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <enumeratedValues> @@ -4181,8 +4181,8 @@ </enumeratedValues> </field> <field> - <name>LDORXPULLD</name> - <description>LDORX Pulldown</description> + <name>LDOTXPULLD</name> + <description>LDOTX Pulldown</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <enumeratedValues> @@ -4199,24 +4199,24 @@ </enumeratedValues> </field> <field> - <name>LDORXVSEL</name> - <description>LDORX Output Voltage Setting</description> + <name>LDOTXVSEL</name> + <description>LDOTX Output Voltage Setting</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> <enumeratedValues> - <enumeratedValue> - <name>0_7</name> - <description>0.7V</description> - <value>0</value> - </enumeratedValue> <enumeratedValue> <name>0_85</name> <description>0.85V</description> - <value>1</value> + <value>0</value> </enumeratedValue> <enumeratedValue> <name>0_9</name> <description>0.9V</description> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>1_0</name> + <description>1.0V</description> <value>2</value> </enumeratedValue> <enumeratedValue> @@ -4227,8 +4227,8 @@ </enumeratedValues> </field> <field> - <name>LDORXBYP</name> - <description>LDORX Bypass Enable</description> + <name>LDOTXBYP</name> + <description>LDOTX Bypass Enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <enumeratedValues> @@ -4245,8 +4245,8 @@ </enumeratedValues> </field> <field> - <name>LDORXDISCH</name> - <description>LDORX Discharge</description> + <name>LDOTXDISCH</name> + <description>LDOTX Discharge</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <enumeratedValues> @@ -4263,8 +4263,8 @@ </enumeratedValues> </field> <field> - <name>LDOTXBYP</name> - <description>LDOTX Bypass Enable</description> + <name>LDORXBYP</name> + <description>LDORX Bypass Enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <enumeratedValues> @@ -4281,8 +4281,8 @@ </enumeratedValues> </field> <field> - <name>LDOTXDISCH</name> - <description>LDOTX Discharge</description> + <name>LDORXDISCH</name> + <description>LDORX Discharge</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <enumeratedValues> @@ -4299,8 +4299,8 @@ </enumeratedValues> </field> <field> - <name>LDOTXENDLY</name> - <description>LDOTX Enable Delay</description> + <name>LDORXENDLY</name> + <description>LDORX Enable Delay</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <enumeratedValues> @@ -4317,8 +4317,8 @@ </enumeratedValues> </field> <field> - <name>LDORXENDLY</name> - <description>LDORX Enable Delay</description> + <name>LDOTXENDLY</name> + <description>LDOTX Enable Delay</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> <enumeratedValues> @@ -4335,14 +4335,14 @@ </enumeratedValues> </field> <field> - <name>LDORXBYPENENDLY</name> - <description>LDOTX Bypass Enable Delay</description> + <name>LDOTXBYPENENDLY</name> + <description>LDORX Bypass Enable Delay</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDOTXBYPENENDLY</name> - <description>LDORX Bypass Enable Delay</description> + <name>LDORXBYPENENDLY</name> + <description>LDOTX Bypass Enable Delay</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> @@ -4360,14 +4360,14 @@ <bitWidth>8</bitWidth> </field> <field> - <name>LDORXDLYCNT</name> - <description>LDORX Delay Count. Count delay base on PCLK/128.</description> + <name>LDOTXDLYCNT</name> + <description>LDOTX Delay Count. Count delay base on PCLK/128.</description> <bitOffset>8</bitOffset> <bitWidth>9</bitWidth> </field> <field> - <name>LDOTXDLYCNT</name> - <description>LDOTX Delay Count. Count delay base on PCLK/128.</description> + <name>LDORXDLYCNT</name> + <description>LDORX Delay Count. Count delay base on PCLK/128.</description> <bitOffset>20</bitOffset> <bitWidth>9</bitWidth> </field> @@ -13121,7 +13121,8 @@ <fields> <field> <name>MAGIC</name> - <description>Magic Word Validation. This bit is set by the system initialization block following power-up.</description> + <description>Magic Word Validation. This bit is set by the system initialization block + following power-up.</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> @@ -13141,7 +13142,8 @@ </field> <field> <name>CRCERR</name> - <description>CRC Error Status. This bit is set by the system initialization block following power-up.</description> + <description>CRC Error Status. This bit is set by the system initialization block + following power-up.</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> @@ -13154,7 +13156,8 @@ </enumeratedValue> <enumeratedValue> <name>error</name> - <description>A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register.</description> + <description>A CRC error occurred while reading the OTP. The address of the failure + location in the OTP memory is stored in the ERRADDR register.</description> <value>1</value> </enumeratedValue> </enumeratedValues> @@ -13163,7 +13166,8 @@ </register> <register> <name>ERRADDR</name> - <description>Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1).</description> + <description>Read-only field set by the SIB block if a CRC error occurs during the read of + the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1).</description> <addressOffset>0x04</addressOffset> <access>read-only</access> <fields> @@ -13174,6 +13178,36 @@ </field> </fields> </register> + <register> + <name>BTLE_LDO_TRIM_TX</name> + <description>BTLE LDO TX Trim register.</description> + <addressOffset>0x54</addressOffset> + <access>read-write</access> + <fields> + <field> + <name>TX</name> + <description>TX LDO trim value.</description> + <bitOffset>0</bitOffset> + <bitWidth>5</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> + <name>BTLE_LDO_TRIM_RX</name> + <description>BTLE LDO RX Trim register.</description> + <addressOffset>0x5C</addressOffset> + <access>read-write</access> + <fields> + <field> + <name>RX</name> + <description>RX LDO trim value.</description> + <bitOffset>0</bitOffset> + <bitWidth>5</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> <register> <name>FSTAT</name> <description>funcstat register.</description> diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/sir_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/sir_regs.h index b9749da3..70db2add 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/sir_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/sir_regs.h @@ -76,7 +76,11 @@ extern "C" { typedef struct { __I uint32_t sistat; /**< <tt>\b 0x00:</tt> SIR SISTAT Register */ __I uint32_t erraddr; /**< <tt>\b 0x04:</tt> SIR ERRADDR Register */ - __R uint32_t rsv_0x8_0xff[62]; + __R uint32_t rsv_0x8_0x53[19]; + __IO uint32_t btle_ldo_trim_tx; /**< <tt>\b 0x54:</tt> SIR BTLE_LDO_TRIM_TX Register */ + __R uint32_t rsv_0x58; + __IO uint32_t btle_ldo_trim_rx; /**< <tt>\b 0x5C:</tt> SIR BTLE_LDO_TRIM_RX Register */ + __R uint32_t rsv_0x60_0xff[40]; __I uint32_t fstat; /**< <tt>\b 0x100:</tt> SIR FSTAT Register */ __I uint32_t sfstat; /**< <tt>\b 0x104:</tt> SIR SFSTAT Register */ } mxc_sir_regs_t; @@ -90,6 +94,8 @@ typedef struct { */ #define MXC_R_SIR_SISTAT ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: <tt> 0x0000</tt> */ #define MXC_R_SIR_ERRADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: <tt> 0x0004</tt> */ +#define MXC_R_SIR_BTLE_LDO_TRIM_TX ((uint32_t)0x00000054UL) /**< Offset from SIR Base Address: <tt> 0x0054</tt> */ +#define MXC_R_SIR_BTLE_LDO_TRIM_RX ((uint32_t)0x0000005CUL) /**< Offset from SIR Base Address: <tt> 0x005C</tt> */ #define MXC_R_SIR_FSTAT ((uint32_t)0x00000100UL) /**< Offset from SIR Base Address: <tt> 0x0100</tt> */ #define MXC_R_SIR_SFSTAT ((uint32_t)0x00000104UL) /**< Offset from SIR Base Address: <tt> 0x0104</tt> */ /**@} end of group sir_registers */ @@ -121,6 +127,28 @@ typedef struct { /**@} end of group SIR_ERRADDR_Register */ +/** + * @ingroup sir_registers + * @defgroup SIR_BTLE_LDO_TRIM_TX SIR_BTLE_LDO_TRIM_TX + * @brief BTLE LDO TX Trim register. + * @{ + */ +#define MXC_F_SIR_BTLE_LDO_TRIM_TX_TX_POS 0 /**< BTLE_LDO_TRIM_TX_TX Position */ +#define MXC_F_SIR_BTLE_LDO_TRIM_TX_TX ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_TX_TX_POS)) /**< BTLE_LDO_TRIM_TX_TX Mask */ + +/**@} end of group SIR_BTLE_LDO_TRIM_TX_Register */ + +/** + * @ingroup sir_registers + * @defgroup SIR_BTLE_LDO_TRIM_RX SIR_BTLE_LDO_TRIM_RX + * @brief BTLE LDO RX Trim register. + * @{ + */ +#define MXC_F_SIR_BTLE_LDO_TRIM_RX_RX_POS 0 /**< BTLE_LDO_TRIM_RX_RX Position */ +#define MXC_F_SIR_BTLE_LDO_TRIM_RX_RX ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_RX_RX_POS)) /**< BTLE_LDO_TRIM_RX_RX Mask */ + +/**@} end of group SIR_BTLE_LDO_TRIM_RX_Register */ + /** * @ingroup sir_registers * @defgroup SIR_FSTAT SIR_FSTAT diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/gcr_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/gcr_regs.h index 5a329868..ff049258 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/gcr_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/gcr_regs.h @@ -681,75 +681,63 @@ typedef struct { * @brief BTLE LDO Control Register * @{ */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXEN_POS 0 /**< BTLELDOCTRL_LDOTXEN Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXEN_POS)) /**< BTLELDOCTRL_LDOTXEN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBEN_POS 0 /**< BTLELDOCTRL_LDOBBEN Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBEN_POS)) /**< BTLELDOCTRL_LDOBBEN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD_POS 1 /**< BTLELDOCTRL_LDOTXPULLD Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD_POS)) /**< BTLELDOCTRL_LDOTXPULLD Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBPULLD_POS 1 /**< BTLELDOCTRL_LDOBBPULLD Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBPULLD_POS)) /**< BTLELDOCTRL_LDOBBPULLD Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS 2 /**< BTLELDOCTRL_LDOTXVSEL Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS)) /**< BTLELDOCTRL_LDOTXVSEL Mask */ -#define MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_7 ((uint32_t)0x0UL) /**< BTLELDOCTRL_LDOTXVSEL_0_7 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDOTXVSEL_0_7 (MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_7 << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS) /**< BTLELDOCTRL_LDOTXVSEL_0_7 Setting */ -#define MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_85 ((uint32_t)0x1UL) /**< BTLELDOCTRL_LDOTXVSEL_0_85 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDOTXVSEL_0_85 (MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_85 << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS) /**< BTLELDOCTRL_LDOTXVSEL_0_85 Setting */ -#define MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_9 ((uint32_t)0x2UL) /**< BTLELDOCTRL_LDOTXVSEL_0_9 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDOTXVSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS) /**< BTLELDOCTRL_LDOTXVSEL_0_9 Setting */ -#define MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_1_1 ((uint32_t)0x3UL) /**< BTLELDOCTRL_LDOTXVSEL_1_1 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDOTXVSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS) /**< BTLELDOCTRL_LDOTXVSEL_1_1 Setting */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS 2 /**< BTLELDOCTRL_LDOBBVSEL Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS)) /**< BTLELDOCTRL_LDOBBVSEL Mask */ +#define MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_0_85 ((uint32_t)0x0UL) /**< BTLELDOCTRL_LDOBBVSEL_0_85 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_0_85 (MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_0_85 << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS) /**< BTLELDOCTRL_LDOBBVSEL_0_85 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_0_9 ((uint32_t)0x1UL) /**< BTLELDOCTRL_LDOBBVSEL_0_9 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS) /**< BTLELDOCTRL_LDOBBVSEL_0_9 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_1_0 ((uint32_t)0x2UL) /**< BTLELDOCTRL_LDOBBVSEL_1_0 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_1_0 (MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_1_0 << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS) /**< BTLELDOCTRL_LDOBBVSEL_1_0 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_1_1 ((uint32_t)0x3UL) /**< BTLELDOCTRL_LDOBBVSEL_1_1 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS) /**< BTLELDOCTRL_LDOBBVSEL_1_1 Setting */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL0_POS 2 /**< BTLELDOCTRL_LDOTXVSEL0 Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL0 ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL0_POS)) /**< BTLELDOCTRL_LDOTXVSEL0 Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFEN_POS 4 /**< BTLELDOCTRL_LDORFEN Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFEN_POS)) /**< BTLELDOCTRL_LDORFEN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL1_POS 3 /**< BTLELDOCTRL_LDOTXVSEL1 Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL1 ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL1_POS)) /**< BTLELDOCTRL_LDOTXVSEL1 Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFPULLD_POS 5 /**< BTLELDOCTRL_LDORFPULLD Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFPULLD_POS)) /**< BTLELDOCTRL_LDORFPULLD Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXEN_POS 4 /**< BTLELDOCTRL_LDORXEN Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXEN_POS)) /**< BTLELDOCTRL_LDORXEN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS 6 /**< BTLELDOCTRL_LDORFVSEL Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS)) /**< BTLELDOCTRL_LDORFVSEL Mask */ +#define MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_0_85 ((uint32_t)0x0UL) /**< BTLELDOCTRL_LDORFVSEL_0_85 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_0_85 (MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_0_85 << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS) /**< BTLELDOCTRL_LDORFVSEL_0_85 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_0_9 ((uint32_t)0x1UL) /**< BTLELDOCTRL_LDORFVSEL_0_9 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS) /**< BTLELDOCTRL_LDORFVSEL_0_9 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_1_0 ((uint32_t)0x2UL) /**< BTLELDOCTRL_LDORFVSEL_1_0 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_1_0 (MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_1_0 << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS) /**< BTLELDOCTRL_LDORFVSEL_1_0 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_1_1 ((uint32_t)0x3UL) /**< BTLELDOCTRL_LDORFVSEL_1_1 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS) /**< BTLELDOCTRL_LDORFVSEL_1_1 Setting */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXPULLD_POS 5 /**< BTLELDOCTRL_LDORXPULLD Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXPULLD_POS)) /**< BTLELDOCTRL_LDORXPULLD Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFBYP_POS 8 /**< BTLELDOCTRL_LDORFBYP Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFBYP_POS)) /**< BTLELDOCTRL_LDORFBYP Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS 6 /**< BTLELDOCTRL_LDORXVSEL Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS)) /**< BTLELDOCTRL_LDORXVSEL Mask */ -#define MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_7 ((uint32_t)0x0UL) /**< BTLELDOCTRL_LDORXVSEL_0_7 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDORXVSEL_0_7 (MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_7 << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS) /**< BTLELDOCTRL_LDORXVSEL_0_7 Setting */ -#define MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_85 ((uint32_t)0x1UL) /**< BTLELDOCTRL_LDORXVSEL_0_85 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDORXVSEL_0_85 (MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_85 << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS) /**< BTLELDOCTRL_LDORXVSEL_0_85 Setting */ -#define MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_9 ((uint32_t)0x2UL) /**< BTLELDOCTRL_LDORXVSEL_0_9 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDORXVSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS) /**< BTLELDOCTRL_LDORXVSEL_0_9 Setting */ -#define MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_1_1 ((uint32_t)0x3UL) /**< BTLELDOCTRL_LDORXVSEL_1_1 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDORXVSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS) /**< BTLELDOCTRL_LDORXVSEL_1_1 Setting */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFDISCH_POS 9 /**< BTLELDOCTRL_LDORFDISCH Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFDISCH_POS)) /**< BTLELDOCTRL_LDORFDISCH Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL0_POS 6 /**< BTLELDOCTRL_LDORXVSEL0 Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL0 ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL0_POS)) /**< BTLELDOCTRL_LDORXVSEL0 Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBBYP_POS 10 /**< BTLELDOCTRL_LDOBBBYP Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBBYP_POS)) /**< BTLELDOCTRL_LDOBBBYP Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL1_POS 7 /**< BTLELDOCTRL_LDORXVSEL1 Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL1 ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL1_POS)) /**< BTLELDOCTRL_LDORXVSEL1 Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBDISCH_POS 11 /**< BTLELDOCTRL_LDOBBDISCH Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBDISCH_POS)) /**< BTLELDOCTRL_LDOBBDISCH Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXBYP_POS 8 /**< BTLELDOCTRL_LDORXBYP Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXBYP_POS)) /**< BTLELDOCTRL_LDORXBYP Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBENDLY_POS 12 /**< BTLELDOCTRL_LDOBBENDLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBENDLY_POS)) /**< BTLELDOCTRL_LDOBBENDLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXDISCH_POS 9 /**< BTLELDOCTRL_LDORXDISCH Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXDISCH_POS)) /**< BTLELDOCTRL_LDORXDISCH Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFENDLY_POS 13 /**< BTLELDOCTRL_LDORFENDLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFENDLY_POS)) /**< BTLELDOCTRL_LDORFENDLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXBYP_POS 10 /**< BTLELDOCTRL_LDOTXBYP Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXBYP_POS)) /**< BTLELDOCTRL_LDOTXBYP Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFBYPENENDLY_POS 14 /**< BTLELDOCTRL_LDORFBYPENENDLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFBYPENENDLY_POS)) /**< BTLELDOCTRL_LDORFBYPENENDLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXDISCH_POS 11 /**< BTLELDOCTRL_LDOTXDISCH Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXDISCH_POS)) /**< BTLELDOCTRL_LDOTXDISCH Mask */ - -#define MXC_F_GCR_BTLELDOCTRL_LDOTXENDLY_POS 12 /**< BTLELDOCTRL_LDOTXENDLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXENDLY_POS)) /**< BTLELDOCTRL_LDOTXENDLY Mask */ - -#define MXC_F_GCR_BTLELDOCTRL_LDORXENDLY_POS 13 /**< BTLELDOCTRL_LDORXENDLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXENDLY_POS)) /**< BTLELDOCTRL_LDORXENDLY Mask */ - -#define MXC_F_GCR_BTLELDOCTRL_LDORXBYPENENDLY_POS 14 /**< BTLELDOCTRL_LDORXBYPENENDLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXBYPENENDLY_POS)) /**< BTLELDOCTRL_LDORXBYPENENDLY Mask */ - -#define MXC_F_GCR_BTLELDOCTRL_LDOTXBYPENENDLY_POS 15 /**< BTLELDOCTRL_LDOTXBYPENENDLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXBYPENENDLY_POS)) /**< BTLELDOCTRL_LDOTXBYPENENDLY Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBBYPENENDLY_POS 15 /**< BTLELDOCTRL_LDOBBBYPENENDLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBBYPENENDLY_POS)) /**< BTLELDOCTRL_LDOBBBYPENENDLY Mask */ /**@} end of group GCR_BTLELDOCTRL_Register */ @@ -762,11 +750,11 @@ typedef struct { #define MXC_F_GCR_BTLELDODLY_BYPDLYCNT_POS 0 /**< BTLELDODLY_BYPDLYCNT Position */ #define MXC_F_GCR_BTLELDODLY_BYPDLYCNT ((uint32_t)(0xFFUL << MXC_F_GCR_BTLELDODLY_BYPDLYCNT_POS)) /**< BTLELDODLY_BYPDLYCNT Mask */ -#define MXC_F_GCR_BTLELDODLY_LDORXDLYCNT_POS 8 /**< BTLELDODLY_LDORXDLYCNT Position */ -#define MXC_F_GCR_BTLELDODLY_LDORXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDORXDLYCNT_POS)) /**< BTLELDODLY_LDORXDLYCNT Mask */ +#define MXC_F_GCR_BTLELDODLY_LDOBBDLYCNT_POS 8 /**< BTLELDODLY_LDOBBDLYCNT Position */ +#define MXC_F_GCR_BTLELDODLY_LDOBBDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDOBBDLYCNT_POS)) /**< BTLELDODLY_LDOBBDLYCNT Mask */ -#define MXC_F_GCR_BTLELDODLY_LDOTXDLYCNT_POS 20 /**< BTLELDODLY_LDOTXDLYCNT Position */ -#define MXC_F_GCR_BTLELDODLY_LDOTXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDOTXDLYCNT_POS)) /**< BTLELDODLY_LDOTXDLYCNT Mask */ +#define MXC_F_GCR_BTLELDODLY_LDORFDLYCNT_POS 20 /**< BTLELDODLY_LDORFDLYCNT Position */ +#define MXC_F_GCR_BTLELDODLY_LDORFDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDORFDLYCNT_POS)) /**< BTLELDODLY_LDORFDLYCNT Mask */ /**@} end of group GCR_BTLELDODLY_Register */ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/max32680.svd b/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/max32680.svd index af2ae925..9ee59137 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/max32680.svd +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/max32680.svd @@ -3794,36 +3794,36 @@ <addressOffset>0x74</addressOffset> <fields> <field> - <name>LDOTXEN</name> - <description>LDOTX Enable.</description> + <name>LDOBBEN</name> + <description>LDOBB Enable.</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDOTXPULLD</name> - <description>LDOTX Pull Down.</description> + <name>LDOBBPULLD</name> + <description>LDOBB Pull Down.</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDOTXVSEL</name> - <description>LDOTX Voltage Setting.</description> + <name>LDOBBVSEL</name> + <description>LDOBB Voltage Setting.</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> <enumeratedValues> - <enumeratedValue> - <name>0_7</name> - <description>0.7V</description> - <value>0</value> - </enumeratedValue> <enumeratedValue> <name>0_85</name> <description>0.85V</description> - <value>1</value> + <value>0</value> </enumeratedValue> <enumeratedValue> <name>0_9</name> <description>0.9V</description> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>1_0</name> + <description>1.0V</description> <value>2</value> </enumeratedValue> <enumeratedValue> @@ -3834,36 +3834,36 @@ </enumeratedValues> </field> <field> - <name>LDORXEN</name> - <description>LDORX Enable.</description> + <name>LDORFEN</name> + <description>LDORF Enable.</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDORXPULLD</name> - <description>LDOrX Pull Down.</description> + <name>LDORFPULLD</name> + <description>LDORF Pull Down.</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDORXVSEL</name> - <description>LDORX Voltage Setting.</description> + <name>LDORFVSEL</name> + <description>LDORF Voltage Setting.</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> <enumeratedValues> - <enumeratedValue> - <name>0_7</name> - <description>0.7V</description> - <value>0</value> - </enumeratedValue> <enumeratedValue> <name>0_85</name> <description>0.85V</description> - <value>1</value> + <value>0</value> </enumeratedValue> <enumeratedValue> <name>0_9</name> <description>0.9V</description> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>1_0</name> + <description>1.0V</description> <value>2</value> </enumeratedValue> <enumeratedValue> @@ -3874,50 +3874,50 @@ </enumeratedValues> </field> <field> - <name>LDORXBYP</name> - <description>LDORX Bypass Enable.</description> + <name>LDORFBYP</name> + <description>LDORF Bypass Enable.</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDORXDISCH</name> - <description>LDORX Discharge.</description> + <name>LDORFDISCH</name> + <description>LDORF Discharge.</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDOTXBYP</name> - <description>LDOTX Bypass Enable.</description> + <name>LDOBBBYP</name> + <description>LDOBB Bypass Enable.</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDOTXDISCH</name> - <description>LDOTX Discharge.</description> + <name>LDOBBDISCH</name> + <description>LDOBB Discharge.</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDOTXENDLY</name> - <description>LDOTX Enable Delay.</description> + <name>LDOBBENDLY</name> + <description>LDOBB Enable Delay.</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDORXENDLY</name> - <description>LDORX Enable Delay.</description> + <name>LDORFENDLY</name> + <description>LDORF Enable Delay.</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDORXBYPENENDLY</name> - <description>LDORX Bypass Enable Delay.</description> + <name>LDORFBYPENENDLY</name> + <description>LDORF Bypass Enable Delay.</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDOTXBYPENENDLY</name> - <description>LDOTX Bypass Enable Delay.</description> + <name>LDOBBBYPENENDLY</name> + <description>LDOBB Bypass Enable Delay.</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> @@ -3935,14 +3935,14 @@ <bitWidth>8</bitWidth> </field> <field> - <name>LDORXDLYCNT</name> - <description>LDORX Delay Count.</description> + <name>LDOBBDLYCNT</name> + <description>LDOBB Delay Count.</description> <bitOffset>8</bitOffset> <bitWidth>9</bitWidth> </field> <field> - <name>LDOTXDLYCNT</name> - <description>LDOTX Delay Count.</description> + <name>LDORFDLYCNT</name> + <description>LDOBB Delay Count.</description> <bitOffset>20</bitOffset> <bitWidth>9</bitWidth> </field> @@ -9121,16 +9121,16 @@ <access>read-write</access> <fields> <field> - <name>TX</name> - <description>TX LDO trim value.</description> - <bitOffset>0</bitOffset> + <name>RF</name> + <description>RF LDO trim value.</description> + <bitOffset>16</bitOffset> <bitWidth>5</bitWidth> <access>read-write</access> </field> <field> - <name>RX</name> - <description>RX LDO trim value.</description> - <bitOffset>8</bitOffset> + <name>BB</name> + <description>BB LDO trim value.</description> + <bitOffset>24</bitOffset> <bitWidth>5</bitWidth> <access>read-write</access> </field> diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/sir_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/sir_regs.h index 5f9e6734..4f8c04c2 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/sir_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/sir_regs.h @@ -130,11 +130,11 @@ typedef struct { * @brief BTLE LDO Trim register. * @{ */ -#define MXC_F_SIR_BTLE_LDO_TRIM_TX_POS 0 /**< BTLE_LDO_TRIM_TX Position */ -#define MXC_F_SIR_BTLE_LDO_TRIM_TX ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_TX_POS)) /**< BTLE_LDO_TRIM_TX Mask */ +#define MXC_F_SIR_BTLE_LDO_TRIM_RF_POS 16 /**< BTLE_LDO_TRIM_RF Position */ +#define MXC_F_SIR_BTLE_LDO_TRIM_RF ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_RF_POS)) /**< BTLE_LDO_TRIM_RF Mask */ -#define MXC_F_SIR_BTLE_LDO_TRIM_RX_POS 8 /**< BTLE_LDO_TRIM_RX Position */ -#define MXC_F_SIR_BTLE_LDO_TRIM_RX ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_RX_POS)) /**< BTLE_LDO_TRIM_RX Mask */ +#define MXC_F_SIR_BTLE_LDO_TRIM_BB_POS 24 /**< BTLE_LDO_TRIM_BB Position */ +#define MXC_F_SIR_BTLE_LDO_TRIM_BB ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_BB_POS)) /**< BTLE_LDO_TRIM_BB Mask */ /**@} end of group SIR_BTLE_LDO_TRIM_Register */ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/gcr_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/gcr_regs.h index 62aed4af..1ab61adf 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/gcr_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/gcr_regs.h @@ -878,47 +878,63 @@ typedef struct { * @brief BTLE LDO Control Register * @{ */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXEN_POS 0 /**< BTLELDOCTRL_LDOTXEN Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXEN_POS)) /**< BTLELDOCTRL_LDOTXEN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBEN_POS 0 /**< BTLELDOCTRL_LDOBBEN Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBEN_POS)) /**< BTLELDOCTRL_LDOBBEN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD_POS 1 /**< BTLELDOCTRL_LDOTXPULLD Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD_POS)) /**< BTLELDOCTRL_LDOTXPULLD Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBPULLD_POS 1 /**< BTLELDOCTRL_LDOBBPULLD Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBPULLD_POS)) /**< BTLELDOCTRL_LDOBBPULLD Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS 2 /**< BTLELDOCTRL_LDOTXVSEL Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS)) /**< BTLELDOCTRL_LDOTXVSEL Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS 2 /**< BTLELDOCTRL_LDOBBVSEL Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS)) /**< BTLELDOCTRL_LDOBBVSEL Mask */ +#define MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_0_85 ((uint32_t)0x0UL) /**< BTLELDOCTRL_LDOBBVSEL_0_85 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_0_85 (MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_0_85 << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS) /**< BTLELDOCTRL_LDOBBVSEL_0_85 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_0_9 ((uint32_t)0x1UL) /**< BTLELDOCTRL_LDOBBVSEL_0_9 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS) /**< BTLELDOCTRL_LDOBBVSEL_0_9 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_1_0 ((uint32_t)0x2UL) /**< BTLELDOCTRL_LDOBBVSEL_1_0 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_1_0 (MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_1_0 << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS) /**< BTLELDOCTRL_LDOBBVSEL_1_0 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_1_1 ((uint32_t)0x3UL) /**< BTLELDOCTRL_LDOBBVSEL_1_1 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS) /**< BTLELDOCTRL_LDOBBVSEL_1_1 Setting */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXEN_POS 4 /**< BTLELDOCTRL_LDORXEN Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXEN_POS)) /**< BTLELDOCTRL_LDORXEN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFEN_POS 4 /**< BTLELDOCTRL_LDORFEN Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFEN_POS)) /**< BTLELDOCTRL_LDORFEN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXPULLD_POS 5 /**< BTLELDOCTRL_LDORXPULLD Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXPULLD_POS)) /**< BTLELDOCTRL_LDORXPULLD Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFPULLD_POS 5 /**< BTLELDOCTRL_LDORFPULLD Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFPULLD_POS)) /**< BTLELDOCTRL_LDORFPULLD Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS 6 /**< BTLELDOCTRL_LDORXVSEL Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS)) /**< BTLELDOCTRL_LDORXVSEL Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS 6 /**< BTLELDOCTRL_LDORFVSEL Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS)) /**< BTLELDOCTRL_LDORFVSEL Mask */ +#define MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_0_85 ((uint32_t)0x0UL) /**< BTLELDOCTRL_LDORFVSEL_0_85 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_0_85 (MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_0_85 << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS) /**< BTLELDOCTRL_LDORFVSEL_0_85 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_0_9 ((uint32_t)0x1UL) /**< BTLELDOCTRL_LDORFVSEL_0_9 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS) /**< BTLELDOCTRL_LDORFVSEL_0_9 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_1_0 ((uint32_t)0x2UL) /**< BTLELDOCTRL_LDORFVSEL_1_0 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_1_0 (MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_1_0 << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS) /**< BTLELDOCTRL_LDORFVSEL_1_0 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_1_1 ((uint32_t)0x3UL) /**< BTLELDOCTRL_LDORFVSEL_1_1 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS) /**< BTLELDOCTRL_LDORFVSEL_1_1 Setting */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXBYP_POS 8 /**< BTLELDOCTRL_LDORXBYP Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXBYP_POS)) /**< BTLELDOCTRL_LDORXBYP Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFBYP_POS 8 /**< BTLELDOCTRL_LDORFBYP Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFBYP_POS)) /**< BTLELDOCTRL_LDORFBYP Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXDISCH_POS 9 /**< BTLELDOCTRL_LDORXDISCH Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXDISCH_POS)) /**< BTLELDOCTRL_LDORXDISCH Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFDISCH_POS 9 /**< BTLELDOCTRL_LDORFDISCH Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFDISCH_POS)) /**< BTLELDOCTRL_LDORFDISCH Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXBYP_POS 10 /**< BTLELDOCTRL_LDOTXBYP Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXBYP_POS)) /**< BTLELDOCTRL_LDOTXBYP Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBBYP_POS 10 /**< BTLELDOCTRL_LDOBBBYP Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBBYP_POS)) /**< BTLELDOCTRL_LDOBBBYP Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXDISCH_POS 11 /**< BTLELDOCTRL_LDOTXDISCH Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXDISCH_POS)) /**< BTLELDOCTRL_LDOTXDISCH Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBDISCH_POS 11 /**< BTLELDOCTRL_LDOBBDISCH Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBDISCH_POS)) /**< BTLELDOCTRL_LDOBBDISCH Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXENDLY_POS 12 /**< BTLELDOCTRL_LDOTXENDLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXENDLY_POS)) /**< BTLELDOCTRL_LDOTXENDLY Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBENDLY_POS 12 /**< BTLELDOCTRL_LDOBBENDLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBENDLY_POS)) /**< BTLELDOCTRL_LDOBBENDLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXENDLY_POS 13 /**< BTLELDOCTRL_LDORXENDLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXENDLY_POS)) /**< BTLELDOCTRL_LDORXENDLY Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFENDLY_POS 13 /**< BTLELDOCTRL_LDORFENDLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFENDLY_POS)) /**< BTLELDOCTRL_LDORFENDLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXBYPENENDLY_POS 14 /**< BTLELDOCTRL_LDORXBYPENENDLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXBYPENENDLY_POS)) /**< BTLELDOCTRL_LDORXBYPENENDLY Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFBYPENENDLY_POS 14 /**< BTLELDOCTRL_LDORFBYPENENDLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFBYPENENDLY_POS)) /**< BTLELDOCTRL_LDORFBYPENENDLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXBYPENENDLY_POS 15 /**< BTLELDOCTRL_LDOTXBYPENENDLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXBYPENENDLY_POS)) /**< BTLELDOCTRL_LDOTXBYPENENDLY Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBBYPENENDLY_POS 15 /**< BTLELDOCTRL_LDOBBBYPENENDLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBBYPENENDLY_POS)) /**< BTLELDOCTRL_LDOBBBYPENENDLY Mask */ /**@} end of group GCR_BTLELDOCTRL_Register */ @@ -931,11 +947,11 @@ typedef struct { #define MXC_F_GCR_BTLELDODLY_BYPDLYCNT_POS 0 /**< BTLELDODLY_BYPDLYCNT Position */ #define MXC_F_GCR_BTLELDODLY_BYPDLYCNT ((uint32_t)(0xFFUL << MXC_F_GCR_BTLELDODLY_BYPDLYCNT_POS)) /**< BTLELDODLY_BYPDLYCNT Mask */ -#define MXC_F_GCR_BTLELDODLY_LDOTXDLYCNT_POS 8 /**< BTLELDODLY_LDOTXDLYCNT Position */ -#define MXC_F_GCR_BTLELDODLY_LDOTXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDOTXDLYCNT_POS)) /**< BTLELDODLY_LDOTXDLYCNT Mask */ +#define MXC_F_GCR_BTLELDODLY_LDORFDLYCNT_POS 8 /**< BTLELDODLY_LDORFDLYCNT Position */ +#define MXC_F_GCR_BTLELDODLY_LDORFDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDORFDLYCNT_POS)) /**< BTLELDODLY_LDORFDLYCNT Mask */ -#define MXC_F_GCR_BTLELDODLY_LDORXDLYCNT_POS 20 /**< BTLELDODLY_LDORXDLYCNT Position */ -#define MXC_F_GCR_BTLELDODLY_LDORXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDORXDLYCNT_POS)) /**< BTLELDODLY_LDORXDLYCNT Mask */ +#define MXC_F_GCR_BTLELDODLY_LDOBBDLYCNT_POS 20 /**< BTLELDODLY_LDOBBDLYCNT Position */ +#define MXC_F_GCR_BTLELDODLY_LDOBBDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDOBBDLYCNT_POS)) /**< BTLELDODLY_LDOBBDLYCNT Mask */ /**@} end of group GCR_BTLELDODLY_Register */ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/max32690.svd b/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/max32690.svd index 0846a01a..56af430f 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/max32690.svd +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/max32690.svd @@ -7334,86 +7334,130 @@ memory. <addressOffset>0x74</addressOffset> <fields> <field> - <name>LDOTXEN</name> - <description>LDOTX Enable.</description> + <name>LDOBBEN</name> + <description>LDOBB Enable.</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDOTXPULLD</name> - <description>LDOTX Pull Down.</description> + <name>LDOBBPULLD</name> + <description>LDOBB Pull Down.</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDOTXVSEL</name> - <description>LDOTX Voltage Setting.</description> + <name>LDOBBVSEL</name> + <description>LDOBB Voltage Setting.</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> + <enumeratedValues> + <enumeratedValue> + <name>0_85</name> + <description>0.85V</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>0_9</name> + <description>0.9V</description> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>1_0</name> + <description>1.0V</description> + <value>2</value> + </enumeratedValue> + <enumeratedValue> + <name>1_1</name> + <description>1.1V</description> + <value>3</value> + </enumeratedValue> + </enumeratedValues> </field> <field> - <name>LDORXEN</name> - <description>LDORX Enable.</description> + <name>LDORFEN</name> + <description>LDORF Enable.</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDORXPULLD</name> - <description>LDOrX Pull Down.</description> + <name>LDORFPULLD</name> + <description>LDORF Pull Down.</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDORXVSEL</name> - <description>LDORX Voltage Setting.</description> + <name>LDORFVSEL</name> + <description>LDORF Voltage Setting.</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> + <enumeratedValues> + <enumeratedValue> + <name>0_85</name> + <description>0.85V</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>0_9</name> + <description>0.9V</description> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>1_0</name> + <description>1.0V</description> + <value>2</value> + </enumeratedValue> + <enumeratedValue> + <name>1_1</name> + <description>1.1V</description> + <value>3</value> + </enumeratedValue> + </enumeratedValues> </field> <field> - <name>LDORXBYP</name> - <description>LDORX Bypass Enable.</description> + <name>LDORFBYP</name> + <description>LDORF Bypass Enable.</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDORXDISCH</name> - <description>LDORX Discharge.</description> + <name>LDORFDISCH</name> + <description>LDORF Discharge.</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDOTXBYP</name> - <description>LDOTX Bypass Enable.</description> + <name>LDOBBBYP</name> + <description>LDOBB Bypass Enable.</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDOTXDISCH</name> - <description>LDOTX Discharge.</description> + <name>LDOBBDISCH</name> + <description>LDOBB Discharge.</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDOTXENDLY</name> - <description>LDOTX Enable Delay.</description> + <name>LDOBBENDLY</name> + <description>LDOBB Enable Delay.</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDORXENDLY</name> - <description>LDORX Enable Delay.</description> + <name>LDORFENDLY</name> + <description>LDORF Enable Delay.</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDORXBYPENENDLY</name> - <description>LDORX Bypass Enable Delay.</description> + <name>LDORFBYPENENDLY</name> + <description>LDORF Bypass Enable Delay.</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> - <name>LDOTXBYPENENDLY</name> - <description>LDOTX Bypass Enable Delay.</description> + <name>LDOBBBYPENENDLY</name> + <description>LDOBB Bypass Enable Delay.</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> @@ -7431,14 +7475,14 @@ memory. <bitWidth>8</bitWidth> </field> <field> - <name>LDOTXDLYCNT</name> - <description>LDOTX Delay Count.</description> + <name>LDORFDLYCNT</name> + <description>LDORF Delay Count.</description> <bitOffset>8</bitOffset> <bitWidth>9</bitWidth> </field> <field> - <name>LDORXDLYCNT</name> - <description>LDORX Delay Count.</description> + <name>LDOBBDLYCNT</name> + <description>LDOBB Delay Count.</description> <bitOffset>20</bitOffset> <bitWidth>9</bitWidth> </field> @@ -13438,7 +13482,8 @@ signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is se <fields> <field> <name>MAGIC</name> - <description>Magic Word Validation. This bit is set by the system initialization block following power-up.</description> + <description>Magic Word Validation. This bit is set by the system initialization block + following power-up.</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> @@ -13458,7 +13503,8 @@ signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is se </field> <field> <name>CRCERR</name> - <description>CRC Error Status. This bit is set by the system initialization block following power-up.</description> + <description>CRC Error Status. This bit is set by the system initialization block + following power-up.</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> @@ -13471,7 +13517,8 @@ signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is se </enumeratedValue> <enumeratedValue> <name>error</name> - <description>A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register.</description> + <description>A CRC error occurred while reading the OTP. The address of the failure + location in the OTP memory is stored in the ERRADDR register.</description> <value>1</value> </enumeratedValue> </enumeratedValues> @@ -13480,7 +13527,8 @@ signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is se </register> <register> <name>SIADDR</name> - <description>Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1).</description> + <description>Read-only field set by the SIB block if a CRC error occurs during the read of + the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1).</description> <addressOffset>0x04</addressOffset> <access>read-only</access> <fields> @@ -13498,15 +13546,15 @@ signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is se <access>read-write</access> <fields> <field> - <name>TX</name> - <description>TX LDO trim value.</description> + <name>RF</name> + <description>RF LDO trim value.</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> <access>read-write</access> </field> <field> - <name>RX</name> - <description>RX LDO trim value.</description> + <name>BB</name> + <description>BB LDO trim value.</description> <bitOffset>5</bitOffset> <bitWidth>5</bitWidth> <access>read-write</access> diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/sir_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/sir_regs.h index cb5b357b..d1b5f527 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/sir_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/sir_regs.h @@ -130,11 +130,11 @@ typedef struct { * @brief BTLE LDO Trim register. * @{ */ -#define MXC_F_SIR_BTLE_LDO_TRIM_TX_POS 0 /**< BTLE_LDO_TRIM_TX Position */ -#define MXC_F_SIR_BTLE_LDO_TRIM_TX ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_TX_POS)) /**< BTLE_LDO_TRIM_TX Mask */ +#define MXC_F_SIR_BTLE_LDO_TRIM_RF_POS 0 /**< BTLE_LDO_TRIM_RF Position */ +#define MXC_F_SIR_BTLE_LDO_TRIM_RF ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_RF_POS)) /**< BTLE_LDO_TRIM_RF Mask */ -#define MXC_F_SIR_BTLE_LDO_TRIM_RX_POS 5 /**< BTLE_LDO_TRIM_RX Position */ -#define MXC_F_SIR_BTLE_LDO_TRIM_RX ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_RX_POS)) /**< BTLE_LDO_TRIM_RX Mask */ +#define MXC_F_SIR_BTLE_LDO_TRIM_BB_POS 5 /**< BTLE_LDO_TRIM_BB Position */ +#define MXC_F_SIR_BTLE_LDO_TRIM_BB ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_BB_POS)) /**< BTLE_LDO_TRIM_BB Mask */ /**@} end of group SIR_BTLE_LDO_TRIM_Register */ diff --git a/MAX/Libraries/PeriphDrivers/Source/AFE/hart_uart.c b/MAX/Libraries/PeriphDrivers/Source/AFE/hart_uart.c index c3ab27eb..b167ab88 100644 --- a/MAX/Libraries/PeriphDrivers/Source/AFE/hart_uart.c +++ b/MAX/Libraries/PeriphDrivers/Source/AFE/hart_uart.c @@ -643,9 +643,9 @@ int hart_clock_enable(void) pPTG->intfl = 0x01; //enable ISO before enabling ERFO - MXC_GCR->btleldoctrl |= (MXC_F_GCR_BTLELDOCTRL_LDOTXEN | MXC_F_GCR_BTLELDOCTRL_LDORXEN | - MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL0 | MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL1 | - MXC_F_GCR_BTLELDOCTRL_LDORXVSEL0 | MXC_F_GCR_BTLELDOCTRL_LDORXVSEL1); + MXC_GCR->btleldoctrl |= + (MXC_F_GCR_BTLELDOCTRL_LDORFEN | MXC_F_GCR_BTLELDOCTRL_LDOBBEN | + MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_0_9 | MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_0_9); MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ISO_EN; diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me14.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me14.svd index 018778fd..52a915dc 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me14.svd +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me14.svd @@ -1864,281 +1864,281 @@ <description>BTLE LDO Control Register</description> <addressOffset>0x74</addressOffset> <fields> - <field> - <name>LDOTXEN</name> - <description>LDOTX Enable</description> - <bitOffset>0</bitOffset> - <bitWidth>1</bitWidth> - <enumeratedValues> - <enumeratedValue> - <name>dis</name> - <description>disabled.</description> - <value>0</value> - </enumeratedValue> - <enumeratedValue> - <name>en</name> - <description>enabled.</description> - <value>1</value> - </enumeratedValue> - </enumeratedValues> - </field> - <field> - <name>LDOTXOPULLD</name> - <description>LDOTX PULL Disable</description> - <bitOffset>1</bitOffset> - <bitWidth>1</bitWidth> - <enumeratedValues> - <enumeratedValue> - <name>en</name> - <description>enabled.</description> - <value>0</value> - </enumeratedValue> - <enumeratedValue> - <name>dis</name> - <description>disabled.</description> - <value>1</value> - </enumeratedValue> - </enumeratedValues> - </field> - <field> - <name>LDOTXVSEL</name> - <description>LDOTX Voltage Setting</description> - <bitOffset>2</bitOffset> - <bitWidth>2</bitWidth> - <enumeratedValues> - <enumeratedValue> - <name>0_7</name> - <description>0.7V</description> - <value>0</value> - </enumeratedValue> - <enumeratedValue> - <name>0_85</name> - <description>0.85V</description> - <value>1</value> - </enumeratedValue> - <enumeratedValue> - <name>0_9</name> - <description>0.9V</description> - <value>2</value> - </enumeratedValue> - <enumeratedValue> - <name>1_1</name> - <description>1.1V</description> - <value>3</value> - </enumeratedValue> - </enumeratedValues> - </field> - <field> - <name>LDORXEN</name> - <description>LDORX Enable</description> - <bitOffset>4</bitOffset> - <bitWidth>1</bitWidth> - <enumeratedValues> - <enumeratedValue> - <name>dis</name> - <description>disabled.</description> - <value>0</value> - </enumeratedValue> - <enumeratedValue> - <name>en</name> - <description>enabled.</description> - <value>1</value> - </enumeratedValue> - </enumeratedValues> - </field> - <field> - <name>LDORXPULLD</name> - <description>LDORX Pulldown</description> - <bitOffset>5</bitOffset> - <bitWidth>1</bitWidth> - <enumeratedValues> - <enumeratedValue> - <name>en</name> - <description>enabled.</description> - <value>0</value> - </enumeratedValue> - <enumeratedValue> - <name>dis</name> - <description>disabled.</description> - <value>1</value> - </enumeratedValue> - </enumeratedValues> - </field> - <field> - <name>LDORXVSEL</name> - <description>LDORX Output Voltage Setting</description> - <bitOffset>6</bitOffset> - <bitWidth>2</bitWidth> - <enumeratedValues> - <enumeratedValue> - <name>0_7</name> - <description>0.7V</description> - <value>0</value> - </enumeratedValue> - <enumeratedValue> - <name>0_85</name> - <description>0.85V</description> - <value>1</value> - </enumeratedValue> - <enumeratedValue> - <name>0_9</name> - <description>0.9V</description> - <value>2</value> - </enumeratedValue> - <enumeratedValue> - <name>1_1</name> - <description>1.1V</description> - <value>3</value> - </enumeratedValue> - </enumeratedValues> - </field> - <field> - <name>LDORXBYP</name> - <description>LDORX Bypass Enable</description> - <bitOffset>8</bitOffset> - <bitWidth>1</bitWidth> - <enumeratedValues> - <enumeratedValue> - <name>dis</name> - <description>disabled.</description> - <value>0</value> - </enumeratedValue> - <enumeratedValue> - <name>en</name> - <description>enabled.</description> - <value>1</value> - </enumeratedValue> - </enumeratedValues> - </field> - <field> - <name>LDORXDISCH</name> - <description>LDORX Discharge</description> - <bitOffset>9</bitOffset> - <bitWidth>1</bitWidth> - <enumeratedValues> - <enumeratedValue> - <name>dis</name> - <description>disabled.</description> - <value>0</value> - </enumeratedValue> - <enumeratedValue> - <name>en</name> - <description>enabled.</description> - <value>1</value> - </enumeratedValue> - </enumeratedValues> - </field> - <field> - <name>LDOTXBYP</name> - <description>LDOTX Bypass Enable</description> - <bitOffset>10</bitOffset> - <bitWidth>1</bitWidth> - <enumeratedValues> - <enumeratedValue> - <name>dis</name> - <description>disabled.</description> - <value>0</value> - </enumeratedValue> - <enumeratedValue> - <name>en</name> - <description>enabled.</description> - <value>1</value> - </enumeratedValue> - </enumeratedValues> - </field> - <field> - <name>LDOTXDISCH</name> - <description>LDOTX Discharge</description> - <bitOffset>11</bitOffset> - <bitWidth>1</bitWidth> - <enumeratedValues> - <enumeratedValue> - <name>dis</name> - <description>disabled.</description> - <value>0</value> - </enumeratedValue> - <enumeratedValue> - <name>en</name> - <description>enabled.</description> - <value>1</value> - </enumeratedValue> - </enumeratedValues> - </field> - <field> - <name>LDOTXENDLY</name> - <description>LDOTX Enable Delay</description> - <bitOffset>12</bitOffset> - <bitWidth>1</bitWidth> - <enumeratedValues> - <enumeratedValue> - <name>dis</name> - <description>disabled.</description> - <value>0</value> - </enumeratedValue> - <enumeratedValue> - <name>en</name> - <description>enabled.</description> - <value>1</value> - </enumeratedValue> - </enumeratedValues> - </field> - <field> - <name>LDORXENDLY</name> - <description>LDORX Enable Delay</description> - <bitOffset>13</bitOffset> - <bitWidth>1</bitWidth> - <enumeratedValues> - <enumeratedValue> - <name>dis</name> - <description>disabled.</description> - <value>0</value> - </enumeratedValue> - <enumeratedValue> - <name>en</name> - <description>enabled.</description> - <value>1</value> - </enumeratedValue> - </enumeratedValues> - </field> - <field> - <name>LDORXBYPENENDLY</name> - <description>LDOTX Bypass Enable Delay</description> - <bitOffset>14</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDOTXBYPENENDLY</name> - <description>LDORX Bypass Enable Delay</description> - <bitOffset>15</bitOffset> - <bitWidth>1</bitWidth> - </field> + <field> + <name>LDORXEN</name> + <description>LDORX Enable</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + <enumeratedValues> + <enumeratedValue> + <name>dis</name> + <description>disabled.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>en</name> + <description>enabled.</description> + <value>1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>LDORXOPULLD</name> + <description>LDORX PULL Disable</description> + <bitOffset>1</bitOffset> + <bitWidth>1</bitWidth> + <enumeratedValues> + <enumeratedValue> + <name>en</name> + <description>enabled.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>dis</name> + <description>disabled.</description> + <value>1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>LDORXVSEL</name> + <description>LDORX Voltage Setting</description> + <bitOffset>2</bitOffset> + <bitWidth>2</bitWidth> + <enumeratedValues> + <enumeratedValue> + <name>0_85</name> + <description>0.85V</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>0_9</name> + <description>0.9V</description> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>1_0</name> + <description>1.0V</description> + <value>2</value> + </enumeratedValue> + <enumeratedValue> + <name>1_1</name> + <description>1.1V</description> + <value>3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>LDOTXEN</name> + <description>LDOTX Enable</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + <enumeratedValues> + <enumeratedValue> + <name>dis</name> + <description>disabled.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>en</name> + <description>enabled.</description> + <value>1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>LDOTXPULLD</name> + <description>LDOTX Pulldown</description> + <bitOffset>5</bitOffset> + <bitWidth>1</bitWidth> + <enumeratedValues> + <enumeratedValue> + <name>en</name> + <description>enabled.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>dis</name> + <description>disabled.</description> + <value>1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>LDOTXVSEL</name> + <description>LDOTX Output Voltage Setting</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <enumeratedValues> + <enumeratedValue> + <name>0_85</name> + <description>0.85V</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>0_9</name> + <description>0.9V</description> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>1_0</name> + <description>1.0V</description> + <value>2</value> + </enumeratedValue> + <enumeratedValue> + <name>1_1</name> + <description>1.1V</description> + <value>3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>LDOTXBYP</name> + <description>LDOTX Bypass Enable</description> + <bitOffset>8</bitOffset> + <bitWidth>1</bitWidth> + <enumeratedValues> + <enumeratedValue> + <name>dis</name> + <description>disabled.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>en</name> + <description>enabled.</description> + <value>1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>LDOTXDISCH</name> + <description>LDOTX Discharge</description> + <bitOffset>9</bitOffset> + <bitWidth>1</bitWidth> + <enumeratedValues> + <enumeratedValue> + <name>dis</name> + <description>disabled.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>en</name> + <description>enabled.</description> + <value>1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>LDORXBYP</name> + <description>LDORX Bypass Enable</description> + <bitOffset>10</bitOffset> + <bitWidth>1</bitWidth> + <enumeratedValues> + <enumeratedValue> + <name>dis</name> + <description>disabled.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>en</name> + <description>enabled.</description> + <value>1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>LDORXDISCH</name> + <description>LDORX Discharge</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + <enumeratedValues> + <enumeratedValue> + <name>dis</name> + <description>disabled.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>en</name> + <description>enabled.</description> + <value>1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>LDORXENDLY</name> + <description>LDORX Enable Delay</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + <enumeratedValues> + <enumeratedValue> + <name>dis</name> + <description>disabled.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>en</name> + <description>enabled.</description> + <value>1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>LDOTXENDLY</name> + <description>LDOTX Enable Delay</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + <enumeratedValues> + <enumeratedValue> + <name>dis</name> + <description>disabled.</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>en</name> + <description>enabled.</description> + <value>1</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>LDOTXBYPENENDLY</name> + <description>LDORX Bypass Enable Delay</description> + <bitOffset>14</bitOffset> + <bitWidth>1</bitWidth> + </field> + <field> + <name>LDORXBYPENENDLY</name> + <description>LDOTX Bypass Enable Delay</description> + <bitOffset>15</bitOffset> + <bitWidth>1</bitWidth> + </field> </fields> - </register> - <register> + </register> + <register> <name>BTLE_LDODCR</name> <description>BTLE LDO Delay Register</description> <addressOffset>0x78</addressOffset> <fields> - <field> - <name>BYPDLYCNT</name> - <description>Bypass Delay Count. Count delay base on PCLK.</description> - <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - </field> - <field> - <name>LDORXDLYCNT</name> - <description>LDORX Delay Count. Count delay base on PCLK/128.</description> - <bitOffset>8</bitOffset> - <bitWidth>9</bitWidth> - </field> - <field> - <name>LDOTXDLYCNT</name> - <description>LDOTX Delay Count. Count delay base on PCLK/128.</description> - <bitOffset>20</bitOffset> - <bitWidth>9</bitWidth> - </field> + <field> + <name>BYPDLYCNT</name> + <description>Bypass Delay Count. Count delay base on PCLK.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> + </field> + <field> + <name>LDOTXDLYCNT</name> + <description>LDOTX Delay Count. Count delay base on PCLK/128.</description> + <bitOffset>8</bitOffset> + <bitWidth>9</bitWidth> + </field> + <field> + <name>LDORXDLYCNT</name> + <description>LDORX Delay Count. Count delay base on PCLK/128.</description> + <bitOffset>20</bitOffset> + <bitWidth>9</bitWidth> + </field> </fields> - </register> + </register> <register> <name>GP0</name> <description>General Purpose Register 0</description> diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me17.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me17.svd index dce8af63..06cc96ff 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me17.svd +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me17.svd @@ -1213,165 +1213,141 @@ </field> </fields> </register> - <register> - <name>BTLELDOCTRL</name> - <description>BTLE LDO Control Register</description> - <addressOffset>0x74</addressOffset> - <fields> - <field> - <name>LDOTXEN</name> - <description>LDOTX Enable.</description> - <bitOffset>0</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDOTXPULLD</name> - <description>LDOTX Pull Down.</description> - <bitOffset>1</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDOTXVSEL</name> - <description>LDOTX Voltage Setting.</description> - <bitOffset>2</bitOffset> - <bitWidth>2</bitWidth> - <enumeratedValues> - <enumeratedValue> - <name>0_7</name> - <description>0.7V</description> - <value>0</value> - </enumeratedValue> - <enumeratedValue> - <name>0_85</name> - <description>0.85V</description> - <value>1</value> - </enumeratedValue> - <enumeratedValue> - <name>0_9</name> - <description>0.9V</description> - <value>2</value> - </enumeratedValue> - <enumeratedValue> - <name>1_1</name> - <description>1.1V</description> - <value>3</value> - </enumeratedValue> - </enumeratedValues> - </field> - <field deprecated="(2-6-2023)"> - <name>LDOTXVSEL0</name> - <description>LDOTX Voltage Setting.</description> - <bitOffset>2</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field deprecated="(2-6-2023)"> - <name>LDOTXVSEL1</name> - <description>LDOTX Voltage Setting.</description> - <bitOffset>3</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDORXEN</name> - <description>LDORX Enable.</description> - <bitOffset>4</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDORXPULLD</name> - <description>LDOrX Pull Down.</description> - <bitOffset>5</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDORXVSEL</name> - <description>LDORX Voltage Setting.</description> - <bitOffset>6</bitOffset> - <bitWidth>2</bitWidth> - <enumeratedValues> - <enumeratedValue> - <name>0_7</name> - <description>0.7V</description> - <value>0</value> - </enumeratedValue> - <enumeratedValue> - <name>0_85</name> - <description>0.85V</description> - <value>1</value> - </enumeratedValue> - <enumeratedValue> - <name>0_9</name> - <description>0.9V</description> - <value>2</value> - </enumeratedValue> - <enumeratedValue> - <name>1_1</name> - <description>1.1V</description> - <value>3</value> - </enumeratedValue> - </enumeratedValues> - </field> - <field deprecated="(2-6-2023)"> - <name>LDORXVSEL0</name> - <description>LDORX Voltage Setting.</description> - <bitOffset>6</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field deprecated="(2-6-2023)"> - <name>LDORXVSEL1</name> - <description>LDORX Voltage Setting.</description> - <bitOffset>7</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDORXBYP</name> - <description>LDORX Bypass Enable.</description> - <bitOffset>8</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDORXDISCH</name> - <description>LDORX Discharge.</description> - <bitOffset>9</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDOTXBYP</name> - <description>LDOTX Bypass Enable.</description> - <bitOffset>10</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDOTXDISCH</name> - <description>LDOTX Discharge.</description> - <bitOffset>11</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDOTXENDLY</name> - <description>LDOTX Enable Delay.</description> - <bitOffset>12</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDORXENDLY</name> - <description>LDORX Enable Delay.</description> - <bitOffset>13</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDORXBYPENENDLY</name> - <description>LDORX Bypass Enable Delay.</description> - <bitOffset>14</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDOTXBYPENENDLY</name> - <description>LDOTX Bypass Enable Delay.</description> - <bitOffset>15</bitOffset> - <bitWidth>1</bitWidth> - </field> - </fields> - </register> + <register> + <name>BTLELDOCTRL</name> + <description>BTLE LDO Control Register</description> + <addressOffset>0x74</addressOffset> + <fields> + <field> + <name>LDOBBEN</name> + <description>LDOBB Enable.</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + </field> + <field> + <name>LDOBBPULLD</name> + <description>LDOBB Pull Down.</description> + <bitOffset>1</bitOffset> + <bitWidth>1</bitWidth> + </field> + <field> + <name>LDOBBVSEL</name> + <description>LDOBB Voltage Setting.</description> + <bitOffset>2</bitOffset> + <bitWidth>2</bitWidth> + <enumeratedValues> + <enumeratedValue> + <name>0_85</name> + <description>0.85V</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>0_9</name> + <description>0.9V</description> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>1_0</name> + <description>1.0V</description> + <value>2</value> + </enumeratedValue> + <enumeratedValue> + <name>1_1</name> + <description>1.1V</description> + <value>3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>LDORFEN</name> + <description>LDORF Enable.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + </field> + <field> + <name>LDORFPULLD</name> + <description>LDORF Pull Down.</description> + <bitOffset>5</bitOffset> + <bitWidth>1</bitWidth> + </field> + <field> + <name>LDORFVSEL</name> + <description>LDORF Voltage Setting.</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <enumeratedValues> + <enumeratedValue> + <name>0_85</name> + <description>0.85V</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>0_9</name> + <description>0.9V</description> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>1_0</name> + <description>1.0V</description> + <value>2</value> + </enumeratedValue> + <enumeratedValue> + <name>1_1</name> + <description>1.1V</description> + <value>3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>LDORFBYP</name> + <description>LDORF Bypass Enable.</description> + <bitOffset>8</bitOffset> + <bitWidth>1</bitWidth> + </field> + <field> + <name>LDORFDISCH</name> + <description>LDORF Discharge.</description> + <bitOffset>9</bitOffset> + <bitWidth>1</bitWidth> + </field> + <field> + <name>LDOBBBYP</name> + <description>LDOBB Bypass Enable.</description> + <bitOffset>10</bitOffset> + <bitWidth>1</bitWidth> + </field> + <field> + <name>LDOBBDISCH</name> + <description>LDOBB Discharge.</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + </field> + <field> + <name>LDOBBENDLY</name> + <description>LDOBB Enable Delay.</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + </field> + <field> + <name>LDORFENDLY</name> + <description>LDORF Enable Delay.</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + </field> + <field> + <name>LDORFBYPENENDLY</name> + <description>LDORF Bypass Enable Delay.</description> + <bitOffset>14</bitOffset> + <bitWidth>1</bitWidth> + </field> + <field> + <name>LDOBBBYPENENDLY</name> + <description>LDOBB Bypass Enable Delay.</description> + <bitOffset>15</bitOffset> + <bitWidth>1</bitWidth> + </field> + </fields> + </register> <register> <name>BTLELDODLY</name> <description>BTLE LDO Delay Register</description> @@ -1384,14 +1360,14 @@ <bitWidth>8</bitWidth> </field> <field> - <name>LDORXDLYCNT</name> - <description>LDORX Delay Count.</description> + <name>LDOBBDLYCNT</name> + <description>LDOBB Delay Count.</description> <bitOffset>8</bitOffset> <bitWidth>9</bitWidth> </field> <field> - <name>LDOTXDLYCNT</name> - <description>LDOTX Delay Count.</description> + <name>LDORFDLYCNT</name> + <description>LDOBB Delay Count.</description> <bitOffset>20</bitOffset> <bitWidth>9</bitWidth> </field> diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me18.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me18.svd index f0389422..9d79a039 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me18.svd +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me18.svd @@ -1596,117 +1596,161 @@ <description>BTLE LDO Control Register</description> <addressOffset>0x74</addressOffset> <fields> - <field> - <name>LDOTXEN</name> - <description>LDOTX Enable.</description> - <bitOffset>0</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDOTXPULLD</name> - <description>LDOTX Pull Down.</description> - <bitOffset>1</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDOTXVSEL</name> - <description>LDOTX Voltage Setting.</description> - <bitOffset>2</bitOffset> - <bitWidth>2</bitWidth> - </field> - <field> - <name>LDORXEN</name> - <description>LDORX Enable.</description> - <bitOffset>4</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDORXPULLD</name> - <description>LDOrX Pull Down.</description> - <bitOffset>5</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDORXVSEL</name> - <description>LDORX Voltage Setting.</description> - <bitOffset>6</bitOffset> - <bitWidth>2</bitWidth> - </field> - <field> - <name>LDORXBYP</name> - <description>LDORX Bypass Enable.</description> - <bitOffset>8</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDORXDISCH</name> - <description>LDORX Discharge.</description> - <bitOffset>9</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDOTXBYP</name> - <description>LDOTX Bypass Enable.</description> - <bitOffset>10</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDOTXDISCH</name> - <description>LDOTX Discharge.</description> - <bitOffset>11</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDOTXENDLY</name> - <description>LDOTX Enable Delay.</description> - <bitOffset>12</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDORXENDLY</name> - <description>LDORX Enable Delay.</description> - <bitOffset>13</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDORXBYPENENDLY</name> - <description>LDORX Bypass Enable Delay.</description> - <bitOffset>14</bitOffset> - <bitWidth>1</bitWidth> - </field> - <field> - <name>LDOTXBYPENENDLY</name> - <description>LDOTX Bypass Enable Delay.</description> - <bitOffset>15</bitOffset> - <bitWidth>1</bitWidth> - </field> + <field> + <name>LDOBBEN</name> + <description>LDOBB Enable.</description> + <bitOffset>0</bitOffset> + <bitWidth>1</bitWidth> + </field> + <field> + <name>LDOBBPULLD</name> + <description>LDOBB Pull Down.</description> + <bitOffset>1</bitOffset> + <bitWidth>1</bitWidth> + </field> + <field> + <name>LDOBBVSEL</name> + <description>LDOBB Voltage Setting.</description> + <bitOffset>2</bitOffset> + <bitWidth>2</bitWidth> + <enumeratedValues> + <enumeratedValue> + <name>0_85</name> + <description>0.85V</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>0_9</name> + <description>0.9V</description> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>1_0</name> + <description>1.0V</description> + <value>2</value> + </enumeratedValue> + <enumeratedValue> + <name>1_1</name> + <description>1.1V</description> + <value>3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>LDORFEN</name> + <description>LDORF Enable.</description> + <bitOffset>4</bitOffset> + <bitWidth>1</bitWidth> + </field> + <field> + <name>LDORFPULLD</name> + <description>LDORF Pull Down.</description> + <bitOffset>5</bitOffset> + <bitWidth>1</bitWidth> + </field> + <field> + <name>LDORFVSEL</name> + <description>LDORF Voltage Setting.</description> + <bitOffset>6</bitOffset> + <bitWidth>2</bitWidth> + <enumeratedValues> + <enumeratedValue> + <name>0_85</name> + <description>0.85V</description> + <value>0</value> + </enumeratedValue> + <enumeratedValue> + <name>0_9</name> + <description>0.9V</description> + <value>1</value> + </enumeratedValue> + <enumeratedValue> + <name>1_0</name> + <description>1.0V</description> + <value>2</value> + </enumeratedValue> + <enumeratedValue> + <name>1_1</name> + <description>1.1V</description> + <value>3</value> + </enumeratedValue> + </enumeratedValues> + </field> + <field> + <name>LDORFBYP</name> + <description>LDORF Bypass Enable.</description> + <bitOffset>8</bitOffset> + <bitWidth>1</bitWidth> + </field> + <field> + <name>LDORFDISCH</name> + <description>LDORF Discharge.</description> + <bitOffset>9</bitOffset> + <bitWidth>1</bitWidth> + </field> + <field> + <name>LDOBBBYP</name> + <description>LDOBB Bypass Enable.</description> + <bitOffset>10</bitOffset> + <bitWidth>1</bitWidth> + </field> + <field> + <name>LDOBBDISCH</name> + <description>LDOBB Discharge.</description> + <bitOffset>11</bitOffset> + <bitWidth>1</bitWidth> + </field> + <field> + <name>LDOBBENDLY</name> + <description>LDOBB Enable Delay.</description> + <bitOffset>12</bitOffset> + <bitWidth>1</bitWidth> + </field> + <field> + <name>LDORFENDLY</name> + <description>LDORF Enable Delay.</description> + <bitOffset>13</bitOffset> + <bitWidth>1</bitWidth> + </field> + <field> + <name>LDORFBYPENENDLY</name> + <description>LDORF Bypass Enable Delay.</description> + <bitOffset>14</bitOffset> + <bitWidth>1</bitWidth> + </field> + <field> + <name>LDOBBBYPENENDLY</name> + <description>LDOBB Bypass Enable Delay.</description> + <bitOffset>15</bitOffset> + <bitWidth>1</bitWidth> + </field> </fields> - </register> - <register> + </register> + <register> <name>BTLELDODLY</name> <description>BTLE LDO Delay Register</description> <addressOffset>0x78</addressOffset> <fields> - <field> - <name>BYPDLYCNT</name> - <description>Bypass Delay Count.</description> - <bitOffset>0</bitOffset> - <bitWidth>8</bitWidth> - </field> - <field> - <name>LDOTXDLYCNT</name> - <description>LDOTX Delay Count.</description> - <bitOffset>8</bitOffset> - <bitWidth>9</bitWidth> - </field> - <field> - <name>LDORXDLYCNT</name> - <description>LDORX Delay Count.</description> - <bitOffset>20</bitOffset> - <bitWidth>9</bitWidth> - </field> + <field> + <name>BYPDLYCNT</name> + <description>Bypass Delay Count.</description> + <bitOffset>0</bitOffset> + <bitWidth>8</bitWidth> + </field> + <field> + <name>LDORFDLYCNT</name> + <description>LDORF Delay Count.</description> + <bitOffset>8</bitOffset> + <bitWidth>9</bitWidth> + </field> + <field> + <name>LDOBBDLYCNT</name> + <description>LDOBB Delay Count.</description> + <bitOffset>20</bitOffset> + <bitWidth>9</bitWidth> + </field> </fields> - </register> + </register> <register> <name>GPR0</name> <description>General Purpose Register 0</description> diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me14.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me14.svd index 33037b35..ee57622c 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me14.svd +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me14.svd @@ -1,5 +1,6 @@ <?xml version="1.0" encoding="utf-8" standalone="no"?> -<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> +<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" + xs:noNamespaceSchemaLocation="svd_schema.xsd"> <peripheral> <name>SIR</name> <description>System Initialization Registers.</description> @@ -19,7 +20,8 @@ <fields> <field> <name>MAGIC</name> - <description>Magic Word Validation. This bit is set by the system initialization block following power-up.</description> + <description>Magic Word Validation. This bit is set by the system initialization block + following power-up.</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> @@ -39,7 +41,8 @@ </field> <field> <name>CRCERR</name> - <description>CRC Error Status. This bit is set by the system initialization block following power-up.</description> + <description>CRC Error Status. This bit is set by the system initialization block + following power-up.</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> @@ -52,7 +55,8 @@ </enumeratedValue> <enumeratedValue> <name>error</name> - <description>A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register.</description> + <description>A CRC error occurred while reading the OTP. The address of the failure + location in the OTP memory is stored in the ERRADDR register.</description> <value>1</value> </enumeratedValue> </enumeratedValues> @@ -61,7 +65,8 @@ </register> <register> <name>ERRADDR</name> - <description>Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1).</description> + <description>Read-only field set by the SIB block if a CRC error occurs during the read of + the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1).</description> <addressOffset>0x04</addressOffset> <access>read-only</access> <fields> @@ -72,6 +77,40 @@ </field> </fields> </register> + + + <register> + <name>BTLE_LDO_TRIM_TX</name> + <description>BTLE LDO TX Trim register.</description> + <addressOffset>0x54</addressOffset> + <access>read-write</access> + <fields> + <field> + <name>TX</name> + <description>TX LDO trim value.</description> + <bitOffset>0</bitOffset> + <bitWidth>5</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + + <register> + <name>BTLE_LDO_TRIM_RX</name> + <description>BTLE LDO RX Trim register.</description> + <addressOffset>0x5C</addressOffset> + <access>read-write</access> + <fields> + <field> + <name>RX</name> + <description>RX LDO trim value.</description> + <bitOffset>0</bitOffset> + <bitWidth>5</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> + <register> <name>FSTAT</name> <description>funcstat register.</description> diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me17.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me17.svd index a3b401cd..e84b7101 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me17.svd +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me17.svd @@ -72,28 +72,28 @@ </field> </fields> </register> - <register> - <name>BTLE_LDO_TRIM</name> - <description>BTLE LDO Trim register.</description> - <addressOffset>0x48</addressOffset> - <access>read-write</access> - <fields> - <field> - <name>TX</name> - <description>TX LDO trim value.</description> - <bitOffset>0</bitOffset> - <bitWidth>5</bitWidth> - <access>read-write</access> - </field> - <field> - <name>RX</name> - <description>RX LDO trim value.</description> - <bitOffset>8</bitOffset> - <bitWidth>5</bitWidth> - <access>read-write</access> - </field> - </fields> - </register> + <register> + <name>BTLE_LDO_TRIM</name> + <description>BTLE LDO Trim register.</description> + <addressOffset>0x48</addressOffset> + <access>read-write</access> + <fields> + <field> + <name>RF</name> + <description>RF LDO trim value.</description> + <bitOffset>16</bitOffset> + <bitWidth>5</bitWidth> + <access>read-write</access> + </field> + <field> + <name>BB</name> + <description>BB LDO trim value.</description> + <bitOffset>24</bitOffset> + <bitWidth>5</bitWidth> + <access>read-write</access> + </field> + </fields> + </register> <register> <name>FSTAT</name> <description>funcstat register.</description> diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me18.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me18.svd index 6174cb8c..da911131 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me18.svd +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me18.svd @@ -1,5 +1,6 @@ <?xml version="1.0" encoding="utf-8" standalone="no"?> -<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> +<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" + xs:noNamespaceSchemaLocation="svd_schema.xsd"> <peripheral> <name>SIR</name> <description>System Initialization Registers.</description> @@ -19,7 +20,8 @@ <fields> <field> <name>MAGIC</name> - <description>Magic Word Validation. This bit is set by the system initialization block following power-up.</description> + <description>Magic Word Validation. This bit is set by the system initialization block + following power-up.</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> @@ -39,7 +41,8 @@ </field> <field> <name>CRCERR</name> - <description>CRC Error Status. This bit is set by the system initialization block following power-up.</description> + <description>CRC Error Status. This bit is set by the system initialization block + following power-up.</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> @@ -52,7 +55,8 @@ </enumeratedValue> <enumeratedValue> <name>error</name> - <description>A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register.</description> + <description>A CRC error occurred while reading the OTP. The address of the failure + location in the OTP memory is stored in the ERRADDR register.</description> <value>1</value> </enumeratedValue> </enumeratedValues> @@ -61,7 +65,8 @@ </register> <register> <name>SIADDR</name> - <description>Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1).</description> + <description>Read-only field set by the SIB block if a CRC error occurs during the read of + the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1).</description> <addressOffset>0x04</addressOffset> <access>read-only</access> <fields> @@ -79,15 +84,15 @@ <access>read-write</access> <fields> <field> - <name>TX</name> - <description>TX LDO trim value.</description> + <name>RF</name> + <description>RF LDO trim value.</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> <access>read-write</access> </field> <field> - <name>RX</name> - <description>RX LDO trim value.</description> + <name>BB</name> + <description>BB LDO trim value.</description> <bitOffset>5</bitOffset> <bitWidth>5</bitWidth> <access>read-write</access> diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me17.c b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me17.c index cb9ad432..ff2d5c92 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me17.c +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me17.c @@ -248,7 +248,7 @@ int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock) break; case MXC_SYS_CLOCK_ERFO: - MXC_GCR->btleldoctrl |= MXC_F_GCR_BTLELDOCTRL_LDOTXEN | MXC_F_GCR_BTLELDOCTRL_LDORXEN; + MXC_GCR->btleldoctrl |= MXC_F_GCR_BTLELDOCTRL_LDORFEN | MXC_F_GCR_BTLELDOCTRL_LDOBBEN; /* Initialize kickstart circuit Select Kick start circuit clock source- IPO/ISO diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me18.c b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me18.c index 40a48497..79aa5c17 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me18.c +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me18.c @@ -255,7 +255,7 @@ int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock) break; case MXC_SYS_CLOCK_ERFO: - MXC_GCR->btleldoctrl |= MXC_F_GCR_BTLELDOCTRL_LDOTXEN | MXC_F_GCR_BTLELDOCTRL_LDORXEN; + MXC_GCR->btleldoctrl |= MXC_F_GCR_BTLELDOCTRL_LDORFEN | MXC_F_GCR_BTLELDOCTRL_LDOBBEN; MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERFO_EN; return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_ERFO_RDY); diff --git a/MAX/msdk_sha b/MAX/msdk_sha index 8e70396a..cb10793f 100644 --- a/MAX/msdk_sha +++ b/MAX/msdk_sha @@ -1 +1 @@ -fb3ae96e021ca2bd195408e1ee0e88f1057e2119 +51ec9ada64735befc5cdc4dac00bbc2f32baf031