From 2d98222bf0ad1338a1ec3062805a5ae82c2eb05c Mon Sep 17 00:00:00 2001 From: Alexis Czezar Torreno Date: Tue, 17 Dec 2024 22:39:00 +0800 Subject: [PATCH] ad353xr: de10nano: add project Adding project ad353xr for de10nano Signed-off-by: Alexis Czezar Torreno --- projects/ad353xr/de10nano/Makefile | 18 ++ projects/ad353xr/de10nano/system_constr.sdc | 10 + projects/ad353xr/de10nano/system_project.tcl | 37 +++ projects/ad353xr/de10nano/system_qsys.tcl | 16 ++ projects/ad353xr/de10nano/system_top.v | 235 +++++++++++++++++++ 5 files changed, 316 insertions(+) create mode 100644 projects/ad353xr/de10nano/Makefile create mode 100644 projects/ad353xr/de10nano/system_constr.sdc create mode 100644 projects/ad353xr/de10nano/system_project.tcl create mode 100644 projects/ad353xr/de10nano/system_qsys.tcl create mode 100644 projects/ad353xr/de10nano/system_top.v diff --git a/projects/ad353xr/de10nano/Makefile b/projects/ad353xr/de10nano/Makefile new file mode 100644 index 0000000000..211eb8a3b2 --- /dev/null +++ b/projects/ad353xr/de10nano/Makefile @@ -0,0 +1,18 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad353xR_de10nano + +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/de10nano/de10nano_system_qsys.tcl +M_DEPS += ../../common/de10nano/de10nano_system_assign.tcl + +LIB_DEPS += axi_dmac +LIB_DEPS += axi_hdmi_tx +LIB_DEPS += axi_sysid +LIB_DEPS += sysid_rom + +include ../../scripts/project-intel.mk diff --git a/projects/ad353xr/de10nano/system_constr.sdc b/projects/ad353xr/de10nano/system_constr.sdc new file mode 100644 index 0000000000..7e13342108 --- /dev/null +++ b/projects/ad353xr/de10nano/system_constr.sdc @@ -0,0 +1,10 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +create_clock -period "20.000 ns" -name sys_clk_50mhz [get_ports {sys_clk}] +create_clock -period "16.666 ns" -name usb_clk_60mhz [get_ports {usbl_clk}] + +derive_pll_clocks +derive_clock_uncertainty diff --git a/projects/ad353xr/de10nano/system_project.tcl b/projects/ad353xr/de10nano/system_project.tcl new file mode 100644 index 0000000000..b3d43545a8 --- /dev/null +++ b/projects/ad353xr/de10nano/system_project.tcl @@ -0,0 +1,37 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set REQUIRED_QUARTUS_VERSION 21.1.0 +set QUARTUS_PRO_ISUSED 0 +source ../../../scripts/adi_env.tcl +source ../../scripts/adi_project_intel.tcl + +adi_project ad353xR_de10nano + +source $ad_hdl_dir/projects/common/de10nano/de10nano_system_assign.tcl + +# SPI connections + +set_location_assignment PIN_AG18 -to spiml_clk ; ## GPIO1 JP7 [33] +set_location_assignment PIN_AF18 -to spiml_miso ; ## GPIO1 JP7 [35] +set_location_assignment PIN_AG15 -to spiml_mosi ; ## GPIO1 JP7 [37] +set_location_assignment PIN_AE19 -to spiml_ss0 ; ## GPIO1 JP7 [39] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spiml_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spiml_clk_miso +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spiml_clk_mosi +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spiml_clk_ss0 + +# GPIO connections + +set_location_assignment PIN_AE20 -to dac_resetb ; ## GPIO1 JP7 [38] +set_location_assignment PIN_AE17 -to dac_ldacb ; ## GPIO1 JP7 [40] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dac_resetb +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dac_ldacb + + + +execute_flow -compile diff --git a/projects/ad353xr/de10nano/system_qsys.tcl b/projects/ad353xr/de10nano/system_qsys.tcl new file mode 100644 index 0000000000..0245f9377b --- /dev/null +++ b/projects/ad353xr/de10nano/system_qsys.tcl @@ -0,0 +1,16 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source $ad_hdl_dir/projects/scripts/adi_pd.tcl +source $ad_hdl_dir/projects/common/de10nano/de10nano_system_qsys.tcl + +#system ID +set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9} +set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9} + +set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "[pwd]/mem_init_sys.txt" + +sysid_gen_sys_init_file; + diff --git a/projects/ad353xr/de10nano/system_top.v b/projects/ad353xr/de10nano/system_top.v new file mode 100644 index 0000000000..67aed44f27 --- /dev/null +++ b/projects/ad353xr/de10nano/system_top.v @@ -0,0 +1,235 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + // clock and resets + input sys_clk, + + // hps-ddr + output [14:0] ddr3_a, + output [ 2:0] ddr3_ba, + output ddr3_reset_n, + output ddr3_ck_p, + output ddr3_ck_n, + output ddr3_cke, + output ddr3_cs_n, + output ddr3_ras_n, + output ddr3_cas_n, + output ddr3_we_n, + inout [31:0] ddr3_dq, + inout [ 3:0] ddr3_dqs_p, + inout [ 3:0] ddr3_dqs_n, + output [ 3:0] ddr3_dm, + output ddr3_odt, + input ddr3_rzq, + + // hps-ethernet + output eth1_tx_clk, + output eth1_tx_ctl, + output [ 3:0] eth1_tx_d, + input eth1_rx_clk, + input eth1_rx_ctl, + input [ 3:0] eth1_rx_d, + output eth1_mdc, + inout eth1_mdio, + + // hps-sdio + output sdio_clk, + inout sdio_cmd, + inout [ 3:0] sdio_d, + + // hps-spim1 + output spim1_ss0, + output spim1_clk, + output spim1_mosi, + input spim1_miso, + + // hps-usb + input usb1_clk, + output usb1_stp, + input usb1_dir, + input usb1_nxt, + inout [ 7:0] usb1_d, + + // hps-uart + input uart0_rx, + output uart0_tx, + inout hps_conv_usb_n, + + // board gpio + output [ 7:0] gpio_bd_o, + input [ 5:0] gpio_bd_i, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [ 23:0] hdmi_data, + + inout hdmi_i2c_scl, + inout hdmi_i2c_sda, + + // additional control signals + output dac_resetb, + output dac_ldacb +); + + // internal signals + + wire sys_resetn; + wire [63:0] gpio_i; + wire [63:0] gpio_o; + + wire i2c0_out_data; + wire i2c0_sda; + wire i2c0_out_clk; + wire i2c0_scl_in_clk; + + // instantiations + + assign gpio_i[63:14] = gpio_o[63:14]; + assign gpio_i[13:8] = gpio_bd_i[5:0]; + + assign gpio_bd_o[7:0] = gpio_o[7:0]; + + assign dac_resetb = gpio_o[33]; + assign dac_ldacb = gpio_o[34]; + + ALT_IOBUF scl_iobuf ( + .i (1'b0), + .oe (i2c0_out_clk), + .o (i2c0_scl_in_clk), + .io (hdmi_i2c_scl)); + + ALT_IOBUF sda_iobuf ( + .i (1'b0), + .oe (i2c0_out_data), + .o (i2c0_sda), + .io (hdmi_i2c_sda)); + + system_bd i_system_bd ( + .sys_clk_clk (sys_clk), + + .sys_hps_h2f_reset_reset_n (sys_resetn), + + .sys_hps_memory_mem_a (ddr3_a), + .sys_hps_memory_mem_ba (ddr3_ba), + .sys_hps_memory_mem_ck (ddr3_ck_p), + .sys_hps_memory_mem_ck_n (ddr3_ck_n), + .sys_hps_memory_mem_cke (ddr3_cke), + .sys_hps_memory_mem_cs_n (ddr3_cs_n), + .sys_hps_memory_mem_ras_n (ddr3_ras_n), + .sys_hps_memory_mem_cas_n (ddr3_cas_n), + .sys_hps_memory_mem_we_n (ddr3_we_n), + .sys_hps_memory_mem_reset_n (ddr3_reset_n), + .sys_hps_memory_mem_dq (ddr3_dq), + .sys_hps_memory_mem_dqs (ddr3_dqs_p), + .sys_hps_memory_mem_dqs_n (ddr3_dqs_n), + .sys_hps_memory_mem_odt (ddr3_odt), + .sys_hps_memory_mem_dm (ddr3_dm), + .sys_hps_memory_oct_rzqin (ddr3_rzq), + + .sys_rst_reset_n (sys_resetn), + + .sys_hps_i2c0_out_data (i2c0_out_data), + .sys_hps_i2c0_sda (i2c0_sda), + .sys_hps_i2c0_clk_clk (i2c0_out_clk), + .sys_hps_i2c0_scl_in_clk (i2c0_scl_in_clk), + + .sys_hps_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk), + .sys_hps_hps_io_hps_io_emac1_inst_TXD0 (eth1_tx_d[0]), + .sys_hps_hps_io_hps_io_emac1_inst_TXD1 (eth1_tx_d[1]), + .sys_hps_hps_io_hps_io_emac1_inst_TXD2 (eth1_tx_d[2]), + .sys_hps_hps_io_hps_io_emac1_inst_TXD3 (eth1_tx_d[3]), + .sys_hps_hps_io_hps_io_emac1_inst_RXD0 (eth1_rx_d[0]), + .sys_hps_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio), + .sys_hps_hps_io_hps_io_emac1_inst_MDC (eth1_mdc), + .sys_hps_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl), + .sys_hps_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl), + .sys_hps_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk), + .sys_hps_hps_io_hps_io_emac1_inst_RXD1 (eth1_rx_d[1]), + .sys_hps_hps_io_hps_io_emac1_inst_RXD2 (eth1_rx_d[2]), + .sys_hps_hps_io_hps_io_emac1_inst_RXD3 (eth1_rx_d[3]), + + .sys_hps_hps_io_hps_io_sdio_inst_CMD (sdio_cmd), + .sys_hps_hps_io_hps_io_sdio_inst_D0 (sdio_d[0]), + .sys_hps_hps_io_hps_io_sdio_inst_D1 (sdio_d[1]), + .sys_hps_hps_io_hps_io_sdio_inst_CLK (sdio_clk), + .sys_hps_hps_io_hps_io_sdio_inst_D2 (sdio_d[2]), + .sys_hps_hps_io_hps_io_sdio_inst_D3 (sdio_d[3]), + + .sys_hps_hps_io_hps_io_usb1_inst_D0 (usb1_d[0]), + .sys_hps_hps_io_hps_io_usb1_inst_D1 (usb1_d[1]), + .sys_hps_hps_io_hps_io_usb1_inst_D2 (usb1_d[2]), + .sys_hps_hps_io_hps_io_usb1_inst_D3 (usb1_d[3]), + .sys_hps_hps_io_hps_io_usb1_inst_D4 (usb1_d[4]), + .sys_hps_hps_io_hps_io_usb1_inst_D5 (usb1_d[5]), + .sys_hps_hps_io_hps_io_usb1_inst_D6 (usb1_d[6]), + .sys_hps_hps_io_hps_io_usb1_inst_D7 (usb1_d[7]), + .sys_hps_hps_io_hps_io_usb1_inst_CLK (usb1_clk), + .sys_hps_hps_io_hps_io_usb1_inst_STP (usb1_stp), + .sys_hps_hps_io_hps_io_usb1_inst_DIR (usb1_dir), + .sys_hps_hps_io_hps_io_usb1_inst_NXT (usb1_nxt), + + .sys_hps_hps_io_hps_io_uart0_inst_RX (uart0_rx), + .sys_hps_hps_io_hps_io_uart0_inst_TX (uart0_tx), + + .sys_hps_hps_io_hps_io_spim1_inst_CLK (spim1_clk), + .sys_hps_hps_io_hps_io_spim1_inst_MOSI (spim1_mosi), + .sys_hps_hps_io_hps_io_spim1_inst_MISO (spim1_miso), + .sys_hps_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0), + + .sys_hps_hps_io_hps_io_gpio_inst_GPIO09 (hps_conv_usb_n), + + .sys_gpio_bd_in_port (gpio_i[31:0]), + .sys_gpio_bd_out_port (gpio_o[31:0]), + .sys_gpio_in_export (gpio_i[63:32]), + .sys_gpio_out_export (gpio_o[63:32]), + + .ltc2308_spi_MISO (1'b0), + .ltc2308_spi_MOSI (), + .ltc2308_spi_SCLK (), + .ltc2308_spi_SS_n (1'b1), + + .axi_hdmi_tx_0_hdmi_if_h_clk (hdmi_out_clk), + .axi_hdmi_tx_0_hdmi_if_h24_hsync (hdmi_hsync), + .axi_hdmi_tx_0_hdmi_if_h24_vsync (hdmi_vsync), + .axi_hdmi_tx_0_hdmi_if_h24_data_e (hdmi_data_e), + .axi_hdmi_tx_0_hdmi_if_h24_data (hdmi_data)); + +endmodule