From a2aa937bef9535455455bf5f5d6ec8424e7eae5d Mon Sep 17 00:00:00 2001 From: caosjr Date: Fri, 13 Dec 2024 10:26:30 -0300 Subject: [PATCH] ADD: update documentation Adapted documentation for the axi_ad35xxr to include the four DACs: AD3541R, AD3542R, AD3551R, and AD3552R. Adapted AD355xR_EVB to include information about the AD3551R and AD3552R. Inserted information about the QSPI_SEL pin. Inserted MULTI_IO_MODE reg to the remap of the ad3552r. Signed-off-by: --- docs/library/axi_ad3552r/index.rst | 88 ++++++++++++++++---------- docs/projects/ad3552r_evb/index.rst | 36 ++++++----- docs/regmap/adi_regmap_axi_ad3552r.txt | 7 ++ projects/ad3542r_evb/Readme.md | 2 +- projects/ad35xxr_evb/Readme.md | 12 +++- 5 files changed, 91 insertions(+), 54 deletions(-) diff --git a/docs/library/axi_ad3552r/index.rst b/docs/library/axi_ad3552r/index.rst index 91131d2c66..3dbe0f591b 100644 --- a/docs/library/axi_ad3552r/index.rst +++ b/docs/library/axi_ad3552r/index.rst @@ -1,29 +1,37 @@ .. _axi_ad3552r: -AXI AD3552R +AXI AD35XXR ================================================================================ .. hdl-component-diagram:: + :path: library/axi_ad35xxr + +The :git-hdl:`AXI AD3552R ` IP core can be used to +interface the :adi:`AD3552R`, :adi:`AD3551R`, :adi:`AD3542R`, and +:adi:`AD3541R`. :adi:`AD3552R` is a low drift, dual channel, ultra-fast, +16-bit accuracy, current output digital-to-analog converter (DAC) that can be +configured in multiple voltage span ranges, the :adi:`AD3551R` is the single +channel part. :adi:`AD3542R` is is a low drift, dual channel, ultra-fast, +12-/16-bit accuracy, voltage output digital-to-analog converter (DAC) that +can be configured in multiple voltage span ranges, the :adi:`AD3541R` is the +single channel part. -The :git-hdl:`AXI AD3552R ` IP core -can be used to interface the :adi:`AD3552R`, a low drift, ultra-fast, 16-bit -accuracy, current output digital-to-analog converter (DAC) that can be -configured in multiple voltage span ranges. Features -------------------------------------------------------------------------------- -* AXI-based configuration -* Vivado compatible -* 8b register read/write SDR/DDR -* 16b register read/write SDR/DDR -* data stream SDR/DDR ( clk_in/8 or clk_in/4 update rate) -* selectable input source: DMA/ADC/TEST_RAMP -* data out clock(SCLK) has clk_in/8 frequency when the converter is configured and - clk_in/2 when the converter is in stream mode -* the IP reference clock (clk_in) can have a maximum frequency of 132MHz -* the IP has multiple device synchronization capability when the DMA is set - as an input data source +* AXI-based configuration; +* Vivado compatible; +* 8b register read/write SDR/DDR; +* 16b register read/write SDR/DDR; +* Data stream SDR/DDR ( clk_in/8 or clk_in/4 update rate); +* Selectable input source: DMA/ADC/TEST_RAMP; +* Data out clock(SCLK) has clk_in/2 frequency for both configuration and streaming + mode; +* The IP reference clock (clk_in) can have a maximum frequency of 132MHz; +* The IP has multiple device synchronization capability when the DMA is set + as an input data source. + Files -------------------------------------------------------------------------------- @@ -33,19 +41,19 @@ Files * - Name - Description - * - :git-hdl:`library/axi_ad3552r/axi_ad3552r.v` + * - :git-hdl:`dev_ad3542r:library/axi_ad35xxr/axi_ad35xxr.v` - Verilog source for the AXI AD3552R. - * - :git-hdl:`library/axi_ad3552r/axi_ad3552r_channel.v` + * - :git-hdl:`dev_ad3542r:library/axi_ad35xxr/axi_ad35xxr_channel.v` - Verilog source for the AXI AD3552R channel. - * - :git-hdl:`library/axi_ad3552r/axi_ad3552r_core.v` + * - :git-hdl:`dev_ad3542r:library/axi_ad35xxr/axi_ad35xxr_core.v` - Verilog source for the AXI AD3552R core. - * - :git-hdl:`library/axi_ad3552r/axi_ad3552r_if.v` + * - :git-hdl:`dev_ad3542r:library/axi_ad35xxr/axi_ad35xxr_if.v` - Verilog source for the AD3552R interface module. - * - :git-hdl:`library/axi_ad3552r/axi_ad3552r_if_tb.v` + * - :git-hdl:`dev_ad3542r:library/axi_ad35xxr/axi_ad35xxr_if_tb.v` - Verilog source for the AD3552R interface module testbench. - * - :git-hdl:`library/axi_ad3552r/axi_ad3552r_if_tb` + * - :git-hdl:`dev_ad3542r:library/axi_ad35xxr/axi_ad35xxr_if_tb` - Setup script for the AD3552R interface module testbench. - * - :git-hdl:`library/axi_ad3552r/axi_ad3552r_ip.tcl` + * - :git-hdl:`dev_ad3542r:library/axi_ad35xxr/axi_ad35xxr_ip.tcl` - TCL script to generate the Vivado IP-integrator project. Block Diagram @@ -98,9 +106,9 @@ Interface * - valid_in_dma_sec - Valid from a secondary DMAC if synchronization is needed. * - external_sync - - External synchronization flag from another axi_ad3552r IP. + - External synchronization flag from another axi_ad35xxr IP. * - sync_ext_device - - Start_sync external device to another axi_ad3552r IP. + - Start_sync external device to another _axi_ad35xxr IP. * - dac_sclk - Serial clock. * - dac_csn @@ -111,6 +119,9 @@ Interface - Serial data in from the DAC. * - sdio_t - I/O buffer control signal. + * - qspi_sel + - QSPI Mode Enable. High level enables quad SPI interface mode + (ad3552r and ad3551r). * - s_axi - Standard AXI Slave Memory Map interface. @@ -118,30 +129,34 @@ Detailed Architecture -------------------------------------------------------------------------------- .. image:: detailed_architecture.svg - :alt: AXI AD3552R detailed architecture + :alt: AXI AD3XXR detailed architecture Detailed Description -------------------------------------------------------------------------------- The top module instantiates: -* The axi_ad3552r interface module -* The axi_ad3552r core module +* The axi_ad35xxr interface module +* The axi_ad35xxr core module * The AXI handling interface -The axi_ad3552r_if has the state machine that controls the quad SPI interface. -The axi_ad3552r_core module instantiates 2 axi_ad3552r channel modules. +The axi_ad35xxr_if has the state machine that controls the SPI interface, +which can be Single SPI (Classic), Dual SPI, and Quad SPI. +The axi_ad35xxr_core module instantiates 2 ad35xxr channel modules even for +the ad35x1r cases. For the single channel and 12 bit accuracy cases, consider +the 16 LSBs -- The 4 LSBs of this word are 0's for the 12-bit accuracy. + Register Map -------------------------------------------------------------------------------- -For the AXI_AD3552R control used registers from DAC Common are: +For the AXI_AD3XXR control used registers from DAC Common are: .. hdl-regmap:: :name: AXI_AD3552R_DAC_COMMON -For the AXI_AD3552R control used registers from DAC Channel are: +For the AXI_AD35XXR control used registers from DAC Channel are: .. hdl-regmap:: :name: AXI_AD3552R_DAC_CHANNEL @@ -163,7 +178,7 @@ For reference, all the register map templates are: Design Guidelines -------------------------------------------------------------------------------- -The control of the chip is done through the AXI_AD3552R IP. +The control of the chip is done through the AXI_AD35XXR IP. The *DAC interface* must be connected to an IO buffer. @@ -190,8 +205,11 @@ Software Support References -------------------------------------------------------------------------------- -* HDL IP core at :git-hdl:`library/axi_ad3552r` -* HDL project at :git-hdl:`projects/ad3552r_evb` +* HDL IP core at :git-hdl:`dev_ad3542r:library/axi_ad35xxr` +* HDL project at :git-hdl:`dev_ad3542r:projects/ad35xxr_evb` * :adi:`AD3552R` +* :adi:`AD3551R` +* :adi:`AD3542R` +* :adi:`AD3541R` * :xilinx:`Zynq-7000 SoC Overview ` * :xilinx:`Zynq-7000 SoC Packaging and Pinout ` diff --git a/docs/projects/ad3552r_evb/index.rst b/docs/projects/ad3552r_evb/index.rst index 167c69beac..7299650719 100644 --- a/docs/projects/ad3552r_evb/index.rst +++ b/docs/projects/ad3552r_evb/index.rst @@ -8,10 +8,12 @@ Overview The :adi:`EVAL-AD3552R ` is an evaluation board for the :adi:`AD3552R `, a dual-channel, 16-bit fast precision -digital-to-analog converter (DAC). Each channel of the :adi:`AD3552R ` -is equipped with a different transimpedance amplifier: Channel 0 has a fast -amplifier that achieves the optimal dynamic performance and Channel 1 has a -precision amplifier that guarantees the optimal DC precision over temperature. +digital-to-analog converter (DAC). The same eval board can be used to evaluate +the :adi:`AD3551R `, the single channel part. Each channel of the +:adi:`AD3552R ` is equipped with a different transimpedance +amplifier: Channel 0 has a fast amplifier that achieves the optimal dynamic +performance and Channel 1 has a precision amplifier that guarantees the +optimal DC precision over temperature. The board allows testing all the output ranges of the DAC, waveform generation, power supply and reference options. @@ -25,6 +27,7 @@ Supported devices ------------------------------------------------------------------------------- - :adi:`AD3552R` +- :adi:`AD3551R` Supported carriers ------------------------------------------------------------------------------- @@ -66,7 +69,7 @@ added to the base address from HDL (see more at :ref:`architecture`). ==================== =============== Instance Zynq/Microblaze ==================== =============== -axi_ad3552r_dac 0x44A7_0000 +axi_ad35xxr_dac 0x44A7_0000 axi_dac_dma 0x44A3_0000 axi_clkgen 0x44B0_0000 ==================== =============== @@ -88,37 +91,37 @@ GPIOs - - Zynq-7000 - Zynq MP - * - ad3552r_resetn + * - ad35xxr_resetn - OUT - 38 - 92 - 116 - * - ad3552r_gpio_9 + * - ad35xxr_gpio_9 - INOUT - 37 - 91 - 115 - * - ad3552r_gpio_8 + * - ad35xxr_gpio_8 - INOUT - 36 - 90 - 114 - * - ad3552r_gpio_7 + * - ad35xxr_gpio_7 - INOUT - 35 - 89 - 113 - * - ad3552r_gpio_6 + * - ad35xxr_gpio_6 - INOUT - 34 - 88 - 112 - * - ad3552r_alertn + * - ad35xxr_alertn - INOUT - 33 - 87 - 111 - * - ad3552r_ldacn + * - ad35xxr_ldacn - INOUT - 32 - 86 @@ -151,8 +154,8 @@ the HDL repository, and then build the project as follows: .. code-block:: :linenos: - user@analog:~$ cd hdl/projects/ad3552r_evb/zed - user@analog:~/hdl/projects/ad3552r_evb/zed$ make + user@analog:~$ cd hdl/projects/ad35xxr_evb/zed + user@analog:~/hdl/projects/ad35xxr_evb/zed$ make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. @@ -170,6 +173,7 @@ Hardware related - Product datasheets: - :adi:`AD3552R` + - :adi:`AD3551R` - :adi:`UG-2217, User Guide | EVAL-AD3552R ` @@ -186,8 +190,8 @@ HDL related - Source code link - Documentation link - * - AXI_AD3552R - - :git-hdl:`library/axi_ad3552r` + * - AXI_AD35XXR + - :git-hdl:`dev_ad3542r:library/axi_ad35xxr` - :ref:`here ` * - AXI_CLKGEN - :git-hdl:`library/axi_clkgen` diff --git a/docs/regmap/adi_regmap_axi_ad3552r.txt b/docs/regmap/adi_regmap_axi_ad3552r.txt index 8e109f545f..9acc0901b8 100644 --- a/docs/regmap/adi_regmap_axi_ad3552r.txt +++ b/docs/regmap/adi_regmap_axi_ad3552r.txt @@ -68,6 +68,13 @@ Register address when the AD3552R is configured or stream start address when the FSM is in stream state. ENDFIELD +FIELD +[3:2] 0x00000000 +MULTI_IO_MODE +RW +Controls the SPI mode (0: Single SPI, 1: Dual SPI, 2: Quad SPI). +ENDFIELD + FIELD [1] 0x00000000 STREAM diff --git a/projects/ad3542r_evb/Readme.md b/projects/ad3542r_evb/Readme.md index a3cd8b3a25..32734cd341 100755 --- a/projects/ad3542r_evb/Readme.md +++ b/projects/ad3542r_evb/Readme.md @@ -2,7 +2,7 @@ Here are some pointers to help you: * [Board Product Page](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad3542r.html) - * Parts : [ AD3552R Dual Channel, 16-Bit, 33 MUPS, Multispan, Multi-IO SPI DAC ](https://www.analog.com/en/products/AD3542R.html) + * Parts : [ Dual Channel, 12-/16-Bit, 16 MUPS, Multispan, Multi-IO SPI DAC ](https://www.analog.com/en/products/AD3542R.html) * Project Doc: https://wiki.analog.com/resources/eval/user-guides/dac/eval-ad3542r * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/dac/eval-ad3542r * Linux Drivers: NA \ No newline at end of file diff --git a/projects/ad35xxr_evb/Readme.md b/projects/ad35xxr_evb/Readme.md index 4c92e827e6..a7205bbe84 100644 --- a/projects/ad35xxr_evb/Readme.md +++ b/projects/ad35xxr_evb/Readme.md @@ -1,8 +1,16 @@ -# AD3552R-EVB HDL Project +# AD35XXR-EVB HDL Project +# It supports both AD3552R and AD3542R Here are some pointers to help you: +* AD3552R: * [Board Product Page](https://www.analog.com/eval-ad3552r) * Parts : [ AD3552R Dual Channel, 16-Bit, 33 MUPS, Multispan, Multi-IO SPI DAC ](https://www.analog.com/en/products/ad3552r.html) * Project Doc: https://wiki.analog.com/resources/eval/user-guides/dac/ad3552r_eval_zed * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/dac/ad3552r_eval_zed - * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-dac/axi-ad3552r \ No newline at end of file + * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-dac/axi-ad3552r +* AD3442R: + * [Board Product Page](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad3542r.html) + * Parts : [ Dual Channel, 12-/16-Bit, 16 MUPS, Multispan, Multi-IO SPI DAC ](https://www.analog.com/en/products/AD3542R.html) + * Project Doc: https://wiki.analog.com/resources/eval/user-guides/dac/eval-ad3542r + * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/dac/eval-ad3542r + * Linux Drivers: NA \ No newline at end of file