diff --git a/docs/library/axi_ad3552r/index.rst b/docs/library/axi_ad3552r/index.rst index 91131d2c66..3dbe0f591b 100644 --- a/docs/library/axi_ad3552r/index.rst +++ b/docs/library/axi_ad3552r/index.rst @@ -1,29 +1,37 @@ .. _axi_ad3552r: -AXI AD3552R +AXI AD35XXR ================================================================================ .. hdl-component-diagram:: + :path: library/axi_ad35xxr + +The :git-hdl:`AXI AD3552R ` IP core can be used to +interface the :adi:`AD3552R`, :adi:`AD3551R`, :adi:`AD3542R`, and +:adi:`AD3541R`. :adi:`AD3552R` is a low drift, dual channel, ultra-fast, +16-bit accuracy, current output digital-to-analog converter (DAC) that can be +configured in multiple voltage span ranges, the :adi:`AD3551R` is the single +channel part. :adi:`AD3542R` is is a low drift, dual channel, ultra-fast, +12-/16-bit accuracy, voltage output digital-to-analog converter (DAC) that +can be configured in multiple voltage span ranges, the :adi:`AD3541R` is the +single channel part. -The :git-hdl:`AXI AD3552R ` IP core -can be used to interface the :adi:`AD3552R`, a low drift, ultra-fast, 16-bit -accuracy, current output digital-to-analog converter (DAC) that can be -configured in multiple voltage span ranges. Features -------------------------------------------------------------------------------- -* AXI-based configuration -* Vivado compatible -* 8b register read/write SDR/DDR -* 16b register read/write SDR/DDR -* data stream SDR/DDR ( clk_in/8 or clk_in/4 update rate) -* selectable input source: DMA/ADC/TEST_RAMP -* data out clock(SCLK) has clk_in/8 frequency when the converter is configured and - clk_in/2 when the converter is in stream mode -* the IP reference clock (clk_in) can have a maximum frequency of 132MHz -* the IP has multiple device synchronization capability when the DMA is set - as an input data source +* AXI-based configuration; +* Vivado compatible; +* 8b register read/write SDR/DDR; +* 16b register read/write SDR/DDR; +* Data stream SDR/DDR ( clk_in/8 or clk_in/4 update rate); +* Selectable input source: DMA/ADC/TEST_RAMP; +* Data out clock(SCLK) has clk_in/2 frequency for both configuration and streaming + mode; +* The IP reference clock (clk_in) can have a maximum frequency of 132MHz; +* The IP has multiple device synchronization capability when the DMA is set + as an input data source. + Files -------------------------------------------------------------------------------- @@ -33,19 +41,19 @@ Files * - Name - Description - * - :git-hdl:`library/axi_ad3552r/axi_ad3552r.v` + * - :git-hdl:`dev_ad3542r:library/axi_ad35xxr/axi_ad35xxr.v` - Verilog source for the AXI AD3552R. - * - :git-hdl:`library/axi_ad3552r/axi_ad3552r_channel.v` + * - :git-hdl:`dev_ad3542r:library/axi_ad35xxr/axi_ad35xxr_channel.v` - Verilog source for the AXI AD3552R channel. - * - :git-hdl:`library/axi_ad3552r/axi_ad3552r_core.v` + * - :git-hdl:`dev_ad3542r:library/axi_ad35xxr/axi_ad35xxr_core.v` - Verilog source for the AXI AD3552R core. - * - :git-hdl:`library/axi_ad3552r/axi_ad3552r_if.v` + * - :git-hdl:`dev_ad3542r:library/axi_ad35xxr/axi_ad35xxr_if.v` - Verilog source for the AD3552R interface module. - * - :git-hdl:`library/axi_ad3552r/axi_ad3552r_if_tb.v` + * - :git-hdl:`dev_ad3542r:library/axi_ad35xxr/axi_ad35xxr_if_tb.v` - Verilog source for the AD3552R interface module testbench. - * - :git-hdl:`library/axi_ad3552r/axi_ad3552r_if_tb` + * - :git-hdl:`dev_ad3542r:library/axi_ad35xxr/axi_ad35xxr_if_tb` - Setup script for the AD3552R interface module testbench. - * - :git-hdl:`library/axi_ad3552r/axi_ad3552r_ip.tcl` + * - :git-hdl:`dev_ad3542r:library/axi_ad35xxr/axi_ad35xxr_ip.tcl` - TCL script to generate the Vivado IP-integrator project. Block Diagram @@ -98,9 +106,9 @@ Interface * - valid_in_dma_sec - Valid from a secondary DMAC if synchronization is needed. * - external_sync - - External synchronization flag from another axi_ad3552r IP. + - External synchronization flag from another axi_ad35xxr IP. * - sync_ext_device - - Start_sync external device to another axi_ad3552r IP. + - Start_sync external device to another _axi_ad35xxr IP. * - dac_sclk - Serial clock. * - dac_csn @@ -111,6 +119,9 @@ Interface - Serial data in from the DAC. * - sdio_t - I/O buffer control signal. + * - qspi_sel + - QSPI Mode Enable. High level enables quad SPI interface mode + (ad3552r and ad3551r). * - s_axi - Standard AXI Slave Memory Map interface. @@ -118,30 +129,34 @@ Detailed Architecture -------------------------------------------------------------------------------- .. image:: detailed_architecture.svg - :alt: AXI AD3552R detailed architecture + :alt: AXI AD3XXR detailed architecture Detailed Description -------------------------------------------------------------------------------- The top module instantiates: -* The axi_ad3552r interface module -* The axi_ad3552r core module +* The axi_ad35xxr interface module +* The axi_ad35xxr core module * The AXI handling interface -The axi_ad3552r_if has the state machine that controls the quad SPI interface. -The axi_ad3552r_core module instantiates 2 axi_ad3552r channel modules. +The axi_ad35xxr_if has the state machine that controls the SPI interface, +which can be Single SPI (Classic), Dual SPI, and Quad SPI. +The axi_ad35xxr_core module instantiates 2 ad35xxr channel modules even for +the ad35x1r cases. For the single channel and 12 bit accuracy cases, consider +the 16 LSBs -- The 4 LSBs of this word are 0's for the 12-bit accuracy. + Register Map -------------------------------------------------------------------------------- -For the AXI_AD3552R control used registers from DAC Common are: +For the AXI_AD3XXR control used registers from DAC Common are: .. hdl-regmap:: :name: AXI_AD3552R_DAC_COMMON -For the AXI_AD3552R control used registers from DAC Channel are: +For the AXI_AD35XXR control used registers from DAC Channel are: .. hdl-regmap:: :name: AXI_AD3552R_DAC_CHANNEL @@ -163,7 +178,7 @@ For reference, all the register map templates are: Design Guidelines -------------------------------------------------------------------------------- -The control of the chip is done through the AXI_AD3552R IP. +The control of the chip is done through the AXI_AD35XXR IP. The *DAC interface* must be connected to an IO buffer. @@ -190,8 +205,11 @@ Software Support References -------------------------------------------------------------------------------- -* HDL IP core at :git-hdl:`library/axi_ad3552r` -* HDL project at :git-hdl:`projects/ad3552r_evb` +* HDL IP core at :git-hdl:`dev_ad3542r:library/axi_ad35xxr` +* HDL project at :git-hdl:`dev_ad3542r:projects/ad35xxr_evb` * :adi:`AD3552R` +* :adi:`AD3551R` +* :adi:`AD3542R` +* :adi:`AD3541R` * :xilinx:`Zynq-7000 SoC Overview ` * :xilinx:`Zynq-7000 SoC Packaging and Pinout ` diff --git a/docs/projects/ad3552r_evb/index.rst b/docs/projects/ad3552r_evb/index.rst index c46f14c825..93a73ac54e 100644 --- a/docs/projects/ad3552r_evb/index.rst +++ b/docs/projects/ad3552r_evb/index.rst @@ -6,12 +6,14 @@ AD3552R-EVB HDL project Overview ------------------------------------------------------------------------------- -The :adi:`EVAL-AD3552R` is an evaluation board for the -:adi:`AD3552R`, a dual-channel, 16-bit fast precision -digital-to-analog converter (DAC). Each channel of the :adi:`AD3552R` -is equipped with a different transimpedance amplifier: Channel 0 has a fast -amplifier that achieves the optimal dynamic performance and Channel 1 has a -precision amplifier that guarantees the optimal DC precision over temperature. +The :adi:`EVAL-AD3552R ` is an evaluation board for the +:adi:`AD3552R `, a dual-channel, 16-bit fast precision +digital-to-analog converter (DAC). The same eval board can be used to evaluate +the :adi:`AD3551R `, the single channel part. Each channel of the +:adi:`AD3552R ` is equipped with a different transimpedance +amplifier: Channel 0 has a fast amplifier that achieves the optimal dynamic +performance and Channel 1 has a precision amplifier that guarantees the +optimal DC precision over temperature. The board allows testing all the output ranges of the DAC, waveform generation, power supply and reference options. @@ -24,7 +26,8 @@ Supported boards Supported devices ------------------------------------------------------------------------------- -- :adi:`AD3552R` +- :adi:`AD3552R` +- :adi:`AD3551R` Supported carriers ------------------------------------------------------------------------------- @@ -66,9 +69,9 @@ added to the base address from HDL (see more at :ref:`architecture cpu-intercon- ==================== =============== Instance Zynq/Microblaze ==================== =============== -axi_ad3552r_dac 0x44A7_0000 -axi_dac_dma 0x44A3_0000 -axi_clkgen 0x44B0_0000 +axi_ad35xxr_dac 0x44A7_0000 +axi_dac_dma 0x44A3_0000 +axi_clkgen 0x44B0_0000 ==================== =============== GPIOs @@ -88,37 +91,37 @@ GPIOs - - Zynq-7000 - Zynq MP - * - ad3552r_resetn + * - ad35xxr_resetn - OUT - 38 - 92 - 116 - * - ad3552r_gpio_9 + * - ad35xxr_gpio_9 - INOUT - 37 - 91 - 115 - * - ad3552r_gpio_8 + * - ad35xxr_gpio_8 - INOUT - 36 - 90 - 114 - * - ad3552r_gpio_7 + * - ad35xxr_gpio_7 - INOUT - 35 - 89 - 113 - * - ad3552r_gpio_6 + * - ad35xxr_gpio_6 - INOUT - 34 - 88 - 112 - * - ad3552r_alertn + * - ad35xxr_alertn - INOUT - 33 - 87 - 111 - * - ad3552r_ldacn + * - ad35xxr_ldacn - INOUT - 32 - 86 @@ -150,8 +153,8 @@ the HDL repository, and then build the project as follows: .. shell:: - $cd hdl/projects/ad3552r_evb/zed - $make + user@analog:~$ cd hdl/projects/ad35xxr_evb/zed + user@analog:~/hdl/projects/ad35xxr_evb/zed$ make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. @@ -168,8 +171,8 @@ Hardware related - Product datasheets: - - :adi:`AD3552R` - - :adi:`EVAL-AD3552R` + - :adi:`AD3552R` + - :adi:`AD3551R` - :adi:`UG-2217, User Guide | EVAL-AD3552R ` @@ -186,9 +189,9 @@ HDL related - Source code link - Documentation link - * - AXI_AD3552R - - :git-hdl:`library/axi_ad3552r` - - :ref:`axi_ad3552r` + * - AXI_AD35XXR + - :git-hdl:`dev_ad3542r:library/axi_ad35xxr` + - :ref:`here ` * - AXI_CLKGEN - :git-hdl:`library/axi_clkgen` - :ref:`axi_clkgen` diff --git a/docs/regmap/adi_regmap_axi_ad3552r.txt b/docs/regmap/adi_regmap_axi_ad3552r.txt index 8e109f545f..9acc0901b8 100644 --- a/docs/regmap/adi_regmap_axi_ad3552r.txt +++ b/docs/regmap/adi_regmap_axi_ad3552r.txt @@ -68,6 +68,13 @@ Register address when the AD3552R is configured or stream start address when the FSM is in stream state. ENDFIELD +FIELD +[3:2] 0x00000000 +MULTI_IO_MODE +RW +Controls the SPI mode (0: Single SPI, 1: Dual SPI, 2: Quad SPI). +ENDFIELD + FIELD [1] 0x00000000 STREAM diff --git a/library/axi_ad3552r/Makefile b/library/axi_ad35xxr/Makefile old mode 100755 new mode 100644 similarity index 85% rename from library/axi_ad3552r/Makefile rename to library/axi_ad35xxr/Makefile index 3970c74819..36b5ff8ff1 --- a/library/axi_ad3552r/Makefile +++ b/library/axi_ad35xxr/Makefile @@ -4,7 +4,7 @@ ## Auto-generated, do not modify! #################################################################################### -LIBRARY_NAME := axi_ad3552r +LIBRARY_NAME := axi_ad35xxr GENERIC_DEPS += ../common/ad_addsub.v GENERIC_DEPS += ../common/ad_dds.v @@ -20,16 +20,16 @@ GENERIC_DEPS += ../common/up_dac_channel.v GENERIC_DEPS += ../common/up_dac_common.v GENERIC_DEPS += ../common/up_xfer_cntrl.v GENERIC_DEPS += ../common/up_xfer_status.v -GENERIC_DEPS += axi_ad3552r.v -GENERIC_DEPS += axi_ad3552r_channel.v -GENERIC_DEPS += axi_ad3552r_core.v -GENERIC_DEPS += axi_ad3552r_if.v +GENERIC_DEPS += axi_ad35xxr.v +GENERIC_DEPS += axi_ad35xxr_channel.v +GENERIC_DEPS += axi_ad35xxr_core.v +GENERIC_DEPS += axi_ad35xxr_if.v XILINX_DEPS += ../xilinx/common/ad_mul.v XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc -XILINX_DEPS += axi_ad3552r_ip.tcl +XILINX_DEPS += axi_ad35xxr_ip.tcl include ../scripts/library.mk diff --git a/library/axi_ad3552r/axi_ad3552r.v b/library/axi_ad35xxr/axi_ad35xxr.v old mode 100755 new mode 100644 similarity index 93% rename from library/axi_ad3552r/axi_ad3552r.v rename to library/axi_ad35xxr/axi_ad35xxr.v index 0685c511d9..8796ebdfd3 --- a/library/axi_ad3552r/axi_ad3552r.v +++ b/library/axi_ad35xxr/axi_ad35xxr.v @@ -35,7 +35,7 @@ `timescale 1ns/100ps -module axi_ad3552r #( +module axi_ad35xxr #( parameter ID = 0, parameter FPGA_TECHNOLOGY = 0, @@ -66,7 +66,8 @@ module axi_ad3552r #( output dac_csn, input [ 3:0] sdio_i, output [ 3:0] sdio_o, - output sdio_t, + output [ 3:0] sdio_t, + output qspi_sel, // sync transfer between 2 DAC'S @@ -118,7 +119,8 @@ module axi_ad3552r #( wire [ 7:0] address; wire [23:0] data_read; wire [23:0] data_write; - wire ddr_sdr_n; + wire [ 1:0] multi_io_mode; + wire sdr_ddr_n; wire symb_8_16b; wire transfer_data; wire stream; @@ -129,11 +131,12 @@ module axi_ad3552r #( // signal name changes - assign up_clk = s_axi_aclk; - assign up_rstn = s_axi_aresetn; + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + assign qspi_sel = (multi_io_mode == 2'd2); //2'd2 is quad spi in multi_io_mode reg // device interface - axi_ad3552r_if axi_ad3552r_interface ( + axi_ad35xxr_if axi_ad35xxr_interface ( .clk_in(dac_clk), .reset_in(dac_rst_s), .dac_data(dac_data), @@ -143,6 +146,7 @@ module axi_ad3552r #( .address(address), .data_read(data_read), .data_write(data_write), + .multi_io_mode(multi_io_mode), .sdr_ddr_n(sdr_ddr_n), .symb_8_16b(symb_8_16b), .transfer_data(transfer_data), @@ -158,7 +162,7 @@ module axi_ad3552r #( .sdio_t(sdio_t)); // core - axi_ad3552r_core #( + axi_ad35xxr_core #( .ID(ID), .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), .FPGA_FAMILY(FPGA_FAMILY), @@ -168,7 +172,7 @@ module axi_ad3552r #( .DDS_TYPE(DDS_TYPE), .DDS_CORDIC_DW(DDS_CORDIC_DW), .DDS_CORDIC_PHASE_DW(DDS_CORDIC_PHASE_DW) - ) axi_ad3552r_up_core ( + ) axi_ad35xxr_up_core ( .dac_clk(dac_clk), .dac_rst(dac_rst_s), .adc_data_in_a(data_in_a), @@ -183,6 +187,7 @@ module axi_ad3552r #( .address(address), .data_read(data_read), .data_write(data_write), + .multi_io_mode(multi_io_mode), .sdr_ddr_n(sdr_ddr_n), .symb_8_16b(symb_8_16b), .transfer_data(transfer_data), diff --git a/library/axi_ad3552r/axi_ad3552r_channel.v b/library/axi_ad35xxr/axi_ad35xxr_channel.v old mode 100755 new mode 100644 similarity index 99% rename from library/axi_ad3552r/axi_ad3552r_channel.v rename to library/axi_ad35xxr/axi_ad35xxr_channel.v index 542806f85f..eaa7b8e9fe --- a/library/axi_ad3552r/axi_ad3552r_channel.v +++ b/library/axi_ad35xxr/axi_ad35xxr_channel.v @@ -35,9 +35,9 @@ `timescale 1ns/100ps -module axi_ad3552r_channel #( +module axi_ad35xxr_channel #( - parameter CHANNEL_ID = 32'h0, + parameter CHANNEL_ID = 32'h0, parameter DDS_DISABLE = 0, parameter DDS_TYPE = 1, parameter DDS_CORDIC_DW = 16, diff --git a/library/axi_ad3552r/axi_ad3552r_core.v b/library/axi_ad35xxr/axi_ad35xxr_core.v old mode 100755 new mode 100644 similarity index 96% rename from library/axi_ad3552r/axi_ad3552r_core.v rename to library/axi_ad35xxr/axi_ad35xxr_core.v index 583f79b112..3267cc7076 --- a/library/axi_ad3552r/axi_ad3552r_core.v +++ b/library/axi_ad35xxr/axi_ad35xxr_core.v @@ -35,7 +35,7 @@ `timescale 1ns/100ps -module axi_ad3552r_core #( +module axi_ad35xxr_core #( parameter ID = 0, parameter FPGA_TECHNOLOGY = 0, parameter FPGA_FAMILY = 0, @@ -67,6 +67,7 @@ module axi_ad3552r_core #( input if_busy, input [23:0] data_read, output [23:0] data_write, + output [ 1:0] multi_io_mode, output sdr_ddr_n, output symb_8_16b, output transfer_data, @@ -118,6 +119,7 @@ module axi_ad3552r_core #( assign data_write = dac_data_control[23:0]; assign transfer_data = dac_control[0]; assign stream = dac_control[1]; + assign multi_io_mode = dac_control[3:2]; assign address = dac_control[31:24]; // processor read interface @@ -136,13 +138,13 @@ module axi_ad3552r_core #( // DAC CHANNEL 0 - axi_ad3552r_channel #( + axi_ad35xxr_channel #( .CHANNEL_ID(0), .DDS_DISABLE(DDS_DISABLE), .DDS_TYPE(DDS_TYPE), .DDS_CORDIC_DW(DDS_CORDIC_DW), .DDS_CORDIC_PHASE_DW(DDS_CORDIC_PHASE_DW) - ) axi_ad3552r_channel_0 ( + ) axi_ad35xxr_channel_0 ( .dac_clk(dac_clk), .dac_rst(dac_rst_s), .dac_data_valid(dac_valid_channel_0), @@ -167,13 +169,13 @@ module axi_ad3552r_core #( // DAC CHANNEL 1 - axi_ad3552r_channel #( + axi_ad35xxr_channel #( .CHANNEL_ID(1), .DDS_DISABLE(DDS_DISABLE), .DDS_TYPE(DDS_TYPE), .DDS_CORDIC_DW(DDS_CORDIC_DW), .DDS_CORDIC_PHASE_DW(DDS_CORDIC_PHASE_DW) - ) axi_ad3552r_channel_1( + ) axi_ad35xxr_channel_1( .dac_clk(dac_clk), .dac_rst(dac_rst_s), .dac_data_valid(dac_valid_channel_1), @@ -205,7 +207,7 @@ module axi_ad3552r_core #( .SPEED_GRADE(SPEED_GRADE), .DEV_PACKAGE(DEV_PACKAGE), .COMMON_ID(6'h00) - ) axi_ad3552r_common_core ( + ) axi_ad35xxr_common_core ( .mmcm_rst(), .dac_clk(dac_clk), .dac_rst(dac_rst_s), diff --git a/library/axi_ad3552r/axi_ad3552r_if.v b/library/axi_ad35xxr/axi_ad35xxr_if.v old mode 100755 new mode 100644 similarity index 54% rename from library/axi_ad3552r/axi_ad3552r_if.v rename to library/axi_ad35xxr/axi_ad35xxr_if.v index cf4fa61800..d1e24a37b9 --- a/library/axi_ad3552r/axi_ad3552r_if.v +++ b/library/axi_ad35xxr/axi_ad35xxr_if.v @@ -35,9 +35,9 @@ `timescale 1ns/100ps -module axi_ad3552r_if ( +module axi_ad35xxr_if ( - input clk_in, // 120MHz + input clk_in, // 132MHz input reset_in, input [31:0] dac_data, input dac_data_valid, @@ -46,6 +46,7 @@ module axi_ad3552r_if ( input [ 7:0] address, input [23:0] data_write, + input [ 1:0] multi_io_mode, input sdr_ddr_n, input symb_8_16b, input transfer_data, @@ -63,7 +64,7 @@ module axi_ad3552r_if ( output reg csn, input [ 3:0] sdio_i, output [ 3:0] sdio_o, - output sdio_t + output [ 3:0] sdio_t ); wire transfer_data_s; @@ -72,17 +73,25 @@ module axi_ad3552r_if ( wire dac_data_valid_synced; wire external_sync_s; - reg [55:0] transfer_reg = 56'h0; - reg [15:0] counter = 16'h0; + reg [55:0] transfer_reg_single = 0; + reg [55:0] transfer_reg_dual = 0; + reg [55:0] transfer_reg_quad = 0; + + reg [15:0] counter = 0; + reg wa_cp = 1'b0; + reg [ 3:0] tf_cp = 4'h0; + reg [ 3:0] st_cp = 4'h0; reg [ 2:0] transfer_state = 0; reg [ 2:0] transfer_state_next = 0; + reg [ 2:0] transfer_state_p = 0; + reg [ 2:0] transfer_state_prev = 0; reg cycle_done = 1'b0; reg transfer_step = 1'b0; reg sclk_ddr = 1'b0; reg full_speed = 1'b0; reg transfer_data_d = 1'b0; reg transfer_data_dd = 1'b0; - reg [ 3:0] valid_captured_d = 4'b0; + reg [ 3:0] valid_captured_d = 4'b0; //why 4 registers? It is using up to the second reg data_r_wn = 1'b0; reg valid_captured = 1'b0; reg start_transfer = 1'b0; @@ -108,7 +117,7 @@ module axi_ad3552r_if ( // start the data stream transfer after valid has been captured assign start_synced = valid_captured_d[1] & start_transfer & stream; - assign sync_ext_device = start_synced ; + assign sync_ext_device = start_synced; // use dac_data valid from an external source only if external_sync_arm_reg is 1 @@ -165,6 +174,7 @@ module axi_ad3552r_if ( transfer_state <= IDLE; end else begin transfer_state <= transfer_state_next; + transfer_state_p <= transfer_state_prev; end end @@ -175,6 +185,7 @@ module axi_ad3552r_if ( IDLE : begin // goes in to the next state only if the control is to transfer register or synced transfer(if it's armed in software) transfer_state_next = ((transfer_data_s == 1'b1 && stream == 1'b0) || (start_synced == 1'b1 && external_sync_s)) ? CS_LOW : IDLE; + transfer_state_prev = IDLE; csn = 1'b1; transfer_step = 0; cycle_done = 0; @@ -183,91 +194,160 @@ module axi_ad3552r_if ( // brings CS down // loads all configuration // puts data on the SDIO pins - // needs 5 ns before risedge of the clock + // needs 5 ns before the rising edge of the clock (t2) transfer_state_next = WRITE_ADDRESS; + transfer_state_prev = CS_LOW; csn = 1'b0; transfer_step = 0; cycle_done = 0; end WRITE_ADDRESS : begin // writes the address - // it works either at full speed (60 MHz) when streaming or normal - // speed (15 MHz) + // 8-bit addressing requires 8 clock cycles because dual mode only support + // the address on a single lane + // step requires at least (t1)ns + // it works either at full speed (66 MHz) when streaming or + // normal at speed (16.5 MHz) // full speed - 2 clock cycles // half speed 8 clock cycles - cycle_done = full_speed ? (counter == 16'h3) : (counter == 16'hf); - transfer_state_next = cycle_done ? (stream ? STREAM : TRANSFER_REGISTER) : WRITE_ADDRESS ; + cycle_done = wa_cp; //It is considering 8 bit address only + transfer_state_next = cycle_done ? (stream ? STREAM : TRANSFER_REGISTER) : WRITE_ADDRESS; + transfer_state_prev = WRITE_ADDRESS; csn = 1'b0; // in streaming, change data on falledge. On regular transfer, change data on negedge. - //A single step should be done for 8 bit addressing - transfer_step = full_speed ? (counter[0]== 1'h1) : ((counter[4:0] == 5'h5)); + transfer_step = full_speed ? counter[0] : ((counter[2:0] == 3'h5)); end TRANSFER_REGISTER : begin - // always works at 15 MHz + // always works at 15 MHz due to the DAC limitation // can be DDR or SDR - cycle_done = sdr_ddr_n ? (symb_8_16b ? (counter == 16'h10) : (counter == 16'h20)) : - (symb_8_16b ? (counter == 16'h09) : (counter == 16'h11)); + // counter is based on the "Clock Cycles Required to Transfer One Byte" table in the doc + cycle_done = (sdr_ddr_n | data_r_wn) ? (symb_8_16b ? tf_cp[0] : tf_cp[1]): + (symb_8_16b ? tf_cp[2] : tf_cp[3]); + //DDR requires one more cycle to fulfill t3 + //DDR is only allowed in writte operations + //It is necessary to keep sclk low for the last bit transfer_state_next = cycle_done ? CS_HIGH : TRANSFER_REGISTER; csn = 1'b0; // in DDR mode, change data on falledge - transfer_step = sdr_ddr_n ? (counter[2:0] == 3'h0) : (counter[1:0] == 2'h0); + transfer_step = (sdr_ddr_n | data_r_wn) ? (counter[2:0] == 3'h5) : ((counter[1:0] == 2'h0) && (transfer_state_p != WRITE_ADDRESS)); + transfer_state_prev = TRANSFER_REGISTER; end STREAM : begin // can be DDR or SDR - // in DDR mode needs to be make sure the clock and data is shifted by 2 ns - cycle_done = stream ? (sdr_ddr_n ? (counter == 16'h0f) : (counter == 16'h7)): - (sdr_ddr_n ? (counter == 16'h10) : (counter == 16'h7)); + // in DDR mode needs to be make sure the clock and data is shifted by 2 ns (t7 and t8) + // the last word in the stream needs one more clock cycle to guarantee t3 + cycle_done = stream ? ((sdr_ddr_n | data_r_wn) ? st_cp[0] : st_cp[1]): + ((sdr_ddr_n | data_r_wn) ? st_cp[2] : st_cp[3]); transfer_state_next = (stream && external_sync_s) ? STREAM: ((cycle_done || external_sync_s == 1'b0) ? CS_HIGH :STREAM); + transfer_state_prev = STREAM; csn = 1'b0; - transfer_step = sdr_ddr_n ? counter[0] : 1'b1; + transfer_step = (sdr_ddr_n | data_r_wn) ? counter[0] : 1'b1; end CS_HIGH : begin cycle_done = 1'b1; transfer_state_next = cycle_done ? IDLE : CS_HIGH; + transfer_state_prev = CS_HIGH; csn = 1'b1; transfer_step = 0; end default : begin cycle_done = 0; transfer_state_next = IDLE; + transfer_state_prev = IDLE; csn = 1'b1; transfer_step = 0; end endcase end + // counter relies on a 132 Mhz clock or slower // counter is used to time all states // depends on number of clock cycles per phase always @(posedge clk_in) begin if (transfer_state == IDLE || reset_in == 1'b1) begin - counter <= 'b0; + counter <= 0; + wa_cp <= 1'b0; + tf_cp[0] <= 1'b0; + tf_cp[1] <= 1'b0; + tf_cp[2] <= 1'b0; + tf_cp[3] <= 1'b0; + st_cp[0] <= 1'b0; + st_cp[1] <= 1'b0; + st_cp[2] <= 1'b0; + st_cp[3] <= 1'b0; end else if (transfer_state == WRITE_ADDRESS | transfer_state == TRANSFER_REGISTER | transfer_state == STREAM) begin if (cycle_done) begin - counter <= 0; + counter <= 0; + wa_cp <= 1'b0; + tf_cp[0] <= 1'b0; + tf_cp[1] <= 1'b0; + tf_cp[2] <= 1'b0; + tf_cp[3] <= 1'b0; + st_cp[0] <= 1'b0; + st_cp[1] <= 1'b0; + st_cp[2] <= 1'b0; + st_cp[3] <= 1'b0; end else begin - counter <= counter + 1; + counter <= counter + 1; + if (multi_io_mode == 2'h1) begin //dual SPI + wa_cp <= full_speed ? (counter == 16'he) : (counter == 16'h3e); + tf_cp[0] <= (counter == 16'h1f); + tf_cp[1] <= (counter == 16'h3f); + tf_cp[2] <= (counter == 16'h10); + tf_cp[3] <= (counter == 16'h20); + st_cp[0] <= (counter == 16'h1e); + st_cp[1] <= (counter == 16'he); + st_cp[2] <= (counter == 16'h1f); + st_cp[3] <= (counter == 16'hf); + end else if (multi_io_mode == 2'h2) begin //Quad SPI + wa_cp <= full_speed ? (counter == 16'h2) : (counter == 16'he); + tf_cp[0] <= (counter == 16'he); + tf_cp[1] <= (counter == 16'h1f); + tf_cp[2] <= (counter == 16'h8); + tf_cp[3] <= (counter == 16'h10); + st_cp[0] <= (counter == 16'he); + st_cp[1] <= (counter == 16'h6); + st_cp[2] <= (counter == 16'hf); + st_cp[3] <= (counter == 16'h7); + end else begin //Any other case is classic SPI + wa_cp <= full_speed ? (counter == 16'he) : (counter == 16'h3e); + tf_cp[0] <= (counter == 16'h3f); + tf_cp[1] <= (counter == 16'h7f); + tf_cp[2] <= (counter == 16'h1f); + tf_cp[3] <= (counter == 16'h3f); + st_cp[0] <= (counter == 16'h3e); + st_cp[1] <= (counter == 16'h1e); + st_cp[2] <= (counter == 16'h3f); + st_cp[3] <= (counter == 16'h1f); + end end end end always @(negedge clk_in) begin - if (transfer_state == STREAM | transfer_state == WRITE_ADDRESS) begin - sclk_ddr <= !sclk_ddr; + if (transfer_state == STREAM | transfer_state == TRANSFER_REGISTER | transfer_state == WRITE_ADDRESS) begin + if (cycle_done) begin + sclk_ddr <= 0; + end else begin + sclk_ddr <= !sclk_ddr; + end end else begin sclk_ddr <= 0; end end - // selection between 60 MHz and 15 MHz - - assign sclk = full_speed ? (sdr_ddr_n ? counter[0] : sclk_ddr) : counter[2]; + // 66MHz for full speed + // 16.5 MHz for normal speed + // selection between 66 MHz and 16.5 MHz clocks for the SCLK + // DDR mode requires a phase shift for the t7 and t8 + assign sclk = full_speed ? ((sdr_ddr_n | data_r_wn) ? counter[0] : sclk_ddr) : counter[2]; always @(posedge clk_in) begin if (transfer_state == CS_LOW) begin data_r_wn <= address[7]; end else if (transfer_state == CS_HIGH) begin - data_r_wn <=1'b0; + data_r_wn <= 1'b0; end if (transfer_state == STREAM) begin if (cycle_done == 1'b1) begin @@ -281,21 +361,49 @@ module axi_ad3552r_if ( if (transfer_state == CS_LOW) begin full_speed = stream; if(stream) begin - transfer_reg <= {address,dac_data_int, 16'h0}; + transfer_reg_single <= {address,dac_data_int, {16{1'b0}}}; + transfer_reg_dual <= {address,dac_data_int, {16{1'b0}}}; + transfer_reg_quad <= {address,dac_data_int, {16{1'b0}}}; end else begin - transfer_reg <= {address,data_write, 24'h0}; + transfer_reg_single <= {address,data_write, {24{1'b0}}}; + transfer_reg_dual <= {address,data_write, {24{1'b0}}}; + transfer_reg_quad <= {address,data_write, {24{1'b0}}}; end end else if ((transfer_state == STREAM & cycle_done) || (transfer_state != STREAM && transfer_state_next == STREAM)) begin - transfer_reg <= {dac_data_int, 24'h0}; + transfer_reg_single <= {dac_data_int, {24{1'b0}}}; + transfer_reg_dual <= {dac_data_int, {24{1'b0}}}; + transfer_reg_quad <= {dac_data_int, {24{1'b0}}}; end else if (transfer_step && transfer_state != CS_HIGH) begin - transfer_reg <= {transfer_reg[51:0], sdio_i}; + if (multi_io_mode == 2'h2) begin //Quad SPI + transfer_reg_quad <= {transfer_reg_quad[51:0], sdio_i}; + end else if ((multi_io_mode == 2'h0 || multi_io_mode == 2'h3)) begin + transfer_reg_single <= {transfer_reg_single[54:0], sdio_i[1]}; + end else begin //Dual SPI + if (transfer_state == WRITE_ADDRESS) begin + transfer_reg_dual <= {transfer_reg_dual[54:0], sdio_i[0]}; + end else begin + transfer_reg_dual <= {transfer_reg_dual[53:0], sdio_i[1:0]}; + end + end end if (transfer_state == CS_HIGH) begin if (symb_8_16b == 1'b0) begin - data_read <= {8'h0,transfer_reg[15:0]}; + if (multi_io_mode == 2'h2) begin //Quad SPI + data_read <= {8'h0, transfer_reg_quad[15:0]}; + end else if((multi_io_mode == 2'h0 || multi_io_mode == 2'h3)) begin + data_read <= {8'h0, transfer_reg_single[15:0]}; + end else begin + data_read <= {8'h0, transfer_reg_dual[15:0]}; + end end else begin - data_read <= {16'h0,transfer_reg[7:0]}; + if (multi_io_mode == 2'h2) begin //Quad SPI + data_read <= {16'h0, transfer_reg_quad[7:0]}; + end else if((multi_io_mode == 2'h0 || multi_io_mode == 2'h3)) begin //Classic SPI + data_read <= {16'h0, transfer_reg_single[7:0]}; + end else begin //dual SPI + data_read <= {16'h0, transfer_reg_dual[7:0]}; + end end end else begin data_read <= data_read; @@ -310,7 +418,13 @@ module axi_ad3552r_if ( // address[7] is r_wn : depends also on the state machine, input only when // in TRANSFER register mode - assign sdio_t = (data_r_wn & transfer_state == TRANSFER_REGISTER); - assign sdio_o = transfer_reg[55:52]; + assign sdio_t[0] = (~(|multi_io_mode)) ? 1'b0 : (data_r_wn && transfer_state == TRANSFER_REGISTER); //for the Single SPI case + assign sdio_t[3:1] = (~(|multi_io_mode)) ? 3'hf : {3{(data_r_wn && transfer_state == TRANSFER_REGISTER)}}; //high-impedance for the Single SPI case + + //multi_io_mode == 0xh3 is undefined, so the Classic SPI is chosen + assign sdio_o = (multi_io_mode == 2'h2) ? transfer_reg_quad[55:52] : + ((multi_io_mode == 2'h0 || multi_io_mode == 2'h3) ? {3'h0, transfer_reg_single[55]} : + ((transfer_state == WRITE_ADDRESS) ? {3'h0, transfer_reg_dual[55]} : + {2'h0, transfer_reg_dual[55:54]})); endmodule diff --git a/library/axi_ad3552r/axi_ad3552r_if_tb b/library/axi_ad35xxr/axi_ad35xxr_if_tb similarity index 72% rename from library/axi_ad3552r/axi_ad3552r_if_tb rename to library/axi_ad35xxr/axi_ad35xxr_if_tb index 485bf965a2..d59bd3c09d 100755 --- a/library/axi_ad3552r/axi_ad3552r_if_tb +++ b/library/axi_ad35xxr/axi_ad35xxr_if_tb @@ -1,7 +1,7 @@ #!/bin/bash SOURCE="$0.v" -SOURCE+=" axi_ad3552r_if.v" +SOURCE+=" axi_ad35xxr_if.v" cd `dirname $0` source ../common/tb/run_tb.sh diff --git a/library/axi_ad3552r/axi_ad3552r_if_tb.v b/library/axi_ad35xxr/axi_ad35xxr_if_tb.v old mode 100755 new mode 100644 similarity index 52% rename from library/axi_ad3552r/axi_ad3552r_if_tb.v rename to library/axi_ad35xxr/axi_ad35xxr_if_tb.v index bd03178e3b..74a56f8186 --- a/library/axi_ad3552r/axi_ad3552r_if_tb.v +++ b/library/axi_ad35xxr/axi_ad35xxr_if_tb.v @@ -35,8 +35,8 @@ `timescale 1ns/100ps -module axi_ad3552r_if_tb; - parameter VCD_FILE = "axi_ad3552r_if_tb.vcd"; +module axi_ad35xxr_if_tb; + parameter VCD_FILE = "axi_ad35xxr_if_tb.vcd"; `define TIMEOUT 9000 `include "../common/tb/tb_base.v" @@ -47,16 +47,17 @@ module axi_ad3552r_if_tb; wire dac_data_ready; wire [ 3:0] sdio_i; wire [ 3:0] sdio_o; - wire sdio_t; + wire [ 3:0] sdio_t; wire [31:0] dac_data_final; wire [ 3:0] readback_data_shift; - wire [ 4:0] data_increment_valid; + wire [ 5:0] data_increment_valid; wire if_busy; reg [ 7:0] address_write = 8'b0; reg dac_clk = 1'b0; reg reset_in = 1'b1; reg transfer_data = 1'b0; + reg [ 1:0] multi_io_mode = 2'h1; reg sdr_ddr_n = 1'b1; reg reg_8b_16bn = 1'b0; reg stream = 1'b0; @@ -64,119 +65,291 @@ module axi_ad3552r_if_tb; reg dac_data_valid = 1'b0; reg [ 3:0] shift_count = 4'b0; reg [31:0] transfer_reg = 32'h89abcdef; - reg [ 4:0] valid_counter = 5'b0; + reg [ 5:0] valid_counter = 6'b0; reg [31:0] dac_data = 32'b0; - always #4 dac_clk <= ~dac_clk; + always #3.8 dac_clk <= ~dac_clk; initial begin #100 reset_in = 1'b0; // Write 8 bit SDR + // Classic SPI + + // wait (if_busy == 1'b0); + // address_write = 8'h2c; + // data_write = 24'hab0000; + // multi_io_mode = 2'h0; + // sdr_ddr_n = 1'b1; + // reg_8b_16bn = 1'b1; + // stream = 1'b0; + // #500 transfer_data = 1'b1; + // #40 transfer_data = 1'b0; + // Read 8 bit SDR + // Dual SPI + + // wait (if_busy == 1'b0); + // address_write = 8'hac; + // data_write = 24'h000000; + // multi_io_mode = 2'h1; + // sdr_ddr_n = 1'b1; + // reg_8b_16bn = 1'b1; + // stream = 1'b0; + // #500 transfer_data = 1'b1; + // #40 transfer_data = 1'b0; + + // Write 8 bit SDR + // Quad SPI + + wait (if_busy == 1'b0); address_write = 8'h2c; data_write = 24'hab0000; + multi_io_mode = 2'h2; sdr_ddr_n = 1'b1; reg_8b_16bn = 1'b1; stream = 1'b0; #500 transfer_data = 1'b1; - #100 transfer_data = 1'b0; + #40 transfer_data = 1'b0; // Read 8 bit SDR + // Quad SPI + wait (if_busy == 1'b0); address_write = 8'hac; data_write = 24'h000000; + multi_io_mode = 2'h2; sdr_ddr_n = 1'b1; reg_8b_16bn = 1'b1; stream = 1'b0; #500 transfer_data = 1'b1; - #100 transfer_data = 1'b0; + #40 transfer_data = 1'b0; + + // Write 16 bit SDR + // Dual SPI + + // wait (if_busy == 1'b0); + // address_write = 8'h2c; + // data_write = 24'h123400; + // multi_io_mode = 2'h1; + // sdr_ddr_n = 1'b1; + // reg_8b_16bn = 1'b0; + // stream = 1'b0; + // #500 transfer_data = 1'b1; + // #40 transfer_data = 1'b0; + + // Read 16 bit SDR + // Classic SPI + + // wait (if_busy == 1'b0); + // address_write = 8'hac; + // data_write = 24'h000000; + // multi_io_mode = 2'h0; + // sdr_ddr_n = 1'b1; + // reg_8b_16bn = 1'b0; + // stream = 1'b0; + // #500 transfer_data = 1'b1; + // #40 transfer_data = 1'b0; // Write 16 bit SDR + // Quad SPI + wait (if_busy == 1'b0); address_write = 8'h2c; data_write = 24'h123400; + multi_io_mode = 2'h2; sdr_ddr_n = 1'b1; reg_8b_16bn = 1'b0; stream = 1'b0; #500 transfer_data = 1'b1; - #100 transfer_data = 1'b0; + #40 transfer_data = 1'b0; // Read 16 bit SDR + // Quad SPI + wait (if_busy == 1'b0); address_write = 8'hac; data_write = 24'h000000; + multi_io_mode = 2'h2; sdr_ddr_n = 1'b1; reg_8b_16bn = 1'b0; stream = 1'b0; #500 transfer_data = 1'b1; - #100 transfer_data = 1'b0; + #40 transfer_data = 1'b0; #500; + // Write 8 bit + // Classic SPI + + // wait (if_busy == 1'b0); + // address_write = 8'h2c; + // multi_io_mode = 2'h0; + // data_write = 24'h120000; + // sdr_ddr_n = 1'b0; + // reg_8b_16bn = 1'b1; + // stream = 1'b0; + // #500 transfer_data = 1'b1; + // #40 transfer_data = 1'b0; + + // Read 8 bit DDR + // it must ignore the sdr_ddr_n bit + // and work as SDR + // Dual SPI + + // wait (if_busy == 1'b0); + // address_write = 8'hac; + // data_write = 24'h000000; + // multi_io_mode = 2'h1; + // sdr_ddr_n = 1'b0; + // reg_8b_16bn = 1'b1; + // stream = 1'b0; + // #500 transfer_data = 1'b1; + // #40 transfer_data = 1'b0; + // Write 8 bit DDR + // Quad SPI + wait (if_busy == 1'b0); address_write = 8'h2c; + multi_io_mode = 2'h2; data_write = 24'h120000; sdr_ddr_n = 1'b0; reg_8b_16bn = 1'b1; stream = 1'b0; #500 transfer_data = 1'b1; - #100 transfer_data = 1'b0; + #40 transfer_data = 1'b0; // Read 8 bit DDR + // it must ignore the sdr_ddr_n bit + // and work as SDR + // Quad SPI + wait (if_busy == 1'b0); address_write = 8'hac; data_write = 24'h000000; + multi_io_mode = 2'h2; sdr_ddr_n = 1'b0; reg_8b_16bn = 1'b1; stream = 1'b0; #500 transfer_data = 1'b1; - #100 transfer_data = 1'b0; + #40 transfer_data = 1'b0; // Write 16 bit DDR + // Classic SPI + + // wait (if_busy == 1'b0); + // address_write = 8'h2c; + // data_write = 24'h123400; + // multi_io_mode = 2'h0; + // sdr_ddr_n = 1'b0; + // reg_8b_16bn = 1'b0; + // stream = 1'b0; + // transfer_data = 1'b1; + // #40 transfer_data = 1'b0; + // Read 16 bit DDR + // it must ignore the sdr_ddr_n bit + // and work as SDR + // Dual SPI + + // wait (if_busy == 1'b0); + // address_write = 8'hac; + // data_write = 24'h000000; + // multi_io_mode = 2'h1; + // sdr_ddr_n = 1'b0; + // reg_8b_16bn = 1'b0; + // stream = 1'b0; + // #500 transfer_data = 1'b1; + // #40 transfer_data = 1'b0; + + // Write 16 bit DDR + // Quad SPI + + wait (if_busy == 1'b0); address_write = 8'h2c; data_write = 24'h123400; + multi_io_mode = 2'h2; sdr_ddr_n = 1'b0; reg_8b_16bn = 1'b0; stream = 1'b0; transfer_data = 1'b1; - #100 transfer_data = 1'b0; + #40 transfer_data = 1'b0; // Read 16 bit DDR + // it must ignore the sdr_ddr_n bit + // and work as SDR + // Quad SPI + wait (if_busy == 1'b0); address_write = 8'hac; data_write = 24'h000000; + multi_io_mode = 2'h2; sdr_ddr_n = 1'b0; reg_8b_16bn = 1'b0; stream = 1'b0; #500 transfer_data = 1'b1; - #100 transfer_data = 1'b0; + #40 transfer_data = 1'b0; #500; // Stream SDR + // Dual SPI + + // wait (if_busy == 1'b0); + // address_write = 8'h2c; + // multi_io_mode = 2'h1; + // sdr_ddr_n = 1'b1; + // reg_8b_16bn = 1'b0; + // stream = 1'b1; + // transfer_data = 1'b1; + // #40 transfer_data = 1'b0; + // #1000 stream = 1'b0; + + // #500; + + // Stream SDR + // Quad SPI + wait (if_busy == 1'b0); address_write = 8'h2c; + multi_io_mode = 2'h2; sdr_ddr_n = 1'b1; reg_8b_16bn = 1'b0; stream = 1'b1; transfer_data = 1'b1; - #100 transfer_data = 1'b0; + #40 transfer_data = 1'b0; #1000 stream = 1'b0; #500; // Stream DDR + // Dual SPI + + // wait (if_busy == 1'b0); + // address_write = 8'h2c; + // multi_io_mode = 2'h1; + // reg_8b_16bn = 1'b1; + // sdr_ddr_n = 1'b0; + // stream = 1'b1; + // transfer_data = 1'b1; + // #40 transfer_data = 1'b0; + // #1000 stream = 1'b0; + + // #500; + + // Stream DDR + // Quad SPI + wait (if_busy == 1'b0); address_write = 8'h2c; + multi_io_mode = 2'h2; reg_8b_16bn = 1'b1; sdr_ddr_n = 1'b0; stream = 1'b1; transfer_data = 1'b1; - #100 transfer_data = 1'b0; + #40 transfer_data = 1'b0; #1000 stream = 1'b0; end @@ -184,39 +357,39 @@ module axi_ad3552r_if_tb; // data is incremented at each complete cycle assign dac_data_final = (stream == 1'b1) ? dac_data : data_write; - assign data_increment_valid = (sdr_ddr_n ) ? 5'd16: 5'h8; + assign data_increment_valid = (sdr_ddr_n ) ? 6'd32: 6'd16; always @(posedge dac_clk) begin if (valid_counter == data_increment_valid) begin dac_data <= dac_data + 32'h00010002; - valid_counter <= 3'b0; + valid_counter <= 6'b0; dac_data_valid <= 1'b1; end else begin dac_data <= dac_data; - valid_counter <= valid_counter + 3'b1; + valid_counter <= valid_counter + 6'b1; dac_data_valid <= 1'b0; end end // data is circullary shifted at every sampling edge - assign readback_data_shift = (sdr_ddr_n ) ? 4'h8 : 4'h4; - assign sdio_i = (sdio_t === 1'b1) ? transfer_reg[31:28] : 4'b0; + assign readback_data_shift = (sdr_ddr_n | address_write[7]) ? 4'h1 : 4'h0; + assign sdio_i = (sdio_t[1] === 1'b1) ? transfer_reg[31:28] : 2'h0;//transfer_reg[31:30] : 2'h0; always @(posedge dac_clk) begin if (shift_count == readback_data_shift) begin - transfer_reg <= {transfer_reg[27:0],transfer_reg[31:28]}; - end else if (sdio_t === 1'b1) begin + transfer_reg <= (~(|multi_io_mode)) ? {transfer_reg[30:0],transfer_reg[31]} : {transfer_reg[27:0],transfer_reg[31:28]};//{transfer_reg[29:0],transfer_reg[31:30]}; + end else if (sdio_t[1] === 1'b1) begin transfer_reg <= transfer_reg; end if (shift_count == readback_data_shift || dac_csn == 1'b1) begin shift_count <= 3'b0; - end else if (sdio_t === 1'b1) begin + end else if (sdio_t[1] === 1'b1) begin shift_count <= shift_count + 3'b1; end end - axi_ad3552r_if axi_ad3552r_interface ( + axi_ad35xxr_if axi_ad35xxr_interface ( .clk_in(dac_clk), .reset_in(reset_in), .dac_data(dac_data_final), @@ -224,6 +397,7 @@ module axi_ad3552r_if_tb; .address(address_write), .data_read(data_read), .data_write(data_write), + .multi_io_mode(multi_io_mode), .sdr_ddr_n(sdr_ddr_n), .symb_8_16b(reg_8b_16bn), .transfer_data(transfer_data), diff --git a/library/axi_ad3552r/axi_ad3552r_ip.tcl b/library/axi_ad35xxr/axi_ad35xxr_ip.tcl old mode 100755 new mode 100644 similarity index 78% rename from library/axi_ad3552r/axi_ad3552r_ip.tcl rename to library/axi_ad35xxr/axi_ad35xxr_ip.tcl index 561cca398d..0f09d053d0 --- a/library/axi_ad3552r/axi_ad3552r_ip.tcl +++ b/library/axi_ad35xxr/axi_ad35xxr_ip.tcl @@ -6,8 +6,8 @@ source ../../scripts/adi_env.tcl source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl -adi_ip_create axi_ad3552r -adi_ip_files axi_ad3552r [list \ +adi_ip_create axi_ad35xxr +adi_ip_files axi_ad35xxr [list \ "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ "$ad_hdl_dir/library/common/ad_rst.v" \ "$ad_hdl_dir/library/common/up_axi.v" \ @@ -27,24 +27,32 @@ adi_ip_files axi_ad3552r [list \ "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ - "axi_ad3552r_channel.v" \ - "axi_ad3552r_core.v" \ - "axi_ad3552r_if.v" \ - "axi_ad3552r.v" ] + "axi_ad35xxr_channel.v" \ + "axi_ad35xxr_core.v" \ + "axi_ad35xxr_if.v" \ + "axi_ad35xxr.v" ] -adi_ip_properties axi_ad3552r +adi_ip_properties axi_ad35xxr adi_init_bd_tcl -adi_ip_bd axi_ad3552r "bd/bd.tcl" +adi_ip_bd axi_ad35xxr "bd/bd.tcl" set cc [ipx::current_core] -set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad3552r} $cc +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad35xxr} $cc set_property driver_value 0 [ipx::get_ports *dac* -of_objects $cc] set_property driver_value 0 [ipx::get_ports *data* -of_objects $cc] set_property driver_value 0 [ipx::get_ports *valid* -of_objects $cc] ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 $cc +adi_add_bus "s_axis" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list {"dac_data_ready" "TREADY"} \ + {"valid_in_dma" "TVALID"} \ + {"dma_data" "TDATA"}] +adi_add_bus_clock "dac_clk" "s_axis" + adi_add_auto_fpga_spec_params ipx::create_xgui_files $cc diff --git a/projects/ad3552r_evb/Readme.md b/projects/ad3552r_evb/Readme.md deleted file mode 100755 index 4c92e827e6..0000000000 --- a/projects/ad3552r_evb/Readme.md +++ /dev/null @@ -1,8 +0,0 @@ -# AD3552R-EVB HDL Project - -Here are some pointers to help you: - * [Board Product Page](https://www.analog.com/eval-ad3552r) - * Parts : [ AD3552R Dual Channel, 16-Bit, 33 MUPS, Multispan, Multi-IO SPI DAC ](https://www.analog.com/en/products/ad3552r.html) - * Project Doc: https://wiki.analog.com/resources/eval/user-guides/dac/ad3552r_eval_zed - * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/dac/ad3552r_eval_zed - * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-dac/axi-ad3552r \ No newline at end of file diff --git a/projects/ad3552r_evb/common/ad3552r_evb_fmc.txt b/projects/ad3552r_evb/common/ad3552r_evb_fmc.txt deleted file mode 100755 index 9fe5aec7f3..0000000000 --- a/projects/ad3552r_evb/common/ad3552r_evb_fmc.txt +++ /dev/null @@ -1,18 +0,0 @@ -# ad3552r - -FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination - - D12 FMC_LA05_N /RESET ad3552r_resetn LVCMOS25 #N/A - G6 FMC_LA00_CC_P SPI_SCLK ad3552r_spi_sclk LVCMOS25 #N/A - G7 FMC_LA00_CC_N SPI_/CS ad3552r_spi_cs LVCMOS25 #N/A - H7 FMC_LA02_P SPI_SDIO0 ad3552r_spi_sdio[0] LVCMOS25 #N/A - H8 FMC_LA02_N SPI_SDIO1 ad3552r_spi_sdio[1] LVCMOS25 #N/A - G9 FMC_LA03_P SPI_SDIO2 ad3552r_spi_sdio[2] LVCMOS25 #N/A - G10 FMC_LA03_N SPI_SDIO3 ad3552r_spi_sdio[3] LVCMOS25 #N/A - D11 FMC_LA05_P /LDAC ad3552r_ldacn LVCMOS25 #N/A - H10 FMC_LA04_P /ALERT ad3552r_alertn LVCMOS25 #N/A - H11 FMC_LA04_N SPI_QPI ad3552r_qspi_sel LVCMOS25 #N/A - C10 FMC_LA06_P GPIO_6 ad3552r_gpio_6 LVCMOS25 #N/A - C11 FMC_LA06_N GPIO_7 ad3552r_gpio_7 LVCMOS25 #N/A - H13 FMC_LA07_P GPIO_8 ad3552r_gpio_8 LVCMOS25 #N/A - H14 FMC_LA07_N GPIO_9 ad3552r_gpio_9 LVCMOS25 #N/A \ No newline at end of file diff --git a/projects/ad3552r_evb/Makefile b/projects/ad35xxr_evb/Makefile old mode 100755 new mode 100644 similarity index 100% rename from projects/ad3552r_evb/Makefile rename to projects/ad35xxr_evb/Makefile diff --git a/projects/ad35xxr_evb/Readme.md b/projects/ad35xxr_evb/Readme.md new file mode 100644 index 0000000000..a7205bbe84 --- /dev/null +++ b/projects/ad35xxr_evb/Readme.md @@ -0,0 +1,16 @@ +# AD35XXR-EVB HDL Project +# It supports both AD3552R and AD3542R + +Here are some pointers to help you: +* AD3552R: + * [Board Product Page](https://www.analog.com/eval-ad3552r) + * Parts : [ AD3552R Dual Channel, 16-Bit, 33 MUPS, Multispan, Multi-IO SPI DAC ](https://www.analog.com/en/products/ad3552r.html) + * Project Doc: https://wiki.analog.com/resources/eval/user-guides/dac/ad3552r_eval_zed + * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/dac/ad3552r_eval_zed + * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-dac/axi-ad3552r +* AD3442R: + * [Board Product Page](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad3542r.html) + * Parts : [ Dual Channel, 12-/16-Bit, 16 MUPS, Multispan, Multi-IO SPI DAC ](https://www.analog.com/en/products/AD3542R.html) + * Project Doc: https://wiki.analog.com/resources/eval/user-guides/dac/eval-ad3542r + * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/dac/eval-ad3542r + * Linux Drivers: NA \ No newline at end of file diff --git a/projects/ad3552r_evb/common/ad3552r_evb_bd.tcl b/projects/ad35xxr_evb/common/ad35xxr_evb_bd.tcl old mode 100755 new mode 100644 similarity index 58% rename from projects/ad3552r_evb/common/ad3552r_evb_bd.tcl rename to projects/ad35xxr_evb/common/ad35xxr_evb_bd.tcl index 45cbc89496..dfb3801633 --- a/projects/ad3552r_evb/common/ad3552r_evb_bd.tcl +++ b/projects/ad35xxr_evb/common/ad35xxr_evb_bd.tcl @@ -7,7 +7,8 @@ create_bd_port -dir O dac_sclk create_bd_port -dir O dac_csn create_bd_port -dir I -from 3 -to 0 dac_spi_sdi create_bd_port -dir O -from 3 -to 0 dac_spi_sdo -create_bd_port -dir O dac_spi_sdo_t +create_bd_port -dir O -from 3 -to 0 dac_spi_sdo_t +create_bd_port -dir O dac_qspi_sel ad_ip_instance axi_dmac axi_dac_dma ad_ip_parameter axi_dac_dma CONFIG.DMA_TYPE_SRC 0 @@ -20,26 +21,29 @@ ad_ip_parameter axi_dac_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_dac_dma CONFIG.DMA_DATA_WIDTH_SRC 32 ad_ip_parameter axi_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 32 -ad_ip_instance axi_ad3552r axi_ad3552r_dac +ad_ip_instance axi_ad35xxr axi_ad35xxr_dac -ad_connect axi_ad3552r_dac/dac_sclk dac_sclk -ad_connect axi_ad3552r_dac/dac_csn dac_csn -ad_connect axi_ad3552r_dac/sdio_i dac_spi_sdi -ad_connect axi_ad3552r_dac/sdio_o dac_spi_sdo -ad_connect axi_ad3552r_dac/sdio_t dac_spi_sdo_t -ad_connect axi_ad3552r_dac/dma_data axi_dac_dma/m_axis_data -ad_connect axi_ad3552r_dac/valid_in_dma axi_dac_dma/m_axis_valid -ad_connect axi_ad3552r_dac/dac_data_ready axi_dac_dma/m_axis_ready +ad_connect axi_ad35xxr_dac/dac_sclk dac_sclk +ad_connect axi_ad35xxr_dac/dac_csn dac_csn +ad_connect axi_ad35xxr_dac/sdio_i dac_spi_sdi +ad_connect axi_ad35xxr_dac/sdio_o dac_spi_sdo +ad_connect axi_ad35xxr_dac/sdio_t dac_spi_sdo_t +ad_connect axi_ad35xxr_dac/qspi_sel dac_qspi_sel + +ad_connect axi_ad35xxr_dac/s_axis axi_dac_dma/m_axis +#ad_connect axi_ad35xxr_dac/dma_data axi_dac_dma/m_axis_data +#ad_connect axi_ad35xxr_dac/valid_in_dma axi_dac_dma/m_axis_valid +#ad_connect axi_ad35xxr_dac/dac_data_ready axi_dac_dma/m_axis_ready ad_connect sys_rstgen/peripheral_aresetn axi_dac_dma/m_src_axi_aresetn # Tie unused inputs to GND -ad_connect axi_ad3552r_dac/valid_in_dma_sec GND -ad_connect axi_ad3552r_dac/data_in_a GND -ad_connect axi_ad3552r_dac/data_in_b GND -ad_connect axi_ad3552r_dac/valid_in_a GND -ad_connect axi_ad3552r_dac/valid_in_b GND -ad_connect axi_ad3552r_dac/external_sync GND +ad_connect axi_ad35xxr_dac/valid_in_dma_sec GND +ad_connect axi_ad35xxr_dac/data_in_a GND +ad_connect axi_ad35xxr_dac/data_in_b GND +ad_connect axi_ad35xxr_dac/valid_in_a GND +ad_connect axi_ad35xxr_dac/valid_in_b GND +ad_connect axi_ad35xxr_dac/external_sync GND ad_ip_instance axi_clkgen axi_clkgen ad_ip_parameter axi_clkgen CONFIG.ID 1 @@ -48,12 +52,12 @@ ad_ip_parameter axi_clkgen CONFIG.VCO_DIV 1 ad_ip_parameter axi_clkgen CONFIG.VCO_MUL 8 ad_ip_parameter axi_clkgen CONFIG.CLK0_DIV 6 -ad_connect axi_clkgen/clk sys_ps7/FCLK_CLK0 -ad_connect axi_clkgen/clk_0 axi_ad3552r_dac/dac_clk +ad_connect $sys_cpu_clk axi_clkgen/clk +ad_connect axi_clkgen/clk_0 axi_ad35xxr_dac/dac_clk ad_connect axi_clkgen/clk_0 axi_dac_dma/m_axis_aclk ad_cpu_interconnect 0x44a30000 axi_dac_dma -ad_cpu_interconnect 0x44a70000 axi_ad3552r_dac +ad_cpu_interconnect 0x44a70000 axi_ad35xxr_dac ad_cpu_interconnect 0x44B00000 axi_clkgen ad_cpu_interrupt "ps-13" "mb-13" axi_dac_dma/irq diff --git a/projects/ad35xxr_evb/common/ad35xxr_evb_fmc.txt b/projects/ad35xxr_evb/common/ad35xxr_evb_fmc.txt new file mode 100644 index 0000000000..19e400bd2d --- /dev/null +++ b/projects/ad35xxr_evb/common/ad35xxr_evb_fmc.txt @@ -0,0 +1,18 @@ +# ad35xxr + +FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination + + D12 FMC_LA05_N /RESET ad35xxr_resetn LVCMOS25 #N/A + G6 FMC_LA00_CC_P SPI_SCLK ad35xxr_spi_sclk LVCMOS25 #N/A + G7 FMC_LA00_CC_N SPI_/CS ad35xxr_spi_cs LVCMOS25 #N/A + H7 FMC_LA02_P SPI_SDIO0 ad35xxr_spi_sdio[0] LVCMOS25 #N/A + H8 FMC_LA02_N SPI_SDIO1 ad35xxr_spi_sdio[1] LVCMOS25 #N/A + G9 FMC_LA03_P SPI_SDIO2 ad35xxr_spi_sdio[2] LVCMOS25 #N/A + G10 FMC_LA03_N SPI_SDIO3 ad35xxr_spi_sdio[3] LVCMOS25 #N/A + D11 FMC_LA05_P /LDAC ad35xxr_ldacn LVCMOS25 #N/A + H10 FMC_LA04_P /ALERT ad35xxr_alertn LVCMOS25 #N/A + H11 FMC_LA04_N SPI_QPI ad35xxr_qspi_sel LVCMOS25 #N/A + C10 FMC_LA06_P GPIO_6 ad35xxr_gpio_6 LVCMOS25 #N/A + C11 FMC_LA06_N GPIO_7 ad35xxr_gpio_7 LVCMOS25 #N/A + H13 FMC_LA07_P GPIO_8 ad35xxr_gpio_8 LVCMOS25 #N/A + H14 FMC_LA07_N GPIO_9 ad35xxr_gpio_9 LVCMOS25 #N/A \ No newline at end of file diff --git a/projects/ad3552r_evb/zed/Makefile b/projects/ad35xxr_evb/zed/Makefile old mode 100755 new mode 100644 similarity index 88% rename from projects/ad3552r_evb/zed/Makefile rename to projects/ad35xxr_evb/zed/Makefile index 23b67010a7..1bd62e8318 --- a/projects/ad3552r_evb/zed/Makefile +++ b/projects/ad35xxr_evb/zed/Makefile @@ -4,15 +4,15 @@ ## Auto-generated, do not modify! #################################################################################### -PROJECT_NAME := ad3552r_evb_zed +PROJECT_NAME := ad35xxr_evb_zed -M_DEPS += ../common/ad3552r_evb_bd.tcl +M_DEPS += ../common/ad35xxr_evb_bd.tcl M_DEPS += ../../scripts/adi_pd.tcl M_DEPS += ../../common/zed/zed_system_constr.xdc M_DEPS += ../../common/zed/zed_system_bd.tcl M_DEPS += ../../../library/common/ad_iobuf.v -LIB_DEPS += axi_ad3552r +LIB_DEPS += axi_ad35xxr LIB_DEPS += axi_clkgen LIB_DEPS += axi_dmac LIB_DEPS += axi_hdmi_tx diff --git a/projects/ad3552r_evb/zed/system_bd.tcl b/projects/ad35xxr_evb/zed/system_bd.tcl old mode 100755 new mode 100644 similarity index 94% rename from projects/ad3552r_evb/zed/system_bd.tcl rename to projects/ad35xxr_evb/zed/system_bd.tcl index 27c857d27e..bc6334b409 --- a/projects/ad3552r_evb/zed/system_bd.tcl +++ b/projects/ad35xxr_evb/zed/system_bd.tcl @@ -7,7 +7,7 @@ source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl source $ad_hdl_dir/projects/scripts/adi_pd.tcl # block design -source ../common/ad3552r_evb_bd.tcl +source ../common/ad35xxr_evb_bd.tcl #system ID ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 diff --git a/projects/ad3552r_evb/zed/system_constr.xdc b/projects/ad35xxr_evb/zed/system_constr.xdc old mode 100755 new mode 100644 similarity index 56% rename from projects/ad3552r_evb/zed/system_constr.xdc rename to projects/ad35xxr_evb/zed/system_constr.xdc index fcaa6473d5..aaaff891f0 --- a/projects/ad3552r_evb/zed/system_constr.xdc +++ b/projects/ad35xxr_evb/zed/system_constr.xdc @@ -3,22 +3,22 @@ ### SPDX short identifier: ADIBSD ############################################################################### -# ad3552r_fmc SPI interface +# ad35xxr_fmc SPI interface -set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad3552r_spi_sdio[0]}] ; # FMC_LA02_P IO_L20P_T3_34 -set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad3552r_spi_sdio[1]}] ; # FMC_LA02_N IO_L20N_T3_34 -set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports {ad3552r_spi_sdio[2]}] ; # FMC_LA03_P IO_L16P_T2_34 -set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports {ad3552r_spi_sdio[3]}] ; # FMC_LA03_N IO_L16N_T2_34 +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {ad35xxr_spi_sdio[0]}] ; # FMC_LA02_P IO_L20P_T3_34 +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {ad35xxr_spi_sdio[1]}] ; # FMC_LA02_N IO_L20N_T3_34 +set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports {ad35xxr_spi_sdio[2]}] ; # FMC_LA03_P IO_L16P_T2_34 +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports {ad35xxr_spi_sdio[3]}] ; # FMC_LA03_N IO_L16N_T2_34 -set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 } [get_ports ad3552r_spi_sclk] ; # FMC_LA00_CC_P IO_L13P_T2_MRCC_34 -set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25 } [get_ports ad3552r_spi_cs] ; # FMC_LA00_CC_N IO_L13N_T2_MRCC_34 +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 } [get_ports ad35xxr_spi_sclk] ; # FMC_LA00_CC_P IO_L13P_T2_MRCC_34 +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25 } [get_ports ad35xxr_spi_cs] ; # FMC_LA00_CC_N IO_L13N_T2_MRCC_34 -set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports ad3552r_ldacn] ; # FMC_LA05_P IO_L7P_T1_34 -set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports ad3552r_resetn] ; # FMC_LA05_N IO_L7N_T1_34 -set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad3552r_alertn] ; # FMC_LA04_P IO_L15P_T2_DQS_34 -set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports ad3552r_qspi_sel] ; # FMC_LA04_N IO_L15N_T2_DQS_34 +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports ad35xxr_ldacn] ; # FMC_LA05_P IO_L7P_T1_34 +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports ad35xxr_resetn] ; # FMC_LA05_N IO_L7N_T1_34 +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad35xxr_alertn] ; # FMC_LA04_P IO_L15P_T2_DQS_34 +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports ad35xxr_qspi_sel] ; # FMC_LA04_N IO_L15N_T2_DQS_34 -set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports ad3552r_gpio_6] ; # FMC_LA06_P IO_L10P_T1_34 -set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports ad3552r_gpio_7] ; # FMC_LA06_N IO_L10N_T1_34 -set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports ad3552r_gpio_8] ; # FMC_LA07_P IO_L21P_T3_DQS_34 -set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports ad3552r_gpio_9] ; # FMC_LA07_N IO_L21N_T3_DQS_34 +set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports ad35xxr_gpio_6] ; # FMC_LA06_P IO_L10P_T1_34 +set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports ad35xxr_gpio_7] ; # FMC_LA06_N IO_L10N_T1_34 +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports ad35xxr_gpio_8] ; # FMC_LA07_P IO_L21P_T3_DQS_34 +set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports ad35xxr_gpio_9] ; # FMC_LA07_N IO_L21N_T3_DQS_34 diff --git a/projects/ad3552r_evb/zed/system_project.tcl b/projects/ad35xxr_evb/zed/system_project.tcl old mode 100755 new mode 100644 similarity index 84% rename from projects/ad3552r_evb/zed/system_project.tcl rename to projects/ad35xxr_evb/zed/system_project.tcl index 08440632b8..7c8e87d3ef --- a/projects/ad3552r_evb/zed/system_project.tcl +++ b/projects/ad35xxr_evb/zed/system_project.tcl @@ -7,11 +7,11 @@ source ../../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl -adi_project ad3552r_evb_zed -adi_project_files ad3552r_evb_zed [list \ +adi_project ad35xxr_evb_zed +adi_project_files ad35xxr_evb_zed [list \ "system_top.v" \ "system_constr.xdc" \ "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \ "$ad_hdl_dir/library/common/ad_iobuf.v" ] -adi_project_run ad3552r_evb_zed +adi_project_run ad35xxr_evb_zed diff --git a/projects/ad3552r_evb/zed/system_top.v b/projects/ad35xxr_evb/zed/system_top.v old mode 100755 new mode 100644 similarity index 85% rename from projects/ad3552r_evb/zed/system_top.v rename to projects/ad35xxr_evb/zed/system_top.v index 14df3bc8d1..bbaf29d0c8 --- a/projects/ad3552r_evb/zed/system_top.v +++ b/projects/ad35xxr_evb/zed/system_top.v @@ -85,17 +85,17 @@ module system_top ( // dac interface - inout ad3552r_ldacn, - inout ad3552r_alertn, - inout ad3552r_gpio_6, - inout ad3552r_gpio_7, - inout ad3552r_gpio_8, - inout ad3552r_gpio_9, - inout [ 3:0] ad3552r_spi_sdio, - output ad3552r_resetn, - output ad3552r_qspi_sel, - output ad3552r_spi_cs, - output ad3552r_spi_sclk + inout ad35xxr_ldacn, + inout ad35xxr_alertn, + inout ad35xxr_gpio_6, + inout ad35xxr_gpio_7, + inout ad35xxr_gpio_8, + inout ad35xxr_gpio_9, + inout [ 3:0] ad35xxr_spi_sdio, + output ad35xxr_resetn, + output ad35xxr_qspi_sel, + output ad35xxr_spi_cs, + output ad35xxr_spi_sclk ); // internal signals @@ -109,35 +109,34 @@ module system_top ( wire [ 1:0] iic_mux_sda_i_s; wire [ 1:0] iic_mux_sda_o_s; wire iic_mux_sda_t_s; - wire [ 3:0] ad3552r_spi_sdo; - wire [ 3:0] ad3552r_spi_sdi; - wire ad3552r_spi_t; + wire [ 3:0] ad35xxr_spi_sdo; + wire [ 3:0] ad35xxr_spi_sdi; + wire [ 3:0] ad35xxr_spi_t; assign gpio_i[63:39] = gpio_o[63:39]; - assign ad3552r_qspi_sel = 1'b1; - assign ad3552r_resetn = gpio_o[38]; + assign ad35xxr_resetn = gpio_o[38]; ad_iobuf #( .DATA_WIDTH(4) ) i_dac_0_spi_iobuf ( - .dio_t({4{ad3552r_spi_t}}), - .dio_i(ad3552r_spi_sdo), - .dio_o(ad3552r_spi_sdi), - .dio_p(ad3552r_spi_sdio)); + .dio_t({ad35xxr_spi_t}), + .dio_i(ad35xxr_spi_sdo), + .dio_o(ad35xxr_spi_sdi), + .dio_p(ad35xxr_spi_sdio)); ad_iobuf #( .DATA_WIDTH(6) - ) i_ad3552r_iobuf ( + ) i_ad35xxr_iobuf ( .dio_t(gpio_t[37:32]), .dio_i(gpio_o[37:32]), .dio_o(gpio_i[37:32]), - .dio_p({ad3552r_gpio_9, - ad3552r_gpio_8, - ad3552r_gpio_7, - ad3552r_gpio_6, - ad3552r_alertn, - ad3552r_ldacn})); + .dio_p({ad35xxr_gpio_9, + ad35xxr_gpio_8, + ad35xxr_gpio_7, + ad35xxr_gpio_6, + ad35xxr_alertn, + ad35xxr_ldacn})); ad_iobuf #( .DATA_WIDTH (32) @@ -236,9 +235,10 @@ module system_top ( //dac interface - .dac_sclk(ad3552r_spi_sclk), - .dac_csn(ad3552r_spi_cs), - .dac_spi_sdi(ad3552r_spi_sdi), - .dac_spi_sdo(ad3552r_spi_sdo), - .dac_spi_sdo_t(ad3552r_spi_t)); + .dac_sclk(ad35xxr_spi_sclk), + .dac_csn(ad35xxr_spi_cs), + .dac_spi_sdi(ad35xxr_spi_sdi), + .dac_spi_sdo(ad35xxr_spi_sdo), + .dac_spi_sdo_t(ad35xxr_spi_t), + .dac_qspi_sel(ad35xxr_qspi_sel)); endmodule