diff --git a/docs/projects/ad353xr/ad353xr_block_diagram.svg b/docs/projects/ad353xr/ad353xr_block_diagram.svg new file mode 100644 index 0000000000..b84750b6c1 --- /dev/null +++ b/docs/projects/ad353xr/ad353xr_block_diagram.svg @@ -0,0 +1 @@ +I2CUARTEthernetSPIDDRxInterruptsARM SoC / Zynq MPTimerFPGA BoardGPIO/FMCGPIO \ No newline at end of file diff --git a/docs/projects/ad353xr/index.rst b/docs/projects/ad353xr/index.rst new file mode 100644 index 0000000000..bf4c7b9914 --- /dev/null +++ b/docs/projects/ad353xr/index.rst @@ -0,0 +1,191 @@ +.. _ad353xr: + +AD353XR HDL project +================================================================================ + +Overview +-------------------------------------------------------------------------------- + +The :adi:`AD3530R`/ :adi:`AD3530` are low power, 8-channel, 16-bit, buffered +voltage output, digital-to-analog converters (DACs) that include a gain bit field, +resulting in a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2) for a +reference voltage of 2.5 V. The :adi:`AD3530R` has an on-chip, buffered, 2.5 V +reference available at the VREF pin, capable of sourcing external loads up to ++5 mA. + +Each DAC channel has its own Input register and DAC register. The DAC Register +stores digital code equivalent to the DAC output voltage while the Input Register +acts as a temporary staging register before being passed on the DAC Register. With +the LDAC function, one or more DAC registers could be updated in parallel with +the data held in the Input Register. The DAC registers can also be directly written +to, in which the corresponding output updates immediately without an LDAC. + +The :adi:`AD3530R`/ :adi:`AD3530` contains eight buffered voltage output DAC +channels capable of sourcing and sinking up to 40 mA of current. + +The :adi:`AD3530R`/ :adi:`AD3530` contains a 27:1 multiplexer which could +output a voltage on the MUX_OUT pin that is a representative of +either the output voltage or output current of a chosen channel, or +the internal die temperature of the device. + + +Applications: + +* Optical transceivers +* Test and measurement +* Industrial automation +* Data acquisition systems + +Supported boards +------------------------------------------------------------------------------- + +- :adi:`EVAL-AD3530RARDZ` + +Supported devices +------------------------------------------------------------------------------- + +- :adi:`AD3530` +- :adi:`AD3530R` + +Supported carriers +------------------------------------------------------------------------------- + +- :xilinx:`ZedBoard ` on FMCs +- :xilinx:`Cora Z7-07S ` on GPIOs +- :intel:`DE10-Nano ` on GPIOs + +Block design +------------------------------------------------------------------------------- + +Block diagram +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The data path is depicted in the below diagram: + +.. image:: ad353xr_block_diagram.svg + :width: 800 + :align: center + :alt: AD353XR block diagram + +Hardware setup +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +============ ================= ============== ================ ============== +Signal AD353XR Testpoint ZedBoard FMC Cora Z7-07S GPIO DE10-Nano GPIO +============ ================= ============== ================ ============== +CSB(SS0) PMOD P1 M19/FMC-LA00_P F16 AE19 +SDO(MOSI) PMOD P2 N19/FMC-LA01_P T12 AG15 +SDI(MISO) PMOD P3 N20/FMC-LA01_N W15 AF18 +SCK PMOD P4 D18/FMC-CLK1_P H15 AG18 +RESETB PMOD P8 T19/FMC-LA10_N V13 AE20 +LDACB PMOD P9 J18/FMC_LA05_P T14 AE17 +============ ================= ============== ================ ============== + +The evaluation board is powered by 5 V voltage from an external USB. + +GPIOs +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The Software GPIO number is calculated as follows: + +- Zynq-7000: if PS7 is used, then the offset is 54 +- All supported boards uses the same HDL GPIO EMIO Number + +.. list-table:: + :widths: 25 25 25 25 + :header-rows: 2 + + * - GPIO signal + - Direction + - HDL GPIO EMIO + - Software GPIO + * - + - (from FPGA view) + - + - Zynq-7000 + * - RESETB + - OUT + - 33 + - 87 + * - LDACB + - OUT + - 34 + - 88 + +Building the HDL project +------------------------------------------------------------------------------- + +The design is built upon ADI's generic HDL reference design framework. +ADI distributes the bit/elf files of these projects as part of the +:dokuwiki:`ADI Kuiper Linux `. +If you want to build the sources, ADI makes them available on the +:git-hdl:`HDL repository `. To get the source you must +`clone `__ +the HDL repository, and then build the project as follows: + +**Linux/Cygwin/WSL** + +.. shell:: + + $cd hdl/projects/ad353xr/zed + $make + +A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. + +Resources +------------------------------------------------------------------------------- + +Hardware related (Links To be Updated) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Product datasheet: :adi:`AD353XR` +- `UG-1203: EVAL-AD3530RARDZ Board User Guide `__ + +HDL related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :git-hdl:`AD353XR HDL project source code ` + +.. list-table:: + :widths: 30 35 35 + :header-rows: 1 + + * - IP name + - Source code link + - Documentation link + * - AXI_CLKGEN + - :git-hdl:`library/axi_clkgen` + - :ref:`axi_clkgen` + * - AXI_DMAC + - :git-hdl:`library/axi_dmac` + - :ref:`axi_dmac` + * - AXI_HDMI_TX + - :git-hdl:`library/axi_hdmi_tx` + - :ref:`axi_hdmi_tx` + * - AXI_I2S_ADI + - :git-hdl:`library/axi_i2s_adi` + - --- + * - AXI_SPDIF_TX + - :git-hdl:`library/axi_spdif_tx` + - --- + * - AXI_SYSID + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` + * - AXI_SYSID_ROM + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` + * - UTIL_I2C_MIXER + - :git-hdl:`library/util_i2c_mixer` + - --- + +Software related (Links To be Updated) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :git-no-os:`AD353XR No-OS project source code ` +- :git-no-os:`AD353XR No-OS Driver source code ` +- :dokuwiki:`AD353XR No-OS Driver documentation ` +- :dokuwiki:`AD353XR IIO Application ` + +.. include:: ../common/more_information.rst + +.. include:: ../common/support.rst diff --git a/projects/ad353xr/Makefile b/projects/ad353xr/Makefile new file mode 100644 index 0000000000..1402069e10 --- /dev/null +++ b/projects/ad353xr/Makefile @@ -0,0 +1,7 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/ad353xr/Readme.md b/projects/ad353xr/Readme.md new file mode 100644 index 0000000000..6c907ea01f --- /dev/null +++ b/projects/ad353xr/Readme.md @@ -0,0 +1,8 @@ +# AD353XR HDL Driver + +Here are some pointers to help you: + * [Board Product Page] To Be Released + * Parts : [ AD353XR Family of Low Power, Buffered Voltage Output, SPI DAC ] To Be Released + * Project Doc: https://wiki.analog.com/resources/eval/user-guides/ad353xr + * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad353xr + * Linux Drivers: To be added after PR and Upstream \ No newline at end of file diff --git a/projects/ad353xr/coraz7s/Makefile b/projects/ad353xr/coraz7s/Makefile new file mode 100644 index 0000000000..46bf00cb17 --- /dev/null +++ b/projects/ad353xr/coraz7s/Makefile @@ -0,0 +1,18 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad353xR_coraz7s + +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl +M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc +M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl +M_DEPS += ../../../library/common/ad_iobuf.v + +LIB_DEPS += axi_sysid +LIB_DEPS += sysid_rom + +include ../../scripts/project-xilinx.mk diff --git a/projects/ad353xr/coraz7s/system_bd.tcl b/projects/ad353xr/coraz7s/system_bd.tcl new file mode 100644 index 0000000000..5c7bb1b6c2 --- /dev/null +++ b/projects/ad353xr/coraz7s/system_bd.tcl @@ -0,0 +1,16 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +sysid_gen_sys_init_file + +set sys_dma_clk [get_bd_nets sys_dma_clk] \ No newline at end of file diff --git a/projects/ad353xr/coraz7s/system_constr.xdc b/projects/ad353xr/coraz7s/system_constr.xdc new file mode 100644 index 0000000000..60631d91da --- /dev/null +++ b/projects/ad353xr/coraz7s/system_constr.xdc @@ -0,0 +1,15 @@ +############################################################################### +## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# DAC SPI interface + +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports spi_sck] ; ## ck_sck H15 +set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS33} [get_ports spi_sdo] ; ## ck_mosi T12 +set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS33} [get_ports spi_sdi] ; ## ck_miso W15 +set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports spi_csb] ; ## ck_ss F16 + +# DAC GPIO interface +set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports dac_resetb] ; ## ck_io[1] V13 +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports dac_ldacb] ; ## ck_io[2] T14 diff --git a/projects/ad353xr/coraz7s/system_project.tcl b/projects/ad353xr/coraz7s/system_project.tcl new file mode 100644 index 0000000000..073e2610c2 --- /dev/null +++ b/projects/ad353xr/coraz7s/system_project.tcl @@ -0,0 +1,20 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project ad353xR_coraz7s + +adi_project_files ad353xR_coraz7s [list \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc"] + +set_property PROCESSING_ORDER LATE [get_files system_constr.xdc] + +adi_project_run ad353xR_coraz7s diff --git a/projects/ad353xr/coraz7s/system_top.v b/projects/ad353xr/coraz7s/system_top.v new file mode 100644 index 0000000000..f48e83d924 --- /dev/null +++ b/projects/ad353xr/coraz7s/system_top.v @@ -0,0 +1,156 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [ 1:0] btn, + inout [ 5:0] led, + + inout iic_ard_scl, + inout iic_ard_sda, + + output dac_resetb, + output dac_ldacb, + + input spi_sdi, + output spi_sdo, + output spi_sck, + output spi_csb +); + + // internal signals + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + // assignments + assign gpio_i[63:32] = gpio_o[63:32]; + assign gpio_i[31:8] = gpio_o[31:8]; + + assign dac_resetb = gpio_o[33]; + assign dac_ldacb = gpio_o[34]; + + // instantiations + ad_iobuf #( + .DATA_WIDTH (2) + ) i_iobuf_buttons ( + .dio_t (gpio_t[1:0]), + .dio_i (gpio_o[1:0]), + .dio_o (gpio_i[1:0]), + .dio_p (btn)); + + ad_iobuf #( + .DATA_WIDTH (6) + ) i_iobuf_leds ( + .dio_t (gpio_t[7:2]), + .dio_i (gpio_o[7:2]), + .dio_o (gpio_i[7:2]), + .dio_p (led)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_sck), + .spi0_csn_0_o (spi_csb), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_sdi), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_sdo), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o(), + .iic_ard_scl_io (iic_ard_scl), + .iic_ard_sda_io (iic_ard_sda)); + +endmodule diff --git a/projects/ad353xr/de10nano/Makefile b/projects/ad353xr/de10nano/Makefile new file mode 100644 index 0000000000..211eb8a3b2 --- /dev/null +++ b/projects/ad353xr/de10nano/Makefile @@ -0,0 +1,18 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad353xR_de10nano + +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/de10nano/de10nano_system_qsys.tcl +M_DEPS += ../../common/de10nano/de10nano_system_assign.tcl + +LIB_DEPS += axi_dmac +LIB_DEPS += axi_hdmi_tx +LIB_DEPS += axi_sysid +LIB_DEPS += sysid_rom + +include ../../scripts/project-intel.mk diff --git a/projects/ad353xr/de10nano/system_constr.sdc b/projects/ad353xr/de10nano/system_constr.sdc new file mode 100644 index 0000000000..7e13342108 --- /dev/null +++ b/projects/ad353xr/de10nano/system_constr.sdc @@ -0,0 +1,10 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +create_clock -period "20.000 ns" -name sys_clk_50mhz [get_ports {sys_clk}] +create_clock -period "16.666 ns" -name usb_clk_60mhz [get_ports {usbl_clk}] + +derive_pll_clocks +derive_clock_uncertainty diff --git a/projects/ad353xr/de10nano/system_project.tcl b/projects/ad353xr/de10nano/system_project.tcl new file mode 100644 index 0000000000..b3d43545a8 --- /dev/null +++ b/projects/ad353xr/de10nano/system_project.tcl @@ -0,0 +1,37 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set REQUIRED_QUARTUS_VERSION 21.1.0 +set QUARTUS_PRO_ISUSED 0 +source ../../../scripts/adi_env.tcl +source ../../scripts/adi_project_intel.tcl + +adi_project ad353xR_de10nano + +source $ad_hdl_dir/projects/common/de10nano/de10nano_system_assign.tcl + +# SPI connections + +set_location_assignment PIN_AG18 -to spiml_clk ; ## GPIO1 JP7 [33] +set_location_assignment PIN_AF18 -to spiml_miso ; ## GPIO1 JP7 [35] +set_location_assignment PIN_AG15 -to spiml_mosi ; ## GPIO1 JP7 [37] +set_location_assignment PIN_AE19 -to spiml_ss0 ; ## GPIO1 JP7 [39] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spiml_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spiml_clk_miso +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spiml_clk_mosi +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spiml_clk_ss0 + +# GPIO connections + +set_location_assignment PIN_AE20 -to dac_resetb ; ## GPIO1 JP7 [38] +set_location_assignment PIN_AE17 -to dac_ldacb ; ## GPIO1 JP7 [40] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dac_resetb +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dac_ldacb + + + +execute_flow -compile diff --git a/projects/ad353xr/de10nano/system_qsys.tcl b/projects/ad353xr/de10nano/system_qsys.tcl new file mode 100644 index 0000000000..0245f9377b --- /dev/null +++ b/projects/ad353xr/de10nano/system_qsys.tcl @@ -0,0 +1,16 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source $ad_hdl_dir/projects/scripts/adi_pd.tcl +source $ad_hdl_dir/projects/common/de10nano/de10nano_system_qsys.tcl + +#system ID +set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9} +set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9} + +set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "[pwd]/mem_init_sys.txt" + +sysid_gen_sys_init_file; + diff --git a/projects/ad353xr/de10nano/system_top.v b/projects/ad353xr/de10nano/system_top.v new file mode 100644 index 0000000000..67aed44f27 --- /dev/null +++ b/projects/ad353xr/de10nano/system_top.v @@ -0,0 +1,235 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + // clock and resets + input sys_clk, + + // hps-ddr + output [14:0] ddr3_a, + output [ 2:0] ddr3_ba, + output ddr3_reset_n, + output ddr3_ck_p, + output ddr3_ck_n, + output ddr3_cke, + output ddr3_cs_n, + output ddr3_ras_n, + output ddr3_cas_n, + output ddr3_we_n, + inout [31:0] ddr3_dq, + inout [ 3:0] ddr3_dqs_p, + inout [ 3:0] ddr3_dqs_n, + output [ 3:0] ddr3_dm, + output ddr3_odt, + input ddr3_rzq, + + // hps-ethernet + output eth1_tx_clk, + output eth1_tx_ctl, + output [ 3:0] eth1_tx_d, + input eth1_rx_clk, + input eth1_rx_ctl, + input [ 3:0] eth1_rx_d, + output eth1_mdc, + inout eth1_mdio, + + // hps-sdio + output sdio_clk, + inout sdio_cmd, + inout [ 3:0] sdio_d, + + // hps-spim1 + output spim1_ss0, + output spim1_clk, + output spim1_mosi, + input spim1_miso, + + // hps-usb + input usb1_clk, + output usb1_stp, + input usb1_dir, + input usb1_nxt, + inout [ 7:0] usb1_d, + + // hps-uart + input uart0_rx, + output uart0_tx, + inout hps_conv_usb_n, + + // board gpio + output [ 7:0] gpio_bd_o, + input [ 5:0] gpio_bd_i, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [ 23:0] hdmi_data, + + inout hdmi_i2c_scl, + inout hdmi_i2c_sda, + + // additional control signals + output dac_resetb, + output dac_ldacb +); + + // internal signals + + wire sys_resetn; + wire [63:0] gpio_i; + wire [63:0] gpio_o; + + wire i2c0_out_data; + wire i2c0_sda; + wire i2c0_out_clk; + wire i2c0_scl_in_clk; + + // instantiations + + assign gpio_i[63:14] = gpio_o[63:14]; + assign gpio_i[13:8] = gpio_bd_i[5:0]; + + assign gpio_bd_o[7:0] = gpio_o[7:0]; + + assign dac_resetb = gpio_o[33]; + assign dac_ldacb = gpio_o[34]; + + ALT_IOBUF scl_iobuf ( + .i (1'b0), + .oe (i2c0_out_clk), + .o (i2c0_scl_in_clk), + .io (hdmi_i2c_scl)); + + ALT_IOBUF sda_iobuf ( + .i (1'b0), + .oe (i2c0_out_data), + .o (i2c0_sda), + .io (hdmi_i2c_sda)); + + system_bd i_system_bd ( + .sys_clk_clk (sys_clk), + + .sys_hps_h2f_reset_reset_n (sys_resetn), + + .sys_hps_memory_mem_a (ddr3_a), + .sys_hps_memory_mem_ba (ddr3_ba), + .sys_hps_memory_mem_ck (ddr3_ck_p), + .sys_hps_memory_mem_ck_n (ddr3_ck_n), + .sys_hps_memory_mem_cke (ddr3_cke), + .sys_hps_memory_mem_cs_n (ddr3_cs_n), + .sys_hps_memory_mem_ras_n (ddr3_ras_n), + .sys_hps_memory_mem_cas_n (ddr3_cas_n), + .sys_hps_memory_mem_we_n (ddr3_we_n), + .sys_hps_memory_mem_reset_n (ddr3_reset_n), + .sys_hps_memory_mem_dq (ddr3_dq), + .sys_hps_memory_mem_dqs (ddr3_dqs_p), + .sys_hps_memory_mem_dqs_n (ddr3_dqs_n), + .sys_hps_memory_mem_odt (ddr3_odt), + .sys_hps_memory_mem_dm (ddr3_dm), + .sys_hps_memory_oct_rzqin (ddr3_rzq), + + .sys_rst_reset_n (sys_resetn), + + .sys_hps_i2c0_out_data (i2c0_out_data), + .sys_hps_i2c0_sda (i2c0_sda), + .sys_hps_i2c0_clk_clk (i2c0_out_clk), + .sys_hps_i2c0_scl_in_clk (i2c0_scl_in_clk), + + .sys_hps_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk), + .sys_hps_hps_io_hps_io_emac1_inst_TXD0 (eth1_tx_d[0]), + .sys_hps_hps_io_hps_io_emac1_inst_TXD1 (eth1_tx_d[1]), + .sys_hps_hps_io_hps_io_emac1_inst_TXD2 (eth1_tx_d[2]), + .sys_hps_hps_io_hps_io_emac1_inst_TXD3 (eth1_tx_d[3]), + .sys_hps_hps_io_hps_io_emac1_inst_RXD0 (eth1_rx_d[0]), + .sys_hps_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio), + .sys_hps_hps_io_hps_io_emac1_inst_MDC (eth1_mdc), + .sys_hps_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl), + .sys_hps_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl), + .sys_hps_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk), + .sys_hps_hps_io_hps_io_emac1_inst_RXD1 (eth1_rx_d[1]), + .sys_hps_hps_io_hps_io_emac1_inst_RXD2 (eth1_rx_d[2]), + .sys_hps_hps_io_hps_io_emac1_inst_RXD3 (eth1_rx_d[3]), + + .sys_hps_hps_io_hps_io_sdio_inst_CMD (sdio_cmd), + .sys_hps_hps_io_hps_io_sdio_inst_D0 (sdio_d[0]), + .sys_hps_hps_io_hps_io_sdio_inst_D1 (sdio_d[1]), + .sys_hps_hps_io_hps_io_sdio_inst_CLK (sdio_clk), + .sys_hps_hps_io_hps_io_sdio_inst_D2 (sdio_d[2]), + .sys_hps_hps_io_hps_io_sdio_inst_D3 (sdio_d[3]), + + .sys_hps_hps_io_hps_io_usb1_inst_D0 (usb1_d[0]), + .sys_hps_hps_io_hps_io_usb1_inst_D1 (usb1_d[1]), + .sys_hps_hps_io_hps_io_usb1_inst_D2 (usb1_d[2]), + .sys_hps_hps_io_hps_io_usb1_inst_D3 (usb1_d[3]), + .sys_hps_hps_io_hps_io_usb1_inst_D4 (usb1_d[4]), + .sys_hps_hps_io_hps_io_usb1_inst_D5 (usb1_d[5]), + .sys_hps_hps_io_hps_io_usb1_inst_D6 (usb1_d[6]), + .sys_hps_hps_io_hps_io_usb1_inst_D7 (usb1_d[7]), + .sys_hps_hps_io_hps_io_usb1_inst_CLK (usb1_clk), + .sys_hps_hps_io_hps_io_usb1_inst_STP (usb1_stp), + .sys_hps_hps_io_hps_io_usb1_inst_DIR (usb1_dir), + .sys_hps_hps_io_hps_io_usb1_inst_NXT (usb1_nxt), + + .sys_hps_hps_io_hps_io_uart0_inst_RX (uart0_rx), + .sys_hps_hps_io_hps_io_uart0_inst_TX (uart0_tx), + + .sys_hps_hps_io_hps_io_spim1_inst_CLK (spim1_clk), + .sys_hps_hps_io_hps_io_spim1_inst_MOSI (spim1_mosi), + .sys_hps_hps_io_hps_io_spim1_inst_MISO (spim1_miso), + .sys_hps_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0), + + .sys_hps_hps_io_hps_io_gpio_inst_GPIO09 (hps_conv_usb_n), + + .sys_gpio_bd_in_port (gpio_i[31:0]), + .sys_gpio_bd_out_port (gpio_o[31:0]), + .sys_gpio_in_export (gpio_i[63:32]), + .sys_gpio_out_export (gpio_o[63:32]), + + .ltc2308_spi_MISO (1'b0), + .ltc2308_spi_MOSI (), + .ltc2308_spi_SCLK (), + .ltc2308_spi_SS_n (1'b1), + + .axi_hdmi_tx_0_hdmi_if_h_clk (hdmi_out_clk), + .axi_hdmi_tx_0_hdmi_if_h24_hsync (hdmi_hsync), + .axi_hdmi_tx_0_hdmi_if_h24_vsync (hdmi_vsync), + .axi_hdmi_tx_0_hdmi_if_h24_data_e (hdmi_data_e), + .axi_hdmi_tx_0_hdmi_if_h24_data (hdmi_data)); + +endmodule diff --git a/projects/ad353xr/zed/Makefile b/projects/ad353xr/zed/Makefile new file mode 100644 index 0000000000..cb596f5b3f --- /dev/null +++ b/projects/ad353xr/zed/Makefile @@ -0,0 +1,23 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad353xR_zed + +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/zed/zed_system_constr.xdc +M_DEPS += ../../common/zed/zed_system_bd.tcl +M_DEPS += ../../../library/common/ad_iobuf.v + +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_hdmi_tx +LIB_DEPS += axi_i2s_adi +LIB_DEPS += axi_spdif_tx +LIB_DEPS += axi_sysid +LIB_DEPS += sysid_rom +LIB_DEPS += util_i2c_mixer + +include ../../scripts/project-xilinx.mk diff --git a/projects/ad353xr/zed/system_bd.tcl b/projects/ad353xr/zed/system_bd.tcl new file mode 100644 index 0000000000..7e763245b2 --- /dev/null +++ b/projects/ad353xr/zed/system_bd.tcl @@ -0,0 +1,16 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl + +set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt; + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +sysid_gen_sys_init_file diff --git a/projects/ad353xr/zed/system_constr.xdc b/projects/ad353xr/zed/system_constr.xdc new file mode 100644 index 0000000000..390407e6e4 --- /dev/null +++ b/projects/ad353xr/zed/system_constr.xdc @@ -0,0 +1,43 @@ +############################################################################### +## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# DAC SPI interface + +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports spi_sck] ; ## FMC-CLK1_P +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS33} [get_ports spi_sdi] ; ## FMC-LA01_N +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS33} [get_ports spi_sdo] ; ## FMC-LA01_P +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS33} [get_ports spi_csb] ; ## FMC-LA00_P + +# DAC GPIO interface +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports dac_ldacb] ; ## FMC-LA05_P +set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS33} [get_ports dac_resetb] ; ## FMC-LA10_N + +# Reconfigure the pins from Bank 34 and Bank 35 to use LVCMOS33 since VADJ must be set to 3.3V + +# otg +set_property IOSTANDARD LVCMOS33 [get_ports otg_vbusoc] + +# gpio (switches, leds and such) +set_property IOSTANDARD LVCMOS33 [get_ports gpio_bd[0]] ; ## BTNC +set_property IOSTANDARD LVCMOS33 [get_ports gpio_bd[1]] ; ## BTND +set_property IOSTANDARD LVCMOS33 [get_ports gpio_bd[2]] ; ## BTNL +set_property IOSTANDARD LVCMOS33 [get_ports gpio_bd[3]] ; ## BTNR +set_property IOSTANDARD LVCMOS33 [get_ports gpio_bd[4]] ; ## BTNU + +set_property IOSTANDARD LVCMOS33 [get_ports gpio_bd[11]] ; ## SW0 +set_property IOSTANDARD LVCMOS33 [get_ports gpio_bd[12]] ; ## SW1 +set_property IOSTANDARD LVCMOS33 [get_ports gpio_bd[13]] ; ## SW2 +set_property IOSTANDARD LVCMOS33 [get_ports gpio_bd[14]] ; ## SW3 +set_property IOSTANDARD LVCMOS33 [get_ports gpio_bd[15]] ; ## SW4 +set_property IOSTANDARD LVCMOS33 [get_ports gpio_bd[16]] ; ## SW5 +set_property IOSTANDARD LVCMOS33 [get_ports gpio_bd[17]] ; ## SW6 +set_property IOSTANDARD LVCMOS33 [get_ports gpio_bd[18]] ; ## SW7 + +set_property IOSTANDARD LVCMOS33 [get_ports gpio_bd[27]] ; ## XADC-GIO0 +set_property IOSTANDARD LVCMOS33 [get_ports gpio_bd[28]] ; ## XADC-GIO1 +set_property IOSTANDARD LVCMOS33 [get_ports gpio_bd[29]] ; ## XADC-GIO2 +set_property IOSTANDARD LVCMOS33 [get_ports gpio_bd[30]] ; ## XADC-GIO3 + +set_property IOSTANDARD LVCMOS33 [get_ports gpio_bd[31]] ; ## OTG-RESETN \ No newline at end of file diff --git a/projects/ad353xr/zed/system_project.tcl b/projects/ad353xr/zed/system_project.tcl new file mode 100644 index 0000000000..d9b8c1edc7 --- /dev/null +++ b/projects/ad353xr/zed/system_project.tcl @@ -0,0 +1,20 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project ad353xR_zed + +adi_project_files ad353xR_zed [list \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] + +set_property PROCESSING_ORDER LATE [get_files system_constr.xdc] + +adi_project_run ad353xR_zed diff --git a/projects/ad353xr/zed/system_top.v b/projects/ad353xr/zed/system_top.v new file mode 100644 index 0000000000..20806fd45a --- /dev/null +++ b/projects/ad353xr/zed/system_top.v @@ -0,0 +1,209 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [31:0] gpio_bd, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + + output spdif, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, + + input otg_vbusoc, + + output dac_resetb, + output dac_ldacb, + + input spi_sdi, + output spi_sdo, + output spi_sck, + output spi_csb +); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + + assign gpio_i[63:32] = gpio_o[63:32]; + + assign dac_resetb = gpio_o[33]; + assign dac_ldacb = gpio_o[34]; + + // instantiations + + ad_iobuf #( + .DATA_WIDTH (32) + ) i_iobuf ( + .dio_t (gpio_t[31:0]), + .dio_i (gpio_o[31:0]), + .dio_o (gpio_i[31:0]), + .dio_p (gpio_bd)); + + ad_iobuf #( + .DATA_WIDTH (2) + ) i_iic_mux_scl ( + .dio_t ({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .dio_i (iic_mux_scl_o_s), + .dio_o (iic_mux_scl_i_s), + .dio_p (iic_mux_scl)); + + ad_iobuf #( + .DATA_WIDTH (2) + ) i_iic_mux_sda ( + .dio_t ({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .dio_i (iic_mux_sda_o_s), + .dio_o (iic_mux_sda_i_s), + .dio_p (iic_mux_sda)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + + .spdif (spdif), + + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + + .otg_vbusoc (otg_vbusoc), + + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_sck), + .spi0_csn_0_o (spi_csb), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_sdi), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_sdo), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o ()); + +endmodule