diff --git a/.github/workflows/scripts/zephyr-hal.sh b/.github/workflows/scripts/zephyr-hal.sh
index 42b212ab5b9..8e37ec2282c 100644
--- a/.github/workflows/scripts/zephyr-hal.sh
+++ b/.github/workflows/scripts/zephyr-hal.sh
@@ -25,6 +25,8 @@ rm -rf ${hal_adi}/MAX/
# Create parent folder
mkdir -p ${hal_adi}/MAX/Libraries/CMSIS
+mkdir -p ${hal_adi}/MAX/Libraries/MAXUSB/include
+mkdir -p ${hal_adi}/MAX/Libraries/MAXUSB/src
mkdir -p ${hal_adi}/MAX/Libraries/PeriphDrivers
# Copy zephyr wrappers, system files and cmakefiles
@@ -38,11 +40,19 @@ cp -rf ${msdk}/Libraries/CMSIS/Include ${hal_adi}/MAX/Libraries/CMSIS/
cp -rf ${msdk}/Libraries/PeriphDrivers/Include ${hal_adi}/MAX/Libraries/PeriphDrivers/
cp -rf ${msdk}/Libraries/PeriphDrivers/Source ${hal_adi}/MAX/Libraries/PeriphDrivers/
+# Copy MAXUSB folder
+cp -rf ${msdk}/Libraries/MAXUSB/include/core ${hal_adi}/MAX/Libraries/MAXUSB/include/
+cp -rf ${msdk}/Libraries/MAXUSB/src/core ${hal_adi}/MAX/Libraries/MAXUSB/src/
+
# Remove unneeded files
rm -rf ${hal_adi}/MAX/Libraries/CMSIS/Device/Maxim/GCC
rm -rf ${hal_adi}/MAX/Libraries/CMSIS/Device/Maxim/MAX*/Source/IAR
rm -rf ${hal_adi}/MAX/Libraries/CMSIS/Device/Maxim/MAX*/Source/GCC
rm -rf ${hal_adi}/MAX/Libraries/CMSIS/Device/Maxim/MAX*/Source/ARM
+rm -rf ${hal_adi}/MAX/Libraries/MAXUSB/include/core/arm
+rm -rf ${hal_adi}/MAX/Libraries/MAXUSB/include/core/maxq
+rm -rf ${hal_adi}/MAX/Libraries/MAXUSB/src/core/arm
+rm -rf ${hal_adi}/MAX/Libraries/MAXUSB/src/core/maxq
# Check either dirty or clean
cd ${hal_adi}
diff --git a/Examples/MAX32655/Bluetooth/BLE_FreeRTOS/freertos_tickless.c b/Examples/MAX32655/Bluetooth/BLE_FreeRTOS/freertos_tickless.c
index 2a241b2791b..d4c9354954e 100644
--- a/Examples/MAX32655/Bluetooth/BLE_FreeRTOS/freertos_tickless.c
+++ b/Examples/MAX32655/Bluetooth/BLE_FreeRTOS/freertos_tickless.c
@@ -160,7 +160,7 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
/* Determine if we need to snapshot the PalBb clock */
if (schTimerActive) {
/* Snapshot the current WUT value with the PalBb clock */
- MXC_WUT_Store(MXC_WUT0);
+ MXC_WUT_StoreCount(MXC_WUT0);
preCapture = MXC_WUT_GetCount(MXC_WUT0);
schUsec = PalTimerGetExpTime();
@@ -176,7 +176,7 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
}
} else {
/* Snapshot the current WUT value */
- MXC_WUT_Edge(MXC_WUT0);
+ MXC_WUT_WaitForEdge(MXC_WUT0);
preCapture = MXC_WUT_GetCount(MXC_WUT0);
bleSleepTicks = 0;
schUsec = 0;
@@ -239,7 +239,7 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
}
/* Recalculate dsWutTicks for the FreeRTOS tick counter update */
- MXC_WUT_Edge(MXC_WUT0);
+ MXC_WUT_WaitForEdge(MXC_WUT0);
postCapture = MXC_WUT_GetCount(MXC_WUT0);
dsWutTicks = postCapture - preCapture;
diff --git a/Examples/MAX32655/Bluetooth/BLE_fit_FreeRTOS/freertos_tickless.c b/Examples/MAX32655/Bluetooth/BLE_fit_FreeRTOS/freertos_tickless.c
index 6113790adda..26528205fab 100644
--- a/Examples/MAX32655/Bluetooth/BLE_fit_FreeRTOS/freertos_tickless.c
+++ b/Examples/MAX32655/Bluetooth/BLE_fit_FreeRTOS/freertos_tickless.c
@@ -160,7 +160,7 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
/* Determine if we need to snapshot the PalBb clock */
if (schTimerActive) {
/* Snapshot the current WUT value with the PalBb clock */
- MXC_WUT_Store(MXC_WUT0);
+ MXC_WUT_StoreCount(MXC_WUT0);
preCapture = MXC_WUT_GetCount(MXC_WUT0);
schUsec = PalTimerGetExpTime();
@@ -176,7 +176,7 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
}
} else {
/* Snapshot the current WUT value */
- MXC_WUT_Edge(MXC_WUT0);
+ MXC_WUT_WaitForEdge(MXC_WUT0);
preCapture = MXC_WUT_GetCount(MXC_WUT0);
bleSleepTicks = 0;
schUsec = 0;
@@ -238,7 +238,7 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
}
/* Recalculate dsWutTicks for the FreeRTOS tick counter update */
- MXC_WUT_Edge(MXC_WUT0);
+ MXC_WUT_WaitForEdge(MXC_WUT0);
postCapture = MXC_WUT_GetCount(MXC_WUT0);
dsWutTicks = postCapture - preCapture;
diff --git a/Examples/MAX32655/Bluetooth/RF_Test/freertos_tickless.c b/Examples/MAX32655/Bluetooth/RF_Test/freertos_tickless.c
index e997be57d10..55a62dcc7e2 100644
--- a/Examples/MAX32655/Bluetooth/RF_Test/freertos_tickless.c
+++ b/Examples/MAX32655/Bluetooth/RF_Test/freertos_tickless.c
@@ -135,10 +135,10 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
MXC_GPIO_OutSet(uart_rts.port, uart_rts.mask);
/* Snapshot the current WUT value */
- MXC_WUT_Edge(MXC_WUT0);
+ MXC_WUT_WaitForEdge(MXC_WUT0);
pre_capture = MXC_WUT_GetCount(MXC_WUT0);
MXC_WUT_SetCompare(MXC_WUT0, pre_capture + wut_ticks);
- MXC_WUT_Edge(MXC_WUT0);
+ MXC_WUT_WaitForEdge(MXC_WUT0);
LED_Off(1);
diff --git a/Examples/MAX32655/FreeRTOSDemo/freertos_tickless.c b/Examples/MAX32655/FreeRTOSDemo/freertos_tickless.c
index e997be57d10..55a62dcc7e2 100644
--- a/Examples/MAX32655/FreeRTOSDemo/freertos_tickless.c
+++ b/Examples/MAX32655/FreeRTOSDemo/freertos_tickless.c
@@ -135,10 +135,10 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
MXC_GPIO_OutSet(uart_rts.port, uart_rts.mask);
/* Snapshot the current WUT value */
- MXC_WUT_Edge(MXC_WUT0);
+ MXC_WUT_WaitForEdge(MXC_WUT0);
pre_capture = MXC_WUT_GetCount(MXC_WUT0);
MXC_WUT_SetCompare(MXC_WUT0, pre_capture + wut_ticks);
- MXC_WUT_Edge(MXC_WUT0);
+ MXC_WUT_WaitForEdge(MXC_WUT0);
LED_Off(1);
diff --git a/Examples/MAX32655/FreeRTOSDemo/main.c b/Examples/MAX32655/FreeRTOSDemo/main.c
index fb244caaee6..6a8aeb83259 100644
--- a/Examples/MAX32655/FreeRTOSDemo/main.c
+++ b/Examples/MAX32655/FreeRTOSDemo/main.c
@@ -352,7 +352,7 @@ int freertos_permit_tickless(void)
*/
void WUT_IRQHandler(void)
{
- MXC_WUT_IntClear(MXC_WUT0);
+ MXC_WUT_ClearFlags(MXC_WUT0);
NVIC_ClearPendingIRQ(WUT_IRQn);
}
diff --git a/Examples/MAX32655/WUT/main.c b/Examples/MAX32655/WUT/main.c
index 5178e4f3fe3..4d6343048fe 100644
--- a/Examples/MAX32655/WUT/main.c
+++ b/Examples/MAX32655/WUT/main.c
@@ -38,7 +38,7 @@
void WUT_IRQHandler(void)
{
- MXC_WUT_IntClear(MXC_WUT0);
+ MXC_WUT_ClearFlags(MXC_WUT0);
}
// *****************************************************************************
diff --git a/Examples/MAX32665/Bluetooth/BLE_FreeRTOS/freertos_tickless.c b/Examples/MAX32665/Bluetooth/BLE_FreeRTOS/freertos_tickless.c
index 6d09bf46b8f..8c773a53bbc 100644
--- a/Examples/MAX32665/Bluetooth/BLE_FreeRTOS/freertos_tickless.c
+++ b/Examples/MAX32665/Bluetooth/BLE_FreeRTOS/freertos_tickless.c
@@ -250,7 +250,7 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
/* Determine if we need to snapshot the PalBb clock */
if (schTimerActive) {
/* Snapshot the current WUT value with the PalBb clock */
- MXC_WUT_Store();
+ MXC_WUT_StoreCount();
preCapture = MXC_WUT_GetCount();
schUsec = PalTimerGetExpTime();
@@ -266,7 +266,7 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
}
} else {
/* Snapshot the current WUT value */
- MXC_WUT_Edge();
+ MXC_WUT_WaitForEdge();
preCapture = MXC_WUT_GetCount();
bleSleepTicks = 0;
schUsec = 0;
@@ -327,7 +327,7 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
}
/* Recalculate dsWutTicks for the FreeRTOS tick counter update */
- MXC_WUT_Edge();
+ MXC_WUT_WaitForEdge();
postCapture = MXC_WUT_GetCount();
dsWutTicks = postCapture - preCapture;
diff --git a/Examples/MAX32665/Bluetooth/BLE_FreeRTOS/stack_dats.c b/Examples/MAX32665/Bluetooth/BLE_FreeRTOS/stack_dats.c
index 3b057e84f47..363e2c6bc94 100644
--- a/Examples/MAX32665/Bluetooth/BLE_FreeRTOS/stack_dats.c
+++ b/Examples/MAX32665/Bluetooth/BLE_FreeRTOS/stack_dats.c
@@ -202,7 +202,7 @@ static void mainWsfInit(void)
/*************************************************************************************************/
void WUT_IRQHandler(void)
{
- MXC_WUT_IntClear();
+ MXC_WUT_ClearFlags();
NVIC_ClearPendingIRQ(WUT_IRQn);
MXC_WUT_Handler();
PalTimerIRQCallBack();
diff --git a/Examples/MAX32665/Bluetooth/RF_Test/freertos_tickless.c b/Examples/MAX32665/Bluetooth/RF_Test/freertos_tickless.c
index 7af8f83779a..de06b4097af 100644
--- a/Examples/MAX32665/Bluetooth/RF_Test/freertos_tickless.c
+++ b/Examples/MAX32665/Bluetooth/RF_Test/freertos_tickless.c
@@ -248,7 +248,7 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
/* Determine if we need to snapshot the PalBb clock */
if (schTimerActive) {
/* Snapshot the current WUT value with the PalBb clock */
- MXC_WUT_Store();
+ MXC_WUT_StoreCount();
preCapture = MXC_WUT_GetCount();
schUsec = PalTimerGetExpTime();
@@ -264,7 +264,7 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
}
} else {
/* Snapshot the current WUT value */
- MXC_WUT_Edge();
+ MXC_WUT_WaitForEdge();
preCapture = MXC_WUT_GetCount();
bleSleepTicks = 0;
schUsec = 0;
@@ -326,7 +326,7 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
}
/* Recalculate dsWutTicks for the FreeRTOS tick counter update */
- MXC_WUT_Edge();
+ MXC_WUT_WaitForEdge();
postCapture = MXC_WUT_GetCount();
dsWutTicks = postCapture - preCapture;
diff --git a/Examples/MAX32665/FreeRTOSDemo/freertos_tickless.c b/Examples/MAX32665/FreeRTOSDemo/freertos_tickless.c
index 90400009b40..f31a1d4500d 100644
--- a/Examples/MAX32665/FreeRTOSDemo/freertos_tickless.c
+++ b/Examples/MAX32665/FreeRTOSDemo/freertos_tickless.c
@@ -235,10 +235,10 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
MXC_GPIO_OutSet(uart_rts.port, uart_rts.mask);
/* Snapshot the current WUT value */
- MXC_WUT_Edge();
+ MXC_WUT_WaitForEdge();
pre_capture = MXC_WUT_GetCount();
MXC_WUT_SetCompare(pre_capture + wut_ticks);
- MXC_WUT_Edge();
+ MXC_WUT_WaitForEdge();
LED_Off(SLEEP_LED);
diff --git a/Examples/MAX32665/FreeRTOSDemo/main.c b/Examples/MAX32665/FreeRTOSDemo/main.c
index e1edac6d0fa..8e24abb4667 100644
--- a/Examples/MAX32665/FreeRTOSDemo/main.c
+++ b/Examples/MAX32665/FreeRTOSDemo/main.c
@@ -397,7 +397,7 @@ void turnOffUnused(void)
*/
void WUT_IRQHandler(void)
{
- MXC_WUT_IntClear();
+ MXC_WUT_ClearFlags();
NVIC_ClearPendingIRQ(WUT_IRQn);
}
diff --git a/Examples/MAX32665/WUT/main.c b/Examples/MAX32665/WUT/main.c
index 17bbb999f0a..576c7dff6b1 100644
--- a/Examples/MAX32665/WUT/main.c
+++ b/Examples/MAX32665/WUT/main.c
@@ -46,7 +46,7 @@
/***** Functions *****/
void WUT_IRQHandler(void)
{
- MXC_WUT_IntClear();
+ MXC_WUT_ClearFlags();
}
// *****************************************************************************
diff --git a/Examples/MAX32680/FreeRTOSDemo/freertos_tickless.c b/Examples/MAX32680/FreeRTOSDemo/freertos_tickless.c
index b0b67a415d3..3727ee9e38f 100644
--- a/Examples/MAX32680/FreeRTOSDemo/freertos_tickless.c
+++ b/Examples/MAX32680/FreeRTOSDemo/freertos_tickless.c
@@ -135,10 +135,10 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
MXC_GPIO_OutSet(uart_rts.port, uart_rts.mask);
/* Snapshot the current WUT value */
- MXC_WUT_Edge(MXC_WUT);
+ MXC_WUT_WaitForEdge(MXC_WUT);
pre_capture = MXC_WUT_GetCount(MXC_WUT);
MXC_WUT_SetCompare(MXC_WUT, pre_capture + wut_ticks);
- MXC_WUT_Edge(MXC_WUT);
+ MXC_WUT_WaitForEdge(MXC_WUT);
LED_Off(1);
diff --git a/Examples/MAX32680/FreeRTOSDemo/main.c b/Examples/MAX32680/FreeRTOSDemo/main.c
index c16f27ccc1f..a43f34682a2 100644
--- a/Examples/MAX32680/FreeRTOSDemo/main.c
+++ b/Examples/MAX32680/FreeRTOSDemo/main.c
@@ -349,7 +349,7 @@ int freertos_permit_tickless(void)
*/
void WUT_IRQHandler(void)
{
- MXC_WUT_IntClear(MXC_WUT);
+ MXC_WUT_ClearFlags(MXC_WUT);
NVIC_ClearPendingIRQ(WUT_IRQn);
}
diff --git a/Examples/MAX32680/WUT/main.c b/Examples/MAX32680/WUT/main.c
index 8e254c8988d..60d4fa1cc41 100644
--- a/Examples/MAX32680/WUT/main.c
+++ b/Examples/MAX32680/WUT/main.c
@@ -65,7 +65,7 @@ void setTrigger(int waitForTrigger)
void WUT_IRQHandler(void)
{
- MXC_WUT_IntClear(MXC_WUT);
+ MXC_WUT_ClearFlags(MXC_WUT);
}
// *****************************************************************************
diff --git a/Examples/MAX32690/Bluetooth/BLE_FreeRTOS/dats_main.c b/Examples/MAX32690/Bluetooth/BLE_FreeRTOS/dats_main.c
index 4987581980b..4e3e6fc638e 100644
--- a/Examples/MAX32690/Bluetooth/BLE_FreeRTOS/dats_main.c
+++ b/Examples/MAX32690/Bluetooth/BLE_FreeRTOS/dats_main.c
@@ -342,7 +342,7 @@ static void trimStart(void)
extern void wutTrimCb(int err);
/* Start the 32 kHz crystal trim procedure */
- err = MXC_WUT_TrimCrystalAsync(wutTrimCb);
+ err = MXC_WUT_TrimCrystalAsync(MXC_WUT0, wutTrimCb);
if (err != E_NO_ERROR) {
APP_TRACE_INFO1("Error starting 32kHz crystal trim %d", err);
}
diff --git a/Examples/MAX32690/Bluetooth/BLE_FreeRTOS/freertos_tickless.c b/Examples/MAX32690/Bluetooth/BLE_FreeRTOS/freertos_tickless.c
index 7f8b864d752..53b76ff2c04 100644
--- a/Examples/MAX32690/Bluetooth/BLE_FreeRTOS/freertos_tickless.c
+++ b/Examples/MAX32690/Bluetooth/BLE_FreeRTOS/freertos_tickless.c
@@ -60,7 +60,7 @@
int freertos_permit_tickless(void)
{
/* Can not disable BLE DBB and 32 MHz clock while trim procedure is ongoing */
- if (MXC_WUT_TrimPending() != E_NO_ERROR) {
+ if (MXC_WUT_TrimPending(MXC_WUT0) != E_NO_ERROR) {
return E_BUSY;
}
@@ -160,8 +160,8 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
/* Determine if we need to snapshot the PalBb clock */
if (schTimerActive) {
/* Snapshot the current WUT value with the PalBb clock */
- MXC_WUT_Store();
- preCapture = MXC_WUT_GetCount();
+ MXC_WUT_StoreCount(MXC_WUT0);
+ preCapture = MXC_WUT_GetCount(MXC_WUT0);
schUsec = PalTimerGetExpTime();
/* Adjust idleTicks for the time it takes to restart the BLE hardware */
@@ -176,8 +176,8 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
}
} else {
/* Snapshot the current WUT value */
- MXC_WUT_Edge();
- preCapture = MXC_WUT_GetCount();
+ MXC_WUT_WaitForEdge(MXC_WUT0);
+ preCapture = MXC_WUT_GetCount(MXC_WUT0);
bleSleepTicks = 0;
schUsec = 0;
}
@@ -221,7 +221,7 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
if (schTimerActive) {
/* Restore the BB counter */
- MXC_WUT_RestoreBBClock(BB_CLK_RATE_HZ);
+ MXC_WUT_RestoreBBClock(MXC_WUT0, BB_CLK_RATE_HZ);
/* Restart the BLE scheduler timer */
dsWutTicks = MXC_WUT->cnt - preCapture;
@@ -237,8 +237,8 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
}
/* Recalculate dsWutTicks for the FreeRTOS tick counter update */
- MXC_WUT_Edge();
- postCapture = MXC_WUT_GetCount();
+ MXC_WUT_WaitForEdge(MXC_WUT0);
+ postCapture = MXC_WUT_GetCount(MXC_WUT0);
dsWutTicks = postCapture - preCapture;
/*
diff --git a/Examples/MAX32690/Bluetooth/BLE_FreeRTOS/stack_dats.c b/Examples/MAX32690/Bluetooth/BLE_FreeRTOS/stack_dats.c
index 4d161efd20f..a478911ed61 100644
--- a/Examples/MAX32690/Bluetooth/BLE_FreeRTOS/stack_dats.c
+++ b/Examples/MAX32690/Bluetooth/BLE_FreeRTOS/stack_dats.c
@@ -279,7 +279,7 @@ void trim32k(void)
/* Execute the trim procedure */
wutTrimComplete = 0;
- if (MXC_WUT_TrimCrystalAsync(wutTrimCb) != E_NO_ERROR) {
+ if (MXC_WUT_TrimCrystalAsync(MXC_WUT0, wutTrimCb) != E_NO_ERROR) {
APP_TRACE_INFO0("Error with 32k trim");
} else {
while (!wutTrimComplete) {}
diff --git a/Examples/MAX32690/Bluetooth/BLE_datc/main.c b/Examples/MAX32690/Bluetooth/BLE_datc/main.c
index 974026c8523..ae3983a5d69 100644
--- a/Examples/MAX32690/Bluetooth/BLE_datc/main.c
+++ b/Examples/MAX32690/Bluetooth/BLE_datc/main.c
@@ -277,7 +277,7 @@ int main(void)
/* Execute the trim procedure */
wutTrimComplete = 0;
- MXC_WUT_TrimCrystalAsync(wutTrimCb);
+ MXC_WUT_TrimCrystalAsync(MXC_WUT0, wutTrimCb);
while (!wutTrimComplete) {}
/* Shutdown the 32 MHz crystal and the BLE DBB */
diff --git a/Examples/MAX32690/Bluetooth/BLE_dats/dats_main.c b/Examples/MAX32690/Bluetooth/BLE_dats/dats_main.c
index 385b79dc7ae..35ae6279283 100644
--- a/Examples/MAX32690/Bluetooth/BLE_dats/dats_main.c
+++ b/Examples/MAX32690/Bluetooth/BLE_dats/dats_main.c
@@ -403,7 +403,7 @@ static void trimStart(void)
extern void wutTrimCb(int err);
/* Start the 32 kHz crystal trim procedure */
- err = MXC_WUT_TrimCrystalAsync(wutTrimCb);
+ err = MXC_WUT_TrimCrystalAsync(MXC_WUT0, wutTrimCb);
if (err != E_NO_ERROR) {
APP_TRACE_INFO1("Error starting 32kHz crystal trim %d", err);
}
diff --git a/Examples/MAX32690/Bluetooth/BLE_dats/main.c b/Examples/MAX32690/Bluetooth/BLE_dats/main.c
index 43d033646e3..94f62ccbf4e 100644
--- a/Examples/MAX32690/Bluetooth/BLE_dats/main.c
+++ b/Examples/MAX32690/Bluetooth/BLE_dats/main.c
@@ -272,7 +272,7 @@ int main(void)
/* Execute the trim procedure */
wutTrimComplete = 0;
- MXC_WUT_TrimCrystalAsync(wutTrimCb);
+ MXC_WUT_TrimCrystalAsync(MXC_WUT0, wutTrimCb);
while (!wutTrimComplete) {}
/* Shutdown the 32 MHz crystal and the BLE DBB */
diff --git a/Examples/MAX32690/Bluetooth/BLE_fit/main.c b/Examples/MAX32690/Bluetooth/BLE_fit/main.c
index 170005b548d..1cec080a019 100644
--- a/Examples/MAX32690/Bluetooth/BLE_fit/main.c
+++ b/Examples/MAX32690/Bluetooth/BLE_fit/main.c
@@ -272,7 +272,7 @@ int main(void)
/* Execute the trim procedure */
wutTrimComplete = 0;
- MXC_WUT_TrimCrystalAsync(wutTrimCb);
+ MXC_WUT_TrimCrystalAsync(MXC_WUT0, wutTrimCb);
while (!wutTrimComplete) {}
/* Shutdown the 32 MHz crystal and the BLE DBB */
diff --git a/Examples/MAX32690/Bluetooth/BLE_otac/main.c b/Examples/MAX32690/Bluetooth/BLE_otac/main.c
index 2e4a0fbd036..2a63e84d709 100644
--- a/Examples/MAX32690/Bluetooth/BLE_otac/main.c
+++ b/Examples/MAX32690/Bluetooth/BLE_otac/main.c
@@ -273,7 +273,7 @@ int main(void)
/* Execute the trim procedure */
wutTrimComplete = 0;
- MXC_WUT_TrimCrystalAsync(wutTrimCb);
+ MXC_WUT_TrimCrystalAsync(MXC_WUT0, wutTrimCb);
while (!wutTrimComplete) {}
/* Shutdown the 32 MHz crystal and the BLE DBB */
diff --git a/Examples/MAX32690/Bluetooth/BLE_otas/dats_main.c b/Examples/MAX32690/Bluetooth/BLE_otas/dats_main.c
index e1748d10954..b201a6f1044 100644
--- a/Examples/MAX32690/Bluetooth/BLE_otas/dats_main.c
+++ b/Examples/MAX32690/Bluetooth/BLE_otas/dats_main.c
@@ -349,7 +349,7 @@ static void trimStart(void)
extern void wutTrimCb(int err);
/* Start the 32 kHz crystal trim procedure */
- err = MXC_WUT_TrimCrystalAsync(wutTrimCb);
+ err = MXC_WUT_TrimCrystalAsync(MXC_WUT0, wutTrimCb);
if (err != E_NO_ERROR) {
APP_TRACE_INFO1("Error starting 32kHz crystal trim %d", err);
}
diff --git a/Examples/MAX32690/Bluetooth/BLE_otas/main.c b/Examples/MAX32690/Bluetooth/BLE_otas/main.c
index e1a07935747..ac69bee4a59 100644
--- a/Examples/MAX32690/Bluetooth/BLE_otas/main.c
+++ b/Examples/MAX32690/Bluetooth/BLE_otas/main.c
@@ -276,7 +276,7 @@ int main(void)
/* Execute the trim procedure */
wutTrimComplete = 0;
- MXC_WUT_TrimCrystalAsync(wutTrimCb);
+ MXC_WUT_TrimCrystalAsync(MXC_WUT0, wutTrimCb);
while (!wutTrimComplete) {}
/* Stop here to measure the 32 kHz clock */
diff --git a/Examples/MAX32690/Bluetooth/RF_Test/freertos_tickless.c b/Examples/MAX32690/Bluetooth/RF_Test/freertos_tickless.c
index cc9813c097e..d910bc4972b 100644
--- a/Examples/MAX32690/Bluetooth/RF_Test/freertos_tickless.c
+++ b/Examples/MAX32690/Bluetooth/RF_Test/freertos_tickless.c
@@ -60,7 +60,7 @@
int freertos_permit_tickless(void)
{
/* Can not disable BLE DBB and 32 MHz clock while trim procedure is ongoing */
- if (MXC_WUT_TrimPending() != E_NO_ERROR) {
+ if (MXC_WUT_TrimPending(MXC_WUT0) != E_NO_ERROR) {
return E_BUSY;
}
@@ -160,8 +160,8 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
/* Determine if we need to snapshot the PalBb clock */
if (schTimerActive) {
/* Snapshot the current WUT value with the PalBb clock */
- MXC_WUT_Store();
- preCapture = MXC_WUT_GetCount();
+ MXC_WUT_StoreCount(MXC_WUT0);
+ preCapture = MXC_WUT_GetCount(MXC_WUT0);
schUsec = PalTimerGetExpTime();
/* Adjust idleTicks for the time it takes to restart the BLE hardware */
@@ -176,8 +176,8 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
}
} else {
/* Snapshot the current WUT value */
- MXC_WUT_Edge();
- preCapture = MXC_WUT_GetCount();
+ MXC_WUT_WaitForEdge(MXC_WUT0);
+ preCapture = MXC_WUT_GetCount(MXC_WUT0);
bleSleepTicks = 0;
schUsec = 0;
}
@@ -222,7 +222,7 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
PalBbRestore();
/* Restore the BB counter */
- MXC_WUT_RestoreBBClock(BB_CLK_RATE_HZ);
+ MXC_WUT_RestoreBBClock(MXC_WUT0, BB_CLK_RATE_HZ);
/* Restart the BLE scheduler timer */
dsWutTicks = MXC_WUT->cnt - preCapture;
@@ -238,8 +238,8 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
}
/* Recalculate dsWutTicks for the FreeRTOS tick counter update */
- MXC_WUT_Edge();
- postCapture = MXC_WUT_GetCount();
+ MXC_WUT_WaitForEdge(MXC_WUT0);
+ postCapture = MXC_WUT_GetCount(MXC_WUT0);
dsWutTicks = postCapture - preCapture;
/*
diff --git a/Examples/MAX32690/FreeRTOSDemo/freertos_tickless.c b/Examples/MAX32690/FreeRTOSDemo/freertos_tickless.c
index 6fc84f7cc72..328b50a6a12 100644
--- a/Examples/MAX32690/FreeRTOSDemo/freertos_tickless.c
+++ b/Examples/MAX32690/FreeRTOSDemo/freertos_tickless.c
@@ -67,7 +67,7 @@ __attribute__((weak)) int freertos_permit_tickless(void)
*/
void wutHitSnooze(void)
{
- wutSnooze = MXC_WUT_GetCount() + MAX_WUT_SNOOZE;
+ wutSnooze = MXC_WUT_GetCount(MXC_WUT0) + MAX_WUT_SNOOZE;
wutSnoozeValid = 1;
}
@@ -108,7 +108,7 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
}
/* Check the WUT snooze */
- if (wutSnoozeValid && (MXC_WUT_GetCount() < wutSnooze)) {
+ if (wutSnoozeValid && (MXC_WUT_GetCount(MXC_WUT0) < wutSnooze)) {
/* Finish out the rest of this tick with normal sleep */
MXC_LP_EnterSleepMode();
return;
@@ -134,16 +134,16 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
MXC_GPIO_OutSet(uart_rts.port, uart_rts.mask);
/* Snapshot the current WUT value */
- MXC_WUT_Edge();
- pre_capture = MXC_WUT_GetCount();
- MXC_WUT_SetCompare(pre_capture + wut_ticks);
- MXC_WUT_Edge();
+ MXC_WUT_WaitForEdge(MXC_WUT0);
+ pre_capture = MXC_WUT_GetCount(MXC_WUT0);
+ MXC_WUT_SetCompare(MXC_WUT0, pre_capture + wut_ticks);
+ MXC_WUT_WaitForEdge(MXC_WUT0);
LED_Off(1);
MXC_LP_EnterStandbyMode();
- post_capture = MXC_WUT_GetCount();
+ post_capture = MXC_WUT_GetCount(MXC_WUT0);
actual_ticks = post_capture - pre_capture;
LED_On(1);
diff --git a/Examples/MAX32690/FreeRTOSDemo/main.c b/Examples/MAX32690/FreeRTOSDemo/main.c
index afcb26f51f9..a4a7c4862b6 100644
--- a/Examples/MAX32690/FreeRTOSDemo/main.c
+++ b/Examples/MAX32690/FreeRTOSDemo/main.c
@@ -345,7 +345,7 @@ int freertos_permit_tickless(void)
*/
void WUT_IRQHandler(void)
{
- MXC_WUT_IntClear();
+ MXC_WUT_ClearFlags(MXC_WUT0);
NVIC_ClearPendingIRQ(WUT0_IRQn);
}
@@ -374,7 +374,7 @@ int main(void)
#if configUSE_TICKLESS_IDLE
/* Initialize Wakeup timer */
- MXC_WUT_Init(MXC_WUT_PRES_1);
+ MXC_WUT_Init(MXC_WUT0, MXC_WUT_PRES_1);
mxc_wut_cfg_t wut_cfg;
wut_cfg.mode = MXC_WUT_MODE_COMPARE;
wut_cfg.cmp_cnt = 0xFFFFFFFF;
@@ -386,8 +386,8 @@ int main(void)
NVIC_EnableIRQ(WUT_IRQn);
/* Configure and start the WUT */
- MXC_WUT_Config(&wut_cfg);
- MXC_WUT_Enable();
+ MXC_WUT_Config(MXC_WUT0, &wut_cfg);
+ MXC_WUT_Enable(MXC_WUT0);
/* Setup CTS interrupt */
MXC_GPIO_IntConfig(&uart_cts, MXC_GPIO_INT_FALLING);
diff --git a/Examples/MAX32690/WUT/main.c b/Examples/MAX32690/WUT/main.c
index 5b021919efa..15e1c875c50 100644
--- a/Examples/MAX32690/WUT/main.c
+++ b/Examples/MAX32690/WUT/main.c
@@ -57,7 +57,7 @@ void setTrigger(int waitForTrigger)
void WUT0_IRQHandler(void)
{
- MXC_WUT_IntClear();
+ MXC_WUT_ClearFlags(MXC_WUT0);
}
int main(void)
@@ -75,15 +75,15 @@ int main(void)
printf("wakeup timer to wake the device in %d Miliseconds.\n\n", MILLISECONDS_WUT);
// Initialize WUT
- MXC_WUT_Init(MXC_WUT_PRES_1);
+ MXC_WUT_Init(MXC_WUT0, MXC_WUT_PRES_1);
// Get ticks based off of milliseconds
- MXC_WUT_GetTicks(MILLISECONDS_WUT, MXC_WUT_UNIT_MILLISEC, &ticks);
+ MXC_WUT_GetTicks(MXC_WUT0, MILLISECONDS_WUT, MXC_WUT_UNIT_MILLISEC, &ticks);
// Config WUT
cfg.mode = MXC_WUT_MODE_ONESHOT;
cfg.cmp_cnt = ticks;
- MXC_WUT_Config(&cfg);
+ MXC_WUT_Config(MXC_WUT0, &cfg);
NVIC_EnableIRQ(WUT0_IRQn);
// Enable WUT wakeup event
@@ -95,7 +95,7 @@ int main(void)
// Start WUT
printf("Entering SLEEP mode.\n");
- MXC_WUT_Enable();
+ MXC_WUT_Enable(MXC_WUT0);
// Put the chip to sleep
MXC_LP_EnterSleepMode();
diff --git a/Examples/MAX78000/CNN/kws20_demo/main.c b/Examples/MAX78000/CNN/kws20_demo/main.c
index ed8fffa6e3c..e489df1e905 100644
--- a/Examples/MAX78000/CNN/kws20_demo/main.c
+++ b/Examples/MAX78000/CNN/kws20_demo/main.c
@@ -258,7 +258,7 @@ int32_t tot_usec = -100000;
void WUT_IRQHandler(void)
{
i2s_flag = 1;
- MXC_WUT_IntClear();
+ MXC_WUT_ClearFlags();
tot_usec += WUT_USEC;
//LED_On(LED2);
diff --git a/Examples/MAX78000/FreeRTOSDemo/freertos_tickless.c b/Examples/MAX78000/FreeRTOSDemo/freertos_tickless.c
index 6fc84f7cc72..8ed03566b50 100644
--- a/Examples/MAX78000/FreeRTOSDemo/freertos_tickless.c
+++ b/Examples/MAX78000/FreeRTOSDemo/freertos_tickless.c
@@ -134,10 +134,10 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
MXC_GPIO_OutSet(uart_rts.port, uart_rts.mask);
/* Snapshot the current WUT value */
- MXC_WUT_Edge();
+ MXC_WUT_WaitForEdge();
pre_capture = MXC_WUT_GetCount();
MXC_WUT_SetCompare(pre_capture + wut_ticks);
- MXC_WUT_Edge();
+ MXC_WUT_WaitForEdge();
LED_Off(1);
diff --git a/Examples/MAX78000/FreeRTOSDemo/main.c b/Examples/MAX78000/FreeRTOSDemo/main.c
index 80f2dd4bfa1..55651e35dfa 100644
--- a/Examples/MAX78000/FreeRTOSDemo/main.c
+++ b/Examples/MAX78000/FreeRTOSDemo/main.c
@@ -345,7 +345,7 @@ int freertos_permit_tickless(void)
*/
void WUT_IRQHandler(void)
{
- MXC_WUT_IntClear();
+ MXC_WUT_ClearFlags();
NVIC_ClearPendingIRQ(WUT_IRQn);
}
diff --git a/Examples/MAX78000/UART/main.c b/Examples/MAX78000/UART/main.c
index 1250a042d04..b46e4a4628d 100644
--- a/Examples/MAX78000/UART/main.c
+++ b/Examples/MAX78000/UART/main.c
@@ -102,8 +102,13 @@ int main(void)
printf("-->Example Failed\n");
return error;
}
-
+#if defined(BOARD_EVKIT_V1)
if ((error = MXC_UART_Init(WRITING_UART, UART_BAUD, MXC_UART_APB_CLK)) != E_NO_ERROR) {
+#elif defined(BOARD_FTHR_REVA)
+ // We define UART3(LPUART) as WRITING_UART for FTHR Board.
+ // LPUART can use IBRO and ERTCO clocks.
+ if ((error = MXC_UART_Init(WRITING_UART, UART_BAUD, MXC_UART_IBRO_CLK)) != E_NO_ERROR) {
+#endif
printf("-->Error initializing UART: %d\n", error);
printf("-->Example Failed\n");
return error;
diff --git a/Examples/MAX78000/WUT/main.c b/Examples/MAX78000/WUT/main.c
index bef18b4e320..05bf06b7adc 100644
--- a/Examples/MAX78000/WUT/main.c
+++ b/Examples/MAX78000/WUT/main.c
@@ -65,7 +65,7 @@ void setTrigger(int waitForTrigger)
void WUT_IRQHandler(void)
{
- MXC_WUT_IntClear();
+ MXC_WUT_ClearFlags();
}
// *****************************************************************************
diff --git a/Examples/MAX78002/CNN/facial_recognition/main.c b/Examples/MAX78002/CNN/facial_recognition/main.c
index 11f1e1bfbd5..5797e39fec6 100644
--- a/Examples/MAX78002/CNN/facial_recognition/main.c
+++ b/Examples/MAX78002/CNN/facial_recognition/main.c
@@ -226,7 +226,7 @@ area_t area_2 = { 0, 260, 80, 30 };
void WUT_IRQHandler(void)
{
- MXC_WUT_IntClear();
+ MXC_WUT_ClearFlags();
}
uint32_t ticks_1;
diff --git a/Examples/MAX78002/CNN/kws20_demo/main.c b/Examples/MAX78002/CNN/kws20_demo/main.c
index 21bc8e5975c..116ee7ff385 100644
--- a/Examples/MAX78002/CNN/kws20_demo/main.c
+++ b/Examples/MAX78002/CNN/kws20_demo/main.c
@@ -206,7 +206,7 @@ int32_t tot_usec = -100000;
void WUT_IRQHandler(void)
{
i2s_flag = 1;
- MXC_WUT_IntClear();
+ MXC_WUT_ClearFlags();
tot_usec += WUT_USEC;
}
diff --git a/Examples/MAX78002/FreeRTOSDemo/freertos_tickless.c b/Examples/MAX78002/FreeRTOSDemo/freertos_tickless.c
index 6fc84f7cc72..8ed03566b50 100644
--- a/Examples/MAX78002/FreeRTOSDemo/freertos_tickless.c
+++ b/Examples/MAX78002/FreeRTOSDemo/freertos_tickless.c
@@ -134,10 +134,10 @@ void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime)
MXC_GPIO_OutSet(uart_rts.port, uart_rts.mask);
/* Snapshot the current WUT value */
- MXC_WUT_Edge();
+ MXC_WUT_WaitForEdge();
pre_capture = MXC_WUT_GetCount();
MXC_WUT_SetCompare(pre_capture + wut_ticks);
- MXC_WUT_Edge();
+ MXC_WUT_WaitForEdge();
LED_Off(1);
diff --git a/Examples/MAX78002/FreeRTOSDemo/main.c b/Examples/MAX78002/FreeRTOSDemo/main.c
index 80f2dd4bfa1..55651e35dfa 100644
--- a/Examples/MAX78002/FreeRTOSDemo/main.c
+++ b/Examples/MAX78002/FreeRTOSDemo/main.c
@@ -345,7 +345,7 @@ int freertos_permit_tickless(void)
*/
void WUT_IRQHandler(void)
{
- MXC_WUT_IntClear();
+ MXC_WUT_ClearFlags();
NVIC_ClearPendingIRQ(WUT_IRQn);
}
diff --git a/Examples/MAX78002/WUT/main.c b/Examples/MAX78002/WUT/main.c
index 99fca7157ad..3305052e43d 100644
--- a/Examples/MAX78002/WUT/main.c
+++ b/Examples/MAX78002/WUT/main.c
@@ -66,7 +66,7 @@ void setTrigger(int waitForTrigger)
void WUT_IRQHandler(void)
{
- MXC_WUT_IntClear();
+ MXC_WUT_ClearFlags();
}
// *****************************************************************************
diff --git a/Libraries/BlePhy/MAX32665/libphy.a b/Libraries/BlePhy/MAX32665/libphy.a
index 012c56a7d88..29d3f5c98be 100644
Binary files a/Libraries/BlePhy/MAX32665/libphy.a and b/Libraries/BlePhy/MAX32665/libphy.a differ
diff --git a/Libraries/BlePhy/MAX32665/libphy_hard.a b/Libraries/BlePhy/MAX32665/libphy_hard.a
index 16756f51441..d97edfd8fe4 100644
Binary files a/Libraries/BlePhy/MAX32665/libphy_hard.a and b/Libraries/BlePhy/MAX32665/libphy_hard.a differ
diff --git a/Libraries/CMSIS/Device/Maxim/GCC/mxc_version.mk b/Libraries/CMSIS/Device/Maxim/GCC/mxc_version.mk
index cde4ab47d13..bd0ef8389cf 100644
--- a/Libraries/CMSIS/Device/Maxim/GCC/mxc_version.mk
+++ b/Libraries/CMSIS/Device/Maxim/GCC/mxc_version.mk
@@ -16,7 +16,7 @@
#
##############################################################################
# Autogenerated version info for build system.
-MSDK_VERSION_STRING := v2023_10-307-gf557dbf1716
+MSDK_VERSION_STRING := v2023_10-333-ga03f3f8b2f8
MSDK_VERSION_YEAR := 2023
MSDK_VERSION_MONTH := 10
diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/max32655.svd b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/max32655.svd
index fe453eda1b2..f4aadcba9ed 100644
--- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/max32655.svd
+++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/max32655.svd
@@ -11168,6 +11168,12 @@
14
1
+
+ ASYNC
+ Allows asynchronous reads of the PWM and CNT registers.
+ 15
+ 1
+
CLKSEL_B
Timer Clock Select for Timer B
diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/tmr_regs.h
index 55a40a62d91..339d28299e3 100644
--- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/tmr_regs.h
+++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/tmr_regs.h
@@ -383,6 +383,9 @@ typedef struct {
#define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */
#define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */
+#define MXC_F_TMR_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */
+#define MXC_F_TMR_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */
+
#define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */
#define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */
diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd
index 0beab42655e..919cf24974d 100644
--- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd
+++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd
@@ -10081,6 +10081,12 @@
14
1
+
+ ASYNC
+ Allows asynchronous reads to the PWM and CNT registers.
+ 15
+ 1
+
CLKSEL_B
Timer Clock Select for Timer B
diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h
index 0a086a133b4..ba6e6fac685 100644
--- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h
+++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h
@@ -38,7 +38,7 @@ extern "C" {
Update if use of this oscillator requires precise timing.*/
/* NOTE: INRO was previously named NANORING */
#ifndef INRO_FREQ
-#define INRO_FREQ 100000
+#define INRO_FREQ 131000
#endif
#ifndef IPO_FREQ
diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h
index 94bf7f6dfcb..b1fe8a68d0f 100644
--- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h
+++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h
@@ -381,6 +381,9 @@ typedef struct {
#define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */
#define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */
+#define MXC_F_TMR_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */
+#define MXC_F_TMR_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */
+
#define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */
#define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */
diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c
index b286490f621..48e262b7ae5 100644
--- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c
+++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c
@@ -81,10 +81,9 @@ __weak void SystemCoreClockUpdate(void)
case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO:
base_freq = ERTCO_FREQ;
break;
- // case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK:
- // base_freq = EXTCLK_FREQ;
- // break;
- // TODO(JC): ^^^ Uncomment when EXTCLK register definition is added
+ case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK:
+ base_freq = EXTCLK_FREQ;
+ break;
default:
// Codes 001 and 111 are reserved.
// This code should never execute, however, initialize to safe value.
diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.svd b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.svd
index e9dc97607e2..fa418eaef48 100644
--- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.svd
+++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.svd
@@ -8541,6 +8541,12 @@
14
1
+
+ ASYNC
+ Allows asynchronous reads to the PWM and CNT registers.
+ 15
+ 1
+
CLKSEL_B
Timer Clock Select for Timer B
diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/tmr_regs.h
index 7e88a04ed02..436c2ab548d 100644
--- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/tmr_regs.h
+++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/tmr_regs.h
@@ -383,6 +383,9 @@ typedef struct {
#define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */
#define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */
+#define MXC_F_TMR_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */
+#define MXC_F_TMR_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */
+
#define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */
#define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */
diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.svd b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.svd
index 98e5cbfeace..b8b9b253990 100644
--- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.svd
+++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.svd
@@ -11666,6 +11666,12 @@
14
1
+
+ ASYNC
+ Allows asynchronous reads to the PWM and CNT registers.
+ 15
+ 1
+
CLKSEL_B
Timer Clock Select for Timer B
diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/tmr_regs.h
index 5bb43b39acf..b2838ddfd77 100644
--- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/tmr_regs.h
+++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/tmr_regs.h
@@ -383,6 +383,9 @@ typedef struct {
#define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */
#define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */
+#define MXC_F_TMR_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */
+#define MXC_F_TMR_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */
+
#define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */
#define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */
diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/max32675.svd b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/max32675.svd
index a1951f062f0..e08e5782812 100644
--- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/max32675.svd
+++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/max32675.svd
@@ -8547,6 +8547,12 @@
14
1
+
+ ASYNC
+ Allows asynchronous reads to the PWM and CNT registers.
+ 15
+ 1
+
CLKSEL_B
Timer Clock Select for Timer B
diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/tmr_regs.h
index 9fc3e78122f..2b4abe9e83a 100644
--- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/tmr_regs.h
+++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/tmr_regs.h
@@ -383,6 +383,9 @@ typedef struct {
#define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */
#define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */
+#define MXC_F_TMR_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */
+#define MXC_F_TMR_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */
+
#define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */
#define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */
diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/max32690.svd b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/max32690.svd
index 5a67f4cede8..6a19424aafe 100644
--- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/max32690.svd
+++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/max32690.svd
@@ -19454,6 +19454,12 @@ signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is se
14
1
+
+ ASYNC
+ Allows asynchronous reads of the PWM and CNT registers.
+ 15
+ 1
+
CLKSEL_B
Timer Clock Select for Timer B
diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/tmr_regs.h
index 3d01330a99b..88f7530e2bf 100644
--- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/tmr_regs.h
+++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/tmr_regs.h
@@ -383,6 +383,9 @@ typedef struct {
#define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */
#define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */
+#define MXC_F_TMR_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */
+#define MXC_F_TMR_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */
+
#define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */
#define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */
diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/max78000.svd b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/max78000.svd
index 3ea4a1309c7..97003bf57c3 100644
--- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/max78000.svd
+++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/max78000.svd
@@ -11101,6 +11101,12 @@
14
1
+
+ ASYNC
+ Allows asynchronous reads of the PWM and CNT registers.
+ 15
+ 1
+
CLKSEL_B
Timer Clock Select for Timer B
diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/tmr_regs.h
index 33e8ce74a0e..cbd908bcfdb 100644
--- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/tmr_regs.h
+++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/tmr_regs.h
@@ -383,6 +383,9 @@ typedef struct {
#define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */
#define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */
+#define MXC_F_TMR_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */
+#define MXC_F_TMR_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */
+
#define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */
#define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */
diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/max78002.svd b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/max78002.svd
index 0919269cd44..8ce8846d2ba 100644
--- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/max78002.svd
+++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/max78002.svd
@@ -16842,6 +16842,12 @@ signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is se
14
1
+
+ ASYNC
+ Allows asynchronous reads of the PWM and CNT registers.
+ 15
+ 1
+
CLKSEL_B
Timer Clock Select for Timer B
diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/tmr_regs.h
index 013b23f71e7..147ec9381d4 100644
--- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/tmr_regs.h
+++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/tmr_regs.h
@@ -383,6 +383,9 @@ typedef struct {
#define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */
#define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */
+#define MXC_F_TMR_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */
+#define MXC_F_TMR_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */
+
#define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */
#define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */
diff --git a/Libraries/Cordio/platform/targets/maxim/max32665/sources/pal_rtc.c b/Libraries/Cordio/platform/targets/maxim/max32665/sources/pal_rtc.c
index 6fd97885be9..45bd54861a7 100644
--- a/Libraries/Cordio/platform/targets/maxim/max32665/sources/pal_rtc.c
+++ b/Libraries/Cordio/platform/targets/maxim/max32665/sources/pal_rtc.c
@@ -64,7 +64,7 @@ static struct {
__attribute__((weak)) void WUT_IRQHandler(void)
{
PalLedOn(PAL_LED_ID_CPU_ACTIVE);
- MXC_WUT_IntClear();
+ MXC_WUT_ClearFlags();
NVIC_ClearPendingIRQ(WUT_IRQn);
}
diff --git a/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_rtc.c b/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_rtc.c
index 56508753209..34f0c97ac5f 100644
--- a/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_rtc.c
+++ b/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_rtc.c
@@ -69,14 +69,14 @@ static struct {
void WUT0_IRQHandler(void)
{
PalLedOn(PAL_LED_ID_CPU_ACTIVE);
- MXC_WUT_Handler();
+ MXC_WUT_Handler(PAL_WUT);
}
#else
void WUT1_IRQHandler(void)
{
PalLedOn(PAL_LED_ID_CPU_ACTIVE);
- MXC_WUT_Handler();
+ MXC_WUT_Handler(PAL_WUT);
}
#endif
@@ -102,7 +102,7 @@ PalRtcState_t PalRtcGetState(void)
/*************************************************************************************************/
void PalRtcCompareSet(uint8_t channelId, uint32_t value)
{
- MXC_WUT_SetCompare(value);
+ MXC_WUT_SetCompare(PAL_WUT, value);
}
/*************************************************************************************************/
@@ -117,15 +117,15 @@ void PalRtcInit(void)
cfg.mode = MXC_WUT_MODE_COMPARE;
cfg.cmp_cnt = PAL_MAX_RTC_COUNTER_VAL;
- MXC_WUT_Init(MXC_WUT_PRES_1);
- MXC_WUT_Config(&cfg);
+ MXC_WUT_Init(PAL_WUT, MXC_WUT_PRES_1);
+ MXC_WUT_Config(PAL_WUT, &cfg);
MXC_LP_EnableWUTAlarmWakeup();
NVIC_ClearPendingIRQ(PAL_WUT_IRQn);
NVIC_EnableIRQ(PAL_WUT_IRQn);
/* Enable WUT */
- MXC_WUT_Enable();
+ MXC_WUT_Enable(PAL_WUT);
palRtcCb.state = PAL_RTC_STATE_READY;
}
@@ -142,7 +142,7 @@ void PalRtcInit(void)
/*************************************************************************************************/
uint32_t PalRtcCounterGet(void)
{
- uint32_t count = MXC_WUT_GetCount();
+ uint32_t count = MXC_WUT_GetCount(PAL_WUT);
return count;
}
@@ -168,6 +168,6 @@ void PalRtcEnableCompareIrq(uint8_t channelId)
/*************************************************************************************************/
void PalRtcDisableCompareIrq(uint8_t channelId)
{
- MXC_WUT_IntClear();
+ MXC_WUT_ClearFlags(PAL_WUT);
NVIC_DisableIRQ(PAL_WUT_IRQn);
}
diff --git a/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_sys.c b/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_sys.c
index 870544c17a5..54be4451b86 100644
--- a/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_sys.c
+++ b/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_sys.c
@@ -52,6 +52,7 @@
#include "wut.h"
#include "uart.h"
#include "sema.h"
+#include "dma.h"
/**************************************************************************************************
Macros
@@ -102,6 +103,76 @@ void PalExitCs(void)
__enable_irq();
}
+/*************************************************************************************************/
+/*!
+ * \brief DMA interrupt handlers.
+ */
+/*************************************************************************************************/
+void DMA0_IRQHandler(void)
+{
+ MXC_DMA_Handler(); /* DMA channel 0 is associated with DMA instance 0 */
+}
+void DMA1_IRQHandler(void)
+{
+ MXC_DMA_Handler(); /* DMA channel 1 is associated with DMA instance 0 */
+}
+void DMA2_IRQHandler(void)
+{
+ MXC_DMA_Handler(); /* DMA channel 2 is associated with DMA instance 0 */
+}
+void DMA3_IRQHandler(void)
+{
+ MXC_DMA_Handler(); /* DMA channel 3 is associated with DMA instance 0 */
+}
+void DMA4_IRQHandler(void)
+{
+ MXC_DMA_Handler(); /* DMA channel 4 is associated with DMA instance 0 */
+}
+void DMA5_IRQHandler(void)
+{
+ MXC_DMA_Handler(); /* DMA channel 5 is associated with DMA instance 0 */
+}
+void DMA6_IRQHandler(void)
+{
+ MXC_DMA_Handler(); /* DMA channel 6 is associated with DMA instance 0 */
+}
+void DMA7_IRQHandler(void)
+{
+ MXC_DMA_Handler(); /* DMA channel 7 is associated with DMA instance 0 */
+}
+void DMA8_IRQHandler(void)
+{
+ MXC_DMA_Handler(); /* DMA channel 8 is associated with DMA instance 0 */
+}
+void DMA9_IRQHandler(void)
+{
+ MXC_DMA_Handler(); /* DMA channel 9 is associated with DMA instance 0 */
+}
+void DMA10_IRQHandler(void)
+{
+ MXC_DMA_Handler(); /* DMA channel 10 is associated with DMA instance 0 */
+}
+void DMA11_IRQHandler(void)
+{
+ MXC_DMA_Handler(); /* DMA channel 11 is associated with DMA instance 0 */
+}
+void DMA12_IRQHandler(void)
+{
+ MXC_DMA_Handler(); /* DMA channel 12 is associated with DMA instance 0 */
+}
+void DMA13_IRQHandler(void)
+{
+ MXC_DMA_Handler(); /* DMA channel 13 is associated with DMA instance 0 */
+}
+void DMA14_IRQHandler(void)
+{
+ MXC_DMA_Handler(); /* DMA channel 14 is associated with DMA instance 0 */
+}
+void DMA15_IRQHandler(void)
+{
+ MXC_DMA_Handler(); /* DMA channel 15 is associated with DMA instance 0 */
+}
+
/*************************************************************************************************/
/*!
* \brief Common platform initialization.
diff --git a/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_uart.c b/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_uart.c
index 51f5af827af..aab5bec3b2d 100644
--- a/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_uart.c
+++ b/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_uart.c
@@ -38,8 +38,13 @@
#include "board.h"
#include "uart.h"
+#include "dma.h"
#include "sema.h"
+#include "uart_revb.h"
+
+#include "wsf_cs.h"
+
#include
/**************************************************************************************************
@@ -65,71 +70,12 @@
/*! \brief Control block. */
static struct {
PalUartState_t state;
- mxc_uart_req_t readReq;
- mxc_uart_req_t writeReq;
PalUartCompCback_t rdCback;
PalUartCompCback_t wrCback;
+ int writeCh;
+ int readCh;
} palUartCb[PAL_UARTS];
-/**************************************************************************************************
- Local Functions
-**************************************************************************************************/
-
-/*************************************************************************************************/
-/*!
- * \brief UART Interrupt handlers.
- *
- * \return None.
- */
-/*************************************************************************************************/
-void UART_CommonHandler(mxc_uart_regs_t *uart)
-{
- const int32_t err = MXC_UART_AsyncHandler(uart);
-
- if(err == E_INVALID)
- {
- const uint8_t uartIdx = MXC_UART_GET_IDX(uart);
-
- if( uartIdx == CONSOLE_UART || uartIdx == HCI_UART)
- {
- MXC_UART_ClearRXFIFO(uart);
- }
- else
- {
- PAL_SYS_ASSERT(err == E_NO_ERROR);
- }
- }
-
-}
-void UART0_IRQHandler(void)
-{
-
- PalLedOn(PAL_LED_ID_CPU_ACTIVE);
- UART_CommonHandler(MXC_UART0);
-
-}
-void UART1_IRQHandler(void)
-{
-
- PalLedOn(PAL_LED_ID_CPU_ACTIVE);
- UART_CommonHandler(MXC_UART1);
-
-}
-void UART2_IRQHandler(void)
-{
-
- PalLedOn(PAL_LED_ID_CPU_ACTIVE);
- UART_CommonHandler(MXC_UART2);
-
-}
-void UART3_IRQHandler(void)
-{
-
- PalLedOn(PAL_LED_ID_CPU_ACTIVE);
- UART_CommonHandler(MXC_UART3);
-
-}
-
/*************************************************************************************************/
/*!
* \brief Inter-processor communication interrupt handlers.
@@ -172,23 +118,30 @@ void RISCV_IRQHandler(void)
* \return None.
*/
/*************************************************************************************************/
-void palUartCallback(mxc_uart_req_t* req, int error)
+void palUartCallback(int ch, int error)
{
int i;
for(i = 0; i < PAL_UARTS; i++) {
/* Find the corresponding rqeuest and call the callback */
- if(req == &palUartCb[i].readReq) {
+
+ if((ch == palUartCb[i].readCh) && (palUartCb[i].state != PAL_UART_STATE_UNINIT)) {
+ palUartCb[i].readCh = -1;
if(palUartCb[i].rdCback != NULL) {
palUartCb[i].rdCback();
}
+
+ MXC_DMA_ReleaseChannel(ch);
return;
}
- if(req == &palUartCb[i].writeReq) {
+ if((ch == palUartCb[i].writeCh) && (palUartCb[i].state != PAL_UART_STATE_UNINIT)) {
+ palUartCb[i].writeCh = -1;
palUartCb[i].state = PAL_UART_STATE_READY;
if(palUartCb[i].wrCback != NULL) {
palUartCb[i].wrCback();
}
+
+ MXC_DMA_ReleaseChannel(ch);
return;
}
}
@@ -283,8 +236,8 @@ static void PalMailInit(const PalUartConfig_t *pCfg)
/*************************************************************************************************/
void PalUartInit(PalUartId_t id, const PalUartConfig_t *pCfg)
{
- uint8_t uartNum;
- int result;
+ uint8_t uartNum = palUartGetNum(id);
+ mxc_uart_regs_t *uart = MXC_UART_GET_UART(uartNum);
#if defined(HCI_TR_MAIL) && (HCI_TR_MAIL != 0)
if(id == PAL_UART_ID_CHCI) {
@@ -293,30 +246,50 @@ void PalUartInit(PalUartId_t id, const PalUartConfig_t *pCfg)
}
#endif
- uartNum = palUartGetNum(id);
-
PAL_SYS_ASSERT(palUartCb[uartNum].state == PAL_UART_STATE_UNINIT);
/* Save the callback */
palUartCb[uartNum].rdCback = pCfg->rdCback;
palUartCb[uartNum].wrCback = pCfg->wrCback;
+ palUartCb[uartNum].readCh = -1;
+ palUartCb[uartNum].writeCh = -1;
+
- result = MXC_UART_Init(MXC_UART_GET_UART(uartNum), pCfg->baud, MXC_UART_IBRO_CLK);
-
+ int result = MXC_UART_Init(uart, pCfg->baud, MXC_UART_IBRO_CLK);
(void)result;
PAL_SYS_ASSERT(result == 0);
- MXC_UART_SetDataSize(MXC_UART_GET_UART(uartNum), 8);
- MXC_UART_SetStopBits(MXC_UART_GET_UART(uartNum), MXC_UART_STOP_1);
- MXC_UART_SetParity(MXC_UART_GET_UART(uartNum), MXC_UART_PARITY_DISABLE);
+ /* Disable UART interrupts */
+ MXC_UART_DisableInt(uart, 0xFFFFFFFF);
+ MXC_UART_ClearFlags(uart, 0xFFFFFFFF);
+
+ MXC_UART_SetDataSize(uart, 8);
+ MXC_UART_SetStopBits(uart, MXC_UART_STOP_1);
+ MXC_UART_SetParity(uart, MXC_UART_PARITY_DISABLE);
if(pCfg->hwFlow) {
- MXC_UART_SetFlowCtrl(MXC_UART_GET_UART(uartNum), MXC_UART_FLOW_EN, 1);
+ MXC_UART_SetFlowCtrl(uart, MXC_UART_FLOW_EN, 1);
}
- const IRQn_Type uartIrqn = MXC_UART_GET_IRQ(uartNum);
- NVIC_ClearPendingIRQ(uartIrqn);
- NVIC_EnableIRQ(uartIrqn);
-
+ MXC_DMA_Init();
+
+ /* Enable the DMA channel interrupts */
+ NVIC_EnableIRQ(DMA0_IRQn);
+ NVIC_EnableIRQ(DMA1_IRQn);
+ NVIC_EnableIRQ(DMA2_IRQn);
+ NVIC_EnableIRQ(DMA3_IRQn);
+ NVIC_EnableIRQ(DMA4_IRQn);
+ NVIC_EnableIRQ(DMA5_IRQn);
+ NVIC_EnableIRQ(DMA6_IRQn);
+ NVIC_EnableIRQ(DMA7_IRQn);
+ NVIC_EnableIRQ(DMA8_IRQn);
+ NVIC_EnableIRQ(DMA9_IRQn);
+ NVIC_EnableIRQ(DMA10_IRQn);
+ NVIC_EnableIRQ(DMA11_IRQn);
+ NVIC_EnableIRQ(DMA12_IRQn);
+ NVIC_EnableIRQ(DMA13_IRQn);
+ NVIC_EnableIRQ(DMA14_IRQn);
+ NVIC_EnableIRQ(DMA15_IRQn);
+
palUartCb[uartNum].state = PAL_UART_STATE_READY;
}
@@ -334,13 +307,13 @@ void PalUartInit(PalUartId_t id, const PalUartConfig_t *pCfg)
void PalUartDeInit(PalUartId_t id)
{
uint8_t uartNum = palUartGetNum(id);
- int result;
- result = MXC_UART_Shutdown(MXC_UART_GET_UART(uartNum));
+ int result = MXC_UART_Shutdown(MXC_UART_GET_UART(uartNum));
(void)result;
PAL_SYS_ASSERT(result);
NVIC_DisableIRQ(MXC_UART_GET_IRQ(uartNum));
+ MXC_DMA_DeInit();
palUartCb[uartNum].state = PAL_UART_STATE_UNINIT;
}
@@ -378,9 +351,8 @@ PalUartState_t PalUartGetState(PalUartId_t id)
/*************************************************************************************************/
void PalUartReadData(PalUartId_t id, uint8_t *pData, uint16_t len)
{
- uint8_t uartNum;
- uint32_t irqn;
- int result;
+ uint8_t uartNum = palUartGetNum(id);
+ mxc_uart_regs_t* uart = MXC_UART_GET_UART(uartNum);
#if defined(HCI_TR_MAIL) && (HCI_TR_MAIL != 0)
if(id == PAL_UART_ID_CHCI) {
@@ -389,26 +361,69 @@ void PalUartReadData(PalUartId_t id, uint8_t *pData, uint16_t len)
}
#endif
- uartNum = palUartGetNum(id);
- irqn = MXC_UART_GET_IRQ(uartNum);
-
- palUartCb[uartNum].readReq.uart = MXC_UART_GET_UART(uartNum);
- palUartCb[uartNum].readReq.rxData = pData;
- palUartCb[uartNum].readReq.rxLen = len;
- palUartCb[uartNum].readReq.txLen = 0;
- palUartCb[uartNum].readReq.callback = palUartCallback;
+ WsfCsEnter();
+ int dmaCh = MXC_DMA_AcquireChannel();
+ WsfCsExit();
+
+ /* Save the channel number */
+ palUartCb[uartNum].readCh = dmaCh;
+
+ /* Setup the DMA transfer */
+ mxc_dma_config_t config = {
+ .ch = dmaCh,
+ .srcwd = MXC_DMA_WIDTH_BYTE,
+ .dstwd = MXC_DMA_WIDTH_BYTE,
+ .srcinc_en = 0,
+ .dstinc_en = 1
+ };
+
+ mxc_dma_srcdst_t srcdst = {
+ .ch = dmaCh,
+ .dest = (void*)pData,
+ .len = len
+ };
+
+ switch (uartNum) {
+ case 0:
+ config.reqsel = MXC_DMA_REQUEST_UART0RX;
+ break;
+
+ case 1:
+ config.reqsel = MXC_DMA_REQUEST_UART1RX;
+ break;
+
+ case 2:
+ config.reqsel = MXC_DMA_REQUEST_UART2RX;
+ break;
+
+ case 3:
+ config.reqsel = MXC_DMA_REQUEST_UART3RX;
+ break;
+
+ default:
+ PAL_SYS_ASSERT(0);
+ return;
+ }
- NVIC_DisableIRQ(irqn);
+ MXC_DMA_ConfigChannel(config, srcdst);
+ MXC_DMA_SetCallback(dmaCh, palUartCallback);
+
+ /* Enable Count-to-Zero (CTZ) interrupt */
+ MXC_DMA_EnableInt(dmaCh);
+ MXC_DMA_SetChannelInterruptEn(dmaCh, 0, 1);
- /* Start the read */
- result = MXC_UART_TransactionAsync(&palUartCb[uartNum].readReq);
- (void)result;
- PAL_SYS_ASSERT(result == E_SUCCESS);
+ /* Set Rx FIFO threshold */
+ uart->dma |= 1 << MXC_F_UART_REVB_DMA_RX_THD_VAL_POS;
+ /* Enable channel receiving */
+ uart->dma |= MXC_F_UART_REVB_DMA_RX_EN;
- /* Enable the interrupt */
- NVIC_EnableIRQ(irqn);
+ /* Start the transfer */
+ MXC_DMA_Start(dmaCh);
}
+
+
+
/*************************************************************************************************/
/*!
* \brief Write data to Tx FIFO.
@@ -424,10 +439,8 @@ void PalUartReadData(PalUartId_t id, uint8_t *pData, uint16_t len)
/*************************************************************************************************/
void PalUartWriteData(PalUartId_t id, const uint8_t *pData, uint16_t len)
{
- uint8_t uartNum;
- uint32_t irqn;
- int result;
-
+ uint8_t uartNum = palUartGetNum(id);
+ mxc_uart_regs_t* uart = MXC_UART_GET_UART(uartNum);
#if defined(HCI_TR_MAIL) && (HCI_TR_MAIL != 0)
if(id == PAL_UART_ID_CHCI) {
@@ -435,25 +448,63 @@ void PalUartWriteData(PalUartId_t id, const uint8_t *pData, uint16_t len)
return;
}
#endif
+
+ WsfCsEnter();
+ int dmaCh = MXC_DMA_AcquireChannel();
+ WsfCsExit();
- uartNum = palUartGetNum(id);
- irqn = MXC_UART_GET_IRQ(uartNum);
+ palUartCb[uartNum].writeCh = dmaCh;
+ palUartCb[uartNum].state = PAL_UART_STATE_BUSY;
- NVIC_DisableIRQ(irqn);
+ /* Setup the DMA transfer */
+ mxc_dma_config_t config = {
+ .ch = dmaCh,
+ .srcwd = MXC_DMA_WIDTH_BYTE,
+ .dstwd = MXC_DMA_WIDTH_BYTE,
+ .srcinc_en = 1,
+ .dstinc_en = 0
+ };
+
+ mxc_dma_srcdst_t srcdst = {
+ .ch = dmaCh,
+ .source = (void*)pData,
+ .len = len
+ };
+
+ switch (uartNum) {
+ case 0:
+ config.reqsel = MXC_DMA_REQUEST_UART0TX;
+ break;
+
+ case 1:
+ config.reqsel = MXC_DMA_REQUEST_UART1TX;
+ break;
+
+ case 2:
+ config.reqsel = MXC_DMA_REQUEST_UART2TX;
+ break;
+
+ case 3:
+ config.reqsel = MXC_DMA_REQUEST_UART3TX;
+ break;
+
+ default:
+ PAL_SYS_ASSERT(0);
+ return;
+ }
- palUartCb[uartNum].state = PAL_UART_STATE_BUSY;
+ MXC_DMA_ConfigChannel(config, srcdst);
+ MXC_DMA_SetCallback(dmaCh, palUartCallback);
- palUartCb[uartNum].writeReq.uart = MXC_UART_GET_UART(uartNum);
- palUartCb[uartNum].writeReq.txData = pData;
- palUartCb[uartNum].writeReq.txLen = len;
- palUartCb[uartNum].writeReq.rxLen = 0;
- palUartCb[uartNum].writeReq.callback = palUartCallback;
+ /* Enable Count-to-Zero (CTZ) interrupt */
+ MXC_DMA_EnableInt(dmaCh);
+ MXC_DMA_SetChannelInterruptEn(dmaCh, 0, 1);
- /* Start the write */
- result = MXC_UART_TransactionAsync(&palUartCb[uartNum].writeReq);
- (void)result;
- PAL_SYS_ASSERT(result == E_SUCCESS);
+ /* Set Tx FIFO threshold */
+ uart->dma |= 2 << MXC_F_UART_REVB_DMA_TX_THD_VAL_POS;
+ /* Enable channel transmission */
+ uart->dma |= MXC_F_UART_REVB_DMA_TX_EN;
- /* Enable the interrupt */
- NVIC_EnableIRQ(irqn);
+ /* Start the transfer */
+ MXC_DMA_Start(dmaCh);
}
diff --git a/Libraries/MAXUSB/include/core/usb_protocol.h b/Libraries/MAXUSB/include/core/usb_protocol.h
index 58fd33c89b5..d1533d26895 100644
--- a/Libraries/MAXUSB/include/core/usb_protocol.h
+++ b/Libraries/MAXUSB/include/core/usb_protocol.h
@@ -149,7 +149,10 @@ typedef __packed struct {
} MXC_USB_interface_descriptor_t;
#define USB_EP_NUM_MASK 0x0F
+
+#ifndef USE_ZEPHYR_USB_STACK
#define USB_EP_DIR_MASK 0x80
+#endif
#if defined(__GNUC__)
typedef struct __attribute__((packed)) {
diff --git a/Libraries/MAXUSB/src/core/musbhsfc/usb.c b/Libraries/MAXUSB/src/core/musbhsfc/usb.c
index e61a4b687db..ef6b099b4fa 100644
--- a/Libraries/MAXUSB/src/core/musbhsfc/usb.c
+++ b/Libraries/MAXUSB/src/core/musbhsfc/usb.c
@@ -941,7 +941,9 @@ int MXC_USB_GetSetup(MXC_USB_SetupPkt *sud)
/* Check for follow-on data and advance state machine */
if (sud->wLength > 0) {
+#ifndef USE_ZEPHYR_USB_STACK
MXC_USBHS->csr0 |= MXC_F_USBHS_CSR0_SERV_OUTPKTRDY;
+#endif
/* Determine if IN or OUT data follows */
if (sud->bmRequestType & RT_DEV_TO_HOST) {
setup_phase = SETUP_DATA_IN;
diff --git a/Libraries/PeriphDrivers/Include/MAX32655/wut.h b/Libraries/PeriphDrivers/Include/MAX32655/wut.h
index 67a8231aecc..db7466ad74e 100644
--- a/Libraries/PeriphDrivers/Include/MAX32655/wut.h
+++ b/Libraries/PeriphDrivers/Include/MAX32655/wut.h
@@ -159,14 +159,29 @@ uint32_t MXC_WUT_GetCount(mxc_wut_regs_t *wut);
* @brief Clear the timer interrupt.
* @param wut Pointer to Wakeup Timer instance to clear interrupts for.
*/
-void MXC_WUT_IntClear(mxc_wut_regs_t *wut);
+__attribute__((deprecated("Use MXC_WUT_ClearFlags instead. See wut.h for more details."))) void
+MXC_WUT_IntClear(mxc_wut_regs_t *wut);
+
+/**
+ * @brief Clear the timer interrupt.
+ * @param wut Pointer to Wakeup Timer instance to clear interrupt flags for.
+ */
+void MXC_WUT_ClearFlags(mxc_wut_regs_t *wut);
/**
* @brief Get the timer interrupt status.
* @param wut Pointer to Wakeup Timer instance to get interrupt staus from.
* @return Returns the interrupt status. 1 if interrupt has occurred.
*/
-uint32_t MXC_WUT_IntStatus(mxc_wut_regs_t *wut);
+__attribute__((deprecated("Use MXC_WUT_GetFlags instead. See wut.h for more details."))) uint32_t
+MXC_WUT_IntStatus(mxc_wut_regs_t *wut);
+
+/**
+ * @brief Get the timer interrupt status.
+ * @param wut Pointer to Wakeup Timer instance to get interrupt status from.
+ * @return Returns the interrupt status. 1 if interrupt has occurred.
+ */
+uint32_t MXC_WUT_GetFlags(mxc_wut_regs_t *wut);
/**
* @brief Set the timer compare count.
@@ -210,13 +225,27 @@ int MXC_WUT_GetTime(mxc_wut_regs_t *wut, uint32_t ticks, uint32_t *time, mxc_wut
* @brief Wait for an edge of the WUT count register.
* @param wut Pointer to Wakeup Timer instance to wait on.
*/
-void MXC_WUT_Edge(mxc_wut_regs_t *wut);
+__attribute__((deprecated("Use MXC_WUT_WaitForEdge instead. See wut.h for more details."))) void
+MXC_WUT_Edge(mxc_wut_regs_t *wut);
+
+/**
+ * @brief Wait for an edge of the WUT count register.
+ * @param wut Pointer to Wakeup Timer instance to wait on.
+ */
+void MXC_WUT_WaitForEdge(mxc_wut_regs_t *wut);
+
+/**
+ * @brief Store the count and snapshot values.
+ * @param wut Pointer to Wakeup Timer instance to store count and snapshot values for.
+ */
+__attribute__((deprecated("Use MXC_WUT_StoreCount instead. See wut.h for more details."))) void
+MXC_WUT_Store(mxc_wut_regs_t *wut);
/**
* @brief Store the count and snapshot values.
* @param wut Pointer to Wakeup Timer instance to store count and snapshot values for.
*/
-void MXC_WUT_Store(mxc_wut_regs_t *wut);
+void MXC_WUT_StoreCount(mxc_wut_regs_t *wut);
/**
* @brief Restore the DBB clock with the stored count and snapshot values.
diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_pins.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_pins.h
index ee29193192a..a103efe4161 100644
--- a/Libraries/PeriphDrivers/Include/MAX32657/mxc_pins.h
+++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_pins.h
@@ -28,6 +28,7 @@
/***** Global Variables *****/
// Predefined GPIO Configurations
+extern const mxc_gpio_cfg_t gpio_cfg_extclk;
extern const mxc_gpio_cfg_t gpio_cfg_i3c;
extern const mxc_gpio_cfg_t gpio_cfg_uart;
diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h
index a763886da73..d1c88f6dae5 100644
--- a/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h
+++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h
@@ -99,9 +99,8 @@ typedef enum {
MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO, /**< Select the Internal Nanoring Oscillator (INRO) */
MXC_SYS_CLOCK_ERTCO =
MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO, /**< Select the External RTC Crystal Oscillator */
- // MXC_SYS_CLOCK_EXTCLK =
- // MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK /**< Use the external system clock input */
- // TODO(JC): ^^^ EXTCLK select is missing from gcr_regs.h (should be 0x7)
+ MXC_SYS_CLOCK_EXTCLK =
+ MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK /**< Use the external system clock input */
} mxc_sys_system_clock_t;
/** @brief Enumeration to set the System Clock divider */
diff --git a/Libraries/PeriphDrivers/Include/MAX32657/wut.h b/Libraries/PeriphDrivers/Include/MAX32657/wut.h
index 187fff5dadf..f8e81a8ac8f 100644
--- a/Libraries/PeriphDrivers/Include/MAX32657/wut.h
+++ b/Libraries/PeriphDrivers/Include/MAX32657/wut.h
@@ -157,14 +157,29 @@ uint32_t MXC_WUT_GetCount(mxc_wut_regs_t *wut);
* @brief Clear the timer interrupt.
* @param wut Pointer to Wakeup Timer instance to clear interrupts for.
*/
-void MXC_WUT_IntClear(mxc_wut_regs_t *wut);
+__attribute__((deprecated("Use MXC_WUT_ClearFlags instead. See wut.h for more details."))) void
+MXC_WUT_IntClear(mxc_wut_regs_t *wut);
+
+/**
+ * @brief Clear the timer interrupt.
+ * @param wut Pointer to Wakeup Timer instance to clear interrupt flags for.
+ */
+void MXC_WUT_ClearFlags(mxc_wut_regs_t *wut);
/**
* @brief Get the timer interrupt status.
* @param wut Pointer to Wakeup Timer instance to get interrupt staus from.
* @return Returns the interrupt status. 1 if interrupt has occurred.
*/
-uint32_t MXC_WUT_IntStatus(mxc_wut_regs_t *wut);
+__attribute__((deprecated("Use MXC_WUT_GetFlags instead. See wut.h for more details."))) uint32_t
+MXC_WUT_IntStatus(mxc_wut_regs_t *wut);
+
+/**
+ * @brief Get the timer interrupt status.
+ * @param wut Pointer to Wakeup Timer instance to get interrupt status from.
+ * @return Returns the interrupt status. 1 if interrupt has occurred.
+ */
+uint32_t MXC_WUT_GetFlags(mxc_wut_regs_t *wut);
/**
* @brief Set the timer compare count.
@@ -208,13 +223,27 @@ int MXC_WUT_GetTime(mxc_wut_regs_t *wut, uint32_t ticks, uint32_t *time, mxc_wut
* @brief Wait for an edge of the WUT count register.
* @param wut Pointer to Wakeup Timer instance to wait on.
*/
-void MXC_WUT_Edge(mxc_wut_regs_t *wut);
+__attribute__((deprecated("Use MXC_WUT_WaitForEdge instead. See wut.h for more details."))) void
+MXC_WUT_Edge(mxc_wut_regs_t *wut);
+
+/**
+ * @brief Wait for an edge of the WUT count register.
+ * @param wut Pointer to Wakeup Timer instance to wait on.
+ */
+void MXC_WUT_WaitForEdge(mxc_wut_regs_t *wut);
+
+/**
+ * @brief Store the count and snapshot values.
+ * @param wut Pointer to Wakeup Timer instance to store count and snapshot values for.
+ */
+__attribute__((deprecated("Use MXC_WUT_StoreCount instead. See wut.h for more details."))) void
+MXC_WUT_Store(mxc_wut_regs_t *wut);
/**
* @brief Store the count and snapshot values.
* @param wut Pointer to Wakeup Timer instance to store count and snapshot values for.
*/
-void MXC_WUT_Store(mxc_wut_regs_t *wut);
+void MXC_WUT_StoreCount(mxc_wut_regs_t *wut);
/**
* @brief Restore the DBB clock with the stored count and snapshot values.
diff --git a/Libraries/PeriphDrivers/Include/MAX32665/wut.h b/Libraries/PeriphDrivers/Include/MAX32665/wut.h
index fbef2fc3a46..a606ca4e2b5 100644
--- a/Libraries/PeriphDrivers/Include/MAX32665/wut.h
+++ b/Libraries/PeriphDrivers/Include/MAX32665/wut.h
@@ -158,13 +158,26 @@ uint32_t MXC_WUT_GetCount(void);
/**
* @brief Clear the timer interrupt.
*/
-void MXC_WUT_IntClear(void);
+__attribute__((deprecated("Use MXC_WUT_ClearFlags instead. See wut.h for more details."))) void
+MXC_WUT_IntClear(void);
+
+/**
+ * @brief Clear the timer interrupt.
+ */
+void MXC_WUT_ClearFlags(void);
+
+/**
+ * @brief Get the timer interrupt status.
+ * @return Returns the interrupt status. 1 if interrupt has occurred.
+ */
+__attribute__((deprecated("Use MXC_WUT_GetFlags instead. See wut.h for more details."))) uint32_t
+MXC_WUT_IntStatus(void);
/**
* @brief Get the timer interrupt status.
* @return Returns the interrupt status. 1 if interrupt has occurred.
*/
-uint32_t MXC_WUT_IntStatus(void);
+uint32_t MXC_WUT_GetFlags(void);
/**
* @brief Set the timer compare count.
@@ -203,12 +216,24 @@ int MXC_WUT_GetTime(uint32_t ticks, uint32_t *time, mxc_wut_unit_t *units);
/**
* @brief Wait for an edge of the WUT count register.
*/
-void MXC_WUT_Edge(void);
+__attribute__((deprecated("Use MXC_WUT_WaitForEdge instead. See wut.h for more details."))) void
+MXC_WUT_Edge(void);
+
+/**
+ * @brief Wait for an edge of the WUT count register.
+ */
+void MXC_WUT_WaitForEdge(void);
+
+/**
+ * @brief Store the count and snapshot values.
+ */
+__attribute__((deprecated("Use MXC_WUT_StoreCount instead. See wut.h for more details."))) void
+MXC_WUT_Store(void);
/**
* @brief Store the count and snapshot values.
*/
-void MXC_WUT_Store(void);
+void MXC_WUT_StoreCount(void);
/**
* @brief Restore the DBB clock with the stored count and snapshot values.
diff --git a/Libraries/PeriphDrivers/Include/MAX32680/wut.h b/Libraries/PeriphDrivers/Include/MAX32680/wut.h
index 031eeff39e8..415e44d9fc7 100644
--- a/Libraries/PeriphDrivers/Include/MAX32680/wut.h
+++ b/Libraries/PeriphDrivers/Include/MAX32680/wut.h
@@ -159,14 +159,29 @@ uint32_t MXC_WUT_GetCount(mxc_wut_regs_t *wut);
* @brief Clear the timer interrupt.
* @param wut Pointer to Wakeup Timer instance to clear interrupts for.
*/
-void MXC_WUT_IntClear(mxc_wut_regs_t *wut);
+__attribute__((deprecated("Use MXC_WUT_ClearFlags instead. See wut.h for more details."))) void
+MXC_WUT_IntClear(mxc_wut_regs_t *wut);
+
+/**
+ * @brief Clear the timer interrupt.
+ * @param wut Pointer to Wakeup Timer instance to clear interrupt flags for.
+ */
+void MXC_WUT_ClearFlags(mxc_wut_regs_t *wut);
+
+/**
+ * @brief Get the timer interrupt status.
+ * @param wut Pointer to Wakeup Timer instance to get interrupt status from.
+ * @return Returns the interrupt status. 1 if interrupt has occurred.
+ */
+__attribute__((deprecated("Use MXC_WUT_GetFlags instead. See wut.h for more details."))) uint32_t
+MXC_WUT_IntStatus(mxc_wut_regs_t *wut);
/**
* @brief Get the timer interrupt status.
* @param wut Pointer to Wakeup Timer instance to get interrupt status from.
* @return Returns the interrupt status. 1 if interrupt has occurred.
*/
-uint32_t MXC_WUT_IntStatus(mxc_wut_regs_t *wut);
+uint32_t MXC_WUT_GetFlags(mxc_wut_regs_t *wut);
/**
* @brief Set the timer compare count.
@@ -210,13 +225,27 @@ int MXC_WUT_GetTime(mxc_wut_regs_t *wut, uint32_t ticks, uint32_t *time, mxc_wut
* @brief Wait for an edge of the WUT count register.
* @param wut Pointer to Wakeup Timer instance to wait on.
*/
-void MXC_WUT_Edge(mxc_wut_regs_t *wut);
+__attribute__((deprecated("Use MXC_WUT_WaitForEdge instead. See wut.h for more details."))) void
+MXC_WUT_Edge(mxc_wut_regs_t *wut);
+
+/**
+ * @brief Wait for an edge of the WUT count register.
+ * @param wut Pointer to Wakeup Timer instance to wait on.
+ */
+void MXC_WUT_WaitForEdge(mxc_wut_regs_t *wut);
+
+/**
+ * @brief Store the count and snapshot values.
+ * @param wut Pointer to Wakeup Timer instance to store count and snapshot values for.
+ */
+__attribute__((deprecated("Use MXC_WUT_StoreCount instead. See wut.h for more details."))) void
+MXC_WUT_Store(mxc_wut_regs_t *wut);
/**
* @brief Store the count and snapshot values.
* @param wut Pointer to Wakeup Timer instance to store count and snapshot values for.
*/
-void MXC_WUT_Store(mxc_wut_regs_t *wut);
+void MXC_WUT_StoreCount(mxc_wut_regs_t *wut);
/**
* @brief Restore the DBB clock with the stored count and snapshot values.
diff --git a/Libraries/PeriphDrivers/Include/MAX32690/wut.h b/Libraries/PeriphDrivers/Include/MAX32690/wut.h
index 84f875640a8..900c84c2202 100644
--- a/Libraries/PeriphDrivers/Include/MAX32690/wut.h
+++ b/Libraries/PeriphDrivers/Include/MAX32690/wut.h
@@ -112,135 +112,156 @@ typedef void (*mxc_wut_complete_cb_t)(int result);
/**
* @brief Initialize timer module clock.
+ * @param wut Pointer to Wakeup Timer instance to initialize.
* @param pres Prescaler value.
*/
-void MXC_WUT_Init(mxc_wut_pres_t pres);
+void MXC_WUT_Init(mxc_wut_regs_t *wut, mxc_wut_pres_t pres);
/**
* @brief Shutdown timer module clock.
+ * @param wut Pointer to Wakeup Timer instance to shutdown.
*/
-void MXC_WUT_Shutdown(void);
+void MXC_WUT_Shutdown(mxc_wut_regs_t *wut);
/**
* @brief Enable the timer.
+ * @param wut Pointer to Wakeup Timer instance to enable.
*/
-void MXC_WUT_Enable(void);
+void MXC_WUT_Enable(mxc_wut_regs_t *wut);
/**
* @brief Disable the timer.
+ * @param wut Pointer to Wakeup Timer instance to disable.
*/
-void MXC_WUT_Disable(void);
+void MXC_WUT_Disable(mxc_wut_regs_t *wut);
/**
* @brief Configure the timer.
+ * @param wut Pointer to Wakeup Timer instance to configure.
* @param cfg Pointer to timer configuration struct.
*/
-void MXC_WUT_Config(const mxc_wut_cfg_t *cfg);
+void MXC_WUT_Config(mxc_wut_regs_t *wut, const mxc_wut_cfg_t *cfg);
/**
* @brief Get the timer compare count.
+ * @param wut Pointer to Wakeup Timer instance to get compare value from.
* @return Returns the current compare count.
*/
-uint32_t MXC_WUT_GetCompare(void);
+uint32_t MXC_WUT_GetCompare(mxc_wut_regs_t *wut);
/**
* @brief Get the timer capture count.
+ * @param wut Pointer to Wakeup Timer instance to get capture count value from.
* @return Returns the most recent capture count.
*/
-uint32_t MXC_WUT_GetCapture(void);
+uint32_t MXC_WUT_GetCapture(mxc_wut_regs_t *wut);
/**
* @brief Get the timer count.
+ * @param wut Pointer to Wakeup Timer instance to get count value from.
* @return Returns the current count.
*/
-uint32_t MXC_WUT_GetCount(void);
+uint32_t MXC_WUT_GetCount(mxc_wut_regs_t *wut);
/**
* @brief Clear the timer interrupt.
+ * @param wut Pointer to Wakeup Timer instance to clear interrupt flags for.
*/
-void MXC_WUT_IntClear(void);
+void MXC_WUT_ClearFlags(mxc_wut_regs_t *wut);
/**
* @brief Get the timer interrupt status.
+ * @param wut Pointer to Wakeup Timer instance to get interrupt status from.
* @return Returns the interrupt status. 1 if interrupt has occurred.
*/
-uint32_t MXC_WUT_IntStatus(void);
+uint32_t MXC_WUT_GetFlags(mxc_wut_regs_t *wut);
/**
* @brief Set the timer compare count.
+ * @param wut Pointer to Wakeup Timer instance to set compare value for.
* @param cmp_cnt New compare count.
* @note This function does not protect against output glitches in PWM mode.
* Use MXC_WUT_PWMSetPeriod when in PWM mode.
*/
-void MXC_WUT_SetCompare(uint32_t cmp_cnt);
+void MXC_WUT_SetCompare(mxc_wut_regs_t *wut, uint32_t cmp_cnt);
/**
* @brief Set the timer count.
+ * @param wut Pointer to Wakeup Timer instance to set count value for.
* @param cnt New count.
*/
-void MXC_WUT_SetCount(uint32_t cnt);
+void MXC_WUT_SetCount(mxc_wut_regs_t *wut, uint32_t cnt);
/**
* @brief Convert real time to timer ticks.
+ * @param wut Pointer to Wakeup Timer instance to get tick count for.
* @param time Number of units of time.
* @param units Which units of time you want to convert.
* @param ticks Pointer to store the number of ticks calculated.
* @return #E_NO_ERROR If everything is successful.
* @return @ref MXC_Error_Codes If function is unsuccessful.
*/
-int MXC_WUT_GetTicks(uint32_t time, mxc_wut_unit_t units, uint32_t *ticks);
+int MXC_WUT_GetTicks(mxc_wut_regs_t *wut, uint32_t time, mxc_wut_unit_t units, uint32_t *ticks);
/**
* @brief Convert timer ticks to real time.
+ * @param wut Pointer to Wakeup Timer instance to get time for.
* @param ticks Number of ticks.
* @param time Pointer to store number of units of time.
* @param units Pointer to store the units that time represents.
* @return #E_NO_ERROR If everything is successful.
* @return @ref MXC_Error_Codes If function is unsuccessful.
*/
-int MXC_WUT_GetTime(uint32_t ticks, uint32_t *time, mxc_wut_unit_t *units);
+int MXC_WUT_GetTime(mxc_wut_regs_t *wut, uint32_t ticks, uint32_t *time, mxc_wut_unit_t *units);
/**
* @brief Wait for an edge of the WUT count register.
+ * @param wut Pointer to Wakeup Timer instance to wait on.
*/
-void MXC_WUT_Edge(void);
+void MXC_WUT_WaitForEdge(mxc_wut_regs_t *wut);
/**
* @brief Store the count and snapshot values.
+ * @param wut Pointer to Wakeup Timer instance to store count and snapshot values for.
*/
-void MXC_WUT_Store(void);
+void MXC_WUT_StoreCount(mxc_wut_regs_t *wut);
/**
* @brief Restore the DBB clock with the stored count and snapshot values.
+ * @param wut Pointer to Wakeup Timer instance restore count and snapshot values for.
* @param dbbFreq Frequency of DBB clock.
*/
-void MXC_WUT_RestoreBBClock(uint32_t dbbFreq);
+void MXC_WUT_RestoreBBClock(mxc_wut_regs_t *wut, uint32_t dbbFreq);
/**
* @brief Get the difference between the stored counter value
* and the current counter value.
+ * @param wut Pointer to Wakeup Timer instance to get current sleep ticks for.
* @return Returns the current counter value - stored counter value.
*/
-uint32_t MXC_WUT_GetSleepTicks(void);
+uint32_t MXC_WUT_GetSleepTicks(mxc_wut_regs_t *wut);
/**
* @brief Delays for the given number of milliseconds.
+ * @param wut Pointer to Wakeup Timer instance to use as the delay timer.
* @param waitMs Number of milliseconds to wait.
*/
-void MXC_WUT_Delay_MS(uint32_t waitMs);
+void MXC_WUT_Delay_MS(mxc_wut_regs_t *wut, uint32_t waitMs);
/**
* @brief Trim the 32 kHz crystal load settings, blocks until complete.
+ * @param wut Pointer to Wakeup Timer instance to trim.
* @details This procedure uses the WUT and the BLE DBB, driven by the 32 MHz crystal,
* to trim the load settings of the 32 kHz crystal. This procedure will only
* work if the BLE DBB is initialized and running.
*
* @return #E_NO_ERROR If everything is successful.
*/
-int MXC_WUT_TrimCrystal(void);
+int MXC_WUT_TrimCrystal(mxc_wut_regs_t *wut);
/**
* @brief Trim the 32 kHz crystal load settings, non-blocking interrupt based.
+ * @param wut Pointer to Wakeup Timer instance to trim.
* @details This procedure uses the WUT and the BLE DBB, driven by the 32 MHz crystal,
* to trim the load settings of the 32 kHz crystal. This procedure will only
* work if the BLE DBB is initialized and running.
@@ -248,21 +269,22 @@ int MXC_WUT_TrimCrystal(void);
* @param cb Callback for when the trim is complete.
* @return #E_NO_ERROR If everything is successful.
*/
-int MXC_WUT_TrimCrystalAsync(mxc_wut_complete_cb_t cb);
+int MXC_WUT_TrimCrystalAsync(mxc_wut_regs_t *wut, mxc_wut_complete_cb_t cb);
/**
* @brief Check to see if the trim procedure is ongoing.
+ * @param wut Pointer to Wakeup Timer instance to check trim status for.
* @details Must leave the 32 MHz clock and BLE DBB running while the trim procedure is pending.
* @return #E_NO_ERROR If trim is complete, E_BUSY if trim procedure is ongoing.
*/
-int MXC_WUT_TrimPending(void);
+int MXC_WUT_TrimPending(mxc_wut_regs_t *wut);
/**
* @brief Interrupt handler for trim procedure.
- *
+ * @param wut Pointer to Wakeup Timer instance to handle interrupts for.
* @return #E_NO_ERROR If trim is complete, E_BUSY if trim procedure is ongoing.
*/
-int MXC_WUT_Handler(void);
+int MXC_WUT_Handler(mxc_wut_regs_t *wut);
/**@} end of group wut */
diff --git a/Libraries/PeriphDrivers/Include/MAX78000/wut.h b/Libraries/PeriphDrivers/Include/MAX78000/wut.h
index 11397713671..53cab45cd9a 100644
--- a/Libraries/PeriphDrivers/Include/MAX78000/wut.h
+++ b/Libraries/PeriphDrivers/Include/MAX78000/wut.h
@@ -151,13 +151,26 @@ uint32_t MXC_WUT_GetCount(void);
/**
* @brief Clear the timer interrupt.
*/
-void MXC_WUT_IntClear(void);
+__attribute__((deprecated("Use MXC_WUT_ClearFlags instead. See wut.h for more details."))) void
+MXC_WUT_IntClear(void);
+
+/**
+ * @brief Clear the timer interrupt.
+ */
+void MXC_WUT_ClearFlags(void);
+
+/**
+ * @brief Get the timer interrupt status.
+ * @return Returns the interrupt status. 1 if interrupt has occurred.
+ */
+__attribute__((deprecated("Use MXC_WUT_GetFlags instead. See wut.h for more details."))) uint32_t
+MXC_WUT_IntStatus(void);
/**
* @brief Get the timer interrupt status.
* @return Returns the interrupt status. 1 if interrupt has occurred.
*/
-uint32_t MXC_WUT_IntStatus(void);
+uint32_t MXC_WUT_GetFlags(void);
/**
* @brief Set the timer compare count.
@@ -196,12 +209,24 @@ int MXC_WUT_GetTime(uint32_t ticks, uint32_t *time, mxc_wut_unit_t *units);
/**
* @brief Wait for an edge of the WUT count register.
*/
-void MXC_WUT_Edge(void);
+__attribute__((deprecated("Use MXC_WUT_WaitForEdge instead. See wut.h for more details."))) void
+MXC_WUT_Edge(void);
+
+/**
+ * @brief Wait for an edge of the WUT count register.
+ */
+void MXC_WUT_WaitForEdge(void);
+
+/**
+ * @brief Store the count and snapshot values.
+ */
+__attribute__((deprecated("Use MXC_WUT_StoreCount instead. See wut.h for more details."))) void
+MXC_WUT_Store(void);
/**
* @brief Store the count and snapshot values.
*/
-void MXC_WUT_Store(void);
+void MXC_WUT_StoreCount(void);
/**
* @brief Restore the DBB clock with the stored count and snapshot values.
diff --git a/Libraries/PeriphDrivers/Include/MAX78002/wut.h b/Libraries/PeriphDrivers/Include/MAX78002/wut.h
index 8212f907b9a..e1405d4573a 100644
--- a/Libraries/PeriphDrivers/Include/MAX78002/wut.h
+++ b/Libraries/PeriphDrivers/Include/MAX78002/wut.h
@@ -150,13 +150,26 @@ uint32_t MXC_WUT_GetCount(void);
/**
* @brief Clear the timer interrupt.
*/
-void MXC_WUT_IntClear(void);
+__attribute__((deprecated("Use MXC_WUT_ClearFlags instead. See wut.h for more details."))) void
+MXC_WUT_IntClear(void);
+
+/**
+ * @brief Clear the timer interrupt.
+ */
+void MXC_WUT_ClearFlags(void);
+
+/**
+ * @brief Get the timer interrupt status.
+ * @return Returns the interrupt status. 1 if interrupt has occurred.
+ */
+__attribute__((deprecated("Use MXC_WUT_GetFlags instead. See wut.h for more details."))) uint32_t
+MXC_WUT_IntStatus(void);
/**
* @brief Get the timer interrupt status.
* @return Returns the interrupt status. 1 if interrupt has occurred.
*/
-uint32_t MXC_WUT_IntStatus(void);
+uint32_t MXC_WUT_GetFlags(void);
/**
* @brief Set the timer compare count.
@@ -195,12 +208,24 @@ int MXC_WUT_GetTime(uint32_t ticks, uint32_t *time, mxc_wut_unit_t *units);
/**
* @brief Wait for an edge of the WUT count register.
*/
-void MXC_WUT_Edge(void);
+__attribute__((deprecated("Use MXC_WUT_WaitForEdge instead. See wut.h for more details."))) void
+MXC_WUT_Edge(void);
+
+/**
+ * @brief Wait for an edge of the WUT count register.
+ */
+void MXC_WUT_WaitForEdge(void);
+
+/**
+ * @brief Store the count and snapshot values.
+ */
+__attribute__((deprecated("Use MXC_WUT_StoreCount instead. See wut.h for more details."))) void
+MXC_WUT_Store(void);
/**
* @brief Store the count and snapshot values.
*/
-void MXC_WUT_Store(void);
+void MXC_WUT_StoreCount(void);
/**
* @brief Restore the DBB clock with the stored count and snapshot values.
diff --git a/Libraries/PeriphDrivers/Source/FLC/flc_me30.c b/Libraries/PeriphDrivers/Source/FLC/flc_me30.c
index eaacb6b8ee6..555a2b4422c 100644
--- a/Libraries/PeriphDrivers/Source/FLC/flc_me30.c
+++ b/Libraries/PeriphDrivers/Source/FLC/flc_me30.c
@@ -183,15 +183,44 @@ int MXC_FLC_MassErase(void)
}
//******************************************************************************
-__weak int MXC_FLC_UnlockInfoBlock(uint32_t address)
+int MXC_FLC_UnlockInfoBlock(uint32_t address)
{
+ /* Flash Controller only accessible in secure world. */
+#if defined(CONFIG_TRUSTED_EXECUTION_SECURE) || (CONFIG_TRUSTED_EXECUTION_SECURE != 0)
+ if ((address < MXC_INFO_MEM_BASE) ||
+ (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) {
+ return E_BAD_PARAM;
+ }
+#else
return E_NOT_SUPPORTED;
+#endif
+
+ /* Make sure the info block is locked */
+ MXC_FLC->actrl = 0x1234;
+
+ /* Write the unlock sequence */
+ MXC_FLC->actrl = 0x55bcbe69;
+ MXC_FLC->actrl = 0x7688c189;
+ MXC_FLC->actrl = 0x82306612;
+
+ return E_NO_ERROR;
}
//******************************************************************************
int MXC_FLC_LockInfoBlock(uint32_t address)
{
- return MXC_FLC_RevA_LockInfoBlock((mxc_flc_reva_regs_t *)MXC_FLC, address);
+ /* Flash Controller only accessible in secure world. */
+#if defined(CONFIG_TRUSTED_EXECUTION_SECURE) || (CONFIG_TRUSTED_EXECUTION_SECURE != 0)
+ if ((address < MXC_INFO_MEM_BASE) ||
+ (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) {
+ return E_BAD_PARAM;
+ }
+#else
+ return E_NOT_SUPPORTED;
+#endif
+
+ MXC_FLC->actrl = 0xDEADBEEF;
+ return E_NO_ERROR;
}
//******************************************************************************
diff --git a/Libraries/PeriphDrivers/Source/I3C/i3c_reva.c b/Libraries/PeriphDrivers/Source/I3C/i3c_reva.c
index 0c453044243..4ff73b55b03 100644
--- a/Libraries/PeriphDrivers/Source/I3C/i3c_reva.c
+++ b/Libraries/PeriphDrivers/Source/I3C/i3c_reva.c
@@ -582,6 +582,8 @@ int MXC_I3C_RevA_Controller_Transaction(mxc_i3c_reva_regs_t *i3c, const mxc_i3c_
int ret;
uint8_t readCount;
uint16_t remaining;
+ uint32_t timeout;
+ uint32_t freq;
if (MXC_I3C_RevA_Controller_GetState(i3c) != MXC_V_I3C_REVA_CONT_STATUS_STATE_IDLE &&
MXC_I3C_RevA_Controller_GetState(i3c) != MXC_V_I3C_REVA_CONT_STATUS_STATE_SDR_NORM) {
@@ -598,10 +600,12 @@ int MXC_I3C_RevA_Controller_Transaction(mxc_i3c_reva_regs_t *i3c, const mxc_i3c_
if (!req->is_i2c) {
ret = MXC_I3C_RevA_EmitStart(i3c, req->is_i2c, MXC_I3C_TRANSFER_TYPE_WRITE,
MXC_I3C_BROADCAST_ADDR, 0);
-
if (ret < 0) {
goto err;
}
+ freq = MXC_I3C_RevA_GetPPFrequency(i3c);
+ } else {
+ freq = MXC_I3C_RevA_GetI2CFrequency(i3c);
}
/* Restart with write */
@@ -612,7 +616,13 @@ int MXC_I3C_RevA_Controller_Transaction(mxc_i3c_reva_regs_t *i3c, const mxc_i3c_
goto err;
}
- ret = MXC_I3C_RevA_WriteTXFIFO(i3c, req->tx_buf, req->tx_len, true, 100);
+ /* A simple linear estimation to find a reasonable write timeout value,
+ proportional to clock period and buffer size. Coefficient value has
+ been found by trial-and-error.
+ */
+ timeout = (uint32_t)(40 * 1000000 / freq) * req->tx_len;
+
+ ret = MXC_I3C_RevA_WriteTXFIFO(i3c, req->tx_buf, req->tx_len, true, timeout);
if (ret < 0) {
goto err;
}
@@ -633,8 +643,14 @@ int MXC_I3C_RevA_Controller_Transaction(mxc_i3c_reva_regs_t *i3c, const mxc_i3c_
goto err;
}
+ /* A simple linear estimation to find a reasonable read timeout value,
+ proportional to clock period and buffer size. Coefficient value has
+ been found by trial-and-error.
+ */
+ timeout = (uint32_t)(80 * 1000000 / freq) * readCount;
+
ret = MXC_I3C_RevA_ReadRXFIFO(i3c, req->rx_buf + (req->rx_len - remaining), readCount,
- 1000);
+ timeout);
if (ret == readCount) {
remaining -= readCount;
} else {
diff --git a/Libraries/PeriphDrivers/Source/SPI/spi_me30.c b/Libraries/PeriphDrivers/Source/SPI/spi_me30.c
index ac48b4f2b2d..1b97472b0cb 100644
--- a/Libraries/PeriphDrivers/Source/SPI/spi_me30.c
+++ b/Libraries/PeriphDrivers/Source/SPI/spi_me30.c
@@ -88,30 +88,20 @@ int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numS
//clear mask
gpio_cfg_spi.mask = 0;
- // TODO(ME30): Validate pin assignments
- // check rest of the pins
if (pins.clock) {
- gpio_cfg_spi.mask |= MXC_GPIO_PIN_23;
+ gpio_cfg_spi.mask |= MXC_GPIO_PIN_6;
}
if (pins.miso) {
- gpio_cfg_spi.mask |= MXC_GPIO_PIN_22;
+ gpio_cfg_spi.mask |= MXC_GPIO_PIN_4;
}
if (pins.mosi) {
- gpio_cfg_spi.mask |= MXC_GPIO_PIN_21;
- }
-
- if (pins.sdio2) {
- gpio_cfg_spi.mask |= MXC_GPIO_PIN_24;
- }
-
- if (pins.sdio3) {
- gpio_cfg_spi.mask |= MXC_GPIO_PIN_25;
+ gpio_cfg_spi.mask |= MXC_GPIO_PIN_2;
}
if (pins.ss0) {
- gpio_cfg_spi.mask |= MXC_GPIO_PIN_20;
+ gpio_cfg_spi.mask |= MXC_GPIO_PIN_3;
}
gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT1;
@@ -146,40 +136,9 @@ int MXC_SPI_ReadyForSleep(mxc_spi_regs_t *spi)
int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi)
{
- int retval;
-
- // TODO(ME30): Validate this logic
- int sys_clk = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL) >>
- MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS;
- switch (sys_clk) {
- case MXC_SYS_CLOCK_IPO:
- retval = IPO_FREQ;
- break;
- case MXC_SYS_CLOCK_IBRO:
- retval = IBRO_FREQ;
- break;
- case MXC_SYS_CLOCK_INRO:
- retval = INRO_FREQ;
- break;
- case MXC_SYS_CLOCK_ERTCO:
- retval = ERTCO_FREQ;
- break;
- // TODO(ME30): EXTCLK definition is missing from registers
- // case MXC_SYS_CLOCK_EXTCLK:
- // retval = EXTCLK_FREQ;
- // break;
-#if TARGET_NUM == 32655 || TARGET_NUM == 32680
- case MXC_SYS_CLOCK_ERFO:
- retval = ERFO_FREQ;
- break;
-#endif
- default:
- return E_BAD_STATE;
- }
-
- retval /= 2;
+ (void)spi;
- return retval;
+ return PeripheralClock / 2;
}
int MXC_SPI_SetFrequency(mxc_spi_regs_t *spi, unsigned int hz)
diff --git a/Libraries/PeriphDrivers/Source/SYS/pins_me30.c b/Libraries/PeriphDrivers/Source/SYS/pins_me30.c
index b7fd798dab0..2b6ae2b03c0 100644
--- a/Libraries/PeriphDrivers/Source/SYS/pins_me30.c
+++ b/Libraries/PeriphDrivers/Source/SYS/pins_me30.c
@@ -24,6 +24,9 @@
/***** Global Variables *****/
// clang-format off
+const mxc_gpio_cfg_t gpio_cfg_extclk = { MXC_GPIO0, (MXC_GPIO_PIN_7), MXC_GPIO_FUNC_IN,
+ MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 };
+
// P0.0 - I3C SCL
// P0.1 - I3C SDA
const mxc_gpio_cfg_t gpio_cfg_i3c = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT1,
diff --git a/Libraries/PeriphDrivers/Source/SYS/sys_me30.c b/Libraries/PeriphDrivers/Source/SYS/sys_me30.c
index b6b286896ea..ee45aa55f6b 100644
--- a/Libraries/PeriphDrivers/Source/SYS/sys_me30.c
+++ b/Libraries/PeriphDrivers/Source/SYS/sys_me30.c
@@ -226,11 +226,10 @@ int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock)
return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_IBRO_RDY);
break;
- // TODO(ME30): EXTCLK is missing from register definitions
- // case MXC_SYS_CLOCK_EXTCLK:
- // // No "RDY" bit to monitor, so just configure the GPIO
- // return MXC_GPIO_Config(&gpio_cfg_extclk);
- // break;
+ case MXC_SYS_CLOCK_EXTCLK:
+ // No "RDY" bit to monitor, so just configure the GPIO
+ return MXC_GPIO_Config(&gpio_cfg_extclk);
+ break;
case MXC_SYS_CLOCK_INRO:
// The 80k clock is always enabled
@@ -291,19 +290,18 @@ int MXC_SYS_ClockSourceDisable(mxc_sys_system_clock_t clock)
MXC_GCR->clkctrl &= ~MXC_F_GCR_CLKCTRL_IBRO_EN;
break;
- // TODO(ME30): Missing EXTCLK register definition
- // case MXC_SYS_CLOCK_EXTCLK:
- // /*
- // There's not a great way to disable the external clock.
- // Deinitializing the GPIO here may have unintended consequences
- // for application code.
- // Selecting a different system clock source is sufficient
- // to "disable" the EXT_CLK source.
- // */
- // break;
+ case MXC_SYS_CLOCK_EXTCLK:
+ /*
+ There's not a great way to disable the external clock.
+ Deinitializing the GPIO here may have unintended consequences
+ for application code.
+ Selecting a different system clock source is sufficient
+ to "disable" the EXT_CLK source.
+ */
+ break;
case MXC_SYS_CLOCK_INRO:
- // The 80k clock is always enabled
+ // The 131k clock is always enabled
break;
case MXC_SYS_CLOCK_ERFO:
@@ -353,6 +351,7 @@ int MXC_SYS_Clock_Timeout(uint32_t ready)
int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock)
{
uint32_t current_clock;
+ int err = E_NO_ERROR;
// Save the current system clock
current_clock = MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL;
@@ -394,21 +393,20 @@ int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock)
break;
- // TODO(ME30): Missing EXTCLK register definition
- // case MXC_SYS_CLOCK_EXTCLK:
- // /*
- // There's not "EXT_CLK RDY" bit for the ME17, so we'll
- // blindly enable (configure GPIO) the external clock every time.
- // */
- // err = MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_EXTCLK);
- // if (err)
- // return err;
-
- // // Set EXT clock as System Clock
- // MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL,
- // MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK);
-
- // break;
+ case MXC_SYS_CLOCK_EXTCLK:
+ /*
+ There's not "EXT_CLK RDY" bit for the ME17, so we'll
+ blindly enable (configure GPIO) the external clock every time.
+ */
+ err = MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_EXTCLK);
+ if (err)
+ return err;
+
+ // Set EXT clock as System Clock
+ MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL,
+ MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK);
+
+ break;
case MXC_SYS_CLOCK_ERFO:
diff --git a/Libraries/PeriphDrivers/Source/TMR/tmr_revb.svd b/Libraries/PeriphDrivers/Source/TMR/tmr_revb.svd
index 4e7fa6ebdc1..a05d5318acd 100644
--- a/Libraries/PeriphDrivers/Source/TMR/tmr_revb.svd
+++ b/Libraries/PeriphDrivers/Source/TMR/tmr_revb.svd
@@ -1,662 +1,668 @@
-
+
-
- TMR
- Low-Power Configurable Timer
- 0x40010000
-
- 0x00
- 0x1000
- registers
-
-
- TMR
-
- 1
-
-
-
-
- CNT
- Timer Counter Register.
- 0x00
- read-write
-
-
- COUNT
- The current count value for the timer. This field increments as the timer counts.
- 0
- 32
-
-
-
-
- CMP
- Timer Compare Register.
- 0x04
- read-write
-
-
- COMPARE
- The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer.
- 0
- 32
-
-
-
-
- PWM
- Timer PWM Register.
- 0x08
- read-write
-
-
- PWM
- Timer PWM Match:
+
+ TMR
+ Low-Power Configurable Timer
+ 0x40010000
+
+ 0x00
+ 0x1000
+ registers
+
+
+ TMR
+
+ 1
+
+
+
+
+ CNT
+ Timer Counter Register.
+ 0x00
+ read-write
+
+
+ COUNT
+ The current count value for the timer. This field increments as the timer counts.
+ 0
+ 32
+
+
+
+
+ CMP
+ Timer Compare Register.
+ 0x04
+ read-write
+
+
+ COMPARE
+ The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer.
+ 0
+ 32
+
+
+
+
+ PWM
+ Timer PWM Register.
+ 0x08
+ read-write
+
+
+ PWM
+ Timer PWM Match:
In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value:
In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs.
- 0
- 32
-
-
-
-
- INTFL
- Timer Interrupt Status Register.
- 0x0C
- read-write
-
-
- IRQ_A
- Interrupt Flag for Timer A.
- 0
- 1
-
-
- WRDONE_A
- Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain.
- 8
- 1
-
-
- WR_DIS_A
- Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration.
- 9
- 1
-
-
- IRQ_B
- Interrupt Flag for Timer B.
- 16
- 1
-
-
- WRDONE_B
- Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain.
- 24
- 1
-
-
- WR_DIS_B
- Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration.
- 25
- 1
-
-
-
-
- CTRL0
- Timer Control Register.
- 0x10
- read-write
-
-
- MODE_A
- Mode Select for Timer A
- 0
- 4
-
-
- ONE_SHOT
- One-Shot Mode
- 0
-
-
- CONTINUOUS
- Continuous Mode
- 1
-
-
- COUNTER
- Counter Mode
- 2
-
-
- PWM
- PWM Mode
- 3
-
-
- CAPTURE
- Capture Mode
- 4
-
-
- COMPARE
- Compare Mode
- 5
-
-
- GATED
- Gated Mode
- 6
-
-
- CAPCOMP
- Capture/Compare Mode
- 7
-
-
- DUAL_EDGE
- Dual Edge Capture Mode
- 8
-
-
- IGATED
- Inactive Gated Mode
- 14
-
-
-
-
- CLKDIV_A
- Clock Divider Select for Timer A
- 4
- 4
-
-
- DIV_BY_1
- Prescaler Divide-By-1
- 0
-
-
- DIV_BY_2
- Prescaler Divide-By-2
- 1
-
-
- DIV_BY_4
- Prescaler Divide-By-4
- 2
-
-
- DIV_BY_8
- Prescaler Divide-By-8
- 3
-
-
- DIV_BY_16
- Prescaler Divide-By-16
- 4
-
-
- DIV_BY_32
- Prescaler Divide-By-32
- 5
-
-
- DIV_BY_64
- Prescaler Divide-By-64
- 6
-
-
- DIV_BY_128
- Prescaler Divide-By-128
- 7
-
-
- DIV_BY_256
- Prescaler Divide-By-256
- 8
-
-
- DIV_BY_512
- Prescaler Divide-By-512
- 9
-
-
- DIV_BY_1024
- Prescaler Divide-By-1024
- 10
-
-
- DIV_BY_2048
- Prescaler Divide-By-2048
- 11
-
-
- DIV_BY_4096
- TBD
- 12
-
-
-
-
- POL_A
- Timer Polarity for Timer A
- 8
- 1
-
-
- PWMSYNC_A
- PWM Synchronization Mode for Timer A
- 9
- 1
-
-
- NOLHPOL_A
- PWM Phase A (Non-Overlapping High) Polarity for Timer A
- 10
- 1
-
-
- NOLLPOL_A
- PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A
- 11
- 1
-
-
- PWMCKBD_A
- PWM Phase A-Prime Output Disable for Timer A
- 12
- 1
-
-
- RST_A
- Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears.
- 13
- 1
-
-
- CLKEN_A
- Write 1 to Enable CLK_TMR for Timer A
- 14
- 1
-
-
- EN_A
- Enable for Timer A
- 15
- 1
-
-
- MODE_B
- Mode Select for Timer B
- 16
- 4
-
-
- ONE_SHOT
- One-Shot Mode
- 0
-
-
- CONTINUOUS
- Continuous Mode
- 1
-
-
- COUNTER
- Counter Mode
- 2
-
-
- PWM
- PWM Mode
- 3
-
-
- CAPTURE
- Capture Mode
- 4
-
-
- COMPARE
- Compare Mode
- 5
-
-
- GATED
- Gated Mode
- 6
-
-
- CAPCOMP
- Capture/Compare Mode
- 7
-
-
- DUAL_EDGE
- Dual Edge Capture Mode
- 8
-
-
- IGATED
- Inactive Gated Mode
- 14
-
-
-
-
- CLKDIV_B
- Clock Divider Select for Timer B
- 20
- 4
-
-
- DIV_BY_1
- Prescaler Divide-By-1
- 0
-
-
- DIV_BY_2
- Prescaler Divide-By-2
- 1
-
-
- DIV_BY_4
- Prescaler Divide-By-4
- 2
-
-
- DIV_BY_8
- Prescaler Divide-By-8
- 3
-
-
- DIV_BY_16
- Prescaler Divide-By-16
- 4
-
-
- DIV_BY_32
- Prescaler Divide-By-32
- 5
-
-
- DIV_BY_64
- Prescaler Divide-By-64
- 6
-
-
- DIV_BY_128
- Prescaler Divide-By-128
- 7
-
-
- DIV_BY_256
- Prescaler Divide-By-256
- 8
-
-
- DIV_BY_512
- Prescaler Divide-By-512
- 9
-
-
- DIV_BY_1024
- Prescaler Divide-By-1024
- 10
-
-
- DIV_BY_2048
- Prescaler Divide-By-2048
- 11
-
-
- DIV_BY_4096
- TBD
- 12
-
-
-
-
- POL_B
- Timer Polarity for Timer B
- 24
- 1
-
-
- PWMSYNC_B
- PWM Synchronization Mode for Timer B
- 25
- 1
-
-
- NOLHPOL_B
- PWM Phase A (Non-Overlapping High) Polarity for Timer B
- 26
- 1
-
-
- NOLLPOL_B
- PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B
- 27
- 1
-
-
- PWMCKBD_B
- PWM Phase A-Prime Output Disable for Timer B
- 28
- 1
-
-
- RST_B
- Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears.
- 29
- 1
-
-
- CLKEN_B
- Write 1 to Enable CLK_TMR for Timer B
- 30
- 1
-
-
- EN_B
- Enable for Timer B
- 31
- 1
-
-
-
-
- NOLCMP
- Timer Non-Overlapping Compare Register.
- 0x14
- read-write
-
-
- LO_A
- Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.
- 0
- 8
-
-
- HI_A
- Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.
- 8
- 8
-
-
- LO_B
- Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.
- 16
- 8
-
-
- HI_B
- Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.
- 24
- 8
-
-
-
-
- CTRL1
- Timer Configuration Register.
- 0x18
- read-write
-
-
- CLKSEL_A
- Timer Clock Select for Timer A
- 0
- 2
-
-
- CLKEN_A
- Timer A Enable Status
- 2
- 1
-
-
- CLKRDY_A
- CLK_TMR Ready Flag for Timer A
- 3
- 1
-
-
- EVENT_SEL_A
- Event Select for Timer A
- 4
- 3
-
-
- NEGTRIG_A
- Negative Edge Trigger for Event for Timer A
- 7
- 1
-
-
- IE_A
- Interrupt Enable for Timer A
- 8
- 1
-
-
- CAPEVENT_SEL_A
- Capture Event Select for Timer A
- 9
- 2
-
-
- SW_CAPEVENT_A
- Software Capture Event for Timer A
- 11
- 1
-
-
- WE_A
- Wake-Up Enable for Timer A
- 12
- 1
-
-
- OUTEN_A
- OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A
- 13
- 1
-
-
- OUTBEN_A
- PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A
- 14
- 1
-
-
- CLKSEL_B
- Timer Clock Select for Timer B
- 16
- 2
-
-
- CLKEN_B
- Timer B Enable Status
- 18
- 1
-
-
- CLKRDY_B
- CLK_TMR Ready Flag for Timer B
- 19
- 1
-
-
- EVENT_SEL_B
- Event Select for Timer B
- 20
- 3
-
-
- NEGTRIG_B
- Negative Edge Trigger for Event for Timer B
- 23
- 1
-
-
- IE_B
- Interrupt Enable for Timer B
- 24
- 1
-
-
- CAPEVENT_SEL_B
- Capture Event Select for Timer B
- 25
- 2
-
-
- SW_CAPEVENT_B
- Software Capture Event for Timer B
- 27
- 1
-
-
- WE_B
- Wake-Up Enable for Timer B
- 28
- 1
-
-
- CASCADE
- Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1.
- 31
- 1
-
-
-
-
- WKFL
- Timer Wakeup Status Register.
- 0x1C
- read-write
-
-
- A
- Wake-Up Flag for Timer A
- 0
- 1
-
-
- B
- Wake-Up Flag for Timer B
- 16
- 1
-
-
-
-
-
-
-
+ 0
+ 32
+
+
+
+
+ INTFL
+ Timer Interrupt Status Register.
+ 0x0C
+ read-write
+
+
+ IRQ_A
+ Interrupt Flag for Timer A.
+ 0
+ 1
+
+
+ WRDONE_A
+ Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain.
+ 8
+ 1
+
+
+ WR_DIS_A
+ Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration.
+ 9
+ 1
+
+
+ IRQ_B
+ Interrupt Flag for Timer B.
+ 16
+ 1
+
+
+ WRDONE_B
+ Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain.
+ 24
+ 1
+
+
+ WR_DIS_B
+ Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration.
+ 25
+ 1
+
+
+
+
+ CTRL0
+ Timer Control Register.
+ 0x10
+ read-write
+
+
+ MODE_A
+ Mode Select for Timer A
+ 0
+ 4
+
+
+ ONE_SHOT
+ One-Shot Mode
+ 0
+
+
+ CONTINUOUS
+ Continuous Mode
+ 1
+
+
+ COUNTER
+ Counter Mode
+ 2
+
+
+ PWM
+ PWM Mode
+ 3
+
+
+ CAPTURE
+ Capture Mode
+ 4
+
+
+ COMPARE
+ Compare Mode
+ 5
+
+
+ GATED
+ Gated Mode
+ 6
+
+
+ CAPCOMP
+ Capture/Compare Mode
+ 7
+
+
+ DUAL_EDGE
+ Dual Edge Capture Mode
+ 8
+
+
+ IGATED
+ Inactive Gated Mode
+ 14
+
+
+
+
+ CLKDIV_A
+ Clock Divider Select for Timer A
+ 4
+ 4
+
+
+ DIV_BY_1
+ Prescaler Divide-By-1
+ 0
+
+
+ DIV_BY_2
+ Prescaler Divide-By-2
+ 1
+
+
+ DIV_BY_4
+ Prescaler Divide-By-4
+ 2
+
+
+ DIV_BY_8
+ Prescaler Divide-By-8
+ 3
+
+
+ DIV_BY_16
+ Prescaler Divide-By-16
+ 4
+
+
+ DIV_BY_32
+ Prescaler Divide-By-32
+ 5
+
+
+ DIV_BY_64
+ Prescaler Divide-By-64
+ 6
+
+
+ DIV_BY_128
+ Prescaler Divide-By-128
+ 7
+
+
+ DIV_BY_256
+ Prescaler Divide-By-256
+ 8
+
+
+ DIV_BY_512
+ Prescaler Divide-By-512
+ 9
+
+
+ DIV_BY_1024
+ Prescaler Divide-By-1024
+ 10
+
+
+ DIV_BY_2048
+ Prescaler Divide-By-2048
+ 11
+
+
+ DIV_BY_4096
+ TBD
+ 12
+
+
+
+
+ POL_A
+ Timer Polarity for Timer A
+ 8
+ 1
+
+
+ PWMSYNC_A
+ PWM Synchronization Mode for Timer A
+ 9
+ 1
+
+
+ NOLHPOL_A
+ PWM Phase A (Non-Overlapping High) Polarity for Timer A
+ 10
+ 1
+
+
+ NOLLPOL_A
+ PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A
+ 11
+ 1
+
+
+ PWMCKBD_A
+ PWM Phase A-Prime Output Disable for Timer A
+ 12
+ 1
+
+
+ RST_A
+ Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears.
+ 13
+ 1
+
+
+ CLKEN_A
+ Write 1 to Enable CLK_TMR for Timer A
+ 14
+ 1
+
+
+ EN_A
+ Enable for Timer A
+ 15
+ 1
+
+
+ MODE_B
+ Mode Select for Timer B
+ 16
+ 4
+
+
+ ONE_SHOT
+ One-Shot Mode
+ 0
+
+
+ CONTINUOUS
+ Continuous Mode
+ 1
+
+
+ COUNTER
+ Counter Mode
+ 2
+
+
+ PWM
+ PWM Mode
+ 3
+
+
+ CAPTURE
+ Capture Mode
+ 4
+
+
+ COMPARE
+ Compare Mode
+ 5
+
+
+ GATED
+ Gated Mode
+ 6
+
+
+ CAPCOMP
+ Capture/Compare Mode
+ 7
+
+
+ DUAL_EDGE
+ Dual Edge Capture Mode
+ 8
+
+
+ IGATED
+ Inactive Gated Mode
+ 14
+
+
+
+
+ CLKDIV_B
+ Clock Divider Select for Timer B
+ 20
+ 4
+
+
+ DIV_BY_1
+ Prescaler Divide-By-1
+ 0
+
+
+ DIV_BY_2
+ Prescaler Divide-By-2
+ 1
+
+
+ DIV_BY_4
+ Prescaler Divide-By-4
+ 2
+
+
+ DIV_BY_8
+ Prescaler Divide-By-8
+ 3
+
+
+ DIV_BY_16
+ Prescaler Divide-By-16
+ 4
+
+
+ DIV_BY_32
+ Prescaler Divide-By-32
+ 5
+
+
+ DIV_BY_64
+ Prescaler Divide-By-64
+ 6
+
+
+ DIV_BY_128
+ Prescaler Divide-By-128
+ 7
+
+
+ DIV_BY_256
+ Prescaler Divide-By-256
+ 8
+
+
+ DIV_BY_512
+ Prescaler Divide-By-512
+ 9
+
+
+ DIV_BY_1024
+ Prescaler Divide-By-1024
+ 10
+
+
+ DIV_BY_2048
+ Prescaler Divide-By-2048
+ 11
+
+
+ DIV_BY_4096
+ TBD
+ 12
+
+
+
+
+ POL_B
+ Timer Polarity for Timer B
+ 24
+ 1
+
+
+ PWMSYNC_B
+ PWM Synchronization Mode for Timer B
+ 25
+ 1
+
+
+ NOLHPOL_B
+ PWM Phase A (Non-Overlapping High) Polarity for Timer B
+ 26
+ 1
+
+
+ NOLLPOL_B
+ PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B
+ 27
+ 1
+
+
+ PWMCKBD_B
+ PWM Phase A-Prime Output Disable for Timer B
+ 28
+ 1
+
+
+ RST_B
+ Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears.
+ 29
+ 1
+
+
+ CLKEN_B
+ Write 1 to Enable CLK_TMR for Timer B
+ 30
+ 1
+
+
+ EN_B
+ Enable for Timer B
+ 31
+ 1
+
+
+
+
+ NOLCMP
+ Timer Non-Overlapping Compare Register.
+ 0x14
+ read-write
+
+
+ LO_A
+ Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.
+ 0
+ 8
+
+
+ HI_A
+ Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.
+ 8
+ 8
+
+
+ LO_B
+ Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.
+ 16
+ 8
+
+
+ HI_B
+ Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.
+ 24
+ 8
+
+
+
+
+ CTRL1
+ Timer Configuration Register.
+ 0x18
+ read-write
+
+
+ CLKSEL_A
+ Timer Clock Select for Timer A
+ 0
+ 2
+
+
+ CLKEN_A
+ Timer A Enable Status
+ 2
+ 1
+
+
+ CLKRDY_A
+ CLK_TMR Ready Flag for Timer A
+ 3
+ 1
+
+
+ EVENT_SEL_A
+ Event Select for Timer A
+ 4
+ 3
+
+
+ NEGTRIG_A
+ Negative Edge Trigger for Event for Timer A
+ 7
+ 1
+
+
+ IE_A
+ Interrupt Enable for Timer A
+ 8
+ 1
+
+
+ CAPEVENT_SEL_A
+ Capture Event Select for Timer A
+ 9
+ 2
+
+
+ SW_CAPEVENT_A
+ Software Capture Event for Timer A
+ 11
+ 1
+
+
+ WE_A
+ Wake-Up Enable for Timer A
+ 12
+ 1
+
+
+ OUTEN_A
+ OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A
+ 13
+ 1
+
+
+ OUTBEN_A
+ PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A
+ 14
+ 1
+
+
+ ASYNC
+ Allows asynchronous reads of the PWM and CNT registers.
+ 15
+ 1
+
+
+ CLKSEL_B
+ Timer Clock Select for Timer B
+ 16
+ 2
+
+
+ CLKEN_B
+ Timer B Enable Status
+ 18
+ 1
+
+
+ CLKRDY_B
+ CLK_TMR Ready Flag for Timer B
+ 19
+ 1
+
+
+ EVENT_SEL_B
+ Event Select for Timer B
+ 20
+ 3
+
+
+ NEGTRIG_B
+ Negative Edge Trigger for Event for Timer B
+ 23
+ 1
+
+
+ IE_B
+ Interrupt Enable for Timer B
+ 24
+ 1
+
+
+ CAPEVENT_SEL_B
+ Capture Event Select for Timer B
+ 25
+ 2
+
+
+ SW_CAPEVENT_B
+ Software Capture Event for Timer B
+ 27
+ 1
+
+
+ WE_B
+ Wake-Up Enable for Timer B
+ 28
+ 1
+
+
+ CASCADE
+ Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1.
+ 31
+ 1
+
+
+
+
+ WKFL
+ Timer Wakeup Status Register.
+ 0x1C
+ read-write
+
+
+ A
+ Wake-Up Flag for Timer A
+ 0
+ 1
+
+
+ B
+ Wake-Up Flag for Timer B
+ 16
+ 1
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me15.svd b/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me15.svd
index 5bb17764a0d..bb65faa3897 100644
--- a/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me15.svd
+++ b/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me15.svd
@@ -1,662 +1,668 @@

-
- TMR
- Low-Power Configurable Timer
- 0x40010000
-
- 0x00
- 0x1000
- registers
-
-
- TMR
-
- 1
-
-
-
-
- CNT
- Timer Counter Register.
- 0x00
- read-write
-
-
- COUNT
- The current count value for the timer. This field increments as the timer counts.
- 0
- 32
-
-
-
-
- CMP
- Timer Compare Register.
- 0x04
- read-write
-
-
- COMPARE
- The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer.
- 0
- 32
-
-
-
-
- PWM
- Timer PWM Register.
- 0x08
- read-write
-
-
- PWM
- Timer PWM Match:
+
+ TMR
+ Low-Power Configurable Timer
+ 0x40010000
+
+ 0x00
+ 0x1000
+ registers
+
+
+ TMR
+
+ 1
+
+
+
+
+ CNT
+ Timer Counter Register.
+ 0x00
+ read-write
+
+
+ COUNT
+ The current count value for the timer. This field increments as the timer counts.
+ 0
+ 32
+
+
+
+
+ CMP
+ Timer Compare Register.
+ 0x04
+ read-write
+
+
+ COMPARE
+ The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer.
+ 0
+ 32
+
+
+
+
+ PWM
+ Timer PWM Register.
+ 0x08
+ read-write
+
+
+ PWM
+ Timer PWM Match:
In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value:
In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs.
- 0
- 32
-
-
-
-
- INTFL
- Timer Interrupt Status Register.
- 0x0C
- read-write
-
-
- IRQ_A
- Interrupt Flag for Timer A.
- 0
- 1
-
-
- WRDONE_A
- Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain.
- 8
- 1
-
-
- WR_DIS_A
- Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration.
- 9
- 1
-
-
- IRQ_B
- Interrupt Flag for Timer B.
- 16
- 1
-
-
- WRDONE_B
- Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain.
- 24
- 1
-
-
- WR_DIS_B
- Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration.
- 25
- 1
-
-
-
-
- CTRL0
- Timer Control Register.
- 0x10
- read-write
-
-
- MODE_A
- Mode Select for Timer A
- 0
- 4
-
-
- ONE_SHOT
- One-Shot Mode
- 0
-
-
- CONTINUOUS
- Continuous Mode
- 1
-
-
- COUNTER
- Counter Mode
- 2
-
-
- PWM
- PWM Mode
- 3
-
-
- CAPTURE
- Capture Mode
- 4
-
-
- COMPARE
- Compare Mode
- 5
-
-
- GATED
- Gated Mode
- 6
-
-
- CAPCOMP
- Capture/Compare Mode
- 7
-
-
- DUAL_EDGE
- Dual Edge Capture Mode
- 8
-
-
- IGATED
- Inactive Gated Mode
- 14
-
-
-
-
- CLKDIV_A
- Clock Divider Select for Timer A
- 4
- 4
-
-
- DIV_BY_1
- Prescaler Divide-By-1
- 0
-
-
- DIV_BY_2
- Prescaler Divide-By-2
- 1
-
-
- DIV_BY_4
- Prescaler Divide-By-4
- 2
-
-
- DIV_BY_8
- Prescaler Divide-By-8
- 3
-
-
- DIV_BY_16
- Prescaler Divide-By-16
- 4
-
-
- DIV_BY_32
- Prescaler Divide-By-32
- 5
-
-
- DIV_BY_64
- Prescaler Divide-By-64
- 6
-
-
- DIV_BY_128
- Prescaler Divide-By-128
- 7
-
-
- DIV_BY_256
- Prescaler Divide-By-256
- 8
-
-
- DIV_BY_512
- Prescaler Divide-By-512
- 9
-
-
- DIV_BY_1024
- Prescaler Divide-By-1024
- 10
-
-
- DIV_BY_2048
- Prescaler Divide-By-2048
- 11
-
-
- DIV_BY_4096
- TBD
- 12
-
-
-
-
- POL_A
- Timer Polarity for Timer A
- 8
- 1
-
-
- PWMSYNC_A
- PWM Synchronization Mode for Timer A
- 9
- 1
-
-
- NOLHPOL_A
- PWM Phase A (Non-Overlapping High) Polarity for Timer A
- 10
- 1
-
-
- NOLLPOL_A
- PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A
- 11
- 1
-
-
- PWMCKBD_A
- PWM Phase A-Prime Output Disable for Timer A
- 12
- 1
-
-
- RST_A
- Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears.
- 13
- 1
-
-
- CLKEN_A
- Write 1 to Enable CLK_TMR for Timer A
- 14
- 1
-
-
- EN_A
- Enable for Timer A
- 15
- 1
-
-
- MODE_B
- Mode Select for Timer B
- 16
- 4
-
-
- ONE_SHOT
- One-Shot Mode
- 0
-
-
- CONTINUOUS
- Continuous Mode
- 1
-
-
- COUNTER
- Counter Mode
- 2
-
-
- PWM
- PWM Mode
- 3
-
-
- CAPTURE
- Capture Mode
- 4
-
-
- COMPARE
- Compare Mode
- 5
-
-
- GATED
- Gated Mode
- 6
-
-
- CAPCOMP
- Capture/Compare Mode
- 7
-
-
- DUAL_EDGE
- Dual Edge Capture Mode
- 8
-
-
- IGATED
- Inactive Gated Mode
- 14
-
-
-
-
- CLKDIV_B
- Clock Divider Select for Timer B
- 20
- 4
-
-
- DIV_BY_1
- Prescaler Divide-By-1
- 0
-
-
- DIV_BY_2
- Prescaler Divide-By-2
- 1
-
-
- DIV_BY_4
- Prescaler Divide-By-4
- 2
-
-
- DIV_BY_8
- Prescaler Divide-By-8
- 3
-
-
- DIV_BY_16
- Prescaler Divide-By-16
- 4
-
-
- DIV_BY_32
- Prescaler Divide-By-32
- 5
-
-
- DIV_BY_64
- Prescaler Divide-By-64
- 6
-
-
- DIV_BY_128
- Prescaler Divide-By-128
- 7
-
-
- DIV_BY_256
- Prescaler Divide-By-256
- 8
-
-
- DIV_BY_512
- Prescaler Divide-By-512
- 9
-
-
- DIV_BY_1024
- Prescaler Divide-By-1024
- 10
-
-
- DIV_BY_2048
- Prescaler Divide-By-2048
- 11
-
-
- DIV_BY_4096
- TBD
- 12
-
-
-
-
- POL_B
- Timer Polarity for Timer B
- 24
- 1
-
-
- PWMSYNC_B
- PWM Synchronization Mode for Timer B
- 25
- 1
-
-
- NOLHPOL_B
- PWM Phase A (Non-Overlapping High) Polarity for Timer B
- 26
- 1
-
-
- NOLLPOL_B
- PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B
- 27
- 1
-
-
- PWMCKBD_B
- PWM Phase A-Prime Output Disable for Timer B
- 28
- 1
-
-
- RST_B
- Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears.
- 29
- 1
-
-
- CLKEN_B
- Write 1 to Enable CLK_TMR for Timer B
- 30
- 1
-
-
- EN_B
- Enable for Timer B
- 31
- 1
-
-
-
-
- NOLCMP
- Timer Non-Overlapping Compare Register.
- 0x14
- read-write
-
-
- LO_A
- Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.
- 0
- 8
-
-
- HI_A
- Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.
- 8
- 8
-
-
- LO_B
- Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.
- 16
- 8
-
-
- HI_B
- Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.
- 24
- 8
-
-
-
-
- CTRL1
- Timer Configuration Register.
- 0x18
- read-write
-
-
- CLKSEL_A
- Timer Clock Select for Timer A
- 0
- 2
-
-
- CLKEN_A
- Timer A Enable Status
- 2
- 1
-
-
- CLKRDY_A
- CLK_TMR Ready Flag for Timer A
- 3
- 1
-
-
- EVENT_SEL_A
- Event Select for Timer A
- 4
- 3
-
-
- NEGTRIG_A
- Negative Edge Trigger for Event for Timer A
- 7
- 1
-
-
- IE_A
- Interrupt Enable for Timer A
- 8
- 1
-
-
- CAPEVENT_SEL_A
- Capture Event Select for Timer A
- 9
- 2
-
-
- SW_CAPEVENT_A
- Software Capture Event for Timer A
- 11
- 1
-
-
- WE_A
- Wake-Up Enable for Timer A
- 12
- 1
-
-
- OUTEN_A
- OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A
- 13
- 1
-
-
- OUTBEN_A
- PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A
- 14
- 1
-
-
- CLKSEL_B
- Timer Clock Select for Timer B
- 16
- 2
-
-
- CLKEN_B
- Timer B Enable Status
- 18
- 1
-
-
- CLKRDY_B
- CLK_TMR Ready Flag for Timer B
- 19
- 1
-
-
- EVENT_SEL_B
- Event Select for Timer B
- 20
- 3
-
-
- NEGTRIG_B
- Negative Edge Trigger for Event for Timer B
- 23
- 1
-
-
- IE_B
- Interrupt Enable for Timer B
- 24
- 1
-
-
- CAPEVENT_SEL_B
- Capture Event Select for Timer B
- 25
- 2
-
-
- SW_CAPEVENT_B
- Software Capture Event for Timer B
- 27
- 1
-
-
- WE_B
- Wake-Up Enable for Timer B
- 28
- 1
-
-
- CASCADE
- Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1.
- 31
- 1
-
-
-
-
- WKFL
- Timer Wakeup Status Register.
- 0x1C
- read-write
-
-
- A
- Wake-Up Flag for Timer A
- 0
- 1
-
-
- B
- Wake-Up Flag for Timer B
- 16
- 1
-
-
-
-
-
-
-
+ 0
+ 32
+
+
+
+
+ INTFL
+ Timer Interrupt Status Register.
+ 0x0C
+ read-write
+
+
+ IRQ_A
+ Interrupt Flag for Timer A.
+ 0
+ 1
+
+
+ WRDONE_A
+ Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain.
+ 8
+ 1
+
+
+ WR_DIS_A
+ Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration.
+ 9
+ 1
+
+
+ IRQ_B
+ Interrupt Flag for Timer B.
+ 16
+ 1
+
+
+ WRDONE_B
+ Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain.
+ 24
+ 1
+
+
+ WR_DIS_B
+ Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration.
+ 25
+ 1
+
+
+
+
+ CTRL0
+ Timer Control Register.
+ 0x10
+ read-write
+
+
+ MODE_A
+ Mode Select for Timer A
+ 0
+ 4
+
+
+ ONE_SHOT
+ One-Shot Mode
+ 0
+
+
+ CONTINUOUS
+ Continuous Mode
+ 1
+
+
+ COUNTER
+ Counter Mode
+ 2
+
+
+ PWM
+ PWM Mode
+ 3
+
+
+ CAPTURE
+ Capture Mode
+ 4
+
+
+ COMPARE
+ Compare Mode
+ 5
+
+
+ GATED
+ Gated Mode
+ 6
+
+
+ CAPCOMP
+ Capture/Compare Mode
+ 7
+
+
+ DUAL_EDGE
+ Dual Edge Capture Mode
+ 8
+
+
+ IGATED
+ Inactive Gated Mode
+ 14
+
+
+
+
+ CLKDIV_A
+ Clock Divider Select for Timer A
+ 4
+ 4
+
+
+ DIV_BY_1
+ Prescaler Divide-By-1
+ 0
+
+
+ DIV_BY_2
+ Prescaler Divide-By-2
+ 1
+
+
+ DIV_BY_4
+ Prescaler Divide-By-4
+ 2
+
+
+ DIV_BY_8
+ Prescaler Divide-By-8
+ 3
+
+
+ DIV_BY_16
+ Prescaler Divide-By-16
+ 4
+
+
+ DIV_BY_32
+ Prescaler Divide-By-32
+ 5
+
+
+ DIV_BY_64
+ Prescaler Divide-By-64
+ 6
+
+
+ DIV_BY_128
+ Prescaler Divide-By-128
+ 7
+
+
+ DIV_BY_256
+ Prescaler Divide-By-256
+ 8
+
+
+ DIV_BY_512
+ Prescaler Divide-By-512
+ 9
+
+
+ DIV_BY_1024
+ Prescaler Divide-By-1024
+ 10
+
+
+ DIV_BY_2048
+ Prescaler Divide-By-2048
+ 11
+
+
+ DIV_BY_4096
+ TBD
+ 12
+
+
+
+
+ POL_A
+ Timer Polarity for Timer A
+ 8
+ 1
+
+
+ PWMSYNC_A
+ PWM Synchronization Mode for Timer A
+ 9
+ 1
+
+
+ NOLHPOL_A
+ PWM Phase A (Non-Overlapping High) Polarity for Timer A
+ 10
+ 1
+
+
+ NOLLPOL_A
+ PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A
+ 11
+ 1
+
+
+ PWMCKBD_A
+ PWM Phase A-Prime Output Disable for Timer A
+ 12
+ 1
+
+
+ RST_A
+ Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears.
+ 13
+ 1
+
+
+ CLKEN_A
+ Write 1 to Enable CLK_TMR for Timer A
+ 14
+ 1
+
+
+ EN_A
+ Enable for Timer A
+ 15
+ 1
+
+
+ MODE_B
+ Mode Select for Timer B
+ 16
+ 4
+
+
+ ONE_SHOT
+ One-Shot Mode
+ 0
+
+
+ CONTINUOUS
+ Continuous Mode
+ 1
+
+
+ COUNTER
+ Counter Mode
+ 2
+
+
+ PWM
+ PWM Mode
+ 3
+
+
+ CAPTURE
+ Capture Mode
+ 4
+
+
+ COMPARE
+ Compare Mode
+ 5
+
+
+ GATED
+ Gated Mode
+ 6
+
+
+ CAPCOMP
+ Capture/Compare Mode
+ 7
+
+
+ DUAL_EDGE
+ Dual Edge Capture Mode
+ 8
+
+
+ IGATED
+ Inactive Gated Mode
+ 14
+
+
+
+
+ CLKDIV_B
+ Clock Divider Select for Timer B
+ 20
+ 4
+
+
+ DIV_BY_1
+ Prescaler Divide-By-1
+ 0
+
+
+ DIV_BY_2
+ Prescaler Divide-By-2
+ 1
+
+
+ DIV_BY_4
+ Prescaler Divide-By-4
+ 2
+
+
+ DIV_BY_8
+ Prescaler Divide-By-8
+ 3
+
+
+ DIV_BY_16
+ Prescaler Divide-By-16
+ 4
+
+
+ DIV_BY_32
+ Prescaler Divide-By-32
+ 5
+
+
+ DIV_BY_64
+ Prescaler Divide-By-64
+ 6
+
+
+ DIV_BY_128
+ Prescaler Divide-By-128
+ 7
+
+
+ DIV_BY_256
+ Prescaler Divide-By-256
+ 8
+
+
+ DIV_BY_512
+ Prescaler Divide-By-512
+ 9
+
+
+ DIV_BY_1024
+ Prescaler Divide-By-1024
+ 10
+
+
+ DIV_BY_2048
+ Prescaler Divide-By-2048
+ 11
+
+
+ DIV_BY_4096
+ TBD
+ 12
+
+
+
+
+ POL_B
+ Timer Polarity for Timer B
+ 24
+ 1
+
+
+ PWMSYNC_B
+ PWM Synchronization Mode for Timer B
+ 25
+ 1
+
+
+ NOLHPOL_B
+ PWM Phase A (Non-Overlapping High) Polarity for Timer B
+ 26
+ 1
+
+
+ NOLLPOL_B
+ PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B
+ 27
+ 1
+
+
+ PWMCKBD_B
+ PWM Phase A-Prime Output Disable for Timer B
+ 28
+ 1
+
+
+ RST_B
+ Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears.
+ 29
+ 1
+
+
+ CLKEN_B
+ Write 1 to Enable CLK_TMR for Timer B
+ 30
+ 1
+
+
+ EN_B
+ Enable for Timer B
+ 31
+ 1
+
+
+
+
+ NOLCMP
+ Timer Non-Overlapping Compare Register.
+ 0x14
+ read-write
+
+
+ LO_A
+ Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.
+ 0
+ 8
+
+
+ HI_A
+ Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.
+ 8
+ 8
+
+
+ LO_B
+ Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.
+ 16
+ 8
+
+
+ HI_B
+ Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.
+ 24
+ 8
+
+
+
+
+ CTRL1
+ Timer Configuration Register.
+ 0x18
+ read-write
+
+
+ CLKSEL_A
+ Timer Clock Select for Timer A
+ 0
+ 2
+
+
+ CLKEN_A
+ Timer A Enable Status
+ 2
+ 1
+
+
+ CLKRDY_A
+ CLK_TMR Ready Flag for Timer A
+ 3
+ 1
+
+
+ EVENT_SEL_A
+ Event Select for Timer A
+ 4
+ 3
+
+
+ NEGTRIG_A
+ Negative Edge Trigger for Event for Timer A
+ 7
+ 1
+
+
+ IE_A
+ Interrupt Enable for Timer A
+ 8
+ 1
+
+
+ CAPEVENT_SEL_A
+ Capture Event Select for Timer A
+ 9
+ 2
+
+
+ SW_CAPEVENT_A
+ Software Capture Event for Timer A
+ 11
+ 1
+
+
+ WE_A
+ Wake-Up Enable for Timer A
+ 12
+ 1
+
+
+ OUTEN_A
+ OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A
+ 13
+ 1
+
+
+ OUTBEN_A
+ PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A
+ 14
+ 1
+
+
+ ASYNC
+ Allows asynchronous reads to the PWM and CNT registers.
+ 15
+ 1
+
+
+ CLKSEL_B
+ Timer Clock Select for Timer B
+ 16
+ 2
+
+
+ CLKEN_B
+ Timer B Enable Status
+ 18
+ 1
+
+
+ CLKRDY_B
+ CLK_TMR Ready Flag for Timer B
+ 19
+ 1
+
+
+ EVENT_SEL_B
+ Event Select for Timer B
+ 20
+ 3
+
+
+ NEGTRIG_B
+ Negative Edge Trigger for Event for Timer B
+ 23
+ 1
+
+
+ IE_B
+ Interrupt Enable for Timer B
+ 24
+ 1
+
+
+ CAPEVENT_SEL_B
+ Capture Event Select for Timer B
+ 25
+ 2
+
+
+ SW_CAPEVENT_B
+ Software Capture Event for Timer B
+ 27
+ 1
+
+
+ WE_B
+ Wake-Up Enable for Timer B
+ 28
+ 1
+
+
+ CASCADE
+ Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1.
+ 31
+ 1
+
+
+
+
+ WKFL
+ Timer Wakeup Status Register.
+ 0x1C
+ read-write
+
+
+ A
+ Wake-Up Flag for Timer A
+ 0
+ 1
+
+
+ B
+ Wake-Up Flag for Timer B
+ 16
+ 1
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me17.svd b/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me17.svd
index 5bb17764a0d..a05d5318acd 100644
--- a/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me17.svd
+++ b/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me17.svd
@@ -1,662 +1,668 @@

-
- TMR
- Low-Power Configurable Timer
- 0x40010000
-
- 0x00
- 0x1000
- registers
-
-
- TMR
-
- 1
-
-
-
-
- CNT
- Timer Counter Register.
- 0x00
- read-write
-
-
- COUNT
- The current count value for the timer. This field increments as the timer counts.
- 0
- 32
-
-
-
-
- CMP
- Timer Compare Register.
- 0x04
- read-write
-
-
- COMPARE
- The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer.
- 0
- 32
-
-
-
-
- PWM
- Timer PWM Register.
- 0x08
- read-write
-
-
- PWM
- Timer PWM Match:
+
+ TMR
+ Low-Power Configurable Timer
+ 0x40010000
+
+ 0x00
+ 0x1000
+ registers
+
+
+ TMR
+
+ 1
+
+
+
+
+ CNT
+ Timer Counter Register.
+ 0x00
+ read-write
+
+
+ COUNT
+ The current count value for the timer. This field increments as the timer counts.
+ 0
+ 32
+
+
+
+
+ CMP
+ Timer Compare Register.
+ 0x04
+ read-write
+
+
+ COMPARE
+ The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer.
+ 0
+ 32
+
+
+
+
+ PWM
+ Timer PWM Register.
+ 0x08
+ read-write
+
+
+ PWM
+ Timer PWM Match:
In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value:
In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs.
- 0
- 32
-
-
-
-
- INTFL
- Timer Interrupt Status Register.
- 0x0C
- read-write
-
-
- IRQ_A
- Interrupt Flag for Timer A.
- 0
- 1
-
-
- WRDONE_A
- Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain.
- 8
- 1
-
-
- WR_DIS_A
- Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration.
- 9
- 1
-
-
- IRQ_B
- Interrupt Flag for Timer B.
- 16
- 1
-
-
- WRDONE_B
- Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain.
- 24
- 1
-
-
- WR_DIS_B
- Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration.
- 25
- 1
-
-
-
-
- CTRL0
- Timer Control Register.
- 0x10
- read-write
-
-
- MODE_A
- Mode Select for Timer A
- 0
- 4
-
-
- ONE_SHOT
- One-Shot Mode
- 0
-
-
- CONTINUOUS
- Continuous Mode
- 1
-
-
- COUNTER
- Counter Mode
- 2
-
-
- PWM
- PWM Mode
- 3
-
-
- CAPTURE
- Capture Mode
- 4
-
-
- COMPARE
- Compare Mode
- 5
-
-
- GATED
- Gated Mode
- 6
-
-
- CAPCOMP
- Capture/Compare Mode
- 7
-
-
- DUAL_EDGE
- Dual Edge Capture Mode
- 8
-
-
- IGATED
- Inactive Gated Mode
- 14
-
-
-
-
- CLKDIV_A
- Clock Divider Select for Timer A
- 4
- 4
-
-
- DIV_BY_1
- Prescaler Divide-By-1
- 0
-
-
- DIV_BY_2
- Prescaler Divide-By-2
- 1
-
-
- DIV_BY_4
- Prescaler Divide-By-4
- 2
-
-
- DIV_BY_8
- Prescaler Divide-By-8
- 3
-
-
- DIV_BY_16
- Prescaler Divide-By-16
- 4
-
-
- DIV_BY_32
- Prescaler Divide-By-32
- 5
-
-
- DIV_BY_64
- Prescaler Divide-By-64
- 6
-
-
- DIV_BY_128
- Prescaler Divide-By-128
- 7
-
-
- DIV_BY_256
- Prescaler Divide-By-256
- 8
-
-
- DIV_BY_512
- Prescaler Divide-By-512
- 9
-
-
- DIV_BY_1024
- Prescaler Divide-By-1024
- 10
-
-
- DIV_BY_2048
- Prescaler Divide-By-2048
- 11
-
-
- DIV_BY_4096
- TBD
- 12
-
-
-
-
- POL_A
- Timer Polarity for Timer A
- 8
- 1
-
-
- PWMSYNC_A
- PWM Synchronization Mode for Timer A
- 9
- 1
-
-
- NOLHPOL_A
- PWM Phase A (Non-Overlapping High) Polarity for Timer A
- 10
- 1
-
-
- NOLLPOL_A
- PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A
- 11
- 1
-
-
- PWMCKBD_A
- PWM Phase A-Prime Output Disable for Timer A
- 12
- 1
-
-
- RST_A
- Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears.
- 13
- 1
-
-
- CLKEN_A
- Write 1 to Enable CLK_TMR for Timer A
- 14
- 1
-
-
- EN_A
- Enable for Timer A
- 15
- 1
-
-
- MODE_B
- Mode Select for Timer B
- 16
- 4
-
-
- ONE_SHOT
- One-Shot Mode
- 0
-
-
- CONTINUOUS
- Continuous Mode
- 1
-
-
- COUNTER
- Counter Mode
- 2
-
-
- PWM
- PWM Mode
- 3
-
-
- CAPTURE
- Capture Mode
- 4
-
-
- COMPARE
- Compare Mode
- 5
-
-
- GATED
- Gated Mode
- 6
-
-
- CAPCOMP
- Capture/Compare Mode
- 7
-
-
- DUAL_EDGE
- Dual Edge Capture Mode
- 8
-
-
- IGATED
- Inactive Gated Mode
- 14
-
-
-
-
- CLKDIV_B
- Clock Divider Select for Timer B
- 20
- 4
-
-
- DIV_BY_1
- Prescaler Divide-By-1
- 0
-
-
- DIV_BY_2
- Prescaler Divide-By-2
- 1
-
-
- DIV_BY_4
- Prescaler Divide-By-4
- 2
-
-
- DIV_BY_8
- Prescaler Divide-By-8
- 3
-
-
- DIV_BY_16
- Prescaler Divide-By-16
- 4
-
-
- DIV_BY_32
- Prescaler Divide-By-32
- 5
-
-
- DIV_BY_64
- Prescaler Divide-By-64
- 6
-
-
- DIV_BY_128
- Prescaler Divide-By-128
- 7
-
-
- DIV_BY_256
- Prescaler Divide-By-256
- 8
-
-
- DIV_BY_512
- Prescaler Divide-By-512
- 9
-
-
- DIV_BY_1024
- Prescaler Divide-By-1024
- 10
-
-
- DIV_BY_2048
- Prescaler Divide-By-2048
- 11
-
-
- DIV_BY_4096
- TBD
- 12
-
-
-
-
- POL_B
- Timer Polarity for Timer B
- 24
- 1
-
-
- PWMSYNC_B
- PWM Synchronization Mode for Timer B
- 25
- 1
-
-
- NOLHPOL_B
- PWM Phase A (Non-Overlapping High) Polarity for Timer B
- 26
- 1
-
-
- NOLLPOL_B
- PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B
- 27
- 1
-
-
- PWMCKBD_B
- PWM Phase A-Prime Output Disable for Timer B
- 28
- 1
-
-
- RST_B
- Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears.
- 29
- 1
-
-
- CLKEN_B
- Write 1 to Enable CLK_TMR for Timer B
- 30
- 1
-
-
- EN_B
- Enable for Timer B
- 31
- 1
-
-
-
-
- NOLCMP
- Timer Non-Overlapping Compare Register.
- 0x14
- read-write
-
-
- LO_A
- Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.
- 0
- 8
-
-
- HI_A
- Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.
- 8
- 8
-
-
- LO_B
- Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.
- 16
- 8
-
-
- HI_B
- Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.
- 24
- 8
-
-
-
-
- CTRL1
- Timer Configuration Register.
- 0x18
- read-write
-
-
- CLKSEL_A
- Timer Clock Select for Timer A
- 0
- 2
-
-
- CLKEN_A
- Timer A Enable Status
- 2
- 1
-
-
- CLKRDY_A
- CLK_TMR Ready Flag for Timer A
- 3
- 1
-
-
- EVENT_SEL_A
- Event Select for Timer A
- 4
- 3
-
-
- NEGTRIG_A
- Negative Edge Trigger for Event for Timer A
- 7
- 1
-
-
- IE_A
- Interrupt Enable for Timer A
- 8
- 1
-
-
- CAPEVENT_SEL_A
- Capture Event Select for Timer A
- 9
- 2
-
-
- SW_CAPEVENT_A
- Software Capture Event for Timer A
- 11
- 1
-
-
- WE_A
- Wake-Up Enable for Timer A
- 12
- 1
-
-
- OUTEN_A
- OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A
- 13
- 1
-
-
- OUTBEN_A
- PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A
- 14
- 1
-
-
- CLKSEL_B
- Timer Clock Select for Timer B
- 16
- 2
-
-
- CLKEN_B
- Timer B Enable Status
- 18
- 1
-
-
- CLKRDY_B
- CLK_TMR Ready Flag for Timer B
- 19
- 1
-
-
- EVENT_SEL_B
- Event Select for Timer B
- 20
- 3
-
-
- NEGTRIG_B
- Negative Edge Trigger for Event for Timer B
- 23
- 1
-
-
- IE_B
- Interrupt Enable for Timer B
- 24
- 1
-
-
- CAPEVENT_SEL_B
- Capture Event Select for Timer B
- 25
- 2
-
-
- SW_CAPEVENT_B
- Software Capture Event for Timer B
- 27
- 1
-
-
- WE_B
- Wake-Up Enable for Timer B
- 28
- 1
-
-
- CASCADE
- Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1.
- 31
- 1
-
-
-
-
- WKFL
- Timer Wakeup Status Register.
- 0x1C
- read-write
-
-
- A
- Wake-Up Flag for Timer A
- 0
- 1
-
-
- B
- Wake-Up Flag for Timer B
- 16
- 1
-
-
-
-
-
-
-
+ 0
+ 32
+
+
+
+
+ INTFL
+ Timer Interrupt Status Register.
+ 0x0C
+ read-write
+
+
+ IRQ_A
+ Interrupt Flag for Timer A.
+ 0
+ 1
+
+
+ WRDONE_A
+ Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain.
+ 8
+ 1
+
+
+ WR_DIS_A
+ Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration.
+ 9
+ 1
+
+
+ IRQ_B
+ Interrupt Flag for Timer B.
+ 16
+ 1
+
+
+ WRDONE_B
+ Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain.
+ 24
+ 1
+
+
+ WR_DIS_B
+ Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration.
+ 25
+ 1
+
+
+
+
+ CTRL0
+ Timer Control Register.
+ 0x10
+ read-write
+
+
+ MODE_A
+ Mode Select for Timer A
+ 0
+ 4
+
+
+ ONE_SHOT
+ One-Shot Mode
+ 0
+
+
+ CONTINUOUS
+ Continuous Mode
+ 1
+
+
+ COUNTER
+ Counter Mode
+ 2
+
+
+ PWM
+ PWM Mode
+ 3
+
+
+ CAPTURE
+ Capture Mode
+ 4
+
+
+ COMPARE
+ Compare Mode
+ 5
+
+
+ GATED
+ Gated Mode
+ 6
+
+
+ CAPCOMP
+ Capture/Compare Mode
+ 7
+
+
+ DUAL_EDGE
+ Dual Edge Capture Mode
+ 8
+
+
+ IGATED
+ Inactive Gated Mode
+ 14
+
+
+
+
+ CLKDIV_A
+ Clock Divider Select for Timer A
+ 4
+ 4
+
+
+ DIV_BY_1
+ Prescaler Divide-By-1
+ 0
+
+
+ DIV_BY_2
+ Prescaler Divide-By-2
+ 1
+
+
+ DIV_BY_4
+ Prescaler Divide-By-4
+ 2
+
+
+ DIV_BY_8
+ Prescaler Divide-By-8
+ 3
+
+
+ DIV_BY_16
+ Prescaler Divide-By-16
+ 4
+
+
+ DIV_BY_32
+ Prescaler Divide-By-32
+ 5
+
+
+ DIV_BY_64
+ Prescaler Divide-By-64
+ 6
+
+
+ DIV_BY_128
+ Prescaler Divide-By-128
+ 7
+
+
+ DIV_BY_256
+ Prescaler Divide-By-256
+ 8
+
+
+ DIV_BY_512
+ Prescaler Divide-By-512
+ 9
+
+
+ DIV_BY_1024
+ Prescaler Divide-By-1024
+ 10
+
+
+ DIV_BY_2048
+ Prescaler Divide-By-2048
+ 11
+
+
+ DIV_BY_4096
+ TBD
+ 12
+
+
+
+
+ POL_A
+ Timer Polarity for Timer A
+ 8
+ 1
+
+
+ PWMSYNC_A
+ PWM Synchronization Mode for Timer A
+ 9
+ 1
+
+
+ NOLHPOL_A
+ PWM Phase A (Non-Overlapping High) Polarity for Timer A
+ 10
+ 1
+
+
+ NOLLPOL_A
+ PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A
+ 11
+ 1
+
+
+ PWMCKBD_A
+ PWM Phase A-Prime Output Disable for Timer A
+ 12
+ 1
+
+
+ RST_A
+ Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears.
+ 13
+ 1
+
+
+ CLKEN_A
+ Write 1 to Enable CLK_TMR for Timer A
+ 14
+ 1
+
+
+ EN_A
+ Enable for Timer A
+ 15
+ 1
+
+
+ MODE_B
+ Mode Select for Timer B
+ 16
+ 4
+
+
+ ONE_SHOT
+ One-Shot Mode
+ 0
+
+
+ CONTINUOUS
+ Continuous Mode
+ 1
+
+
+ COUNTER
+ Counter Mode
+ 2
+
+
+ PWM
+ PWM Mode
+ 3
+
+
+ CAPTURE
+ Capture Mode
+ 4
+
+
+ COMPARE
+ Compare Mode
+ 5
+
+
+ GATED
+ Gated Mode
+ 6
+
+
+ CAPCOMP
+ Capture/Compare Mode
+ 7
+
+
+ DUAL_EDGE
+ Dual Edge Capture Mode
+ 8
+
+
+ IGATED
+ Inactive Gated Mode
+ 14
+
+
+
+
+ CLKDIV_B
+ Clock Divider Select for Timer B
+ 20
+ 4
+
+
+ DIV_BY_1
+ Prescaler Divide-By-1
+ 0
+
+
+ DIV_BY_2
+ Prescaler Divide-By-2
+ 1
+
+
+ DIV_BY_4
+ Prescaler Divide-By-4
+ 2
+
+
+ DIV_BY_8
+ Prescaler Divide-By-8
+ 3
+
+
+ DIV_BY_16
+ Prescaler Divide-By-16
+ 4
+
+
+ DIV_BY_32
+ Prescaler Divide-By-32
+ 5
+
+
+ DIV_BY_64
+ Prescaler Divide-By-64
+ 6
+
+
+ DIV_BY_128
+ Prescaler Divide-By-128
+ 7
+
+
+ DIV_BY_256
+ Prescaler Divide-By-256
+ 8
+
+
+ DIV_BY_512
+ Prescaler Divide-By-512
+ 9
+
+
+ DIV_BY_1024
+ Prescaler Divide-By-1024
+ 10
+
+
+ DIV_BY_2048
+ Prescaler Divide-By-2048
+ 11
+
+
+ DIV_BY_4096
+ TBD
+ 12
+
+
+
+
+ POL_B
+ Timer Polarity for Timer B
+ 24
+ 1
+
+
+ PWMSYNC_B
+ PWM Synchronization Mode for Timer B
+ 25
+ 1
+
+
+ NOLHPOL_B
+ PWM Phase A (Non-Overlapping High) Polarity for Timer B
+ 26
+ 1
+
+
+ NOLLPOL_B
+ PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B
+ 27
+ 1
+
+
+ PWMCKBD_B
+ PWM Phase A-Prime Output Disable for Timer B
+ 28
+ 1
+
+
+ RST_B
+ Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears.
+ 29
+ 1
+
+
+ CLKEN_B
+ Write 1 to Enable CLK_TMR for Timer B
+ 30
+ 1
+
+
+ EN_B
+ Enable for Timer B
+ 31
+ 1
+
+
+
+
+ NOLCMP
+ Timer Non-Overlapping Compare Register.
+ 0x14
+ read-write
+
+
+ LO_A
+ Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.
+ 0
+ 8
+
+
+ HI_A
+ Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.
+ 8
+ 8
+
+
+ LO_B
+ Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.
+ 16
+ 8
+
+
+ HI_B
+ Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.
+ 24
+ 8
+
+
+
+
+ CTRL1
+ Timer Configuration Register.
+ 0x18
+ read-write
+
+
+ CLKSEL_A
+ Timer Clock Select for Timer A
+ 0
+ 2
+
+
+ CLKEN_A
+ Timer A Enable Status
+ 2
+ 1
+
+
+ CLKRDY_A
+ CLK_TMR Ready Flag for Timer A
+ 3
+ 1
+
+
+ EVENT_SEL_A
+ Event Select for Timer A
+ 4
+ 3
+
+
+ NEGTRIG_A
+ Negative Edge Trigger for Event for Timer A
+ 7
+ 1
+
+
+ IE_A
+ Interrupt Enable for Timer A
+ 8
+ 1
+
+
+ CAPEVENT_SEL_A
+ Capture Event Select for Timer A
+ 9
+ 2
+
+
+ SW_CAPEVENT_A
+ Software Capture Event for Timer A
+ 11
+ 1
+
+
+ WE_A
+ Wake-Up Enable for Timer A
+ 12
+ 1
+
+
+ OUTEN_A
+ OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A
+ 13
+ 1
+
+
+ OUTBEN_A
+ PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A
+ 14
+ 1
+
+
+ ASYNC
+ Allows asynchronous reads of the PWM and CNT registers.
+ 15
+ 1
+
+
+ CLKSEL_B
+ Timer Clock Select for Timer B
+ 16
+ 2
+
+
+ CLKEN_B
+ Timer B Enable Status
+ 18
+ 1
+
+
+ CLKRDY_B
+ CLK_TMR Ready Flag for Timer B
+ 19
+ 1
+
+
+ EVENT_SEL_B
+ Event Select for Timer B
+ 20
+ 3
+
+
+ NEGTRIG_B
+ Negative Edge Trigger for Event for Timer B
+ 23
+ 1
+
+
+ IE_B
+ Interrupt Enable for Timer B
+ 24
+ 1
+
+
+ CAPEVENT_SEL_B
+ Capture Event Select for Timer B
+ 25
+ 2
+
+
+ SW_CAPEVENT_B
+ Software Capture Event for Timer B
+ 27
+ 1
+
+
+ WE_B
+ Wake-Up Enable for Timer B
+ 28
+ 1
+
+
+ CASCADE
+ Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1.
+ 31
+ 1
+
+
+
+
+ WKFL
+ Timer Wakeup Status Register.
+ 0x1C
+ read-write
+
+
+ A
+ Wake-Up Flag for Timer A
+ 0
+ 1
+
+
+ B
+ Wake-Up Flag for Timer B
+ 16
+ 1
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me21.svd b/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me21.svd
index 03f4811b31f..d591d208d15 100644
--- a/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me21.svd
+++ b/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me21.svd
@@ -1,662 +1,668 @@
-
+
-
- TMR
- Low-Power Configurable Timer
- 0x40010000
-
- 0x00
- 0x1000
- registers
-
-
- TMR
-
- 1
-
-
-
-
- CNT
- Timer Counter Register.
- 0x00
- read-write
-
-
- COUNT
- The current count value for the timer. This field increments as the timer counts.
- 0
- 32
-
-
-
-
- CMP
- Timer Compare Register.
- 0x04
- read-write
-
-
- COMPARE
- The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer.
- 0
- 32
-
-
-
-
- PWM
- Timer PWM Register.
- 0x08
- read-write
-
-
- PWM
- Timer PWM Match:
+
+ TMR
+ Low-Power Configurable Timer
+ 0x40010000
+
+ 0x00
+ 0x1000
+ registers
+
+
+ TMR
+
+ 1
+
+
+
+
+ CNT
+ Timer Counter Register.
+ 0x00
+ read-write
+
+
+ COUNT
+ The current count value for the timer. This field increments as the timer counts.
+ 0
+ 32
+
+
+
+
+ CMP
+ Timer Compare Register.
+ 0x04
+ read-write
+
+
+ COMPARE
+ The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer.
+ 0
+ 32
+
+
+
+
+ PWM
+ Timer PWM Register.
+ 0x08
+ read-write
+
+
+ PWM
+ Timer PWM Match:
In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value:
In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs.
- 0
- 32
-
-
-
-
- INTFL
- Timer Interrupt Status Register.
- 0x0C
- read-write
-
-
- IRQ_A
- Interrupt Flag for Timer A.
- 0
- 1
-
-
- WRDONE_A
- Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain.
- 8
- 1
-
-
- WR_DIS_A
- Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration.
- 9
- 1
-
-
- IRQ_B
- Interrupt Flag for Timer B.
- 16
- 1
-
-
- WRDONE_B
- Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain.
- 24
- 1
-
-
- WR_DIS_B
- Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration.
- 25
- 1
-
-
-
-
- CTRL0
- Timer Control Register.
- 0x10
- read-write
-
-
- MODE_A
- Mode Select for Timer A
- 0
- 4
-
-
- ONE_SHOT
- One-Shot Mode
- 0
-
-
- CONTINUOUS
- Continuous Mode
- 1
-
-
- COUNTER
- Counter Mode
- 2
-
-
- PWM
- PWM Mode
- 3
-
-
- CAPTURE
- Capture Mode
- 4
-
-
- COMPARE
- Compare Mode
- 5
-
-
- GATED
- Gated Mode
- 6
-
-
- CAPCOMP
- Capture/Compare Mode
- 7
-
-
- DUAL_EDGE
- Dual Edge Capture Mode
- 8
-
-
- IGATED
- Inactive Gated Mode
- 12
-
-
-
-
- CLKDIV_A
- Clock Divider Select for Timer A
- 4
- 4
-
-
- DIV_BY_1
- Prescaler Divide-By-1
- 0
-
-
- DIV_BY_2
- Prescaler Divide-By-2
- 1
-
-
- DIV_BY_4
- Prescaler Divide-By-4
- 2
-
-
- DIV_BY_8
- Prescaler Divide-By-8
- 3
-
-
- DIV_BY_16
- Prescaler Divide-By-16
- 4
-
-
- DIV_BY_32
- Prescaler Divide-By-32
- 5
-
-
- DIV_BY_64
- Prescaler Divide-By-64
- 6
-
-
- DIV_BY_128
- Prescaler Divide-By-128
- 7
-
-
- DIV_BY_256
- Prescaler Divide-By-256
- 8
-
-
- DIV_BY_512
- Prescaler Divide-By-512
- 9
-
-
- DIV_BY_1024
- Prescaler Divide-By-1024
- 10
-
-
- DIV_BY_2048
- Prescaler Divide-By-2048
- 11
-
-
- DIV_BY_4096
- TBD
- 12
-
-
-
-
- POL_A
- Timer Polarity for Timer A
- 8
- 1
-
-
- PWMSYNC_A
- PWM Synchronization Mode for Timer A
- 9
- 1
-
-
- NOLHPOL_A
- PWM Phase A (Non-Overlapping High) Polarity for Timer A
- 10
- 1
-
-
- NOLLPOL_A
- PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A
- 11
- 1
-
-
- PWMCKBD_A
- PWM Phase A-Prime Output Disable for Timer A
- 12
- 1
-
-
- RST_A
- Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears.
- 13
- 1
-
-
- CLKEN_A
- Write 1 to Enable CLK_TMR for Timer A
- 14
- 1
-
-
- EN_A
- Enable for Timer A
- 15
- 1
-
-
- MODE_B
- Mode Select for Timer B
- 16
- 4
-
-
- ONE_SHOT
- One-Shot Mode
- 0
-
-
- CONTINUOUS
- Continuous Mode
- 1
-
-
- COUNTER
- Counter Mode
- 2
-
-
- PWM
- PWM Mode
- 3
-
-
- CAPTURE
- Capture Mode
- 4
-
-
- COMPARE
- Compare Mode
- 5
-
-
- GATED
- Gated Mode
- 6
-
-
- CAPCOMP
- Capture/Compare Mode
- 7
-
-
- DUAL_EDGE
- Dual Edge Capture Mode
- 8
-
-
- IGATED
- Inactive Gated Mode
- 14
-
-
-
-
- CLKDIV_B
- Clock Divider Select for Timer B
- 20
- 4
-
-
- DIV_BY_1
- Prescaler Divide-By-1
- 0
-
-
- DIV_BY_2
- Prescaler Divide-By-2
- 1
-
-
- DIV_BY_4
- Prescaler Divide-By-4
- 2
-
-
- DIV_BY_8
- Prescaler Divide-By-8
- 3
-
-
- DIV_BY_16
- Prescaler Divide-By-16
- 4
-
-
- DIV_BY_32
- Prescaler Divide-By-32
- 5
-
-
- DIV_BY_64
- Prescaler Divide-By-64
- 6
-
-
- DIV_BY_128
- Prescaler Divide-By-128
- 7
-
-
- DIV_BY_256
- Prescaler Divide-By-256
- 8
-
-
- DIV_BY_512
- Prescaler Divide-By-512
- 9
-
-
- DIV_BY_1024
- Prescaler Divide-By-1024
- 10
-
-
- DIV_BY_2048
- Prescaler Divide-By-2048
- 11
-
-
- DIV_BY_4096
- TBD
- 12
-
-
-
-
- POL_B
- Timer Polarity for Timer B
- 24
- 1
-
-
- PWMSYNC_B
- PWM Synchronization Mode for Timer B
- 25
- 1
-
-
- NOLHPOL_B
- PWM Phase A (Non-Overlapping High) Polarity for Timer B
- 26
- 1
-
-
- NOLLPOL_B
- PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B
- 27
- 1
-
-
- PWMCKBD_B
- PWM Phase A-Prime Output Disable for Timer B
- 28
- 1
-
-
- RST_B
- Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears.
- 29
- 1
-
-
- CLKEN_B
- Write 1 to Enable CLK_TMR for Timer B
- 30
- 1
-
-
- EN_B
- Enable for Timer B
- 31
- 1
-
-
-
-
- NOLCMP
- Timer Non-Overlapping Compare Register.
- 0x14
- read-write
-
-
- LO_A
- Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.
- 0
- 8
-
-
- HI_A
- Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.
- 8
- 8
-
-
- LO_B
- Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.
- 16
- 8
-
-
- HI_B
- Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.
- 24
- 8
-
-
-
-
- CTRL1
- Timer Configuration Register.
- 0x18
- read-write
-
-
- CLKSEL_A
- Timer Clock Select for Timer A
- 0
- 2
-
-
- CLKEN_A
- Timer A Enable Status
- 2
- 1
-
-
- CLKRDY_A
- CLK_TMR Ready Flag for Timer A
- 3
- 1
-
-
- EVENT_SEL_A
- Event Select for Timer A
- 4
- 3
-
-
- NEGTRIG_A
- Negative Edge Trigger for Event for Timer A
- 7
- 1
-
-
- IE_A
- Interrupt Enable for Timer A
- 8
- 1
-
-
- CAPEVENT_SEL_A
- Capture Event Select for Timer A
- 9
- 2
-
-
- SW_CAPEVENT_A
- Software Capture Event for Timer A
- 11
- 1
-
-
- WE_A
- Wake-Up Enable for Timer A
- 12
- 1
-
-
- OUTEN_A
- OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A
- 13
- 1
-
-
- OUTBEN_A
- PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A
- 14
- 1
-
-
- CLKSEL_B
- Timer Clock Select for Timer B
- 16
- 2
-
-
- CLKEN_B
- Timer B Enable Status
- 18
- 1
-
-
- CLKRDY_B
- CLK_TMR Ready Flag for Timer B
- 19
- 1
-
-
- EVENT_SEL_B
- Event Select for Timer B
- 20
- 3
-
-
- NEGTRIG_B
- Negative Edge Trigger for Event for Timer B
- 23
- 1
-
-
- IE_B
- Interrupt Enable for Timer B
- 24
- 1
-
-
- CAPEVENT_SEL_B
- Capture Event Select for Timer B
- 25
- 2
-
-
- SW_CAPEVENT_B
- Software Capture Event for Timer B
- 27
- 1
-
-
- WE_B
- Wake-Up Enable for Timer B
- 28
- 1
-
-
- CASCADE
- Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1.
- 31
- 1
-
-
-
-
- WKFL
- Timer Wakeup Status Register.
- 0x1C
- read-write
-
-
- A
- Wake-Up Flag for Timer A
- 0
- 1
-
-
- B
- Wake-Up Flag for Timer B
- 16
- 1
-
-
-
-
-
-
-
+ 0
+ 32
+
+
+
+
+ INTFL
+ Timer Interrupt Status Register.
+ 0x0C
+ read-write
+
+
+ IRQ_A
+ Interrupt Flag for Timer A.
+ 0
+ 1
+
+
+ WRDONE_A
+ Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain.
+ 8
+ 1
+
+
+ WR_DIS_A
+ Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration.
+ 9
+ 1
+
+
+ IRQ_B
+ Interrupt Flag for Timer B.
+ 16
+ 1
+
+
+ WRDONE_B
+ Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain.
+ 24
+ 1
+
+
+ WR_DIS_B
+ Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration.
+ 25
+ 1
+
+
+
+
+ CTRL0
+ Timer Control Register.
+ 0x10
+ read-write
+
+
+ MODE_A
+ Mode Select for Timer A
+ 0
+ 4
+
+
+ ONE_SHOT
+ One-Shot Mode
+ 0
+
+
+ CONTINUOUS
+ Continuous Mode
+ 1
+
+
+ COUNTER
+ Counter Mode
+ 2
+
+
+ PWM
+ PWM Mode
+ 3
+
+
+ CAPTURE
+ Capture Mode
+ 4
+
+
+ COMPARE
+ Compare Mode
+ 5
+
+
+ GATED
+ Gated Mode
+ 6
+
+
+ CAPCOMP
+ Capture/Compare Mode
+ 7
+
+
+ DUAL_EDGE
+ Dual Edge Capture Mode
+ 8
+
+
+ IGATED
+ Inactive Gated Mode
+ 12
+
+
+
+
+ CLKDIV_A
+ Clock Divider Select for Timer A
+ 4
+ 4
+
+
+ DIV_BY_1
+ Prescaler Divide-By-1
+ 0
+
+
+ DIV_BY_2
+ Prescaler Divide-By-2
+ 1
+
+
+ DIV_BY_4
+ Prescaler Divide-By-4
+ 2
+
+
+ DIV_BY_8
+ Prescaler Divide-By-8
+ 3
+
+
+ DIV_BY_16
+ Prescaler Divide-By-16
+ 4
+
+
+ DIV_BY_32
+ Prescaler Divide-By-32
+ 5
+
+
+ DIV_BY_64
+ Prescaler Divide-By-64
+ 6
+
+
+ DIV_BY_128
+ Prescaler Divide-By-128
+ 7
+
+
+ DIV_BY_256
+ Prescaler Divide-By-256
+ 8
+
+
+ DIV_BY_512
+ Prescaler Divide-By-512
+ 9
+
+
+ DIV_BY_1024
+ Prescaler Divide-By-1024
+ 10
+
+
+ DIV_BY_2048
+ Prescaler Divide-By-2048
+ 11
+
+
+ DIV_BY_4096
+ TBD
+ 12
+
+
+
+
+ POL_A
+ Timer Polarity for Timer A
+ 8
+ 1
+
+
+ PWMSYNC_A
+ PWM Synchronization Mode for Timer A
+ 9
+ 1
+
+
+ NOLHPOL_A
+ PWM Phase A (Non-Overlapping High) Polarity for Timer A
+ 10
+ 1
+
+
+ NOLLPOL_A
+ PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A
+ 11
+ 1
+
+
+ PWMCKBD_A
+ PWM Phase A-Prime Output Disable for Timer A
+ 12
+ 1
+
+
+ RST_A
+ Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears.
+ 13
+ 1
+
+
+ CLKEN_A
+ Write 1 to Enable CLK_TMR for Timer A
+ 14
+ 1
+
+
+ EN_A
+ Enable for Timer A
+ 15
+ 1
+
+
+ MODE_B
+ Mode Select for Timer B
+ 16
+ 4
+
+
+ ONE_SHOT
+ One-Shot Mode
+ 0
+
+
+ CONTINUOUS
+ Continuous Mode
+ 1
+
+
+ COUNTER
+ Counter Mode
+ 2
+
+
+ PWM
+ PWM Mode
+ 3
+
+
+ CAPTURE
+ Capture Mode
+ 4
+
+
+ COMPARE
+ Compare Mode
+ 5
+
+
+ GATED
+ Gated Mode
+ 6
+
+
+ CAPCOMP
+ Capture/Compare Mode
+ 7
+
+
+ DUAL_EDGE
+ Dual Edge Capture Mode
+ 8
+
+
+ IGATED
+ Inactive Gated Mode
+ 14
+
+
+
+
+ CLKDIV_B
+ Clock Divider Select for Timer B
+ 20
+ 4
+
+
+ DIV_BY_1
+ Prescaler Divide-By-1
+ 0
+
+
+ DIV_BY_2
+ Prescaler Divide-By-2
+ 1
+
+
+ DIV_BY_4
+ Prescaler Divide-By-4
+ 2
+
+
+ DIV_BY_8
+ Prescaler Divide-By-8
+ 3
+
+
+ DIV_BY_16
+ Prescaler Divide-By-16
+ 4
+
+
+ DIV_BY_32
+ Prescaler Divide-By-32
+ 5
+
+
+ DIV_BY_64
+ Prescaler Divide-By-64
+ 6
+
+
+ DIV_BY_128
+ Prescaler Divide-By-128
+ 7
+
+
+ DIV_BY_256
+ Prescaler Divide-By-256
+ 8
+
+
+ DIV_BY_512
+ Prescaler Divide-By-512
+ 9
+
+
+ DIV_BY_1024
+ Prescaler Divide-By-1024
+ 10
+
+
+ DIV_BY_2048
+ Prescaler Divide-By-2048
+ 11
+
+
+ DIV_BY_4096
+ TBD
+ 12
+
+
+
+
+ POL_B
+ Timer Polarity for Timer B
+ 24
+ 1
+
+
+ PWMSYNC_B
+ PWM Synchronization Mode for Timer B
+ 25
+ 1
+
+
+ NOLHPOL_B
+ PWM Phase A (Non-Overlapping High) Polarity for Timer B
+ 26
+ 1
+
+
+ NOLLPOL_B
+ PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B
+ 27
+ 1
+
+
+ PWMCKBD_B
+ PWM Phase A-Prime Output Disable for Timer B
+ 28
+ 1
+
+
+ RST_B
+ Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears.
+ 29
+ 1
+
+
+ CLKEN_B
+ Write 1 to Enable CLK_TMR for Timer B
+ 30
+ 1
+
+
+ EN_B
+ Enable for Timer B
+ 31
+ 1
+
+
+
+
+ NOLCMP
+ Timer Non-Overlapping Compare Register.
+ 0x14
+ read-write
+
+
+ LO_A
+ Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.
+ 0
+ 8
+
+
+ HI_A
+ Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.
+ 8
+ 8
+
+
+ LO_B
+ Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.
+ 16
+ 8
+
+
+ HI_B
+ Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.
+ 24
+ 8
+
+
+
+
+ CTRL1
+ Timer Configuration Register.
+ 0x18
+ read-write
+
+
+ CLKSEL_A
+ Timer Clock Select for Timer A
+ 0
+ 2
+
+
+ CLKEN_A
+ Timer A Enable Status
+ 2
+ 1
+
+
+ CLKRDY_A
+ CLK_TMR Ready Flag for Timer A
+ 3
+ 1
+
+
+ EVENT_SEL_A
+ Event Select for Timer A
+ 4
+ 3
+
+
+ NEGTRIG_A
+ Negative Edge Trigger for Event for Timer A
+ 7
+ 1
+
+
+ IE_A
+ Interrupt Enable for Timer A
+ 8
+ 1
+
+
+ CAPEVENT_SEL_A
+ Capture Event Select for Timer A
+ 9
+ 2
+
+
+ SW_CAPEVENT_A
+ Software Capture Event for Timer A
+ 11
+ 1
+
+
+ WE_A
+ Wake-Up Enable for Timer A
+ 12
+ 1
+
+
+ OUTEN_A
+ OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A
+ 13
+ 1
+
+
+ OUTBEN_A
+ PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A
+ 14
+ 1
+
+
+ ASYNC
+ Allows asynchronous reads to the PWM and CNT registers.
+ 15
+ 1
+
+
+ CLKSEL_B
+ Timer Clock Select for Timer B
+ 16
+ 2
+
+
+ CLKEN_B
+ Timer B Enable Status
+ 18
+ 1
+
+
+ CLKRDY_B
+ CLK_TMR Ready Flag for Timer B
+ 19
+ 1
+
+
+ EVENT_SEL_B
+ Event Select for Timer B
+ 20
+ 3
+
+
+ NEGTRIG_B
+ Negative Edge Trigger for Event for Timer B
+ 23
+ 1
+
+
+ IE_B
+ Interrupt Enable for Timer B
+ 24
+ 1
+
+
+ CAPEVENT_SEL_B
+ Capture Event Select for Timer B
+ 25
+ 2
+
+
+ SW_CAPEVENT_B
+ Software Capture Event for Timer B
+ 27
+ 1
+
+
+ WE_B
+ Wake-Up Enable for Timer B
+ 28
+ 1
+
+
+ CASCADE
+ Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1.
+ 31
+ 1
+
+
+
+
+ WKFL
+ Timer Wakeup Status Register.
+ 0x1C
+ read-write
+
+
+ A
+ Wake-Up Flag for Timer A
+ 0
+ 1
+
+
+ B
+ Wake-Up Flag for Timer B
+ 16
+ 1
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me30.svd b/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me30.svd
index 5bb17764a0d..bb65faa3897 100644
--- a/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me30.svd
+++ b/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me30.svd
@@ -1,662 +1,668 @@

-
- TMR
- Low-Power Configurable Timer
- 0x40010000
-
- 0x00
- 0x1000
- registers
-
-
- TMR
-
- 1
-
-
-
-
- CNT
- Timer Counter Register.
- 0x00
- read-write
-
-
- COUNT
- The current count value for the timer. This field increments as the timer counts.
- 0
- 32
-
-
-
-
- CMP
- Timer Compare Register.
- 0x04
- read-write
-
-
- COMPARE
- The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer.
- 0
- 32
-
-
-
-
- PWM
- Timer PWM Register.
- 0x08
- read-write
-
-
- PWM
- Timer PWM Match:
+
+ TMR
+ Low-Power Configurable Timer
+ 0x40010000
+
+ 0x00
+ 0x1000
+ registers
+
+
+ TMR
+
+ 1
+
+
+
+
+ CNT
+ Timer Counter Register.
+ 0x00
+ read-write
+
+
+ COUNT
+ The current count value for the timer. This field increments as the timer counts.
+ 0
+ 32
+
+
+
+
+ CMP
+ Timer Compare Register.
+ 0x04
+ read-write
+
+
+ COMPARE
+ The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer.
+ 0
+ 32
+
+
+
+
+ PWM
+ Timer PWM Register.
+ 0x08
+ read-write
+
+
+ PWM
+ Timer PWM Match:
In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value:
In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs.
- 0
- 32
-
-
-
-
- INTFL
- Timer Interrupt Status Register.
- 0x0C
- read-write
-
-
- IRQ_A
- Interrupt Flag for Timer A.
- 0
- 1
-
-
- WRDONE_A
- Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain.
- 8
- 1
-
-
- WR_DIS_A
- Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration.
- 9
- 1
-
-
- IRQ_B
- Interrupt Flag for Timer B.
- 16
- 1
-
-
- WRDONE_B
- Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain.
- 24
- 1
-
-
- WR_DIS_B
- Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration.
- 25
- 1
-
-
-
-
- CTRL0
- Timer Control Register.
- 0x10
- read-write
-
-
- MODE_A
- Mode Select for Timer A
- 0
- 4
-
-
- ONE_SHOT
- One-Shot Mode
- 0
-
-
- CONTINUOUS
- Continuous Mode
- 1
-
-
- COUNTER
- Counter Mode
- 2
-
-
- PWM
- PWM Mode
- 3
-
-
- CAPTURE
- Capture Mode
- 4
-
-
- COMPARE
- Compare Mode
- 5
-
-
- GATED
- Gated Mode
- 6
-
-
- CAPCOMP
- Capture/Compare Mode
- 7
-
-
- DUAL_EDGE
- Dual Edge Capture Mode
- 8
-
-
- IGATED
- Inactive Gated Mode
- 14
-
-
-
-
- CLKDIV_A
- Clock Divider Select for Timer A
- 4
- 4
-
-
- DIV_BY_1
- Prescaler Divide-By-1
- 0
-
-
- DIV_BY_2
- Prescaler Divide-By-2
- 1
-
-
- DIV_BY_4
- Prescaler Divide-By-4
- 2
-
-
- DIV_BY_8
- Prescaler Divide-By-8
- 3
-
-
- DIV_BY_16
- Prescaler Divide-By-16
- 4
-
-
- DIV_BY_32
- Prescaler Divide-By-32
- 5
-
-
- DIV_BY_64
- Prescaler Divide-By-64
- 6
-
-
- DIV_BY_128
- Prescaler Divide-By-128
- 7
-
-
- DIV_BY_256
- Prescaler Divide-By-256
- 8
-
-
- DIV_BY_512
- Prescaler Divide-By-512
- 9
-
-
- DIV_BY_1024
- Prescaler Divide-By-1024
- 10
-
-
- DIV_BY_2048
- Prescaler Divide-By-2048
- 11
-
-
- DIV_BY_4096
- TBD
- 12
-
-
-
-
- POL_A
- Timer Polarity for Timer A
- 8
- 1
-
-
- PWMSYNC_A
- PWM Synchronization Mode for Timer A
- 9
- 1
-
-
- NOLHPOL_A
- PWM Phase A (Non-Overlapping High) Polarity for Timer A
- 10
- 1
-
-
- NOLLPOL_A
- PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A
- 11
- 1
-
-
- PWMCKBD_A
- PWM Phase A-Prime Output Disable for Timer A
- 12
- 1
-
-
- RST_A
- Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears.
- 13
- 1
-
-
- CLKEN_A
- Write 1 to Enable CLK_TMR for Timer A
- 14
- 1
-
-
- EN_A
- Enable for Timer A
- 15
- 1
-
-
- MODE_B
- Mode Select for Timer B
- 16
- 4
-
-
- ONE_SHOT
- One-Shot Mode
- 0
-
-
- CONTINUOUS
- Continuous Mode
- 1
-
-
- COUNTER
- Counter Mode
- 2
-
-
- PWM
- PWM Mode
- 3
-
-
- CAPTURE
- Capture Mode
- 4
-
-
- COMPARE
- Compare Mode
- 5
-
-
- GATED
- Gated Mode
- 6
-
-
- CAPCOMP
- Capture/Compare Mode
- 7
-
-
- DUAL_EDGE
- Dual Edge Capture Mode
- 8
-
-
- IGATED
- Inactive Gated Mode
- 14
-
-
-
-
- CLKDIV_B
- Clock Divider Select for Timer B
- 20
- 4
-
-
- DIV_BY_1
- Prescaler Divide-By-1
- 0
-
-
- DIV_BY_2
- Prescaler Divide-By-2
- 1
-
-
- DIV_BY_4
- Prescaler Divide-By-4
- 2
-
-
- DIV_BY_8
- Prescaler Divide-By-8
- 3
-
-
- DIV_BY_16
- Prescaler Divide-By-16
- 4
-
-
- DIV_BY_32
- Prescaler Divide-By-32
- 5
-
-
- DIV_BY_64
- Prescaler Divide-By-64
- 6
-
-
- DIV_BY_128
- Prescaler Divide-By-128
- 7
-
-
- DIV_BY_256
- Prescaler Divide-By-256
- 8
-
-
- DIV_BY_512
- Prescaler Divide-By-512
- 9
-
-
- DIV_BY_1024
- Prescaler Divide-By-1024
- 10
-
-
- DIV_BY_2048
- Prescaler Divide-By-2048
- 11
-
-
- DIV_BY_4096
- TBD
- 12
-
-
-
-
- POL_B
- Timer Polarity for Timer B
- 24
- 1
-
-
- PWMSYNC_B
- PWM Synchronization Mode for Timer B
- 25
- 1
-
-
- NOLHPOL_B
- PWM Phase A (Non-Overlapping High) Polarity for Timer B
- 26
- 1
-
-
- NOLLPOL_B
- PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B
- 27
- 1
-
-
- PWMCKBD_B
- PWM Phase A-Prime Output Disable for Timer B
- 28
- 1
-
-
- RST_B
- Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears.
- 29
- 1
-
-
- CLKEN_B
- Write 1 to Enable CLK_TMR for Timer B
- 30
- 1
-
-
- EN_B
- Enable for Timer B
- 31
- 1
-
-
-
-
- NOLCMP
- Timer Non-Overlapping Compare Register.
- 0x14
- read-write
-
-
- LO_A
- Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.
- 0
- 8
-
-
- HI_A
- Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.
- 8
- 8
-
-
- LO_B
- Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.
- 16
- 8
-
-
- HI_B
- Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.
- 24
- 8
-
-
-
-
- CTRL1
- Timer Configuration Register.
- 0x18
- read-write
-
-
- CLKSEL_A
- Timer Clock Select for Timer A
- 0
- 2
-
-
- CLKEN_A
- Timer A Enable Status
- 2
- 1
-
-
- CLKRDY_A
- CLK_TMR Ready Flag for Timer A
- 3
- 1
-
-
- EVENT_SEL_A
- Event Select for Timer A
- 4
- 3
-
-
- NEGTRIG_A
- Negative Edge Trigger for Event for Timer A
- 7
- 1
-
-
- IE_A
- Interrupt Enable for Timer A
- 8
- 1
-
-
- CAPEVENT_SEL_A
- Capture Event Select for Timer A
- 9
- 2
-
-
- SW_CAPEVENT_A
- Software Capture Event for Timer A
- 11
- 1
-
-
- WE_A
- Wake-Up Enable for Timer A
- 12
- 1
-
-
- OUTEN_A
- OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A
- 13
- 1
-
-
- OUTBEN_A
- PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A
- 14
- 1
-
-
- CLKSEL_B
- Timer Clock Select for Timer B
- 16
- 2
-
-
- CLKEN_B
- Timer B Enable Status
- 18
- 1
-
-
- CLKRDY_B
- CLK_TMR Ready Flag for Timer B
- 19
- 1
-
-
- EVENT_SEL_B
- Event Select for Timer B
- 20
- 3
-
-
- NEGTRIG_B
- Negative Edge Trigger for Event for Timer B
- 23
- 1
-
-
- IE_B
- Interrupt Enable for Timer B
- 24
- 1
-
-
- CAPEVENT_SEL_B
- Capture Event Select for Timer B
- 25
- 2
-
-
- SW_CAPEVENT_B
- Software Capture Event for Timer B
- 27
- 1
-
-
- WE_B
- Wake-Up Enable for Timer B
- 28
- 1
-
-
- CASCADE
- Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1.
- 31
- 1
-
-
-
-
- WKFL
- Timer Wakeup Status Register.
- 0x1C
- read-write
-
-
- A
- Wake-Up Flag for Timer A
- 0
- 1
-
-
- B
- Wake-Up Flag for Timer B
- 16
- 1
-
-
-
-
-
-
-
+ 0
+ 32
+
+
+
+
+ INTFL
+ Timer Interrupt Status Register.
+ 0x0C
+ read-write
+
+
+ IRQ_A
+ Interrupt Flag for Timer A.
+ 0
+ 1
+
+
+ WRDONE_A
+ Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain.
+ 8
+ 1
+
+
+ WR_DIS_A
+ Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration.
+ 9
+ 1
+
+
+ IRQ_B
+ Interrupt Flag for Timer B.
+ 16
+ 1
+
+
+ WRDONE_B
+ Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain.
+ 24
+ 1
+
+
+ WR_DIS_B
+ Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration.
+ 25
+ 1
+
+
+
+
+ CTRL0
+ Timer Control Register.
+ 0x10
+ read-write
+
+
+ MODE_A
+ Mode Select for Timer A
+ 0
+ 4
+
+
+ ONE_SHOT
+ One-Shot Mode
+ 0
+
+
+ CONTINUOUS
+ Continuous Mode
+ 1
+
+
+ COUNTER
+ Counter Mode
+ 2
+
+
+ PWM
+ PWM Mode
+ 3
+
+
+ CAPTURE
+ Capture Mode
+ 4
+
+
+ COMPARE
+ Compare Mode
+ 5
+
+
+ GATED
+ Gated Mode
+ 6
+
+
+ CAPCOMP
+ Capture/Compare Mode
+ 7
+
+
+ DUAL_EDGE
+ Dual Edge Capture Mode
+ 8
+
+
+ IGATED
+ Inactive Gated Mode
+ 14
+
+
+
+
+ CLKDIV_A
+ Clock Divider Select for Timer A
+ 4
+ 4
+
+
+ DIV_BY_1
+ Prescaler Divide-By-1
+ 0
+
+
+ DIV_BY_2
+ Prescaler Divide-By-2
+ 1
+
+
+ DIV_BY_4
+ Prescaler Divide-By-4
+ 2
+
+
+ DIV_BY_8
+ Prescaler Divide-By-8
+ 3
+
+
+ DIV_BY_16
+ Prescaler Divide-By-16
+ 4
+
+
+ DIV_BY_32
+ Prescaler Divide-By-32
+ 5
+
+
+ DIV_BY_64
+ Prescaler Divide-By-64
+ 6
+
+
+ DIV_BY_128
+ Prescaler Divide-By-128
+ 7
+
+
+ DIV_BY_256
+ Prescaler Divide-By-256
+ 8
+
+
+ DIV_BY_512
+ Prescaler Divide-By-512
+ 9
+
+
+ DIV_BY_1024
+ Prescaler Divide-By-1024
+ 10
+
+
+ DIV_BY_2048
+ Prescaler Divide-By-2048
+ 11
+
+
+ DIV_BY_4096
+ TBD
+ 12
+
+
+
+
+ POL_A
+ Timer Polarity for Timer A
+ 8
+ 1
+
+
+ PWMSYNC_A
+ PWM Synchronization Mode for Timer A
+ 9
+ 1
+
+
+ NOLHPOL_A
+ PWM Phase A (Non-Overlapping High) Polarity for Timer A
+ 10
+ 1
+
+
+ NOLLPOL_A
+ PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A
+ 11
+ 1
+
+
+ PWMCKBD_A
+ PWM Phase A-Prime Output Disable for Timer A
+ 12
+ 1
+
+
+ RST_A
+ Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears.
+ 13
+ 1
+
+
+ CLKEN_A
+ Write 1 to Enable CLK_TMR for Timer A
+ 14
+ 1
+
+
+ EN_A
+ Enable for Timer A
+ 15
+ 1
+
+
+ MODE_B
+ Mode Select for Timer B
+ 16
+ 4
+
+
+ ONE_SHOT
+ One-Shot Mode
+ 0
+
+
+ CONTINUOUS
+ Continuous Mode
+ 1
+
+
+ COUNTER
+ Counter Mode
+ 2
+
+
+ PWM
+ PWM Mode
+ 3
+
+
+ CAPTURE
+ Capture Mode
+ 4
+
+
+ COMPARE
+ Compare Mode
+ 5
+
+
+ GATED
+ Gated Mode
+ 6
+
+
+ CAPCOMP
+ Capture/Compare Mode
+ 7
+
+
+ DUAL_EDGE
+ Dual Edge Capture Mode
+ 8
+
+
+ IGATED
+ Inactive Gated Mode
+ 14
+
+
+
+
+ CLKDIV_B
+ Clock Divider Select for Timer B
+ 20
+ 4
+
+
+ DIV_BY_1
+ Prescaler Divide-By-1
+ 0
+
+
+ DIV_BY_2
+ Prescaler Divide-By-2
+ 1
+
+
+ DIV_BY_4
+ Prescaler Divide-By-4
+ 2
+
+
+ DIV_BY_8
+ Prescaler Divide-By-8
+ 3
+
+
+ DIV_BY_16
+ Prescaler Divide-By-16
+ 4
+
+
+ DIV_BY_32
+ Prescaler Divide-By-32
+ 5
+
+
+ DIV_BY_64
+ Prescaler Divide-By-64
+ 6
+
+
+ DIV_BY_128
+ Prescaler Divide-By-128
+ 7
+
+
+ DIV_BY_256
+ Prescaler Divide-By-256
+ 8
+
+
+ DIV_BY_512
+ Prescaler Divide-By-512
+ 9
+
+
+ DIV_BY_1024
+ Prescaler Divide-By-1024
+ 10
+
+
+ DIV_BY_2048
+ Prescaler Divide-By-2048
+ 11
+
+
+ DIV_BY_4096
+ TBD
+ 12
+
+
+
+
+ POL_B
+ Timer Polarity for Timer B
+ 24
+ 1
+
+
+ PWMSYNC_B
+ PWM Synchronization Mode for Timer B
+ 25
+ 1
+
+
+ NOLHPOL_B
+ PWM Phase A (Non-Overlapping High) Polarity for Timer B
+ 26
+ 1
+
+
+ NOLLPOL_B
+ PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B
+ 27
+ 1
+
+
+ PWMCKBD_B
+ PWM Phase A-Prime Output Disable for Timer B
+ 28
+ 1
+
+
+ RST_B
+ Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears.
+ 29
+ 1
+
+
+ CLKEN_B
+ Write 1 to Enable CLK_TMR for Timer B
+ 30
+ 1
+
+
+ EN_B
+ Enable for Timer B
+ 31
+ 1
+
+
+
+
+ NOLCMP
+ Timer Non-Overlapping Compare Register.
+ 0x14
+ read-write
+
+
+ LO_A
+ Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.
+ 0
+ 8
+
+
+ HI_A
+ Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.
+ 8
+ 8
+
+
+ LO_B
+ Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.
+ 16
+ 8
+
+
+ HI_B
+ Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.
+ 24
+ 8
+
+
+
+
+ CTRL1
+ Timer Configuration Register.
+ 0x18
+ read-write
+
+
+ CLKSEL_A
+ Timer Clock Select for Timer A
+ 0
+ 2
+
+
+ CLKEN_A
+ Timer A Enable Status
+ 2
+ 1
+
+
+ CLKRDY_A
+ CLK_TMR Ready Flag for Timer A
+ 3
+ 1
+
+
+ EVENT_SEL_A
+ Event Select for Timer A
+ 4
+ 3
+
+
+ NEGTRIG_A
+ Negative Edge Trigger for Event for Timer A
+ 7
+ 1
+
+
+ IE_A
+ Interrupt Enable for Timer A
+ 8
+ 1
+
+
+ CAPEVENT_SEL_A
+ Capture Event Select for Timer A
+ 9
+ 2
+
+
+ SW_CAPEVENT_A
+ Software Capture Event for Timer A
+ 11
+ 1
+
+
+ WE_A
+ Wake-Up Enable for Timer A
+ 12
+ 1
+
+
+ OUTEN_A
+ OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A
+ 13
+ 1
+
+
+ OUTBEN_A
+ PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A
+ 14
+ 1
+
+
+ ASYNC
+ Allows asynchronous reads to the PWM and CNT registers.
+ 15
+ 1
+
+
+ CLKSEL_B
+ Timer Clock Select for Timer B
+ 16
+ 2
+
+
+ CLKEN_B
+ Timer B Enable Status
+ 18
+ 1
+
+
+ CLKRDY_B
+ CLK_TMR Ready Flag for Timer B
+ 19
+ 1
+
+
+ EVENT_SEL_B
+ Event Select for Timer B
+ 20
+ 3
+
+
+ NEGTRIG_B
+ Negative Edge Trigger for Event for Timer B
+ 23
+ 1
+
+
+ IE_B
+ Interrupt Enable for Timer B
+ 24
+ 1
+
+
+ CAPEVENT_SEL_B
+ Capture Event Select for Timer B
+ 25
+ 2
+
+
+ SW_CAPEVENT_B
+ Software Capture Event for Timer B
+ 27
+ 1
+
+
+ WE_B
+ Wake-Up Enable for Timer B
+ 28
+ 1
+
+
+ CASCADE
+ Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1.
+ 31
+ 1
+
+
+
+
+ WKFL
+ Timer Wakeup Status Register.
+ 0x1C
+ read-write
+
+
+ A
+ Wake-Up Flag for Timer A
+ 0
+ 1
+
+
+ B
+ Wake-Up Flag for Timer B
+ 16
+ 1
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Libraries/PeriphDrivers/Source/TMR/tmr_revb_regs.h b/Libraries/PeriphDrivers/Source/TMR/tmr_revb_regs.h
index 282738bdf30..ae3f65ca0e9 100644
--- a/Libraries/PeriphDrivers/Source/TMR/tmr_revb_regs.h
+++ b/Libraries/PeriphDrivers/Source/TMR/tmr_revb_regs.h
@@ -1,6 +1,8 @@
/**
* @file tmr_revb_regs.h
* @brief Registers, Bit Masks and Bit Positions for the TMR_REVB Peripheral Module.
+ * @note This file is @generated.
+ * @ingroup tmr_revb_registers
*/
/******************************************************************************
@@ -23,8 +25,8 @@
*
******************************************************************************/
-#ifndef _TMR_REVB_REGS_H_
-#define _TMR_REVB_REGS_H_
+#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_REVB_REGS_H_
+#define LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_REVB_REGS_H_
/* **** Includes **** */
#include
@@ -32,11 +34,11 @@
#ifdef __cplusplus
extern "C" {
#endif
-
+
#if defined (__ICCARM__)
#pragma system_include
#endif
-
+
#if defined (__CC_ARM)
#pragma anon_unions
#endif
@@ -48,7 +50,11 @@ extern "C" {
#define __IO volatile
#endif
#ifndef __I
-#define __I volatile const
+#ifdef __cplusplus
+#define __I volatile
+#else
+#define __I volatile const
+#endif
#endif
#ifndef __O
#define __O volatile
@@ -64,7 +70,7 @@ extern "C" {
* @ingroup tmr_revb
* @defgroup tmr_revb_registers TMR_REVB_Registers
* @brief Registers, Bit Masks and Bit Positions for the TMR_REVB Peripheral Module.
- * @details Low-Power Configurable Timer
+ * @details Low-Power Configurable Timer
*/
/**
@@ -82,31 +88,14 @@ typedef struct {
__IO uint32_t wkfl; /**< \b 0x1C: TMR_REVB WKFL Register */
} mxc_tmr_revb_regs_t;
-/* Register offsets for module TMR_REVB */
-/**
- * @ingroup tmr_revb_registers
- * @defgroup TMR_REVB_Register_Offsets Register Offsets
- * @brief TMR_REVB Peripheral Register Offsets from the TMR_REVB Base Peripheral Address.
- * @{
- */
- #define MXC_R_TMR_REVB_CNT ((uint32_t)0x00000000UL) /**< Offset from TMR_REVB Base Address: 0x0000 */
- #define MXC_R_TMR_REVB_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR_REVB Base Address: 0x0004 */
- #define MXC_R_TMR_REVB_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR_REVB Base Address: 0x0008 */
- #define MXC_R_TMR_REVB_INTFL ((uint32_t)0x0000000CUL) /**< Offset from TMR_REVB Base Address: 0x000C */
- #define MXC_R_TMR_REVB_CTRL0 ((uint32_t)0x00000010UL) /**< Offset from TMR_REVB Base Address: 0x0010 */
- #define MXC_R_TMR_REVB_NOLCMP ((uint32_t)0x00000014UL) /**< Offset from TMR_REVB Base Address: 0x0014 */
- #define MXC_R_TMR_REVB_CTRL1 ((uint32_t)0x00000018UL) /**< Offset from TMR_REVB Base Address: 0x0018 */
- #define MXC_R_TMR_REVB_WKFL ((uint32_t)0x0000001CUL) /**< Offset from TMR_REVB Base Address: 0x001C */
-/**@} end of group tmr_revb_registers */
-
/**
* @ingroup tmr_revb_registers
* @defgroup TMR_REVB_CNT TMR_REVB_CNT
* @brief Timer Counter Register.
* @{
*/
- #define MXC_F_TMR_REVB_CNT_COUNT_POS 0 /**< CNT_COUNT Position */
- #define MXC_F_TMR_REVB_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_REVB_CNT_COUNT_POS)) /**< CNT_COUNT Mask */
+#define MXC_F_TMR_REVB_CNT_COUNT_POS 0 /**< CNT_COUNT Position */
+#define MXC_F_TMR_REVB_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_REVB_CNT_COUNT_POS)) /**< CNT_COUNT Mask */
/**@} end of group TMR_REVB_CNT_Register */
@@ -116,8 +105,8 @@ typedef struct {
* @brief Timer Compare Register.
* @{
*/
- #define MXC_F_TMR_REVB_CMP_COMPARE_POS 0 /**< CMP_COMPARE Position */
- #define MXC_F_TMR_REVB_CMP_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_REVB_CMP_COMPARE_POS)) /**< CMP_COMPARE Mask */
+#define MXC_F_TMR_REVB_CMP_COMPARE_POS 0 /**< CMP_COMPARE Position */
+#define MXC_F_TMR_REVB_CMP_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_REVB_CMP_COMPARE_POS)) /**< CMP_COMPARE Mask */
/**@} end of group TMR_REVB_CMP_Register */
@@ -127,8 +116,8 @@ typedef struct {
* @brief Timer PWM Register.
* @{
*/
- #define MXC_F_TMR_REVB_PWM_PWM_POS 0 /**< PWM_PWM Position */
- #define MXC_F_TMR_REVB_PWM_PWM ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_REVB_PWM_PWM_POS)) /**< PWM_PWM Mask */
+#define MXC_F_TMR_REVB_PWM_PWM_POS 0 /**< PWM_PWM Position */
+#define MXC_F_TMR_REVB_PWM_PWM ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_REVB_PWM_PWM_POS)) /**< PWM_PWM Mask */
/**@} end of group TMR_REVB_PWM_Register */
@@ -138,23 +127,23 @@ typedef struct {
* @brief Timer Interrupt Status Register.
* @{
*/
- #define MXC_F_TMR_REVB_INTFL_IRQ_A_POS 0 /**< INTFL_IRQ_A Position */
- #define MXC_F_TMR_REVB_INTFL_IRQ_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_IRQ_A_POS)) /**< INTFL_IRQ_A Mask */
+#define MXC_F_TMR_REVB_INTFL_IRQ_A_POS 0 /**< INTFL_IRQ_A Position */
+#define MXC_F_TMR_REVB_INTFL_IRQ_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_IRQ_A_POS)) /**< INTFL_IRQ_A Mask */
- #define MXC_F_TMR_REVB_INTFL_WRDONE_A_POS 8 /**< INTFL_WRDONE_A Position */
- #define MXC_F_TMR_REVB_INTFL_WRDONE_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_WRDONE_A_POS)) /**< INTFL_WRDONE_A Mask */
+#define MXC_F_TMR_REVB_INTFL_WRDONE_A_POS 8 /**< INTFL_WRDONE_A Position */
+#define MXC_F_TMR_REVB_INTFL_WRDONE_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_WRDONE_A_POS)) /**< INTFL_WRDONE_A Mask */
- #define MXC_F_TMR_REVB_INTFL_WR_DIS_A_POS 9 /**< INTFL_WR_DIS_A Position */
- #define MXC_F_TMR_REVB_INTFL_WR_DIS_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_WR_DIS_A_POS)) /**< INTFL_WR_DIS_A Mask */
+#define MXC_F_TMR_REVB_INTFL_WR_DIS_A_POS 9 /**< INTFL_WR_DIS_A Position */
+#define MXC_F_TMR_REVB_INTFL_WR_DIS_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_WR_DIS_A_POS)) /**< INTFL_WR_DIS_A Mask */
- #define MXC_F_TMR_REVB_INTFL_IRQ_B_POS 16 /**< INTFL_IRQ_B Position */
- #define MXC_F_TMR_REVB_INTFL_IRQ_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_IRQ_B_POS)) /**< INTFL_IRQ_B Mask */
+#define MXC_F_TMR_REVB_INTFL_IRQ_B_POS 16 /**< INTFL_IRQ_B Position */
+#define MXC_F_TMR_REVB_INTFL_IRQ_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_IRQ_B_POS)) /**< INTFL_IRQ_B Mask */
- #define MXC_F_TMR_REVB_INTFL_WRDONE_B_POS 24 /**< INTFL_WRDONE_B Position */
- #define MXC_F_TMR_REVB_INTFL_WRDONE_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_WRDONE_B_POS)) /**< INTFL_WRDONE_B Mask */
+#define MXC_F_TMR_REVB_INTFL_WRDONE_B_POS 24 /**< INTFL_WRDONE_B Position */
+#define MXC_F_TMR_REVB_INTFL_WRDONE_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_WRDONE_B_POS)) /**< INTFL_WRDONE_B Mask */
- #define MXC_F_TMR_REVB_INTFL_WR_DIS_B_POS 25 /**< INTFL_WR_DIS_B Position */
- #define MXC_F_TMR_REVB_INTFL_WR_DIS_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_WR_DIS_B_POS)) /**< INTFL_WR_DIS_B Mask */
+#define MXC_F_TMR_REVB_INTFL_WR_DIS_B_POS 25 /**< INTFL_WR_DIS_B Position */
+#define MXC_F_TMR_REVB_INTFL_WR_DIS_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_WR_DIS_B_POS)) /**< INTFL_WR_DIS_B Mask */
/**@} end of group TMR_REVB_INTFL_Register */
@@ -164,157 +153,157 @@ typedef struct {
* @brief Timer Control Register.
* @{
*/
- #define MXC_F_TMR_REVB_CTRL0_MODE_A_POS 0 /**< CTRL0_MODE_A Position */
- #define MXC_F_TMR_REVB_CTRL0_MODE_A ((uint32_t)(0xFUL << MXC_F_TMR_REVB_CTRL0_MODE_A_POS)) /**< CTRL0_MODE_A Mask */
- #define MXC_V_TMR_REVB_CTRL0_MODE_A_ONE_SHOT ((uint32_t)0x0UL) /**< CTRL0_MODE_A_ONE_SHOT Value */
- #define MXC_S_TMR_REVB_CTRL0_MODE_A_ONE_SHOT (MXC_V_TMR_REVB_CTRL0_MODE_A_ONE_SHOT << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_ONE_SHOT Setting */
- #define MXC_V_TMR_REVB_CTRL0_MODE_A_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL0_MODE_A_CONTINUOUS Value */
- #define MXC_S_TMR_REVB_CTRL0_MODE_A_CONTINUOUS (MXC_V_TMR_REVB_CTRL0_MODE_A_CONTINUOUS << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CONTINUOUS Setting */
- #define MXC_V_TMR_REVB_CTRL0_MODE_A_COUNTER ((uint32_t)0x2UL) /**< CTRL0_MODE_A_COUNTER Value */
- #define MXC_S_TMR_REVB_CTRL0_MODE_A_COUNTER (MXC_V_TMR_REVB_CTRL0_MODE_A_COUNTER << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COUNTER Setting */
- #define MXC_V_TMR_REVB_CTRL0_MODE_A_PWM ((uint32_t)0x3UL) /**< CTRL0_MODE_A_PWM Value */
- #define MXC_S_TMR_REVB_CTRL0_MODE_A_PWM (MXC_V_TMR_REVB_CTRL0_MODE_A_PWM << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_PWM Setting */
- #define MXC_V_TMR_REVB_CTRL0_MODE_A_CAPTURE ((uint32_t)0x4UL) /**< CTRL0_MODE_A_CAPTURE Value */
- #define MXC_S_TMR_REVB_CTRL0_MODE_A_CAPTURE (MXC_V_TMR_REVB_CTRL0_MODE_A_CAPTURE << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPTURE Setting */
- #define MXC_V_TMR_REVB_CTRL0_MODE_A_COMPARE ((uint32_t)0x5UL) /**< CTRL0_MODE_A_COMPARE Value */
- #define MXC_S_TMR_REVB_CTRL0_MODE_A_COMPARE (MXC_V_TMR_REVB_CTRL0_MODE_A_COMPARE << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COMPARE Setting */
- #define MXC_V_TMR_REVB_CTRL0_MODE_A_GATED ((uint32_t)0x6UL) /**< CTRL0_MODE_A_GATED Value */
- #define MXC_S_TMR_REVB_CTRL0_MODE_A_GATED (MXC_V_TMR_REVB_CTRL0_MODE_A_GATED << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_GATED Setting */
- #define MXC_V_TMR_REVB_CTRL0_MODE_A_CAPCOMP ((uint32_t)0x7UL) /**< CTRL0_MODE_A_CAPCOMP Value */
- #define MXC_S_TMR_REVB_CTRL0_MODE_A_CAPCOMP (MXC_V_TMR_REVB_CTRL0_MODE_A_CAPCOMP << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPCOMP Setting */
- #define MXC_V_TMR_REVB_CTRL0_MODE_A_DUAL_EDGE ((uint32_t)0x8UL) /**< CTRL0_MODE_A_DUAL_EDGE Value */
- #define MXC_S_TMR_REVB_CTRL0_MODE_A_DUAL_EDGE (MXC_V_TMR_REVB_CTRL0_MODE_A_DUAL_EDGE << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_DUAL_EDGE Setting */
- #define MXC_V_TMR_REVB_CTRL0_MODE_A_IGATED ((uint32_t)0xCUL) /**< CTRL0_MODE_A_IGATED Value */
- #define MXC_S_TMR_REVB_CTRL0_MODE_A_IGATED (MXC_V_TMR_REVB_CTRL0_MODE_A_IGATED << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_IGATED Setting */
-
- #define MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS 4 /**< CTRL0_CLKDIV_A Position */
- #define MXC_F_TMR_REVB_CTRL0_CLKDIV_A ((uint32_t)(0xFUL << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS)) /**< CTRL0_CLKDIV_A Mask */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1 ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_A_DIV_BY_1 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1 Setting */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2 ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_A_DIV_BY_2 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2 Setting */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4 ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_A_DIV_BY_4 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4 Setting */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_8 ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_A_DIV_BY_8 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_8 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_8 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_8 Setting */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_16 ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_A_DIV_BY_16 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_16 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_16 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_16 Setting */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_32 ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_A_DIV_BY_32 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_32 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_32 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_32 Setting */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_64 ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_A_DIV_BY_64 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_64 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_64 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_64 Setting */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_128 ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_A_DIV_BY_128 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_128 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_128 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_128 Setting */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_256 ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_A_DIV_BY_256 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_256 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_256 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_256 Setting */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_512 ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_A_DIV_BY_512 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_512 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_512 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_512 Setting */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1024 ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1024 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1024 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Setting */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2048 ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2048 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2048 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Setting */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4096 ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4096 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4096 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Setting */
-
- #define MXC_F_TMR_REVB_CTRL0_POL_A_POS 8 /**< CTRL0_POL_A Position */
- #define MXC_F_TMR_REVB_CTRL0_POL_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_POL_A_POS)) /**< CTRL0_POL_A Mask */
-
- #define MXC_F_TMR_REVB_CTRL0_PWMSYNC_A_POS 9 /**< CTRL0_PWMSYNC_A Position */
- #define MXC_F_TMR_REVB_CTRL0_PWMSYNC_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_PWMSYNC_A_POS)) /**< CTRL0_PWMSYNC_A Mask */
-
- #define MXC_F_TMR_REVB_CTRL0_NOLHPOL_A_POS 10 /**< CTRL0_NOLHPOL_A Position */
- #define MXC_F_TMR_REVB_CTRL0_NOLHPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_NOLHPOL_A_POS)) /**< CTRL0_NOLHPOL_A Mask */
-
- #define MXC_F_TMR_REVB_CTRL0_NOLLPOL_A_POS 11 /**< CTRL0_NOLLPOL_A Position */
- #define MXC_F_TMR_REVB_CTRL0_NOLLPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_NOLLPOL_A_POS)) /**< CTRL0_NOLLPOL_A Mask */
-
- #define MXC_F_TMR_REVB_CTRL0_PWMCKBD_A_POS 12 /**< CTRL0_PWMCKBD_A Position */
- #define MXC_F_TMR_REVB_CTRL0_PWMCKBD_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_PWMCKBD_A_POS)) /**< CTRL0_PWMCKBD_A Mask */
-
- #define MXC_F_TMR_REVB_CTRL0_RST_A_POS 13 /**< CTRL0_RST_A Position */
- #define MXC_F_TMR_REVB_CTRL0_RST_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_RST_A_POS)) /**< CTRL0_RST_A Mask */
-
- #define MXC_F_TMR_REVB_CTRL0_CLKEN_A_POS 14 /**< CTRL0_CLKEN_A Position */
- #define MXC_F_TMR_REVB_CTRL0_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_CLKEN_A_POS)) /**< CTRL0_CLKEN_A Mask */
-
- #define MXC_F_TMR_REVB_CTRL0_EN_A_POS 15 /**< CTRL0_EN_A Position */
- #define MXC_F_TMR_REVB_CTRL0_EN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_EN_A_POS)) /**< CTRL0_EN_A Mask */
-
- #define MXC_F_TMR_REVB_CTRL0_MODE_B_POS 16 /**< CTRL0_MODE_B Position */
- #define MXC_F_TMR_REVB_CTRL0_MODE_B ((uint32_t)(0xFUL << MXC_F_TMR_REVB_CTRL0_MODE_B_POS)) /**< CTRL0_MODE_B Mask */
- #define MXC_V_TMR_REVB_CTRL0_MODE_B_ONE_SHOT ((uint32_t)0x0UL) /**< CTRL0_MODE_B_ONE_SHOT Value */
- #define MXC_S_TMR_REVB_CTRL0_MODE_B_ONE_SHOT (MXC_V_TMR_REVB_CTRL0_MODE_B_ONE_SHOT << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_ONE_SHOT Setting */
- #define MXC_V_TMR_REVB_CTRL0_MODE_B_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL0_MODE_B_CONTINUOUS Value */
- #define MXC_S_TMR_REVB_CTRL0_MODE_B_CONTINUOUS (MXC_V_TMR_REVB_CTRL0_MODE_B_CONTINUOUS << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CONTINUOUS Setting */
- #define MXC_V_TMR_REVB_CTRL0_MODE_B_COUNTER ((uint32_t)0x2UL) /**< CTRL0_MODE_B_COUNTER Value */
- #define MXC_S_TMR_REVB_CTRL0_MODE_B_COUNTER (MXC_V_TMR_REVB_CTRL0_MODE_B_COUNTER << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COUNTER Setting */
- #define MXC_V_TMR_REVB_CTRL0_MODE_B_PWM ((uint32_t)0x3UL) /**< CTRL0_MODE_B_PWM Value */
- #define MXC_S_TMR_REVB_CTRL0_MODE_B_PWM (MXC_V_TMR_REVB_CTRL0_MODE_B_PWM << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_PWM Setting */
- #define MXC_V_TMR_REVB_CTRL0_MODE_B_CAPTURE ((uint32_t)0x4UL) /**< CTRL0_MODE_B_CAPTURE Value */
- #define MXC_S_TMR_REVB_CTRL0_MODE_B_CAPTURE (MXC_V_TMR_REVB_CTRL0_MODE_B_CAPTURE << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPTURE Setting */
- #define MXC_V_TMR_REVB_CTRL0_MODE_B_COMPARE ((uint32_t)0x5UL) /**< CTRL0_MODE_B_COMPARE Value */
- #define MXC_S_TMR_REVB_CTRL0_MODE_B_COMPARE (MXC_V_TMR_REVB_CTRL0_MODE_B_COMPARE << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COMPARE Setting */
- #define MXC_V_TMR_REVB_CTRL0_MODE_B_GATED ((uint32_t)0x6UL) /**< CTRL0_MODE_B_GATED Value */
- #define MXC_S_TMR_REVB_CTRL0_MODE_B_GATED (MXC_V_TMR_REVB_CTRL0_MODE_B_GATED << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_GATED Setting */
- #define MXC_V_TMR_REVB_CTRL0_MODE_B_CAPCOMP ((uint32_t)0x7UL) /**< CTRL0_MODE_B_CAPCOMP Value */
- #define MXC_S_TMR_REVB_CTRL0_MODE_B_CAPCOMP (MXC_V_TMR_REVB_CTRL0_MODE_B_CAPCOMP << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPCOMP Setting */
- #define MXC_V_TMR_REVB_CTRL0_MODE_B_DUAL_EDGE ((uint32_t)0x8UL) /**< CTRL0_MODE_B_DUAL_EDGE Value */
- #define MXC_S_TMR_REVB_CTRL0_MODE_B_DUAL_EDGE (MXC_V_TMR_REVB_CTRL0_MODE_B_DUAL_EDGE << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_DUAL_EDGE Setting */
- #define MXC_V_TMR_REVB_CTRL0_MODE_B_IGATED ((uint32_t)0xEUL) /**< CTRL0_MODE_B_IGATED Value */
- #define MXC_S_TMR_REVB_CTRL0_MODE_B_IGATED (MXC_V_TMR_REVB_CTRL0_MODE_B_IGATED << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_IGATED Setting */
-
- #define MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS 20 /**< CTRL0_CLKDIV_B Position */
- #define MXC_F_TMR_REVB_CTRL0_CLKDIV_B ((uint32_t)(0xFUL << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS)) /**< CTRL0_CLKDIV_B Mask */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1 ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_B_DIV_BY_1 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1 Setting */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2 ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_B_DIV_BY_2 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2 Setting */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4 ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_B_DIV_BY_4 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4 Setting */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_8 ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_B_DIV_BY_8 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_8 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_8 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_8 Setting */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_16 ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_B_DIV_BY_16 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_16 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_16 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_16 Setting */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_32 ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_B_DIV_BY_32 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_32 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_32 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_32 Setting */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_64 ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_B_DIV_BY_64 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_64 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_64 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_64 Setting */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_128 ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_B_DIV_BY_128 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_128 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_128 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_128 Setting */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_256 ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_B_DIV_BY_256 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_256 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_256 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_256 Setting */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_512 ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_B_DIV_BY_512 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_512 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_512 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_512 Setting */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1024 ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1024 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1024 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Setting */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2048 ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2048 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2048 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Setting */
- #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4096 ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Value */
- #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4096 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4096 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Setting */
-
- #define MXC_F_TMR_REVB_CTRL0_POL_B_POS 24 /**< CTRL0_POL_B Position */
- #define MXC_F_TMR_REVB_CTRL0_POL_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_POL_B_POS)) /**< CTRL0_POL_B Mask */
-
- #define MXC_F_TMR_REVB_CTRL0_PWMSYNC_B_POS 25 /**< CTRL0_PWMSYNC_B Position */
- #define MXC_F_TMR_REVB_CTRL0_PWMSYNC_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_PWMSYNC_B_POS)) /**< CTRL0_PWMSYNC_B Mask */
-
- #define MXC_F_TMR_REVB_CTRL0_NOLHPOL_B_POS 26 /**< CTRL0_NOLHPOL_B Position */
- #define MXC_F_TMR_REVB_CTRL0_NOLHPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_NOLHPOL_B_POS)) /**< CTRL0_NOLHPOL_B Mask */
-
- #define MXC_F_TMR_REVB_CTRL0_NOLLPOL_B_POS 27 /**< CTRL0_NOLLPOL_B Position */
- #define MXC_F_TMR_REVB_CTRL0_NOLLPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_NOLLPOL_B_POS)) /**< CTRL0_NOLLPOL_B Mask */
-
- #define MXC_F_TMR_REVB_CTRL0_PWMCKBD_B_POS 28 /**< CTRL0_PWMCKBD_B Position */
- #define MXC_F_TMR_REVB_CTRL0_PWMCKBD_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_PWMCKBD_B_POS)) /**< CTRL0_PWMCKBD_B Mask */
-
- #define MXC_F_TMR_REVB_CTRL0_RST_B_POS 29 /**< CTRL0_RST_B Position */
- #define MXC_F_TMR_REVB_CTRL0_RST_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_RST_B_POS)) /**< CTRL0_RST_B Mask */
-
- #define MXC_F_TMR_REVB_CTRL0_CLKEN_B_POS 30 /**< CTRL0_CLKEN_B Position */
- #define MXC_F_TMR_REVB_CTRL0_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_CLKEN_B_POS)) /**< CTRL0_CLKEN_B Mask */
-
- #define MXC_F_TMR_REVB_CTRL0_EN_B_POS 31 /**< CTRL0_EN_B Position */
- #define MXC_F_TMR_REVB_CTRL0_EN_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_EN_B_POS)) /**< CTRL0_EN_B Mask */
+#define MXC_F_TMR_REVB_CTRL0_MODE_A_POS 0 /**< CTRL0_MODE_A Position */
+#define MXC_F_TMR_REVB_CTRL0_MODE_A ((uint32_t)(0xFUL << MXC_F_TMR_REVB_CTRL0_MODE_A_POS)) /**< CTRL0_MODE_A Mask */
+#define MXC_V_TMR_REVB_CTRL0_MODE_A_ONE_SHOT ((uint32_t)0x0UL) /**< CTRL0_MODE_A_ONE_SHOT Value */
+#define MXC_S_TMR_REVB_CTRL0_MODE_A_ONE_SHOT (MXC_V_TMR_REVB_CTRL0_MODE_A_ONE_SHOT << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_ONE_SHOT Setting */
+#define MXC_V_TMR_REVB_CTRL0_MODE_A_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL0_MODE_A_CONTINUOUS Value */
+#define MXC_S_TMR_REVB_CTRL0_MODE_A_CONTINUOUS (MXC_V_TMR_REVB_CTRL0_MODE_A_CONTINUOUS << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CONTINUOUS Setting */
+#define MXC_V_TMR_REVB_CTRL0_MODE_A_COUNTER ((uint32_t)0x2UL) /**< CTRL0_MODE_A_COUNTER Value */
+#define MXC_S_TMR_REVB_CTRL0_MODE_A_COUNTER (MXC_V_TMR_REVB_CTRL0_MODE_A_COUNTER << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COUNTER Setting */
+#define MXC_V_TMR_REVB_CTRL0_MODE_A_PWM ((uint32_t)0x3UL) /**< CTRL0_MODE_A_PWM Value */
+#define MXC_S_TMR_REVB_CTRL0_MODE_A_PWM (MXC_V_TMR_REVB_CTRL0_MODE_A_PWM << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_PWM Setting */
+#define MXC_V_TMR_REVB_CTRL0_MODE_A_CAPTURE ((uint32_t)0x4UL) /**< CTRL0_MODE_A_CAPTURE Value */
+#define MXC_S_TMR_REVB_CTRL0_MODE_A_CAPTURE (MXC_V_TMR_REVB_CTRL0_MODE_A_CAPTURE << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPTURE Setting */
+#define MXC_V_TMR_REVB_CTRL0_MODE_A_COMPARE ((uint32_t)0x5UL) /**< CTRL0_MODE_A_COMPARE Value */
+#define MXC_S_TMR_REVB_CTRL0_MODE_A_COMPARE (MXC_V_TMR_REVB_CTRL0_MODE_A_COMPARE << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COMPARE Setting */
+#define MXC_V_TMR_REVB_CTRL0_MODE_A_GATED ((uint32_t)0x6UL) /**< CTRL0_MODE_A_GATED Value */
+#define MXC_S_TMR_REVB_CTRL0_MODE_A_GATED (MXC_V_TMR_REVB_CTRL0_MODE_A_GATED << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_GATED Setting */
+#define MXC_V_TMR_REVB_CTRL0_MODE_A_CAPCOMP ((uint32_t)0x7UL) /**< CTRL0_MODE_A_CAPCOMP Value */
+#define MXC_S_TMR_REVB_CTRL0_MODE_A_CAPCOMP (MXC_V_TMR_REVB_CTRL0_MODE_A_CAPCOMP << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPCOMP Setting */
+#define MXC_V_TMR_REVB_CTRL0_MODE_A_DUAL_EDGE ((uint32_t)0x8UL) /**< CTRL0_MODE_A_DUAL_EDGE Value */
+#define MXC_S_TMR_REVB_CTRL0_MODE_A_DUAL_EDGE (MXC_V_TMR_REVB_CTRL0_MODE_A_DUAL_EDGE << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_DUAL_EDGE Setting */
+#define MXC_V_TMR_REVB_CTRL0_MODE_A_IGATED ((uint32_t)0xEUL) /**< CTRL0_MODE_A_IGATED Value */
+#define MXC_S_TMR_REVB_CTRL0_MODE_A_IGATED (MXC_V_TMR_REVB_CTRL0_MODE_A_IGATED << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_IGATED Setting */
+
+#define MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS 4 /**< CTRL0_CLKDIV_A Position */
+#define MXC_F_TMR_REVB_CTRL0_CLKDIV_A ((uint32_t)(0xFUL << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS)) /**< CTRL0_CLKDIV_A Mask */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1 ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_A_DIV_BY_1 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1 Setting */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2 ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_A_DIV_BY_2 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2 Setting */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4 ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_A_DIV_BY_4 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4 Setting */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_8 ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_A_DIV_BY_8 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_8 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_8 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_8 Setting */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_16 ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_A_DIV_BY_16 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_16 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_16 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_16 Setting */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_32 ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_A_DIV_BY_32 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_32 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_32 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_32 Setting */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_64 ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_A_DIV_BY_64 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_64 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_64 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_64 Setting */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_128 ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_A_DIV_BY_128 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_128 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_128 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_128 Setting */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_256 ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_A_DIV_BY_256 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_256 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_256 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_256 Setting */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_512 ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_A_DIV_BY_512 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_512 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_512 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_512 Setting */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1024 ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1024 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1024 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Setting */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2048 ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2048 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2048 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Setting */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4096 ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4096 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4096 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Setting */
+
+#define MXC_F_TMR_REVB_CTRL0_POL_A_POS 8 /**< CTRL0_POL_A Position */
+#define MXC_F_TMR_REVB_CTRL0_POL_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_POL_A_POS)) /**< CTRL0_POL_A Mask */
+
+#define MXC_F_TMR_REVB_CTRL0_PWMSYNC_A_POS 9 /**< CTRL0_PWMSYNC_A Position */
+#define MXC_F_TMR_REVB_CTRL0_PWMSYNC_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_PWMSYNC_A_POS)) /**< CTRL0_PWMSYNC_A Mask */
+
+#define MXC_F_TMR_REVB_CTRL0_NOLHPOL_A_POS 10 /**< CTRL0_NOLHPOL_A Position */
+#define MXC_F_TMR_REVB_CTRL0_NOLHPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_NOLHPOL_A_POS)) /**< CTRL0_NOLHPOL_A Mask */
+
+#define MXC_F_TMR_REVB_CTRL0_NOLLPOL_A_POS 11 /**< CTRL0_NOLLPOL_A Position */
+#define MXC_F_TMR_REVB_CTRL0_NOLLPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_NOLLPOL_A_POS)) /**< CTRL0_NOLLPOL_A Mask */
+
+#define MXC_F_TMR_REVB_CTRL0_PWMCKBD_A_POS 12 /**< CTRL0_PWMCKBD_A Position */
+#define MXC_F_TMR_REVB_CTRL0_PWMCKBD_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_PWMCKBD_A_POS)) /**< CTRL0_PWMCKBD_A Mask */
+
+#define MXC_F_TMR_REVB_CTRL0_RST_A_POS 13 /**< CTRL0_RST_A Position */
+#define MXC_F_TMR_REVB_CTRL0_RST_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_RST_A_POS)) /**< CTRL0_RST_A Mask */
+
+#define MXC_F_TMR_REVB_CTRL0_CLKEN_A_POS 14 /**< CTRL0_CLKEN_A Position */
+#define MXC_F_TMR_REVB_CTRL0_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_CLKEN_A_POS)) /**< CTRL0_CLKEN_A Mask */
+
+#define MXC_F_TMR_REVB_CTRL0_EN_A_POS 15 /**< CTRL0_EN_A Position */
+#define MXC_F_TMR_REVB_CTRL0_EN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_EN_A_POS)) /**< CTRL0_EN_A Mask */
+
+#define MXC_F_TMR_REVB_CTRL0_MODE_B_POS 16 /**< CTRL0_MODE_B Position */
+#define MXC_F_TMR_REVB_CTRL0_MODE_B ((uint32_t)(0xFUL << MXC_F_TMR_REVB_CTRL0_MODE_B_POS)) /**< CTRL0_MODE_B Mask */
+#define MXC_V_TMR_REVB_CTRL0_MODE_B_ONE_SHOT ((uint32_t)0x0UL) /**< CTRL0_MODE_B_ONE_SHOT Value */
+#define MXC_S_TMR_REVB_CTRL0_MODE_B_ONE_SHOT (MXC_V_TMR_REVB_CTRL0_MODE_B_ONE_SHOT << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_ONE_SHOT Setting */
+#define MXC_V_TMR_REVB_CTRL0_MODE_B_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL0_MODE_B_CONTINUOUS Value */
+#define MXC_S_TMR_REVB_CTRL0_MODE_B_CONTINUOUS (MXC_V_TMR_REVB_CTRL0_MODE_B_CONTINUOUS << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CONTINUOUS Setting */
+#define MXC_V_TMR_REVB_CTRL0_MODE_B_COUNTER ((uint32_t)0x2UL) /**< CTRL0_MODE_B_COUNTER Value */
+#define MXC_S_TMR_REVB_CTRL0_MODE_B_COUNTER (MXC_V_TMR_REVB_CTRL0_MODE_B_COUNTER << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COUNTER Setting */
+#define MXC_V_TMR_REVB_CTRL0_MODE_B_PWM ((uint32_t)0x3UL) /**< CTRL0_MODE_B_PWM Value */
+#define MXC_S_TMR_REVB_CTRL0_MODE_B_PWM (MXC_V_TMR_REVB_CTRL0_MODE_B_PWM << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_PWM Setting */
+#define MXC_V_TMR_REVB_CTRL0_MODE_B_CAPTURE ((uint32_t)0x4UL) /**< CTRL0_MODE_B_CAPTURE Value */
+#define MXC_S_TMR_REVB_CTRL0_MODE_B_CAPTURE (MXC_V_TMR_REVB_CTRL0_MODE_B_CAPTURE << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPTURE Setting */
+#define MXC_V_TMR_REVB_CTRL0_MODE_B_COMPARE ((uint32_t)0x5UL) /**< CTRL0_MODE_B_COMPARE Value */
+#define MXC_S_TMR_REVB_CTRL0_MODE_B_COMPARE (MXC_V_TMR_REVB_CTRL0_MODE_B_COMPARE << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COMPARE Setting */
+#define MXC_V_TMR_REVB_CTRL0_MODE_B_GATED ((uint32_t)0x6UL) /**< CTRL0_MODE_B_GATED Value */
+#define MXC_S_TMR_REVB_CTRL0_MODE_B_GATED (MXC_V_TMR_REVB_CTRL0_MODE_B_GATED << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_GATED Setting */
+#define MXC_V_TMR_REVB_CTRL0_MODE_B_CAPCOMP ((uint32_t)0x7UL) /**< CTRL0_MODE_B_CAPCOMP Value */
+#define MXC_S_TMR_REVB_CTRL0_MODE_B_CAPCOMP (MXC_V_TMR_REVB_CTRL0_MODE_B_CAPCOMP << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPCOMP Setting */
+#define MXC_V_TMR_REVB_CTRL0_MODE_B_DUAL_EDGE ((uint32_t)0x8UL) /**< CTRL0_MODE_B_DUAL_EDGE Value */
+#define MXC_S_TMR_REVB_CTRL0_MODE_B_DUAL_EDGE (MXC_V_TMR_REVB_CTRL0_MODE_B_DUAL_EDGE << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_DUAL_EDGE Setting */
+#define MXC_V_TMR_REVB_CTRL0_MODE_B_IGATED ((uint32_t)0xEUL) /**< CTRL0_MODE_B_IGATED Value */
+#define MXC_S_TMR_REVB_CTRL0_MODE_B_IGATED (MXC_V_TMR_REVB_CTRL0_MODE_B_IGATED << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_IGATED Setting */
+
+#define MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS 20 /**< CTRL0_CLKDIV_B Position */
+#define MXC_F_TMR_REVB_CTRL0_CLKDIV_B ((uint32_t)(0xFUL << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS)) /**< CTRL0_CLKDIV_B Mask */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1 ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_B_DIV_BY_1 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1 Setting */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2 ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_B_DIV_BY_2 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2 Setting */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4 ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_B_DIV_BY_4 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4 Setting */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_8 ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_B_DIV_BY_8 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_8 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_8 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_8 Setting */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_16 ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_B_DIV_BY_16 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_16 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_16 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_16 Setting */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_32 ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_B_DIV_BY_32 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_32 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_32 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_32 Setting */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_64 ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_B_DIV_BY_64 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_64 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_64 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_64 Setting */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_128 ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_B_DIV_BY_128 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_128 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_128 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_128 Setting */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_256 ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_B_DIV_BY_256 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_256 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_256 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_256 Setting */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_512 ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_B_DIV_BY_512 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_512 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_512 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_512 Setting */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1024 ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1024 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1024 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Setting */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2048 ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2048 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2048 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Setting */
+#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4096 ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Value */
+#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4096 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4096 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Setting */
+
+#define MXC_F_TMR_REVB_CTRL0_POL_B_POS 24 /**< CTRL0_POL_B Position */
+#define MXC_F_TMR_REVB_CTRL0_POL_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_POL_B_POS)) /**< CTRL0_POL_B Mask */
+
+#define MXC_F_TMR_REVB_CTRL0_PWMSYNC_B_POS 25 /**< CTRL0_PWMSYNC_B Position */
+#define MXC_F_TMR_REVB_CTRL0_PWMSYNC_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_PWMSYNC_B_POS)) /**< CTRL0_PWMSYNC_B Mask */
+
+#define MXC_F_TMR_REVB_CTRL0_NOLHPOL_B_POS 26 /**< CTRL0_NOLHPOL_B Position */
+#define MXC_F_TMR_REVB_CTRL0_NOLHPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_NOLHPOL_B_POS)) /**< CTRL0_NOLHPOL_B Mask */
+
+#define MXC_F_TMR_REVB_CTRL0_NOLLPOL_B_POS 27 /**< CTRL0_NOLLPOL_B Position */
+#define MXC_F_TMR_REVB_CTRL0_NOLLPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_NOLLPOL_B_POS)) /**< CTRL0_NOLLPOL_B Mask */
+
+#define MXC_F_TMR_REVB_CTRL0_PWMCKBD_B_POS 28 /**< CTRL0_PWMCKBD_B Position */
+#define MXC_F_TMR_REVB_CTRL0_PWMCKBD_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_PWMCKBD_B_POS)) /**< CTRL0_PWMCKBD_B Mask */
+
+#define MXC_F_TMR_REVB_CTRL0_RST_B_POS 29 /**< CTRL0_RST_B Position */
+#define MXC_F_TMR_REVB_CTRL0_RST_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_RST_B_POS)) /**< CTRL0_RST_B Mask */
+
+#define MXC_F_TMR_REVB_CTRL0_CLKEN_B_POS 30 /**< CTRL0_CLKEN_B Position */
+#define MXC_F_TMR_REVB_CTRL0_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_CLKEN_B_POS)) /**< CTRL0_CLKEN_B Mask */
+
+#define MXC_F_TMR_REVB_CTRL0_EN_B_POS 31 /**< CTRL0_EN_B Position */
+#define MXC_F_TMR_REVB_CTRL0_EN_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_EN_B_POS)) /**< CTRL0_EN_B Mask */
/**@} end of group TMR_REVB_CTRL0_Register */
@@ -324,17 +313,17 @@ typedef struct {
* @brief Timer Non-Overlapping Compare Register.
* @{
*/
- #define MXC_F_TMR_REVB_NOLCMP_LO_A_POS 0 /**< NOLCMP_LO_A Position */
- #define MXC_F_TMR_REVB_NOLCMP_LO_A ((uint32_t)(0xFFUL << MXC_F_TMR_REVB_NOLCMP_LO_A_POS)) /**< NOLCMP_LO_A Mask */
+#define MXC_F_TMR_REVB_NOLCMP_LO_A_POS 0 /**< NOLCMP_LO_A Position */
+#define MXC_F_TMR_REVB_NOLCMP_LO_A ((uint32_t)(0xFFUL << MXC_F_TMR_REVB_NOLCMP_LO_A_POS)) /**< NOLCMP_LO_A Mask */
- #define MXC_F_TMR_REVB_NOLCMP_HI_A_POS 8 /**< NOLCMP_HI_A Position */
- #define MXC_F_TMR_REVB_NOLCMP_HI_A ((uint32_t)(0xFFUL << MXC_F_TMR_REVB_NOLCMP_HI_A_POS)) /**< NOLCMP_HI_A Mask */
+#define MXC_F_TMR_REVB_NOLCMP_HI_A_POS 8 /**< NOLCMP_HI_A Position */
+#define MXC_F_TMR_REVB_NOLCMP_HI_A ((uint32_t)(0xFFUL << MXC_F_TMR_REVB_NOLCMP_HI_A_POS)) /**< NOLCMP_HI_A Mask */
- #define MXC_F_TMR_REVB_NOLCMP_LO_B_POS 16 /**< NOLCMP_LO_B Position */
- #define MXC_F_TMR_REVB_NOLCMP_LO_B ((uint32_t)(0xFFUL << MXC_F_TMR_REVB_NOLCMP_LO_B_POS)) /**< NOLCMP_LO_B Mask */
+#define MXC_F_TMR_REVB_NOLCMP_LO_B_POS 16 /**< NOLCMP_LO_B Position */
+#define MXC_F_TMR_REVB_NOLCMP_LO_B ((uint32_t)(0xFFUL << MXC_F_TMR_REVB_NOLCMP_LO_B_POS)) /**< NOLCMP_LO_B Mask */
- #define MXC_F_TMR_REVB_NOLCMP_HI_B_POS 24 /**< NOLCMP_HI_B Position */
- #define MXC_F_TMR_REVB_NOLCMP_HI_B ((uint32_t)(0xFFUL << MXC_F_TMR_REVB_NOLCMP_HI_B_POS)) /**< NOLCMP_HI_B Mask */
+#define MXC_F_TMR_REVB_NOLCMP_HI_B_POS 24 /**< NOLCMP_HI_B Position */
+#define MXC_F_TMR_REVB_NOLCMP_HI_B ((uint32_t)(0xFFUL << MXC_F_TMR_REVB_NOLCMP_HI_B_POS)) /**< NOLCMP_HI_B Mask */
/**@} end of group TMR_REVB_NOLCMP_Register */
@@ -344,68 +333,71 @@ typedef struct {
* @brief Timer Configuration Register.
* @{
*/
- #define MXC_F_TMR_REVB_CTRL1_CLKSEL_A_POS 0 /**< CTRL1_CLKSEL_A Position */
- #define MXC_F_TMR_REVB_CTRL1_CLKSEL_A ((uint32_t)(0x3UL << MXC_F_TMR_REVB_CTRL1_CLKSEL_A_POS)) /**< CTRL1_CLKSEL_A Mask */
+#define MXC_F_TMR_REVB_CTRL1_CLKSEL_A_POS 0 /**< CTRL1_CLKSEL_A Position */
+#define MXC_F_TMR_REVB_CTRL1_CLKSEL_A ((uint32_t)(0x3UL << MXC_F_TMR_REVB_CTRL1_CLKSEL_A_POS)) /**< CTRL1_CLKSEL_A Mask */
+
+#define MXC_F_TMR_REVB_CTRL1_CLKEN_A_POS 2 /**< CTRL1_CLKEN_A Position */
+#define MXC_F_TMR_REVB_CTRL1_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CLKEN_A_POS)) /**< CTRL1_CLKEN_A Mask */
- #define MXC_F_TMR_REVB_CTRL1_CLKEN_A_POS 2 /**< CTRL1_CLKEN_A Position */
- #define MXC_F_TMR_REVB_CTRL1_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CLKEN_A_POS)) /**< CTRL1_CLKEN_A Mask */
+#define MXC_F_TMR_REVB_CTRL1_CLKRDY_A_POS 3 /**< CTRL1_CLKRDY_A Position */
+#define MXC_F_TMR_REVB_CTRL1_CLKRDY_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CLKRDY_A_POS)) /**< CTRL1_CLKRDY_A Mask */
- #define MXC_F_TMR_REVB_CTRL1_CLKRDY_A_POS 3 /**< CTRL1_CLKRDY_A Position */
- #define MXC_F_TMR_REVB_CTRL1_CLKRDY_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CLKRDY_A_POS)) /**< CTRL1_CLKRDY_A Mask */
+#define MXC_F_TMR_REVB_CTRL1_EVENT_SEL_A_POS 4 /**< CTRL1_EVENT_SEL_A Position */
+#define MXC_F_TMR_REVB_CTRL1_EVENT_SEL_A ((uint32_t)(0x7UL << MXC_F_TMR_REVB_CTRL1_EVENT_SEL_A_POS)) /**< CTRL1_EVENT_SEL_A Mask */
- #define MXC_F_TMR_REVB_CTRL1_EVENT_SEL_A_POS 4 /**< CTRL1_EVENT_SEL_A Position */
- #define MXC_F_TMR_REVB_CTRL1_EVENT_SEL_A ((uint32_t)(0x7UL << MXC_F_TMR_REVB_CTRL1_EVENT_SEL_A_POS)) /**< CTRL1_EVENT_SEL_A Mask */
+#define MXC_F_TMR_REVB_CTRL1_NEGTRIG_A_POS 7 /**< CTRL1_NEGTRIG_A Position */
+#define MXC_F_TMR_REVB_CTRL1_NEGTRIG_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_NEGTRIG_A_POS)) /**< CTRL1_NEGTRIG_A Mask */
- #define MXC_F_TMR_REVB_CTRL1_NEGTRIG_A_POS 7 /**< CTRL1_NEGTRIG_A Position */
- #define MXC_F_TMR_REVB_CTRL1_NEGTRIG_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_NEGTRIG_A_POS)) /**< CTRL1_NEGTRIG_A Mask */
+#define MXC_F_TMR_REVB_CTRL1_IE_A_POS 8 /**< CTRL1_IE_A Position */
+#define MXC_F_TMR_REVB_CTRL1_IE_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_IE_A_POS)) /**< CTRL1_IE_A Mask */
- #define MXC_F_TMR_REVB_CTRL1_IE_A_POS 8 /**< CTRL1_IE_A Position */
- #define MXC_F_TMR_REVB_CTRL1_IE_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_IE_A_POS)) /**< CTRL1_IE_A Mask */
+#define MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_A_POS 9 /**< CTRL1_CAPEVENT_SEL_A Position */
+#define MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_A ((uint32_t)(0x3UL << MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_A_POS)) /**< CTRL1_CAPEVENT_SEL_A Mask */
- #define MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_A_POS 9 /**< CTRL1_CAPEVENT_SEL_A Position */
- #define MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_A ((uint32_t)(0x3UL << MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_A_POS)) /**< CTRL1_CAPEVENT_SEL_A Mask */
+#define MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_A_POS 11 /**< CTRL1_SW_CAPEVENT_A Position */
+#define MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_A_POS)) /**< CTRL1_SW_CAPEVENT_A Mask */
- #define MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_A_POS 11 /**< CTRL1_SW_CAPEVENT_A Position */
- #define MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_A_POS)) /**< CTRL1_SW_CAPEVENT_A Mask */
+#define MXC_F_TMR_REVB_CTRL1_WE_A_POS 12 /**< CTRL1_WE_A Position */
+#define MXC_F_TMR_REVB_CTRL1_WE_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_WE_A_POS)) /**< CTRL1_WE_A Mask */
- #define MXC_F_TMR_REVB_CTRL1_WE_A_POS 12 /**< CTRL1_WE_A Position */
- #define MXC_F_TMR_REVB_CTRL1_WE_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_WE_A_POS)) /**< CTRL1_WE_A Mask */
+#define MXC_F_TMR_REVB_CTRL1_OUTEN_A_POS 13 /**< CTRL1_OUTEN_A Position */
+#define MXC_F_TMR_REVB_CTRL1_OUTEN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_OUTEN_A_POS)) /**< CTRL1_OUTEN_A Mask */
- #define MXC_F_TMR_REVB_CTRL1_OUTEN_A_POS 13 /**< CTRL1_OUTEN_A Position */
- #define MXC_F_TMR_REVB_CTRL1_OUTEN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_OUTEN_A_POS)) /**< CTRL1_OUTEN_A Mask */
+#define MXC_F_TMR_REVB_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */
+#define MXC_F_TMR_REVB_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */
- #define MXC_F_TMR_REVB_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */
- #define MXC_F_TMR_REVB_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */
+#define MXC_F_TMR_REVB_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */
+#define MXC_F_TMR_REVB_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */
- #define MXC_F_TMR_REVB_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */
- #define MXC_F_TMR_REVB_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_REVB_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */
+#define MXC_F_TMR_REVB_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */
+#define MXC_F_TMR_REVB_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_REVB_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */
- #define MXC_F_TMR_REVB_CTRL1_CLKEN_B_POS 18 /**< CTRL1_CLKEN_B Position */
- #define MXC_F_TMR_REVB_CTRL1_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CLKEN_B_POS)) /**< CTRL1_CLKEN_B Mask */
+#define MXC_F_TMR_REVB_CTRL1_CLKEN_B_POS 18 /**< CTRL1_CLKEN_B Position */
+#define MXC_F_TMR_REVB_CTRL1_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CLKEN_B_POS)) /**< CTRL1_CLKEN_B Mask */
- #define MXC_F_TMR_REVB_CTRL1_CLKRDY_B_POS 19 /**< CTRL1_CLKRDY_B Position */
- #define MXC_F_TMR_REVB_CTRL1_CLKRDY_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CLKRDY_B_POS)) /**< CTRL1_CLKRDY_B Mask */
+#define MXC_F_TMR_REVB_CTRL1_CLKRDY_B_POS 19 /**< CTRL1_CLKRDY_B Position */
+#define MXC_F_TMR_REVB_CTRL1_CLKRDY_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CLKRDY_B_POS)) /**< CTRL1_CLKRDY_B Mask */
- #define MXC_F_TMR_REVB_CTRL1_EVENT_SEL_B_POS 20 /**< CTRL1_EVENT_SEL_B Position */
- #define MXC_F_TMR_REVB_CTRL1_EVENT_SEL_B ((uint32_t)(0x7UL << MXC_F_TMR_REVB_CTRL1_EVENT_SEL_B_POS)) /**< CTRL1_EVENT_SEL_B Mask */
+#define MXC_F_TMR_REVB_CTRL1_EVENT_SEL_B_POS 20 /**< CTRL1_EVENT_SEL_B Position */
+#define MXC_F_TMR_REVB_CTRL1_EVENT_SEL_B ((uint32_t)(0x7UL << MXC_F_TMR_REVB_CTRL1_EVENT_SEL_B_POS)) /**< CTRL1_EVENT_SEL_B Mask */
- #define MXC_F_TMR_REVB_CTRL1_NEGTRIG_B_POS 23 /**< CTRL1_NEGTRIG_B Position */
- #define MXC_F_TMR_REVB_CTRL1_NEGTRIG_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_NEGTRIG_B_POS)) /**< CTRL1_NEGTRIG_B Mask */
+#define MXC_F_TMR_REVB_CTRL1_NEGTRIG_B_POS 23 /**< CTRL1_NEGTRIG_B Position */
+#define MXC_F_TMR_REVB_CTRL1_NEGTRIG_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_NEGTRIG_B_POS)) /**< CTRL1_NEGTRIG_B Mask */
- #define MXC_F_TMR_REVB_CTRL1_IE_B_POS 24 /**< CTRL1_IE_B Position */
- #define MXC_F_TMR_REVB_CTRL1_IE_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_IE_B_POS)) /**< CTRL1_IE_B Mask */
+#define MXC_F_TMR_REVB_CTRL1_IE_B_POS 24 /**< CTRL1_IE_B Position */
+#define MXC_F_TMR_REVB_CTRL1_IE_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_IE_B_POS)) /**< CTRL1_IE_B Mask */
- #define MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_B_POS 25 /**< CTRL1_CAPEVENT_SEL_B Position */
- #define MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_B ((uint32_t)(0x3UL << MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_B_POS)) /**< CTRL1_CAPEVENT_SEL_B Mask */
+#define MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_B_POS 25 /**< CTRL1_CAPEVENT_SEL_B Position */
+#define MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_B ((uint32_t)(0x3UL << MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_B_POS)) /**< CTRL1_CAPEVENT_SEL_B Mask */
- #define MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_B_POS 27 /**< CTRL1_SW_CAPEVENT_B Position */
- #define MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_B_POS)) /**< CTRL1_SW_CAPEVENT_B Mask */
+#define MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_B_POS 27 /**< CTRL1_SW_CAPEVENT_B Position */
+#define MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_B_POS)) /**< CTRL1_SW_CAPEVENT_B Mask */
- #define MXC_F_TMR_REVB_CTRL1_WE_B_POS 28 /**< CTRL1_WE_B Position */
- #define MXC_F_TMR_REVB_CTRL1_WE_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_WE_B_POS)) /**< CTRL1_WE_B Mask */
+#define MXC_F_TMR_REVB_CTRL1_WE_B_POS 28 /**< CTRL1_WE_B Position */
+#define MXC_F_TMR_REVB_CTRL1_WE_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_WE_B_POS)) /**< CTRL1_WE_B Mask */
- #define MXC_F_TMR_REVB_CTRL1_CASCADE_POS 31 /**< CTRL1_CASCADE Position */
- #define MXC_F_TMR_REVB_CTRL1_CASCADE ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CASCADE_POS)) /**< CTRL1_CASCADE Mask */
+#define MXC_F_TMR_REVB_CTRL1_CASCADE_POS 31 /**< CTRL1_CASCADE Position */
+#define MXC_F_TMR_REVB_CTRL1_CASCADE ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CASCADE_POS)) /**< CTRL1_CASCADE Mask */
/**@} end of group TMR_REVB_CTRL1_Register */
@@ -415,11 +407,11 @@ typedef struct {
* @brief Timer Wakeup Status Register.
* @{
*/
- #define MXC_F_TMR_REVB_WKFL_A_POS 0 /**< WKFL_A Position */
- #define MXC_F_TMR_REVB_WKFL_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_WKFL_A_POS)) /**< WKFL_A Mask */
+#define MXC_F_TMR_REVB_WKFL_A_POS 0 /**< WKFL_A Position */
+#define MXC_F_TMR_REVB_WKFL_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_WKFL_A_POS)) /**< WKFL_A Mask */
- #define MXC_F_TMR_REVB_WKFL_B_POS 16 /**< WKFL_B Position */
- #define MXC_F_TMR_REVB_WKFL_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_WKFL_B_POS)) /**< WKFL_B Mask */
+#define MXC_F_TMR_REVB_WKFL_B_POS 16 /**< WKFL_B Position */
+#define MXC_F_TMR_REVB_WKFL_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_WKFL_B_POS)) /**< WKFL_B Mask */
/**@} end of group TMR_REVB_WKFL_Register */
@@ -427,4 +419,4 @@ typedef struct {
}
#endif
-#endif /* _TMR_REVB_REGS_H_ */
+#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_REVB_REGS_H_
diff --git a/Libraries/PeriphDrivers/Source/UART/uart_ai85.c b/Libraries/PeriphDrivers/Source/UART/uart_ai85.c
index 11ca9567843..ead00fc63b6 100644
--- a/Libraries/PeriphDrivers/Source/UART/uart_ai85.c
+++ b/Libraries/PeriphDrivers/Source/UART/uart_ai85.c
@@ -273,14 +273,14 @@ int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, mxc_uart_clock_t clock)
#ifndef MSDK_NO_GPIO_CLK_INIT
retval = MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IBRO);
#endif // MSDK_NO_GPIO_CLK_INIT
- clock_option = 2;
+ clock_option = 0;
break;
case MXC_UART_ERTCO_CLK:
#ifndef MSDK_NO_GPIO_CLK_INIT
retval = MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERTCO);
#endif // MSDK_NO_GPIO_CLK_INIT
- clock_option = 3;
+ clock_option = 1;
break;
default:
@@ -316,9 +316,9 @@ mxc_uart_clock_t MXC_UART_GetClockSource(mxc_uart_regs_t *uart)
break;
case 3:
switch (clock_option) {
- case 2:
+ case 0:
return MXC_UART_IBRO_CLK;
- case 3:
+ case 1:
return MXC_UART_ERTCO_CLK;
default:
return E_BAD_STATE;
diff --git a/Libraries/PeriphDrivers/Source/UART/uart_revb_regs.h b/Libraries/PeriphDrivers/Source/UART/uart_revb_regs.h
index ff2e8c77e97..b8cc0e9fba0 100644
--- a/Libraries/PeriphDrivers/Source/UART/uart_revb_regs.h
+++ b/Libraries/PeriphDrivers/Source/UART/uart_revb_regs.h
@@ -1,6 +1,8 @@
/**
* @file uart_revb_regs.h
* @brief Registers, Bit Masks and Bit Positions for the UART_REVB Peripheral Module.
+ * @note This file is @generated.
+ * @ingroup uart_revb_registers
*/
/******************************************************************************
@@ -23,8 +25,8 @@
*
******************************************************************************/
-#ifndef _UART_REVB_REGS_H_
-#define _UART_REVB_REGS_H_
+#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_REVB_REGS_H_
+#define LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_REVB_REGS_H_
/* **** Includes **** */
#include
@@ -32,11 +34,11 @@
#ifdef __cplusplus
extern "C" {
#endif
-
+
#if defined (__ICCARM__)
#pragma system_include
#endif
-
+
#if defined (__CC_ARM)
#pragma anon_unions
#endif
@@ -48,7 +50,11 @@ extern "C" {
#define __IO volatile
#endif
#ifndef __I
-#define __I volatile const
+#ifdef __cplusplus
+#define __I volatile
+#else
+#define __I volatile const
+#endif
#endif
#ifndef __O
#define __O volatile
@@ -64,7 +70,7 @@ extern "C" {
* @ingroup uart_revb
* @defgroup uart_revb_registers UART_REVB_Registers
* @brief Registers, Bit Masks and Bit Positions for the UART_REVB Peripheral Module.
- * @details UART Low Power Registers
+ * @details UART Low Power Registers
*/
/**
@@ -87,102 +93,81 @@ typedef struct {
__IO uint32_t wkfl; /**< \b 0x0038: UART_REVB WKFL Register */
} mxc_uart_revb_regs_t;
-/* Register offsets for module UART_REVB */
-/**
- * @ingroup uart_revb_registers
- * @defgroup UART_REVB_Register_Offsets Register Offsets
- * @brief UART_REVB Peripheral Register Offsets from the UART_REVB Base Peripheral Address.
- * @{
- */
- #define MXC_R_UART_REVB_CTRL ((uint32_t)0x00000000UL) /**< Offset from UART_REVB Base Address: 0x0000 */
- #define MXC_R_UART_REVB_STATUS ((uint32_t)0x00000004UL) /**< Offset from UART_REVB Base Address: 0x0004 */
- #define MXC_R_UART_REVB_INT_EN ((uint32_t)0x00000008UL) /**< Offset from UART_REVB Base Address: 0x0008 */
- #define MXC_R_UART_REVB_INT_FL ((uint32_t)0x0000000CUL) /**< Offset from UART_REVB Base Address: 0x000C */
- #define MXC_R_UART_REVB_CLKDIV ((uint32_t)0x00000010UL) /**< Offset from UART_REVB Base Address: 0x0010 */
- #define MXC_R_UART_REVB_OSR ((uint32_t)0x00000014UL) /**< Offset from UART_REVB Base Address: 0x0014 */
- #define MXC_R_UART_REVB_TXPEEK ((uint32_t)0x00000018UL) /**< Offset from UART_REVB Base Address: 0x0018 */
- #define MXC_R_UART_REVB_PNR ((uint32_t)0x0000001CUL) /**< Offset from UART_REVB Base Address: 0x001C */
- #define MXC_R_UART_REVB_FIFO ((uint32_t)0x00000020UL) /**< Offset from UART_REVB Base Address: 0x0020 */
- #define MXC_R_UART_REVB_DMA ((uint32_t)0x00000030UL) /**< Offset from UART_REVB Base Address: 0x0030 */
- #define MXC_R_UART_REVB_WKEN ((uint32_t)0x00000034UL) /**< Offset from UART_REVB Base Address: 0x0034 */
- #define MXC_R_UART_REVB_WKFL ((uint32_t)0x00000038UL) /**< Offset from UART_REVB Base Address: 0x0038 */
-/**@} end of group uart_revb_registers */
-
/**
* @ingroup uart_revb_registers
* @defgroup UART_REVB_CTRL UART_REVB_CTRL
* @brief Control register
* @{
*/
- #define MXC_F_UART_REVB_CTRL_RX_THD_VAL_POS 0 /**< CTRL_RX_THD_VAL Position */
- #define MXC_F_UART_REVB_CTRL_RX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_REVB_CTRL_RX_THD_VAL_POS)) /**< CTRL_RX_THD_VAL Mask */
+#define MXC_F_UART_REVB_CTRL_RX_THD_VAL_POS 0 /**< CTRL_RX_THD_VAL Position */
+#define MXC_F_UART_REVB_CTRL_RX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_REVB_CTRL_RX_THD_VAL_POS)) /**< CTRL_RX_THD_VAL Mask */
- #define MXC_F_UART_REVB_CTRL_PAR_EN_POS 4 /**< CTRL_PAR_EN Position */
- #define MXC_F_UART_REVB_CTRL_PAR_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_PAR_EN_POS)) /**< CTRL_PAR_EN Mask */
+#define MXC_F_UART_REVB_CTRL_PAR_EN_POS 4 /**< CTRL_PAR_EN Position */
+#define MXC_F_UART_REVB_CTRL_PAR_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_PAR_EN_POS)) /**< CTRL_PAR_EN Mask */
- #define MXC_F_UART_REVB_CTRL_PAR_EO_POS 5 /**< CTRL_PAR_EO Position */
- #define MXC_F_UART_REVB_CTRL_PAR_EO ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_PAR_EO_POS)) /**< CTRL_PAR_EO Mask */
+#define MXC_F_UART_REVB_CTRL_PAR_EO_POS 5 /**< CTRL_PAR_EO Position */
+#define MXC_F_UART_REVB_CTRL_PAR_EO ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_PAR_EO_POS)) /**< CTRL_PAR_EO Mask */
- #define MXC_F_UART_REVB_CTRL_PAR_MD_POS 6 /**< CTRL_PAR_MD Position */
- #define MXC_F_UART_REVB_CTRL_PAR_MD ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_PAR_MD_POS)) /**< CTRL_PAR_MD Mask */
+#define MXC_F_UART_REVB_CTRL_PAR_MD_POS 6 /**< CTRL_PAR_MD Position */
+#define MXC_F_UART_REVB_CTRL_PAR_MD ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_PAR_MD_POS)) /**< CTRL_PAR_MD Mask */
- #define MXC_F_UART_REVB_CTRL_CTS_DIS_POS 7 /**< CTRL_CTS_DIS Position */
- #define MXC_F_UART_REVB_CTRL_CTS_DIS ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_CTS_DIS_POS)) /**< CTRL_CTS_DIS Mask */
+#define MXC_F_UART_REVB_CTRL_CTS_DIS_POS 7 /**< CTRL_CTS_DIS Position */
+#define MXC_F_UART_REVB_CTRL_CTS_DIS ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_CTS_DIS_POS)) /**< CTRL_CTS_DIS Mask */
- #define MXC_F_UART_REVB_CTRL_TX_FLUSH_POS 8 /**< CTRL_TX_FLUSH Position */
- #define MXC_F_UART_REVB_CTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */
+#define MXC_F_UART_REVB_CTRL_TX_FLUSH_POS 8 /**< CTRL_TX_FLUSH Position */
+#define MXC_F_UART_REVB_CTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */
- #define MXC_F_UART_REVB_CTRL_RX_FLUSH_POS 9 /**< CTRL_RX_FLUSH Position */
- #define MXC_F_UART_REVB_CTRL_RX_FLUSH ((uint32_t)(0x3UL << MXC_F_UART_REVB_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */
+#define MXC_F_UART_REVB_CTRL_RX_FLUSH_POS 9 /**< CTRL_RX_FLUSH Position */
+#define MXC_F_UART_REVB_CTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */
- #define MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS 10 /**< CTRL_CHAR_SIZE Position */
- #define MXC_F_UART_REVB_CTRL_CHAR_SIZE ((uint32_t)(0x3UL << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */
- #define MXC_V_UART_REVB_CTRL_CHAR_SIZE_5BITS ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5BITS Value */
- #define MXC_S_UART_REVB_CTRL_CHAR_SIZE_5BITS (MXC_V_UART_REVB_CTRL_CHAR_SIZE_5BITS << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5BITS Setting */
- #define MXC_V_UART_REVB_CTRL_CHAR_SIZE_6BITS ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6BITS Value */
- #define MXC_S_UART_REVB_CTRL_CHAR_SIZE_6BITS (MXC_V_UART_REVB_CTRL_CHAR_SIZE_6BITS << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6BITS Setting */
- #define MXC_V_UART_REVB_CTRL_CHAR_SIZE_7BITS ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7BITS Value */
- #define MXC_S_UART_REVB_CTRL_CHAR_SIZE_7BITS (MXC_V_UART_REVB_CTRL_CHAR_SIZE_7BITS << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7BITS Setting */
- #define MXC_V_UART_REVB_CTRL_CHAR_SIZE_8BITS ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8BITS Value */
- #define MXC_S_UART_REVB_CTRL_CHAR_SIZE_8BITS (MXC_V_UART_REVB_CTRL_CHAR_SIZE_8BITS << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8BITS Setting */
+#define MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS 10 /**< CTRL_CHAR_SIZE Position */
+#define MXC_F_UART_REVB_CTRL_CHAR_SIZE ((uint32_t)(0x3UL << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */
+#define MXC_V_UART_REVB_CTRL_CHAR_SIZE_5BITS ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5BITS Value */
+#define MXC_S_UART_REVB_CTRL_CHAR_SIZE_5BITS (MXC_V_UART_REVB_CTRL_CHAR_SIZE_5BITS << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5BITS Setting */
+#define MXC_V_UART_REVB_CTRL_CHAR_SIZE_6BITS ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6BITS Value */
+#define MXC_S_UART_REVB_CTRL_CHAR_SIZE_6BITS (MXC_V_UART_REVB_CTRL_CHAR_SIZE_6BITS << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6BITS Setting */
+#define MXC_V_UART_REVB_CTRL_CHAR_SIZE_7BITS ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7BITS Value */
+#define MXC_S_UART_REVB_CTRL_CHAR_SIZE_7BITS (MXC_V_UART_REVB_CTRL_CHAR_SIZE_7BITS << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7BITS Setting */
+#define MXC_V_UART_REVB_CTRL_CHAR_SIZE_8BITS ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8BITS Value */
+#define MXC_S_UART_REVB_CTRL_CHAR_SIZE_8BITS (MXC_V_UART_REVB_CTRL_CHAR_SIZE_8BITS << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8BITS Setting */
- #define MXC_F_UART_REVB_CTRL_STOPBITS_POS 12 /**< CTRL_STOPBITS Position */
- #define MXC_F_UART_REVB_CTRL_STOPBITS ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */
+#define MXC_F_UART_REVB_CTRL_STOPBITS_POS 12 /**< CTRL_STOPBITS Position */
+#define MXC_F_UART_REVB_CTRL_STOPBITS ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */
- #define MXC_F_UART_REVB_CTRL_HFC_EN_POS 13 /**< CTRL_HFC_EN Position */
- #define MXC_F_UART_REVB_CTRL_HFC_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_HFC_EN_POS)) /**< CTRL_HFC_EN Mask */
+#define MXC_F_UART_REVB_CTRL_HFC_EN_POS 13 /**< CTRL_HFC_EN Position */
+#define MXC_F_UART_REVB_CTRL_HFC_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_HFC_EN_POS)) /**< CTRL_HFC_EN Mask */
- #define MXC_F_UART_REVB_CTRL_RTSDC_POS 14 /**< CTRL_RTSDC Position */
- #define MXC_F_UART_REVB_CTRL_RTSDC ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_RTSDC_POS)) /**< CTRL_RTSDC Mask */
+#define MXC_F_UART_REVB_CTRL_RTSDC_POS 14 /**< CTRL_RTSDC Position */
+#define MXC_F_UART_REVB_CTRL_RTSDC ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_RTSDC_POS)) /**< CTRL_RTSDC Mask */
- #define MXC_F_UART_REVB_CTRL_BCLKEN_POS 15 /**< CTRL_BCLKEN Position */
- #define MXC_F_UART_REVB_CTRL_BCLKEN ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_BCLKEN_POS)) /**< CTRL_BCLKEN Mask */
+#define MXC_F_UART_REVB_CTRL_BCLKEN_POS 15 /**< CTRL_BCLKEN Position */
+#define MXC_F_UART_REVB_CTRL_BCLKEN ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_BCLKEN_POS)) /**< CTRL_BCLKEN Mask */
- #define MXC_F_UART_REVB_CTRL_BCLKSRC_POS 16 /**< CTRL_BCLKSRC Position */
- #define MXC_F_UART_REVB_CTRL_BCLKSRC ((uint32_t)(0x3UL << MXC_F_UART_REVB_CTRL_BCLKSRC_POS)) /**< CTRL_BCLKSRC Mask */
- #define MXC_V_UART_REVB_CTRL_BCLKSRC_PERIPHERAL_CLOCK ((uint32_t)0x0UL) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Value */
- #define MXC_S_UART_REVB_CTRL_BCLKSRC_PERIPHERAL_CLOCK (MXC_V_UART_REVB_CTRL_BCLKSRC_PERIPHERAL_CLOCK << MXC_F_UART_REVB_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Setting */
- #define MXC_V_UART_REVB_CTRL_BCLKSRC_CLK1 ((uint32_t)0x1UL) /**< CTRL_BCLKSRC_CLK1 Value */
- #define MXC_S_UART_REVB_CTRL_BCLKSRC_CLK1 (MXC_V_UART_REVB_CTRL_BCLKSRC_CLK1 << MXC_F_UART_REVB_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK1 Setting */
- #define MXC_V_UART_REVB_CTRL_BCLKSRC_CLK2 ((uint32_t)0x2UL) /**< CTRL_BCLKSRC_CLK2 Value */
- #define MXC_S_UART_REVB_CTRL_BCLKSRC_CLK2 (MXC_V_UART_REVB_CTRL_BCLKSRC_CLK2 << MXC_F_UART_REVB_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK2 Setting */
- #define MXC_V_UART_REVB_CTRL_BCLKSRC_CLK3 ((uint32_t)0x3UL) /**< CTRL_BCLKSRC_CLK3 Value */
- #define MXC_S_UART_REVB_CTRL_BCLKSRC_CLK3 (MXC_V_UART_REVB_CTRL_BCLKSRC_CLK3 << MXC_F_UART_REVB_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK3 Setting */
+#define MXC_F_UART_REVB_CTRL_BCLKSRC_POS 16 /**< CTRL_BCLKSRC Position */
+#define MXC_F_UART_REVB_CTRL_BCLKSRC ((uint32_t)(0x3UL << MXC_F_UART_REVB_CTRL_BCLKSRC_POS)) /**< CTRL_BCLKSRC Mask */
+#define MXC_V_UART_REVB_CTRL_BCLKSRC_PERIPHERAL_CLOCK ((uint32_t)0x0UL) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Value */
+#define MXC_S_UART_REVB_CTRL_BCLKSRC_PERIPHERAL_CLOCK (MXC_V_UART_REVB_CTRL_BCLKSRC_PERIPHERAL_CLOCK << MXC_F_UART_REVB_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Setting */
+#define MXC_V_UART_REVB_CTRL_BCLKSRC_CLK1 ((uint32_t)0x1UL) /**< CTRL_BCLKSRC_CLK1 Value */
+#define MXC_S_UART_REVB_CTRL_BCLKSRC_CLK1 (MXC_V_UART_REVB_CTRL_BCLKSRC_CLK1 << MXC_F_UART_REVB_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK1 Setting */
+#define MXC_V_UART_REVB_CTRL_BCLKSRC_CLK2 ((uint32_t)0x2UL) /**< CTRL_BCLKSRC_CLK2 Value */
+#define MXC_S_UART_REVB_CTRL_BCLKSRC_CLK2 (MXC_V_UART_REVB_CTRL_BCLKSRC_CLK2 << MXC_F_UART_REVB_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK2 Setting */
+#define MXC_V_UART_REVB_CTRL_BCLKSRC_CLK3 ((uint32_t)0x3UL) /**< CTRL_BCLKSRC_CLK3 Value */
+#define MXC_S_UART_REVB_CTRL_BCLKSRC_CLK3 (MXC_V_UART_REVB_CTRL_BCLKSRC_CLK3 << MXC_F_UART_REVB_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK3 Setting */
- #define MXC_F_UART_REVB_CTRL_DPFE_EN_POS 18 /**< CTRL_DPFE_EN Position */
- #define MXC_F_UART_REVB_CTRL_DPFE_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_DPFE_EN_POS)) /**< CTRL_DPFE_EN Mask */
+#define MXC_F_UART_REVB_CTRL_DPFE_EN_POS 18 /**< CTRL_DPFE_EN Position */
+#define MXC_F_UART_REVB_CTRL_DPFE_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_DPFE_EN_POS)) /**< CTRL_DPFE_EN Mask */
- #define MXC_F_UART_REVB_CTRL_BCLKRDY_POS 19 /**< CTRL_BCLKRDY Position */
- #define MXC_F_UART_REVB_CTRL_BCLKRDY ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_BCLKRDY_POS)) /**< CTRL_BCLKRDY Mask */
+#define MXC_F_UART_REVB_CTRL_BCLKRDY_POS 19 /**< CTRL_BCLKRDY Position */
+#define MXC_F_UART_REVB_CTRL_BCLKRDY ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_BCLKRDY_POS)) /**< CTRL_BCLKRDY Mask */
- #define MXC_F_UART_REVB_CTRL_UCAGM_POS 20 /**< CTRL_UCAGM Position */
- #define MXC_F_UART_REVB_CTRL_UCAGM ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_UCAGM_POS)) /**< CTRL_UCAGM Mask */
+#define MXC_F_UART_REVB_CTRL_UCAGM_POS 20 /**< CTRL_UCAGM Position */
+#define MXC_F_UART_REVB_CTRL_UCAGM ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_UCAGM_POS)) /**< CTRL_UCAGM Mask */
- #define MXC_F_UART_REVB_CTRL_FDM_POS 21 /**< CTRL_FDM Position */
- #define MXC_F_UART_REVB_CTRL_FDM ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_FDM_POS)) /**< CTRL_FDM Mask */
+#define MXC_F_UART_REVB_CTRL_FDM_POS 21 /**< CTRL_FDM Position */
+#define MXC_F_UART_REVB_CTRL_FDM ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_FDM_POS)) /**< CTRL_FDM Mask */
- #define MXC_F_UART_REVB_CTRL_DESM_POS 22 /**< CTRL_DESM Position */
- #define MXC_F_UART_REVB_CTRL_DESM ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_DESM_POS)) /**< CTRL_DESM Mask */
+#define MXC_F_UART_REVB_CTRL_DESM_POS 22 /**< CTRL_DESM Position */
+#define MXC_F_UART_REVB_CTRL_DESM ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_DESM_POS)) /**< CTRL_DESM Mask */
/**@} end of group UART_REVB_CTRL_Register */
@@ -192,29 +177,29 @@ typedef struct {
* @brief Status register
* @{
*/
- #define MXC_F_UART_REVB_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */
- #define MXC_F_UART_REVB_STATUS_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */
+#define MXC_F_UART_REVB_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */
+#define MXC_F_UART_REVB_STATUS_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */
- #define MXC_F_UART_REVB_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */
- #define MXC_F_UART_REVB_STATUS_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */
+#define MXC_F_UART_REVB_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */
+#define MXC_F_UART_REVB_STATUS_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */
- #define MXC_F_UART_REVB_STATUS_RX_EM_POS 4 /**< STATUS_RX_EM Position */
- #define MXC_F_UART_REVB_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */
+#define MXC_F_UART_REVB_STATUS_RX_EM_POS 4 /**< STATUS_RX_EM Position */
+#define MXC_F_UART_REVB_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */
- #define MXC_F_UART_REVB_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */
- #define MXC_F_UART_REVB_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */
+#define MXC_F_UART_REVB_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */
+#define MXC_F_UART_REVB_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */
- #define MXC_F_UART_REVB_STATUS_TX_EM_POS 6 /**< STATUS_TX_EM Position */
- #define MXC_F_UART_REVB_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */
+#define MXC_F_UART_REVB_STATUS_TX_EM_POS 6 /**< STATUS_TX_EM Position */
+#define MXC_F_UART_REVB_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */
- #define MXC_F_UART_REVB_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */
- #define MXC_F_UART_REVB_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */
+#define MXC_F_UART_REVB_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */
+#define MXC_F_UART_REVB_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */
- #define MXC_F_UART_REVB_STATUS_RX_LVL_POS 8 /**< STATUS_RX_LVL Position */
- #define MXC_F_UART_REVB_STATUS_RX_LVL ((uint32_t)(0xFUL << MXC_F_UART_REVB_STATUS_RX_LVL_POS)) /**< STATUS_RX_LVL Mask */
+#define MXC_F_UART_REVB_STATUS_RX_LVL_POS 8 /**< STATUS_RX_LVL Position */
+#define MXC_F_UART_REVB_STATUS_RX_LVL ((uint32_t)(0xFUL << MXC_F_UART_REVB_STATUS_RX_LVL_POS)) /**< STATUS_RX_LVL Mask */
- #define MXC_F_UART_REVB_STATUS_TX_LVL_POS 12 /**< STATUS_TX_LVL Position */
- #define MXC_F_UART_REVB_STATUS_TX_LVL ((uint32_t)(0xFUL << MXC_F_UART_REVB_STATUS_TX_LVL_POS)) /**< STATUS_TX_LVL Mask */
+#define MXC_F_UART_REVB_STATUS_TX_LVL_POS 12 /**< STATUS_TX_LVL Position */
+#define MXC_F_UART_REVB_STATUS_TX_LVL ((uint32_t)(0xFUL << MXC_F_UART_REVB_STATUS_TX_LVL_POS)) /**< STATUS_TX_LVL Mask */
/**@} end of group UART_REVB_STATUS_Register */
@@ -224,26 +209,26 @@ typedef struct {
* @brief Interrupt Enable control register
* @{
*/
- #define MXC_F_UART_REVB_INT_EN_RX_FERR_POS 0 /**< INT_EN_RX_FERR Position */
- #define MXC_F_UART_REVB_INT_EN_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_RX_FERR_POS)) /**< INT_EN_RX_FERR Mask */
+#define MXC_F_UART_REVB_INT_EN_RX_FERR_POS 0 /**< INT_EN_RX_FERR Position */
+#define MXC_F_UART_REVB_INT_EN_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_RX_FERR_POS)) /**< INT_EN_RX_FERR Mask */
- #define MXC_F_UART_REVB_INT_EN_RX_PAR_POS 1 /**< INT_EN_RX_PAR Position */
- #define MXC_F_UART_REVB_INT_EN_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_RX_PAR_POS)) /**< INT_EN_RX_PAR Mask */
+#define MXC_F_UART_REVB_INT_EN_RX_PAR_POS 1 /**< INT_EN_RX_PAR Position */
+#define MXC_F_UART_REVB_INT_EN_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_RX_PAR_POS)) /**< INT_EN_RX_PAR Mask */
- #define MXC_F_UART_REVB_INT_EN_CTS_EV_POS 2 /**< INT_EN_CTS_EV Position */
- #define MXC_F_UART_REVB_INT_EN_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_CTS_EV_POS)) /**< INT_EN_CTS_EV Mask */
+#define MXC_F_UART_REVB_INT_EN_CTS_EV_POS 2 /**< INT_EN_CTS_EV Position */
+#define MXC_F_UART_REVB_INT_EN_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_CTS_EV_POS)) /**< INT_EN_CTS_EV Mask */
- #define MXC_F_UART_REVB_INT_EN_RX_OV_POS 3 /**< INT_EN_RX_OV Position */
- #define MXC_F_UART_REVB_INT_EN_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_RX_OV_POS)) /**< INT_EN_RX_OV Mask */
+#define MXC_F_UART_REVB_INT_EN_RX_OV_POS 3 /**< INT_EN_RX_OV Position */
+#define MXC_F_UART_REVB_INT_EN_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_RX_OV_POS)) /**< INT_EN_RX_OV Mask */
- #define MXC_F_UART_REVB_INT_EN_RX_THD_POS 4 /**< INT_EN_RX_THD Position */
- #define MXC_F_UART_REVB_INT_EN_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_RX_THD_POS)) /**< INT_EN_RX_THD Mask */
+#define MXC_F_UART_REVB_INT_EN_RX_THD_POS 4 /**< INT_EN_RX_THD Position */
+#define MXC_F_UART_REVB_INT_EN_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_RX_THD_POS)) /**< INT_EN_RX_THD Mask */
- #define MXC_F_UART_REVB_INT_EN_TX_OB_POS 5 /**< INT_EN_TX_OB Position */
- #define MXC_F_UART_REVB_INT_EN_TX_OB ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_TX_OB_POS)) /**< INT_EN_TX_OB Mask */
+#define MXC_F_UART_REVB_INT_EN_TX_OB_POS 5 /**< INT_EN_TX_OB Position */
+#define MXC_F_UART_REVB_INT_EN_TX_OB ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_TX_OB_POS)) /**< INT_EN_TX_OB Mask */
- #define MXC_F_UART_REVB_INT_EN_TX_HE_POS 6 /**< INT_EN_TX_HE Position */
- #define MXC_F_UART_REVB_INT_EN_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_TX_HE_POS)) /**< INT_EN_TX_HE Mask */
+#define MXC_F_UART_REVB_INT_EN_TX_HE_POS 6 /**< INT_EN_TX_HE Position */
+#define MXC_F_UART_REVB_INT_EN_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_TX_HE_POS)) /**< INT_EN_TX_HE Mask */
/**@} end of group UART_REVB_INT_EN_Register */
@@ -253,26 +238,26 @@ typedef struct {
* @brief Interrupt status flags Control register
* @{
*/
- #define MXC_F_UART_REVB_INT_FL_RX_FERR_POS 0 /**< INT_FL_RX_FERR Position */
- #define MXC_F_UART_REVB_INT_FL_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_RX_FERR_POS)) /**< INT_FL_RX_FERR Mask */
+#define MXC_F_UART_REVB_INT_FL_RX_FERR_POS 0 /**< INT_FL_RX_FERR Position */
+#define MXC_F_UART_REVB_INT_FL_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_RX_FERR_POS)) /**< INT_FL_RX_FERR Mask */
- #define MXC_F_UART_REVB_INT_FL_RX_PAR_POS 1 /**< INT_FL_RX_PAR Position */
- #define MXC_F_UART_REVB_INT_FL_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_RX_PAR_POS)) /**< INT_FL_RX_PAR Mask */
+#define MXC_F_UART_REVB_INT_FL_RX_PAR_POS 1 /**< INT_FL_RX_PAR Position */
+#define MXC_F_UART_REVB_INT_FL_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_RX_PAR_POS)) /**< INT_FL_RX_PAR Mask */
- #define MXC_F_UART_REVB_INT_FL_CTS_EV_POS 2 /**< INT_FL_CTS_EV Position */
- #define MXC_F_UART_REVB_INT_FL_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_CTS_EV_POS)) /**< INT_FL_CTS_EV Mask */
+#define MXC_F_UART_REVB_INT_FL_CTS_EV_POS 2 /**< INT_FL_CTS_EV Position */
+#define MXC_F_UART_REVB_INT_FL_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_CTS_EV_POS)) /**< INT_FL_CTS_EV Mask */
- #define MXC_F_UART_REVB_INT_FL_RX_OV_POS 3 /**< INT_FL_RX_OV Position */
- #define MXC_F_UART_REVB_INT_FL_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_RX_OV_POS)) /**< INT_FL_RX_OV Mask */
+#define MXC_F_UART_REVB_INT_FL_RX_OV_POS 3 /**< INT_FL_RX_OV Position */
+#define MXC_F_UART_REVB_INT_FL_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_RX_OV_POS)) /**< INT_FL_RX_OV Mask */
- #define MXC_F_UART_REVB_INT_FL_RX_THD_POS 4 /**< INT_FL_RX_THD Position */
- #define MXC_F_UART_REVB_INT_FL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_RX_THD_POS)) /**< INT_FL_RX_THD Mask */
+#define MXC_F_UART_REVB_INT_FL_RX_THD_POS 4 /**< INT_FL_RX_THD Position */
+#define MXC_F_UART_REVB_INT_FL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_RX_THD_POS)) /**< INT_FL_RX_THD Mask */
- #define MXC_F_UART_REVB_INT_FL_TX_OB_POS 5 /**< INT_FL_TX_OB Position */
- #define MXC_F_UART_REVB_INT_FL_TX_OB ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_TX_OB_POS)) /**< INT_FL_TX_OB Mask */
+#define MXC_F_UART_REVB_INT_FL_TX_OB_POS 5 /**< INT_FL_TX_OB Position */
+#define MXC_F_UART_REVB_INT_FL_TX_OB ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_TX_OB_POS)) /**< INT_FL_TX_OB Mask */
- #define MXC_F_UART_REVB_INT_FL_TX_HE_POS 6 /**< INT_FL_TX_HE Position */
- #define MXC_F_UART_REVB_INT_FL_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_TX_HE_POS)) /**< INT_FL_TX_HE Mask */
+#define MXC_F_UART_REVB_INT_FL_TX_HE_POS 6 /**< INT_FL_TX_HE Position */
+#define MXC_F_UART_REVB_INT_FL_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_TX_HE_POS)) /**< INT_FL_TX_HE Mask */
/**@} end of group UART_REVB_INT_FL_Register */
@@ -282,8 +267,8 @@ typedef struct {
* @brief Clock Divider register
* @{
*/
- #define MXC_F_UART_REVB_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */
- #define MXC_F_UART_REVB_CLKDIV_CLKDIV ((uint32_t)(0xFFFFFUL << MXC_F_UART_REVB_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
+#define MXC_F_UART_REVB_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */
+#define MXC_F_UART_REVB_CLKDIV_CLKDIV ((uint32_t)(0xFFFFFUL << MXC_F_UART_REVB_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
/**@} end of group UART_REVB_CLKDIV_Register */
@@ -293,8 +278,8 @@ typedef struct {
* @brief Over Sampling Rate register
* @{
*/
- #define MXC_F_UART_REVB_OSR_OSR_POS 0 /**< OSR_OSR Position */
- #define MXC_F_UART_REVB_OSR_OSR ((uint32_t)(0x7UL << MXC_F_UART_REVB_OSR_OSR_POS)) /**< OSR_OSR Mask */
+#define MXC_F_UART_REVB_OSR_OSR_POS 0 /**< OSR_OSR Position */
+#define MXC_F_UART_REVB_OSR_OSR ((uint32_t)(0x7UL << MXC_F_UART_REVB_OSR_OSR_POS)) /**< OSR_OSR Mask */
/**@} end of group UART_REVB_OSR_Register */
@@ -304,8 +289,8 @@ typedef struct {
* @brief TX FIFO Output Peek register
* @{
*/
- #define MXC_F_UART_REVB_TXPEEK_DATA_POS 0 /**< TXPEEK_DATA Position */
- #define MXC_F_UART_REVB_TXPEEK_DATA ((uint32_t)(0xFFUL << MXC_F_UART_REVB_TXPEEK_DATA_POS)) /**< TXPEEK_DATA Mask */
+#define MXC_F_UART_REVB_TXPEEK_DATA_POS 0 /**< TXPEEK_DATA Position */
+#define MXC_F_UART_REVB_TXPEEK_DATA ((uint32_t)(0xFFUL << MXC_F_UART_REVB_TXPEEK_DATA_POS)) /**< TXPEEK_DATA Mask */
/**@} end of group UART_REVB_TXPEEK_Register */
@@ -315,11 +300,11 @@ typedef struct {
* @brief Pin register
* @{
*/
- #define MXC_F_UART_REVB_PNR_CTS_POS 0 /**< PNR_CTS Position */
- #define MXC_F_UART_REVB_PNR_CTS ((uint32_t)(0x1UL << MXC_F_UART_REVB_PNR_CTS_POS)) /**< PNR_CTS Mask */
+#define MXC_F_UART_REVB_PNR_CTS_POS 0 /**< PNR_CTS Position */
+#define MXC_F_UART_REVB_PNR_CTS ((uint32_t)(0x1UL << MXC_F_UART_REVB_PNR_CTS_POS)) /**< PNR_CTS Mask */
- #define MXC_F_UART_REVB_PNR_RTS_POS 1 /**< PNR_RTS Position */
- #define MXC_F_UART_REVB_PNR_RTS ((uint32_t)(0x1UL << MXC_F_UART_REVB_PNR_RTS_POS)) /**< PNR_RTS Mask */
+#define MXC_F_UART_REVB_PNR_RTS_POS 1 /**< PNR_RTS Position */
+#define MXC_F_UART_REVB_PNR_RTS ((uint32_t)(0x1UL << MXC_F_UART_REVB_PNR_RTS_POS)) /**< PNR_RTS Mask */
/**@} end of group UART_REVB_PNR_Register */
@@ -329,11 +314,11 @@ typedef struct {
* @brief FIFO Read/Write register
* @{
*/
- #define MXC_F_UART_REVB_FIFO_DATA_POS 0 /**< FIFO_DATA Position */
- #define MXC_F_UART_REVB_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_UART_REVB_FIFO_DATA_POS)) /**< FIFO_DATA Mask */
+#define MXC_F_UART_REVB_FIFO_DATA_POS 0 /**< FIFO_DATA Position */
+#define MXC_F_UART_REVB_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_UART_REVB_FIFO_DATA_POS)) /**< FIFO_DATA Mask */
- #define MXC_F_UART_REVB_FIFO_RX_PAR_POS 8 /**< FIFO_RX_PAR Position */
- #define MXC_F_UART_REVB_FIFO_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_REVB_FIFO_RX_PAR_POS)) /**< FIFO_RX_PAR Mask */
+#define MXC_F_UART_REVB_FIFO_RX_PAR_POS 8 /**< FIFO_RX_PAR Position */
+#define MXC_F_UART_REVB_FIFO_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_REVB_FIFO_RX_PAR_POS)) /**< FIFO_RX_PAR Mask */
/**@} end of group UART_REVB_FIFO_Register */
@@ -343,17 +328,17 @@ typedef struct {
* @brief DMA Configuration register
* @{
*/
- #define MXC_F_UART_REVB_DMA_TX_THD_VAL_POS 0 /**< DMA_TX_THD_VAL Position */
- #define MXC_F_UART_REVB_DMA_TX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_REVB_DMA_TX_THD_VAL_POS)) /**< DMA_TX_THD_VAL Mask */
+#define MXC_F_UART_REVB_DMA_TX_THD_VAL_POS 0 /**< DMA_TX_THD_VAL Position */
+#define MXC_F_UART_REVB_DMA_TX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_REVB_DMA_TX_THD_VAL_POS)) /**< DMA_TX_THD_VAL Mask */
- #define MXC_F_UART_REVB_DMA_TX_EN_POS 4 /**< DMA_TX_EN Position */
- #define MXC_F_UART_REVB_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */
+#define MXC_F_UART_REVB_DMA_TX_EN_POS 4 /**< DMA_TX_EN Position */
+#define MXC_F_UART_REVB_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */
- #define MXC_F_UART_REVB_DMA_RX_THD_VAL_POS 5 /**< DMA_RX_THD_VAL Position */
- #define MXC_F_UART_REVB_DMA_RX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_REVB_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */
+#define MXC_F_UART_REVB_DMA_RX_THD_VAL_POS 5 /**< DMA_RX_THD_VAL Position */
+#define MXC_F_UART_REVB_DMA_RX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_REVB_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */
- #define MXC_F_UART_REVB_DMA_RX_EN_POS 9 /**< DMA_RX_EN Position */
- #define MXC_F_UART_REVB_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */
+#define MXC_F_UART_REVB_DMA_RX_EN_POS 9 /**< DMA_RX_EN Position */
+#define MXC_F_UART_REVB_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */
/**@} end of group UART_REVB_DMA_Register */
@@ -363,14 +348,14 @@ typedef struct {
* @brief Wake up enable Control register
* @{
*/
- #define MXC_F_UART_REVB_WKEN_RX_NE_POS 0 /**< WKEN_RX_NE Position */
- #define MXC_F_UART_REVB_WKEN_RX_NE ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKEN_RX_NE_POS)) /**< WKEN_RX_NE Mask */
+#define MXC_F_UART_REVB_WKEN_RX_NE_POS 0 /**< WKEN_RX_NE Position */
+#define MXC_F_UART_REVB_WKEN_RX_NE ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKEN_RX_NE_POS)) /**< WKEN_RX_NE Mask */
- #define MXC_F_UART_REVB_WKEN_RX_FULL_POS 1 /**< WKEN_RX_FULL Position */
- #define MXC_F_UART_REVB_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */
+#define MXC_F_UART_REVB_WKEN_RX_FULL_POS 1 /**< WKEN_RX_FULL Position */
+#define MXC_F_UART_REVB_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */
- #define MXC_F_UART_REVB_WKEN_RX_THD_POS 1 /**< WKEN_RX_THD Position */
- #define MXC_F_UART_REVB_WKEN_RX_THD ((uint32_t)(0x3UL << MXC_F_UART_REVB_WKEN_RX_THD_POS)) /**< WKEN_RX_THD Mask */
+#define MXC_F_UART_REVB_WKEN_RX_THD_POS 2 /**< WKEN_RX_THD Position */
+#define MXC_F_UART_REVB_WKEN_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKEN_RX_THD_POS)) /**< WKEN_RX_THD Mask */
/**@} end of group UART_REVB_WKEN_Register */
@@ -380,14 +365,14 @@ typedef struct {
* @brief Wake up Flags register
* @{
*/
- #define MXC_F_UART_REVB_WKFL_RX_NE_POS 0 /**< WKFL_RX_NE Position */
- #define MXC_F_UART_REVB_WKFL_RX_NE ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKFL_RX_NE_POS)) /**< WKFL_RX_NE Mask */
+#define MXC_F_UART_REVB_WKFL_RX_NE_POS 0 /**< WKFL_RX_NE Position */
+#define MXC_F_UART_REVB_WKFL_RX_NE ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKFL_RX_NE_POS)) /**< WKFL_RX_NE Mask */
- #define MXC_F_UART_REVB_WKFL_RX_FULL_POS 1 /**< WKFL_RX_FULL Position */
- #define MXC_F_UART_REVB_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */
+#define MXC_F_UART_REVB_WKFL_RX_FULL_POS 1 /**< WKFL_RX_FULL Position */
+#define MXC_F_UART_REVB_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */
- #define MXC_F_UART_REVB_WKFL_RX_THD_POS 2 /**< WKFL_RX_THD Position */
- #define MXC_F_UART_REVB_WKFL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKFL_RX_THD_POS)) /**< WKFL_RX_THD Mask */
+#define MXC_F_UART_REVB_WKFL_RX_THD_POS 2 /**< WKFL_RX_THD Position */
+#define MXC_F_UART_REVB_WKFL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKFL_RX_THD_POS)) /**< WKFL_RX_THD Mask */
/**@} end of group UART_REVB_WKFL_Register */
@@ -395,4 +380,4 @@ typedef struct {
}
#endif
-#endif /* _UART_REVB_REGS_H_ */
+#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_REVB_REGS_H_
diff --git a/Libraries/PeriphDrivers/Source/WUT/wut_ai85.c b/Libraries/PeriphDrivers/Source/WUT/wut_ai85.c
index aa1d1887a44..8243c7de9dc 100644
--- a/Libraries/PeriphDrivers/Source/WUT/wut_ai85.c
+++ b/Libraries/PeriphDrivers/Source/WUT/wut_ai85.c
@@ -98,12 +98,24 @@ void MXC_WUT_IntClear(void)
MXC_WUT_RevA_IntClear((mxc_wut_reva_regs_t *)MXC_WUT);
}
+/* ************************************************************************* */
+void MXC_WUT_ClearFlags(void)
+{
+ MXC_WUT_RevA_IntClear((mxc_wut_reva_regs_t *)MXC_WUT);
+}
+
/* ************************************************************************* */
uint32_t MXC_WUT_IntStatus(void)
{
return MXC_WUT_RevA_IntStatus((mxc_wut_reva_regs_t *)MXC_WUT);
}
+/* ************************************************************************* */
+uint32_t MXC_WUT_GetFlags(void)
+{
+ return MXC_WUT_RevA_IntStatus((mxc_wut_reva_regs_t *)MXC_WUT);
+}
+
/* ************************************************************************* */
void MXC_WUT_SetCompare(uint32_t cmp_cnt)
{
@@ -135,12 +147,24 @@ void MXC_WUT_Edge(void)
MXC_WUT_RevA_Edge((mxc_wut_reva_regs_t *)MXC_WUT);
}
+/* ************************************************************************** */
+void MXC_WUT_WaitForEdge(void)
+{
+ MXC_WUT_RevA_Edge((mxc_wut_reva_regs_t *)MXC_WUT);
+}
+
/* ************************************************************************** */
void MXC_WUT_Store(void)
{
MXC_WUT_RevA_Store((mxc_wut_reva_regs_t *)MXC_WUT);
}
+/* ************************************************************************** */
+void MXC_WUT_StoreCount(void)
+{
+ MXC_WUT_RevA_Store((mxc_wut_reva_regs_t *)MXC_WUT);
+}
+
/* ************************************************************************** */
void MXC_WUT_RestoreBBClock(uint32_t dbbFreq)
{
@@ -223,7 +247,7 @@ int MXC_WUT_Handler(void)
mxc_wut_complete_cb_t cbTemp;
/* Clear the interrupt flags */
- MXC_WUT_IntClear();
+ MXC_WUT_ClearFlags();
if (!trimPending) {
return E_NO_ERROR;
diff --git a/Libraries/PeriphDrivers/Source/WUT/wut_ai87.c b/Libraries/PeriphDrivers/Source/WUT/wut_ai87.c
index 06f97dfa663..458623ce17f 100644
--- a/Libraries/PeriphDrivers/Source/WUT/wut_ai87.c
+++ b/Libraries/PeriphDrivers/Source/WUT/wut_ai87.c
@@ -88,12 +88,24 @@ void MXC_WUT_IntClear(void)
MXC_WUT_RevA_IntClear((mxc_wut_reva_regs_t *)MXC_WUT);
}
+/* ************************************************************************* */
+void MXC_WUT_ClearFlags(void)
+{
+ MXC_WUT_RevA_IntClear((mxc_wut_reva_regs_t *)MXC_WUT);
+}
+
/* ************************************************************************* */
uint32_t MXC_WUT_IntStatus(void)
{
return MXC_WUT_RevA_IntStatus((mxc_wut_reva_regs_t *)MXC_WUT);
}
+/* ************************************************************************* */
+uint32_t MXC_WUT_GetFlags(void)
+{
+ return MXC_WUT_RevA_IntStatus((mxc_wut_reva_regs_t *)MXC_WUT);
+}
+
/* ************************************************************************* */
void MXC_WUT_SetCompare(uint32_t cmp_cnt)
{
@@ -125,12 +137,24 @@ void MXC_WUT_Edge(void)
MXC_WUT_RevA_Edge((mxc_wut_reva_regs_t *)MXC_WUT);
}
+/* ************************************************************************** */
+void MXC_WUT_WaitForEdge(void)
+{
+ MXC_WUT_RevA_Edge((mxc_wut_reva_regs_t *)MXC_WUT);
+}
+
/* ************************************************************************** */
void MXC_WUT_Store(void)
{
MXC_WUT_RevA_Store((mxc_wut_reva_regs_t *)MXC_WUT);
}
+/* ************************************************************************** */
+void MXC_WUT_StoreCount(void)
+{
+ MXC_WUT_RevA_Store((mxc_wut_reva_regs_t *)MXC_WUT);
+}
+
/* ************************************************************************** */
void MXC_WUT_RestoreBBClock(uint32_t dbbFreq)
{
diff --git a/Libraries/PeriphDrivers/Source/WUT/wut_me14.c b/Libraries/PeriphDrivers/Source/WUT/wut_me14.c
index 95d829d2824..717cf3873ce 100644
--- a/Libraries/PeriphDrivers/Source/WUT/wut_me14.c
+++ b/Libraries/PeriphDrivers/Source/WUT/wut_me14.c
@@ -105,12 +105,24 @@ void MXC_WUT_IntClear(void)
MXC_WUT_RevA_IntClear((mxc_wut_reva_regs_t *)MXC_WUT);
}
+/* ************************************************************************* */
+void MXC_WUT_ClearFlags(void)
+{
+ MXC_WUT_RevA_IntClear((mxc_wut_reva_regs_t *)MXC_WUT);
+}
+
/* ************************************************************************* */
uint32_t MXC_WUT_IntStatus(void)
{
return MXC_WUT_RevA_IntStatus((mxc_wut_reva_regs_t *)MXC_WUT);
}
+/* ************************************************************************* */
+uint32_t MXC_WUT_GetFlags(void)
+{
+ return MXC_WUT_RevA_IntStatus((mxc_wut_reva_regs_t *)MXC_WUT);
+}
+
/* ************************************************************************* */
void MXC_WUT_SetCompare(uint32_t cmp_cnt)
{
@@ -142,12 +154,24 @@ void MXC_WUT_Edge(void)
MXC_WUT_RevA_Edge((mxc_wut_reva_regs_t *)MXC_WUT);
}
+/* ************************************************************************** */
+void MXC_WUT_WaitForEdge(void)
+{
+ MXC_WUT_RevA_Edge((mxc_wut_reva_regs_t *)MXC_WUT);
+}
+
/* ************************************************************************** */
void MXC_WUT_Store(void)
{
MXC_WUT_RevA_Store((mxc_wut_reva_regs_t *)MXC_WUT);
}
+/* ************************************************************************** */
+void MXC_WUT_StoreCount(void)
+{
+ MXC_WUT_RevA_Store((mxc_wut_reva_regs_t *)MXC_WUT);
+}
+
/* ************************************************************************** */
void MXC_WUT_RestoreBBClock(uint32_t dbbFreq)
{
@@ -234,7 +258,7 @@ int MXC_WUT_Handler(void)
mxc_wut_complete_cb_t cbTemp;
/* Clear the interrupt flags */
- MXC_WUT_IntClear();
+ MXC_WUT_ClearFlags();
if (!trimPending) {
return E_NO_ERROR;
diff --git a/Libraries/PeriphDrivers/Source/WUT/wut_me17.c b/Libraries/PeriphDrivers/Source/WUT/wut_me17.c
index 021f1861f7b..f7da6f83da0 100644
--- a/Libraries/PeriphDrivers/Source/WUT/wut_me17.c
+++ b/Libraries/PeriphDrivers/Source/WUT/wut_me17.c
@@ -98,12 +98,24 @@ void MXC_WUT_IntClear(mxc_wut_regs_t *wut)
MXC_WUT_RevA_IntClear((mxc_wut_reva_regs_t *)wut);
}
+/* ************************************************************************* */
+void MXC_WUT_ClearFlags(mxc_wut_regs_t *wut)
+{
+ MXC_WUT_RevA_IntClear((mxc_wut_reva_regs_t *)wut);
+}
+
/* ************************************************************************* */
uint32_t MXC_WUT_IntStatus(mxc_wut_regs_t *wut)
{
return MXC_WUT_RevA_IntStatus((mxc_wut_reva_regs_t *)wut);
}
+/* ************************************************************************* */
+uint32_t MXC_WUT_GetFlags(mxc_wut_regs_t *wut)
+{
+ return MXC_WUT_RevA_IntStatus((mxc_wut_reva_regs_t *)wut);
+}
+
/* ************************************************************************* */
void MXC_WUT_SetCompare(mxc_wut_regs_t *wut, uint32_t cmp_cnt)
{
@@ -135,12 +147,24 @@ void MXC_WUT_Edge(mxc_wut_regs_t *wut)
MXC_WUT_RevA_Edge((mxc_wut_reva_regs_t *)wut);
}
+/* ************************************************************************** */
+void MXC_WUT_WaitForEdge(mxc_wut_regs_t *wut)
+{
+ MXC_WUT_RevA_Edge((mxc_wut_reva_regs_t *)wut);
+}
+
/* ************************************************************************** */
void MXC_WUT_Store(mxc_wut_regs_t *wut)
{
MXC_WUT_RevA_Store((mxc_wut_reva_regs_t *)wut);
}
+/* ************************************************************************** */
+void MXC_WUT_StoreCount(mxc_wut_regs_t *wut)
+{
+ MXC_WUT_RevA_Store((mxc_wut_reva_regs_t *)wut);
+}
+
/* ************************************************************************** */
void MXC_WUT_RestoreBBClock(mxc_wut_regs_t *wut, uint32_t dbbFreq)
{
@@ -223,7 +247,7 @@ int MXC_WUT_Handler(mxc_wut_regs_t *wut)
mxc_wut_complete_cb_t cbTemp;
/* Clear the interrupt flags */
- MXC_WUT_IntClear(wut);
+ MXC_WUT_ClearFlags(wut);
if (!trimPending) {
return E_NO_ERROR;
diff --git a/Libraries/PeriphDrivers/Source/WUT/wut_me18.c b/Libraries/PeriphDrivers/Source/WUT/wut_me18.c
index 48913670a00..fb0d32e191b 100644
--- a/Libraries/PeriphDrivers/Source/WUT/wut_me18.c
+++ b/Libraries/PeriphDrivers/Source/WUT/wut_me18.c
@@ -49,130 +49,130 @@ static mxc_wut_complete_cb_t cb_async;
/* **** Functions **** */
/* ************************************************************************** */
-void MXC_WUT_Init(mxc_wut_pres_t pres)
+void MXC_WUT_Init(mxc_wut_regs_t *wut, mxc_wut_pres_t pres)
{
#ifndef MSDK_NO_GPIO_CLK_INIT
MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERTCO);
#endif
- MXC_WUT_RevA_Init((mxc_wut_reva_regs_t *)MXC_WUT, (mxc_wut_reva_pres_t)pres);
+ MXC_WUT_RevA_Init((mxc_wut_reva_regs_t *)wut, (mxc_wut_reva_pres_t)pres);
}
/* ************************************************************************** */
-void MXC_WUT_Shutdown(void)
+void MXC_WUT_Shutdown(mxc_wut_regs_t *wut)
{
- MXC_WUT_RevA_Shutdown((mxc_wut_reva_regs_t *)MXC_WUT);
+ MXC_WUT_RevA_Shutdown((mxc_wut_reva_regs_t *)wut);
}
/* ************************************************************************** */
-void MXC_WUT_Enable(void)
+void MXC_WUT_Enable(mxc_wut_regs_t *wut)
{
- MXC_WUT_RevA_Enable((mxc_wut_reva_regs_t *)MXC_WUT);
+ MXC_WUT_RevA_Enable((mxc_wut_reva_regs_t *)wut);
}
/* ************************************************************************** */
-void MXC_WUT_Disable(void)
+void MXC_WUT_Disable(mxc_wut_regs_t *wut)
{
- MXC_WUT_RevA_Disable((mxc_wut_reva_regs_t *)MXC_WUT);
+ MXC_WUT_RevA_Disable((mxc_wut_reva_regs_t *)wut);
}
/* ************************************************************************** */
-void MXC_WUT_Config(const mxc_wut_cfg_t *cfg)
+void MXC_WUT_Config(mxc_wut_regs_t *wut, const mxc_wut_cfg_t *cfg)
{
- MXC_WUT_RevA_Config((mxc_wut_reva_regs_t *)MXC_WUT, (mxc_wut_reva_cfg_t *)cfg);
+ MXC_WUT_RevA_Config((mxc_wut_reva_regs_t *)wut, (mxc_wut_reva_cfg_t *)cfg);
}
/* ************************************************************************** */
-uint32_t MXC_WUT_GetCompare(void)
+uint32_t MXC_WUT_GetCompare(mxc_wut_regs_t *wut)
{
- return MXC_WUT_RevA_GetCompare((mxc_wut_reva_regs_t *)MXC_WUT);
+ return MXC_WUT_RevA_GetCompare((mxc_wut_reva_regs_t *)wut);
}
/* ************************************************************************** */
-uint32_t MXC_WUT_GetCapture(void)
+uint32_t MXC_WUT_GetCapture(mxc_wut_regs_t *wut)
{
- return MXC_WUT_RevA_GetCapture((mxc_wut_reva_regs_t *)MXC_WUT);
+ return MXC_WUT_RevA_GetCapture((mxc_wut_reva_regs_t *)wut);
}
/* ************************************************************************* */
-uint32_t MXC_WUT_GetCount(void)
+uint32_t MXC_WUT_GetCount(mxc_wut_regs_t *wut)
{
- return MXC_WUT_RevA_GetCount((mxc_wut_reva_regs_t *)MXC_WUT);
+ return MXC_WUT_RevA_GetCount((mxc_wut_reva_regs_t *)wut);
}
/* ************************************************************************* */
-void MXC_WUT_IntClear(void)
+void MXC_WUT_ClearFlags(mxc_wut_regs_t *wut)
{
- MXC_WUT_RevA_IntClear((mxc_wut_reva_regs_t *)MXC_WUT);
+ MXC_WUT_RevA_IntClear((mxc_wut_reva_regs_t *)wut);
}
/* ************************************************************************* */
-uint32_t MXC_WUT_IntStatus(void)
+uint32_t MXC_WUT_GetFlags(mxc_wut_regs_t *wut)
{
- return MXC_WUT_RevA_IntStatus((mxc_wut_reva_regs_t *)MXC_WUT);
+ return MXC_WUT_RevA_IntStatus((mxc_wut_reva_regs_t *)wut);
}
/* ************************************************************************* */
-void MXC_WUT_SetCompare(uint32_t cmp_cnt)
+void MXC_WUT_SetCompare(mxc_wut_regs_t *wut, uint32_t cmp_cnt)
{
- MXC_WUT_RevA_SetCompare((mxc_wut_reva_regs_t *)MXC_WUT, cmp_cnt);
+ MXC_WUT_RevA_SetCompare((mxc_wut_reva_regs_t *)wut, cmp_cnt);
}
/* ************************************************************************* */
-void MXC_WUT_SetCount(uint32_t cnt)
+void MXC_WUT_SetCount(mxc_wut_regs_t *wut, uint32_t cnt)
{
- MXC_WUT_RevA_SetCount((mxc_wut_reva_regs_t *)MXC_WUT, cnt);
+ MXC_WUT_RevA_SetCount((mxc_wut_reva_regs_t *)wut, cnt);
}
/* ************************************************************************* */
-int MXC_WUT_GetTicks(uint32_t time, mxc_wut_unit_t units, uint32_t *ticks)
+int MXC_WUT_GetTicks(mxc_wut_regs_t *wut, uint32_t time, mxc_wut_unit_t units, uint32_t *ticks)
{
- return MXC_WUT_RevA_GetTicks((mxc_wut_reva_regs_t *)MXC_WUT, ERTCO_FREQ, time,
+ return MXC_WUT_RevA_GetTicks((mxc_wut_reva_regs_t *)wut, ERTCO_FREQ, time,
(mxc_wut_reva_unit_t)units, ticks);
}
/* ************************************************************************* */
-int MXC_WUT_GetTime(uint32_t ticks, uint32_t *time, mxc_wut_unit_t *units)
+int MXC_WUT_GetTime(mxc_wut_regs_t *wut, uint32_t ticks, uint32_t *time, mxc_wut_unit_t *units)
{
- return MXC_WUT_RevA_GetTime((mxc_wut_reva_regs_t *)MXC_WUT, ERTCO_FREQ, ticks, time,
+ return MXC_WUT_RevA_GetTime((mxc_wut_reva_regs_t *)wut, ERTCO_FREQ, ticks, time,
(mxc_wut_reva_unit_t *)units);
}
/* ************************************************************************** */
-void MXC_WUT_Edge(void)
+void MXC_WUT_WaitForEdge(mxc_wut_regs_t *wut)
{
- MXC_WUT_RevA_Edge((mxc_wut_reva_regs_t *)MXC_WUT);
+ MXC_WUT_RevA_Edge((mxc_wut_reva_regs_t *)wut);
}
/* ************************************************************************** */
-void MXC_WUT_Store(void)
+void MXC_WUT_StoreCount(mxc_wut_regs_t *wut)
{
- MXC_WUT_RevA_Store((mxc_wut_reva_regs_t *)MXC_WUT);
+ MXC_WUT_RevA_Store((mxc_wut_reva_regs_t *)wut);
}
/* ************************************************************************** */
-void MXC_WUT_RestoreBBClock(uint32_t dbbFreq)
+void MXC_WUT_RestoreBBClock(mxc_wut_regs_t *wut, uint32_t dbbFreq)
{
- MXC_WUT_RevA_RestoreBBClock((mxc_wut_reva_regs_t *)MXC_WUT, dbbFreq, ERTCO_FREQ);
+ MXC_WUT_RevA_RestoreBBClock((mxc_wut_reva_regs_t *)wut, dbbFreq, ERTCO_FREQ);
}
/* ************************************************************************** */
-uint32_t MXC_WUT_GetSleepTicks(void)
+uint32_t MXC_WUT_GetSleepTicks(mxc_wut_regs_t *wut)
{
- return MXC_WUT_RevA_GetSleepTicks((mxc_wut_reva_regs_t *)MXC_WUT);
+ return MXC_WUT_RevA_GetSleepTicks((mxc_wut_reva_regs_t *)wut);
}
/* ************************************************************************** */
-void MXC_WUT_Delay_MS(uint32_t waitMs)
+void MXC_WUT_Delay_MS(mxc_wut_regs_t *wut, uint32_t waitMs)
{
- MXC_WUT_RevA_Delay_MS((mxc_wut_reva_regs_t *)MXC_WUT, waitMs, ERTCO_FREQ);
+ MXC_WUT_RevA_Delay_MS((mxc_wut_reva_regs_t *)wut, waitMs, ERTCO_FREQ);
}
/* ************************************************************************** */
-static void MXC_WUT_GetWUTSync(uint32_t *wutCnt, uint32_t *snapshot)
+static void MXC_WUT_GetWUTSync(mxc_wut_regs_t *wut, uint32_t *wutCnt, uint32_t *snapshot)
{
- MXC_WUT_RevA_Edge((mxc_wut_reva_regs_t *)MXC_WUT);
- *wutCnt = MXC_WUT->cnt;
- *snapshot = MXC_WUT->snapshot;
+ MXC_WUT_RevA_Edge((mxc_wut_reva_regs_t *)wut);
+ *wutCnt = wut->cnt;
+ *snapshot = wut->snapshot;
}
/* ************************************************************************** */
@@ -185,24 +185,24 @@ static void MXC_WUT_SetTrim(uint32_t trimValue)
}
/* ************************************************************************** */
-static int MXC_WUT_StarTrim(void)
+static int MXC_WUT_StartTrim(mxc_wut_regs_t *wut)
{
uint32_t wutCnt0, wutCnt1;
uint32_t snapshot0, snapshot1;
uint32_t trimValue;
/* Make sure the WUT is running in compare mode */
- if (!(MXC_WUT->ctrl & MXC_F_WUT_REVA_CTRL_TEN)) {
+ if (!(wut->ctrl & MXC_F_WUT_REVA_CTRL_TEN)) {
return E_UNINITIALIZED;
}
- if ((MXC_WUT->ctrl & MXC_F_WUT_CTRL_TMODE) != MXC_S_WUT_CTRL_TMODE_COMPARE) {
+ if ((wut->ctrl & MXC_F_WUT_CTRL_TMODE) != MXC_S_WUT_CTRL_TMODE_COMPARE) {
return E_UNINITIALIZED;
}
/* Make sure that DBB counter is running */
- MXC_WUT_GetWUTSync(&wutCnt0, &snapshot0);
- MXC_WUT_GetWUTSync(&wutCnt1, &snapshot1);
+ MXC_WUT_GetWUTSync(wut, &wutCnt0, &snapshot0);
+ MXC_WUT_GetWUTSync(wut, &wutCnt1, &snapshot1);
if (snapshot0 == snapshot1) {
return E_UNINITIALIZED;
}
@@ -216,7 +216,7 @@ static int MXC_WUT_StarTrim(void)
bestDiff_async = 0xFFFF;
/* Get the initial snapshot */
- MXC_WUT_GetWUTSync(&wutCnt0_async, &snapshot0_async);
+ MXC_WUT_GetWUTSync(wut, &wutCnt0_async, &snapshot0_async);
trimPending = 1;
@@ -224,7 +224,7 @@ static int MXC_WUT_StarTrim(void)
}
/* ************************************************************************** */
-int MXC_WUT_Handler(void)
+int MXC_WUT_Handler(mxc_wut_regs_t *wut)
{
uint32_t wutCnt1;
uint32_t snapshot1;
@@ -235,14 +235,14 @@ int MXC_WUT_Handler(void)
mxc_wut_complete_cb_t cbTemp;
/* Clear the interrupt flags */
- MXC_WUT_IntClear();
+ MXC_WUT_ClearFlags(wut);
if (!trimPending) {
return E_NO_ERROR;
}
/* Store the snapshot */
- MXC_WUT_GetWUTSync(&wutCnt1, &snapshot1);
+ MXC_WUT_GetWUTSync(wut, &wutCnt1, &snapshot1);
snapTicks = snapshot1 - snapshot0_async;
wutTicks = wutCnt1 - wutCnt0_async;
@@ -316,11 +316,11 @@ int MXC_WUT_Handler(void)
/* Start the next step */
MXC_WUT_SetTrim(trimValue);
- MXC_WUT_GetWUTSync(&wutCnt0_async, &snapshot0_async);
+ MXC_WUT_GetWUTSync(wut, &wutCnt0_async, &snapshot0_async);
if (cb_async != NULL) {
/* Prime the compare interrupt */
- MXC_WUT->cmp = MXC_WUT->cnt + WUT_TRIM_TICKS - 1;
+ wut->cmp = wut->cnt + WUT_TRIM_TICKS - 1;
}
/* Return E_BUSY to indicate the trim procedure is still running */
@@ -328,7 +328,7 @@ int MXC_WUT_Handler(void)
}
/* ************************************************************************** */
-int MXC_WUT_TrimCrystal(void)
+int MXC_WUT_TrimCrystal(mxc_wut_regs_t *wut)
{
int err, i;
@@ -336,21 +336,21 @@ int MXC_WUT_TrimCrystal(void)
cb_async = NULL;
/* Start the trim procedure */
- err = MXC_WUT_StarTrim();
+ err = MXC_WUT_StartTrim(wut);
if (err != E_NO_ERROR) {
return err;
}
do {
for (i = 0; i < (WUT_TRIM_TICKS - 1); i++) {
- MXC_WUT_RevA_Edge((mxc_wut_reva_regs_t *)MXC_WUT);
+ MXC_WUT_RevA_Edge((mxc_wut_reva_regs_t *)wut);
}
- } while (MXC_WUT_Handler() != E_NO_ERROR);
+ } while (MXC_WUT_Handler(wut) != E_NO_ERROR);
return E_NO_ERROR;
}
/* ************************************************************************** */
-int MXC_WUT_TrimCrystalAsync(mxc_wut_complete_cb_t cb)
+int MXC_WUT_TrimCrystalAsync(mxc_wut_regs_t *wut, mxc_wut_complete_cb_t cb)
{
int err;
@@ -362,19 +362,19 @@ int MXC_WUT_TrimCrystalAsync(mxc_wut_complete_cb_t cb)
cb_async = cb;
/* Start the trim procedure */
- err = MXC_WUT_StarTrim();
+ err = MXC_WUT_StartTrim(wut);
if (err != E_NO_ERROR) {
return err;
}
/* Prime the compare interrupt */
- MXC_WUT->cmp = MXC_WUT->cnt + WUT_TRIM_TICKS - 1;
+ wut->cmp = wut->cnt + WUT_TRIM_TICKS - 1;
return E_NO_ERROR;
}
/* ************************************************************************** */
-int MXC_WUT_TrimPending(void)
+int MXC_WUT_TrimPending(mxc_wut_regs_t *wut)
{
if (trimPending) {
return E_BUSY;
diff --git a/Libraries/PeriphDrivers/Source/WUT/wut_me30.c b/Libraries/PeriphDrivers/Source/WUT/wut_me30.c
index 2d51c4d2f8f..bffcb509d68 100644
--- a/Libraries/PeriphDrivers/Source/WUT/wut_me30.c
+++ b/Libraries/PeriphDrivers/Source/WUT/wut_me30.c
@@ -96,12 +96,24 @@ void MXC_WUT_IntClear(mxc_wut_regs_t *wut)
MXC_WUT_RevA_IntClear((mxc_wut_reva_regs_t *)wut);
}
+/* ************************************************************************* */
+void MXC_WUT_ClearFlags(mxc_wut_regs_t *wut)
+{
+ MXC_WUT_RevA_IntClear((mxc_wut_reva_regs_t *)wut);
+}
+
/* ************************************************************************* */
uint32_t MXC_WUT_IntStatus(mxc_wut_regs_t *wut)
{
return MXC_WUT_RevA_IntStatus((mxc_wut_reva_regs_t *)wut);
}
+/* ************************************************************************* */
+uint32_t MXC_WUT_GetFlags(mxc_wut_regs_t *wut)
+{
+ return MXC_WUT_RevA_IntStatus((mxc_wut_reva_regs_t *)wut);
+}
+
/* ************************************************************************* */
void MXC_WUT_SetCompare(mxc_wut_regs_t *wut, uint32_t cmp_cnt)
{
@@ -133,12 +145,24 @@ void MXC_WUT_Edge(mxc_wut_regs_t *wut)
MXC_WUT_RevA_Edge((mxc_wut_reva_regs_t *)wut);
}
+/* ************************************************************************** */
+void MXC_WUT_WaitForEdge(mxc_wut_regs_t *wut)
+{
+ MXC_WUT_RevA_Edge((mxc_wut_reva_regs_t *)wut);
+}
+
/* ************************************************************************** */
void MXC_WUT_Store(mxc_wut_regs_t *wut)
{
MXC_WUT_RevA_Store((mxc_wut_reva_regs_t *)wut);
}
+/* ************************************************************************** */
+void MXC_WUT_StoreCount(mxc_wut_regs_t *wut)
+{
+ MXC_WUT_RevA_Store((mxc_wut_reva_regs_t *)wut);
+}
+
/* ************************************************************************** */
void MXC_WUT_RestoreBBClock(mxc_wut_regs_t *wut, uint32_t dbbFreq)
{
@@ -223,7 +247,7 @@ int MXC_WUT_Handler(mxc_wut_regs_t *wut)
mxc_wut_complete_cb_t cbTemp;
/* Clear the interrupt flags */
- MXC_WUT_IntClear(wut);
+ MXC_WUT_ClearFlags(wut);
if (!trimPending) {
return E_NO_ERROR;
diff --git a/Libraries/zephyr/MAX/CMakeLists.txt b/Libraries/zephyr/MAX/CMakeLists.txt
index 717feffc148..4c00577044f 100644
--- a/Libraries/zephyr/MAX/CMakeLists.txt
+++ b/Libraries/zephyr/MAX/CMakeLists.txt
@@ -46,6 +46,24 @@ zephyr_include_directories(
${MSDK_PERIPH_INC_DIR}
)
+if (CONFIG_UDC_MAX32)
+ zephyr_compile_definitions(
+ -DUSE_ZEPHYR_USB_STACK=1
+ )
+
+ set(MSDK_MAXUSB_DIR ${MSDK_LIBRARY_DIR}/MAXUSB)
+
+ zephyr_include_directories(
+ ${MSDK_MAXUSB_DIR}/include/core
+ ${MSDK_MAXUSB_DIR}/include/core/musbhsfc
+ )
+
+ zephyr_library_sources(
+ ${MSDK_MAXUSB_DIR}/src/core/usb_event.c
+ ${MSDK_MAXUSB_DIR}/src/core/musbhsfc/usb.c
+ )
+endif()
+
add_subdirectory_ifdef(CONFIG_SOC_MAX32520 Source/MAX32520)
add_subdirectory_ifdef(CONFIG_SOC_MAX32570 Source/MAX32570)
add_subdirectory_ifdef(CONFIG_SOC_MAX32572 Source/MAX32572)
diff --git a/Libraries/zephyr/MAX/Include/wrap_max32_adc.h b/Libraries/zephyr/MAX/Include/wrap_max32_adc.h
index acd90ab080c..e8765d26ed8 100644
--- a/Libraries/zephyr/MAX/Include/wrap_max32_adc.h
+++ b/Libraries/zephyr/MAX/Include/wrap_max32_adc.h
@@ -53,8 +53,8 @@ typedef enum {
/*
* MAX32655, MAX32665, MAX32666 related mapping
*/
-#if defined(CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666) || \
- (CONFIG_SOC_MAX32680)
+#if defined(CONFIG_SOC_MAX32655) || defined(CONFIG_SOC_MAX32665) || \
+ defined(CONFIG_SOC_MAX32666) || defined(CONFIG_SOC_MAX32680)
#define WRAP_MXC_F_ADC_CONV_DONE_IE MXC_F_ADC_INTR_DONE_IE
#define WRAP_MXC_F_ADC_CONV_DONE_IF MXC_F_ADC_INTR_DONE_IF
@@ -153,8 +153,8 @@ static inline void Wrap_MXC_ADC_GetData(uint16_t **outdata)
/*
* MAX32690, related mapping
*/
-#elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || \
- (CONFIG_SOC_MAX78002)
+#elif defined(CONFIG_SOC_MAX32690) || defined(CONFIG_SOC_MAX32672) || \
+ defined(CONFIG_SOC_MAX32662) || defined(CONFIG_SOC_MAX78002)
#define WRAP_MXC_F_ADC_CONV_DONE_IE MXC_F_ADC_INTEN_SEQ_DONE
#define WRAP_MXC_F_ADC_CONV_DONE_IF MXC_F_ADC_INTFL_SEQ_DONE
diff --git a/Libraries/zephyr/MAX/Include/wrap_max32_dma.h b/Libraries/zephyr/MAX/Include/wrap_max32_dma.h
index fe228dc3d96..5690cedc9b5 100644
--- a/Libraries/zephyr/MAX/Include/wrap_max32_dma.h
+++ b/Libraries/zephyr/MAX/Include/wrap_max32_dma.h
@@ -26,7 +26,7 @@
extern "C" {
#endif
-#if defined(CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666)
+#if defined(CONFIG_SOC_MAX32665) || defined(CONFIG_SOC_MAX32666)
#define ADI_MAX32_DMA_CTRL_DIS_IE MXC_F_DMA_CFG_CHDIEN
#define ADI_MAX32_DMA_CTRL_CTZIEN MXC_F_DMA_CFG_CTZIEN
@@ -50,7 +50,7 @@ extern "C" {
static inline int MXC_DMA_GetIntFlags(mxc_dma_regs_t *dma)
{
-#if defined(CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666)
+#if defined(CONFIG_SOC_MAX32665) || defined(CONFIG_SOC_MAX32666)
return dma->intr;
#else
return dma->intfl;
@@ -59,7 +59,7 @@ static inline int MXC_DMA_GetIntFlags(mxc_dma_regs_t *dma)
static inline int Wrap_MXC_DMA_Init(mxc_dma_regs_t *dma)
{
-#if defined(CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666)
+#if defined(CONFIG_SOC_MAX32657) || defined(CONFIG_SOC_MAX32665) || defined(CONFIG_SOC_MAX32666)
return MXC_DMA_Init(dma);
#else
(void)dma;
@@ -69,7 +69,7 @@ static inline int Wrap_MXC_DMA_Init(mxc_dma_regs_t *dma)
static inline void Wrap_MXC_DMA_DeInit(mxc_dma_regs_t *dma)
{
-#if defined(CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666)
+#if defined(CONFIG_SOC_MAX32657) || defined(CONFIG_SOC_MAX32665) || defined(CONFIG_SOC_MAX32666)
MXC_DMA_DeInit(dma);
#else
(void)dma;
@@ -79,7 +79,7 @@ static inline void Wrap_MXC_DMA_DeInit(mxc_dma_regs_t *dma)
static inline int Wrap_MXC_DMA_AcquireChannel(mxc_dma_regs_t *dma)
{
-#if defined(CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666)
+#if defined(CONFIG_SOC_MAX32657) || defined(CONFIG_SOC_MAX32665) || defined(CONFIG_SOC_MAX32666)
return MXC_DMA_AcquireChannel(dma);
#else
(void)dma;
@@ -89,7 +89,7 @@ static inline int Wrap_MXC_DMA_AcquireChannel(mxc_dma_regs_t *dma)
static inline void Wrap_MXC_DMA_Handler(mxc_dma_regs_t *dma)
{
-#if defined(CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666)
+#if defined(CONFIG_SOC_MAX32657) || defined(CONFIG_SOC_MAX32665) || defined(CONFIG_SOC_MAX32666)
MXC_DMA_Handler(dma);
#else
(void)dma;
@@ -100,7 +100,7 @@ static inline void Wrap_MXC_DMA_Handler(mxc_dma_regs_t *dma)
static inline int Wrap_MXC_DMA_MemCpy(mxc_dma_regs_t *dma, void *dest, void *src, int len,
mxc_dma_complete_cb_t callback)
{
-#if defined(CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666)
+#if defined(CONFIG_SOC_MAX32657) || defined(CONFIG_SOC_MAX32665) || defined(CONFIG_SOC_MAX32666)
return MXC_DMA_MemCpy(dma, dest, src, len, callback);
#else
(void)dma;
@@ -112,7 +112,7 @@ static inline int Wrap_MXC_DMA_DoTransfer(mxc_dma_regs_t *dma, mxc_dma_config_t
mxc_dma_srcdst_t firstSrcDst,
mxc_dma_trans_chain_t callback)
{
-#if defined(CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666)
+#if defined(CONFIG_SOC_MAX32657) || defined(CONFIG_SOC_MAX32665) || defined(CONFIG_SOC_MAX32666)
return MXC_DMA_DoTransfer(dma, config, firstSrcDst, callback);
#else
(void)dma;
diff --git a/Libraries/zephyr/MAX/Include/wrap_max32_i2c.h b/Libraries/zephyr/MAX/Include/wrap_max32_i2c.h
index b3a23108489..f6d56d4c394 100644
--- a/Libraries/zephyr/MAX/Include/wrap_max32_i2c.h
+++ b/Libraries/zephyr/MAX/Include/wrap_max32_i2c.h
@@ -29,7 +29,7 @@ extern "C" {
/*
* MAX32665, MAX32666 related mapping
*/
-#if defined(CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666)
+#if defined(CONFIG_SOC_MAX32665) || defined(CONFIG_SOC_MAX32666)
/*
* Control register bits
@@ -128,9 +128,10 @@ static inline void Wrap_MXC_I2C_Stop(mxc_i2c_regs_t *i2c)
/*
* MAX32690, MAX32655 related mapping
*/
-#elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \
- (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \
- (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX78002)
+#elif defined(CONFIG_SOC_MAX32690) || defined(CONFIG_SOC_MAX32655) || \
+ defined(CONFIG_SOC_MAX32670) || defined(CONFIG_SOC_MAX32672) || \
+ defined(CONFIG_SOC_MAX32662) || defined(CONFIG_SOC_MAX32675) || \
+ defined(CONFIG_SOC_MAX32680) || defined(CONFIG_SOC_MAX32657) || defined(CONFIG_SOC_MAX78002)
/*
* Control register bits
*/
diff --git a/Libraries/zephyr/MAX/Include/wrap_max32_lp.h b/Libraries/zephyr/MAX/Include/wrap_max32_lp.h
index 2f3281f31eb..98b73d8e2d2 100644
--- a/Libraries/zephyr/MAX/Include/wrap_max32_lp.h
+++ b/Libraries/zephyr/MAX/Include/wrap_max32_lp.h
@@ -29,8 +29,9 @@ extern "C" {
/*
* MAX32665, MAX32666 related mapping
*/
-#if defined(CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666) || (CONFIG_SOC_MAX32670) || \
- (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675)
+#if defined(CONFIG_SOC_MAX32665) || defined(CONFIG_SOC_MAX32666) || \
+ defined(CONFIG_SOC_MAX32670) || defined(CONFIG_SOC_MAX32672) || \
+ defined(CONFIG_SOC_MAX32662) || defined(CONFIG_SOC_MAX32675)
static inline void Wrap_MXC_LP_EnterLowPowerMode(void)
{
@@ -55,8 +56,8 @@ static inline void Wrap_MXC_LP_EnterPowerDownMode(void)
/*
* MAX32690, MAX32655 related mapping
*/
-#elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32680) || \
- (CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX78002)
+#elif defined(CONFIG_SOC_MAX32690) || defined(CONFIG_SOC_MAX32655) || \
+ defined(CONFIG_SOC_MAX32680) || defined(CONFIG_SOC_MAX32657) || defined(CONFIG_SOC_MAX78002)
static inline void Wrap_MXC_LP_EnterLowPowerMode(void)
{
diff --git a/Libraries/zephyr/MAX/Include/wrap_max32_owm.h b/Libraries/zephyr/MAX/Include/wrap_max32_owm.h
index 21d5528e443..fdcae50d04b 100644
--- a/Libraries/zephyr/MAX/Include/wrap_max32_owm.h
+++ b/Libraries/zephyr/MAX/Include/wrap_max32_owm.h
@@ -29,7 +29,7 @@ extern "C" {
/*
* MAX32665, MAX32666 related mapping
*/
-#if defined(CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666)
+#if defined(CONFIG_SOC_MAX32665) || defined(CONFIG_SOC_MAX32666)
static inline int Wrap_MXC_OWM_Init(const mxc_owm_cfg_t *cfg)
{
@@ -40,8 +40,8 @@ static inline int Wrap_MXC_OWM_Init(const mxc_owm_cfg_t *cfg)
/*
* MAX32690, MAX32655 related mapping
*/
-#elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32680) || \
- (CONFIG_SOC_MAX78002)
+#elif defined(CONFIG_SOC_MAX32690) || defined(CONFIG_SOC_MAX32655) || \
+ defined(CONFIG_SOC_MAX32680) || defined(CONFIG_SOC_MAX78002)
static inline int Wrap_MXC_OWM_Init(const mxc_owm_cfg_t *cfg)
{
diff --git a/Libraries/zephyr/MAX/Include/wrap_max32_spi.h b/Libraries/zephyr/MAX/Include/wrap_max32_spi.h
index bf2acbc9d11..ed3c81f0643 100644
--- a/Libraries/zephyr/MAX/Include/wrap_max32_spi.h
+++ b/Libraries/zephyr/MAX/Include/wrap_max32_spi.h
@@ -29,7 +29,7 @@ extern "C" {
/*
* MAX32665, MAX32666 related mapping
*/
-#if defined(CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666)
+#if defined(CONFIG_SOC_MAX32665) || defined(CONFIG_SOC_MAX32666)
#define ADI_MAX32_SPI_CTRL_MASTER_MODE MXC_F_SPI_CTRL0_MASTER
@@ -73,9 +73,10 @@ static inline int Wrap_MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int qua
/*
* MAX32690, MAX32655 related mapping
*/
-#elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \
- (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \
- (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX78002)
+#elif defined(CONFIG_SOC_MAX32690) || defined(CONFIG_SOC_MAX32655) || \
+ defined(CONFIG_SOC_MAX32670) || defined(CONFIG_SOC_MAX32672) || \
+ defined(CONFIG_SOC_MAX32662) || defined(CONFIG_SOC_MAX32675) || \
+ defined(CONFIG_SOC_MAX32680) || defined(CONFIG_SOC_MAX32657) || defined(CONFIG_SOC_MAX78002)
#if defined(CONFIG_SOC_MAX32657)
#define ADI_MAX32_SPI_CTRL_MASTER_MODE MXC_F_SPI_CTRL0_CONT_MODE
#else
@@ -128,7 +129,7 @@ static inline int Wrap_MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int qua
static inline int Wrap_MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed,
int numSlaves, unsigned ssPolarity, unsigned int hz)
{
-#if defined(CONFIG_SOC_MAX32670) || (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32675)
+#if defined(CONFIG_SOC_MAX32670) || defined(CONFIG_SOC_MAX32672) || defined(CONFIG_SOC_MAX32675)
return MXC_SPI_Init(spi, masterMode, quadModeUsed, numSlaves, ssPolarity, hz);
#else
mxc_spi_pins_t tmp; // not used
diff --git a/Libraries/zephyr/MAX/Include/wrap_max32_sys.h b/Libraries/zephyr/MAX/Include/wrap_max32_sys.h
index a1d3d14b9cd..79efddebc7c 100644
--- a/Libraries/zephyr/MAX/Include/wrap_max32_sys.h
+++ b/Libraries/zephyr/MAX/Include/wrap_max32_sys.h
@@ -34,7 +34,7 @@ void max32xx_system_init(void);
/*
* MAX32665, MAX32666 related mapping
*/
-#if defined(CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666)
+#if defined(CONFIG_SOC_MAX32665) || defined(CONFIG_SOC_MAX32666)
#define ADI_MAX32_CLK_IPO MXC_SYS_CLOCK_HIRC96
#define ADI_MAX32_CLK_ERFO MXC_SYS_CLOCK_XTAL32M
@@ -54,9 +54,10 @@ static inline void Wrap_MXC_SYS_SetClockDiv(int div)
/*
* MAX32690, MAX32655 related mapping
*/
-#elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \
- (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \
- (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX78002)
+#elif defined(CONFIG_SOC_MAX32690) || defined(CONFIG_SOC_MAX32655) || \
+ defined(CONFIG_SOC_MAX32670) || defined(CONFIG_SOC_MAX32672) || \
+ defined(CONFIG_SOC_MAX32662) || defined(CONFIG_SOC_MAX32675) || \
+ defined(CONFIG_SOC_MAX32680) || defined(CONFIG_SOC_MAX32657) || defined(CONFIG_SOC_MAX78002)
#define ADI_MAX32_CLK_IPO MXC_SYS_CLOCK_IPO
#if defined(CONFIG_SOC_MAX78002)
@@ -69,8 +70,8 @@ static inline void Wrap_MXC_SYS_SetClockDiv(int div)
#define ADI_MAX32_CLK_INRO MXC_SYS_CLOCK_INRO
#define ADI_MAX32_CLK_ERTCO MXC_SYS_CLOCK_ERTCO
#define ADI_MAX32_CLK_EXTCLK MXC_SYS_CLOCK_EXTCLK
-#if !(defined(CONFIG_SOC_MAX32670) || (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || \
- (CONFIG_SOC_MAX32675))
+#if !(defined(CONFIG_SOC_MAX32670) || defined(CONFIG_SOC_MAX32672) || \
+ defined(CONFIG_SOC_MAX32662) || defined(CONFIG_SOC_MAX32675))
#define ADI_MAX32_CLK_ISO MXC_SYS_CLOCK_ISO
#endif
diff --git a/Libraries/zephyr/MAX/Include/wrap_max32_tmr.h b/Libraries/zephyr/MAX/Include/wrap_max32_tmr.h
index 310e90edfac..884aa2bf90c 100644
--- a/Libraries/zephyr/MAX/Include/wrap_max32_tmr.h
+++ b/Libraries/zephyr/MAX/Include/wrap_max32_tmr.h
@@ -39,7 +39,7 @@ typedef struct {
/*
* MAX32665, MAX32666 related mapping
*/
-#if defined(CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666)
+#if defined(CONFIG_SOC_MAX32665) || defined(CONFIG_SOC_MAX32666)
/* All timers are 32bits */
#define WRAP_MXC_IS_32B_TIMER(idx) (1)
@@ -101,12 +101,13 @@ int Wrap_MXC_TMR_GetPendingInt(mxc_tmr_regs_t *tmr)
/*
* MAX32690, MAX32655 related mapping
*/
-#elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \
- (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \
- (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX78002)
+#elif defined(CONFIG_SOC_MAX32690) || defined(CONFIG_SOC_MAX32655) || \
+ defined(CONFIG_SOC_MAX32670) || defined(CONFIG_SOC_MAX32672) || \
+ defined(CONFIG_SOC_MAX32662) || defined(CONFIG_SOC_MAX32675) || \
+ defined(CONFIG_SOC_MAX32680) || defined(CONFIG_SOC_MAX32657) || defined(CONFIG_SOC_MAX78002)
-#if defined(CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32675) || (CONFIG_SOC_MAX32657) || \
- (CONFIG_SOC_MAX32670)
+#if defined(CONFIG_SOC_MAX32672) || defined(CONFIG_SOC_MAX32675) || \
+ defined(CONFIG_SOC_MAX32657) || defined(CONFIG_SOC_MAX32670)
/* All timers are 32bits */
#define WRAP_MXC_IS_32B_TIMER(idx) (1)
#elif defined(CONFIG_SOC_MAX32662)
@@ -151,8 +152,8 @@ static inline int Wrap_MXC_TMR_GetClockIndex(int z_clock)
return MXC_TMR_32K_CLK;
case 5: //ADI_MAX32_PRPH_CLK_SRC_INRO
return MXC_TMR_INRO_CLK;
-#if defined(CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32690) || \
- (CONFIG_SOC_MAX78002)
+#if defined(CONFIG_SOC_MAX32655) || defined(CONFIG_SOC_MAX32680) || \
+ defined(CONFIG_SOC_MAX32690) || defined(CONFIG_SOC_MAX78002)
case 6: //ADI_MAX32_PRPH_CLK_SRC_ISO
return MXC_TMR_ISO_CLK;
#endif
diff --git a/Libraries/zephyr/MAX/Include/wrap_max32_trng.h b/Libraries/zephyr/MAX/Include/wrap_max32_trng.h
index b9f3a72e3ac..794c6faaeed 100644
--- a/Libraries/zephyr/MAX/Include/wrap_max32_trng.h
+++ b/Libraries/zephyr/MAX/Include/wrap_max32_trng.h
@@ -29,7 +29,7 @@ extern "C" {
/*
* MAX32665, MAX32666 related mapping
*/
-#if defined(CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666)
+#if defined(CONFIG_SOC_MAX32665) || defined(CONFIG_SOC_MAX32666)
static inline int Wrap_MXC_TRNG_RandomInt_NonBlocking(uint32_t *data)
{
@@ -44,9 +44,10 @@ static inline int Wrap_MXC_TRNG_RandomInt_NonBlocking(uint32_t *data)
/*
* MAX32690, MAX32655 related mapping
*/
-#elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \
- (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \
- (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX78002)
+#elif defined(CONFIG_SOC_MAX32690) || defined(CONFIG_SOC_MAX32655) || \
+ defined(CONFIG_SOC_MAX32670) || defined(CONFIG_SOC_MAX32672) || \
+ defined(CONFIG_SOC_MAX32662) || defined(CONFIG_SOC_MAX32675) || \
+ defined(CONFIG_SOC_MAX32680) || defined(CONFIG_SOC_MAX32657) || defined(CONFIG_SOC_MAX78002)
static inline int Wrap_MXC_TRNG_RandomInt_NonBlocking(uint32_t *data)
{
diff --git a/Libraries/zephyr/MAX/Include/wrap_max32_uart.h b/Libraries/zephyr/MAX/Include/wrap_max32_uart.h
index 713ec47a166..08b3abf8aca 100644
--- a/Libraries/zephyr/MAX/Include/wrap_max32_uart.h
+++ b/Libraries/zephyr/MAX/Include/wrap_max32_uart.h
@@ -26,7 +26,7 @@
extern "C" {
#endif
-#if defined(CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666)
+#if defined(CONFIG_SOC_MAX32665) || defined(CONFIG_SOC_MAX32666)
// status flags
#define ADI_MAX32_UART_RX_EMPTY MXC_F_UART_STATUS_RX_EMPTY
#define ADI_MAX32_UART_TX_EMPTY MXC_F_UART_STATUS_TX_EMPTY
@@ -117,14 +117,15 @@ static inline void Wrap_MXC_UART_DisableRxDMA(mxc_uart_regs_t *uart)
/*
* MAX32690, MAX32655 related mapping
*/
-#elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \
- (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \
- (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX78002)
+#elif defined(CONFIG_SOC_MAX32690) || defined(CONFIG_SOC_MAX32655) || \
+ defined(CONFIG_SOC_MAX32670) || defined(CONFIG_SOC_MAX32672) || \
+ defined(CONFIG_SOC_MAX32662) || defined(CONFIG_SOC_MAX32675) || \
+ defined(CONFIG_SOC_MAX32680) || defined(CONFIG_SOC_MAX32657) || defined(CONFIG_SOC_MAX78002)
// status flags
#define ADI_MAX32_UART_RX_EMPTY MXC_F_UART_STATUS_RX_EM
#define ADI_MAX32_UART_TX_EMPTY MXC_F_UART_STATUS_TX_EM
-#if defined(CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32657)
+#if defined(CONFIG_SOC_MAX32662) || defined(CONFIG_SOC_MAX32657)
// error flags
#define ADI_MAX32_UART_ERROR_OVERRUN MXC_F_UART_INTFL_RX_OV
#define ADI_MAX32_UART_ERROR_PARITY MXC_F_UART_INTFL_RX_PAR
@@ -215,11 +216,11 @@ static inline void Wrap_MXC_UART_DisableRxDMA(mxc_uart_regs_t *uart)
uart->dma &= ~MXC_F_UART_DMA_RX_EN;
}
-#endif // defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655)
+#endif // defined(CONFIG_SOC_MAX32690) || defined(CONFIG_SOC_MAX32655)
static inline unsigned int Wrap_MXC_UART_GetRegINTEN(mxc_uart_regs_t *uart)
{
-#if defined(CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32657)
+#if defined(CONFIG_SOC_MAX32662) || defined(CONFIG_SOC_MAX32657)
return uart->inten;
#else
return uart->int_en;
diff --git a/Libraries/zephyr/MAX/Include/wrap_max32_wdt.h b/Libraries/zephyr/MAX/Include/wrap_max32_wdt.h
index 07823afffac..7c0f8f863e1 100644
--- a/Libraries/zephyr/MAX/Include/wrap_max32_wdt.h
+++ b/Libraries/zephyr/MAX/Include/wrap_max32_wdt.h
@@ -37,7 +37,7 @@ typedef struct {
/*
* MAX32665, MAX32666 related mapping
*/
-#if defined(CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666)
+#if defined(CONFIG_SOC_MAX32665) || defined(CONFIG_SOC_MAX32666)
#define WRAP_MXC_F_WDT_CTRL_EN MXC_F_WDT_CTRL_WDT_EN
@@ -83,9 +83,10 @@ static inline int Wrap_MXC_WDT_SelectClockSource(mxc_wdt_regs_t *wdt, uint32_t c
/*
* MAX32690, MAX32655 related mapping
*/
-#elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \
- (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \
- (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX78002)
+#elif defined(CONFIG_SOC_MAX32690) || defined(CONFIG_SOC_MAX32655) || \
+ defined(CONFIG_SOC_MAX32670) || defined(CONFIG_SOC_MAX32672) || \
+ defined(CONFIG_SOC_MAX32662) || defined(CONFIG_SOC_MAX32675) || \
+ defined(CONFIG_SOC_MAX32680) || defined(CONFIG_SOC_MAX32657) || defined(CONFIG_SOC_MAX78002)
#define WRAP_MXC_F_WDT_CTRL_EN MXC_F_WDT_CTRL_EN
@@ -138,7 +139,7 @@ static inline int Wrap_MXC_WDT_SelectClockSource(mxc_wdt_regs_t *wdt, uint32_t c
clk_src = MXC_WDT_INRO_CLK;
#endif
break;
-#if !(defined(CONFIG_SOC_MAX32675) || (CONFIG_SOC_MAX32680))
+#if !(defined(CONFIG_SOC_MAX32675) || defined(CONFIG_SOC_MAX32680))
case 4: // ADI_MAX32_PRPH_CLK_SRC_ERTCO
clk_src = MXC_WDT_ERTCO_CLK;
break;
diff --git a/Libraries/zephyr/MAX/Include/wrap_max32xxx.h b/Libraries/zephyr/MAX/Include/wrap_max32xxx.h
index a8baaea0eab..34522e12d24 100644
--- a/Libraries/zephyr/MAX/Include/wrap_max32xxx.h
+++ b/Libraries/zephyr/MAX/Include/wrap_max32xxx.h
@@ -36,7 +36,7 @@ extern "C" {
#elif defined(CONFIG_SOC_MAX32655)
#include
#elif defined(CONFIG_SOC_MAX32660)
-#include
+#include
#elif defined(CONFIG_SOC_MAX32662)
#include
#elif defined(CONFIG_SOC_MAX32665)
diff --git a/Libraries/zephyr/MAX/Source/MAX32655/CMakeLists.txt b/Libraries/zephyr/MAX/Source/MAX32655/CMakeLists.txt
index 3dcf1822f32..f8362fddee9 100644
--- a/Libraries/zephyr/MAX/Source/MAX32655/CMakeLists.txt
+++ b/Libraries/zephyr/MAX/Source/MAX32655/CMakeLists.txt
@@ -132,7 +132,7 @@ zephyr_library_sources(
)
endif()
-if (CONFIG_SOC_FLASH_MAX32)
+if (CONFIG_SOC_FLASH_MAX32 OR CONFIG_HWINFO_MAX32)
zephyr_library_sources(
${MSDK_PERIPH_SRC_DIR}/FLC/flc_common.c
${MSDK_PERIPH_SRC_DIR}/FLC/flc_me17.c
@@ -176,7 +176,7 @@ zephyr_library_sources(
)
endif()
-if (CONFIG_CRYPTO_MAX32 OR CONFIG_BT)
+if (CONFIG_CRYPTO_MAX32 OR CONFIG_BT OR CONFIG_HWINFO_MAX32)
zephyr_library_sources(
${MSDK_PERIPH_SRC_DIR}/AES/aes_me17.c
${MSDK_PERIPH_SRC_DIR}/AES/aes_revb.c
diff --git a/Libraries/zephyr/MAX/Source/MAX32657/CMakeLists.txt b/Libraries/zephyr/MAX/Source/MAX32657/CMakeLists.txt
index c037d8a699f..13d76e95a0b 100644
--- a/Libraries/zephyr/MAX/Source/MAX32657/CMakeLists.txt
+++ b/Libraries/zephyr/MAX/Source/MAX32657/CMakeLists.txt
@@ -119,7 +119,7 @@ zephyr_library_sources(
)
endif()
-if (CONFIG_SOC_FLASH_MAX32)
+if (CONFIG_SOC_FLASH_MAX32 OR CONFIG_HWINFO_MAX32)
zephyr_library_sources(
${MSDK_PERIPH_SRC_DIR}/FLC/flc_common.c
${MSDK_PERIPH_SRC_DIR}/FLC/flc_me30.c
@@ -142,7 +142,7 @@ zephyr_library_sources(
)
endif()
-if (CONFIG_CRYPTO_MAX32 OR CONFIG_BT)
+if (CONFIG_CRYPTO_MAX32 OR CONFIG_BT OR CONFIG_HWINFO_MAX32)
zephyr_library_sources(
${MSDK_PERIPH_SRC_DIR}/AES/aes_me30.c
${MSDK_PERIPH_SRC_DIR}/AES/aes_revb.c
diff --git a/Libraries/zephyr/MAX/Source/MAX32662/CMakeLists.txt b/Libraries/zephyr/MAX/Source/MAX32662/CMakeLists.txt
index 11214a29304..49b168a68bb 100644
--- a/Libraries/zephyr/MAX/Source/MAX32662/CMakeLists.txt
+++ b/Libraries/zephyr/MAX/Source/MAX32662/CMakeLists.txt
@@ -129,7 +129,7 @@ zephyr_library_sources(
)
endif()
-if (CONFIG_SOC_FLASH_MAX32)
+if (CONFIG_SOC_FLASH_MAX32 OR CONFIG_HWINFO_MAX32)
zephyr_library_sources(
${MSDK_PERIPH_SRC_DIR}/FLC/flc_common.c
${MSDK_PERIPH_SRC_DIR}/FLC/flc_me12.c
@@ -152,7 +152,7 @@ zephyr_library_sources(
)
endif()
-if (CONFIG_CRYPTO_MAX32)
+if (CONFIG_CRYPTO_MAX32 OR CONFIG_HWINFO_MAX32)
zephyr_library_sources(
${MSDK_PERIPH_SRC_DIR}/AES/aes_me12.c
${MSDK_PERIPH_SRC_DIR}/AES/aes_revb.c
diff --git a/Libraries/zephyr/MAX/Source/MAX32665/CMakeLists.txt b/Libraries/zephyr/MAX/Source/MAX32665/CMakeLists.txt
index db5517ccd74..cea33cc479e 100644
--- a/Libraries/zephyr/MAX/Source/MAX32665/CMakeLists.txt
+++ b/Libraries/zephyr/MAX/Source/MAX32665/CMakeLists.txt
@@ -153,7 +153,7 @@ zephyr_library_sources(
)
endif()
-if (CONFIG_SOC_FLASH_MAX32)
+if (CONFIG_SOC_FLASH_MAX32 OR CONFIG_HWINFO_MAX32)
zephyr_library_sources(
${MSDK_PERIPH_SRC_DIR}/FLC/flc_common.c
${MSDK_PERIPH_SRC_DIR}/FLC/flc_me14.c
diff --git a/Libraries/zephyr/MAX/Source/MAX32670/CMakeLists.txt b/Libraries/zephyr/MAX/Source/MAX32670/CMakeLists.txt
index 398df229b0c..940d130133e 100644
--- a/Libraries/zephyr/MAX/Source/MAX32670/CMakeLists.txt
+++ b/Libraries/zephyr/MAX/Source/MAX32670/CMakeLists.txt
@@ -23,6 +23,7 @@ if(NOT TARGET_REV)
endif()
zephyr_include_directories(
+ ${MSDK_PERIPH_SRC_DIR}/AES
${MSDK_PERIPH_SRC_DIR}/DMA
${MSDK_PERIPH_SRC_DIR}/FLC
${MSDK_PERIPH_SRC_DIR}/GPIO
@@ -105,7 +106,7 @@ zephyr_library_sources(
)
endif()
-if (CONFIG_SOC_FLASH_MAX32)
+if (CONFIG_SOC_FLASH_MAX32 OR CONFIG_HWINFO_MAX32)
zephyr_library_sources(
${MSDK_PERIPH_SRC_DIR}/FLC/flc_common.c
${MSDK_PERIPH_SRC_DIR}/FLC/flc_me15.c
@@ -121,9 +122,16 @@ zephyr_library_sources(
)
endif()
-if (CONFIG_ENTROPY_MAX32_TRNG)
+if (CONFIG_ENTROPY_MAX32_TRNG OR CONFIG_HWINFO_MAX32)
zephyr_library_sources(
${MSDK_PERIPH_SRC_DIR}/TRNG/trng_me15.c
${MSDK_PERIPH_SRC_DIR}/TRNG/trng_revb.c
)
endif()
+
+if (CONFIG_HWINFO_MAX32)
+zephyr_library_sources(
+ ${MSDK_PERIPH_SRC_DIR}/AES/aes_me15.c
+ ${MSDK_PERIPH_SRC_DIR}/AES/aes_revb.c
+)
+endif()
diff --git a/Libraries/zephyr/MAX/Source/MAX32672/CMakeLists.txt b/Libraries/zephyr/MAX/Source/MAX32672/CMakeLists.txt
index 96cee524cb4..a0a9e3eddce 100644
--- a/Libraries/zephyr/MAX/Source/MAX32672/CMakeLists.txt
+++ b/Libraries/zephyr/MAX/Source/MAX32672/CMakeLists.txt
@@ -126,7 +126,7 @@ zephyr_library_sources(
)
endif()
-if (CONFIG_SOC_FLASH_MAX32)
+if (CONFIG_SOC_FLASH_MAX32 OR CONFIG_HWINFO_MAX32)
zephyr_library_sources(
${MSDK_PERIPH_SRC_DIR}/FLC/flc_common.c
${MSDK_PERIPH_SRC_DIR}/FLC/flc_me21.c
@@ -149,11 +149,15 @@ zephyr_library_sources(
)
endif()
-if (CONFIG_CRYPTO_MAX32)
+if (CONFIG_CRYPTO_MAX32 OR CONFIG_HWINFO_MAX32)
zephyr_library_sources(
${MSDK_PERIPH_SRC_DIR}/AES/aes_me21.c
${MSDK_PERIPH_SRC_DIR}/AES/aes_revb.c
+)
+endif()
+if (CONFIG_CRYPTO_MAX32)
+zephyr_library_sources(
${MSDK_PERIPH_SRC_DIR}/CTB/ctb_me21.c
${MSDK_PERIPH_SRC_DIR}/CTB/ctb_reva.c
${MSDK_PERIPH_SRC_DIR}/CTB/ctb_common.c
diff --git a/Libraries/zephyr/MAX/Source/MAX32675/CMakeLists.txt b/Libraries/zephyr/MAX/Source/MAX32675/CMakeLists.txt
index 897a758cdb6..94d88e4124a 100644
--- a/Libraries/zephyr/MAX/Source/MAX32675/CMakeLists.txt
+++ b/Libraries/zephyr/MAX/Source/MAX32675/CMakeLists.txt
@@ -120,7 +120,7 @@ zephyr_library_sources(
)
endif()
-if (CONFIG_SOC_FLASH_MAX32)
+if (CONFIG_SOC_FLASH_MAX32 OR CONFIG_HWINFO_MAX32)
zephyr_library_sources(
${MSDK_PERIPH_SRC_DIR}/FLC/flc_common.c
${MSDK_PERIPH_SRC_DIR}/FLC/flc_me15.c
@@ -136,7 +136,7 @@ zephyr_library_sources(
)
endif()
-if (CONFIG_ENTROPY_MAX32_TRNG)
+if (CONFIG_ENTROPY_MAX32_TRNG OR CONFIG_HWINFO_MAX32)
zephyr_library_sources(
${MSDK_PERIPH_SRC_DIR}/TRNG/trng_me15.c
${MSDK_PERIPH_SRC_DIR}/TRNG/trng_revb.c
diff --git a/Libraries/zephyr/MAX/Source/MAX32680/CMakeLists.txt b/Libraries/zephyr/MAX/Source/MAX32680/CMakeLists.txt
index 03458b6a9e8..b4fe6f283e8 100644
--- a/Libraries/zephyr/MAX/Source/MAX32680/CMakeLists.txt
+++ b/Libraries/zephyr/MAX/Source/MAX32680/CMakeLists.txt
@@ -135,7 +135,7 @@ zephyr_library_sources(
)
endif()
-if (CONFIG_SOC_FLASH_MAX32)
+if (CONFIG_SOC_FLASH_MAX32 OR CONFIG_HWINFO_MAX32)
zephyr_library_sources(
${MSDK_PERIPH_SRC_DIR}/FLC/flc_common.c
${MSDK_PERIPH_SRC_DIR}/FLC/flc_me17.c
@@ -179,11 +179,15 @@ zephyr_library_sources(
)
endif()
-if (CONFIG_CRYPTO_MAX32)
+if (CONFIG_CRYPTO_MAX32 OR CONFIG_HWINFO_MAX32)
zephyr_library_sources(
${MSDK_PERIPH_SRC_DIR}/AES/aes_me17.c
${MSDK_PERIPH_SRC_DIR}/AES/aes_revb.c
+)
+endif()
+if (CONFIG_CRYPTO_MAX32)
+zephyr_library_sources(
${MSDK_PERIPH_SRC_DIR}/CRC/crc_me17.c
${MSDK_PERIPH_SRC_DIR}/CRC/crc_reva.c
)
diff --git a/Libraries/zephyr/MAX/Source/MAX32690/CMakeLists.txt b/Libraries/zephyr/MAX/Source/MAX32690/CMakeLists.txt
index 53afa9fe036..4cb6e303060 100644
--- a/Libraries/zephyr/MAX/Source/MAX32690/CMakeLists.txt
+++ b/Libraries/zephyr/MAX/Source/MAX32690/CMakeLists.txt
@@ -144,7 +144,7 @@ zephyr_library_sources(
)
endif()
-if (CONFIG_SOC_FLASH_MAX32)
+if (CONFIG_SOC_FLASH_MAX32 OR CONFIG_HWINFO_MAX32)
zephyr_library_sources(
${MSDK_PERIPH_SRC_DIR}/FLC/flc_common.c
${MSDK_PERIPH_SRC_DIR}/FLC/flc_me18.c
@@ -188,7 +188,7 @@ zephyr_library_sources(
)
endif()
-if (CONFIG_CRYPTO_MAX32)
+if (CONFIG_CRYPTO_MAX32 OR CONFIG_HWINFO_MAX32)
zephyr_library_sources(
${MSDK_PERIPH_SRC_DIR}/CTB/ctb_me18.c
${MSDK_PERIPH_SRC_DIR}/CTB/ctb_reva.c
diff --git a/Libraries/zephyr/MAX/Source/MAX78002/CMakeLists.txt b/Libraries/zephyr/MAX/Source/MAX78002/CMakeLists.txt
index 11839a856fd..2b37c766782 100644
--- a/Libraries/zephyr/MAX/Source/MAX78002/CMakeLists.txt
+++ b/Libraries/zephyr/MAX/Source/MAX78002/CMakeLists.txt
@@ -142,7 +142,7 @@ zephyr_library_sources(
)
endif()
-if (CONFIG_SOC_FLASH_MAX32)
+if (CONFIG_SOC_FLASH_MAX32 OR CONFIG_HWINFO_MAX32)
zephyr_library_sources(
${MSDK_PERIPH_SRC_DIR}/FLC/flc_common.c
${MSDK_PERIPH_SRC_DIR}/FLC/flc_ai87.c
@@ -158,18 +158,22 @@ zephyr_library_sources(
)
endif()
-if (CONFIG_ENTROPY_MAX32_TRNG)
+if (CONFIG_ENTROPY_MAX32_TRNG OR CONFIG_HWINFO_MAX32)
zephyr_library_sources(
${MSDK_PERIPH_SRC_DIR}/TRNG/trng_ai87.c
${MSDK_PERIPH_SRC_DIR}/TRNG/trng_revb.c
)
endif()
-if (CONFIG_CRYPTO_MAX32)
+if (CONFIG_CRYPTO_MAX32 OR CONFIG_HWINFO_MAX32)
zephyr_library_sources(
${MSDK_PERIPH_SRC_DIR}/AES/aes_ai87.c
${MSDK_PERIPH_SRC_DIR}/AES/aes_revb.c
+)
+endif()
+if (CONFIG_CRYPTO_MAX32)
+zephyr_library_sources(
${MSDK_PERIPH_SRC_DIR}/CRC/crc_ai87.c
${MSDK_PERIPH_SRC_DIR}/CRC/crc_reva.c
)