diff --git a/drivers/power/adp1050/adp1050.c b/drivers/power/adp1050/adp1050.c
index 872d3b34617..d44b20e9ad6 100644
--- a/drivers/power/adp1050/adp1050.c
+++ b/drivers/power/adp1050/adp1050.c
@@ -155,6 +155,7 @@ int adp1050_read_status(struct adp1050_desc *desc,
 	case ADP1050_STATUS_INPUT_TYPE:
 	case ADP1050_STATUS_TEMPERATURE_TYPE:
 	case ADP1050_STATUS_CML_TYPE:
+	case ADP1051_STATUS_IOUT_TYPE:
 		ret = adp1050_read(desc, (uint16_t)status, &read_byte, 1);
 		if (ret)
 			return ret;
@@ -346,7 +347,7 @@ int adp1050_pwm_duty_cycle(struct adp1050_desc *desc, uint16_t pulse_width,
 		redge_msb = no_os_field_get(ADP1050_EDGE_MSB_MASK, pulse_start);
 		lsb = no_os_field_get(ADP1050_FALLING_EDGE_LSB_MASK,
 				      pulse_width + pulse_start) | no_os_field_get(ADP1050_RISING_EDGE_LSB_MASK,
-						      pulse_start);
+					      pulse_start);
 
 		reg_fedge = ADP1050_OUTA_FALLING_EDGE_TIMING;
 		reg_redge = ADP1050_OUTA_RISING_EDGE_TIMING;
@@ -358,7 +359,31 @@ int adp1050_pwm_duty_cycle(struct adp1050_desc *desc, uint16_t pulse_width,
 		redge_msb = no_os_field_get(ADP1050_EDGE_MSB_MASK, pulse_start);
 		lsb = no_os_field_get(ADP1050_FALLING_EDGE_LSB_MASK,
 				      pulse_width + pulse_start) | no_os_field_get(ADP1050_RISING_EDGE_LSB_MASK,
-						      pulse_start);
+					      pulse_start);
+
+		reg_fedge = ADP1050_OUTB_FALLING_EDGE_TIMING;
+		reg_redge = ADP1050_OUTB_RISING_EDGE_TIMING;
+		reg_lsb = ADP1050_OUTB_RISING_FALLING_TIMING_LSB;
+
+		break;
+	case ADP1050_OUTC:
+		fedge_msb = no_os_field_get(ADP1050_EDGE_MSB_MASK, pulse_width + pulse_start);
+		redge_msb = no_os_field_get(ADP1050_EDGE_MSB_MASK, pulse_start);
+		lsb = no_os_field_get(ADP1050_FALLING_EDGE_LSB_MASK,
+				      pulse_width + pulse_start) | no_os_field_get(ADP1050_RISING_EDGE_LSB_MASK,
+					      pulse_start);
+
+		reg_fedge = ADP1050_OUTB_FALLING_EDGE_TIMING;
+		reg_redge = ADP1050_OUTB_RISING_EDGE_TIMING;
+		reg_lsb = ADP1050_OUTB_RISING_FALLING_TIMING_LSB;
+
+		break;
+	case ADP1050_OUTD:
+		fedge_msb = no_os_field_get(ADP1050_EDGE_MSB_MASK, pulse_width + pulse_start);
+		redge_msb = no_os_field_get(ADP1050_EDGE_MSB_MASK, pulse_start);
+		lsb = no_os_field_get(ADP1050_FALLING_EDGE_LSB_MASK,
+				      pulse_width + pulse_start) | no_os_field_get(ADP1050_RISING_EDGE_LSB_MASK,
+					      pulse_start);
 
 		reg_fedge = ADP1050_OUTB_FALLING_EDGE_TIMING;
 		reg_redge = ADP1050_OUTB_RISING_EDGE_TIMING;
@@ -370,7 +395,7 @@ int adp1050_pwm_duty_cycle(struct adp1050_desc *desc, uint16_t pulse_width,
 		fedge_msb = no_os_field_get(ADP1050_EDGE_MSB_MASK, pulse_start);
 		lsb = no_os_field_get(ADP1050_RISING_EDGE_LSB_MASK,
 				      pulse_width + pulse_start) | no_os_field_get(ADP1050_FALLING_EDGE_LSB_MASK,
-						      pulse_start);
+					      pulse_start);
 
 		reg_fedge = ADP1050_SR1_FALLING_EDGE_TIMING;
 		reg_redge = ADP1050_SR1_RISING_EDGE_TIMING;
@@ -382,7 +407,7 @@ int adp1050_pwm_duty_cycle(struct adp1050_desc *desc, uint16_t pulse_width,
 		fedge_msb = no_os_field_get(ADP1050_EDGE_MSB_MASK, pulse_start);
 		lsb = no_os_field_get(ADP1050_RISING_EDGE_LSB_MASK,
 				      pulse_width + pulse_start) | no_os_field_get(ADP1050_FALLING_EDGE_LSB_MASK,
-						      pulse_start);
+					      pulse_start);
 
 		reg_fedge = ADP1050_SR2_FALLING_EDGE_TIMING;
 		reg_redge = ADP1050_SR2_RISING_EDGE_TIMING;
@@ -421,17 +446,17 @@ int adp1050_pwm_modulation(struct adp1050_desc *desc, enum adp1050_mod mod,
 	uint32_t mask, reg;
 
 	switch (mod) {
-	case ADP1050_OUTA_SR1_FALLING_MOD:
-		mask = ADP1050_OUTA_SR1_FALLING_MOD_MASK;
+	case ADP1050_OUTA_OUTC_SR1_FALLING_MOD:
+		mask = ADP1050_OUTA_OUTC_SR1_FALLING_MOD_MASK;
 		break;
-	case ADP1050_OUTA_SR1_RISING_MOD:
-		mask = ADP1050_OUTA_SR1_RISING_MOD_MASK;
+	case ADP1050_OUTA_OUTC_SR1_RISING_MOD:
+		mask = ADP1050_OUTA_OUTC_SR1_RISING_MOD_MASK;
 		break;
-	case ADP1050_OUTB_SR2_FALLING_MOD:
-		mask = ADP1050_OUTB_SR2_FALLING_MOD_MASK;
+	case ADP1050_OUTB_OUTD_SR2_FALLING_MOD:
+		mask = ADP1050_OUTB_OUTD_SR2_FALLING_MOD_MASK;
 		break;
-	case ADP1050_OUTB_SR2_RISING_MOD:
-		mask = ADP1050_OUTB_SR2_RISING_MOD_MASK;
+	case ADP1050_OUTB_OUTD_SR2_RISING_MOD:
+		mask = ADP1050_OUTB_OUTD_SR2_RISING_MOD_MASK;
 		break;
 	default:
 		return -EINVAL;
@@ -442,6 +467,10 @@ int adp1050_pwm_modulation(struct adp1050_desc *desc, enum adp1050_mod mod,
 	case ADP1050_OUTB:
 		reg = ADP1050_OUTA_OUTB_MODULATION_SETTINGS;
 		break;
+	case ADP1050_OUTC:
+	case ADP1050_OUTD:
+		reg = ADP1051_OUTC_OUTD_MODULATION_SETTINGS;
+		break;
 	case ADP1050_SR1:
 	case ADP1050_SR2:
 		reg = ADP1050_SR1_SR2_MODULATION_SETTINGS;
@@ -530,6 +559,20 @@ int adp1050_set_vin(struct adp1050_desc *desc, int16_t mantissa, int8_t exp,
 			     val, 2);
 }
 
+/**
+ * @brief Set ADP1051 vout droop for setting the rate of output voltage and current
+ * @param desc - ADP1050 device descriptor
+ * @param mantissa - Mantissa value to be transmitted, 7 bit twos complment
+ * @return 0 in case of success, negative error code otherwise
+*/
+int adp1051_set_vout_droop(struct adp1050_desc *desc, uint16_t mantissa)
+{
+	if(mantissa > ADP1051_VDROOP_MAXVAL)
+		return -EINVAL;
+
+	return adp1050_write(desc, ADP1051_VOUT_DROOP, mantissa, 2);
+}
+
 /**
  * @brief Set current limit fast fault for overcurrent protection and current
  * 	  limit cycle-by-cycle reference
@@ -578,6 +621,96 @@ int adp1050_set_cs1_settings(struct adp1050_desc *desc,
 	return adp1050_write(desc, ADP1050_CS1_CBC_CURR_LIM_SETTINGS, val, 1);
 }
 
+/**
+ * @brief Set light load and deep light load common setting
+ * @param desc - ADP1050 device descriptor
+ * @param drooping - avg speed for drooping contrl
+ * @param avg_speed - light load and deep light load avg speed
+ * @param hysteresis - light load and deep light load hysteresis
+ * @return 0 in case of succes, negative error code otherwise.
+*/
+int adp1051_llm_dllm_comm_setting(struct adp1050_desc *desc,
+				  enum adp1051_llm_dlm_drooping drooping,
+				  enum adp1051_llm_dlm_avg_speed avg_speed,
+				  enum adp1051_llm_dlm_hysteresis hysteresis)
+{
+	uint16_t val;
+
+	val = no_os_field_prep(ADP1051_LLM_DLM_DROOPING_MASK, drooping) |
+	      no_os_field_prep(ADP1051_LLM_DLM_AVG_SPEED_MASK, avg_speed) |
+	      no_os_field_prep(ADP1051_LLM_DLM_HYST_MASK, hysteresis);
+
+	return adp1050_write(desc, ADP1051_LLM_DLM_SET, val, 1);
+}
+
+/**
+ * @brief Set light load and deep light load
+ * @param desc - ADP1050 device descriptor
+ * @param llm_debounce - cs3_oc_fault flag debounce
+ * @param thresh - light load and deep light load threshold
+ * @param light en - 1 to enable light load mode
+ * @return 0 in case of succes, negative error code otherwise.
+*/
+int adp1051_llm_dllm_setting(struct adp1050_desc *desc,
+			     enum adp1051_cs2_lightload_debounce llm_debounce,
+			     enum adp1051_llm_dlm_thresh thresh,
+			     bool light_en)
+{
+	int16_t val;
+
+	if (light_en)
+		val = no_os_field_prep(ADP1051_LLM_DEBOUNCE_MASK, 1) |
+		      no_os_field_prep(ADP1051_LLM_DEBOUNCE_MASK, llm_debounce) |
+		      no_os_field_prep(ADP1051_LLM_THRESH_MASK, thresh);
+
+	return adp1050_write(desc, ADP1051_CS2_LIGHT_THRESH, val, 1);
+
+	if (!light_en)
+		val = no_os_field_prep(ADP1051_LLM_THRESH_MASK, thresh);
+
+	return adp1050_write(desc, ADP1051_CS2_LIGHT_THRESH, val, 1);
+}
+
+/**
+ * @brief Set the IOUT calibration gain for ADP1051
+ * @param desc - ADP1050 device descriptor
+ * @param mantissa - Mantissa value to be transmitted, 11 bit twos complement.
+ * @param exp - Exponent value to be transmitted, 5 bit twos complement.
+ * added support for ADP1051 - usually used in the read_iout command
+ */
+int adp1051_set_iout_cal_gain(struct adp1050_desc *desc, int16_t mantissa,
+			      int8_t exp)
+{
+	uint16_t val;
+
+	if (mantissa > ADP1050_MANT_MAX || exp > ADP1050_EXP_MAX)
+		return -EINVAL;
+
+	val = no_os_field_prep(ADP1050_EXP_MASK, exp) | mantissa;
+
+	return adp1050_write(desc, ADP1051_IOUT_CAL_GAIN, val, 2);
+}
+
+/**
+ * @brief Set the IOUT OC fault limit for ADP1051
+ * @param desc - ADP1050 device descriptor
+ * @param mantissa - Mantissa value to be transmitted, 11 bit twos complement.
+ * @param exp - Exponent value to be transmitted, 5 bit twos complement.
+ * added support for ADP1051 -
+ */
+int adp1051_set_iout_oc_fault_limit(struct adp1050_desc *desc, int16_t mantissa,
+				    int8_t exp)
+{
+	uint16_t val;
+
+	if (mantissa > ADP1050_MANT_MAX || exp > ADP1050_EXP_MAX)
+		return -EINVAL;
+
+	val = no_os_field_prep(ADP1050_EXP_MASK, exp) | mantissa;
+
+	return adp1050_write(desc, ADP1051_IOUT_OC_FAULT_LIMIT, val, 2);
+}
+
 /**
  * @brief Set requested ADP1050 channel in Open Loop operation mode.
  * @param desc - ADP1050 device descriptor.
@@ -591,7 +724,8 @@ int adp1050_set_open_loop(struct adp1050_desc *desc, uint8_t rising_edge,
 {
 	int ret;
 
-	if ((chan == ADP1050_OUTA || chan == ADP1050_OUTB)
+	if ((chan == ADP1050_OUTA || chan == ADP1050_OUTB || chan == ADP1051_OUTC
+	|| chan == ADP1051_OUTD)
 	    && falling_edge < rising_edge)
 		return -EINVAL;
 
@@ -610,6 +744,8 @@ int adp1050_set_open_loop(struct adp1050_desc *desc, uint8_t rising_edge,
 	switch (chan) {
 	case ADP1050_OUTA:
 	case ADP1050_OUTB:
+	case ADP1051_OUTC:
+	case ADP1051_OUTD:
 		ret = adp1050_pwm_duty_cycle(desc, falling_edge, falling_edge - rising_edge,
 					     chan);
 		break;
@@ -634,7 +770,8 @@ int adp1050_set_open_loop(struct adp1050_desc *desc, uint8_t rising_edge,
 	if (ret)
 		return ret;
 
-	if (chan == ADP1050_OUTA || chan == ADP1050_OUTB) {
+	if (chan == ADP1050_OUTA || chan == ADP1050_OUTB || chan == ADP1051_OUTC
+	|| chan == ADP1051_OUTD) {
 		ret = adp1050_write(desc, ADP1050_SOFT_START_SETTING_OL,
 				    ADP1050_OL_SS_64_CYCLES, 1);
 		if (ret)
@@ -773,8 +910,8 @@ int adp1050_set_flgi_response(struct adp1050_desc *desc,
  * @param hf - Normal mode high filter gain settings.
  * @return 0 in case of succes, negative error code otherwise
 */
-int adp1050_filter(struct adp1050_desc *desc, uint8_t zero, uint8_t pole,
-		   uint8_t lf, uint8_t hf)
+int adp1050_nfilter(struct adp1050_desc *desc, uint8_t zero, uint8_t pole,
+		    uint8_t lf, uint8_t hf)
 {
 	int ret;
 
@@ -793,6 +930,35 @@ int adp1050_filter(struct adp1050_desc *desc, uint8_t zero, uint8_t pole,
 	return adp1050_write(desc, ADP1050_NORMAL_MODE_COMP_HIGH_FREQ, hf, 1);
 }
 
+/**
+ * @brief Adjust filter settings of the light mode compensator
+ * @param desc - ADP1050 device descriptor
+ * @param zero - light mode zero settings.
+ * @param pole - light mode pole settings.
+ * @param lf - light mode low filter gain settings.
+ * @param hf - light mode high filter gain settings.
+ * @return 0 in case of succes, negative error code otherwise
+*/
+int adp1050_lfilter(struct adp1050_desc *desc, uint8_t zero, uint8_t pole,
+		    uint8_t lf, uint8_t hf)
+{
+	int ret;
+
+	ret = adp1050_write(desc, ADP1051_LIGHT_MOD_COMP_LOW_FREQ, lf, 1);
+	if (ret)
+		return ret;
+
+	ret = adp1050_write(desc, ADP1051_LIGHT_MODE_COMP_ZERO, zero, 1);
+	if (ret)
+		return ret;
+
+	ret = adp1050_write(desc, ADP1051_LIGHT_MODE_COMP_POLE, pole, 1);
+	if (ret)
+		return ret;
+
+	return adp1050_write(desc, ADP1051_LIGHTL_MODE_COMP_HIGH_FREQ, hf, 1);
+}
+
 /**
  * @brief Trim IIN(CS1 pin)/VIN(VF pin)/VOUT(VS pin).
  * @param desc - ADP1050 device descriptor
@@ -831,7 +997,7 @@ int adp1050_trim(struct adp1050_desc *desc, enum adp1050_trim_type trim_type,
 		   for the device to trim it. CS1 voltage needs to be applied
 		   according to datasheet specifications. */
 		while (read_val != ADP1050_CS1_TRIM_VAL
-		       && init_val < ADP1050_CS1_MAX_INIT_VAL) {
+				   && init_val < ADP1050_CS1_MAX_INIT_VAL) {
 			ret = adp1050_write(desc, ADP1050_CS1_GAIN_TRIM, init_val++, 1);
 			if (ret)
 				return ret;
@@ -892,8 +1058,8 @@ int adp1050_trim(struct adp1050_desc *desc, enum adp1050_trim_type trim_type,
 			return ret;
 
 		while (read_val != trim_val
-		       && no_os_field_get(ADP1050_VS_INIT_MASK,
-					  init_val) < ADP1050_VS_OFFSET_MAX_INIT_VAL) {
+				   && no_os_field_get(ADP1050_VS_INIT_MASK,
+						      init_val) < ADP1050_VS_OFFSET_MAX_INIT_VAL) {
 			ret = adp1050_vout_offset(desc,
 						  (read_val < trim_val) ? init_val++ : init_val--);
 			if (ret)
@@ -1184,4 +1350,4 @@ int adp1050_remove(struct adp1050_desc *desc)
 	no_os_free(desc);
 
 	return 0;
-}
+}
\ No newline at end of file
diff --git a/drivers/power/adp1050/adp1050.h b/drivers/power/adp1050/adp1050.h
index d5fd9b8fac2..ede2a27ea47 100644
--- a/drivers/power/adp1050/adp1050.h
+++ b/drivers/power/adp1050/adp1050.h
@@ -33,6 +33,10 @@
 #ifndef __ADP_1050_H__
 #define __ADP_1050_H__
 
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
 #include <stdint.h>
 #include <stdbool.h>
 #include <stdio.h>
@@ -42,6 +46,9 @@
 #include "no_os_util.h"
 #include "no_os_units.h"
 
+/*****************************************************************************/
+/************************** ADP1050 Constants ********************************/
+/*****************************************************************************/
 #define ADP1050_EXTENDED_COMMAND		0xFF
 #define ADP1050_WRITE_BYTE_MAX_VAL		0xFF
 
@@ -83,6 +90,8 @@
 #define ADP1050_EXP_MASK			NO_OS_GENMASK(15, 11)
 #define ADP1050_MANT_MASK			NO_OS_GENMASK(10, 0)
 
+#define ADP1051_VDROOP_MAXVAL			0xFF
+
 #define ADP1050_VOUT_EXP_MASK			NO_OS_GENMASK(4, 0)
 #define ADP1050_VOUT_GO_COMMAND			0x06
 #define ADP1050_VOUT_OFF			0x00
@@ -106,13 +115,22 @@
 
 #define ADP1050_OUTA_OL_ENABLE			NO_OS_BIT(0)
 #define ADP1050_OUTB_OL_ENABLE			NO_OS_BIT(1)
+#define ADP1051_OUTC_OL_ENABLE			NO_OS_BIT(2)
+#define ADP1051_OUTD_OL_ENABLE			NO_OS_BIT(3)
 #define ADP1050_SR1_OL_ENABLE			NO_OS_BIT(4)
 #define ADP1050_SR2_OL_ENABLE			NO_OS_BIT(5)
 
-#define ADP1050_OUTB_SR2_RISING_MOD_MASK	NO_OS_GENMASK(7, 6)
-#define ADP1050_OUTB_SR2_FALLING_MOD_MASK	NO_OS_GENMASK(5, 4)
-#define ADP1050_OUTA_SR1_RISING_MOD_MASK	NO_OS_GENMASK(3, 2)
-#define ADP1050_OUTA_SR1_FALLING_MOD_MASK	NO_OS_GENMASK(1, 0)
+#define ADP1050_OUTB_OUTD_SR2_RISING_MOD_MASK	NO_OS_GENMASK(7, 6)
+#define ADP1051_OUTD_SR2_RISING_MOD_MASK	NO_OS_GENMASK(7, 6)
+
+#define ADP1050_OUTB_OUTD_SR2_FALLING_MOD_MASK	NO_OS_GENMASK(5, 4)
+#define ADP1051_OUTD_SR2_FALLING_MOD_MASK	NO_OS_GENMASK(5 ,4)
+
+#define ADP1050_OUTA_OUTC_SR1_RISING_MOD_MASK	NO_OS_GENMASK(3, 2)
+#define ADP1051_OUTC_SR1_RISING_MOD_MASK	NO_OS_GENMASK(3, 2)
+
+#define ADP1050_OUTA_OUTC_SR1_FALLING_MOD_MASK	NO_OS_GENMASK(1, 0)
+#define ADP1051_OUTC_SR1_FALLING_MOD_MASK	NO_OS_GENMASK(1, 0)
 
 #define ADP1050_POSITIVE_MOD_SIGN		0x02
 #define ADP1050_NEGATIVE_MOD_SIGN		0x03
@@ -127,6 +145,7 @@
 
 #define ADP1050_FREQ_SYNC_ON			0x48
 #define ADP1050_FREQ_SYNC_OFF			0x49
+
 #define ADP1050_MAX_PERIOD_INTEGER(x)		((1000 / (x)) * 1000)
 #define ADP1050_MAX_PERIOD_FLOAT(x)		((1000 / (((x) - 0xF800) / 2)) * 1000)
 #define ADP1050_FLOAT_FREQ_MASK			NO_OS_BIT(15)
@@ -158,6 +177,14 @@
 #define ADP1050_VS_MAX_INIT_VAL			0xFF
 #define ADP1050_VS_INIT_MASK			NO_OS_GENMASK(14, 0)
 
+#define ADP1051_LLM_DLM_DROOPING_MASK		NO_OS_GENMASK(7, 6)
+#define ADP1051_LLM_DLM_AVG_SPEED_MASK		NO_OS_GENMASK(5, 4)
+#define ADP1051_LLM_DLM_HYST_MASK		NO_OS_GENMASK(3, 2)
+
+#define ADP1051_LLM_DEBOUNCE_MASK		NO_OS_GENMASK(6, 5)
+#define ADP1051_LLM_THRESH_MASK			NO_OS_GENMASK(3, 0)
+#define ADP1051_LLM_ENABLE_MASK			NO_OS_BIT(4)
+
 /* PMBus Addresses */
 #define ADP1050_PMBUS_10KOHM_ADDRESS		0x70
 #define ADP1050_PMBUS_31KOHM_ADDRESS		0x71
@@ -188,7 +215,9 @@
 #define ADP1050_TON_RISE_60MS			0x003C
 #define ADP1050_TON_RISE_100MS			0x0064
 
-/* PMBus COMMAND SET */
+/*****************************************************************************/
+/************************** ADP1050 Registers ********************************/
+/*****************************************************************************/
 #define ADP1050_OPERATION			0x01
 #define ADP1050_ON_OFF_CONFIG			0x02
 #define ADP1050_CLEAR_FAULTS			0x03
@@ -205,15 +234,20 @@
 #define ADP1050_VOUT_MARGIN_HIGH		0x25
 #define ADP1050_VOUT_MARGIN_LOW			0x26
 #define ADP1050_VOUT_TRANSITION_RATE		0x27
+#define ADP1051_VOUT_DROOP			0x28
 #define ADP1050_VOUT_SCALE_LOOP			0x29
 #define ADP1050_VOUT_SCALE_MONITOR		0x2A
 #define ADP1050_FREQUENCY_SWITCH		0x33
 #define ADP1050_VIN_ON				0x35
 #define ADP1050_VIN_OFF				0x36
+#define ADP1051_IOUT_CAL_GAIN			0x38
 #define ADP1050_VOUT_OV_FAULT_LIMIT		0x40
 #define ADP1050_VOUT_OV_FAULT_RESPONSE		0x41
 #define ADP1050_VOUT_UV_FAULT_LIMIT		0x44
 #define ADP1050_VOUT_UV_FAULT_RESPONSE		0x45
+#define ADP1051_IOUT_OC_FAULT_LIMIT		0x46
+#define ADP1051_IOUT_OC_FAULT_RES		0x47
+#define ADP1051_IOUT_OC_LV_FAULT_LIMIT		0x48
 #define ADP1050_OT_FAULT_LIMIT			0x4F
 #define ADP1050_OT_FAULT_RESPONSE		0x50
 #define ADP1050_POWER_GOOD_ON			0x5E
@@ -224,12 +258,14 @@
 #define ADP1050_STATUS_BYTE			0x78
 #define ADP1050_STATUS_WORD			0x79
 #define ADP1050_STATUS_VOUT			0x7A
+#define ADP1051_STATUS_IOUT			0x7B
 #define ADP1050_STATUS_INPUT			0x7C
 #define ADP1050_STATUS_TEMPERATURE		0x7D
 #define ADP1050_STATUS_CML			0x7E
 #define ADP1050_READ_VIN			0x88
 #define ADP1050_READ_IIN			0x89
 #define ADP1050_READ_VOUT			0x8B
+#define ADP1051_READ_IOUT			0x8C
 #define ADP1050_READ_TEMPERATURE		0x8D
 #define ADP1050_READ_DUTY_CYCLE			0x94
 #define ADP1050_READ_FREQUENCY			0x95
@@ -297,11 +333,15 @@
 
 /* Current Sense and Limit Setting Registers */
 #define ADP1050_CS1_GAIN_TRIM			0xFE14
-#define ADP1050_CS3_OC_DEBOUNCE			0xFE19
+#define ADP1051_CS2_GAIN_TRIM			0xFE15
+#define ADP1051_CS2_DIG_OFFSET_TRIM		0xFE16
+#define ADP1051_CS2_ANA_TRIM			0xFE17
+#define ADP1051_CS2_LIGHT_THRESH		0xFE19
 #define ADP1050_IIN_OC_FAST_FAULT_LIMIT		0xFE1A
 #define ADP1050_CS1_CBC_CURR_LIM_REF		0xFE1B
+#define ADP1051_PWM_OUT_DIS_DLM			0xFE1C
 #define ADP1050_MATCHED_CBC_CURR_LIM_SETTINGS	0xFE1D
-#define ADP1050_SR1_SR2_RESPONSE_CBC_CURR_LIM	0xFE1E
+#define ADP1051_LLM_DLM_SET			0xFE1E
 #define ADP1050_CS1_CBC_CURR_LIM_SETTINGS	0xFE1F
 
 /* Voltage Sense and Limit Setting Registers */
@@ -328,6 +368,10 @@
 #define ADP1050_PWM_180_PHASE_SHIFT_SETTINGS	0xFE3B
 #define ADP1050_MODULATION_LIMIT		0xFE3C
 #define ADP1050_FEEDFORWARD_SS_FILTER_GAIN	0xFE3D
+#define ADP1051_LIGHT_MOD_COMP_LOW_FREQ		0xFE34
+#define ADP1051_LIGHT_MODE_COMP_ZERO		0xFE35
+#define ADP1051_LIGHT_MODE_COMP_POLE		0xFE36
+#define ADP1051_LIGHTL_MODE_COMP_HIGH_FREQ	0xFE37
 
 /* PWM Outputs Timing Registers */
 #define ADP1050_OUTA_RISING_EDGE_TIMING		0xFE3E
@@ -345,16 +389,33 @@
 #define ADP1050_OUTA_OUTB_MODULATION_SETTINGS	0xFE50
 #define ADP1050_SR1_SR2_MODULATION_SETTINGS	0xFE52
 #define ADP1050_PWM_OUTPUT_DISABLE		0xFE53
+#define ADP1051_OUTC_RISING_EDGE_TIMING		0xFE44
+#define ADP1051_OUTC_FALLING_EDGE_TIMING	0xFE45
+#define ADP1051_OUTC_RISING_FALLING_TIMING_LSB	0xFE46
+#define ADP1051_OUTD_RISING_EDGE_TIMING		0xFE47
+#define ADP1051_OUTD_FALLING_EDGE_TIMING	0xFE48
+#define ADP1051_OUTD_RISING_FALLING_TIMING_LSB	0xFE49
+#define ADP1051_OUTC_OUTD_MODULATION_SETTINGS	0xFE51
 
 /* Volt-Second Balance Control Registers */
 #define ADP1050_VS_BAL_CTRL_GENERAL_SETTINGS	0xFE54
 #define ADP1050_VS_BAL_CTRL_OUTA_OUTB		0xFE55
 #define ADP1050_VS_BAL_CTRL_SR1_SR2		0xFE57
+#define ADP1051_VS_BAL_CTRL_OUTC_OUTD		0xFE56
 
 /* Duty Cycle Reading Setting Registers */
 #define ADP1050_DUTY_CYCLE_READING_SETTINGS	0xFE58
 #define ADP1050_INPUT_VOLTAGE_COMP_MULT		0xFE59
 
+/* Adaptive Dead Time Compensation Registers */
+#define ADP1051_ADAPTIVE_DTIME_TRESH		0xFE5A
+#define ADP1051_OUTA_DTIME			0xFE5B
+#define ADP1051_OUTB_DTIME			0xFE5C
+#define ADP1051_OUTC_DTIME			0xFE5D
+#define ADP1051_OUTD_DTIME			0xFE5E
+#define ADP1051_SR1_DTIME			0xFE5F
+#define ADP1051_SR2_DTIME			0xFE60
+
 /* Other Setting Registers */
 #define ADP1050_GO_COMMANDS			0xFE61
 #define ADP1050_CUSTOMIZED_REGISTERS		0xFE62
@@ -368,6 +429,9 @@
 #define ADP1050_MOD_FLAG_OVP_SELECTION		0xFE6C
 #define ADP1050_OUTA_OUTB_ADJ_REF_SYNCH		0xFE6D
 #define ADP1050_SR1_SR2_ADJ_REF_SYNCH		0xFE6F
+#define ADP1051_ADAPTIVE_DTIME_COMP_CONFIG	0xFE66
+#define ADP1051_OFFSET_SR1_SR2			0xFE68
+#define ADP1051_OUTC_OUTD_ADJ_REF_SYNC		0xFE6E
 
 /* Manufacturer Specific Fault Flag Registers */
 #define ADP1050_FLAG_REGISTER1			0xFEA0
@@ -386,6 +450,7 @@
 #define ADP1050_VF_VALUE			0xFEAC
 #define ADP1050_DUTY_CYCLE_VALUE		0xFEAD
 #define ADP1050_INPUT_POWER_VALUE		0xFEAE
+#define ADP1051_OUTPUT_POWER_VALUE	0xFEAF
 
 enum adp1050_loop {
 	ADP1050_CLOSE_LOOP,
@@ -395,16 +460,18 @@ enum adp1050_loop {
 enum adp1050_channel {
 	ADP1050_OUTA,
 	ADP1050_OUTB,
+	ADP1051_OUTC,
+	ADP1051_OUTD,
 	ADP1050_SR1,
 	ADP1050_SR2,
 	ADP1050_DISABLE_ALL
 };
 
 enum adp1050_mod {
-	ADP1050_OUTA_SR1_FALLING_MOD = NO_OS_BIT(1),
-	ADP1050_OUTA_SR1_RISING_MOD = NO_OS_BIT(3),
-	ADP1050_OUTB_SR2_FALLING_MOD = NO_OS_BIT(5),
-	ADP1050_OUTB_SR2_RISING_MOD = NO_OS_BIT(7),
+	ADP1050_OUTA_OUTC_SR1_FALLING_MOD = NO_OS_BIT(1),
+	ADP1050_OUTA_OUTC_SR1_RISING_MOD = NO_OS_BIT(3),
+	ADP1050_OUTB_OUTD_SR2_FALLING_MOD = NO_OS_BIT(5),
+	ADP1050_OUTB_OUTD_SR2_RISING_MOD = NO_OS_BIT(7),
 };
 
 enum adp1050_pass_type {
@@ -439,24 +506,27 @@ enum adp1050_freq {
 	ADP1050_397KHZ = 0x018D,
 	ADP1050_403KHZ = 0x0193,
 	ADP1050_410KHZ = 0x019A,
-	ADP1050_97_5KHZ = 0xF8C3,
-	ADP1050_111_5KHZ = 0xF8DF,
-	ADP1050_156_5KHZ = 0xF939,
-	ADP1050_164_5KHZ = 0xF949,
-	ADP1050_173_5KHZ = 0xF95B,
-	ADP1050_195_5KHZ = 0xF987,
-	ADP1050_201_5KHZ = 0xF993,
-	ADP1050_208_5KHZ = 0xF9A1,
-	ADP1050_215_5KHZ = 0xF9AF,
-	ADP1050_231_5KHZ = 0xF9CF,
-	ADP1050_240_5KHZ = 0xF9E1,
-	ADP1050_260_5KHZ = 0xFA09,
-	ADP1050_271_5KHZ = 0xFA1F,
-	ADP1050_297_5KHZ = 0xFA53,
-	ADP1050_312_5KHZ = 0xFA71,
-	ADP1050_320_5KHZ = 0xFA81,
-	ADP1050_367_5KHZ = 0xFADF,
-	ADP1050_390_5KHZ = 0xFB0D,
+	ADP1050_416_5KHZ = 0xFB41,
+	ADP1050_426_5KHZ = 0xFB4F,
+	ADP1050_431KHZ = 0x1AF,
+	ADP1050_438_5KHZ = 0xFB6D,
+	ADP1050_446_5KHZ = 0xFB7D,
+	ADP1050_454_5KHZ = 0xFB8D,
+	ADP1050_463KHZ = 0x01CF,
+	ADP1050_472KHZ = 0x01D8,
+	ADP1050_481KHZ = 0x01E1,
+	ADP1050_490KHZ = 0x1EA,
+	ADP1050_500KHZ = 0x1F4,
+	ADP1050_510KHZ = 0x01FE,
+	ADP1050_520KHZ = 0x0208,
+	ADP1050_531KHZ = 0x0213,
+	ADP1050_543KHZ = 0x021F,
+	ADP1050_556KHZ = 0x022C,
+	ADP1050_568KHZ = 0x0238,
+	ADP1050_581KHZ = 0x0245,
+	ADP1050_595KHZ = 0x0253,
+	ADP1050_610KHZ = 0x0262,
+	ADP1050_625KHZ = 0x0271,
 };
 
 enum adp1050_vout_tr {
@@ -522,7 +592,8 @@ enum adp1050_value_type {
 	ADP1050_IIN = ADP1050_READ_IIN,
 	ADP1050_TEMP = ADP1050_READ_TEMPERATURE,
 	ADP1050_DUTY_CYCLE = ADP1050_READ_DUTY_CYCLE,
-	ADP1050_FREQUENCY = ADP1050_READ_FREQUENCY
+	ADP1050_FREQUENCY = ADP1050_READ_FREQUENCY,
+	ADP1051_IOUT = ADP1051_READ_IOUT,
 };
 
 enum adp1050_status_type {
@@ -530,17 +601,70 @@ enum adp1050_status_type {
 	ADP1050_STATUS_INPUT_TYPE = ADP1050_STATUS_INPUT,
 	ADP1050_STATUS_WORD_TYPE = ADP1050_STATUS_WORD,
 	ADP1050_STATUS_TEMPERATURE_TYPE = ADP1050_STATUS_TEMPERATURE,
-	ADP1050_STATUS_CML_TYPE = ADP1050_STATUS_CML
+	ADP1050_STATUS_CML_TYPE = ADP1050_STATUS_CML,
+	ADP1051_STATUS_IOUT_TYPE = ADP1051_STATUS_IOUT,
 };
 
 enum adp1050_trim_type {
 	ADP1050_CS1_IIN_TRIM,
 	ADP1050_VS_VOUT_TRIM,
-	ADP1050_VF_VIN_TRIM
+	ADP1050_VF_VIN_TRIM,
+};
+
+enum adp105x_id {
+	ID_ADP1050,
+	ID_ADP1051,
+};
+
+enum adp1051_llm_dlm_drooping {
+	ADP1051_82US_7B,
+	ADP1051_164US_8B = 0x40,
+	ADP1051_328US_9B = 0x80,
+	ADP1051_656_10B = 0xC0,
+};
+
+enum adp1051_llm_dlm_avg_speed {
+	ADP1051_41US_6B_AVG,
+	ADP1051_82US_7B_AVG = 0x10,
+	ADP1051_164US_8B_AVG = 0x20,
+	ADP1051_328US_9B_AVG = 0x30,
+};
+
+enum adp1051_llm_dlm_hysteresis {
+	ADP1051_3LSB,
+	ADP1051_8LSB = 0x04,
+	ADP1051_12LSB = 0x08,
+	ADP1051_16LSB = 0x0C,
+};
+
+enum adp1051_cs2_lightload_debounce {
+	ADP1051_0MS,
+	ADP1051_10MS = 0x20,
+	ADP1051_20MS = 0x40,
+	ADP1051_200MS = 0x60,
+};
+
+enum adp1051_llm_dlm_thresh {
+	ADP1051_0mv,
+	ADP1051_093_7mv = 0x01,
+	ADP1051_187_15mv = 0x02,
+	ADP1051_281_22mv = 0x03,
+	ADP1051_375_30mv = 0x04,
+	ADP1051_468_37mv = 0x05,
+	ADP1051_562_45mv = 0x06,
+	ADP1051_656_52mv = 0x07,
+	ADP1051_750_60mv = 0x08,
+	ADP1051_843_67mv = 0x09,
+	ADP1051_937_75mv = 0x0A,
+	ADP1051_103_82mv = 0x0B,
+	ADP1051_112_90mv = 0x0C,
+	ADP1051_121_97mv = 0x0D,
+	ADP1051_131_105mv = 0x0E,
+	ADP1051_140_112mv = 0x0F,
 };
 
 /**
- * @brief Initialization parameter for the ADP1050 device.
+ * @brief Initialization parameter for the ADP105x devices.
 */
 struct adp1050_init_param {
 	struct no_os_i2c_init_param *i2c_param;
@@ -550,10 +674,11 @@ struct adp1050_init_param {
 	struct no_os_gpio_init_param *ctrl_param;
 	uint8_t on_off_config;
 	bool ext_syni;
+	enum adp105x_id device_id;
 };
 
 /**
- * @brief Device descriptor for ADP1050.
+ * @brief Device descriptor for ADP105x
 */
 struct adp1050_desc {
 	struct no_os_i2c_desc *i2c_desc;
@@ -654,10 +779,6 @@ int adp1050_set_flgi_response(struct adp1050_desc *desc,
 			      enum adp1050_flgi_fault_response fault_response,
 			      enum adp1050_flgi_after_fault after_fault);
 
-/** Set ADP1050's filter value. */
-int adp1050_filter(struct adp1050_desc *desc, uint8_t zero, uint8_t pole,
-		   uint8_t lf, uint8_t hf);
-
 /** Set ADP1050's trim. */
 int adp1050_trim(struct adp1050_desc *desc, enum adp1050_trim_type trim_type,
 		 uint16_t vout_command, uint16_t vout_scale, uint16_t trim_val);
@@ -684,4 +805,35 @@ int adp1050_init(struct adp1050_desc **desc,
 /** Remove resources allocated by the init function. */
 int adp1050_remove(struct adp1050_desc *desc);
 
+/** Light Load and Deep Light Load Mode Common Setting */
+int adp1051_llm_dllm_comm_setting(struct adp1050_desc *desc,
+				  enum adp1051_llm_dlm_drooping drooping,
+				  enum adp1051_llm_dlm_avg_speed avg_speed,
+				  enum adp1051_llm_dlm_hysteresis hysteresis);
+
+/** Light Load and Deep Light Load Mode Setting */
+int adp1051_llm_dllm_setting(struct adp1050_desc *desc,
+			     enum adp1051_cs2_lightload_debounce llm_debounce,
+			     enum adp1051_llm_dlm_thresh thresh,
+			     bool light_en);
+
+/** Sets IOUT calibration gain */
+int adp1051_set_iout_cal_gain(struct adp1050_desc *desc, int16_t mantissa,
+			      int8_t exp);
+
+/** Sets VOUT drooping */
+int adp1051_set_vout_droop(struct adp1050_desc *desc, uint16_t mantissa);
+
+/** Sets IOUT OC fault limit */
+int adp1051_set_iout_oc_fault_limit(struct adp1050_desc *desc, int16_t mantissa,
+				    int8_t exp);
+
+/** Adjust filter settings of the light mode compensator */
+int adp1050_lfilter(struct adp1050_desc *desc, uint8_t zero, uint8_t pole,
+		    uint8_t lf, uint8_t hf);
+
+/**  Adjust filter settings of the normal mode compensator */
+int adp1050_nfilter(struct adp1050_desc *desc, uint8_t zero, uint8_t pole,
+		    uint8_t lf, uint8_t hf);
+
 #endif /** __ADP_1050_H__ */