diff --git a/adi/__init__.py b/adi/__init__.py index 57dfd9ce8..289ad84a0 100644 --- a/adi/__init__.py +++ b/adi/__init__.py @@ -127,6 +127,7 @@ from adi.tddn import tddn try: + from adi.sshfs import sshfs from adi.jesd import jesd except ImportError: pass diff --git a/adi/ad9162.py b/adi/ad9162.py index a30243ab2..a500d2cd9 100644 --- a/adi/ad9162.py +++ b/adi/ad9162.py @@ -13,7 +13,7 @@ class ad9162(tx, context_manager, sync_start): _complex_data = False # _complex_data = True - _tx_channel_names = ["voltage0_i", "voltage0_q"] + _tx_channel_names = ["voltage0"] _device_name = "" def __init__(self, uri="", username="root", password="analog"): @@ -21,26 +21,26 @@ def __init__(self, uri="", username="root", password="analog"): context_manager.__init__(self, uri, self._device_name) self._jesd = jesd(uri, username=username, password=password) - self._txdac = self._ctx.find_device("axi-ad9162-hpc") + self._txdac = self._ctx.find_device("axi-ad9164-hpc") tx.__init__(self) @property def fir85_enable(self): - return self._get_iio_attr("voltage0_i", "fir85_enable", True, self._txdac) + return self._get_iio_attr("altvoltage0", "fir85_enable", True, self._txdac) @fir85_enable.setter def fir85_enable(self, value): - self._set_iio_attr("voltage0_i", "fir85_enable", True, value, self._txdac) + self._set_iio_attr("voltage0", "fir85_enable", True, value, self._txdac) @property def sample_rate(self): """sample_rate: Sample frequency rate TX path in samples per second.""" - return self._get_iio_attr("voltage0_i", "sampling_frequency", True, self._txdac) + return self._get_iio_attr("voltage0", "sampling_frequency", True, self._txdac) @property def scale(self): - return self._get_iio_attr("voltage0_i", "scale", True, self._txdac) + return self._get_iio_attr("voltage0", "scale", True, self._txdac) @property def frequency_nco(self): @@ -53,3 +53,11 @@ def frequency_nco(self, value): @property def jesd204_statuses(self): return self._jesd.get_all_statuses() + + def register_read(self, reg): + """Direct Register Access via debugfs""" + self._set_iio_debug_attr_str("direct_reg_access", reg, self._txdac) + return self._get_iio_debug_attr_str("direct_reg_access", self._txdac) + def register_write(self, reg, value): + """Direct Register Access via debugfs""" + self._set_iio_debug_attr_str("direct_reg_access", f"{reg} {value}", self._txdac) diff --git a/examples/ad9164_example.py b/examples/ad9164_example.py new file mode 100755 index 000000000..5193bedad --- /dev/null +++ b/examples/ad9164_example.py @@ -0,0 +1,52 @@ +# Copyright (C) 2022 Analog Devices, Inc. +# +# SPDX short identifier: ADIBSD + +import time +import sys +import adi +import math +import matplotlib.pyplot as plt +import numpy as np +from scipy import signal + +url = "local:" if len(sys.argv) == 1 else sys.argv[1] +tx = adi.ad9162(url) +gpio_controller = adi.one_bit_adc_dac(uri=url, name="one-bit-adc-dac") +ssh = adi.sshfs(address=url, username="root", password="analog") + +gpio_controller.gpio_dac_ctrl_0 = 1 +gpio_controller.gpio_dac_ctrl_1 = 1 +gpio_controller.gpio_dac_ctrl_2 = 1 +gpio_controller.gpio_dac_ctrl_3 = 1 +gpio_controller.gpio_dac_ctrl_4 = 0 + +tx.tx_cyclic_buffer = True +tx.tx_enabled_channels = [0] +dds_or_dma_signal = 1 + +#Signal generation + +Amp = 0.5 * 2**16 # -6 dBFS +Freq = 1e9 + +fs = int(tx.sample_rate) +print(fs) +N_tx = int(fs/Freq)*8 +T = N_tx / fs +t = np.linspace(0, T, N_tx) +tx_sig = Amp * np.sin(2 * math.pi * Freq * t) + +if dds_or_dma_signal : + tx.dds_enabled = [1] + tx.dds_single_tone(Freq,0.5) +else: + tx.tx(tx_sig) + +plt.plot(tx_sig) +plt.show() + +if dds_or_dma_signal == 0: + tx.tx_destroy_buffer() + +stdout, stderr = ssh._run(f"busybox devmem 0x{0x84a04000 + 0x0418:02x} 32 0x3")