From 08af95857527ae6e7568de120afcc3a0ca5edb5c Mon Sep 17 00:00:00 2001 From: IstvanZsSzekely <122256380+IstvanZsSzekely@users.noreply.github.com> Date: Thu, 5 Dec 2024 12:04:42 +0200 Subject: [PATCH] ad7606x: Updated testbenches (#144) Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com> --- testbenches/project/ad7606x/system_bd.tcl | 10 +- .../project/ad7606x/system_project.tcl | 8 - testbenches/project/ad7606x/system_tb.sv | 21 +- .../project/ad7606x/tests/test_program_4ch.sv | 490 +++++++------- .../project/ad7606x/tests/test_program_6ch.sv | 404 ++++++------ .../project/ad7606x/tests/test_program_8ch.sv | 493 +++++++------- .../project/ad7606x/tests/test_program_si.sv | 610 +++++++++--------- 7 files changed, 1000 insertions(+), 1036 deletions(-) diff --git a/testbenches/project/ad7606x/system_bd.tcl b/testbenches/project/ad7606x/system_bd.tcl index e41dc01f..46d20621 100755 --- a/testbenches/project/ad7606x/system_bd.tcl +++ b/testbenches/project/ad7606x/system_bd.tcl @@ -54,14 +54,10 @@ create_bd_port -dir O sys_clk ad_connect sys_clk sys_cpu_clk -set BA_AD7606X 0x44A00000 -adi_sim_add_define "AXI_AD7606X_BA=[format "%d" ${BA_AD7606X}]" - -set BA_SPI_REGMAP 0x44A00000 -adi_sim_add_define "SPI_AD7606_REGMAP_BA=[format "%d" ${BA_SPI_REGMAP}]" - if {$INTF == 0} { + set BA_AD7606X 0x44A00000 set_property offset $BA_AD7606X [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ad7606x}] + adi_sim_add_define "AXI_AD7606X_BA=[format "%d" ${BA_AD7606X}]" } else { create_bd_port -dir O spi_clk ad_connect spi_clk spi_clkgen/clk_0 @@ -69,7 +65,9 @@ if {$INTF == 0} { create_bd_port -dir O ad7606_irq ad_connect ad7606_irq spi_ad7606/irq + set BA_SPI_REGMAP 0x44A00000 set_property offset $BA_SPI_REGMAP [get_bd_addr_segs {mng_axi_vip/Master_AXI/spi_ad7606_axi_regmap}] + adi_sim_add_define "SPI_AD7606_REGMAP_BA=[format "%d" ${BA_SPI_REGMAP}]" set BA_CLKGEN 0x44A70000 set_property offset $BA_CLKGEN [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_spi_clkgen}] diff --git a/testbenches/project/ad7606x/system_project.tcl b/testbenches/project/ad7606x/system_project.tcl index 49fa4580..651ff7cb 100755 --- a/testbenches/project/ad7606x/system_project.tcl +++ b/testbenches/project/ad7606x/system_project.tcl @@ -13,14 +13,6 @@ source "cfgs/${cfg_file}" # Set the project name set project_name [file rootname $cfg_file] -# Set project params - -global ad_project_params - -set INTF $ad_project_params(INTF) -set ADC_N_BITS $ad_project_params(ADC_N_BITS) -set NUM_OF_SDI $ad_project_params(NUM_OF_SDI) - #set a default test program adi_sim_add_define "TEST_PROGRAM=test_program_si" diff --git a/testbenches/project/ad7606x/system_tb.sv b/testbenches/project/ad7606x/system_tb.sv index f1c0f5c6..db6083ae 100755 --- a/testbenches/project/ad7606x/system_tb.sv +++ b/testbenches/project/ad7606x/system_tb.sv @@ -60,9 +60,6 @@ module system_tb(); wire [4:0] num_chs; - parameter ADC_N_BITS = 16; - localparam NEG_EDGE = 1; - `TEST_PROGRAM test( .adc_config_mode (adc_config_mode), .rx_cnvst_n (rx_cnvst_n), @@ -113,14 +110,14 @@ module system_tb(); end else //serial interface begin - wire ad7606_spi_sclk; - wire ad7606_spi_sdo; - wire [`NUM_OF_SDI-1:0] ad7606_spi_sdi; - wire ad7606_spi_cs; - wire spi_clk; - wire adc_busy; - wire adc_cnvst_n; - wire ad7606_irq; + wire ad7606_spi_sclk; + wire ad7606_spi_sdo; + wire [`NUM_OF_SDI-1:0] ad7606_spi_sdi; + wire ad7606_spi_cs; + wire spi_clk; + wire adc_busy; + wire adc_cnvst_n; + wire ad7606_irq; `TEST_PROGRAM test( .spi_clk (spi_clk), @@ -141,6 +138,6 @@ module system_tb(); assign adc_busy = adc_cnvst_n; end - endgenerate + endgenerate endmodule diff --git a/testbenches/project/ad7606x/tests/test_program_4ch.sv b/testbenches/project/ad7606x/tests/test_program_4ch.sv index 6c52d67e..0bcedcfb 100755 --- a/testbenches/project/ad7606x/tests/test_program_4ch.sv +++ b/testbenches/project/ad7606x/tests/test_program_4ch.sv @@ -47,12 +47,12 @@ import adi_regmap_common_pkg::*; import adi_regmap_dmac_pkg::*; import adi_regmap_pwm_gen_pkg::*; -parameter SIMPLE_STATUS_CRC = 0; +localparam SIMPLE_STATUS_CRC = 0; -parameter CH0 = 8'h00 * 4; -parameter CH1 = 8'h10 * 4; -parameter CH2 = 8'h20 * 4; -parameter CH3 = 8'h30 * 4; +localparam CH0 = 8'h00 * 4; +localparam CH1 = 8'h10 * 4; +localparam CH2 = 8'h20 * 4; +localparam CH3 = 8'h30 * 4; program test_program_4ch ( input rx_cnvst_n, @@ -67,82 +67,78 @@ program test_program_4ch ( input [15:0] rx_db_o, input sys_clk, output rx_busy, - output bit [2:0] adc_config_mode); + output logic [2:0] adc_config_mode); -test_harness_env env; + test_harness_env env; -// -------------------------- -// Wrapper function for AXI read verif -// -------------------------- -task axi_read_v( + // -------------------------- + // Wrapper function for AXI read verif + // -------------------------- + task axi_read_v( input [31:0] raddr, input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); -endtask + env.mng.RegReadVerify32(raddr,vdata); + endtask -task axi_read( + task axi_read( input [31:0] raddr, output [31:0] data); - env.mng.RegRead32(raddr,data); -endtask + env.mng.RegRead32(raddr,data); + endtask -// -------------------------- -// Wrapper function for AXI write -// -------------------------- -task axi_write( - input [31:0] waddr, - input [31:0] wdata); + // -------------------------- + // Wrapper function for AXI write + // -------------------------- + task axi_write( + input [31:0] waddr, + input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); -endtask + env.mng.RegWrite32(waddr,wdata); + endtask -// -------------------------- -// Main procedure -// -------------------------- -initial begin + // -------------------------- + // Main procedure + // -------------------------- + initial begin - //creating environment - env = new("AD7606X Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + //creating environment + env = new("AD7606X Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); - setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); + setLoggerVerbosity(ADI_VERBOSITY_NONE); - //asserts all the resets for 100 ns - `TH.`SYS_RST.inst.IF.assert_reset; - #100 - `TH.`SYS_RST.inst.IF.deassert_reset; - #100 + env.start(); + env.sys_reset(); - sanity_test(); + sanity_test(); - #100 adc_config_number_of_channels(); + #100 adc_config_number_of_channels(); - #100 adc_config_SIMPLE_test(); + #100 adc_config_SIMPLE_test(); - #200 adc_config_CRC_test(); + #200 adc_config_CRC_test(); - #200 adc_config_STATUS_test(); + #200 adc_config_STATUS_test(); - #200 adc_config_STATUS_CRC_test(); + #200 adc_config_STATUS_CRC_test(); - #200 adc_config_SIMPLE_test(); + #200 adc_config_SIMPLE_test(); - #100 db_transmission_test(); + #100 db_transmission_test(); - env.stop(); + env.stop(); - `INFO(("Test Done"), ADI_VERBOSITY_NONE); - $finish; + `INFO(("Test Done"), ADI_VERBOSITY_NONE); + $finish; -end + end // fixed data for channels bit [(`ADC_N_BITS == 18 ? 17 : 15):0] tx_ch1 = (`ADC_N_BITS == 18) ? 18'hAB322 : 16'hACCA; @@ -171,210 +167,211 @@ end wire [4:0] num_of_transfers; assign num_of_transfers = (`ADC_N_BITS == 16) ? ((adc_config_mode == 0 ? 8 : (adc_config_mode == 1 ? 9 : (adc_config_mode == 2 ? 16 : 17)))) : ((adc_config_mode == 0 || adc_config_mode == 2) ? 16 : 17); -//--------------------------------------------------------------------------- -// Sanity test reg interface -//--------------------------------------------------------------------------- + //--------------------------------------------------------------------------- + // Sanity test reg interface + //--------------------------------------------------------------------------- -task sanity_test(); + task sanity_test(); // check ADC VERSION axi_read_v (`AXI_AD7606X_BA + GetAddrs(COMMON_REG_VERSION), `SET_COMMON_REG_VERSION_VERSION('h000a0300)); `INFO(("Sanity Test Done"), ADI_VERBOSITY_LOW); -endtask - -//--------------------------------------------------------------------------- -// Transfer Counter -//--------------------------------------------------------------------------- - -bit [31:0] transfer_cnt; -assign transfer_cnt = rx_ch_count; - -initial begin - while (1) begin - @(negedge rx_data_ready); - case (transfer_cnt) - 32'h00000000: tx_data_buf = 16'h0; - 32'h00000001: begin - if (`ADC_N_BITS == 16) begin - tx_data_buf = tx_ch1; - end else if (`ADC_N_BITS == 18) begin - tx_data_buf = tx_ch1[17:2]; - end - end - 32'h00000002: begin - if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin - tx_data_buf = {8'b0,tx_status_1}; - end else if ((`ADC_N_BITS == 16) && (adc_config_mode == 0 || adc_config_mode == 1)) begin - tx_data_buf = tx_ch2; - end - if (`ADC_N_BITS == 18) begin - if (adc_config_mode == 0 || adc_config_mode == 1) begin - tx_data_buf = {tx_ch1[1:0],14'b0}; - end else if (adc_config_mode == 2 || adc_config_mode == 3) begin - tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + endtask + + //--------------------------------------------------------------------------- + // Transfer Counter + //--------------------------------------------------------------------------- + + bit [31:0] transfer_cnt; + assign transfer_cnt = rx_ch_count; + + initial begin + forever begin + @(negedge rx_data_ready); + case (transfer_cnt) + 32'h00000000: tx_data_buf = 16'h0; + 32'h00000001: begin + if (`ADC_N_BITS == 16) begin + tx_data_buf = tx_ch1; + end else if (`ADC_N_BITS == 18) begin + tx_data_buf = tx_ch1[17:2]; end end - end - 32'h00000003: begin - tx_data_buf = tx_ch3; - if (`ADC_N_BITS == 18) begin - tx_data_buf = tx_ch2[17:2]; - end - end - 32'h00000004: begin - if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin - tx_data_buf = {8'b0,tx_status_2}; - end else if ((`ADC_N_BITS == 16) && (adc_config_mode == 0 || adc_config_mode == 1)) begin - tx_data_buf = tx_ch4; - end - if (`ADC_N_BITS == 18) begin - if (adc_config_mode == 0 || adc_config_mode == 1) begin - tx_data_buf = {tx_ch1[1:0],14'b0}; - end else if (adc_config_mode == 2 || adc_config_mode == 3) begin - tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + 32'h00000002: begin + if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin + tx_data_buf = {8'b0,tx_status_1}; + end else if ((`ADC_N_BITS == 16) && (adc_config_mode == 0 || adc_config_mode == 1)) begin + tx_data_buf = tx_ch2; end - end - end - 32'h00000005: begin - tx_data_buf = tx_ch5; - if (`ADC_N_BITS == 18) begin - tx_data_buf = tx_ch3[17:2]; - end - end - 32'h00000006: begin - if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin - tx_data_buf = {8'b0,tx_status_3}; - end else if ((`ADC_N_BITS == 16) && (adc_config_mode == 0 || adc_config_mode == 1)) begin - tx_data_buf = tx_ch6; - end - if (`ADC_N_BITS == 18) begin - if (adc_config_mode == 0 || adc_config_mode == 1) begin - tx_data_buf = {tx_ch1[1:0],14'b0}; - end else if (adc_config_mode == 2 || adc_config_mode == 3) begin - tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + if (`ADC_N_BITS == 18) begin + if (adc_config_mode == 0 || adc_config_mode == 1) begin + tx_data_buf = {tx_ch1[1:0],14'b0}; + end else if (adc_config_mode == 2 || adc_config_mode == 3) begin + tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + end end end - end - 32'h00000007: begin - tx_data_buf = tx_ch7; - if (`ADC_N_BITS == 18) begin - tx_data_buf = tx_ch4[17:2]; - end - end - 32'h00000008: begin - if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin - tx_data_buf = {8'b0,tx_status_4}; - end else if ((`ADC_N_BITS == 16) && (adc_config_mode == 0 || adc_config_mode == 1)) begin - tx_data_buf = tx_ch8; + 32'h00000003: begin + tx_data_buf = tx_ch3; + if (`ADC_N_BITS == 18) begin + tx_data_buf = tx_ch2[17:2]; + end end - if (`ADC_N_BITS == 18) begin - if (adc_config_mode == 0 || adc_config_mode == 1) begin - tx_data_buf = {tx_ch1[1:0],14'b0}; - end else if (adc_config_mode == 2 || adc_config_mode == 3) begin - tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + 32'h00000004: begin + if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin + tx_data_buf = {8'b0,tx_status_2}; + end else if ((`ADC_N_BITS == 16) && (adc_config_mode == 0 || adc_config_mode == 1)) begin + tx_data_buf = tx_ch4; + end + if (`ADC_N_BITS == 18) begin + if (adc_config_mode == 0 || adc_config_mode == 1) begin + tx_data_buf = {tx_ch1[1:0],14'b0}; + end else if (adc_config_mode == 2 || adc_config_mode == 3) begin + tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + end end end - end - 32'h00000009: begin - if (`ADC_N_BITS == 18) begin - tx_data_buf = tx_ch5[17:2]; - end else begin - tx_data_buf = tx_crc; + 32'h00000005: begin + tx_data_buf = tx_ch5; + if (`ADC_N_BITS == 18) begin + tx_data_buf = tx_ch3[17:2]; + end end - end - 32'h0000000A: begin - if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin - tx_data_buf = {8'b0,tx_status_5}; + 32'h00000006: begin + if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin + tx_data_buf = {8'b0,tx_status_3}; + end else if ((`ADC_N_BITS == 16) && (adc_config_mode == 0 || adc_config_mode == 1)) begin + tx_data_buf = tx_ch6; + end + if (`ADC_N_BITS == 18) begin + if (adc_config_mode == 0 || adc_config_mode == 1) begin + tx_data_buf = {tx_ch1[1:0],14'b0}; + end else if (adc_config_mode == 2 || adc_config_mode == 3) begin + tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + end + end end - if (`ADC_N_BITS == 18) begin - if (adc_config_mode == 0 || adc_config_mode == 1) begin - tx_data_buf = {tx_ch1[1:0],14'b0}; - end else if (adc_config_mode == 2 || adc_config_mode == 3) begin - tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + 32'h00000007: begin + tx_data_buf = tx_ch7; + if (`ADC_N_BITS == 18) begin + tx_data_buf = tx_ch4[17:2]; end end - end - 32'h0000000B: begin - if (`ADC_N_BITS == 18) begin - tx_data_buf = tx_ch6[17:2]; + 32'h00000008: begin + if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin + tx_data_buf = {8'b0,tx_status_4}; + end else if ((`ADC_N_BITS == 16) && (adc_config_mode == 0 || adc_config_mode == 1)) begin + tx_data_buf = tx_ch8; + end + if (`ADC_N_BITS == 18) begin + if (adc_config_mode == 0 || adc_config_mode == 1) begin + tx_data_buf = {tx_ch1[1:0],14'b0}; + end else if (adc_config_mode == 2 || adc_config_mode == 3) begin + tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + end + end end - end - 32'h0000000C: begin - if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin - tx_data_buf = {8'b0,tx_status_6}; + 32'h00000009: begin + if (`ADC_N_BITS == 18) begin + tx_data_buf = tx_ch5[17:2]; + end else begin + tx_data_buf = tx_crc; + end end - if (`ADC_N_BITS == 18) begin - if (adc_config_mode == 0 || adc_config_mode == 1) begin - tx_data_buf = {tx_ch1[1:0],14'b0}; - end else if (adc_config_mode == 2 || adc_config_mode == 3) begin - tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + 32'h0000000A: begin + if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin + tx_data_buf = {8'b0,tx_status_5}; + end + if (`ADC_N_BITS == 18) begin + if (adc_config_mode == 0 || adc_config_mode == 1) begin + tx_data_buf = {tx_ch1[1:0],14'b0}; + end else if (adc_config_mode == 2 || adc_config_mode == 3) begin + tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + end end end - end - 32'h0000000D: begin - if (`ADC_N_BITS == 18) begin - tx_data_buf = tx_ch7[17:2]; + 32'h0000000B: begin + if (`ADC_N_BITS == 18) begin + tx_data_buf = tx_ch6[17:2]; + end end - end - 32'h0000000E: begin - if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin - tx_data_buf = {8'b0,tx_status_7}; + 32'h0000000C: begin + if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin + tx_data_buf = {8'b0,tx_status_6}; + end + if (`ADC_N_BITS == 18) begin + if (adc_config_mode == 0 || adc_config_mode == 1) begin + tx_data_buf = {tx_ch1[1:0],14'b0}; + end else if (adc_config_mode == 2 || adc_config_mode == 3) begin + tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + end + end end - if (`ADC_N_BITS == 18) begin - if (adc_config_mode == 0 || adc_config_mode == 1) begin - tx_data_buf = {tx_ch1[1:0],14'b0}; - end else if (adc_config_mode == 2 || adc_config_mode == 3) begin - tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + 32'h0000000D: begin + if (`ADC_N_BITS == 18) begin + tx_data_buf = tx_ch7[17:2]; end end - end - 32'h0000000F: begin - if (`ADC_N_BITS == 18) begin - tx_data_buf = tx_ch8[17:2]; + 32'h0000000E: begin + if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin + tx_data_buf = {8'b0,tx_status_7}; + end + if (`ADC_N_BITS == 18) begin + if (adc_config_mode == 0 || adc_config_mode == 1) begin + tx_data_buf = {tx_ch1[1:0],14'b0}; + end else if (adc_config_mode == 2 || adc_config_mode == 3) begin + tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + end + end end - end - 32'h00000010: begin - if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin - tx_data_buf = {8'b0,tx_status_8}; + 32'h0000000F: begin + if (`ADC_N_BITS == 18) begin + tx_data_buf = tx_ch8[17:2]; + end end - if (`ADC_N_BITS == 18) begin - if (adc_config_mode == 0 || adc_config_mode == 1) begin - tx_data_buf = {tx_ch1[1:0],14'b0}; - end else if (adc_config_mode == 2 || adc_config_mode == 3) begin - tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + 32'h00000010: begin + if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin + tx_data_buf = {8'b0,tx_status_8}; + end + if (`ADC_N_BITS == 18) begin + if (adc_config_mode == 0 || adc_config_mode == 1) begin + tx_data_buf = {tx_ch1[1:0],14'b0}; + end else if (adc_config_mode == 2 || adc_config_mode == 3) begin + tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + end end end - end - 32'h00000011: begin - if ((`ADC_N_BITS == 16) && adc_config_mode == 3) begin - tx_data_buf = {8'b0,tx_status_8}; - end else if (`ADC_N_BITS == 18 && (adc_config_mode == 1 || adc_config_mode == 3)) begin - tx_data_buf = tx_crc; + 32'h00000011: begin + if ((`ADC_N_BITS == 16) && adc_config_mode == 3) begin + tx_data_buf = {8'b0,tx_status_8}; + end else if (`ADC_N_BITS == 18 && (adc_config_mode == 1 || adc_config_mode == 3)) begin + tx_data_buf = tx_crc; + end end - end - endcase + default: ; + endcase + end end -end - -//--------------------------------------------------------------------------- -// Configuration Test -//--------------------------------------------------------------------------- - -bit transfer_status = 0; -bit [31:0] config_CRC = 'h0; // CRC with channel static data setup -bit [31:0] config_SIMPLE = 'h0; // channel static data setup -bit [31:0] config_STATUS = 'h0; // channel static data setup + Status header -bit [31:0] config_STATUS_CRC = 'h0; // CRC with channel static data setup + Status header -bit [31:0] config_wr_CRC = 'h0; // write request sent result -bit [31:0] config_wr_SIMPLE = 'h0; // write request sent result -bit [31:0] config_wr_STATUS = 'h0; // write request sent result -bit [31:0] config_wr_STATUS_CRC = 'h0; // write request sent result -bit ctrl_status_CRC = 'h0; // ctrl_status bit from ADC common core -bit ctrl_status_SIMPLE = 'h0; // ctrl_status bit from ADC common core -bit ctrl_status_STATUS = 'h0; // ctrl_status bit from ADC common core -bit ctrl_status_STATUS_CRC = 'h0; // ctrl_status bit from ADC common core - -task adc_config_SIMPLE_test(); + + //--------------------------------------------------------------------------- + // Configuration Test + //--------------------------------------------------------------------------- + + bit transfer_status = 0; + bit [31:0] config_CRC = 'h0; // CRC with channel static data setup + bit [31:0] config_SIMPLE = 'h0; // channel static data setup + bit [31:0] config_STATUS = 'h0; // channel static data setup + Status header + bit [31:0] config_STATUS_CRC = 'h0; // CRC with channel static data setup + Status header + bit [31:0] config_wr_CRC = 'h0; // write request sent result + bit [31:0] config_wr_SIMPLE = 'h0; // write request sent result + bit [31:0] config_wr_STATUS = 'h0; // write request sent result + bit [31:0] config_wr_STATUS_CRC = 'h0; // write request sent result + bit ctrl_status_CRC = 'h0; // ctrl_status bit from ADC common core + bit ctrl_status_SIMPLE = 'h0; // ctrl_status bit from ADC common core + bit ctrl_status_STATUS = 'h0; // ctrl_status bit from ADC common core + bit ctrl_status_STATUS_CRC = 'h0; // ctrl_status bit from ADC common core + + task adc_config_SIMPLE_test(); axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1'b1)); //ADC common core out of reset axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), `SET_ADC_COMMON_REG_ADC_CONFIG_WR_ADC_CONFIG_WR(32'h00002181)); // set static data setup in device's reg 0x21 axi_read(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), config_SIMPLE); // read last config result @@ -397,9 +394,9 @@ task adc_config_SIMPLE_test(); axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_CNTRL_3), 'h100); // set default adc_config_mode = 3'h0; -endtask + endtask -task adc_config_CRC_test(); + task adc_config_CRC_test(); axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1'b1)); //ADC common core out of reset axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), `SET_ADC_COMMON_REG_ADC_CONFIG_WR_ADC_CONFIG_WR(32'h00002185)); // set CRC and static data setup in device's reg 0x21 axi_read(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), config_CRC); // read last config result @@ -422,9 +419,9 @@ task adc_config_CRC_test(); axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_CNTRL_3), 'h101); // set default adc_config_mode = 3'h1; -endtask + endtask -task adc_config_STATUS_test(); + task adc_config_STATUS_test(); axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1'b1)); //ADC common core out of reset axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), `SET_ADC_COMMON_REG_ADC_CONFIG_WR_ADC_CONFIG_WR(32'h00002181)); // static data setup in device's reg 0x21 axi_read(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), config_STATUS); // read last config result @@ -460,9 +457,9 @@ task adc_config_STATUS_test(); axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_CNTRL_3), 'h102); // set default adc_config_mode = 3'h2; -endtask + endtask -task adc_config_STATUS_CRC_test(); + task adc_config_STATUS_CRC_test(); axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1'b1)); //ADC common core out of reset axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), `SET_ADC_COMMON_REG_ADC_CONFIG_WR_ADC_CONFIG_WR(32'h00002185)); // static data and CRC setup in device's reg 0x21 axi_read(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), config_STATUS); // read last config result @@ -498,27 +495,26 @@ task adc_config_STATUS_CRC_test(); axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_CNTRL_3), 'h103); // set default adc_config_mode = 3'h3; -endtask + endtask -task adc_config_number_of_channels(); - + task adc_config_number_of_channels(); axi_write (`AXI_AD7606X_BA + CH0 + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL),`SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); axi_write (`AXI_AD7606X_BA + CH1 + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL),`SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); axi_write (`AXI_AD7606X_BA + CH2 + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL),`SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); axi_write (`AXI_AD7606X_BA + CH3 + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL),`SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); - //set HDL config mode - // axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_CNTRL_3), 'h103); // set default + //set HDL config mode + // axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_CNTRL_3), 'h103); // set default adc_config_mode = 3'h4; -endtask + endtask -//--------------------------------------------------------------------------- -// DB transmission test -//--------------------------------------------------------------------------- -bit [31:0] capp_word; -task db_transmission_test(); - #100 transfer_status = 1; + //--------------------------------------------------------------------------- + // DB transmission test + //--------------------------------------------------------------------------- + bit [31:0] capp_word; + task db_transmission_test(); + transfer_status = 1; // Generate cnvst_n pulse using AXI_PWM_GEN axi_write (`AXI_PWMGEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_RESET(1)); // PWM_GEN reset in regmap (ACTIVE HIGH) @@ -533,6 +529,6 @@ task db_transmission_test(); // Stop pwm gen axi_write (`AXI_PWMGEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_RESET(1)); `INFO(("Axi_pwm_gen stopped"), ADI_VERBOSITY_LOW); -endtask + endtask endprogram diff --git a/testbenches/project/ad7606x/tests/test_program_6ch.sv b/testbenches/project/ad7606x/tests/test_program_6ch.sv index c99f6408..2613b3bc 100755 --- a/testbenches/project/ad7606x/tests/test_program_6ch.sv +++ b/testbenches/project/ad7606x/tests/test_program_6ch.sv @@ -47,14 +47,14 @@ import adi_regmap_common_pkg::*; import adi_regmap_dmac_pkg::*; import adi_regmap_pwm_gen_pkg::*; -parameter SIMPLE_STATUS_CRC = 0; +localparam SIMPLE_STATUS_CRC = 0; -parameter CH0 = 8'h00 * 4; -parameter CH1 = 8'h10 * 4; -parameter CH2 = 8'h20 * 4; -parameter CH3 = 8'h30 * 4; -parameter CH4 = 8'h40 * 4; -parameter CH5 = 8'h50 * 4; +localparam CH0 = 8'h00 * 4; +localparam CH1 = 8'h10 * 4; +localparam CH2 = 8'h20 * 4; +localparam CH3 = 8'h30 * 4; +localparam CH4 = 8'h40 * 4; +localparam CH5 = 8'h50 * 4; program test_program_6ch ( input rx_cnvst_n, @@ -69,81 +69,76 @@ program test_program_6ch ( input [15:0] rx_db_o, input sys_clk, output rx_busy, - output bit [2:0] adc_config_mode); + output logic [2:0] adc_config_mode); -test_harness_env env; + test_harness_env env; -// -------------------------- -// Wrapper function for AXI read verif -// -------------------------- -task axi_read_v( + // -------------------------- + // Wrapper function for AXI read verif + // -------------------------- + task axi_read_v( input [31:0] raddr, input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); -endtask + env.mng.RegReadVerify32(raddr,vdata); + endtask -task axi_read( + task axi_read( input [31:0] raddr, output [31:0] data); - env.mng.RegRead32(raddr,data); -endtask + env.mng.RegRead32(raddr,data); + endtask -// -------------------------- -// Wrapper function for AXI write -// -------------------------- -task axi_write( - input [31:0] waddr, - input [31:0] wdata); + // -------------------------- + // Wrapper function for AXI write + // -------------------------- + task axi_write( + input [31:0] waddr, + input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); -endtask + env.mng.RegWrite32(waddr,wdata); + endtask -// -------------------------- -// Main procedure -// -------------------------- -initial begin + // -------------------------- + // Main procedure + // -------------------------- + initial begin - //creating environment - env = new("AD7616 Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + //creating environment + env = new("AD7606X Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); - setLoggerVerbosity(6); - env.start(); + setLoggerVerbosity(ADI_VERBOSITY_NONE); - //asserts all the resets for 100 ns - `TH.`SYS_RST.inst.IF.assert_reset; - #100 - `TH.`SYS_RST.inst.IF.deassert_reset; - #100 + env.start(); + env.sys_reset(); - sanity_test(); + sanity_test(); - #100 adc_config_number_of_channels(); + #100 adc_config_number_of_channels(); - #100 adc_config_SIMPLE_test(); + #100 adc_config_SIMPLE_test(); - #200 adc_config_CRC_test(); + #200 adc_config_CRC_test(); - #200 adc_config_STATUS_test(); + #200 adc_config_STATUS_test(); - #200 adc_config_STATUS_CRC_test(); + #200 adc_config_STATUS_CRC_test(); - #200 adc_config_SIMPLE_test(); + #200 adc_config_SIMPLE_test(); - #100 db_transmission_test(); + #100 db_transmission_test(); - `INFO(("Test Done"), ADI_VERBOSITY_NONE); + `INFO(("Test Done"), ADI_VERBOSITY_NONE); + $finish; - $finish; - -end + end // fixed data for channels bit [(`ADC_N_BITS == 18 ? 17 : 15):0] tx_ch1 = (`ADC_N_BITS == 18) ? 18'hAB322 : 16'hACCA; @@ -170,152 +165,150 @@ end wire [4:0] num_of_transfers; assign num_of_transfers = (`ADC_N_BITS == 16) ? ((adc_config_mode == 0 ? 8 : (adc_config_mode == 1 ? 9 : (adc_config_mode == 2 ? 16 : 17)))) : ((adc_config_mode == 0 || adc_config_mode == 2) ? 16 : 17); -//--------------------------------------------------------------------------- -// Sanity test reg interface -//--------------------------------------------------------------------------- - -task sanity_test(); - // check ADC VERSION - axi_read_v (`AXI_AD7606X_BA + GetAddrs(COMMON_REG_VERSION), - `SET_COMMON_REG_VERSION_VERSION('h000a0300)); - `INFO(("Sanity Test Done."), ADI_VERBOSITY_LOW); -endtask - -//--------------------------------------------------------------------------- -// Transfer Counter -//--------------------------------------------------------------------------- - -bit [31:0] transfer_cnt; -assign transfer_cnt = rx_ch_count; - -initial begin - while (1) begin - @(negedge rx_data_ready); - case (transfer_cnt) - 32'h00000000: tx_data_buf = 16'h0; - 32'h00000001: begin - if (`ADC_N_BITS == 16) begin - tx_data_buf = tx_ch1; - end else if (`ADC_N_BITS == 18) begin - tx_data_buf = tx_ch1[17:2]; - end - end - 32'h00000002: begin - if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin - tx_data_buf = {8'b0,tx_status_1}; - end else if ((`ADC_N_BITS == 16) && (adc_config_mode == 0 || adc_config_mode == 1)) begin - tx_data_buf = tx_ch2; - end - if (`ADC_N_BITS == 18) begin - if (adc_config_mode == 0 || adc_config_mode == 1) begin - tx_data_buf = {tx_ch1[1:0],14'b0}; - end else if (adc_config_mode == 2 || adc_config_mode == 3) begin - tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + //--------------------------------------------------------------------------- + // Sanity test reg interface + //--------------------------------------------------------------------------- + + task sanity_test(); + // check ADC VERSION + axi_read_v (`AXI_AD7606X_BA + GetAddrs(COMMON_REG_VERSION), + `SET_COMMON_REG_VERSION_VERSION('h000a0300)); + `INFO(("Sanity Test Done."), ADI_VERBOSITY_LOW); + endtask + + //--------------------------------------------------------------------------- + // Transfer Counter + //--------------------------------------------------------------------------- + + bit [31:0] transfer_cnt; + assign transfer_cnt = rx_ch_count; + + initial begin + forever begin + @(negedge rx_data_ready); + case (transfer_cnt) + 32'h00000000: tx_data_buf = 16'h0; + 32'h00000001: begin + if (`ADC_N_BITS == 16) begin + tx_data_buf = tx_ch1; + end else if (`ADC_N_BITS == 18) begin + tx_data_buf = tx_ch1[17:2]; end end - end - 32'h00000003: begin - tx_data_buf = tx_ch3; - if (`ADC_N_BITS == 18) begin - tx_data_buf = tx_ch2[17:2]; - end - end - 32'h00000004: begin - if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin - tx_data_buf = {8'b0,tx_status_2}; - end else if ((`ADC_N_BITS == 16) && (adc_config_mode == 0 || adc_config_mode == 1)) begin - tx_data_buf = tx_ch4; - end - if (`ADC_N_BITS == 18) begin - if (adc_config_mode == 0 || adc_config_mode == 1) begin - tx_data_buf = {tx_ch1[1:0],14'b0}; - end else if (adc_config_mode == 2 || adc_config_mode == 3) begin - tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + 32'h00000002: begin + if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin + tx_data_buf = {8'b0,tx_status_1}; + end else if ((`ADC_N_BITS == 16) && (adc_config_mode == 0 || adc_config_mode == 1)) begin + tx_data_buf = tx_ch2; + end + if (`ADC_N_BITS == 18) begin + if (adc_config_mode == 0 || adc_config_mode == 1) begin + tx_data_buf = {tx_ch1[1:0],14'b0}; + end else if (adc_config_mode == 2 || adc_config_mode == 3) begin + tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + end end end - end - 32'h00000005: begin - tx_data_buf = tx_ch5; - if (`ADC_N_BITS == 18) begin - tx_data_buf = tx_ch3[17:2]; - end - end - 32'h00000006: begin - if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin - tx_data_buf = {8'b0,tx_status_3}; - end else if ((`ADC_N_BITS == 16) && (adc_config_mode == 0 || adc_config_mode == 1)) begin - tx_data_buf = tx_ch6; + 32'h00000003: begin + tx_data_buf = tx_ch3; + if (`ADC_N_BITS == 18) begin + tx_data_buf = tx_ch2[17:2]; + end end - if (`ADC_N_BITS == 18) begin - if (adc_config_mode == 0 || adc_config_mode == 1) begin - tx_data_buf = {tx_ch1[1:0],14'b0}; - end else if (adc_config_mode == 2 || adc_config_mode == 3) begin - tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + 32'h00000004: begin + if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin + tx_data_buf = {8'b0,tx_status_2}; + end else if ((`ADC_N_BITS == 16) && (adc_config_mode == 0 || adc_config_mode == 1)) begin + tx_data_buf = tx_ch4; + end + if (`ADC_N_BITS == 18) begin + if (adc_config_mode == 0 || adc_config_mode == 1) begin + tx_data_buf = {tx_ch1[1:0],14'b0}; + end else if (adc_config_mode == 2 || adc_config_mode == 3) begin + tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + end end end - end - - - 32'h00000009: begin - if (`ADC_N_BITS == 18) begin - tx_data_buf = tx_ch5[17:2]; - end else begin - tx_data_buf = tx_crc; + 32'h00000005: begin + tx_data_buf = tx_ch5; + if (`ADC_N_BITS == 18) begin + tx_data_buf = tx_ch3[17:2]; + end end - end - 32'h0000000A: begin - if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin - tx_data_buf = {8'b0,tx_status_5}; + 32'h00000006: begin + if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin + tx_data_buf = {8'b0,tx_status_3}; + end else if ((`ADC_N_BITS == 16) && (adc_config_mode == 0 || adc_config_mode == 1)) begin + tx_data_buf = tx_ch6; + end + if (`ADC_N_BITS == 18) begin + if (adc_config_mode == 0 || adc_config_mode == 1) begin + tx_data_buf = {tx_ch1[1:0],14'b0}; + end else if (adc_config_mode == 2 || adc_config_mode == 3) begin + tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + end + end end - if (`ADC_N_BITS == 18) begin - if (adc_config_mode == 0 || adc_config_mode == 1) begin - tx_data_buf = {tx_ch1[1:0],14'b0}; - end else if (adc_config_mode == 2 || adc_config_mode == 3) begin - tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + 32'h00000009: begin + if (`ADC_N_BITS == 18) begin + tx_data_buf = tx_ch5[17:2]; + end else begin + tx_data_buf = tx_crc; end end - end - 32'h0000000B: begin - if (`ADC_N_BITS == 18) begin - tx_data_buf = tx_ch6[17:2]; + 32'h0000000A: begin + if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin + tx_data_buf = {8'b0,tx_status_5}; + end + if (`ADC_N_BITS == 18) begin + if (adc_config_mode == 0 || adc_config_mode == 1) begin + tx_data_buf = {tx_ch1[1:0],14'b0}; + end else if (adc_config_mode == 2 || adc_config_mode == 3) begin + tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + end + end end - end - 32'h0000000C: begin - if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin - tx_data_buf = {8'b0,tx_status_6}; + 32'h0000000B: begin + if (`ADC_N_BITS == 18) begin + tx_data_buf = tx_ch6[17:2]; + end end - if (`ADC_N_BITS == 18) begin - if (adc_config_mode == 0 || adc_config_mode == 1) begin - tx_data_buf = {tx_ch1[1:0],14'b0}; - end else if (adc_config_mode == 2 || adc_config_mode == 3) begin - tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + 32'h0000000C: begin + if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin + tx_data_buf = {8'b0,tx_status_6}; + end + if (`ADC_N_BITS == 18) begin + if (adc_config_mode == 0 || adc_config_mode == 1) begin + tx_data_buf = {tx_ch1[1:0],14'b0}; + end else if (adc_config_mode == 2 || adc_config_mode == 3) begin + tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + end end end - end - - endcase + default: ; + endcase + end end -end - -//--------------------------------------------------------------------------- -// Configuration Test -//--------------------------------------------------------------------------- - -bit transfer_status = 0; -bit [31:0] config_CRC = 'h0; // CRC with channel static data setup -bit [31:0] config_SIMPLE = 'h0; // channel static data setup -bit [31:0] config_STATUS = 'h0; // channel static data setup + Status header -bit [31:0] config_STATUS_CRC = 'h0; // CRC with channel static data setup + Status header -bit [31:0] config_wr_CRC = 'h0; // write request sent result -bit [31:0] config_wr_SIMPLE = 'h0; // write request sent result -bit [31:0] config_wr_STATUS = 'h0; // write request sent result -bit [31:0] config_wr_STATUS_CRC = 'h0; // write request sent result -bit ctrl_status_CRC = 'h0; // ctrl_status bit from ADC common core -bit ctrl_status_SIMPLE = 'h0; // ctrl_status bit from ADC common core -bit ctrl_status_STATUS = 'h0; // ctrl_status bit from ADC common core -bit ctrl_status_STATUS_CRC = 'h0; // ctrl_status bit from ADC common core - -task adc_config_SIMPLE_test(); + + //--------------------------------------------------------------------------- + // Configuration Test + //--------------------------------------------------------------------------- + + bit transfer_status = 0; + bit [31:0] config_CRC = 'h0; // CRC with channel static data setup + bit [31:0] config_SIMPLE = 'h0; // channel static data setup + bit [31:0] config_STATUS = 'h0; // channel static data setup + Status header + bit [31:0] config_STATUS_CRC = 'h0; // CRC with channel static data setup + Status header + bit [31:0] config_wr_CRC = 'h0; // write request sent result + bit [31:0] config_wr_SIMPLE = 'h0; // write request sent result + bit [31:0] config_wr_STATUS = 'h0; // write request sent result + bit [31:0] config_wr_STATUS_CRC = 'h0; // write request sent result + bit ctrl_status_CRC = 'h0; // ctrl_status bit from ADC common core + bit ctrl_status_SIMPLE = 'h0; // ctrl_status bit from ADC common core + bit ctrl_status_STATUS = 'h0; // ctrl_status bit from ADC common core + bit ctrl_status_STATUS_CRC = 'h0; // ctrl_status bit from ADC common core + + task adc_config_SIMPLE_test(); axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1'b1)); //ADC common core out of reset axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), `SET_ADC_COMMON_REG_ADC_CONFIG_WR_ADC_CONFIG_WR(32'h00002181)); // set static data setup in device's reg 0x21 axi_read(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), config_SIMPLE); // read last config result @@ -338,9 +331,9 @@ task adc_config_SIMPLE_test(); axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_CNTRL_3), 'h100); // set default adc_config_mode = 3'h0; -endtask + endtask -task adc_config_CRC_test(); + task adc_config_CRC_test(); axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1'b1)); //ADC common core out of reset axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), `SET_ADC_COMMON_REG_ADC_CONFIG_WR_ADC_CONFIG_WR(32'h00002185)); // set CRC and static data setup in device's reg 0x21 axi_read(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), config_CRC); // read last config result @@ -363,9 +356,9 @@ task adc_config_CRC_test(); axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_CNTRL_3), 'h101); // set default adc_config_mode = 3'h1; -endtask + endtask -task adc_config_STATUS_test(); + task adc_config_STATUS_test(); axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1'b1)); //ADC common core out of reset axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), `SET_ADC_COMMON_REG_ADC_CONFIG_WR_ADC_CONFIG_WR(32'h00002181)); // static data setup in device's reg 0x21 axi_read(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), config_STATUS); // read last config result @@ -401,9 +394,9 @@ task adc_config_STATUS_test(); axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_CNTRL_3), 'h102); // set default adc_config_mode = 3'h2; -endtask + endtask -task adc_config_STATUS_CRC_test(); + task adc_config_STATUS_CRC_test(); axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1'b1)); //ADC common core out of reset axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), `SET_ADC_COMMON_REG_ADC_CONFIG_WR_ADC_CONFIG_WR(32'h00002185)); // static data and CRC setup in device's reg 0x21 axi_read(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), config_STATUS); // read last config result @@ -439,10 +432,9 @@ task adc_config_STATUS_CRC_test(); axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_CNTRL_3), 'h103); // set default adc_config_mode = 3'h3; -endtask + endtask -task adc_config_number_of_channels(); - + task adc_config_number_of_channels(); axi_write (`AXI_AD7606X_BA + CH0 + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL),`SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); axi_write (`AXI_AD7606X_BA + CH1 + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL),`SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); axi_write (`AXI_AD7606X_BA + CH2 + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL),`SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); @@ -450,18 +442,18 @@ task adc_config_number_of_channels(); axi_write (`AXI_AD7606X_BA + CH4 + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL),`SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); axi_write (`AXI_AD7606X_BA + CH5 + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL),`SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); - //set HDL config mode - // axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_CNTRL_3), 'h103); // set default + //set HDL config mode + // axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_CNTRL_3), 'h103); // set default adc_config_mode = 3'h4; -endtask + endtask -//--------------------------------------------------------------------------- -// DB transmission test -//--------------------------------------------------------------------------- -bit [31:0] capp_word; -task db_transmission_test(); - #100 transfer_status = 1; + //--------------------------------------------------------------------------- + // DB transmission test + //--------------------------------------------------------------------------- + bit [31:0] capp_word; + task db_transmission_test(); + transfer_status = 1; // Generate cnvst_n pulse using AXI_PWM_GEN axi_write (`AXI_PWMGEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_RESET(1)); // PWM_GEN reset in regmap (ACTIVE HIGH) @@ -476,6 +468,6 @@ task db_transmission_test(); // Stop pwm gen axi_write (`AXI_PWMGEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_RESET(1)); `INFO(("axi_pwm_gen stopped."), ADI_VERBOSITY_LOW); -endtask + endtask endprogram diff --git a/testbenches/project/ad7606x/tests/test_program_8ch.sv b/testbenches/project/ad7606x/tests/test_program_8ch.sv index 93d5d69c..df553d99 100755 --- a/testbenches/project/ad7606x/tests/test_program_8ch.sv +++ b/testbenches/project/ad7606x/tests/test_program_8ch.sv @@ -47,16 +47,16 @@ import adi_regmap_common_pkg::*; import adi_regmap_dmac_pkg::*; import adi_regmap_pwm_gen_pkg::*; -parameter SIMPLE_STATUS_CRC = 0; +localparam SIMPLE_STATUS_CRC = 0; -parameter CH0 = 8'h00 * 4; -parameter CH1 = 8'h10 * 4; -parameter CH2 = 8'h20 * 4; -parameter CH3 = 8'h30 * 4; -parameter CH4 = 8'h40 * 4; -parameter CH5 = 8'h50 * 4; -parameter CH6 = 8'h60 * 4; -parameter CH7 = 8'h70 * 4; +localparam CH0 = 8'h00 * 4; +localparam CH1 = 8'h10 * 4; +localparam CH2 = 8'h20 * 4; +localparam CH3 = 8'h30 * 4; +localparam CH4 = 8'h40 * 4; +localparam CH5 = 8'h50 * 4; +localparam CH6 = 8'h60 * 4; +localparam CH7 = 8'h70 * 4; program test_program_8ch ( input rx_cnvst_n, @@ -71,81 +71,76 @@ program test_program_8ch ( input [15:0] rx_db_o, input sys_clk, output rx_busy, - output bit [2:0] adc_config_mode); + output logic [2:0] adc_config_mode); -test_harness_env env; + test_harness_env env; -// -------------------------- -// Wrapper function for AXI read verif -// -------------------------- -task axi_read_v( + // -------------------------- + // Wrapper function for AXI read verif + // -------------------------- + task axi_read_v( input [31:0] raddr, input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); -endtask + env.mng.RegReadVerify32(raddr,vdata); + endtask -task axi_read( + task axi_read( input [31:0] raddr, output [31:0] data); - env.mng.RegRead32(raddr,data); -endtask + env.mng.RegRead32(raddr,data); + endtask -// -------------------------- -// Wrapper function for AXI write -// -------------------------- -task axi_write( - input [31:0] waddr, - input [31:0] wdata); + // -------------------------- + // Wrapper function for AXI write + // -------------------------- + task axi_write( + input [31:0] waddr, + input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); -endtask + env.mng.RegWrite32(waddr,wdata); + endtask -// -------------------------- -// Main procedure -// -------------------------- -initial begin + // -------------------------- + // Main procedure + // -------------------------- + initial begin - //creating environment - env = new("AD7616 Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + //creating environment + env = new("AD7606X Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); - setLoggerVerbosity(6); - env.start(); + setLoggerVerbosity(ADI_VERBOSITY_NONE); - //asserts all the resets for 100 ns - `TH.`SYS_RST.inst.IF.assert_reset; - #100 - `TH.`SYS_RST.inst.IF.deassert_reset; - #100 + env.start(); + env.sys_reset(); - sanity_test(); + sanity_test(); - #100 adc_config_number_of_channels(); + #100 adc_config_number_of_channels(); - #100 adc_config_SIMPLE_test(); + #100 adc_config_SIMPLE_test(); - #200 adc_config_CRC_test(); + #200 adc_config_CRC_test(); - #200 adc_config_STATUS_test(); + #200 adc_config_STATUS_test(); - #200 adc_config_STATUS_CRC_test(); + #200 adc_config_STATUS_CRC_test(); - #200 adc_config_SIMPLE_test(); + #200 adc_config_SIMPLE_test(); - #100 db_transmission_test(); + #100 db_transmission_test(); - `INFO(("Test Done"), ADI_VERBOSITY_NONE); + `INFO(("Test Done"), ADI_VERBOSITY_NONE); + $finish; - $finish; - -end + end // fixed data for channels bit [(`ADC_N_BITS == 18 ? 17 : 15):0] tx_ch1 = (`ADC_N_BITS == 18) ? 18'hAB322 : 16'hACCA; @@ -174,210 +169,211 @@ end wire [4:0] num_of_transfers; assign num_of_transfers = (`ADC_N_BITS == 16) ? ((adc_config_mode == 0 ? 8 : (adc_config_mode == 1 ? 9 : (adc_config_mode == 2 ? 16 : 17)))) : ((adc_config_mode == 0 || adc_config_mode == 2) ? 16 : 17); -//--------------------------------------------------------------------------- -// Sanity test reg interface -//--------------------------------------------------------------------------- + //--------------------------------------------------------------------------- + // Sanity test reg interface + //--------------------------------------------------------------------------- -task sanity_test(); + task sanity_test(); // check ADC VERSION axi_read_v (`AXI_AD7606X_BA + GetAddrs(COMMON_REG_VERSION), `SET_COMMON_REG_VERSION_VERSION('h000a0300)); - $display("[%t] Sanity Test Done.", $time); -endtask - -//--------------------------------------------------------------------------- -// Transfer Counter -//--------------------------------------------------------------------------- - -bit [31:0] transfer_cnt; -assign transfer_cnt = rx_ch_count; - -initial begin - while (1) begin - @(negedge rx_data_ready); - case (transfer_cnt) - 32'h00000000: tx_data_buf = 16'h0; - 32'h00000001: begin - if (`ADC_N_BITS == 16) begin - tx_data_buf = tx_ch1; - end else if (`ADC_N_BITS == 18) begin - tx_data_buf = tx_ch1[17:2]; - end - end - 32'h00000002: begin - if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin - tx_data_buf = {8'b0,tx_status_1}; - end else if ((`ADC_N_BITS == 16) && (adc_config_mode == 0 || adc_config_mode == 1)) begin - tx_data_buf = tx_ch2; - end - if (`ADC_N_BITS == 18) begin - if (adc_config_mode == 0 || adc_config_mode == 1) begin - tx_data_buf = {tx_ch1[1:0],14'b0}; - end else if (adc_config_mode == 2 || adc_config_mode == 3) begin - tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + `INFO(("Sanity Test Done"), ADI_VERBOSITY_LOW); + endtask + + //--------------------------------------------------------------------------- + // Transfer Counter + //--------------------------------------------------------------------------- + + bit [31:0] transfer_cnt; + assign transfer_cnt = rx_ch_count; + + initial begin + forever begin + @(negedge rx_data_ready); + case (transfer_cnt) + 32'h00000000: tx_data_buf = 16'h0; + 32'h00000001: begin + if (`ADC_N_BITS == 16) begin + tx_data_buf = tx_ch1; + end else if (`ADC_N_BITS == 18) begin + tx_data_buf = tx_ch1[17:2]; end end - end - 32'h00000003: begin - tx_data_buf = tx_ch3; - if (`ADC_N_BITS == 18) begin - tx_data_buf = tx_ch2[17:2]; - end - end - 32'h00000004: begin - if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin - tx_data_buf = {8'b0,tx_status_2}; - end else if ((`ADC_N_BITS == 16) && (adc_config_mode == 0 || adc_config_mode == 1)) begin - tx_data_buf = tx_ch4; - end - if (`ADC_N_BITS == 18) begin - if (adc_config_mode == 0 || adc_config_mode == 1) begin - tx_data_buf = {tx_ch1[1:0],14'b0}; - end else if (adc_config_mode == 2 || adc_config_mode == 3) begin - tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + 32'h00000002: begin + if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin + tx_data_buf = {8'b0,tx_status_1}; + end else if ((`ADC_N_BITS == 16) && (adc_config_mode == 0 || adc_config_mode == 1)) begin + tx_data_buf = tx_ch2; end - end - end - 32'h00000005: begin - tx_data_buf = tx_ch5; - if (`ADC_N_BITS == 18) begin - tx_data_buf = tx_ch3[17:2]; - end - end - 32'h00000006: begin - if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin - tx_data_buf = {8'b0,tx_status_3}; - end else if ((`ADC_N_BITS == 16) && (adc_config_mode == 0 || adc_config_mode == 1)) begin - tx_data_buf = tx_ch6; - end - if (`ADC_N_BITS == 18) begin - if (adc_config_mode == 0 || adc_config_mode == 1) begin - tx_data_buf = {tx_ch1[1:0],14'b0}; - end else if (adc_config_mode == 2 || adc_config_mode == 3) begin - tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + if (`ADC_N_BITS == 18) begin + if (adc_config_mode == 0 || adc_config_mode == 1) begin + tx_data_buf = {tx_ch1[1:0],14'b0}; + end else if (adc_config_mode == 2 || adc_config_mode == 3) begin + tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + end end end - end - 32'h00000007: begin - tx_data_buf = tx_ch7; - if (`ADC_N_BITS == 18) begin - tx_data_buf = tx_ch4[17:2]; - end - end - 32'h00000008: begin - if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin - tx_data_buf = {8'b0,tx_status_4}; - end else if ((`ADC_N_BITS == 16) && (adc_config_mode == 0 || adc_config_mode == 1)) begin - tx_data_buf = tx_ch8; + 32'h00000003: begin + tx_data_buf = tx_ch3; + if (`ADC_N_BITS == 18) begin + tx_data_buf = tx_ch2[17:2]; + end end - if (`ADC_N_BITS == 18) begin - if (adc_config_mode == 0 || adc_config_mode == 1) begin - tx_data_buf = {tx_ch1[1:0],14'b0}; - end else if (adc_config_mode == 2 || adc_config_mode == 3) begin - tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + 32'h00000004: begin + if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin + tx_data_buf = {8'b0,tx_status_2}; + end else if ((`ADC_N_BITS == 16) && (adc_config_mode == 0 || adc_config_mode == 1)) begin + tx_data_buf = tx_ch4; + end + if (`ADC_N_BITS == 18) begin + if (adc_config_mode == 0 || adc_config_mode == 1) begin + tx_data_buf = {tx_ch1[1:0],14'b0}; + end else if (adc_config_mode == 2 || adc_config_mode == 3) begin + tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + end end end - end - 32'h00000009: begin - if (`ADC_N_BITS == 18) begin - tx_data_buf = tx_ch5[17:2]; - end else begin - tx_data_buf = tx_crc; + 32'h00000005: begin + tx_data_buf = tx_ch5; + if (`ADC_N_BITS == 18) begin + tx_data_buf = tx_ch3[17:2]; + end end - end - 32'h0000000A: begin - if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin - tx_data_buf = {8'b0,tx_status_5}; + 32'h00000006: begin + if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin + tx_data_buf = {8'b0,tx_status_3}; + end else if ((`ADC_N_BITS == 16) && (adc_config_mode == 0 || adc_config_mode == 1)) begin + tx_data_buf = tx_ch6; + end + if (`ADC_N_BITS == 18) begin + if (adc_config_mode == 0 || adc_config_mode == 1) begin + tx_data_buf = {tx_ch1[1:0],14'b0}; + end else if (adc_config_mode == 2 || adc_config_mode == 3) begin + tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + end + end end - if (`ADC_N_BITS == 18) begin - if (adc_config_mode == 0 || adc_config_mode == 1) begin - tx_data_buf = {tx_ch1[1:0],14'b0}; - end else if (adc_config_mode == 2 || adc_config_mode == 3) begin - tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + 32'h00000007: begin + tx_data_buf = tx_ch7; + if (`ADC_N_BITS == 18) begin + tx_data_buf = tx_ch4[17:2]; end end - end - 32'h0000000B: begin - if (`ADC_N_BITS == 18) begin - tx_data_buf = tx_ch6[17:2]; + 32'h00000008: begin + if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin + tx_data_buf = {8'b0,tx_status_4}; + end else if ((`ADC_N_BITS == 16) && (adc_config_mode == 0 || adc_config_mode == 1)) begin + tx_data_buf = tx_ch8; + end + if (`ADC_N_BITS == 18) begin + if (adc_config_mode == 0 || adc_config_mode == 1) begin + tx_data_buf = {tx_ch1[1:0],14'b0}; + end else if (adc_config_mode == 2 || adc_config_mode == 3) begin + tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + end + end end - end - 32'h0000000C: begin - if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin - tx_data_buf = {8'b0,tx_status_6}; + 32'h00000009: begin + if (`ADC_N_BITS == 18) begin + tx_data_buf = tx_ch5[17:2]; + end else begin + tx_data_buf = tx_crc; + end end - if (`ADC_N_BITS == 18) begin - if (adc_config_mode == 0 || adc_config_mode == 1) begin - tx_data_buf = {tx_ch1[1:0],14'b0}; - end else if (adc_config_mode == 2 || adc_config_mode == 3) begin - tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + 32'h0000000A: begin + if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin + tx_data_buf = {8'b0,tx_status_5}; + end + if (`ADC_N_BITS == 18) begin + if (adc_config_mode == 0 || adc_config_mode == 1) begin + tx_data_buf = {tx_ch1[1:0],14'b0}; + end else if (adc_config_mode == 2 || adc_config_mode == 3) begin + tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + end end end - end - 32'h0000000D: begin - if (`ADC_N_BITS == 18) begin - tx_data_buf = tx_ch7[17:2]; + 32'h0000000B: begin + if (`ADC_N_BITS == 18) begin + tx_data_buf = tx_ch6[17:2]; + end end - end - 32'h0000000E: begin - if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin - tx_data_buf = {8'b0,tx_status_7}; + 32'h0000000C: begin + if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin + tx_data_buf = {8'b0,tx_status_6}; + end + if (`ADC_N_BITS == 18) begin + if (adc_config_mode == 0 || adc_config_mode == 1) begin + tx_data_buf = {tx_ch1[1:0],14'b0}; + end else if (adc_config_mode == 2 || adc_config_mode == 3) begin + tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + end + end end - if (`ADC_N_BITS == 18) begin - if (adc_config_mode == 0 || adc_config_mode == 1) begin - tx_data_buf = {tx_ch1[1:0],14'b0}; - end else if (adc_config_mode == 2 || adc_config_mode == 3) begin - tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + 32'h0000000D: begin + if (`ADC_N_BITS == 18) begin + tx_data_buf = tx_ch7[17:2]; end end - end - 32'h0000000F: begin - if (`ADC_N_BITS == 18) begin - tx_data_buf = tx_ch8[17:2]; + 32'h0000000E: begin + if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin + tx_data_buf = {8'b0,tx_status_7}; + end + if (`ADC_N_BITS == 18) begin + if (adc_config_mode == 0 || adc_config_mode == 1) begin + tx_data_buf = {tx_ch1[1:0],14'b0}; + end else if (adc_config_mode == 2 || adc_config_mode == 3) begin + tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + end + end end - end - 32'h00000010: begin - if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin - tx_data_buf = {8'b0,tx_status_8}; + 32'h0000000F: begin + if (`ADC_N_BITS == 18) begin + tx_data_buf = tx_ch8[17:2]; + end end - if (`ADC_N_BITS == 18) begin - if (adc_config_mode == 0 || adc_config_mode == 1) begin - tx_data_buf = {tx_ch1[1:0],14'b0}; - end else if (adc_config_mode == 2 || adc_config_mode == 3) begin - tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + 32'h00000010: begin + if ((`ADC_N_BITS == 16) && (adc_config_mode == 2 || adc_config_mode == 3)) begin + tx_data_buf = {8'b0,tx_status_8}; + end + if (`ADC_N_BITS == 18) begin + if (adc_config_mode == 0 || adc_config_mode == 1) begin + tx_data_buf = {tx_ch1[1:0],14'b0}; + end else if (adc_config_mode == 2 || adc_config_mode == 3) begin + tx_data_buf = {tx_ch1[1:0],5'b0,tx_status_1}; + end end end - end - 32'h00000011: begin - if ((`ADC_N_BITS == 16) && adc_config_mode == 3) begin - tx_data_buf = {8'b0,tx_status_8}; - end else if (`ADC_N_BITS == 18 && (adc_config_mode == 1 || adc_config_mode == 3)) begin - tx_data_buf = tx_crc; + 32'h00000011: begin + if ((`ADC_N_BITS == 16) && adc_config_mode == 3) begin + tx_data_buf = {8'b0,tx_status_8}; + end else if (`ADC_N_BITS == 18 && (adc_config_mode == 1 || adc_config_mode == 3)) begin + tx_data_buf = tx_crc; + end end - end - endcase + default: ; + endcase + end end -end - -//--------------------------------------------------------------------------- -// Configuration Test -//--------------------------------------------------------------------------- - -bit transfer_status = 0; -bit [31:0] config_CRC = 'h0; // CRC with channel static data setup -bit [31:0] config_SIMPLE = 'h0; // channel static data setup -bit [31:0] config_STATUS = 'h0; // channel static data setup + Status header -bit [31:0] config_STATUS_CRC = 'h0; // CRC with channel static data setup + Status header -bit [31:0] config_wr_CRC = 'h0; // write request sent result -bit [31:0] config_wr_SIMPLE = 'h0; // write request sent result -bit [31:0] config_wr_STATUS = 'h0; // write request sent result -bit [31:0] config_wr_STATUS_CRC = 'h0; // write request sent result -bit ctrl_status_CRC = 'h0; // ctrl_status bit from ADC common core -bit ctrl_status_SIMPLE = 'h0; // ctrl_status bit from ADC common core -bit ctrl_status_STATUS = 'h0; // ctrl_status bit from ADC common core -bit ctrl_status_STATUS_CRC = 'h0; // ctrl_status bit from ADC common core - -task adc_config_SIMPLE_test(); + + //--------------------------------------------------------------------------- + // Configuration Test + //--------------------------------------------------------------------------- + + bit transfer_status = 0; + bit [31:0] config_CRC = 'h0; // CRC with channel static data setup + bit [31:0] config_SIMPLE = 'h0; // channel static data setup + bit [31:0] config_STATUS = 'h0; // channel static data setup + Status header + bit [31:0] config_STATUS_CRC = 'h0; // CRC with channel static data setup + Status header + bit [31:0] config_wr_CRC = 'h0; // write request sent result + bit [31:0] config_wr_SIMPLE = 'h0; // write request sent result + bit [31:0] config_wr_STATUS = 'h0; // write request sent result + bit [31:0] config_wr_STATUS_CRC = 'h0; // write request sent result + bit ctrl_status_CRC = 'h0; // ctrl_status bit from ADC common core + bit ctrl_status_SIMPLE = 'h0; // ctrl_status bit from ADC common core + bit ctrl_status_STATUS = 'h0; // ctrl_status bit from ADC common core + bit ctrl_status_STATUS_CRC = 'h0; // ctrl_status bit from ADC common core + + task adc_config_SIMPLE_test(); axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1'b1)); //ADC common core out of reset axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), `SET_ADC_COMMON_REG_ADC_CONFIG_WR_ADC_CONFIG_WR(32'h00002181)); // set static data setup in device's reg 0x21 axi_read(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), config_SIMPLE); // read last config result @@ -400,9 +396,9 @@ task adc_config_SIMPLE_test(); axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_CNTRL_3), 'h100); // set default adc_config_mode = 3'h0; -endtask + endtask -task adc_config_CRC_test(); + task adc_config_CRC_test(); axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1'b1)); //ADC common core out of reset axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), `SET_ADC_COMMON_REG_ADC_CONFIG_WR_ADC_CONFIG_WR(32'h00002185)); // set CRC and static data setup in device's reg 0x21 axi_read(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), config_CRC); // read last config result @@ -425,9 +421,9 @@ task adc_config_CRC_test(); axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_CNTRL_3), 'h101); // set default adc_config_mode = 3'h1; -endtask + endtask -task adc_config_STATUS_test(); + task adc_config_STATUS_test(); axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1'b1)); //ADC common core out of reset axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), `SET_ADC_COMMON_REG_ADC_CONFIG_WR_ADC_CONFIG_WR(32'h00002181)); // static data setup in device's reg 0x21 axi_read(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), config_STATUS); // read last config result @@ -463,9 +459,9 @@ task adc_config_STATUS_test(); axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_CNTRL_3), 'h102); // set default adc_config_mode = 3'h2; -endtask + endtask -task adc_config_STATUS_CRC_test(); + task adc_config_STATUS_CRC_test(); axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_RSTN(1'b1)); //ADC common core out of reset axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), `SET_ADC_COMMON_REG_ADC_CONFIG_WR_ADC_CONFIG_WR(32'h00002185)); // static data and CRC setup in device's reg 0x21 axi_read(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_ADC_CONFIG_WR), config_STATUS); // read last config result @@ -501,10 +497,9 @@ task adc_config_STATUS_CRC_test(); axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_CNTRL_3), 'h103); // set default adc_config_mode = 3'h3; -endtask + endtask -task adc_config_number_of_channels(); - + task adc_config_number_of_channels(); axi_write (`AXI_AD7606X_BA + CH0 + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL),`SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); axi_write (`AXI_AD7606X_BA + CH1 + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL),`SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); axi_write (`AXI_AD7606X_BA + CH2 + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL),`SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); @@ -518,13 +513,13 @@ task adc_config_number_of_channels(); // axi_write(`AXI_AD7606X_BA + GetAddrs(ADC_COMMON_REG_CNTRL_3), 'h103); // set default adc_config_mode = 3'h4; -endtask + endtask -//--------------------------------------------------------------------------- -// DB transmission test -//--------------------------------------------------------------------------- -bit [31:0] capp_word; -task db_transmission_test(); + //--------------------------------------------------------------------------- + // DB transmission test + //--------------------------------------------------------------------------- + bit [31:0] capp_word; + task db_transmission_test(); #100 transfer_status = 1; // Generate cnvst_n pulse using AXI_PWM_GEN @@ -542,6 +537,6 @@ task db_transmission_test(); // Stop pwm gen axi_write (`AXI_PWMGEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_RESET(1)); `INFO(("axi_pwm_gen stopped."), ADI_VERBOSITY_LOW); -endtask + endtask endprogram diff --git a/testbenches/project/ad7606x/tests/test_program_si.sv b/testbenches/project/ad7606x/tests/test_program_si.sv index ee4d7277..fed5120c 100755 --- a/testbenches/project/ad7606x/tests/test_program_si.sv +++ b/testbenches/project/ad7606x/tests/test_program_si.sv @@ -100,93 +100,88 @@ program test_program_si ( input rx_busy, output rx_cnvst_n); -test_harness_env env; + test_harness_env env; -// -------------------------- -// Wrapper function for AXI read verify -// -------------------------- -task axi_read_v( + // -------------------------- + // Wrapper function for AXI read verify + // -------------------------- + task axi_read_v( input [31:0] raddr, input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); -endtask + env.mng.RegReadVerify32(raddr,vdata); + endtask -task axi_read( + task axi_read( input [31:0] raddr, output [31:0] data); - env.mng.RegRead32(raddr,data); -endtask + env.mng.RegRead32(raddr,data); + endtask -// -------------------------- -// Wrapper function for AXI write -// -------------------------- -task axi_write( - input [31:0] waddr, - input [31:0] wdata); + // -------------------------- + // Wrapper function for AXI write + // -------------------------- + task axi_write( + input [31:0] waddr, + input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); -endtask + env.mng.RegWrite32(waddr,wdata); + endtask -// -------------------------- -// Main procedure -// -------------------------- -initial begin - - //creating environment - env = new("AD7616 Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); - - setLoggerVerbosity(6); - env.start(); - - //asserts all the resets for 100 ns - `TH.`SYS_RST.inst.IF.assert_reset; - #100 - `TH.`SYS_RST.inst.IF.deassert_reset; - #100 - - sanity_test(); + // -------------------------- + // Main procedure + // -------------------------- + initial begin - #100 + //creating environment + env = new("AD7606X Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); - fifo_spi_test(); + setLoggerVerbosity(ADI_VERBOSITY_NONE); - #100 + env.start(); + env.sys_reset(); - offload_spi_test(); + sanity_test(); - `INFO(("Test Done"), ADI_VERBOSITY_NONE); + #100 - $finish; + fifo_spi_test(); -end + #100 -//--------------------------------------------------------------------------- -// Sanity test reg interface -//--------------------------------------------------------------------------- + offload_spi_test(); -task sanity_test(); - bit [31:0] pcore_version = (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_PATCH) - | (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MINOR)<<8 - | (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR)<<16; - axi_read_v (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_VERSION), pcore_version); - axi_write (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SCRATCH), 32'hDEADBEEF); - axi_read_v (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SCRATCH), 32'hDEADBEEF); - `INFO(("Sanity Test Done"), ADI_VERBOSITY_LOW); -endtask + `INFO(("Test Done"), ADI_VERBOSITY_NONE); + $finish; -//--------------------------------------------------------------------------- -// SPI Engine generate transfer -//--------------------------------------------------------------------------- + end -task generate_transfer_cmd( + //--------------------------------------------------------------------------- + // Sanity test reg interface + //--------------------------------------------------------------------------- + + task sanity_test(); + bit [31:0] pcore_version = (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_PATCH) + | (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MINOR)<<8 + | (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR)<<16; + axi_read_v (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_VERSION), pcore_version); + axi_write (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SCRATCH), 32'hDEADBEEF); + axi_read_v (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SCRATCH), 32'hDEADBEEF); + `INFO(("Sanity Test Done"), ADI_VERBOSITY_LOW); + endtask + + //--------------------------------------------------------------------------- + // SPI Engine generate transfer + //--------------------------------------------------------------------------- + + task generate_transfer_cmd( input [7:0] sync_id); // assert CSN @@ -198,50 +193,50 @@ task generate_transfer_cmd( // SYNC command to generate interrupt axi_write (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (INST_SYNC | sync_id)); `INFO(("Transfer generation finished."), ADI_VERBOSITY_LOW); -endtask + endtask -//--------------------------------------------------------------------------- -// IRQ callback -//--------------------------------------------------------------------------- + //--------------------------------------------------------------------------- + // IRQ callback + //--------------------------------------------------------------------------- -reg [4:0] irq_pending = 0; -reg [7:0] sync_id = 0; - -initial begin - while (1) begin - @(posedge ad7606_irq); - // read pending IRQs - axi_read (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_PENDING), irq_pending); - // IRQ launched by Offload SYNC command - if (irq_pending & 5'b10000) begin - axi_read (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SYNC_ID), sync_id); - `INFO(("Offload SYNC %d IRQ. An offload transfer just finished.", sync_id), ADI_VERBOSITY_LOW); - end - // IRQ launched by SYNC command - if (irq_pending & 5'b01000) begin - axi_read (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SYNC_ID), sync_id); - `INFO(("SYNC %d IRQ. FIFO transfer just finished.", sync_id), ADI_VERBOSITY_LOW); - end - // IRQ launched by SDI FIFO - if (irq_pending & 5'b00100) begin - `INFO(("SDI FIFO IRQ."), ADI_VERBOSITY_LOW); - end - // IRQ launched by SDO FIFO - if (irq_pending & 5'b00010) begin - `INFO(("SDO FIFO IRQ."), ADI_VERBOSITY_LOW); - end - // IRQ launched by SDO FIFO - if (irq_pending & 5'b00001) begin - `INFO(("CMD FIFO IRQ."), ADI_VERBOSITY_LOW); + reg [4:0] irq_pending = 0; + reg [7:0] sync_id = 0; + + initial begin + forever begin + @(posedge ad7606_irq); + // read pending IRQs + axi_read (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_PENDING), irq_pending); + // IRQ launched by Offload SYNC command + if (irq_pending & 5'b10000) begin + axi_read (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SYNC_ID), sync_id); + `INFO(("Offload SYNC %d IRQ. An offload transfer just finished.", sync_id), ADI_VERBOSITY_LOW); + end + // IRQ launched by SYNC command + if (irq_pending & 5'b01000) begin + axi_read (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SYNC_ID), sync_id); + `INFO(("SYNC %d IRQ. FIFO transfer just finished.", sync_id), ADI_VERBOSITY_LOW); + end + // IRQ launched by SDI FIFO + if (irq_pending & 5'b00100) begin + `INFO(("SDI FIFO IRQ."), ADI_VERBOSITY_LOW); + end + // IRQ launched by SDO FIFO + if (irq_pending & 5'b00010) begin + `INFO(("SDO FIFO IRQ."), ADI_VERBOSITY_LOW); + end + // IRQ launched by SDO FIFO + if (irq_pending & 5'b00001) begin + `INFO(("CMD FIFO IRQ."), ADI_VERBOSITY_LOW); + end + // Clear all pending IRQs + axi_write (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_PENDING), irq_pending); end - // Clear all pending IRQs - axi_write (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_PENDING), irq_pending); end -end -//--------------------------------------------------------------------------- -// Echo SCLK generation - we need this only if ECHO_SCLK is enabled -//--------------------------------------------------------------------------- + //--------------------------------------------------------------------------- + // Echo SCLK generation - we need this only if ECHO_SCLK is enabled + //--------------------------------------------------------------------------- reg [SDI_PHY_DELAY:0] echo_delay_sclk = {SDI_PHY_DELAY{1'b0}}; reg delay_clk = 0; @@ -251,7 +246,7 @@ end // Add an arbitrary delay to the echo_sclk signal initial begin - while(1) begin + forever begin @(posedge delay_clk) begin echo_delay_sclk <= {echo_delay_sclk, m_rx_sclk}; end @@ -259,182 +254,181 @@ end end assign ad7606_echo_sclk = echo_delay_sclk[SDI_PHY_DELAY-1]; -initial begin - while(1) begin - #0.5 delay_clk = ~delay_clk; + initial begin + forever begin + #0.5 delay_clk = ~delay_clk; + end end -end -//--------------------------------------------------------------------------- -// SDI data generator -//--------------------------------------------------------------------------- + //--------------------------------------------------------------------------- + // SDI data generator + //--------------------------------------------------------------------------- + + wire end_of_word; + wire rx_sclk_bfm = ad7606_echo_sclk; + wire m_spi_csn_negedge_s; + wire m_spi_csn_int_s = &ad7606_spi_cs; + bit m_spi_csn_int_d = 0; + bit [31:0] sdi_shiftreg; + wire [31:0] sdi_shiftreg2; + bit [7:0] rx_sclk_pos_counter = 0; + bit [7:0] rx_sclk_neg_counter = 0; + bit [31:0] sdi_preg[$]; + bit [31:0] sdi_nreg[$]; -wire end_of_word; -wire rx_sclk_bfm = ad7606_echo_sclk; -wire m_spi_csn_negedge_s; -wire m_spi_csn_int_s = &ad7606_spi_cs; -bit m_spi_csn_int_d = 0; -bit [31:0] sdi_shiftreg; -wire [31:0] sdi_shiftreg2; -bit [7:0] rx_sclk_pos_counter = 0; -bit [7:0] rx_sclk_neg_counter = 0; -bit [31:0] sdi_preg[$]; -bit [31:0] sdi_nreg[$]; - -initial begin - while(1) begin - @(posedge spi_clk); - m_spi_csn_int_d <= m_spi_csn_int_s; + initial begin + forever begin + @(posedge spi_clk); + m_spi_csn_int_d <= m_spi_csn_int_s; + end end -end - -assign m_spi_csn_negedge_s = ~m_spi_csn_int_s & m_spi_csn_int_d; - -genvar i; -for (i = 0; i < `NUM_OF_SDI; i++) begin - assign ad7606_spi_sdi[i] = sdi_shiftreg[31]; // all SDI lanes got the same data -end -assign end_of_word = (CPOL ^ CPHA) ? - (rx_sclk_pos_counter == 32) : - (rx_sclk_neg_counter == 32); + assign m_spi_csn_negedge_s = ~m_spi_csn_int_s & m_spi_csn_int_d; -initial begin - while(1) begin - @(posedge rx_sclk_bfm or posedge m_spi_csn_negedge_s); - if (m_spi_csn_negedge_s) begin - rx_sclk_pos_counter <= 8'b0; - end else begin - rx_sclk_pos_counter <= (rx_sclk_pos_counter == DATA_DLENGTH) ? 0 : rx_sclk_pos_counter+1; - end + genvar i; + for (i = 0; i < `NUM_OF_SDI; i++) begin + assign ad7606_spi_sdi[i] = sdi_shiftreg[31]; // all SDI lanes got the same data end -end -initial begin - while(1) begin - @(negedge rx_sclk_bfm or posedge m_spi_csn_negedge_s); - if (m_spi_csn_negedge_s) begin - rx_sclk_neg_counter <= 8'b0; - end else begin - rx_sclk_neg_counter <= (rx_sclk_neg_counter == DATA_DLENGTH) ? 0 : rx_sclk_neg_counter+1; + assign end_of_word = (CPOL ^ CPHA) ? + (rx_sclk_pos_counter == 32) : + (rx_sclk_neg_counter == 32); + + initial begin + forever begin + @(posedge rx_sclk_bfm or posedge m_spi_csn_negedge_s); + if (m_spi_csn_negedge_s) begin + rx_sclk_pos_counter <= 8'b0; + end else begin + rx_sclk_pos_counter <= (rx_sclk_pos_counter == DATA_DLENGTH) ? 0 : rx_sclk_pos_counter+1; + end end end -end -// SDI shift register -initial begin - while(1) begin - // synchronization - if (CPHA ^ CPOL) - @(posedge rx_sclk_bfm or posedge m_spi_csn_negedge_s); - else + initial begin + forever begin @(negedge rx_sclk_bfm or posedge m_spi_csn_negedge_s); - if ((m_spi_csn_negedge_s) || (end_of_word)) begin - // delete the last word at end_of_word - if (end_of_word) begin - sdi_preg.pop_back(); - sdi_nreg.pop_back(); - end if (m_spi_csn_negedge_s) begin - // NOTE: assuming queue is empty - repeat (NUM_OF_WORDS) begin - sdi_preg.push_front($urandom); - sdi_nreg.push_front($urandom); - end - #1; // prevent race condition - sdi_shiftreg <= (CPOL ^ CPHA) ? - sdi_preg[$] : - sdi_nreg[$]; - `INFO(("SR 1"), ADI_VERBOSITY_LOW); + rx_sclk_neg_counter <= 8'b0; end else begin - sdi_shiftreg <= (CPOL ^ CPHA) ? - sdi_preg[$] : - sdi_nreg[$]; - `INFO(("SR 2"), ADI_VERBOSITY_LOW); + rx_sclk_neg_counter <= (rx_sclk_neg_counter == DATA_DLENGTH) ? 0 : rx_sclk_neg_counter+1; end - if (m_spi_csn_negedge_s) @(posedge rx_sclk_bfm); // NOTE: when PHA=1 first shift should be at the second positive edge - end else begin /* if ((m_spi_csn_negedge_s) || (end_of_word)) */ - sdi_shiftreg <= {sdi_shiftreg[30:0], 1'b0}; end end -end -//--------------------------------------------------------------------------- -// Storing SDI Data for later comparison -//--------------------------------------------------------------------------- - -bit offload_status = 0; -bit shiftreg_sampled = 0; -bit [15:0] sdi_store_cnt = 'h0; -bit [31:0] offload_sdi_data_store_arr [(`NUM_OF_SDI * NUM_OF_TRANSFERS)-1:0]; -bit [31:0] sdi_fifo_data_store; -bit [31:0] sdi_data_store; -bit [31:0] sdi_shiftreg2; -bit [31:0] sdi_shiftreg_aux; -bit [31:0] sdi_shiftreg_aux_old; - -assign sdi_shiftreg2 = {1'b0, sdi_shiftreg[31:1]}; - -initial begin - while(1) begin - @(posedge ad7606_echo_sclk); - sdi_data_store <= {sdi_shiftreg[27:0], 4'b0}; - if (sdi_data_store == 'h0 && shiftreg_sampled == 'h1 && sdi_shiftreg != 'h0) begin - shiftreg_sampled <= 'h0; - if (offload_status) begin - sdi_store_cnt <= sdi_store_cnt + 1; - end - end else if (shiftreg_sampled == 'h0 && sdi_data_store != 'h0) begin - if (offload_status) begin - if (`NUM_OF_SDI == 1) begin - offload_sdi_data_store_arr[sdi_store_cnt] = sdi_shiftreg; - end else if (`NUM_OF_SDI == 2) begin - offload_sdi_data_store_arr[0+(2*sdi_store_cnt)] = sdi_shiftreg; - offload_sdi_data_store_arr[1+(2*sdi_store_cnt)] = sdi_shiftreg; - end else if (`NUM_OF_SDI == 4) begin - offload_sdi_data_store_arr[0+(4*sdi_store_cnt)] = sdi_shiftreg; - offload_sdi_data_store_arr[1+(4*sdi_store_cnt)] = sdi_shiftreg; - offload_sdi_data_store_arr[2+(4*sdi_store_cnt)] = sdi_shiftreg; - offload_sdi_data_store_arr[3+(4*sdi_store_cnt)] = sdi_shiftreg; - end else if (`NUM_OF_SDI == 8) begin - offload_sdi_data_store_arr[0+(8*sdi_store_cnt)] = sdi_shiftreg; - offload_sdi_data_store_arr[1+(8*sdi_store_cnt)] = sdi_shiftreg; - offload_sdi_data_store_arr[2+(8*sdi_store_cnt)] = sdi_shiftreg; - offload_sdi_data_store_arr[3+(8*sdi_store_cnt)] = sdi_shiftreg; - offload_sdi_data_store_arr[4+(8*sdi_store_cnt)] = sdi_shiftreg; - offload_sdi_data_store_arr[5+(8*sdi_store_cnt)] = sdi_shiftreg; - offload_sdi_data_store_arr[6+(8*sdi_store_cnt)] = sdi_shiftreg; - offload_sdi_data_store_arr[7+(8*sdi_store_cnt)] = sdi_shiftreg; + // SDI shift register + initial begin + forever begin + // synchronization + if (CPHA ^ CPOL) + @(posedge rx_sclk_bfm or posedge m_spi_csn_negedge_s); + else + @(negedge rx_sclk_bfm or posedge m_spi_csn_negedge_s); + if ((m_spi_csn_negedge_s) || (end_of_word)) begin + // delete the last word at end_of_word + if (end_of_word) begin + sdi_preg.pop_back(); + sdi_nreg.pop_back(); + end + if (m_spi_csn_negedge_s) begin + // NOTE: assuming queue is empty + repeat (NUM_OF_WORDS) begin + sdi_preg.push_front($urandom); + sdi_nreg.push_front($urandom); end - end else begin - sdi_fifo_data_store = sdi_shiftreg; + #1; // prevent race condition + sdi_shiftreg <= (CPOL ^ CPHA) ? + sdi_preg[$] : + sdi_nreg[$]; + `INFO(("SR 1"), ADI_VERBOSITY_LOW); + end else begin + sdi_shiftreg <= (CPOL ^ CPHA) ? + sdi_preg[$] : + sdi_nreg[$]; + `INFO(("SR 2"), ADI_VERBOSITY_LOW); + end + if (m_spi_csn_negedge_s) @(posedge rx_sclk_bfm); // NOTE: when PHA=1 first shift should be at the second positive edge + end else begin /* if ((m_spi_csn_negedge_s) || (end_of_word)) */ + sdi_shiftreg <= {sdi_shiftreg[30:0], 1'b0}; end - shiftreg_sampled <= 'h1; end end -end -//--------------------------------------------------------------------------- -// Offload Transfer Counter -//--------------------------------------------------------------------------- + //--------------------------------------------------------------------------- + // Storing SDI Data for later comparison + //--------------------------------------------------------------------------- + + bit offload_status = 0; + bit shiftreg_sampled = 0; + bit [15:0] sdi_store_cnt = 'h0; + bit [31:0] offload_sdi_data_store_arr [(`NUM_OF_SDI * NUM_OF_TRANSFERS)-1:0]; + bit [31:0] sdi_fifo_data_store; + bit [31:0] sdi_data_store; + bit [31:0] sdi_shiftreg2; + bit [31:0] sdi_shiftreg_aux; + bit [31:0] sdi_shiftreg_aux_old; -bit [31:0] offload_transfer_cnt; + assign sdi_shiftreg2 = {1'b0, sdi_shiftreg[31:1]}; -initial begin - while(1) begin - @(posedge shiftreg_sampled && offload_status); - offload_transfer_cnt <= offload_transfer_cnt + 'h1; + initial begin + forever begin + @(posedge ad7606_echo_sclk); + sdi_data_store <= {sdi_shiftreg[27:0], 4'b0}; + if (sdi_data_store == 'h0 && shiftreg_sampled == 'h1 && sdi_shiftreg != 'h0) begin + shiftreg_sampled <= 'h0; + if (offload_status) begin + sdi_store_cnt <= sdi_store_cnt + 1; + end + end else if (shiftreg_sampled == 'h0 && sdi_data_store != 'h0) begin + if (offload_status) begin + if (`NUM_OF_SDI == 1) begin + offload_sdi_data_store_arr[sdi_store_cnt] = sdi_shiftreg; + end else if (`NUM_OF_SDI == 2) begin + offload_sdi_data_store_arr[0+(2*sdi_store_cnt)] = sdi_shiftreg; + offload_sdi_data_store_arr[1+(2*sdi_store_cnt)] = sdi_shiftreg; + end else if (`NUM_OF_SDI == 4) begin + offload_sdi_data_store_arr[0+(4*sdi_store_cnt)] = sdi_shiftreg; + offload_sdi_data_store_arr[1+(4*sdi_store_cnt)] = sdi_shiftreg; + offload_sdi_data_store_arr[2+(4*sdi_store_cnt)] = sdi_shiftreg; + offload_sdi_data_store_arr[3+(4*sdi_store_cnt)] = sdi_shiftreg; + end else if (`NUM_OF_SDI == 8) begin + offload_sdi_data_store_arr[0+(8*sdi_store_cnt)] = sdi_shiftreg; + offload_sdi_data_store_arr[1+(8*sdi_store_cnt)] = sdi_shiftreg; + offload_sdi_data_store_arr[2+(8*sdi_store_cnt)] = sdi_shiftreg; + offload_sdi_data_store_arr[3+(8*sdi_store_cnt)] = sdi_shiftreg; + offload_sdi_data_store_arr[4+(8*sdi_store_cnt)] = sdi_shiftreg; + offload_sdi_data_store_arr[5+(8*sdi_store_cnt)] = sdi_shiftreg; + offload_sdi_data_store_arr[6+(8*sdi_store_cnt)] = sdi_shiftreg; + offload_sdi_data_store_arr[7+(8*sdi_store_cnt)] = sdi_shiftreg; + end + end else begin + sdi_fifo_data_store = sdi_shiftreg; + end + shiftreg_sampled <= 'h1; + end + end end -end -//--------------------------------------------------------------------------- -// Offload SPI Test -//--------------------------------------------------------------------------- + //--------------------------------------------------------------------------- + // Offload Transfer Counter + //--------------------------------------------------------------------------- + + bit [31:0] offload_transfer_cnt; -bit [31:0] offload_captured_word_arr [(`NUM_OF_SDI * NUM_OF_TRANSFERS) -1 :0]; + initial begin + forever begin + @(posedge shiftreg_sampled && offload_status); + offload_transfer_cnt <= offload_transfer_cnt + 'h1; + end + end -task offload_spi_test(); + //--------------------------------------------------------------------------- + // Offload SPI Test + //--------------------------------------------------------------------------- + bit [31:0] offload_captured_word_arr [(`NUM_OF_SDI * NUM_OF_TRANSFERS) -1 :0]; + + task offload_spi_test(); //Configure DMA env.mng.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA env.mng.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_FLAGS), @@ -479,67 +473,67 @@ task offload_spi_test(); end else begin `INFO(("Offload Test PASSED"), ADI_VERBOSITY_LOW); end -endtask - -//--------------------------------------------------------------------------- -// FIFO SPI Test -//--------------------------------------------------------------------------- - -bit [31:0] sdi_fifo_data = 0; - -task fifo_spi_test(); - -`ifdef AD7606X_AXI_CLKGEN_BA - // Start spi clk generator - axi_write (`AD7606X_AXI_CLKGEN_BA + GetAddrs(AXI_CLKGEN_REG_RSTN), - `SET_AXI_CLKGEN_REG_RSTN_MMCM_RSTN(1) | - `SET_AXI_CLKGEN_REG_RSTN_RSTN(1) - ); -`endif - - // Configure pwm - axi_write (`AXI_PWMGEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_RESET(1)); // PWM_GEN reset in regmap (ACTIVE HIGH) - axi_write (`AXI_PWMGEN_BA + GetAddrs(AXI_PWM_GEN_REG_PULSE_X_PERIOD), `SET_AXI_PWM_GEN_REG_PULSE_X_PERIOD_PULSE_X_PERIOD('h64)); // set PWM period - axi_write (`AXI_PWMGEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_LOAD_CONFIG(1)); // load AXI_PWM_GEN configuration - `INFO(("axi_pwm_gen started."), ADI_VERBOSITY_LOW); - - // Enable SPI Engine - axi_write (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_ENABLE), `SET_AXI_SPI_ENGINE_ENABLE_ENABLE(0)); - - // Configure the execution module - axi_write (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), INST_CFG); - axi_write (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), INST_PRESCALE); - axi_write (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), INST_DLENGTH); - - // Set up the interrupts - axi_write (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_MASK), - `SET_AXI_SPI_ENGINE_IRQ_MASK_SYNC_EVENT(1) | - `SET_AXI_SPI_ENGINE_IRQ_MASK_OFFLOAD_SYNC_ID_PENDING(1) - ); - - #100 - // Generate a FIFO transaction, write SDO first - repeat (NUM_OF_WORDS) begin - axi_write (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SDO_FIFO), (16'hDEAD << (DATA_WIDTH - DATA_DLENGTH))); - end + endtask + + //--------------------------------------------------------------------------- + // FIFO SPI Test + //--------------------------------------------------------------------------- + + bit [31:0] sdi_fifo_data = 0; + + task fifo_spi_test(); + + `ifdef AD7606X_AXI_CLKGEN_BA + // Start spi clk generator + axi_write (`AD7606X_AXI_CLKGEN_BA + GetAddrs(AXI_CLKGEN_REG_RSTN), + `SET_AXI_CLKGEN_REG_RSTN_MMCM_RSTN(1) | + `SET_AXI_CLKGEN_REG_RSTN_RSTN(1) + ); + `endif + + // Configure pwm + axi_write (`AXI_PWMGEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_RESET(1)); // PWM_GEN reset in regmap (ACTIVE HIGH) + axi_write (`AXI_PWMGEN_BA + GetAddrs(AXI_PWM_GEN_REG_PULSE_X_PERIOD), `SET_AXI_PWM_GEN_REG_PULSE_X_PERIOD_PULSE_X_PERIOD('h64)); // set PWM period + axi_write (`AXI_PWMGEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_LOAD_CONFIG(1)); // load AXI_PWM_GEN configuration + `INFO(("axi_pwm_gen started."), ADI_VERBOSITY_LOW); + + // Enable SPI Engine + axi_write (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_ENABLE), `SET_AXI_SPI_ENGINE_ENABLE_ENABLE(0)); + + // Configure the execution module + axi_write (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), INST_CFG); + axi_write (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), INST_PRESCALE); + axi_write (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), INST_DLENGTH); + + // Set up the interrupts + axi_write (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_MASK), + `SET_AXI_SPI_ENGINE_IRQ_MASK_SYNC_EVENT(1) | + `SET_AXI_SPI_ENGINE_IRQ_MASK_OFFLOAD_SYNC_ID_PENDING(1) + ); + + #100 + // Generate a FIFO transaction, write SDO first + repeat (NUM_OF_WORDS) begin + axi_write (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SDO_FIFO), (16'hDEAD << (DATA_WIDTH - DATA_DLENGTH))); + end - generate_transfer_cmd(1); + generate_transfer_cmd(1); - #100 - wait(sync_id == 1); - #100 + #100 + wait(sync_id == 1); + #100 - repeat (NUM_OF_WORDS) begin - axi_read (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SDI_FIFO_PEEK) , sdi_fifo_data); - end + repeat (NUM_OF_WORDS) begin + axi_read (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SDI_FIFO_PEEK) , sdi_fifo_data); + end - `INFO(("sdi_fifo_data: %x; sdi_fifo_data_store %x", sdi_fifo_data, sdi_fifo_data_store), ADI_VERBOSITY_LOW); + `INFO(("sdi_fifo_data: %x; sdi_fifo_data_store %x", sdi_fifo_data, sdi_fifo_data_store), ADI_VERBOSITY_LOW); - if (sdi_fifo_data != sdi_fifo_data_store) begin - `ERROR(("Fifo Read Test FAILED")); - end else begin - `INFO(("Fifo Read Test PASSED"), ADI_VERBOSITY_LOW); - end -endtask + if (sdi_fifo_data != sdi_fifo_data_store) begin + `ERROR(("Fifo Read Test FAILED")); + end else begin + `INFO(("Fifo Read Test PASSED"), ADI_VERBOSITY_LOW); + end + endtask endprogram