docs/ad463x: PR changes

docs/testbenches/project_based/ad463x/index.rst

@@ -16,7 +16,7 @@ Block design
 -------------------------------------------------------------------------------
 
 The testbench block design includes part of the AD4630-FMC HDL reference design,
-along with VIPs used for clock & reset, DDR and PS AXI.
+along with VIPs used for clocking, reset, PS and DDR simulations.
 
 Block diagram
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -49,8 +49,8 @@ The following parameters of this project that can be configured:
 Build parameters
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-The parameters mentioned above can be configured during the build, like in the
-following example:
+The parameters mentioned above can be configured when starting the build, like in
+the following example:
 
 .. shell::
    :showuser:
@@ -121,10 +121,10 @@ SPI mode        yes                yes                yes
 Echo Clock mode yes                yes                yes
 =============== ================== ================== ==================
 
-CPU/Memory interconnects addresses
+CPU/Memory interconnect addresses
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-Below are the CPU/Memory interconnects addresses used in this project:
+Below are the CPU/Memory interconnect addresses used in this project:
 
 =====================  ===========
 Instance               Address
@@ -362,7 +362,6 @@ Testbenches related dependencies
      - :git-testbenches:`library/utilities/utils.svh`
      - ---
 
-
 .. include:: ../../common/more_information.rst
 
 .. include:: ../../common/support.rst