From 5ccf0e6817d50dcfe5f96f120cdb70c080b086c8 Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Mon, 5 Aug 2024 14:50:35 +0300 Subject: [PATCH] docs: Remove some library subdirectories --- docs/library/IPs/index.rst | 15 -- docs/library/IPs/template_ip/index.rst | 129 ------------------ docs/library/frameworks/index.rst | 16 --- docs/library/frameworks/jesd204/index.rst | 5 - docs/library/frameworks/spi_engine/index.rst | 5 - .../frameworks/template_framework/index.rst | 51 ------- docs/library/index.rst | 44 +++++- docs/library/xilinx/clk_vip/index.rst | 119 +--------------- 8 files changed, 40 insertions(+), 344 deletions(-) delete mode 100644 docs/library/IPs/index.rst delete mode 100644 docs/library/IPs/template_ip/index.rst delete mode 100644 docs/library/frameworks/index.rst delete mode 100644 docs/library/frameworks/jesd204/index.rst delete mode 100644 docs/library/frameworks/spi_engine/index.rst delete mode 100644 docs/library/frameworks/template_framework/index.rst diff --git a/docs/library/IPs/index.rst b/docs/library/IPs/index.rst deleted file mode 100644 index 93113411..00000000 --- a/docs/library/IPs/index.rst +++ /dev/null @@ -1,15 +0,0 @@ -IPs -=============================================================================== - -.. note:: - - This page lists only the IPs that have been ported to the new documentation - format. - -Contents -------------------------------------------------------------------------------- - -.. toctree:: - :maxdepth: 1 - - template_ip/index \ No newline at end of file diff --git a/docs/library/IPs/template_ip/index.rst b/docs/library/IPs/template_ip/index.rst deleted file mode 100644 index 048138cd..00000000 --- a/docs/library/IPs/template_ip/index.rst +++ /dev/null @@ -1,129 +0,0 @@ -:orphan: - -.. _template_ip: - -IP Template -================================================================================ - -.. hdl-component-diagram:: - :path: library/spi_engine/spi_engine_execution - -Features --------------------------------------------------------------------------------- - -* AXI-based configuration -* Vivado and Quartus Compatible - -Files --------------------------------------------------------------------------------- - -.. list-table:: - :header-rows: 1 - - * - Name - - Description - * - :git-hdl:`library/axi_dmac/axi_dmac.v` - - Verilog source for the peripheral. - - -Block Diagram --------------------------------------------------------------------------------- - -.. image:: ../axi_dmac/block_diagram.svg - :alt: Template IP block diagram - :align: center - -Configuration Parameters --------------------------------------------------------------------------------- - -.. hdl-parameters:: - :path: library/spi_engine/spi_engine_interconnect - - * - DATA_WIDTH - - Data width of the parallel SDI/SDO data interfaces. - -.. _template_ip interface: - -Interface --------------------------------------------------------------------------------- - -.. hdl-interfaces:: - :path: library/axi_ad9783 - -Detailed Architecture --------------------------------------------------------------------------------- - - .. image:: detailed_architecture.svg - :alt: Template IP detailed architecture - :align: center - -Detailed Description --------------------------------------------------------------------------------- - -The top module instantiates - -* The ADC channel register map. -* The ADC common register map. -* The AXI handling interface. - -The data from the interface module is processed by the ADC channel module. -The Up_adc_common module implements the ADC COMMON register map, allowing for -basic monitoring and control of the ADC. -The Up_adc_channel module implements the ADC CHANNEL register map, allowing for -basic monitoring and control of the ADC's channel. - -Register Map --------------------------------------------------------------------------------- - -.. hdl-regmap:: - :name: COMMON - :no-type-info: - -.. hdl-regmap:: - :name: ADC_COMMON - :no-type-info: - -.. hdl-regmap:: - :name: ADC_CHANNEL - :no-type-info: - -Design Guidelines --------------------------------------------------------------------------------- - -The control of the chip is done through an SPI interface, which is needed at -system level. -The :ref:`template_ip interface` must be connected directly to the top file of -the design, as I/O primitives are part of the IP. - -The example design uses a DMA to move the data from the output of the IP to -the memory. If the data needs to be processed in HDL before moving to the -memory, it can be done at the output of the IP (at the system level) or inside -the ADC interface module (at the IP level). - -The example design uses a processor to program all the registers. -If no processor is available in your system, you can create your IP starting -from the interface module. - -Software Guidelines (if necessary) --------------------------------------------------------------------------------- - -To note all the details needed by the software to be in a certain way. - -Software Support --------------------------------------------------------------------------------- - -* Linux device driver at :git-linux:`/` -* Linux device tree at :git-linux:`/` -* Linux documentation at ... -* No-OS device driver at :git-no-os:`/` -* No-OS project at :git-no-os:`/` -* No-OS documentation at ... -* IIO support at ... - -References --------------------------------------------------------------------------------- - -* :git-hdl:`/`, :git-hdl:`library/axi_ad777x` library. -* :git-linux:`master:/`. -* :xilinx:`Zynq-7000 SoC Overview `. -* :xilinx:`Zynq-7000 SoC Packaging and Pinout `. diff --git a/docs/library/frameworks/index.rst b/docs/library/frameworks/index.rst deleted file mode 100644 index 2233983c..00000000 --- a/docs/library/frameworks/index.rst +++ /dev/null @@ -1,16 +0,0 @@ -Frameworks -=============================================================================== - -.. note:: - - This page lists only the IPs that have been ported to the new documentation - format. - -Contents -------------------------------------------------------------------------------- - -.. toctree:: - :maxdepth: 1 - - spi_engine/index - jesd204/index diff --git a/docs/library/frameworks/jesd204/index.rst b/docs/library/frameworks/jesd204/index.rst deleted file mode 100644 index d30ee485..00000000 --- a/docs/library/frameworks/jesd204/index.rst +++ /dev/null @@ -1,5 +0,0 @@ -.. _jesd204: - -JESD204 Interface Framework -================================================================================ - diff --git a/docs/library/frameworks/spi_engine/index.rst b/docs/library/frameworks/spi_engine/index.rst deleted file mode 100644 index 0d10a112..00000000 --- a/docs/library/frameworks/spi_engine/index.rst +++ /dev/null @@ -1,5 +0,0 @@ -.. _spi_engine: - -SPI Engine -================================================================================ - diff --git a/docs/library/frameworks/template_framework/index.rst b/docs/library/frameworks/template_framework/index.rst deleted file mode 100644 index d03fea2c..00000000 --- a/docs/library/frameworks/template_framework/index.rst +++ /dev/null @@ -1,51 +0,0 @@ -:orphan: - -.. _template_framework: - -Framework Template -================================================================================ - -.. toctree:: - :hidden: - - Template Module - Template Interface - Instruction Set Template - -{brief introdution}. - -Sub-modules --------------------------------------------------------------------------------- - -* :ref:`template_framework module`: {brief description}. - -Interfaces --------------------------------------------------------------------------------- - -* :ref:`template_framework interface`: {brief description}. - -Software --------------------------------------------------------------------------------- - -* :ref:`template_framework instruction-set`: {brief description}. - -Related IP Cores --------------------------------------------------------------------------------- - -This list contains cores that are not part of the core {ip name} but -make use of its interfaces and are intend to be used together with the {ip name}. - -* :dokuwiki:`util-sigma-delta-spi `: - Helper module for interfacing ADCs from the Analog Devices Sigma-Delta family. - -Examples --------------------------------------------------------------------------------- - -* :dokuwiki:`CN0363 `: - Colorimeter application using the :adi:`AD7175-2` Sigma-Delta ADC. - -Additional Resources --------------------------------------------------------------------------------- - -* :download:`Presentation: SPI Engine Design Philosophy `. -* :ref:`spi_engine tutorial`. diff --git a/docs/library/index.rst b/docs/library/index.rst index 2d86e67e..55fcaae9 100644 --- a/docs/library/index.rst +++ b/docs/library/index.rst @@ -1,17 +1,49 @@ -Libraries +.. _library: + +IP Cores =============================================================================== .. note:: - This page lists only the IPs that have been ported to the new documentation - format. + See :ref:`user_guide ip_cores` for templates and user guides. + +Frameworks +------------------------------------------------------------------------------- + +.. toctree:: + :maxdepth: 1 + + jesd204/index + spi_engine/index + +ADC/DAC +------------------------------------------------------------------------------- + +.. toctree:: + :maxdepth: 1 + +.. Example: axi_ad7616/index + +Data Offload +------------------------------------------------------------------------------- + +.. toctree:: + :maxdepth: 1 + +.. Example: data_offload/index + +DMA +------------------------------------------------------------------------------- + +.. toctree:: + :maxdepth: 1 + +.. Example: axi_dmac/index -Contents +Utilities ------------------------------------------------------------------------------- .. toctree:: :maxdepth: 1 - frameworks/index - IPs/index xilinx/index diff --git a/docs/library/xilinx/clk_vip/index.rst b/docs/library/xilinx/clk_vip/index.rst index e3d30c9c..73c83b8e 100644 --- a/docs/library/xilinx/clk_vip/index.rst +++ b/docs/library/xilinx/clk_vip/index.rst @@ -1,119 +1,4 @@ -:orphan: +.. _clk_vip: -.. _template_ip: - -IP Template +CLK VIP ================================================================================ - -.. hdl-component-diagram:: - :path: library/spi_engine/spi_engine_execution - -Features --------------------------------------------------------------------------------- - -* AXI-based configuration -* Vivado and Quartus Compatible - -Files --------------------------------------------------------------------------------- - -.. list-table:: - :header-rows: 1 - - * - Name - - Description - * - :git-hdl:`library/axi_dmac/axi_dmac.v` - - Verilog source for the peripheral. - - -Block Diagram --------------------------------------------------------------------------------- - -.. image:: ../axi_dmac/block_diagram.svg - :alt: Template IP block diagram - :align: center - -Configuration Parameters --------------------------------------------------------------------------------- - -.. hdl-parameters:: - :path: library/spi_engine/spi_engine_interconnect - - * - DATA_WIDTH - - Data width of the parallel SDI/SDO data interfaces. - -.. _template_ip interface: - -Interface --------------------------------------------------------------------------------- - -.. hdl-interfaces:: - :path: library/axi_ad9783 - -Detailed Architecture --------------------------------------------------------------------------------- - -:: - - .. image:: detailed_architecture.svg - :alt: Template IP detailed architecture - :align: center - -Detailed Description --------------------------------------------------------------------------------- - -The top module instantiates - -* The ADC channel register map. -* The ADC common register map. -* The AXI handling interface. - -The data from the interface module is processed by the ADC channel module. -The Up_adc_common module implements the ADC COMMON register map, allowing for -basic monitoring and control of the ADC. -The Up_adc_channel module implements the ADC CHANNEL register map, allowing for -basic monitoring and control of the ADC's channel. - -Register Map --------------------------------------------------------------------------------- - -.. hdl-regmap:: - :name: COMMON - :no-type-info: - -.. hdl-regmap:: - :name: ADC_COMMON - :no-type-info: - -.. hdl-regmap:: - :name: ADC_CHANNEL - :no-type-info: - -Design Guidelines --------------------------------------------------------------------------------- - -The control of the chip is done through an SPI interface, which is needed at the -system level. -The :ref:`template_ip interface` must be connected directly to the top file of -the design, as IO primitives are part of the IP. - -The example design uses a DMA to move the data from the output of the IP to memory. -If the data needs to be processed in HDL before moving to the memory, it can be -done at the output of the IP (at the system level) or inside the ADC interface -module (at the IP level). -The example design uses a processor to program all the registers. -If no processor is available in your system, you can create your IP starting -from the interface module. - -Software Guidelines --------------------------------------------------------------------------------- - -Linux is supported also using :git-linux:`master:/`. - -References --------------------------------------------------------------------------------- - -* :git-hdl:`/`, :git-hdl:`library/axi_ad777x` library. -* :git-linux:`master:/`. -* :xilinx:`Zynq-7000 SoC Overview `. -* :xilinx:`Zynq-7000 SoC Packaging and Pinout `.