From b5bd38c7c63f2bc5134edae34ef04729e7e1b9f7 Mon Sep 17 00:00:00 2001 From: Jorge Marques Date: Fri, 23 Aug 2024 15:26:20 +0200 Subject: [PATCH] V3: Update scoreboard, clean-up Signed-off-by: Jorge Marques --- common/sv/dma_trans.sv | 4 +- common/sv/dmac_api.sv | 34 +++---- common/sv/io_vip/io_vip.sv | 13 ++- common/sv/io_vip/io_vip_if.sv | 10 +- common/sv/io_vip/io_vip_ip.tcl | 2 - common/sv/io_vip/io_vip_pkg.ttcl | 2 +- common/sv/m_axis_sequencer.sv | 2 +- dma_flock/environment.sv | 35 +++---- dma_flock/scoreboard.sv | 102 ++++++++++---------- dma_flock/system_bd.tcl | 8 +- dma_flock/system_tb.sv | 2 +- dma_flock/tests/test_program.sv | 16 +-- dma_flock/tests/test_program_frame_delay.sv | 12 +-- 13 files changed, 113 insertions(+), 129 deletions(-) diff --git a/common/sv/dma_trans.sv b/common/sv/dma_trans.sv index 58dab1f7..ba12dcec 100644 --- a/common/sv/dma_trans.sv +++ b/common/sv/dma_trans.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2018, 2024 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -396,7 +396,7 @@ package dma_trans_pkg; return sa; endfunction - endclass + endclass : dma_partial_2d_segment //========================================================================== /* diff --git a/common/sv/dmac_api.sv b/common/sv/dmac_api.sv index 00e8f718..a8a4e627 100644 --- a/common/sv/dmac_api.sv +++ b/common/sv/dmac_api.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2018, 2024 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -79,11 +79,11 @@ package dmac_api_pkg; p.USE_EXT_SYNC = `GET_DMAC_INTERFACE_DESCRIPTION_1_USE_EXT_SYNC(val); p.HAS_AUTORUN = `GET_DMAC_INTERFACE_DESCRIPTION_1_HAS_AUTORUN(val); this.axi_write(GetAddrs(DMAC_X_LENGTH), - `SET_DMAC_X_LENGTH_X_LENGTH(32'h0)); + `SET_DMAC_X_LENGTH_X_LENGTH(32'h0)); this.axi_read(GetAddrs(DMAC_X_LENGTH), val); p.DMA_LENGTH_ALIGN = `GET_DMAC_X_LENGTH_X_LENGTH(val)+1; this.axi_write(GetAddrs(DMAC_Y_LENGTH), - `SET_DMAC_Y_LENGTH_Y_LENGTH(32'hFFFFFFFF)); + `SET_DMAC_Y_LENGTH_Y_LENGTH(32'hFFFFFFFF)); this.axi_read(GetAddrs(DMAC_Y_LENGTH), val); if (val==0) begin p.DMA_2D_TRANSFER = 0; @@ -123,7 +123,7 @@ package dmac_api_pkg; // ----------------- task enable_dma(); this.axi_write(GetAddrs(DMAC_CONTROL), - `SET_DMAC_CONTROL_ENABLE(1)); + `SET_DMAC_CONTROL_ENABLE(1)); endtask : enable_dma // ----------------- @@ -131,7 +131,7 @@ package dmac_api_pkg; // ----------------- task disable_dma(); this.axi_write(GetAddrs(DMAC_CONTROL), - `SET_DMAC_CONTROL_PAUSE(0)); + `SET_DMAC_CONTROL_PAUSE(0)); endtask : disable_dma // ----------------- @@ -139,10 +139,10 @@ package dmac_api_pkg; // ----------------- task set_control(input bit[3:0] control); this.axi_write(GetAddrs(DMAC_CONTROL), - `SET_DMAC_CONTROL_ENABLE(control[0]) | - `SET_DMAC_CONTROL_PAUSE(control[1]) | - `SET_DMAC_CONTROL_HWDESC(control[2]) | - `SET_DMAC_CONTROL_FRAMELOCK(control[3])); + `SET_DMAC_CONTROL_ENABLE(control[0]) | + `SET_DMAC_CONTROL_PAUSE(control[1]) | + `SET_DMAC_CONTROL_HWDESC(control[2]) | + `SET_DMAC_CONTROL_FRAMELOCK(control[3])); endtask : set_control // ----------------- @@ -150,9 +150,9 @@ package dmac_api_pkg; // ----------------- task set_flags(input bit[3:0] flags); this.axi_write(GetAddrs(DMAC_FLAGS), - `SET_DMAC_FLAGS_CYCLIC(flags[0]) | - `SET_DMAC_FLAGS_TLAST(flags[1]) | - `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(flags[2])); + `SET_DMAC_FLAGS_CYCLIC(flags[0]) | + `SET_DMAC_FLAGS_TLAST(flags[1]) | + `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(flags[2])); endtask : set_flags // ----------------- @@ -186,7 +186,7 @@ package dmac_api_pkg; // ----------------- task transfer_start; this.axi_write(GetAddrs(DMAC_TRANSFER_SUBMIT), - `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); + `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); `INFO(("Transfer start")); endtask : transfer_start @@ -195,7 +195,7 @@ package dmac_api_pkg; // ----------------- task set_dest_addr(input int xfer_addr); this.axi_write(GetAddrs(DMAC_DEST_ADDRESS), - `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(xfer_addr)); + `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(xfer_addr)); endtask : set_dest_addr // ----------------- @@ -203,7 +203,7 @@ package dmac_api_pkg; // ----------------- task set_src_addr(input int xfer_addr); this.axi_write(GetAddrs(DMAC_SRC_ADDRESS), - `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(xfer_addr)); + `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(xfer_addr)); endtask : set_src_addr // ----------------- @@ -213,9 +213,9 @@ package dmac_api_pkg; input int xfer_length_x, input int xfer_length_y); this.axi_write(GetAddrs(DMAC_X_LENGTH), - `SET_DMAC_X_LENGTH_X_LENGTH(xfer_length_x)); + `SET_DMAC_X_LENGTH_X_LENGTH(xfer_length_x)); this.axi_write(GetAddrs(DMAC_Y_LENGTH), - `SET_DMAC_Y_LENGTH_Y_LENGTH(xfer_length_y)); + `SET_DMAC_Y_LENGTH_Y_LENGTH(xfer_length_y)); endtask : set_lengths // ----------------- diff --git a/common/sv/io_vip/io_vip.sv b/common/sv/io_vip/io_vip.sv index a163df47..62eb8f65 100644 --- a/common/sv/io_vip/io_vip.sv +++ b/common/sv/io_vip/io_vip.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -34,12 +34,12 @@ // *************************************************************************** module io_vip #( - parameter MODE = 1, // 1 - driver, 0 - monitor + parameter MODE = 1, // 1 - master, 0 - slave parameter WIDTH = 1 )( input clk, - input in, - output out + input [WIDTH-1:0] in, + output [WIDTH-1:0] out ); io_vip_if #( @@ -49,9 +49,8 @@ module io_vip #( .clk(clk) ); - generate if (MODE) begin - assign out = IF.io; - end else begin + assign out = IF.io; + generate if (~MODE) begin assign IF.io = in; end endgenerate diff --git a/common/sv/io_vip/io_vip_if.sv b/common/sv/io_vip/io_vip_if.sv index 6e680357..c9fb7dac 100644 --- a/common/sv/io_vip/io_vip_if.sv +++ b/common/sv/io_vip/io_vip_if.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -34,7 +34,7 @@ // *************************************************************************** interface io_vip_if #( - int MODE = 0, // 1 - driver, 0 - monitor + int MODE = 0, // 1 - master, 0 - slave WIDTH = 1 ) ( input bit clk @@ -42,10 +42,10 @@ interface io_vip_if #( logic [WIDTH-1:0] io = 0; - // Driver functions + // Master functions function void set_io(int o); if (MODE === 0) begin - $display("[ERROR] %0t Unsupported in monitor mode", $time); + $display("[ERROR] %0t Unsupported in slave mode", $time); $finish; end else begin io <= o[WIDTH-1:0]; @@ -58,7 +58,7 @@ interface io_vip_if #( set_io(o); endtask - // Monitor functions + // Slave functions function int get_io(); return io; endfunction diff --git a/common/sv/io_vip/io_vip_ip.tcl b/common/sv/io_vip/io_vip_ip.tcl index 144ee464..b72efeea 100644 --- a/common/sv/io_vip/io_vip_ip.tcl +++ b/common/sv/io_vip/io_vip_ip.tcl @@ -22,8 +22,6 @@ ipx::remove_all_bus_interface [ipx::current_core] adi_set_ports_dependency "in" \ "(spirit:decode(id('MODELPARAM_VALUE.MODE')) = 0)" -adi_set_ports_dependency "out" \ - "(spirit:decode(id('MODELPARAM_VALUE.MODE')) = 1)" set cc [ipx::current_core] diff --git a/common/sv/io_vip/io_vip_pkg.ttcl b/common/sv/io_vip/io_vip_pkg.ttcl index 058a811e..38b81bce 100644 --- a/common/sv/io_vip/io_vip_pkg.ttcl +++ b/common/sv/io_vip/io_vip_pkg.ttcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2018-2024 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2024 Analog Devices, Inc. All rights reserved. # SPDX short identifier: ADIBSD ############################################################################### diff --git a/common/sv/m_axis_sequencer.sv b/common/sv/m_axis_sequencer.sv index 7761826c..0d8d3404 100644 --- a/common/sv/m_axis_sequencer.sv +++ b/common/sv/m_axis_sequencer.sv @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // diff --git a/dma_flock/environment.sv b/dma_flock/environment.sv index 65267020..cce8ca2b 100644 --- a/dma_flock/environment.sv +++ b/dma_flock/environment.sv @@ -79,7 +79,6 @@ package environment_pkg; // Register accessors dma_transfer_group trans_q[$]; - bit done = 0; scoreboard scrb; @@ -95,10 +94,10 @@ package environment_pkg; virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, mng_axi_vip)) mng_vip_if, virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, ddr_axi_vip)) ddr_vip_if, - `ifdef HAS_XIL_VDMA + `ifdef HAS_XIL_VDMA virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, ref_src_axis_vip)) ref_src_axis_vip_if, virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, ref_dst_axis_vip)) ref_dst_axis_vip_if, - `endif + `endif virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, src_axis_vip)) src_axis_vip_if, virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, dst_axis_vip)) dst_axis_vip_if ); @@ -112,18 +111,18 @@ package environment_pkg; // Creating the agents src_axis_agent = new("Src AXI stream agent", src_axis_vip_if); dst_axis_agent = new("Dest AXI stream agent", dst_axis_vip_if); - `ifdef HAS_XIL_VDMA + `ifdef HAS_XIL_VDMA ref_src_axis_agent = new("Ref Src AXI stream agent", ref_src_axis_vip_if); ref_dst_axis_agent = new("Ref Dest AXI stream agent", ref_dst_axis_vip_if); - `endif + `endif // Creating the sequencers src_axis_seq = new(src_axis_agent); dst_axis_seq = new(dst_axis_agent); - `ifdef HAS_XIL_VDMA + `ifdef HAS_XIL_VDMA ref_src_axis_seq = new(ref_src_axis_agent); ref_dst_axis_seq = new(ref_dst_axis_agent); - `endif + `endif scrb = new; @@ -143,10 +142,10 @@ package environment_pkg; src_axis_agent.start_master(); dst_axis_agent.start_slave(); - `ifdef HAS_XIL_VDMA + `ifdef HAS_XIL_VDMA ref_src_axis_agent.start_master(); ref_dst_axis_agent.start_slave(); - `endif + `endif endtask @@ -157,16 +156,14 @@ package environment_pkg; //============================================================================ task test(); super.test(); - fork - src_axis_seq.run(); - `ifdef HAS_XIL_VDMA - ref_src_axis_seq.run(); - `endif - // DEST AXIS does not have to run, scoreboard connects and - // gathers packets from the agent - scrb.run(); - test_c_run(); - join_none + src_axis_seq.run(); + `ifdef HAS_XIL_VDMA + ref_src_axis_seq.run(); + `endif + // DEST AXIS does not have to run, scoreboard connects and + // gathers packets from the agent + scrb.run(); + test_c_run(); endtask //============================================================================ diff --git a/dma_flock/scoreboard.sv b/dma_flock/scoreboard.sv index f71b897d..7d03ab63 100644 --- a/dma_flock/scoreboard.sv +++ b/dma_flock/scoreboard.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -44,24 +44,33 @@ package scoreboard_pkg; import logger_pkg::*; class scoreboard; - // List of analysis ports from the monitors xil_analysis_port #(axi4stream_monitor_transaction) src_axis_ap; xil_analysis_port #(axi4stream_monitor_transaction) dst_axis_ap; + protected event shutdown_event; + + function new(); + endfunction: new + function void connect( xil_analysis_port #(axi4stream_monitor_transaction) src_axis_ap, xil_analysis_port #(axi4stream_monitor_transaction) dst_axis_ap); + this.src_axis_ap = src_axis_ap; this.dst_axis_ap = dst_axis_ap; - endfunction + endfunction: connect task run(); - fork - run_src; - run_dst; - join - endtask + fork begin + fork + run_src(); + run_dst(); + join_none + @shutdown_event; + disable fork; + end join_none + endtask: run task run_src(); endtask : run_src @@ -70,59 +79,48 @@ package scoreboard_pkg; axi4stream_monitor_transaction dst_axis_trans; xil_axi4stream_data_beat data_beat; int num_bytes; - - xil_axi4stream_data_byte expected_byte; xil_axi4stream_data_byte received_byte; bit received_tuser; - bit received_tlast; - int frame_count,prev_frame_count = 0; - while (1) begin - if (dst_axis_ap.get_item_cnt() >= 1) begin - dst_axis_ap.get(dst_axis_trans); - - // get TDATA - // Assumption is that all bytes from beat are valid - data_beat = dst_axis_trans.get_data_beat(); - num_bytes = dst_axis_trans.get_data_width()/8; - // Get TUSER[0] - received_tuser = dst_axis_trans.get_user_beat(); - // Get TLAST - received_tlast = dst_axis_trans.get_last(); - - // TUSER marks the start of frame; set the current frame number based - // on first beat first pixel - if (received_tuser == 1) begin - frame_count = data_beat[7:0]; - if (frame_count < prev_frame_count) - `ERROR(("Frame count out of order. Expected at least: 0x%h ; Found : 0x%h", prev_frame_count, frame_count)); - else - `INFO(("Received frame 0x%0h ", frame_count)); - prev_frame_count = frame_count; - end - // Compare data against the frame counter; all pixels from frame - // should match the frame counter. - for (int i = 0; i < num_bytes; i++) begin - expected_byte = frame_count; - received_byte = data_beat[i*8+:8]; - if (expected_byte !== received_byte) - `ERROR(("Data mismatch. Expected : 0x%h ; Found : 0x%h", expected_byte, received_byte)); - else - `INFOV(("Received byte 0x%h ", received_byte), 99); - end - + forever begin + dst_axis_ap.get(dst_axis_trans); + // get TDATA + // Assumption is that all bytes from beat are valid + data_beat = dst_axis_trans.get_data_beat(); + num_bytes = dst_axis_trans.get_data_width()/8; + // Get TUSER[0] + received_tuser = dst_axis_trans.get_user_beat(); + // Get TLAST + received_tlast = dst_axis_trans.get_last(); + // TUSER marks the start of frame; set the current frame number based + // on first beat first pixel + if (received_tuser == 1) begin + frame_count = data_beat[7:0]; + if (frame_count < prev_frame_count) + `ERROR(("Frame count out of order. Expected at least: 0x%h ; Found : 0x%h", prev_frame_count, frame_count)); + else + `INFO(("Received frame 0x%0h ", frame_count)); + prev_frame_count = frame_count; + end + // Compare data against the frame counter; all pixels from frame + // should match the frame counter. + for (int i = 0; i < num_bytes; i++) begin + expected_byte = frame_count; + received_byte = data_beat[i*8+:8]; + if (expected_byte !== received_byte) + `ERROR(("Data mismatch. Expected : 0x%h ; Found : 0x%h", expected_byte, received_byte)); + else + `INFOV(("Received byte 0x%h ", received_byte), 99); end - - #1; end - endtask : run_dst - task shutdown; - endtask - endclass + -> shutdown_event; + endtask: shutdown + + endclass: scoreboard endpackage diff --git a/dma_flock/system_bd.tcl b/dma_flock/system_bd.tcl index 15349b8c..32cde5d3 100644 --- a/dma_flock/system_bd.tcl +++ b/dma_flock/system_bd.tcl @@ -128,8 +128,12 @@ ad_connect dut_tx_dma/m_framelock dut_rx_dma/s_framelock ## connect cpu -ad_cpu_interconnect 0x7C420000 dut_rx_dma -ad_cpu_interconnect 0x7C430000 dut_tx_dma +set DUT_RX_DMA 0x7C420000 +set DUT_TX_DMA 0x7C430000 +ad_cpu_interconnect $DUT_RX_DMA dut_rx_dma +ad_cpu_interconnect $DUT_TX_DMA dut_tx_dma +adi_sim_add_define "DUT_RX_DMA_BA=[format "%d" ${DUT_RX_DMA}]" +adi_sim_add_define "DUT_TX_DMA_BA=[format "%d" ${DUT_TX_DMA}]" ad_mem_hp0_interconnect $sys_dma_clk dut_rx_dma/m_src_axi ad_mem_hp0_interconnect $sys_dma_clk dut_tx_dma/m_dest_axi diff --git a/dma_flock/system_tb.sv b/dma_flock/system_tb.sv index 88d2b618..8fb9ed2f 100644 --- a/dma_flock/system_tb.sv +++ b/dma_flock/system_tb.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/dma_flock/tests/test_program.sv b/dma_flock/tests/test_program.sv index fe6d5ccb..adb297b9 100644 --- a/dma_flock/tests/test_program.sv +++ b/dma_flock/tests/test_program.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -92,7 +92,7 @@ program test_program; sanity_test; start_clocks(); - sys_reset(); + env.sys_reset(); // Test synchronous (reader and writer at the same speed) singleTest( @@ -122,8 +122,9 @@ program test_program; ); stop_clocks(); + env.stop(); - $display("Testbench done!"); + `INFO(("Testbench done!")); $finish(); end @@ -333,13 +334,6 @@ program test_program; `TH.`DST_CLK.inst.IF.stop_clock; endtask - // Asserts all the resets for 100 ns - task sys_reset; - `TH.`SYS_RST.inst.IF.assert_reset; - #100 - `TH.`SYS_RST.inst.IF.deassert_reset; - endtask - // Assert external sync for one clock cycle task assert_writer_ext_sync; `ifdef SRC_SYNC_IO @@ -377,7 +371,7 @@ program test_program; // Calculate and wait one output frame duration plus a margin incycles = bytes_to_transfer / `DST_AXIS_VIP_CFG_TDATA_NUM_BYTES * 1.5; fperiod = (incycles*1000000000)/ clk_period; - #fperiod; + #(fperiod*1ns); endtask endprogram diff --git a/dma_flock/tests/test_program_frame_delay.sv b/dma_flock/tests/test_program_frame_delay.sv index 9074413a..13e117ba 100644 --- a/dma_flock/tests/test_program_frame_delay.sv +++ b/dma_flock/tests/test_program_frame_delay.sv @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -99,7 +99,7 @@ program test_program_frame_delay; end start_clocks(); - sys_reset(); + env.sys_reset(); // Test non-autorun mode if (has_sautorun + has_dautorun == 0) begin @@ -151,6 +151,7 @@ program test_program_frame_delay; end stop_clocks(); + env.stop(); $display("Testbench done!"); $finish(); @@ -382,13 +383,6 @@ program test_program_frame_delay; `TH.`DST_CLK.inst.IF.stop_clock; endtask - // Asserts all the resets for 100 ns - task sys_reset; - `TH.`SYS_RST.inst.IF.assert_reset; - #100 - `TH.`SYS_RST.inst.IF.deassert_reset; - endtask - // Assert external sync for one clock cycle task assert_writer_ext_sync; `ifdef SRC_SYNC_IO