From b6f0bb143215c61c0b46382040e2159e776cce0d Mon Sep 17 00:00:00 2001 From: IstvanZsSzekely <122256380+IstvanZsSzekely@users.noreply.github.com> Date: Wed, 20 Nov 2024 16:26:01 +0200 Subject: [PATCH] Logger update (#128) * logger: Updated logger - Added a reporter and a component base classes to instantiate from - Feature to get path from which hierarchy was reporting called - Added separate logging options for elaborated code - Updated class inheritance to support hierarchy level logging - Updated libraries to use the appropriate reporting functions - Updated testbenches Signed-off-by: Istvan-Zsolt Szekely --- library/drivers/common/mailbox.sv | 14 +- library/drivers/common/scoreboard.sv | 20 +- library/drivers/common/scoreboard_pack.sv | 11 +- library/drivers/common/watchdog.sv | 18 +- library/drivers/common/x_monitor.sv | 31 +-- .../drivers/data_offload/data_offload_api.sv | 9 +- library/drivers/dmac/dma_trans.sv | 44 ++--- library/drivers/dmac/dmac_api.sv | 49 ++--- library/drivers/jesd/adi_jesd204_pkg.sv | 58 +++--- library/drivers/xcvr/adi_xcvr_pkg.sv | 84 ++++---- library/regmaps/adi_peripheral_pkg.sv | 14 +- library/regmaps/adi_regmap_pkg.sv | 8 +- library/regmaps/reg_accessor.sv | 19 +- library/utilities/logger_pkg.sv | 109 ++++++++--- library/utilities/test_harness_env.sv | 11 +- library/utilities/utils.svh | 34 ++-- library/vip/adi/spi_vip/adi_spi_vip.sv | 2 +- library/vip/adi/spi_vip/adi_spi_vip_pkg.sv | 34 +++- library/vip/adi/spi_vip/s_spi_sequencer.sv | 12 +- library/vip/amd/m_axi_sequencer.sv | 25 ++- library/vip/amd/m_axis_sequencer.sv | 65 ++++--- library/vip/amd/s_axi_sequencer.sv | 18 +- library/vip/amd/s_axis_sequencer.sv | 21 +- scripts/project-sim.mk | 2 +- testbenches/ip/axi_tdd/tests/test_program.sv | 34 ++-- testbenches/ip/axis_sequencers/environment.sv | 9 +- .../ip/axis_sequencers/tests/test_program.sv | 20 +- testbenches/ip/base/environment.sv | 5 +- testbenches/ip/base/tests/test_program.sv | 9 +- testbenches/ip/data_offload/do_scoreboard.sv | 36 ++-- testbenches/ip/data_offload/environment.sv | 12 +- .../ip/data_offload/tests/test_program.sv | 22 +-- .../ip/data_offload_2/data_offload_pkg.sv | 6 +- .../ip/data_offload_2/do_scoreboard.sv | 16 +- testbenches/ip/data_offload_2/environment.sv | 8 +- .../ip/data_offload_2/tests/test_program.sv | 10 +- .../data_offload_2/tests/test_program_sync.sv | 10 +- .../ip/dma_loopback/tests/test_program.sv | 9 +- .../ip/dma_sg/tests/test_program_1d.sv | 14 +- .../ip/dma_sg/tests/test_program_2d.sv | 14 +- .../ip/dma_sg/tests/test_program_tr_queue.sv | 14 +- testbenches/ip/hbm/tests/test_program.sv | 15 +- .../ip/i3c_controller/tests/test_program.sv | 179 +++++++++--------- .../ip/jesd_loopback/tests/test_program.sv | 45 +++-- .../ip/jesd_loopback_64b/environment.sv | 100 ---------- .../jesd_loopback_64b/tests/test_program.sv | 11 +- testbenches/ip/scoreboard/environment.sv | 53 +++--- .../ip/scoreboard/tests/test_program.sv | 37 ++-- testbenches/ip/spi_engine/spi_environment.sv | 11 +- .../ip/spi_engine/tests/test_program.sv | 54 +++--- .../ip/spi_engine/tests/test_sleep_delay.sv | 61 +++--- testbenches/ip/util_pack/environment.sv | 25 +-- .../ip/util_pack/tests/test_program.sv | 19 +- .../project/ad463x/tests/test_program.sv | 37 ++-- .../project/ad57xx/ad57xx_environment.sv | 9 +- .../project/ad57xx/tests/test_program.sv | 43 +++-- .../project/ad738x/tests/test_program.sv | 36 ++-- testbenches/project/ad7606x/Makefile | 16 +- .../project/ad7606x/tests/test_program_4ch.sv | 62 +++--- .../project/ad7606x/tests/test_program_6ch.sv | 59 +++--- .../project/ad7606x/tests/test_program_8ch.sv | 59 +++--- .../project/ad7606x/tests/test_program_si.sv | 37 ++-- .../project/ad7616/tests/test_program_pi.sv | 16 +- .../project/ad7616/tests/test_program_si.sv | 36 ++-- .../project/ad9083/tests/test_program.sv | 10 +- .../ad_quadmxfe1_ebz/tests/test_dma.sv | 12 +- .../ad_quadmxfe1_ebz/tests/test_program.sv | 37 ++-- .../tests/test_program_64b66b.sv | 20 +- .../project/adrv9001/tests/test_program.sv | 12 +- testbenches/project/adrv9009/environment.sv | 100 ---------- .../project/adrv9009/tests/test_program.sv | 20 +- .../project/fmcomms2/tests/test_program.sv | 12 +- .../project/mxfe/tests/test_program.sv | 37 ++-- .../project/pluto/tests/test_program.sv | 10 +- .../pulsar_adc_pmdz/tests/test_program.sv | 41 ++-- 75 files changed, 1188 insertions(+), 1103 deletions(-) delete mode 100644 testbenches/ip/jesd_loopback_64b/environment.sv delete mode 100755 testbenches/project/adrv9009/environment.sv diff --git a/library/drivers/common/mailbox.sv b/library/drivers/common/mailbox.sv index 8a4745e3..4f468bc2 100644 --- a/library/drivers/common/mailbox.sv +++ b/library/drivers/common/mailbox.sv @@ -4,7 +4,7 @@ package mailbox_pkg; import logger_pkg::*; - class mailbox_c #(type T); + class mailbox_c #(type T) extends adi_component; T queue[$]; @@ -13,7 +13,13 @@ package mailbox_pkg; event q_event; // constructor - function new(int size_max = 0); + function new( + input string name, + input int size_max = 0, + input adi_component parent = null); + + super.new(name, parent); + this.size_max = size_max; endfunction @@ -36,14 +42,14 @@ package mailbox_pkg; return 1; endfunction - task put(T element); + task put(input T element); if (this.size_max == this.num() && this.size_max != 0) @this.q_event; this.queue.push_front(element); ->this.q_event; endtask - function int try_put(T element); + function int try_put(input T element); if (this.size_max == this.num() && this.size_max != 0) return 0; this.queue.push_front(element); diff --git a/library/drivers/common/scoreboard.sv b/library/drivers/common/scoreboard.sv index 859fac47..640dabab 100644 --- a/library/drivers/common/scoreboard.sv +++ b/library/drivers/common/scoreboard.sv @@ -9,7 +9,7 @@ package scoreboard_pkg; import x_monitor_pkg::*; import mailbox_pkg::*; - class scoreboard extends xil_component; + class scoreboard extends adi_component; typedef enum bit { CYCLIC=0, ONESHOT } sink_type_t; protected sink_type_t sink_type; @@ -35,9 +35,11 @@ package scoreboard_pkg; protected event sink_transaction_event; // constructor - function new(input string name); + function new( + input string name, + input adi_component parent = null); - super.new(name); + super.new(name, parent); this.enabled = 0; this.sink_type = ONESHOT; @@ -88,7 +90,7 @@ package scoreboard_pkg; if (!this.enabled) begin this.sink_type = sink_type_t'(sink_type); end else begin - `ERROR(("ERROR Scoreboard: Can not configure sink_type while scoreboard is running.")); + this.error($sformatf("Can not configure sink_type while scoreboard is running.")); end endfunction: set_sink_type @@ -137,7 +139,7 @@ package scoreboard_pkg; this.source_byte_stream.push_front(source_byte); end this.source_byte_stream_size += this.source_monitor.mailbox.num(); - `INFOV(("Source transaction received, size: %d - %d", this.source_monitor.mailbox.num(), this.source_byte_stream_size), 200); + this.info($sformatf("Source transaction received, size: %d - %d", this.source_monitor.mailbox.num(), this.source_byte_stream_size), ADI_VERBOSITY_MEDIUM); ->>source_transaction_event; this.source_monitor.put_key(); end @@ -168,7 +170,7 @@ package scoreboard_pkg; this.sink_byte_stream.push_front(sink_byte); end this.sink_byte_stream_size += this.sink_monitor.mailbox.num(); - `INFOV(("Sink transaction received, size: %d - %d", this.sink_monitor.mailbox.num(), this.sink_byte_stream_size), 200); + this.info($sformatf("Sink transaction received, size: %d - %d", this.sink_monitor.mailbox.num(), this.sink_byte_stream_size), ADI_VERBOSITY_MEDIUM); ->>sink_transaction_event; this.sink_monitor.put_key(); end @@ -181,7 +183,7 @@ package scoreboard_pkg; logic [7:0] source_byte; logic [7:0] sink_byte; - `INFOV(("Scoreboard started"), 100); + this.info($sformatf("Started"), ADI_VERBOSITY_MEDIUM); forever begin : tx_path if (this.enabled == 0) @@ -196,9 +198,9 @@ package scoreboard_pkg; this.source_byte_stream_size--; sink_byte = this.sink_byte_stream.pop_back(); this.sink_byte_stream_size--; - `INFOV(("Scoreboard source-sink data: exp %h - rcv %h", source_byte, sink_byte), 100); + this.info($sformatf("Source-sink data: exp %h - rcv %h", source_byte, sink_byte), ADI_VERBOSITY_MEDIUM); if (source_byte != sink_byte) begin - `ERROR(("Scoreboard failed at: exp %h - rcv %h", source_byte, sink_byte)); + this.error($sformatf("Failed at: exp %h - rcv %h", source_byte, sink_byte)); end end else begin if ((this.source_byte_stream_size == 0) && diff --git a/library/drivers/common/scoreboard_pack.sv b/library/drivers/common/scoreboard_pack.sv index fe2a5c6f..7a7b151d 100644 --- a/library/drivers/common/scoreboard_pack.sv +++ b/library/drivers/common/scoreboard_pack.sv @@ -29,9 +29,10 @@ package scoreboard_pack_pkg; input int channels, input int samples, input int width, - input pack_type mode); + input pack_type mode, + input adi_component parent = null); - super.new(name); + super.new(name, parent); this.channels = channels; this.samples = samples; @@ -50,7 +51,7 @@ package scoreboard_pack_pkg; int outer_loop = (this.mode == CPACK) ? this.channels : this.samples; int inner_loop = (this.mode == CPACK) ? this.samples : this.channels; - `INFOV(("Scoreboard started"), 100); + this.info($sformatf("Scoreboard started"), 100); forever begin : tx_path if (this.enabled == 0) @@ -71,9 +72,9 @@ package scoreboard_pack_pkg; else this.source_byte_stream_size--; sink_byte = sink_byte_stream_block[(outer_loop*j+i)*this.width/8+k]; - `INFOV(("Scoreboard source-sink data: exp %h - rcv %h", source_byte, sink_byte), 100); + this.info($sformatf("Scoreboard source-sink data: exp %h - rcv %h", source_byte, sink_byte), 100); if (source_byte != sink_byte) begin - `ERROR(("Scoreboard failed at: exp %h - rcv %h", source_byte, sink_byte)); + this.error($sformatf("Scoreboard failed at: exp %h - rcv %h", source_byte, sink_byte)); end end end diff --git a/library/drivers/common/watchdog.sv b/library/drivers/common/watchdog.sv index 3eb6fd84..917f3a32 100644 --- a/library/drivers/common/watchdog.sv +++ b/library/drivers/common/watchdog.sv @@ -38,7 +38,7 @@ package watchdog_pkg; import logger_pkg::*; - class watchdog; + class watchdog extends adi_component; protected event stop_event; protected bit [31:0] timer; @@ -46,18 +46,22 @@ package watchdog_pkg; function new( - bit [31:0] timer, - string message); + input string name, + input bit [31:0] timer, + input string message, + input adi_component parent = null); + + super.new(name, parent); this.timer = timer; this.message = message; endfunction - function void update_message(string message); + function void update_message(input string message); this.message = message; endfunction: update_message - function void update_timer(bit [31:0] timer); + function void update_timer(input bit [31:0] timer); this.timer = timer; endfunction: update_timer @@ -77,12 +81,12 @@ package watchdog_pkg; fork begin #(this.timer*1ns); - `ERROR(("Watchdog timer timed out! %s", this.message)); + this.error($sformatf("Watchdog timer timed out! %s", this.message)); end @this.stop_event; join_any disable fork; - `INFOV(("Watchdog timer reset. %s", this.message), 100); + this.info($sformatf("Watchdog timer reset. %s", this.message), ADI_VERBOSITY_MEDIUM); end join_none endtask: start diff --git a/library/drivers/common/x_monitor.sv b/library/drivers/common/x_monitor.sv index f2f69994..2852b789 100644 --- a/library/drivers/common/x_monitor.sv +++ b/library/drivers/common/x_monitor.sv @@ -8,7 +8,7 @@ package x_monitor_pkg; import logger_pkg::*; import mailbox_pkg::*; - class x_monitor extends xil_component; + class x_monitor extends adi_component; mailbox_c #(logic [7:0]) mailbox; protected semaphore semaphore_key; @@ -17,10 +17,13 @@ package x_monitor_pkg; protected bit enabled; // constructor - function new(input string name); - super.new(name); + function new( + input string name, + input adi_component parent = null); + + super.new(name, parent); - this.mailbox = new; + this.mailbox = new("Mailbox", 0, this); this.semaphore_key = new(1); endfunction @@ -81,9 +84,12 @@ package x_monitor_pkg; protected int axi_byte_stream_size; // constructor - function new(input string name, T agent); + function new( + input string name, + input T agent, + input adi_component parent = null); - super.new(name); + super.new(name, parent); this.enabled = 0; @@ -124,7 +130,7 @@ package x_monitor_pkg; this.axi_byte_stream_size++; end end - `INFOV(("Caught an AXI4 transaction: %d", this.axi_byte_stream_size), 100); + this.info($sformatf("Caught an AXI4 transaction: %d", this.axi_byte_stream_size), ADI_VERBOSITY_MEDIUM); this.transaction_captured(); #1step; #1step; @@ -154,9 +160,12 @@ package x_monitor_pkg; protected T agent; // constructor - function new(input string name, T agent); + function new( + input string name, + input T agent, + input adi_component parent = null); - super.new(name); + super.new(name, parent); this.enabled = 0; this.tx_sink_type = CYCLIC; @@ -172,7 +181,7 @@ package x_monitor_pkg; if (!this.enabled) begin this.tx_sink_type = sink_type_t'(sink_type); end else begin - `ERROR(("ERROR Scoreboard: Can not configure sink_type while scoreboard is running.")); + this.error($sformatf("ERROR Scoreboard: Can not configure sink_type while scoreboard is running.")); end endfunction @@ -205,7 +214,7 @@ package x_monitor_pkg; if (keep_beat[j+:1] || !this.agent.vif_proxy.C_XIL_AXI4STREAM_SIGNAL_SET[XIL_AXI4STREAM_SIGSET_POS_KEEP]) this.mailbox.put(axi_byte); end - `INFOV(("Caught an AXI4 stream transaction: %d", this.mailbox.num()), 100); + this.info($sformatf("Caught an AXI4 stream transaction: %d", this.mailbox.num()), ADI_VERBOSITY_MEDIUM); this.transaction_captured(); #1step; this.mailbox.flush(); diff --git a/library/drivers/data_offload/data_offload_api.sv b/library/drivers/data_offload/data_offload_api.sv index 8244328c..c36ef999 100644 --- a/library/drivers/data_offload/data_offload_api.sv +++ b/library/drivers/data_offload/data_offload_api.sv @@ -48,8 +48,13 @@ package data_offload_api_pkg; // ----------------- // // ----------------- - function new(string name, reg_accessor bus, bit [31:0] base_address); - super.new(name, bus, base_address); + function new( + input string name, + input reg_accessor bus, + input bit [31:0] base_address, + input adi_component parent = null); + + super.new(name, bus, base_address, parent); endfunction // ----------------- diff --git a/library/drivers/dmac/dma_trans.sv b/library/drivers/dmac/dma_trans.sv index 9918d8b1..23cebbe2 100644 --- a/library/drivers/dmac/dma_trans.sv +++ b/library/drivers/dmac/dma_trans.sv @@ -112,13 +112,13 @@ package dma_trans_pkg; // // ----------------- virtual function void print(); - `INFO(("--------------------------")); - `INFO(("src_addr is 0x%h",src_addr)); - `INFO(("dst_addr is 0x%h",dst_addr)); - `INFO(("length is %0d",length)); - `INFO(("first is %0d",first)); - `INFO(("last is %0d",last)); - `INFO(("skip is %0d",skip)); + `INFO(("--------------------------"), ADI_VERBOSITY_MEDIUM); + `INFO(("src_addr is 0x%h",src_addr), ADI_VERBOSITY_MEDIUM); + `INFO(("dst_addr is 0x%h",dst_addr), ADI_VERBOSITY_MEDIUM); + `INFO(("length is %0d",length), ADI_VERBOSITY_MEDIUM); + `INFO(("first is %0d",first), ADI_VERBOSITY_MEDIUM); + `INFO(("last is %0d",last), ADI_VERBOSITY_MEDIUM); + `INFO(("skip is %0d",skip), ADI_VERBOSITY_MEDIUM); endfunction // ----------------- @@ -179,7 +179,7 @@ package dma_trans_pkg; // ----------------- virtual function void print(); super.print(); - `INFO(("partial length is %0d", reduced_length)); + `INFO(("partial length is %0d", reduced_length), ADI_VERBOSITY_MEDIUM); endfunction // length resolution @@ -271,9 +271,9 @@ package dma_trans_pkg; // ----------------- virtual function void print(); super.print(); - `INFO(("ylength is %0d", ylength)); - `INFO(("src_stride is 0x%0h", src_stride)); - `INFO(("dst_stride is 0x%0h", dst_stride)); + `INFO(("ylength is %0d", ylength), ADI_VERBOSITY_MEDIUM); + `INFO(("src_stride is 0x%0h", src_stride), ADI_VERBOSITY_MEDIUM); + `INFO(("dst_stride is 0x%0h", dst_stride), ADI_VERBOSITY_MEDIUM); endfunction // ----------------- @@ -353,8 +353,8 @@ package dma_trans_pkg; // ----------------- virtual function void print(); super.print(); - `INFO(("partial_segment_no is %0d", partial_segment_no)); - `INFO(("reduced_length is %0d", reduced_length)); + `INFO(("partial_segment_no is %0d", partial_segment_no), ADI_VERBOSITY_MEDIUM); + `INFO(("reduced_length is %0d", reduced_length), ADI_VERBOSITY_MEDIUM); endfunction // ----------------- @@ -377,7 +377,7 @@ package dma_trans_pkg; if (i != ylength-1) s.last = 0; sa[i] = s; - `INFO((" generating segment ")); + `INFO((" generating segment "), ADI_VERBOSITY_MEDIUM); s.print(); end else begin ps = new(p); @@ -389,7 +389,7 @@ package dma_trans_pkg; ps.last = 1; sa[i] = ps; skip_segment = 1; - `INFO((" generating partial segment ")); + `INFO((" generating partial segment "), ADI_VERBOSITY_MEDIUM); ps.print(); end end @@ -435,9 +435,9 @@ package dma_trans_pkg; virtual function void print(); super.print(); - `INFO(("flock_framenum is %0d", flock_framenum)); - `INFO(("flock_distance is %0d", flock_distance)); - `INFO(("flock_stride is 0x%0h", flock_stride)); + `INFO(("flock_framenum is %0d", flock_framenum), ADI_VERBOSITY_MEDIUM); + `INFO(("flock_distance is %0d", flock_distance), ADI_VERBOSITY_MEDIUM); + `INFO(("flock_stride is 0x%0h", flock_stride), ADI_VERBOSITY_MEDIUM); endfunction @@ -495,11 +495,11 @@ package dma_trans_pkg; // // ----------------- virtual function void print(); - `INFO(("transfer S")); + `INFO(("transfer S"), ADI_VERBOSITY_MEDIUM); for (int i=0; i 0) begin - `ERROR(("Transfer length (%0d) must be multiple of largest interface (%0d)", t.length, p.DMA_LENGTH_ALIGN)); + this.error($sformatf("Transfer length (%0d) must be multiple of largest interface (%0d)", t.length, p.DMA_LENGTH_ALIGN)); end if (p.DMA_TYPE_SRC == 0) begin this.axi_write(GetAddrs(DMAC_SRC_ADDRESS), diff --git a/library/drivers/jesd/adi_jesd204_pkg.sv b/library/drivers/jesd/adi_jesd204_pkg.sv index 86e61978..bea6f505 100644 --- a/library/drivers/jesd/adi_jesd204_pkg.sv +++ b/library/drivers/jesd/adi_jesd204_pkg.sv @@ -124,22 +124,22 @@ package adi_jesd204_pkg; // // ----------------- virtual function void print(); - `INFO(("--------------------------")); - `INFO(("--Link parameters---------")); - `INFO(("--------------------------")); - `INFO(("L is %0d", L)); - `INFO(("M is %0d", M)); - `INFO(("F is %0d", F)); - `INFO(("S is %0d", S)); - `INFO(("K is %0d", K)); - `INFO(("E is %0d", E)); - `INFO(("N is %0d", N)); - `INFO(("N' is %0d", NP)); - `INFO(("CS is %0d", CS)); - `INFO(("HD is %0d", HD)); - `INFO(("SCR is %0d", SCR)); - `INFO(("SUBCLASSV is %0d", SUBCLASSV)); - `INFO(("ENCODING is %s", encoding_s[encoding])); + `INFO(("--------------------------"), ADI_VERBOSITY_MEDIUM); + `INFO(("--Link parameters---------"), ADI_VERBOSITY_MEDIUM); + `INFO(("--------------------------"), ADI_VERBOSITY_MEDIUM); + `INFO(("L is %0d", L), ADI_VERBOSITY_MEDIUM); + `INFO(("M is %0d", M), ADI_VERBOSITY_MEDIUM); + `INFO(("F is %0d", F), ADI_VERBOSITY_MEDIUM); + `INFO(("S is %0d", S), ADI_VERBOSITY_MEDIUM); + `INFO(("K is %0d", K), ADI_VERBOSITY_MEDIUM); + `INFO(("E is %0d", E), ADI_VERBOSITY_MEDIUM); + `INFO(("N is %0d", N), ADI_VERBOSITY_MEDIUM); + `INFO(("N' is %0d", NP), ADI_VERBOSITY_MEDIUM); + `INFO(("CS is %0d", CS), ADI_VERBOSITY_MEDIUM); + `INFO(("HD is %0d", HD), ADI_VERBOSITY_MEDIUM); + `INFO(("SCR is %0d", SCR), ADI_VERBOSITY_MEDIUM); + `INFO(("SUBCLASSV is %0d", SUBCLASSV), ADI_VERBOSITY_MEDIUM); + `INFO(("ENCODING is %s", encoding_s[encoding]), ADI_VERBOSITY_MEDIUM); endfunction // ----------------- @@ -148,7 +148,7 @@ package adi_jesd204_pkg; function int check_config(); // 8 * F * L = M * N' * S if (8 * F * L != M * NP * S) begin - `ERROR(("Configuration mismatch. 8 * F * L != M * N' * S")); + `FATAL(("Configuration mismatch. 8 * F * L != M * N' * S")); return 1; end return 0; @@ -259,7 +259,7 @@ package adi_jesd204_pkg; sysref_clk = link_clk * dp_width / (link.K * link.F); sysref_clk_fract = sysref_clk - $floor(sysref_clk); if (sysref_clk_fract != 0) - `ERROR(("Current clock generator can't generate this exact frequency: %f", sysref_clk)); + this.error($sformatf("Current clock generator can't generate this exact frequency: %f", sysref_clk)); return sysref_clk; endfunction : calc_sysref_clk; @@ -370,11 +370,11 @@ package adi_jesd204_pkg; if (link.encoding == enc8b10b) begin lane_state = `GET_JESD_RX_LANEn_STATUS_CGS_STATE(val); if (lane_state != ls_8b10b_data) - `ERROR(("Lane %d state %s",i,rx_lane_states_8b10b[i])); + this.error($sformatf("Lane %d state %s",i,rx_lane_states_8b10b[i])); end else begin lane_state = `GET_JESD_RX_LANEn_STATUS_EMB_STATE(val); if (lane_state != ls_64b66b_emb_lock) - `ERROR(("Lane %d state %s",i,rx_lane_states_64b66b[i])); + this.error($sformatf("Lane %d state %s",i,rx_lane_states_64b66b[i])); end end @@ -411,15 +411,15 @@ package adi_jesd204_pkg; bit [31:0] val; this.bus.RegRead32(this.base_address + GetAddrs(JESD_RX_LINK_STATUS), val); if (link.encoding == enc8b10b) begin - `INFO(("Link status : %s", rx_link_states_8b10b[`GET_JESD_RX_LINK_STATUS_STATUS_STATE(val)])); + this.info($sformatf("Link status : %s", rx_link_states_8b10b[`GET_JESD_RX_LINK_STATUS_STATUS_STATE(val)]), ADI_VERBOSITY_MEDIUM); end else begin - `INFO(("Link status : %s", rx_link_states_64b66b[`GET_JESD_RX_LINK_STATUS_STATUS_STATE(val)])); + this.info($sformatf("Link status : %s", rx_link_states_64b66b[`GET_JESD_RX_LINK_STATUS_STATUS_STATE(val)]), ADI_VERBOSITY_MEDIUM); end // Check SYSREF alignment ERROR this.bus.RegRead32(this.base_address + GetAddrs(JESD_RX_SYSREF_STATUS), val); - `INFO(("SYSREF captured : %s", `GET_JESD_RX_SYSREF_STATUS_SYSREF_DETECTED(val) ? "Yes" : "No")); - `INFO(("SYSREF alignment error : %s", `GET_JESD_RX_SYSREF_STATUS_SYSREF_ALIGNMENT_ERROR(val) ? "Yes" : "No")); + this.info($sformatf("SYSREF captured : %s", `GET_JESD_RX_SYSREF_STATUS_SYSREF_DETECTED(val) ? "Yes" : "No"), ADI_VERBOSITY_MEDIUM); + this.info($sformatf("SYSREF alignment error : %s", `GET_JESD_RX_SYSREF_STATUS_SYSREF_ALIGNMENT_ERROR(val) ? "Yes" : "No"), ADI_VERBOSITY_MEDIUM); endtask : link_status_print @@ -551,16 +551,16 @@ package adi_jesd204_pkg; // There is no SYNC signal in 64b66b this.bus.RegRead32(this.base_address + GetAddrs(JESD_TX_LINK_STATUS), val); if (link.encoding == enc8b10b) begin - `INFO(("Link status : %s", tx_link_states_8b10b[`GET_JESD_TX_LINK_STATUS_STATUS_STATE(val)])); - `INFO(("SYNC~ : %s", `SET_JESD_TX_LINK_STATUS_STATUS_SYNC(val) ? "deasserted" : "asserted")); + this.info($sformatf("Link status : %s", tx_link_states_8b10b[`GET_JESD_TX_LINK_STATUS_STATUS_STATE(val)]), ADI_VERBOSITY_MEDIUM); + this.info($sformatf("SYNC~ : %s", `SET_JESD_TX_LINK_STATUS_STATUS_SYNC(val) ? "deasserted" : "asserted"), ADI_VERBOSITY_MEDIUM); end else begin - `INFO(("Link status %s", tx_link_states_64b66b[`GET_JESD_TX_LINK_STATUS_STATUS_STATE(val)])); + this.info($sformatf("Link status %s", tx_link_states_64b66b[`GET_JESD_TX_LINK_STATUS_STATUS_STATE(val)]), ADI_VERBOSITY_MEDIUM); end // Check SYSREF alignment ERROR this.bus.RegRead32(this.base_address + GetAddrs(JESD_TX_SYSREF_STATUS), val); - `INFO(("SYSREF captured : %s", `GET_JESD_TX_SYSREF_STATUS_SYSREF_DETECTED(val) ? "Yes" : "No")); - `INFO(("SYSREF alignment error : %s", `GET_JESD_TX_SYSREF_STATUS_SYSREF_ALIGNMENT_ERROR(val) ? "Yes" : "No")); + this.info($sformatf("SYSREF captured : %s", `GET_JESD_TX_SYSREF_STATUS_SYSREF_DETECTED(val) ? "Yes" : "No"), ADI_VERBOSITY_MEDIUM); + this.info($sformatf("SYSREF alignment error : %s", `GET_JESD_TX_SYSREF_STATUS_SYSREF_ALIGNMENT_ERROR(val) ? "Yes" : "No"), ADI_VERBOSITY_MEDIUM); endtask : link_status_print diff --git a/library/drivers/xcvr/adi_xcvr_pkg.sv b/library/drivers/xcvr/adi_xcvr_pkg.sv index 8f3ad35d..e31576c0 100644 --- a/library/drivers/xcvr/adi_xcvr_pkg.sv +++ b/library/drivers/xcvr/adi_xcvr_pkg.sv @@ -86,7 +86,7 @@ package adi_xcvr_pkg; 3: return 1; 4: return 2; 5: return 3; - default: `ERROR(("CPLL FBDIV value not supported")); + default: `FATAL(("CPLL FBDIV value not supported")); endcase return 0; endfunction : cpll_fbdiv_drp @@ -98,7 +98,7 @@ package adi_xcvr_pkg; case (val) 4: return 0; 5: return 1; - default: `ERROR(("CPLL FBDIV_45 value not supported")); + default: `FATAL(("CPLL FBDIV_45 value not supported")); endcase return 0; endfunction : cpll_fbdiv_45_drp @@ -110,7 +110,7 @@ package adi_xcvr_pkg; case (val) 1: return 16; 2: return 0; - default: `ERROR(("CPLL REFCLKDIV value not supported")); + default: `FATAL(("CPLL REFCLKDIV value not supported")); endcase return 0; endfunction : cpll_refclk_div_drp @@ -125,7 +125,7 @@ package adi_xcvr_pkg; 4: return 2; 8: return 3; 16: return 4; - default: `ERROR(("OUTDIV value not supported")); + default: `FATAL(("OUTDIV value not supported")); endcase return 0; endfunction : out_div_drp @@ -142,7 +142,7 @@ package adi_xcvr_pkg; 2: return 0; 3: return 1; 4: return 2; - default: `ERROR(("QPLL REFCLKDIV value not supported")); + default: `FATAL(("QPLL REFCLKDIV value not supported")); endcase return 0; endfunction : qpll_refclk_div_drp @@ -323,13 +323,13 @@ package adi_xcvr_pkg; task probe (); super.probe(); discover_capabs(); - `INFO(("Found %0s %0s XCVR = %0s on %0d lanes, QPLL access : %0d" , + this.info($sformatf("Found %0s %0s XCVR = %0s on %0d lanes, QPLL access : %0d" , tx_or_rx_n ? "TX" : "RX", link_mode == 1 ? "8B10B" : link_mode == 2 ? "64B66B" : "Unknown", xcvr_type.name(), num_lanes, qpll_enable - )); + ), ADI_VERBOSITY_MEDIUM); case (xcvr_type) GTXE2: begin @@ -352,7 +352,7 @@ package adi_xcvr_pkg; p = GTHE4p; end default: - `ERROR(("Case not supported")); + this.error($sformatf("Case not supported")); endcase endtask : probe @@ -502,9 +502,9 @@ package adi_xcvr_pkg; timeout--; end if (timeout == 0) begin - `ERROR(("[%s] XCVR status: 0, PLL lock: %0d", name, ~pll_lock_n)); + this.error($sformatf("[%s] XCVR status: 0, PLL lock: %0d", name, ~pll_lock_n)); end else begin - `INFO(("[%s] XCVR status: 1, PLL lock: %0d", name, ~pll_lock_n)); + this.info($sformatf("[%s] XCVR status: 1, PLL lock: %0d", name, ~pll_lock_n), ADI_VERBOSITY_MEDIUM); end endtask : up @@ -542,7 +542,7 @@ package adi_xcvr_pkg; invalid_plls = plls_to_try.find(x) with (x == QPLL1); if (invalid_plls.size() != 0) - `ERROR(("QPLL1 is not supported on GTXE2")); + this.error($sformatf("QPLL1 is not supported on GTXE2")); out_clk_sel = OUTCLKPMA; end @@ -556,7 +556,7 @@ package adi_xcvr_pkg; out_clk_sel = PROGDIVCLK; end default: - `ERROR(("Case not supported")); + this.error($sformatf("Case not supported")); endcase foreach (plls_to_try[pll_idx]) begin @@ -568,7 +568,7 @@ package adi_xcvr_pkg; QPLL0: calc_qpll(lane_rate, ref_clk, 0, pll_success, out_div); default: - `ERROR(("Case not supported")); + this.error($sformatf("Case not supported")); endcase if (pll_success) begin pll_type = plls_to_try[pll_idx]; @@ -577,21 +577,21 @@ package adi_xcvr_pkg; end if (pll_success == 0) begin - `ERROR(("No PLL could be set")); + this.error($sformatf("No PLL could be set")); end for (int ch_idx = 0; ch_idx < num_lanes; ch_idx++) begin if (out_clk_sel == PROGDIVCLK) begin case (xcvr_type) GTXE2: - `ERROR(("No PROGDIV support")); + this.error($sformatf("No PROGDIV support")); GTHE3, GTHE4, GTYE3_NOT_SUPPORTED, GTYE4: set_progdiv(ch_idx, out_div); default: - `ERROR(("Case not supported")); + this.error($sformatf("Case not supported")); endcase end @@ -622,16 +622,16 @@ package adi_xcvr_pkg; int f_fbdiv, f_fbdiv_45, f_refclk_div; int found = 0; - `INFO(("Searching valid config for lane rate %0d ref clock %0d", lane_rate, ref_clk)); + this.info($sformatf("Searching valid config for lane rate %0d ref clock %0d", lane_rate, ref_clk), ADI_VERBOSITY_MEDIUM); for (int fbdiv = 1; fbdiv <= 5; fbdiv++) begin for (int fbdiv_45 = 4; fbdiv_45 <= 5; fbdiv_45++) begin for (int refclk_div = 1; refclk_div <= 2; refclk_div++) begin cpll_vco = ref_clk * fbdiv_45 * fbdiv / refclk_div; if (p.cpll_check_vco_range(cpll_vco)) begin - `INFOV(("Skipping CPLL vco %0d . Out of range, [ %0d - %0d ]", + this.info($sformatf("Skipping CPLL vco %0d . Out of range, [ %0d - %0d ]", cpll_vco, p.cpll_vco_min, - p.cpll_vco_max), 100); + p.cpll_vco_max), ADI_VERBOSITY_MEDIUM); continue; end for (int out_div_idx = 0; out_div_idx <= 3; out_div_idx++) begin @@ -653,13 +653,13 @@ package adi_xcvr_pkg; end if (found) begin - `INFO(("Found cpll_vco : %0d", cpll_vco)); - `INFO(("Found cpll_fbdiv : %0d", f_fbdiv)); - `INFO(("Found cpll_fbdiv_45 : %0d", f_fbdiv_45)); - `INFO(("Found cpll_refclk_div : %0d", f_refclk_div)); - `INFO(("Found out_div : %0d", f_out_div)); + this.info($sformatf("Found cpll_vco : %0d", cpll_vco), ADI_VERBOSITY_MEDIUM); + this.info($sformatf("Found cpll_fbdiv : %0d", f_fbdiv), ADI_VERBOSITY_MEDIUM); + this.info($sformatf("Found cpll_fbdiv_45 : %0d", f_fbdiv_45), ADI_VERBOSITY_MEDIUM); + this.info($sformatf("Found cpll_refclk_div : %0d", f_refclk_div), ADI_VERBOSITY_MEDIUM); + this.info($sformatf("Found out_div : %0d", f_out_div), ADI_VERBOSITY_MEDIUM); end else begin - `INFO(("No valid config found for CPLL lane rate %0d ref clock %0d", lane_rate, ref_clk)); + this.info($sformatf("No valid config found for CPLL lane rate %0d ref clock %0d", lane_rate, ref_clk), ADI_VERBOSITY_MEDIUM); success = 0; return; end @@ -703,7 +703,7 @@ package adi_xcvr_pkg; ); end default: - `ERROR(("Case not supported")); + this.error($sformatf("Case not supported")); endcase endtask : set_cpll_divs @@ -734,12 +734,12 @@ package adi_xcvr_pkg; qpll_clkoutrate_min = 2; // Half rate endcase - `INFO(("Searching valid config for lane rate %0d ref clock %0d", lane_rate, ref_clk)); + this.info($sformatf("Searching valid config for lane rate %0d ref clock %0d", lane_rate, ref_clk), ADI_VERBOSITY_MEDIUM); foreach (p.qpll_fbdiv_drp[fbdiv]) begin : fbdiv_loop for (int refclk_div = 1; refclk_div <= 4; refclk_div++) begin qpll_vco = ref_clk * fbdiv / refclk_div; if (p.qpll_check_vco_range(qpll_vco, is_qpll1)) begin - `INFOV(("Skipping QPLL vco %0d . Out of range. fbdiv = %0d refclk_div = %0d", qpll_vco, fbdiv, refclk_div), 100); + this.info($sformatf("Skipping QPLL vco %0d . Out of range. fbdiv = %0d refclk_div = %0d", qpll_vco, fbdiv, refclk_div), ADI_VERBOSITY_MEDIUM); continue; end for (qpll_clkoutrate = qpll_clkoutrate_min; qpll_clkoutrate <= 2; qpll_clkoutrate++) begin @@ -761,13 +761,13 @@ package adi_xcvr_pkg; end if (found) begin - `INFO(("Found qpll_vco : %0d", qpll_vco)); - `INFO(("Found qpll_fbdiv : %0d", f_fbdiv)); - `INFO(("Found qpll_refclk_div : %0d", f_refclk_div)); - `INFO(("Found qpll_clkoutrate : %0d", qpll_clkoutrate)); - `INFO(("Found out_div : %0d", f_out_div)); + this.info($sformatf("Found qpll_vco : %0d", qpll_vco), ADI_VERBOSITY_MEDIUM); + this.info($sformatf("Found qpll_fbdiv : %0d", f_fbdiv), ADI_VERBOSITY_MEDIUM); + this.info($sformatf("Found qpll_refclk_div : %0d", f_refclk_div), ADI_VERBOSITY_MEDIUM); + this.info($sformatf("Found qpll_clkoutrate : %0d", qpll_clkoutrate), ADI_VERBOSITY_MEDIUM); + this.info($sformatf("Found out_div : %0d", f_out_div), ADI_VERBOSITY_MEDIUM); end else begin - `INFO(("No valid config found for QPLL%0d lane rate %0d ref clock %0d", is_qpll1, lane_rate, ref_clk)); + this.info($sformatf("No valid config found for QPLL%0d lane rate %0d ref clock %0d", is_qpll1, lane_rate, ref_clk), ADI_VERBOSITY_MEDIUM); success = 0; return; end @@ -778,7 +778,7 @@ package adi_xcvr_pkg; if (qpll_enable) set_qpll_divs(ch_idx, is_qpll1, f_refclk_div, f_fbdiv, qpll_clkoutrate); else - `INFO(("WARNING: Skipping QPLL configuration. Current AXI_XCVR does not have access to the CM ports")); + this.info($sformatf("WARNING: Skipping QPLL configuration. Current AXI_XCVR does not have access to the CM ports"), ADI_VERBOSITY_MEDIUM); end end @@ -824,7 +824,7 @@ package adi_xcvr_pkg; end end default: - `ERROR(("Case not supported")); + this.error($sformatf("Case not supported")); endcase endtask : set_qpll_divs @@ -865,7 +865,7 @@ package adi_xcvr_pkg; end end default: - `ERROR(("Case not supported")); + this.error($sformatf("Case not supported")); endcase endtask : set_out_div @@ -891,7 +891,7 @@ package adi_xcvr_pkg; 2: progdiv = 40; 4: progdiv = 80; default: - `ERROR(("Case not supported")); + this.error($sformatf("Case not supported")); endcase GTYE3_NOT_SUPPORTED, GTYE4: @@ -901,10 +901,10 @@ package adi_xcvr_pkg; 4: progdiv = 40; 8: progdiv = 80; default: - `ERROR(("Case not supported")); + this.error($sformatf("Case not supported")); endcase default: - `ERROR(("Case not supported")); + this.error($sformatf("Case not supported")); endcase end else if (link_mode == 2) begin @@ -913,11 +913,11 @@ package adi_xcvr_pkg; 2: progdiv = 33; 4: progdiv = 66; default: - `ERROR(("Case not supported")); + this.error($sformatf("Case not supported")); endcase end else begin - `ERROR(("Case not supported")); + this.error($sformatf("Case not supported")); end case (xcvr_type) diff --git a/library/regmaps/adi_peripheral_pkg.sv b/library/regmaps/adi_peripheral_pkg.sv index fdce397b..d947dc8f 100644 --- a/library/regmaps/adi_peripheral_pkg.sv +++ b/library/regmaps/adi_peripheral_pkg.sv @@ -42,7 +42,7 @@ package adi_peripheral_pkg; //============================================================================ // Base peripheral class //============================================================================ - class adi_peripheral; + class adi_peripheral extends adi_component; reg_accessor bus; bit [31:0] base_address; @@ -56,8 +56,14 @@ package adi_peripheral_pkg; // ----------------- // // ----------------- - function new (string name, reg_accessor bus, bit [31:0] base_address); - this.name = name; + function new( + input string name, + input reg_accessor bus, + input bit [31:0] base_address, + input adi_component parent = null); + + super.new(name, parent); + this.bus = bus; this.base_address = base_address; endfunction @@ -69,7 +75,7 @@ package adi_peripheral_pkg; bit [31:0] val; this.bus.RegRead32(this.base_address + 'h0, val); {ver_major, ver_minor, ver_patch} = val; - `INFO(("Found peripheral version: %0d.%0d.%s", ver_major, ver_minor, ver_patch)); + this.info($sformatf("Found peripheral version: %0d.%0d.%s", ver_major, ver_minor, ver_patch), ADI_VERBOSITY_HIGH); endtask // ----------------- diff --git a/library/regmaps/adi_regmap_pkg.sv b/library/regmaps/adi_regmap_pkg.sv index 00744607..c67e1cf3 100644 --- a/library/regmaps/adi_regmap_pkg.sv +++ b/library/regmaps/adi_regmap_pkg.sv @@ -65,7 +65,7 @@ package adi_regmap_pkg; int lsb, msb; if (!register.fields.exists(field)) - `ERROR(("Field %s in reg %s does not exists", field, register.name)); + `FATAL(("Field %s in reg %s does not exists", field, register.name)); lsb = register.fields[field].lsb; msb = register.fields[field].msb; @@ -75,7 +75,7 @@ package adi_regmap_pkg; ret[i]=1'b0; end - `INFOV(("Setting reg %s[%0d:%0d] field %s with %h (%h)", register.name, msb, lsb, field, value, ret), 10); + `INFO(("Setting reg %s[%0d:%0d] field %s with %h (%h)", register.name, msb, lsb, field, value, ret), ADI_VERBOSITY_HIGH); return ret; endfunction; @@ -87,7 +87,7 @@ package adi_regmap_pkg; int lsb, msb; if (!register.fields.exists(field)) - `ERROR(("Field %s in reg %s does not exists", field, register.name)); + `FATAL(("Field %s in reg %s does not exists", field, register.name)); lsb = register.fields[field].lsb; msb = register.fields[field].msb; @@ -109,7 +109,7 @@ package adi_regmap_pkg; bit [31:0] ret = curregvalue; if (!register.fields.exists(field)) - `ERROR(("Field %s in reg %s does not exists", field, register.name)); + `FATAL(("Field %s in reg %s does not exists", field, register.name)); ret = ret & (~SetField(register, field, 'hFFFF)); // mask ret = ret | SetField(register, field, regvalue); // update register diff --git a/library/regmaps/reg_accessor.sv b/library/regmaps/reg_accessor.sv index 29d9a256..519e0689 100644 --- a/library/regmaps/reg_accessor.sv +++ b/library/regmaps/reg_accessor.sv @@ -36,17 +36,28 @@ package reg_accessor_pkg; import axi_vip_pkg::*; + import logger_pkg::*; - virtual class reg_accessor; + class reg_accessor extends adi_component; - pure virtual task automatic RegWrite32(input xil_axi_ulong addr =0, + function new( + input string name, + input adi_component parent = null); + + super.new(name, parent); + endfunction + + virtual task automatic RegWrite32(input xil_axi_ulong addr =0, input bit [31:0] data); + endtask: RegWrite32 - pure virtual task automatic RegRead32(input xil_axi_ulong addr =0, + virtual task automatic RegRead32(input xil_axi_ulong addr =0, output bit [31:0] data); + endtask: RegRead32 - pure virtual task automatic RegReadVerify32(input xil_axi_ulong addr =0, + virtual task automatic RegReadVerify32(input xil_axi_ulong addr =0, input bit [31:0] data); + endtask: RegReadVerify32 endclass diff --git a/library/utilities/logger_pkg.sv b/library/utilities/logger_pkg.sv index 18df4429..0b2b64d2 100644 --- a/library/utilities/logger_pkg.sv +++ b/library/utilities/logger_pkg.sv @@ -33,31 +33,92 @@ // *************************************************************************** // *************************************************************************** +`include "utils.svh" + package logger_pkg; -// info - 2 -// warning - 1 -// error - 0 -int verbosity = 2; - -int error_count = 0; - -function void PrintInfo(string inStr, integer msgVerborisity = 2); - if (verbosity >= msgVerborisity) begin - $display("[INFO] %0t %s", $time, inStr); - end -endfunction - -function void PrintError(string inStr); - if (verbosity >= 0) begin - error_count = error_count + 1; - $display("[ERROR] %0t %s", $time, inStr); - $finish; - end -endfunction - -function void setLoggerVerbosity(int value); - verbosity = value; -endfunction + typedef enum { + ADI_VERBOSITY_NONE = 0, // highest priority, test passed message, randomization state, cannot be disabled + ADI_VERBOSITY_LOW = 1, // test_program level debugging + ADI_VERBOSITY_MEDIUM = 2, // driver level debugging + ADI_VERBOSITY_HIGH = 3 // VIP, regmap, utilities level debugging + } adi_verbosity_t; + + adi_verbosity_t verbosity = ADI_VERBOSITY_HIGH; + + function void PrintInfo( + input string inStr, + input adi_verbosity_t msgVerborisity); + + if (verbosity >= msgVerborisity) begin + $display("[INFO] @ %0t: %s", $time, inStr); + end + endfunction: PrintInfo + + function void PrintWarning(input string inStr); + $warning("%s", inStr); + endfunction: PrintWarning + + function void PrintError(input string inStr); + $error("%s", inStr); + endfunction: PrintError + + function void PrintFatal(input string inStr); + $fatal(1, "%s", inStr); + endfunction: PrintFatal + + function void setLoggerVerbosity(input adi_verbosity_t value); + verbosity = value; + endfunction: setLoggerVerbosity + + + class adi_reporter; + string name; + adi_reporter parent; + + function new( + input string name, + input adi_reporter parent = null); + + this.name = name; + this.parent = parent; + endfunction + + function string get_path(); + if (this.parent == null) + return this.name; + else + return $sformatf("%s.%s", this.parent.get_path(), this.name); + endfunction: get_path + + function void info( + input string message, + input adi_verbosity_t verbosity); + + PrintInfo($sformatf("[%s] %s", this.get_path(), message), verbosity); + endfunction: info + + function void warning(input string message); + PrintWarning($sformatf("[%s] %s", this.get_path(), message)); + endfunction: warning + + function void error(input string message); + PrintError($sformatf("[%s] %s", this.get_path(), message)); + endfunction: error + + function void fatal(input string message); + PrintFatal($sformatf("[%s] %s", this.get_path(), message)); + endfunction: fatal + endclass: adi_reporter + + + class adi_component extends adi_reporter; + function new( + input string name, + input adi_component parent = null); + + super.new(name, parent); + endfunction: new + endclass: adi_component endpackage diff --git a/library/utilities/test_harness_env.sv b/library/utilities/test_harness_env.sv index 3da6d0c9..2850c1b0 100644 --- a/library/utilities/test_harness_env.sv +++ b/library/utilities/test_harness_env.sv @@ -37,6 +37,7 @@ package test_harness_env_pkg; + import logger_pkg::*; import axi_vip_pkg::*; import axi4stream_vip_pkg::*; import m_axi_sequencer_pkg::*; @@ -44,7 +45,7 @@ package test_harness_env_pkg; import `PKGIFY(test_harness, mng_axi_vip)::*; import `PKGIFY(test_harness, ddr_axi_vip)::*; - class test_harness_env; + class test_harness_env extends adi_component; // Agents `AGENT(test_harness, mng_axi_vip, mst_t) mng_agent; @@ -67,6 +68,8 @@ package test_harness_env_pkg; // Constructor //============================================================================ function new( + input string name, + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if, virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if, virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if, @@ -77,6 +80,8 @@ package test_harness_env_pkg; virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, ddr_axi_vip)) ddr_vip_if ); + super.new(name); + this.sys_clk_vip_if = sys_clk_vip_if; this.dma_clk_vip_if = dma_clk_vip_if; this.ddr_clk_vip_if = ddr_clk_vip_if; @@ -87,8 +92,8 @@ package test_harness_env_pkg; ddr_axi_agent = new("AXI DDR stub agent", ddr_vip_if); // Creating the sequencers - mng = new(mng_agent); - ddr_axi_seq = new(ddr_axi_agent); + mng = new("AXI Manager sequencer", mng_agent, this); + ddr_axi_seq = new("AXI DDR stub sequencer", ddr_axi_agent, this); endfunction diff --git a/library/utilities/utils.svh b/library/utilities/utils.svh index 8186ad2d..a14e3493 100644 --- a/library/utilities/utils.svh +++ b/library/utilities/utils.svh @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -187,24 +187,22 @@ `define AXIS 1 `define FIFO 2 +// Macros used in Simulation files during simulation +`define INFO(m,v) \ + PrintInfo($sformatf("%s", \ + $sformatf m ),v) + +`define WARNING(m) \ + PrintWarning($sformatf("%s", \ + $sformatf m )) + `define ERROR(m) \ - do begin \ - PrintError($sformatf(" %s \n found in %s:%0d", \ - $sformatf m , `__FILE__, `__LINE__)); \ - end while(0) - -`define INFO(m) \ - do begin \ - PrintInfo($sformatf(" %s", \ - $sformatf m )); \ - end while(0) - -// Info with verbosity option -`define INFOV(m,v) \ - do begin \ - PrintInfo($sformatf(" %s", \ - $sformatf m ),v); \ - end while(0) + PrintError($sformatf("%s", \ + $sformatf m )) + +`define FATAL(m) \ + PrintFatal($sformatf("%s\n found in %s:%0d", \ + $sformatf m , `__FILE__, `__LINE__)) `define MAX(a,b) ((a > b) ? a : b) `define MIN(a,b) ((a > b) ? b : a) diff --git a/library/vip/adi/spi_vip/adi_spi_vip.sv b/library/vip/adi/spi_vip/adi_spi_vip.sv index ebae4f6e..fd3ec55c 100644 --- a/library/vip/adi/spi_vip/adi_spi_vip.sv +++ b/library/vip/adi/spi_vip/adi_spi_vip.sv @@ -79,7 +79,7 @@ module adi_spi_vip #( initial begin : ASSERT_PARAMETERS assert (MODE == MODE_SLAVE) else begin - $error("Unsupported mode %s. Valid values are 0=SLAVE, 1=MASTER, 2=MONITOR. Only 0(SLAVE) is currently supported.",MODE); + $error("Unsupported mode %s. Valid values are 0=SLAVE, 1=MASTER, 2=MONITOR. Only 0(SLAVE) is currently supported.", MODE); end end : ASSERT_PARAMETERS diff --git a/library/vip/adi/spi_vip/adi_spi_vip_pkg.sv b/library/vip/adi/spi_vip/adi_spi_vip_pkg.sv index bd881447..b403a0ba 100644 --- a/library/vip/adi/spi_vip/adi_spi_vip_pkg.sv +++ b/library/vip/adi/spi_vip/adi_spi_vip_pkg.sv @@ -37,6 +37,8 @@ package adi_spi_vip_pkg; + import logger_pkg::*; + `define SPI_VIP_PARAM_ORDER SPI_VIP_MODE ,\ SPI_VIP_CPOL ,\ SPI_VIP_CPHA ,\ @@ -61,7 +63,7 @@ package adi_spi_vip_pkg; th``_``vip``_0_VIP_CS_TO_MISO,\ th``_``vip``_0_VIP_DEFAULT_MISO_DATA - class adi_spi_driver #(int `SPI_VIP_PARAM_ORDER); + class adi_spi_driver #(int `SPI_VIP_PARAM_ORDER) extends adi_component; typedef mailbox #(logic [SPI_VIP_DATA_DLENGTH-1:0]) spi_mbx_t; protected spi_mbx_t mosi_mbx; @@ -73,7 +75,13 @@ package adi_spi_vip_pkg; protected event tx_mbx_updated; virtual spi_vip_if #(`SPI_VIP_PARAM_ORDER) vif; - function new(virtual spi_vip_if #(`SPI_VIP_PARAM_ORDER) intf); + function new( + input string name, + virtual spi_vip_if #(`SPI_VIP_PARAM_ORDER) intf, + input adi_component parent = null); + + super.new(name, parent); + this.vif = intf; this.active = 0; this.stop_flag = 0; @@ -155,7 +163,7 @@ package adi_spi_vip_pkg; if (!vif.cs_active) begin // if i!=0, we got !cs_active in the middle of a transaction if (i != 0) begin - $error("tx_miso: early exit due to unexpected CS inactive!"); + this.fatal($sformatf("tx_miso: early exit due to unexpected CS inactive!")); end break; end else if (pending_mbx) begin @@ -171,7 +179,7 @@ package adi_spi_vip_pkg; miso_reg = {miso_reg[SPI_VIP_DATA_DLENGTH-2:0], 1'b0}; end if (i == SPI_VIP_DATA_DLENGTH-1) begin - $display("[SPI VIP] MISO Tx end of transfer."); + this.info($sformatf("[SPI VIP] MISO Tx end of transfer."), ADI_VERBOSITY_HIGH); if (!using_default) begin // finally pop an item from the mailbox after a complete transfer miso_mbx.get(miso_reg); @@ -244,7 +252,7 @@ package adi_spi_vip_pkg; fork begin @(posedge this.stop_flag); - $display("[SPI VIP] Stop event triggered."); + this.info($sformatf("[SPI VIP] Stop event triggered."), ADI_VERBOSITY_HIGH); this.stop_flag = 0; end begin @@ -256,7 +264,7 @@ package adi_spi_vip_pkg; join this.clear_active(); end else begin - $error("Already running!"); + this.error($sformatf("Already running!")); end endtask @@ -264,18 +272,24 @@ package adi_spi_vip_pkg; if (this.get_active()) begin this.stop_flag = 1; end else begin - $error("Already inactive!"); + this.error($sformatf("Already inactive!")); end endtask endclass - class adi_spi_agent #(int `SPI_VIP_PARAM_ORDER); + class adi_spi_agent #(int `SPI_VIP_PARAM_ORDER) extends adi_component; protected adi_spi_driver #(`SPI_VIP_PARAM_ORDER) driver; - function new(virtual spi_vip_if #(`SPI_VIP_PARAM_ORDER) intf); - this.driver = new(intf); + function new( + input string name, + virtual spi_vip_if #(`SPI_VIP_PARAM_ORDER) intf, + input adi_component parent = null); + + super.new(name, parent); + + this.driver = new("Driver", intf, this); endfunction virtual task send_data(input int unsigned data); diff --git a/library/vip/adi/spi_vip/s_spi_sequencer.sv b/library/vip/adi/spi_vip/s_spi_sequencer.sv index d34613ed..82995926 100644 --- a/library/vip/adi/spi_vip/s_spi_sequencer.sv +++ b/library/vip/adi/spi_vip/s_spi_sequencer.sv @@ -40,11 +40,17 @@ package s_spi_sequencer_pkg; import logger_pkg::*; import adi_spi_vip_pkg::*; - class s_spi_sequencer #(`SPI_VIP_PARAM_ORDER); + class s_spi_sequencer #(`SPI_VIP_PARAM_ORDER) extends adi_component; protected adi_spi_agent #(`SPI_VIP_PARAM_ORDER) agent; - function new(adi_spi_agent #(`SPI_VIP_PARAM_ORDER) agent); + function new( + input string name, + input adi_spi_agent #(`SPI_VIP_PARAM_ORDER) agent, + input adi_component parent = null); + + super.new(name, parent); + this.agent = agent; endfunction: new @@ -60,7 +66,7 @@ package s_spi_sequencer_pkg; int unsigned received; this.agent.receive_data(received); if (received !== expected) begin - `ERROR(("Data mismatch. Received : %h; expected %h", received, expected)); + this.error($sformatf("Data mismatch. Received : %h; expected %h", received, expected)); end endtask : receive_data_verify diff --git a/library/vip/amd/m_axi_sequencer.sv b/library/vip/amd/m_axi_sequencer.sv index 96bc17b0..eb25855d 100644 --- a/library/vip/amd/m_axi_sequencer.sv +++ b/library/vip/amd/m_axi_sequencer.sv @@ -48,8 +48,15 @@ package m_axi_sequencer_pkg; semaphore reader_s; semaphore writer_s; - function new(T agent); + function new( + input string name, + input T agent, + input adi_component parent = null); + + super.new(name, parent); + this.agent = agent; + reader_s = new(1); writer_s = new(1); endfunction @@ -63,7 +70,7 @@ package m_axi_sequencer_pkg; static xil_axi_uint id =0; writer_s.get(1); - `INFOV(("writing to address %h value %h", addr , data), 10); + this.info($sformatf("writing to address %h value %h", addr , data), ADI_VERBOSITY_HIGH); single_write_transaction_readback_api(.id(id), .addr(addr), @@ -92,7 +99,7 @@ package m_axi_sequencer_pkg; .Rdatabeat(DataBeat_for_read)); id++; data = DataBeat_for_read[0][0+:32]; - `INFOV((" Reading data : %h @ 0x%h", data, addr), 10); + this.info($sformatf(" Reading data : %h @ 0x%h", data, addr), ADI_VERBOSITY_HIGH); reader_s.put(1); @@ -100,12 +107,12 @@ package m_axi_sequencer_pkg; virtual task automatic RegReadVerify32(input xil_axi_ulong addr =0, input bit [31:0] data); - bit [31:0] data_out; - RegRead32(.addr(addr), - .data(data_out)); - if (data !== data_out) begin - `ERROR((" Address : %h; Data mismatch. Read data is : %h; expected is %h", addr, data_out, data)); - end + bit [31:0] data_out; + RegRead32(.addr(addr), + .data(data_out)); + if (data !== data_out) begin + this.error($sformatf(" Address : %h; Data mismatch. Read data is : %h; expected is %h", addr, data_out, data)); + end endtask : RegReadVerify32 diff --git a/library/vip/amd/m_axis_sequencer.sv b/library/vip/amd/m_axis_sequencer.sv index f5c1abf3..91fc876e 100644 --- a/library/vip/amd/m_axis_sequencer.sv +++ b/library/vip/amd/m_axis_sequencer.sv @@ -54,7 +54,7 @@ package m_axis_sequencer_pkg; } stop_policy_t; - class m_axis_sequencer_base; + class m_axis_sequencer_base extends adi_component; protected bit enabled; protected bit queue_empty_sig; @@ -95,7 +95,12 @@ package m_axis_sequencer_pkg; // new - function new(); + function new( + input string name, + input adi_component parent = null); + + super.new(name, parent); + this.enabled = 1'b0; this.data_gen_mode = DATA_GEN_MODE_AUTO_INCR; this.descriptor_gen_mode = 1'b0; @@ -138,50 +143,50 @@ package m_axis_sequencer_pkg; // set disable policy function void set_stop_policy(input stop_policy_t stop_policy); if (enabled) - `ERROR(("Sequencer must be disabled before configuring stop policy")); + this.error($sformatf("Sequencer must be disabled before configuring stop policy")); this.stop_policy = stop_policy; - `INFOV(("Disable policy configured"), 55); + this.info($sformatf("Disable policy configured"), ADI_VERBOSITY_HIGH); endfunction: set_stop_policy // set data generation mode function void set_data_gen_mode(input data_gen_mode_t data_gen_mode); if (enabled) - `ERROR(("Sequencer must be disabled before configuring data generation mode")); + this.error($sformatf("Sequencer must be disabled before configuring data generation mode")); this.data_gen_mode = data_gen_mode; - `INFOV(("Data generation mode configured"), 55); + this.info($sformatf("Data generation mode configured"), ADI_VERBOSITY_HIGH); endfunction: set_data_gen_mode // set data generation mode function void set_descriptor_gen_mode(input bit descriptor_gen_mode); if (enabled) - `ERROR(("Sequencer must be disabled before configuring descriptor generation mode")); + this.error($sformatf("Sequencer must be disabled before configuring descriptor generation mode")); this.descriptor_gen_mode = descriptor_gen_mode; - `INFOV(("Descriptor generation mode configured"), 55); + this.info($sformatf("Descriptor generation mode configured"), ADI_VERBOSITY_HIGH); endfunction: set_descriptor_gen_mode // set data beat delay function void set_data_beat_delay(input int data_beat_delay); this.data_beat_delay = data_beat_delay; - `INFOV(("Data beat delay configured"), 55); + this.info($sformatf("Data beat delay configured"), ADI_VERBOSITY_HIGH); endfunction: set_data_beat_delay // set descriptor delay function void set_descriptor_delay(input int descriptor_delay); this.descriptor_delay = descriptor_delay; - `INFOV(("Descriptor delay configured"), 55); + this.info($sformatf("Descriptor delay configured"), ADI_VERBOSITY_HIGH); endfunction: set_descriptor_delay // set all bytes valid in a sample, sets keep to 1 function void set_keep_all(); if (enabled) - `ERROR(("Sequencer must be disabled before configuring keep all parameter")); + this.error($sformatf("Sequencer must be disabled before configuring keep all parameter")); this.keep_all = 1; endfunction: set_keep_all // bytes in a sample may not be valid, sets some bits of keep to 0 function void set_keep_some(); if (enabled) - `ERROR(("Sequencer must be disabled before configuring keep all parameter")); + this.error($sformatf("Sequencer must be disabled before configuring keep all parameter")); this.keep_all = 0; endfunction: set_keep_some @@ -195,8 +200,8 @@ package m_axis_sequencer_pkg; descriptor.num_bytes = bytes_to_generate; descriptor.gen_last = gen_last; descriptor.gen_sync = gen_sync; - // `INFOV(("Updating generator with %0d bytes with last %0d, sync %0d", - // bytes_to_generate, gen_last, gen_sync), 5); + // this.info($sformatf("Updating generator with %0d bytes with last %0d, sync %0d", + // bytes_to_generate, gen_last, gen_sync), ADI_VERBOSITY_HIGH); descriptor_q.push_back(descriptor); this.queue_empty_sig = 0; @@ -233,11 +238,11 @@ package m_axis_sequencer_pkg; // generate transfer with transfer descriptors protected task generator(); - `INFOV(("generator start"), 55); + this.info($sformatf("generator start"), ADI_VERBOSITY_HIGH); forever begin - `INFOV(("Waiting for enable"), 55); + this.info($sformatf("Waiting for enable"), ADI_VERBOSITY_HIGH); @enable_ev; - `INFOV(("Enable found"), 55); + this.info($sformatf("Enable found"), ADI_VERBOSITY_HIGH); fork begin fork begin @@ -282,13 +287,13 @@ package m_axis_sequencer_pkg; endtask: data_beat_delay_subroutine task start(); - `INFOV(("enable sequencer"), 55); + this.info($sformatf("enable sequencer"), ADI_VERBOSITY_HIGH); enabled = 1; ->> enable_ev; endtask: start task stop(); - `INFOV(("disable sequencer"), 55); + this.info($sformatf("disable sequencer"), ADI_VERBOSITY_HIGH); enabled = 0; byte_count = 0; ->> disable_ev; @@ -310,8 +315,12 @@ package m_axis_sequencer_pkg; protected T agent; - function new(T agent); - super.new(); + function new( + input string name, + input T agent, + input adi_component parent = null); + + super.new(name, parent); this.agent = agent; this.agent.vif_proxy.set_no_insert_x_when_keep_low(1); @@ -352,7 +361,7 @@ package m_axis_sequencer_pkg; int byte_per_beat; descriptor_t descriptor; - `INFOV(("packetize start"), 55); + this.info($sformatf("packetize start"), ADI_VERBOSITY_HIGH); byte_per_beat = AXIS_VIP_DATA_WIDTH/8; descriptor = descriptor_q.pop_front(); @@ -411,7 +420,7 @@ package m_axis_sequencer_pkg; endcase end - `INFOV(("generating axis transaction"), 55); + this.info($sformatf("generating axis transaction"), ADI_VERBOSITY_HIGH); trans = agent.driver.create_transaction(); trans.set_data(data); trans.set_id('h0); @@ -428,7 +437,7 @@ package m_axis_sequencer_pkg; trans.set_user_beat((tc == 0) & descriptor.gen_sync); ->> data_av_ev; - `INFOV(("waiting transfer to complete"), 55); + this.info($sformatf("waiting transfer to complete"), ADI_VERBOSITY_HIGH); @beat_done; end ->> packet_done; @@ -436,11 +445,11 @@ package m_axis_sequencer_pkg; // packet sender function virtual protected task sender(); - `INFOV(("sender start"), 55); + this.info($sformatf("sender start"), ADI_VERBOSITY_HIGH); forever begin - `INFOV(("Waiting for enable"), 55); + this.info($sformatf("Waiting for enable"), ADI_VERBOSITY_HIGH); @enable_ev; - `INFOV(("Enable found"), 55); + this.info($sformatf("Enable found"), ADI_VERBOSITY_HIGH); fork begin fork begin @@ -455,7 +464,7 @@ package m_axis_sequencer_pkg; end forever begin @data_av_ev; - `INFOV(("sending axis transaction"), 55); + this.info($sformatf("sending axis transaction"), ADI_VERBOSITY_HIGH); agent.driver.send(trans); ->> beat_done; end diff --git a/library/vip/amd/s_axi_sequencer.sv b/library/vip/amd/s_axi_sequencer.sv index 0a6b1051..a097ece3 100644 --- a/library/vip/amd/s_axi_sequencer.sv +++ b/library/vip/amd/s_axi_sequencer.sv @@ -41,15 +41,21 @@ package s_axi_sequencer_pkg; import axi_vip_pkg::*; import logger_pkg::*; - class s_axi_sequencer #( type T ); + class s_axi_sequencer #( type T ) extends adi_component; T agent; - function new(T agent); + function new( + input string name, + input T agent, + input adi_component parent = null); + + super.new(name, parent); + this.agent = agent; endfunction - task get_byte_from_mem(xil_axi_ulong addr, + task get_byte_from_mem(input xil_axi_ulong addr, output bit [7:0] data); bit [31:0] four_bytes; four_bytes = agent.mem_model.backdoor_memory_read_4byte(addr); @@ -61,7 +67,7 @@ package s_axi_sequencer_pkg; endcase endtask - task set_byte_in_mem(xil_axi_ulong addr, + task set_byte_in_mem(input xil_axi_ulong addr, input bit [7:0] data); bit [3:0] strb; case (addr[1:0]) @@ -75,13 +81,13 @@ package s_axi_sequencer_pkg; .strb(strb)); endtask - task verify_byte(xil_axi_ulong addr, + task verify_byte(input xil_axi_ulong addr, input bit [7:0] refdata); bit [7:0] data; get_byte_from_mem (addr, data); if (data !== refdata) begin - `ERROR(("Unexpected value at address %0h . Expected: %0h Found: %0h", addr, refdata, data)); + this.error($sformatf("Unexpected value at address %0h . Expected: %0h Found: %0h", addr, refdata, data)); end endtask diff --git a/library/vip/amd/s_axis_sequencer.sv b/library/vip/amd/s_axis_sequencer.sv index eede6bac..35418e6c 100644 --- a/library/vip/amd/s_axis_sequencer.sv +++ b/library/vip/amd/s_axis_sequencer.sv @@ -40,7 +40,7 @@ package s_axis_sequencer_pkg; import axi4stream_vip_pkg::*; import logger_pkg::*; - class s_axis_sequencer_base; + class s_axis_sequencer_base extends adi_component; protected xil_axi4stream_data_byte byte_stream [$]; protected xil_axi4stream_ready_gen_policy_t mode; @@ -58,7 +58,12 @@ package s_axis_sequencer_pkg; // new - function new(); + function new( + input string name, + input adi_component parent = null); + + super.new(name, parent); + this.mode = XIL_AXI4STREAM_READY_GEN_RANDOM; this.low_time = 0; this.high_time = 1; @@ -126,11 +131,11 @@ package s_axis_sequencer_pkg; task verify_byte(input bit [7:0] refdata); bit [7:0] data; if (byte_stream.size() == 0) begin - `ERROR(("Byte steam empty !!!")); + this.error($sformatf("Byte steam empty !!!")); end else begin data = byte_stream.pop_front(); if (data !== refdata) begin - `ERROR(("Unexpected data received. Expected: %0h Found: %0h Left : %0d", refdata, data, byte_stream.size())); + this.error($sformatf("Unexpected data received. Expected: %0h Found: %0h Left : %0d", refdata, data, byte_stream.size())); end end endtask @@ -156,8 +161,12 @@ package s_axis_sequencer_pkg; protected T agent; - function new(T agent); - super.new(); + function new( + input string name, + input T agent, + input adi_component parent = null); + + super.new(name, parent); this.agent = agent; endfunction diff --git a/scripts/project-sim.mk b/scripts/project-sim.mk index 953773b7..255b64f9 100644 --- a/scripts/project-sim.mk +++ b/scripts/project-sim.mk @@ -37,7 +37,7 @@ fi; \ (ERR=0; \ END=$$(date +%s); \ DIFF=$$(( $$END - $$START )); \ -ERRS=`grep -v ^# $(2) | grep -w -i -e ^error -e ^fatal -e ^fatal_error -e "\[ERROR\]" -e "while\\ executing" -C 10 | sed 's//\>/g'`; \ +ERRS=`grep -v ^# $(2) | grep -w -i -e ^error -e ^fatal -e ^fatal_error -e "\[ERROR\]" -e "\[FATAL\]" -e "while\\ executing" -C 10 | sed 's//\>/g'`; \ if [[ $$ERRS > 0 ]]; then \ ERR=1; \ fi; \ diff --git a/testbenches/ip/axi_tdd/tests/test_program.sv b/testbenches/ip/axi_tdd/tests/test_program.sv index 7a366777..05324c7b 100644 --- a/testbenches/ip/axi_tdd/tests/test_program.sv +++ b/testbenches/ip/axi_tdd/tests/test_program.sv @@ -88,7 +88,8 @@ program test_program; initial begin //creating environment - env = new(`TH.`SYS_CLK.inst.IF, + env = new("Axi TDD Environment", + `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, `TH.`SYS_RST.inst.IF, @@ -97,7 +98,7 @@ program test_program; #2ps; - setLoggerVerbosity(6); + setLoggerVerbosity(ADI_VERBOSITY_NONE); env.start(); start_clocks(); @@ -190,7 +191,7 @@ program test_program; end if (val !== expected_val) begin - `ERROR(("Address 0x%h Expected 0x%h found 0x%h", GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, expected_val, val)); + `FATAL(("Address 0x%h Expected 0x%h found 0x%h", GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, expected_val, val)); end else begin success_count++; end @@ -204,7 +205,7 @@ program test_program; end if (val !== expected_val) begin - `ERROR(("Address 0x%h Expected 0x%h found 0x%h", GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, expected_val, val)); + `FATAL(("Address 0x%h Expected 0x%h found 0x%h", GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, expected_val, val)); end else begin success_count++; end @@ -214,7 +215,7 @@ program test_program; env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); if (current_state !== 2'b00) begin - `ERROR(("Idle state: Expected 2'b00 found 2'b%b", current_state)); + `FATAL(("Idle state: Expected 2'b00 found 2'b%b", current_state)); end else begin success_count++; end @@ -240,7 +241,7 @@ program test_program; env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); if (current_state !== 2'b10) begin - `ERROR(("Waiting state: Expected 2'b10 found 2'b%b", current_state)); + `FATAL(("Waiting state: Expected 2'b10 found 2'b%b", current_state)); end else begin success_count++; end @@ -256,7 +257,7 @@ program test_program; // Check the initial startup delay if (expected_delay !== read_delay) begin - `ERROR(("Initial counter delay: Expected %t found %t", expected_delay, read_delay)); + `FATAL(("Initial counter delay: Expected %t found %t", expected_delay, read_delay)); end else begin success_count++; end @@ -266,7 +267,7 @@ program test_program; env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); if (current_state !== 2'b11) begin - `ERROR(("Running state: Expected 2'b11 found 2'b%b", current_state)); + `FATAL(("Running state: Expected 2'b11 found 2'b%b", current_state)); end else begin success_count++; end @@ -283,7 +284,7 @@ program test_program; env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); if (current_state !== 2'b01) begin - `ERROR(("Armed state: Expected 2'b01 found 2'b%b", current_state)); + `FATAL(("Armed state: Expected 2'b01 found 2'b%b", current_state)); end else begin success_count++; end @@ -361,7 +362,7 @@ program test_program; end if (val !== expected_val) begin - `ERROR(("Address 0x%h Expected 0x%h found 0x%h", GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, expected_val, val)); + `FATAL(("Address 0x%h Expected 0x%h found 0x%h", GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, expected_val, val)); end else begin success_count++; end @@ -375,7 +376,7 @@ program test_program; end if (val !== expected_val) begin - `ERROR(("Address 0x%h Expected 0x%h found 0x%h", GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, expected_val, val)); + `FATAL(("Address 0x%h Expected 0x%h found 0x%h", GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, expected_val, val)); end else begin success_count++; end @@ -480,7 +481,7 @@ program test_program; // Check the burst count value, thus validating that the TDD is still transferring the first frame if (`TH.dut_tdd.inst.i_counter.tdd_burst_counter !== (channel_count+2)) begin - `ERROR(("Burst counter: Expected %d found %d", channel_count+1, `TH.dut_tdd.inst.i_counter.tdd_burst_counter)); + `FATAL(("Burst counter: Expected %d found %d", channel_count+1, `TH.dut_tdd.inst.i_counter.tdd_burst_counter)); end else begin success_count++; end @@ -529,7 +530,7 @@ program test_program; @(posedge `TH.dut_tdd.inst.tdd_endof_frame); if (`TH.dut_tdd.inst.i_counter.tdd_burst_counter !== 0) begin - `ERROR(("Burst counter: Expected 0 found %d", `TH.dut_tdd.inst.i_counter.tdd_burst_counter)); + `FATAL(("Burst counter: Expected 0 found %d", `TH.dut_tdd.inst.i_counter.tdd_burst_counter)); end else begin success_count++; end @@ -547,7 +548,7 @@ program test_program; @(posedge `TH.dut_tdd.inst.tdd_endof_frame); if (`TH.dut_tdd.inst.i_counter.tdd_burst_counter !== 0) begin - `ERROR(("Burst counter: Expected 0 found %d", `TH.dut_tdd.inst.i_counter.tdd_burst_counter)); + `FATAL(("Burst counter: Expected 0 found %d", `TH.dut_tdd.inst.i_counter.tdd_burst_counter)); end else begin success_count++; end @@ -565,6 +566,9 @@ program test_program; stop_clocks(); + `INFO(("Testbench finished!"), ADI_VERBOSITY_NONE); + $finish; + end @@ -616,7 +620,7 @@ program test_program; end if (expected_pulse_lengh !== (t2-t1)) begin - `ERROR(("Pulse length channel[%2d]: Expected %t found %t", i, expected_pulse_lengh, t2-t1)); + `FATAL(("Pulse length channel[%2d]: Expected %t found %t", i, expected_pulse_lengh, t2-t1)); end else begin success_count++; end diff --git a/testbenches/ip/axis_sequencers/environment.sv b/testbenches/ip/axis_sequencers/environment.sv index bf357ed0..ba3fe31c 100644 --- a/testbenches/ip/axis_sequencers/environment.sv +++ b/testbenches/ip/axis_sequencers/environment.sv @@ -32,6 +32,8 @@ package environment_pkg; // Constructor //============================================================================ function new ( + input string name, + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if, virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if, virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if, @@ -46,7 +48,8 @@ package environment_pkg; ); // creating the agents - super.new(sys_clk_vip_if, + super.new(name, + sys_clk_vip_if, dma_clk_vip_if, ddr_clk_vip_if, sys_rst_vip_if, @@ -56,8 +59,8 @@ package environment_pkg; src_axis_agent = new("Source AXI Stream Agent", src_axis_vip_if); dst_axis_agent = new("Destination AXI Stream Agent", dst_axis_vip_if); - src_axis_seq = new(src_axis_agent); - dst_axis_seq = new(dst_axis_agent); + src_axis_seq = new("Source AXI Stream Agent", src_axis_agent, this); + dst_axis_seq = new("Destination AXI Stream Agent", dst_axis_agent, this); endfunction diff --git a/testbenches/ip/axis_sequencers/tests/test_program.sv b/testbenches/ip/axis_sequencers/tests/test_program.sv index c44e2f35..ac02bb73 100644 --- a/testbenches/ip/axis_sequencers/tests/test_program.sv +++ b/testbenches/ip/axis_sequencers/tests/test_program.sv @@ -59,7 +59,8 @@ program test_program; initial begin // create environment - env = new(`TH.`SYS_CLK.inst.IF, + env = new("Axis Sequencers Environment", + `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, `TH.`SYS_RST.inst.IF, @@ -69,9 +70,7 @@ program test_program; `TH.`DST_AXIS.inst.IF ); - #1step; - - setLoggerVerbosity(250); + setLoggerVerbosity(ADI_VERBOSITY_NONE); env.start(); env.sys_reset(); @@ -89,7 +88,7 @@ program test_program; case (`DEST_BACKPRESSURE) 1: env.dst_axis_seq.set_mode(XIL_AXI4STREAM_READY_GEN_SINGLE); 2: env.dst_axis_seq.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); - default: `ERROR(("Destination backpressure mode parameter incorrect!")); + default: `FATAL(("Destination backpressure mode parameter incorrect!")); endcase case (`SRC_DESCRIPTORS) @@ -99,24 +98,23 @@ program test_program; // env.src_axis_seq.add_xfer_descriptor(32'h600, 1, 0); env.src_axis_seq.add_xfer_descriptor_packet_size(32'd10, 1, 0); - send_data_wd = new(1000, "Send data"); + send_data_wd = new("Axis Sequencer Watchdog", 1000, "Send data"); end 2: begin env.src_axis_seq.set_descriptor_gen_mode(0); env.src_axis_seq.set_stop_policy(STOP_POLICY_DESCRIPTOR_QUEUE); repeat (10) env.src_axis_seq.add_xfer_descriptor(32'h600, 1, 0); - send_data_wd = new(30000, "Send data"); + send_data_wd = new("Axis Sequencer Watchdog", 30000, "Send data"); end 3: begin env.src_axis_seq.set_descriptor_gen_mode(1); env.src_axis_seq.set_stop_policy(STOP_POLICY_PACKET); env.src_axis_seq.add_xfer_descriptor(32'h600, 1, 0); - send_data_wd = new(20000, "Send data"); + send_data_wd = new("Axis Sequencer Watchdog", 20000, "Send data"); end - default: - `ERROR(("Source descriptor parameter incorrect!")); + default: `FATAL(("Source descriptor parameter incorrect!")); endcase send_data_wd.start(); @@ -143,7 +141,7 @@ program test_program; env.stop(); - `INFO(("Test bench done!")); + `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); $finish(); end diff --git a/testbenches/ip/base/environment.sv b/testbenches/ip/base/environment.sv index 970789c5..ebcb278f 100644 --- a/testbenches/ip/base/environment.sv +++ b/testbenches/ip/base/environment.sv @@ -25,6 +25,8 @@ package environment_pkg; // Constructor //============================================================================ function new ( + input string name, + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if, virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if, virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if, @@ -36,7 +38,8 @@ package environment_pkg; ); // Creating the agents - super.new(sys_clk_vip_if, + super.new(name, + sys_clk_vip_if, dma_clk_vip_if, ddr_clk_vip_if, sys_rst_vip_if, diff --git a/testbenches/ip/base/tests/test_program.sv b/testbenches/ip/base/tests/test_program.sv index 7f0da586..ecb5a4ef 100644 --- a/testbenches/ip/base/tests/test_program.sv +++ b/testbenches/ip/base/tests/test_program.sv @@ -54,12 +54,13 @@ program test_program; current_process = process::self(); current_process_random_state = current_process.get_randstate(); - `INFO(("Randomization state: %s", current_process_random_state)); + `INFO(("Randomization state: %s", current_process_random_state), ADI_VERBOSITY_NONE); - setLoggerVerbosity(250); + setLoggerVerbosity(ADI_VERBOSITY_NONE); // Create environment - env = new(`TH.`SYS_CLK.inst.IF, + env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, `TH.`SYS_RST.inst.IF, @@ -78,7 +79,7 @@ program test_program; env.stop(); - `INFO(("Test bench done!")); + `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); $finish(); end diff --git a/testbenches/ip/data_offload/do_scoreboard.sv b/testbenches/ip/data_offload/do_scoreboard.sv index e6a5b766..5d7b3a70 100644 --- a/testbenches/ip/data_offload/do_scoreboard.sv +++ b/testbenches/ip/data_offload/do_scoreboard.sv @@ -85,7 +85,7 @@ package do_scoreboard_pkg; if (!this.enabled) begin this.tx_sink_type = sink_type_t'(sink_type); end else begin - `ERROR(("ERROR Scoreboard: Can not configure sink_type while scoreboard is running.")); + `FATAL(("ERROR Scoreboard: Can not configure sink_type while scoreboard is running.")); end endfunction @@ -111,11 +111,11 @@ package do_scoreboard_pkg; for (int j=0; j 0) begin - `INFOV(("Caught a TX AXI4 stream transaction: %d", this.tx_sink_axis_ap.get_item_cnt()), 100); + `INFO(("Caught a TX AXI4 stream transaction: %d", this.tx_sink_axis_ap.get_item_cnt()), ADI_VERBOSITY_LOW); this.tx_sink_axis_ap.get(transaction); // all bytes from a beat are valid num_bytes = transaction.get_data_width()/8; @@ -175,7 +175,7 @@ package do_scoreboard_pkg; forever begin if (this.rx_source_axis_ap.get_item_cnt() > 0) begin - `INFOV(("Caught a RX AXI4 stream transaction: %d", this.rx_source_axis_ap.get_item_cnt()), 100); + `INFO(("Caught a RX AXI4 stream transaction: %d", this.rx_source_axis_ap.get_item_cnt()), ADI_VERBOSITY_LOW); this.rx_source_axis_ap.get(transaction); // all bytes from a beat are valid num_bytes = transaction.get_data_width()/8; @@ -203,7 +203,7 @@ package do_scoreboard_pkg; this.rx_source_byte_stream_size--; sink_byte = this.rx_sink_byte_stream.pop_front(); this.rx_sink_byte_stream_size--; - `INFOV(("Scoreboard RX sink/source data: exp %h - rcv %h", source_byte, sink_byte), 100); + `INFO(("Scoreboard RX sink/source data: exp %h - rcv %h", source_byte, sink_byte), ADI_VERBOSITY_LOW); if (source_byte !== sink_byte) begin `ERROR(("RX Scoreboard failed at: exp %h - rcv %h", source_byte, sink_byte)); this.rx_error_cnt++; @@ -229,9 +229,9 @@ package do_scoreboard_pkg; this.tx_source_byte_stream_size--; sink_byte = this.tx_sink_byte_stream.pop_front(); this.tx_sink_byte_stream_size--; - `INFOV(("Scoreboard TX sink/source data: exp %h - rcv %h", source_byte, sink_byte), 100); + `INFO(("Scoreboard TX sink/source data: exp %h - rcv %h", source_byte, sink_byte), ADI_VERBOSITY_LOW); if (source_byte !== sink_byte) begin - `INFOV(("TX Scoreboard failed at: exp %h - rcv %h", source_byte, sink_byte), 100); + `INFO(("TX Scoreboard failed at: exp %h - rcv %h", source_byte, sink_byte), ADI_VERBOSITY_LOW); this.tx_error_cnt++; this.tx_comparison_cnt++; end else begin @@ -273,31 +273,29 @@ package do_scoreboard_pkg; function void post_tx_test(); if (this.enabled == 0) begin - `INFO(("Scoreboard was inactive.")); + `INFO(("Scoreboard was inactive."), ADI_VERBOSITY_LOW); end else begin if (tx_comparison_cnt == 0) begin - `ERROR(("TX scoreboard is empty! Check your interfaces or increase the runtime. Collected transactions are %d for source side and %d for sink side.", this.tx_source_byte_stream_size, this.tx_sink_byte_stream_size)); + `FATAL(("TX scoreboard is empty! Check your interfaces or increase the runtime. Collected transactions are %d for source side and %d for sink side.", this.tx_source_byte_stream_size, this.tx_sink_byte_stream_size)); end else if (tx_error_cnt > 0) begin - `ERROR(("ERROR: TX scoreboard has %d errors!", tx_error_cnt)); - `INFO(("TX scoreboard has passed. %d bytes were checked.", this.tx_comparison_cnt)); - `INFO(("TX transfer size are %d bytes.", this.tx_all_transfer_size)); + `FATAL(("ERROR: TX scoreboard has %d errors!", tx_error_cnt)); end else begin - `INFO(("TX scoreboard has passed. %d bytes were checked.", this.tx_comparison_cnt)); - `INFO(("TX transfer size are %d bytes.", this.tx_all_transfer_size)); + `INFO(("TX scoreboard has passed. %d bytes were checked.", this.tx_comparison_cnt), ADI_VERBOSITY_LOW); + `INFO(("TX transfer size are %d bytes.", this.tx_all_transfer_size), ADI_VERBOSITY_LOW); end end endfunction /* post_tx_test */ function void post_rx_test(); if (this.enabled == 0) begin - `INFO(("Scoreboard was inactive.")); + `INFO(("Scoreboard was inactive."), ADI_VERBOSITY_LOW); end else begin if (rx_comparison_cnt == 0) begin - `ERROR(("RX scoreboard is empty! Check your interfaces or increase the runtime. Collected transactions are %d for source side and %d for sink side.", this.rx_source_byte_stream_size, this.rx_sink_byte_stream_size)); + `FATAL(("RX scoreboard is empty! Check your interfaces or increase the runtime. Collected transactions are %d for source side and %d for sink side.", this.rx_source_byte_stream_size, this.rx_sink_byte_stream_size)); end else if (rx_error_cnt > 0) begin - `ERROR(("ERROR: RX scoreboard has %d errors!", rx_error_cnt)); + `FATAL(("ERROR: RX scoreboard has %d errors!", rx_error_cnt)); end else begin - `INFO(("RX scoreboard has passed. %d bytes were checked.", this.rx_comparison_cnt)); + `INFO(("RX scoreboard has passed. %d bytes were checked.", this.rx_comparison_cnt), ADI_VERBOSITY_LOW); end end endfunction /* post_rx_test */ diff --git a/testbenches/ip/data_offload/environment.sv b/testbenches/ip/data_offload/environment.sv index de537560..66c3fafe 100644 --- a/testbenches/ip/data_offload/environment.sv +++ b/testbenches/ip/data_offload/environment.sv @@ -50,15 +50,15 @@ package environment_pkg; mng_agent = new("AXI Manager Agent", mng_vip_if); ddr_agent = new("System DDR Agent", ddr_vip_if); plddr_agent = new("PL DDR Agent", pl_ddr_vip_if); - adc_src_axis_agent = new("ADC Source AXI Stream Agent", adc_src_axis_vip_if); + adc_src_axis_agent = new("ADC Source AXI Stream Agent", adc_src_axis_vip_if); dac_dst_axis_agent = new("DAC Destination AXI Stream Agent", dac_dst_axis_vip_if); // create sequencers - mng = new(mng_agent); - ddr = new(ddr_agent); - adc_src_axis_seq = new(adc_src_axis_agent); - dac_dst_axis_seq = new(dac_dst_axis_agent); + mng = new("AXI Manager Seuencer", mng_agent); + ddr = new("System DDR Sequencer", ddr_agent); + adc_src_axis_seq = new("ADC Source AXI Stream Sequencer", adc_src_axis_agent); + dac_dst_axis_seq = new("DAC Destination AXI Stream Sequencer", dac_dst_axis_agent); // create scoreboard scoreboard = new("Data Offload Verification Environment Scoreboard"); @@ -123,7 +123,7 @@ package environment_pkg; ADC_TRANSACTION_FAIL: assert(rx_transaction.randomize()); rx_transaction.set_delay(adc_data_rate_ratio - 1); adc_src_axis_agent.driver.send(rx_transaction); - `INFOV(("Sent new transaction to ADC driver"), 55); + `INFO(("Sent new transaction to ADC driver"), ADI_VERBOSITY_LOW); #0; end else begin #1; diff --git a/testbenches/ip/data_offload/tests/test_program.sv b/testbenches/ip/data_offload/tests/test_program.sv index 4cc7b4d8..3268193e 100644 --- a/testbenches/ip/data_offload/tests/test_program.sv +++ b/testbenches/ip/data_offload/tests/test_program.sv @@ -90,7 +90,7 @@ module test_program(); //========================================================================= - setLoggerVerbosity(250); + setLoggerVerbosity(ADI_VERBOSITY_NONE); `TH.`PLDDR_RST.inst.IF.assert_reset; #1; @@ -102,29 +102,29 @@ module test_program(); env.start(); #100 - `INFO(("Bring up IP from reset.")); + `INFO(("Bring up IP from reset."), ADI_VERBOSITY_LOW); systemBringUp(); //do_set_transfer_length(`ADC_TRANSFER_LENGTH); do_set_transfer_length(`ADC_TRANSFER_LENGTH/64); // Start the ADC/DAC stubs - `INFO(("Call the run() ...")); + `INFO(("Call the run() ..."), ADI_VERBOSITY_LOW); env.run(); env.adc_src_axis_seq.start(); // Generate DMA transfers #100 - `INFO(("Start RX DMA ...")); + `INFO(("Start RX DMA ..."), ADI_VERBOSITY_LOW); rx_dma_transfer(`RX_DMA_BA, 32'h80000000, `ADC_TRANSFER_LENGTH); #10000 - `INFO(("Initialize the memory ...")); + `INFO(("Initialize the memory ..."), ADI_VERBOSITY_LOW); init_mem_64(32'h80000000, 1024); - `INFO(("Start TX DMA ...")); + `INFO(("Start TX DMA ..."), ADI_VERBOSITY_LOW); tx_dma_transfer(`TX_DMA_BA, 32'h80000000, 1024); #30000 @@ -132,7 +132,7 @@ module test_program(); stop_clocks(); - `INFO(("Test bench done!")); + `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); $finish(); end @@ -171,9 +171,9 @@ module test_program(); task systemBringUp(); // bring up the Data Offload instances from reset - `INFO(("Bring up RX Data Offload")); + `INFO(("Bring up RX Data Offload"), ADI_VERBOSITY_LOW); env.mng.RegWrite32(`RX_DOFF_BA + `DO_ADDR_CONTROL_1, 32'h1); - `INFO(("Bring up TX Data Offload")); + `INFO(("Bring up TX Data Offload"), ADI_VERBOSITY_LOW); env.mng.RegWrite32(`TX_DOFF_BA + `DO_ADDR_CONTROL_1, 32'h1); // Enable tx oneshot mode @@ -181,9 +181,9 @@ module test_program(); // bring up the DMAC instances from reset - `INFO(("Bring up RX DMAC")); + `INFO(("Bring up RX DMAC"), ADI_VERBOSITY_LOW); env.mng.RegWrite32(`RX_DMA_BA + `DMAC_ADDR_CONTROL, 32'h1); - `INFO(("Bring up TX DMAC")); + `INFO(("Bring up TX DMAC"), ADI_VERBOSITY_LOW); env.mng.RegWrite32(`TX_DMA_BA + `DMAC_ADDR_CONTROL, 32'h1); endtask diff --git a/testbenches/ip/data_offload_2/data_offload_pkg.sv b/testbenches/ip/data_offload_2/data_offload_pkg.sv index 6ca322b4..9b79fdb9 100644 --- a/testbenches/ip/data_offload_2/data_offload_pkg.sv +++ b/testbenches/ip/data_offload_2/data_offload_pkg.sv @@ -90,15 +90,15 @@ package data_offload_pkg; task set_transfer_length(input bit [33:0] length); if (length & 34'h3f) begin // Transfer length not divisble by 64 - `ERROR(("data_offload: Attempted to set transfer_length %x mod 64 != 0!", length)); + `FATAL(("data_offload: Attempted to set transfer_length %x mod 64 != 0!", length)); end - `INFO(("data_offload: Writing transfer length! %x", length)); + `INFO(("data_offload: Writing transfer length! %x", length), ADI_VERBOSITY_LOW); this.bus.RegWrite32(this.base_address + `DO_ADDR_TRANSFER_LENGTH, length >> 6); endtask : set_transfer_length; task set_sync_config(input bit [1:0] sync_config); if (sync_config == 3) - `ERROR(("data_offload: Invalid sync_config mode 3 requested!")); + `FATAL(("data_offload: Invalid sync_config mode 3 requested!")); this.bus.RegWrite32(this.base_address + `DO_ADDR_SYNC_CONFIG, {30'h0, sync_config}); endtask : set_sync_config; diff --git a/testbenches/ip/data_offload_2/do_scoreboard.sv b/testbenches/ip/data_offload_2/do_scoreboard.sv index 252b7061..8a4f56a3 100644 --- a/testbenches/ip/data_offload_2/do_scoreboard.sv +++ b/testbenches/ip/data_offload_2/do_scoreboard.sv @@ -103,7 +103,7 @@ package do_scoreboard_pkg; if (!this.enabled) begin this.do_mode = do_mode_t'(do_mode); end else begin - `ERROR(("ERROR Scoreboard: Can not configure oneshot mode while scoreboard is running.")); + `FATAL(("ERROR Scoreboard: Can not configure oneshot mode while scoreboard is running.")); end endfunction @@ -111,7 +111,7 @@ package do_scoreboard_pkg; if (!this.enabled) begin this.path_type = path_type_t'(path_type); end else begin - `ERROR(("ERROR Scoreboard: Can not configure path type while scoreboard is running!")); + `FATAL(("ERROR Scoreboard: Can not configure path type while scoreboard is running!")); end endfunction @@ -131,7 +131,7 @@ package do_scoreboard_pkg; forever begin if (this.src_axis_ap.get_item_cnt() > 0) begin - `INFOV(("Caught a TX AXI4 stream transaction: %d", this.src_axis_ap.get_item_cnt()), 100); + `INFO(("Caught a TX AXI4 stream transaction: %d", this.src_axis_ap.get_item_cnt()), ADI_VERBOSITY_LOW); this.src_axis_ap.get(transaction); // all bytes from a beat are valid num_bytes = transaction.get_data_width()/8; @@ -170,7 +170,7 @@ package do_scoreboard_pkg; forever begin if (this.dst_axis_ap.get_item_cnt() > 0) begin - `INFOV(("Caught a RX AXI4 stream transaction: %d", this.dst_axis_ap.get_item_cnt()), 100); + `INFO(("Caught a RX AXI4 stream transaction: %d", this.dst_axis_ap.get_item_cnt()), ADI_VERBOSITY_LOW); this.dst_axis_ap.get(transaction); // all bytes from a beat are valid num_bytes = transaction.get_data_width()/8; @@ -181,7 +181,7 @@ package do_scoreboard_pkg; reading_lock.put(); if (this.byte_stream.size() == 0) begin - `ERROR(("ERROR: Received unexpected transfer - is the data_offload running cyclically?")); + `FATAL(("ERROR: Received unexpected transfer - is the data_offload running cyclically?")); continue; end @@ -202,12 +202,12 @@ package do_scoreboard_pkg; function void post_test(); if (this.enabled == 0) begin - `INFO(("Scoreboard was inactive.")); + `INFO(("Scoreboard was inactive."), ADI_VERBOSITY_LOW); end else begin if (this.do_mode == ONESHOT && this.byte_stream.size() > 0) begin - `ERROR(("ERROR: Not all samples have arrived yet!")); + `FATAL(("ERROR: Not all samples have arrived yet!")); end else begin - `INFO(("Scoreboard passed!")); + `INFO(("Scoreboard passed!"), ADI_VERBOSITY_LOW); end end endfunction /* post_tx_test */ diff --git a/testbenches/ip/data_offload_2/environment.sv b/testbenches/ip/data_offload_2/environment.sv index 6d327e62..f204d1fb 100644 --- a/testbenches/ip/data_offload_2/environment.sv +++ b/testbenches/ip/data_offload_2/environment.sv @@ -81,9 +81,9 @@ package environment_pkg; dst_axis_agent = new("Destination AXI Stream Agent", dst_axis_vip_if); // create sequencers - mng = new(mng_agent); - src_axis_seq = new(src_axis_agent); - dst_axis_seq = new(dst_axis_agent); + mng = new("AXI Manager Sequencer", mng_agent); + src_axis_seq = new("Source AXI Stream Sequencer", src_axis_agent); + dst_axis_seq = new("Destination AXI Stream Sequencer", dst_axis_agent); scoreboard = new("do_scoreboard"); @@ -146,7 +146,7 @@ package environment_pkg; TRANSACTION_FAIL: assert(rx_transaction.randomize()); rx_transaction.set_delay(data_rate_ratio - 1); src_axis_agent.driver.send(rx_transaction); - `INFOV(("Sent new transaction to ADC driver"), 55); + `INFO(("Sent new transaction to ADC driver"), ADI_VERBOSITY_LOW); #0; end else begin #1; diff --git a/testbenches/ip/data_offload_2/tests/test_program.sv b/testbenches/ip/data_offload_2/tests/test_program.sv index 234d1fd1..a58d67f2 100644 --- a/testbenches/ip/data_offload_2/tests/test_program.sv +++ b/testbenches/ip/data_offload_2/tests/test_program.sv @@ -90,7 +90,7 @@ module test_program( //========================================================================= - setLoggerVerbosity(250); + setLoggerVerbosity(ADI_VERBOSITY_NONE); env.scoreboard.set_oneshot(`OFFLOAD_ONESHOT); env.scoreboard.set_path_type(`OFFLOAD_PATH_TYPE); @@ -109,13 +109,13 @@ module test_program( `endif #100 - `INFO(("Bring up IP from reset.")); + `INFO(("Bring up IP from reset."), ADI_VERBOSITY_LOW); systemBringUp(); env.src_axis_seq.start(); // Start the ADC/DAC stubs - `INFO(("Call the run() ...")); + `INFO(("Call the run() ..."), ADI_VERBOSITY_LOW); env.run(); init_req <= 1'b1; @@ -145,7 +145,7 @@ module test_program( stop_clocks(); - `INFO(("Test bench done!")); + `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); $finish(); end @@ -182,7 +182,7 @@ module test_program( task systemBringUp(); // bring up the Data Offload instances from reset - `INFO(("Bring up TX Data Offload")); + `INFO(("Bring up TX Data Offload"), ADI_VERBOSITY_LOW); dut.set_oneshot(`OFFLOAD_ONESHOT); diff --git a/testbenches/ip/data_offload_2/tests/test_program_sync.sv b/testbenches/ip/data_offload_2/tests/test_program_sync.sv index 9bc9c449..4955b720 100644 --- a/testbenches/ip/data_offload_2/tests/test_program_sync.sv +++ b/testbenches/ip/data_offload_2/tests/test_program_sync.sv @@ -81,7 +81,7 @@ module test_program_sync ( //========================================================================= - setLoggerVerbosity(250); + setLoggerVerbosity(ADI_VERBOSITY_NONE); env.scoreboard.set_oneshot(1); @@ -92,13 +92,13 @@ module test_program_sync ( env.start(); #100 - `INFO(("Bring up IP from reset.")); + `INFO(("Bring up IP from reset."), ADI_VERBOSITY_LOW); systemBringUp(); env.src_axis_seq.start(); // Start the ADC/DAC stubs - `INFO(("Call the run() ...")); + `INFO(("Call the run() ..."), ADI_VERBOSITY_LOW); env.run(); init_req <= 1'b1; @@ -156,7 +156,7 @@ module test_program_sync ( stop_clocks(); - `INFO(("Test bench done!")); + `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); $finish(); end @@ -189,7 +189,7 @@ module test_program_sync ( task systemBringUp(); // bring up the Data Offload instances from reset - `INFO(("Bring up TX Data Offload")); + `INFO(("Bring up TX Data Offload"), ADI_VERBOSITY_LOW); dut.set_oneshot(0); dut.set_sync_config(1); // Hardware Sync diff --git a/testbenches/ip/dma_loopback/tests/test_program.sv b/testbenches/ip/dma_loopback/tests/test_program.sv index bdb5b8c0..0e609f33 100644 --- a/testbenches/ip/dma_loopback/tests/test_program.sv +++ b/testbenches/ip/dma_loopback/tests/test_program.sv @@ -56,7 +56,8 @@ program test_program; initial begin //creating environment - env = new(`TH.`SYS_CLK.inst.IF, + env = new("DMA Loopback Environment", + `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, `TH.`SYS_RST.inst.IF, @@ -65,13 +66,13 @@ program test_program; #2ps; - setLoggerVerbosity(6); + setLoggerVerbosity(ADI_VERBOSITY_NONE); env.start(); - m_dmac_api = new("TX_DMA_BA", env.mng, `TX_DMA_BA); + m_dmac_api = new("TX_DMA", env.mng, `TX_DMA_BA); m_dmac_api.probe(); - s_dmac_api = new("RX_DMA_BA", env.mng, `RX_DMA_BA); + s_dmac_api = new("RX_DMA", env.mng, `RX_DMA_BA); s_dmac_api.probe(); start_clocks(); diff --git a/testbenches/ip/dma_sg/tests/test_program_1d.sv b/testbenches/ip/dma_sg/tests/test_program_1d.sv index 8e714bf4..12921e48 100644 --- a/testbenches/ip/dma_sg/tests/test_program_1d.sv +++ b/testbenches/ip/dma_sg/tests/test_program_1d.sv @@ -56,7 +56,8 @@ program test_program_1d; initial begin // Creating environment - env = new(`TH.`SYS_CLK.inst.IF, + env = new("DMA SG Environment", + `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, `TH.`SYS_RST.inst.IF, @@ -65,16 +66,16 @@ program test_program_1d; #2ps; - setLoggerVerbosity(6); + setLoggerVerbosity(ADI_VERBOSITY_NONE); env.start(); `TH.`DEVICE_CLK.inst.IF.start_clock(); env.sys_reset(); - m_dmac_api = new("TX_DMA_BA", env.mng, `TX_DMA_BA); + m_dmac_api = new("TX_DMA", env.mng, `TX_DMA_BA); m_dmac_api.probe(); - s_dmac_api = new("RX_DMA_BA", env.mng, `RX_DMA_BA); + s_dmac_api = new("RX_DMA", env.mng, `RX_DMA_BA); s_dmac_api.probe(); #1us; @@ -147,6 +148,11 @@ program test_program_1d; .length('h8000) ); + env.stop(); + + `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); + $finish(); + end task write_descriptor(bit [31:0] desc_addr, diff --git a/testbenches/ip/dma_sg/tests/test_program_2d.sv b/testbenches/ip/dma_sg/tests/test_program_2d.sv index accc7558..e585c255 100644 --- a/testbenches/ip/dma_sg/tests/test_program_2d.sv +++ b/testbenches/ip/dma_sg/tests/test_program_2d.sv @@ -56,7 +56,8 @@ program test_program_2d; initial begin // Creating environment - env = new(`TH.`SYS_CLK.inst.IF, + env = new("DMA SG Environment", + `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, `TH.`SYS_RST.inst.IF, @@ -65,16 +66,16 @@ program test_program_2d; #2ps; - setLoggerVerbosity(6); + setLoggerVerbosity(ADI_VERBOSITY_NONE); env.start(); `TH.`DEVICE_CLK.inst.IF.start_clock(); env.sys_reset(); - m_dmac_api = new("TX_DMA_BA", env.mng, `TX_DMA_BA); + m_dmac_api = new("TX_DMA", env.mng, `TX_DMA_BA); m_dmac_api.probe(); - s_dmac_api = new("RX_DMA_BA", env.mng, `RX_DMA_BA); + s_dmac_api = new("RX_DMA", env.mng, `RX_DMA_BA); s_dmac_api.probe(); #1us; @@ -141,6 +142,11 @@ program test_program_2d; .length('h8000) ); + env.stop(); + + `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); + $finish(); + end task write_descriptor(bit [31:0] desc_addr, diff --git a/testbenches/ip/dma_sg/tests/test_program_tr_queue.sv b/testbenches/ip/dma_sg/tests/test_program_tr_queue.sv index 9d9b4b6d..1fdbd096 100644 --- a/testbenches/ip/dma_sg/tests/test_program_tr_queue.sv +++ b/testbenches/ip/dma_sg/tests/test_program_tr_queue.sv @@ -56,7 +56,8 @@ program test_program_tr_queue; initial begin // Creating environment - env = new(`TH.`SYS_CLK.inst.IF, + env = new("DMA SG Environment", + `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, `TH.`SYS_RST.inst.IF, @@ -65,16 +66,16 @@ program test_program_tr_queue; #2ps; - setLoggerVerbosity(6); + setLoggerVerbosity(ADI_VERBOSITY_NONE); env.start(); `TH.`DEVICE_CLK.inst.IF.start_clock(); env.sys_reset(); - m_dmac_api = new("TX_DMA_BA", env.mng, `TX_DMA_BA); + m_dmac_api = new("TX_DMA", env.mng, `TX_DMA_BA); m_dmac_api.probe(); - s_dmac_api = new("RX_DMA_BA", env.mng, `RX_DMA_BA); + s_dmac_api = new("RX_DMA", env.mng, `RX_DMA_BA); s_dmac_api.probe(); #1us; @@ -153,6 +154,11 @@ program test_program_tr_queue; .length('h8000) ); + env.stop(); + + `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); + $finish(); + end task write_descriptor(bit [31:0] desc_addr, diff --git a/testbenches/ip/hbm/tests/test_program.sv b/testbenches/ip/hbm/tests/test_program.sv index aa4e4408..a8480581 100644 --- a/testbenches/ip/hbm/tests/test_program.sv +++ b/testbenches/ip/hbm/tests/test_program.sv @@ -57,7 +57,8 @@ program test_program; initial begin //creating environment - env = new(`TH.`SYS_CLK.inst.IF, + env = new("HBM Environment", + `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, `TH.`SYS_RST.inst.IF, @@ -66,15 +67,12 @@ program test_program; #2ps; - setLoggerVerbosity(6); + setLoggerVerbosity(ADI_VERBOSITY_NONE); env.start(); `TH.`HBM_CLK.inst.IF.start_clock; - //asserts all the resets for 100 ns - `TH.`SYS_RST.inst.IF.assert_reset; - #100 - `TH.`SYS_RST.inst.IF.deassert_reset; + env.sys_reset(); #1us; @@ -100,6 +98,11 @@ program test_program; // .dest_addr(`DDR_BASE+'h2000), // .length('h1000) // ); +// +// env.stop(); +// +// `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); +// $finish(); // end diff --git a/testbenches/ip/i3c_controller/tests/test_program.sv b/testbenches/ip/i3c_controller/tests/test_program.sv index 0be4fc4b..1fe35528 100755 --- a/testbenches/ip/i3c_controller/tests/test_program.sv +++ b/testbenches/ip/i3c_controller/tests/test_program.sv @@ -53,7 +53,7 @@ import test_harness_env_pkg::*; fork \ begin \ #``TIMEOUT``ns \ - `ERROR(("Wait statement expired.")); \ + `FATAL(("Wait statement expired.")); \ end \ begin \ wait (CONDITION); \ @@ -203,11 +203,11 @@ endtask // Information //--------------------------------------------------------------------------- task print_cmdr (input int data); - `INFO(("[%t] Got CMDR error %d, length %d, sync %d", $time, data[23:20], data[19:8], data[7:0])); + `INFO(("[%t] Got CMDR error %d, length %d, sync %d", $time, data[23:20], data[19:8], data[7:0]), ADI_VERBOSITY_LOW); endtask task print_ibi(input int data); - `INFO(("[%t] Got IBI DA %b, MDB %b, Sync %d.", $time, data[23:17], data[15:08], data[7:0])); + `INFO(("[%t] Got IBI DA %b, MDB %b, Sync %d.", $time, data[23:17], data[15:08], data[7:0]), ADI_VERBOSITY_LOW); endtask //--------------------------------------------------------------------------- @@ -248,14 +248,15 @@ end initial begin // Creating environment - env = new(`TH.`SYS_CLK.inst.IF, + env = new("I3C Controller Environment", + `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, `TH.`SYS_RST.inst.IF, `TH.`MNG_AXI.inst.IF, `TH.`DDR_AXI.inst.IF); - setLoggerVerbosity(6); + setLoggerVerbosity(ADI_VERBOSITY_NONE); env.start(); env.sys_reset(); @@ -282,7 +283,9 @@ initial begin ibi_i3c_test(); - `INFO(("Test Done")); + env.stop(); + + `INFO(("Test Done"), ADI_VERBOSITY_NONE); $finish; @@ -299,13 +302,13 @@ initial begin axi_read (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_PENDING, irq_pending); if (irq_pending & (1'b1 << `I3C_REGMAP_IRQ_CMDR_PENDING)) begin - `INFO(("[%t] NOTE: Got CMDR IRQ", $time)); + `INFO(("[%t] NOTE: Got CMDR IRQ", $time), ADI_VERBOSITY_LOW); end else if (irq_pending & (1'b1 << `I3C_REGMAP_IRQ_IBI_PENDING)) begin - `INFO(("[%t] NOTE: Got IBI IRQ", $time)); + `INFO(("[%t] NOTE: Got IBI IRQ", $time), ADI_VERBOSITY_LOW); end else if (irq_pending & (1'b1 << `I3C_REGMAP_IRQ_DAA_PENDING)) begin - `INFO(("[%t] NOTE: Got DAA IRQ", $time)); + `INFO(("[%t] NOTE: Got DAA IRQ", $time), ADI_VERBOSITY_LOW); end else begin - `INFO(("[%t] NOTE: Got IRQ %h", $time, irq_pending)); + `INFO(("[%t] NOTE: Got IRQ %h", $time, irq_pending), ADI_VERBOSITY_LOW); end end end @@ -314,12 +317,12 @@ end // Sanity test reg interface //--------------------------------------------------------------------------- task sanity_test(); - `INFO(("Sanity Started")); + `INFO(("Sanity Started"), ADI_VERBOSITY_LOW); axi_read_v (`I3C_CONTROLLER_BA, `I3C_REGMAP_VERSION, I3C_VERSION_CHECK); axi_read_v (`I3C_CONTROLLER_BA, `I3C_REGMAP_DEVICE_ID, I3C_DEVICE_ID_CHECK); axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_SCRATCH, I3C_SCRATCH_CHECK); axi_read_v (`I3C_CONTROLLER_BA, `I3C_REGMAP_SCRATCH, I3C_SCRATCH_CHECK); - `INFO(("Sanity Test Done")); + `INFO(("Sanity Test Done"), ADI_VERBOSITY_LOW); endtask //--------------------------------------------------------------------------- @@ -329,7 +332,7 @@ bit [31:0] cmdr_fifo_data = 0; bit [31:0] sdi_fifo_data = 0; task ccc_i3c_test; - `INFO(("CCC I3C Started")); + `INFO(("CCC I3C Started"), ADI_VERBOSITY_LOW); auto_ack <= 1'b1; @@ -340,7 +343,7 @@ task ccc_i3c_test; axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_MASK, 32'h20); // Test #1, CCC without payload - `INFO(("CCC I3C Test #1")); + `INFO(("CCC I3C Test #1"), ADI_VERBOSITY_LOW); axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_CMD_FIFO, I3C_CCC_CMD_RSTDAA); // CCC, length 0 axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_CMD_FIFO, I3C_CCC_RSTDAA); @(posedge i3c_irq); @@ -348,10 +351,10 @@ task ccc_i3c_test; axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_PENDING, 1'b1 << `I3C_REGMAP_IRQ_CMDR_PENDING); print_cmdr (cmdr_fifo_data); if (cmdr_fifo_data[19:8] != 0) - `ERROR(("CMD -> CMDR read length test FAILED")); + `FATAL(("CMD -> CMDR read length test FAILED")); // Test #2, CCC with length 1 write payload - `INFO(("CCC I3C Test #2")); + `INFO(("CCC I3C Test #2"), ADI_VERBOSITY_LOW); axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_SDO_FIFO, 32'h0000000b); // See DISEC spec. for +info axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_CMD_FIFO, I3C_CCC_CMD_DISEC); // CCC, length tx 1 axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_CMD_FIFO, I3C_CCC_DISEC); @@ -360,10 +363,10 @@ task ccc_i3c_test; axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_PENDING, 1'b1 << `I3C_REGMAP_IRQ_CMDR_PENDING); print_cmdr (cmdr_fifo_data); if (cmdr_fifo_data[19:8] != 1) - `ERROR(("CMD -> CMDR write length test FAILED")); + `FATAL(("CMD -> CMDR write length test FAILED")); // Test #3, CCC with length 6 read payload but DA is unknown - `INFO(("CCC I3C Test #3")); + `INFO(("CCC I3C Test #3"), ADI_VERBOSITY_LOW); axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_CMD_FIFO, I3C_CMD_GETPID_UDA); // CCC, length rx 6 axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_CMD_FIFO, I3C_CCC_GETPID); wait (i3c_irq); @@ -371,10 +374,10 @@ task ccc_i3c_test; axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_PENDING, 1'b1 << `I3C_REGMAP_IRQ_CMDR_PENDING); print_cmdr (cmdr_fifo_data); if (cmdr_fifo_data[23:20] != 8) - `ERROR(("#4: CMD -> CMDR UDA_ERROR assertion FAILED")); + `FATAL(("#4: CMD -> CMDR UDA_ERROR assertion FAILED")); // Test #4, CCC with length 6 read payload, DA is known - `INFO(("CCC I3C Test #4")); + `INFO(("CCC I3C Test #4"), ADI_VERBOSITY_LOW); axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_CMD_FIFO, I3C_CMD_GETPID); // CCC, length rx 6 axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_CMD_FIFO, I3C_CCC_GETPID); wait (`DUT_I3C_WORD.st == `CMDW_MSG_RX); @@ -390,10 +393,10 @@ task ccc_i3c_test; axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_PENDING, 1'b1 << `I3C_REGMAP_IRQ_CMDR_PENDING); print_cmdr (cmdr_fifo_data); if (cmdr_fifo_data[19:8] != 6) - `ERROR(("CMD -> CMDR read length test FAILED")); + `FATAL(("CMD -> CMDR read length test FAILED")); // Test #5, CCC with length 1 read payload, DA is known - `INFO(("CCC I3C Test #5")); + `INFO(("CCC I3C Test #5"), ADI_VERBOSITY_LOW); axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_CMD_FIFO, I3C_CMD_GETDCR); // CCC, length rx 1 axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_CMD_FIFO, I3C_CCC_GETDCR); wait (`DUT_I3C_WORD.st == `CMDW_MSG_RX); @@ -407,20 +410,20 @@ task ccc_i3c_test; axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_PENDING, 1'b1 << `I3C_REGMAP_IRQ_CMDR_PENDING); print_cmdr (cmdr_fifo_data); if (cmdr_fifo_data[19:8] != 1) - `ERROR(("CMD -> CMDR read length test FAILED")); + `FATAL(("CMD -> CMDR read length test FAILED")); // Mask CMDR interrupt axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_MASK, 32'h00); // Clear all pending IRQs axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_PENDING, irq_pending); - `INFO(("CCC I3C Test Done")); + `INFO(("CCC I3C Test Done"), ADI_VERBOSITY_LOW); endtask //--------------------------------------------------------------------------- // Private transfer I3C Test //--------------------------------------------------------------------------- task priv_i3c_test(); - `INFO(("Private Transfer I3C Started")); + `INFO(("Private Transfer I3C Started"), ADI_VERBOSITY_LOW); // Disable IBI axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IBI_CONFIG, 2'b00); @@ -432,7 +435,7 @@ task priv_i3c_test(); axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_MASK, 32'h20); // Test #1, controller does private write transfer that is ACK - `INFO(("PRIV I3C Test #1")); + `INFO(("PRIV I3C Test #1"), ADI_VERBOSITY_LOW); // Write SDO payload axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_SDO_FIFO, 32'hDEAD_BEEF); @@ -443,7 +446,7 @@ task priv_i3c_test(); `WAIT (`DUT_I3C_BIT_MOD.nop == 1, 100000); // Test #2, controller does private read transfer that is ACK - `INFO(("PRIV I3C Test #2")); + `INFO(("PRIV I3C Test #2"), ADI_VERBOSITY_LOW); // Change speed grade to 6.25 MHz axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_OPS, {2'b10, 4'd0, 1'b0}); @@ -461,7 +464,7 @@ task priv_i3c_test(); // Test #3, controller does private read transfer that is cancelled // at the first T-Bit - `INFO(("PRIV I3C Test #3")); + `INFO(("PRIV I3C Test #3"), ADI_VERBOSITY_LOW); // Write CMD instruction axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_CMD_FIFO, I3C_CMD_3); @@ -478,7 +481,7 @@ task priv_i3c_test(); // Test #4, controller does private write transfer to an unknown DA. // Expected result: return UDA_ERROR in receipt - `INFO(("PRIV I3C Test #4")); + `INFO(("PRIV I3C Test #4"), ADI_VERBOSITY_LOW); // Write SDO payload axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_SDO_FIFO, 32'hDEAD_BEEF); @@ -488,7 +491,7 @@ task priv_i3c_test(); wait (`DUT_I3C_BIT_MOD.nop == 1); // Test #5, controller does private read transfer that is NACK - `INFO(("PRIV I3C Test #5")); + `INFO(("PRIV I3C Test #5"), ADI_VERBOSITY_LOW); // Write SDO payload axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_SDO_FIFO, 32'hDEAD_BEEF); @@ -502,7 +505,7 @@ task priv_i3c_test(); // Test #6, controller does private read transfer that is ACK, // no broadcast address. - `INFO(("PRIV I3C Test #6")); + `INFO(("PRIV I3C Test #6"), ADI_VERBOSITY_LOW); // Write CMD instruction axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_CMD_FIFO, I3C_CMD_5); @@ -518,68 +521,68 @@ task priv_i3c_test(); // Read Results if (~`DUT_I3C_REGMAP.up_irq_pending[`I3C_REGMAP_IRQ_CMDR_PENDING]) - `ERROR(("#0: IRQ CMDR FAILED")); + `FATAL(("#0: IRQ CMDR FAILED")); axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_PENDING, 1'b1 << `I3C_REGMAP_IRQ_CMDR_PENDING); axi_read (`I3C_CONTROLLER_BA, `I3C_REGMAP_CMDR_FIFO, cmdr_fifo_data); print_cmdr (cmdr_fifo_data); if (cmdr_fifo_data[19:8] != I3C_CMD_1[19:8]) // Wrote all bytes - `ERROR(("#1: CMD -> CMDR write length test FAILED")); + `FATAL(("#1: CMD -> CMDR write length test FAILED")); if (cmdr_fifo_data[23:20] != 0) - `ERROR(("#1: CMD -> CMDR NO_ERROR assertion FAILED")); + `FATAL(("#1: CMD -> CMDR NO_ERROR assertion FAILED")); axi_read (`I3C_CONTROLLER_BA, `I3C_REGMAP_CMDR_FIFO, cmdr_fifo_data); print_cmdr (cmdr_fifo_data); if (cmdr_fifo_data[19:8] != I3C_CMD_3[19:8]) // Read all bytes - `ERROR(("#2: CMD -> CMDR read length test FAILED")); + `FATAL(("#2: CMD -> CMDR read length test FAILED")); if (cmdr_fifo_data[23:20] != 0) - `ERROR(("#2: CMD -> CMDR NO_ERROR assertion FAILED")); + `FATAL(("#2: CMD -> CMDR NO_ERROR assertion FAILED")); axi_read (`I3C_CONTROLLER_BA, `I3C_REGMAP_CMDR_FIFO, cmdr_fifo_data); print_cmdr (cmdr_fifo_data); if (cmdr_fifo_data[19:8] != 1) // Read one byte - `ERROR(("#3: CMD -> CMDR read length test FAILED")); + `FATAL(("#3: CMD -> CMDR read length test FAILED")); if (cmdr_fifo_data[23:20] != 6) - `ERROR(("#3: CMD -> CMDR NACK_RESP assertion FAILED")); + `FATAL(("#3: CMD -> CMDR NACK_RESP assertion FAILED")); axi_read (`I3C_CONTROLLER_BA, `I3C_REGMAP_CMDR_FIFO, cmdr_fifo_data); print_cmdr (cmdr_fifo_data); if (cmdr_fifo_data[23:20] != 8) - `ERROR(("#4: CMD -> CMDR UDA_ERROR assertion FAILED")); + `FATAL(("#4: CMD -> CMDR UDA_ERROR assertion FAILED")); axi_read (`I3C_CONTROLLER_BA, `I3C_REGMAP_CMDR_FIFO, cmdr_fifo_data); print_cmdr (cmdr_fifo_data); if (cmdr_fifo_data[19:8] != 0) // Wrote no bytes - `ERROR(("#5: CMD -> CMDR write length test FAILED")); + `FATAL(("#5: CMD -> CMDR write length test FAILED")); if (cmdr_fifo_data[23:20] != 4) - `ERROR(("#5: CMD -> CMDR CEO_ERROR assertion FAILED")); + `FATAL(("#5: CMD -> CMDR CEO_ERROR assertion FAILED")); axi_read (`I3C_CONTROLLER_BA, `I3C_REGMAP_CMDR_FIFO, cmdr_fifo_data); print_cmdr (cmdr_fifo_data); if (cmdr_fifo_data[19:8] != I3C_CMD_5[19:8]) // Read all bytes - `ERROR(("#6: CMD -> CMDR read length test FAILED")); + `FATAL(("#6: CMD -> CMDR read length test FAILED")); if (cmdr_fifo_data[23:20] != 0) - `ERROR(("#6: CMD -> CMDR NO_ERROR assertion FAILED")); + `FATAL(("#6: CMD -> CMDR NO_ERROR assertion FAILED")); // Mask CMDR interrupt axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_MASK, 32'h00); // Clear all pending IRQs axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_PENDING, irq_pending); - `INFO(("Private Transfer I3C Ended")); + `INFO(("Private Transfer I3C Ended"), ADI_VERBOSITY_LOW); endtask //--------------------------------------------------------------------------- // Private transfer I²C Test //--------------------------------------------------------------------------- task priv_i2c_test(); - `INFO(("Private Transfer I2C Started")); + `INFO(("Private Transfer I2C Started"), ADI_VERBOSITY_LOW); // Unmask CMDR interrupt axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_MASK, 32'h20); // Test #1, controller does private write transfer that is ACK - `INFO(("PRIV I2C Test #1")); + `INFO(("PRIV I2C Test #1"), ADI_VERBOSITY_LOW); auto_ack <= 1'b1; // Write SDO payload @@ -590,12 +593,12 @@ task priv_i2c_test(); wait (`DUT_I3C_BIT_MOD.nop == 0); // Assert is in I²C mode if (`DUT_I3C_BIT_MOD.i2c_mode !== 1) - `ERROR(("Not in I2C mode!")); + `FATAL(("Not in I2C mode!")); wait (`DUT_I3C_BIT_MOD.nop == 1); // Test #2, controller does private read transfer and ACKs all receiving // bytes. - `INFO(("PRIV I2C Test #2")); + `INFO(("PRIV I2C Test #2"), ADI_VERBOSITY_LOW); // Write CMD instruction axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_CMD_FIFO, I2C_CMD_2); @@ -614,7 +617,7 @@ task priv_i2c_test(); auto_ack <= 1'b1; // Test #3, controller does private write transfer that stalls for a while - `INFO(("PRIV I2C Test #3")); + `INFO(("PRIV I2C Test #3"), ADI_VERBOSITY_LOW); auto_ack <= 1'b1; // Write SDO payload @@ -627,30 +630,30 @@ task priv_i2c_test(); wait (`DUT_I3C_BIT_MOD.sm == 1); #10000ns if (i3c_scl !== 0) - `ERROR(("Bus is not stalled (SCL != 0)")); + `FATAL(("Bus is not stalled (SCL != 0)")); axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_SDO_FIFO, 32'h0000_00DE); wait (`DUT_I3C_BIT_MOD.nop == 1); // Read Results if (~`DUT_I3C_REGMAP.up_irq_pending[`I3C_REGMAP_IRQ_CMDR_PENDING]) - `ERROR(("#0: IRQ CMDR FAILED")); + `FATAL(("#0: IRQ CMDR FAILED")); axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_PENDING, 1'b1 << `I3C_REGMAP_IRQ_CMDR_PENDING); axi_read (`I3C_CONTROLLER_BA, `I3C_REGMAP_CMDR_FIFO, cmdr_fifo_data); print_cmdr (cmdr_fifo_data); if (cmdr_fifo_data[19:8] != I2C_CMD_1[19:8]) // Wrote all bytes - `ERROR(("#1: CMD -> CMDR write length test FAILED")); + `FATAL(("#1: CMD -> CMDR write length test FAILED")); axi_read (`I3C_CONTROLLER_BA, `I3C_REGMAP_CMDR_FIFO, cmdr_fifo_data); print_cmdr (cmdr_fifo_data); if (cmdr_fifo_data[23:20] == 4'd1) - `ERROR(("#2: CMD -> CMDR CE0_ERROR check FAILED")); + `FATAL(("#2: CMD -> CMDR CE0_ERROR check FAILED")); axi_read (`I3C_CONTROLLER_BA, `I3C_REGMAP_CMDR_FIFO, cmdr_fifo_data); print_cmdr (cmdr_fifo_data); if (cmdr_fifo_data[19:8] != 12'd6) // Wrote 6 bytes - `ERROR(("#3: CMD -> CMDR write length test FAILED")); + `FATAL(("#3: CMD -> CMDR write length test FAILED")); // Mask CMDR interrupt axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_MASK, 32'h00); @@ -661,7 +664,7 @@ task priv_i2c_test(); axi_read (`I3C_CONTROLLER_BA, `I3C_REGMAP_SDI_FIFO, sdi_fifo_data); end - `INFO(("Private Transfer I2C Ended")); + `INFO(("Private Transfer I2C Ended"), ADI_VERBOSITY_LOW); endtask //--------------------------------------------------------------------------- @@ -672,7 +675,7 @@ bit [31:0] ibi_fifo_data = 0; task ibi_i3c_test(); auto_ack <= 1'b0; - `INFO(("IBI I3C Test Started")); + `INFO(("IBI I3C Test Started"), ADI_VERBOSITY_LOW); // Unask IBI, CMDR interrupt axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_MASK, 32'h60); @@ -684,14 +687,14 @@ task ibi_i3c_test(); // Expected result: the controller accepts the IBI by driving SCL, // obtains the DA and MDB from the IBI. - `INFO(("IBI I3C Test #1")); + `INFO(("IBI I3C Test #1"), ADI_VERBOSITY_LOW); write_ibi_da(DEVICE_DA1); @(posedge i3c_irq); axi_read (`I3C_CONTROLLER_BA, `I3C_REGMAP_IBI_FIFO, ibi_fifo_data); print_ibi(ibi_fifo_data); if (ibi_fifo_data[23:17] != DEVICE_DA1) - `ERROR(("Wrong IBI DA")); + `FATAL(("Wrong IBI DA")); axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_PENDING, 1'b1 << `I3C_REGMAP_IRQ_IBI_PENDING); // Test #2, peripheral does an IBI request by sending its DA during broadcast @@ -699,7 +702,7 @@ task ibi_i3c_test(); // Expected result: the controller retrieves the DA and MDB from the IBI, // and continues the cmd transfer after resolving the IBI request. - `INFO(("IBI I3C Test #2")); + `INFO(("IBI I3C Test #2"), ADI_VERBOSITY_LOW); // Write SDO payload axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_SDO_FIFO, 32'hDEAD_BEEF); @@ -717,7 +720,7 @@ task ibi_i3c_test(); axi_read (`I3C_CONTROLLER_BA, `I3C_REGMAP_IBI_FIFO, ibi_fifo_data); print_ibi (ibi_fifo_data); if (ibi_fifo_data[23:17] != DEVICE_DA1) - `ERROR(("Wrong IBI DA")); + `FATAL(("Wrong IBI DA")); axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_PENDING, 1'b1 << `I3C_REGMAP_IRQ_IBI_PENDING); wait (i3c_irq); // cmdr_irq @@ -725,20 +728,20 @@ task ibi_i3c_test(); axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_PENDING, 1'b1 << `I3C_REGMAP_IRQ_CMDR_PENDING); print_cmdr (cmdr_fifo_data); if (cmdr_fifo_data[19:8] != I3C_CMD_1[19:8]) - `ERROR(("CMD transfer after resolving IBI FAILED")); + `FATAL(("CMD transfer after resolving IBI FAILED")); // Test #3, peripheral does IBI request by pulling SDA low, // but the DA is unkown. // Expected result: the controller rejects the IBI by NACKIng the, // request. No ibi is written to the FIFO. - `INFO(("IBI I3C Test #3")); + `INFO(("IBI I3C Test #3"), ADI_VERBOSITY_LOW); auto_ack <= 1'b0; write_ibi_da(START_DA); #10000ns if (`DUT_I3C_REGMAP.ibi_fifo_valid) - `ERROR(("IBI should not have thrown IBI")); + `FATAL(("IBI should not have thrown IBI")); // Test #4, peripheral does an IBI request by sending its DA during broadcast // address, but the DA is unknown @@ -747,7 +750,7 @@ task ibi_i3c_test(); // after resolving the IBI request. #12000ns - `INFO(("IBI I3C Test #4")); + `INFO(("IBI I3C Test #4"), ADI_VERBOSITY_LOW); // Write SDO payload axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_SDO_FIFO, 32'hDEAD_BEEF); @@ -764,9 +767,9 @@ task ibi_i3c_test(); axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_PENDING, 1'b1 << `I3C_REGMAP_IRQ_CMDR_PENDING); print_cmdr (cmdr_fifo_data); if (cmdr_fifo_data[19:8] != I3C_CMD_1[19:8]) - `ERROR(("CMD transfer after resolving IBI FAILED")); + `FATAL(("CMD transfer after resolving IBI FAILED")); if (`DUT_I3C_REGMAP.ibi_fifo_valid) - `ERROR(("IBI should not throwed IBI")); + `FATAL(("IBI should not throwed IBI")); // Test #5, peripheral does IBI request by pulling SDA low, DA is known but // BCR[2] is Low (no following MDB) @@ -774,7 +777,7 @@ task ibi_i3c_test(); // ACKs the IBI and follows with a Stop. #12000ns - `INFO(("IBI I3C Test #5")); + `INFO(("IBI I3C Test #5"), ADI_VERBOSITY_LOW); auto_ack <= 1'b0; write_ibi_da(DEVICE_DA1+1); @@ -782,7 +785,7 @@ task ibi_i3c_test(); axi_read (`I3C_CONTROLLER_BA, `I3C_REGMAP_IBI_FIFO, ibi_fifo_data); print_ibi(ibi_fifo_data); if (ibi_fifo_data[23:17] != DEVICE_DA1+1) - `ERROR(("Wrong IBI DA")); + `FATAL(("Wrong IBI DA")); axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_PENDING, 1'b1 << `I3C_REGMAP_IRQ_IBI_PENDING); // Test #6, peripheral does IBI request by pulling SDA low, but @@ -794,13 +797,13 @@ task ibi_i3c_test(); axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IBI_CONFIG, 2'b10); #12000ns - `INFO(("IBI I3C Test #6")); + `INFO(("IBI I3C Test #6"), ADI_VERBOSITY_LOW); auto_ack <= 1'b0; write_ibi_da(DEVICE_DA1+1); #10000ns if (`DUT_I3C_REGMAP.ibi_fifo_valid) - `ERROR(("IBI should not have thrown IBI")); + `FATAL(("IBI should not have thrown IBI")); auto_ack <= 1'b1; @@ -813,20 +816,20 @@ task ibi_i3c_test(); // Clear all pending IRQs axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_PENDING, irq_pending); - `INFO(("IBI I3C Test Done")); + `INFO(("IBI I3C Test Done"), ADI_VERBOSITY_LOW); endtask //--------------------------------------------------------------------------- // DAA I3C Test //--------------------------------------------------------------------------- task daa_i3c_test(); - `INFO(("DAA I3C Started")); + `INFO(("DAA I3C Started"), ADI_VERBOSITY_LOW); // Unmask the CMDR and DAA interrupt axi_write (`I3C_CONTROLLER_BA,`I3C_REGMAP_IRQ_MASK, 32'ha0); if (`DUT_I3C_REGMAP.i_sdi_fifo.m_axis_level) - `ERROR(("SDI FIFO must be empty for the DAA procedure")); + `FATAL(("SDI FIFO must be empty for the DAA procedure")); auto_ack <= 1'b1; // Disable IBI @@ -842,17 +845,17 @@ task daa_i3c_test(); `WAIT (`DUT_I3C_FRAMING.st == `CMDW_START, 10000); @(posedge i3c_irq); - `INFO(("GOT DAA IRQ")); + `INFO(("GOT DAA IRQ"), ADI_VERBOSITY_LOW); // Assert 2x32-bit in SDI FIFO (PID+BCR+DCR) if (`DUT_I3C_REGMAP.i_sdi_fifo.m_axis_level != 2) - `ERROR(("Wrong SDI FIFO level")); + `FATAL(("Wrong SDI FIFO level")); axi_read (`I3C_CONTROLLER_BA, `I3C_REGMAP_SDI_FIFO, sdi_fifo_data); axi_read (`I3C_CONTROLLER_BA, `I3C_REGMAP_SDI_FIFO, sdi_fifo_data); // Assert that irq won't be cleared if SDO is empty axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_PENDING, 1'b1 << `I3C_REGMAP_IRQ_DAA_PENDING); if (~`DUT_I3C_REGMAP.up_irq_pending[`I3C_REGMAP_IRQ_DAA_PENDING]) - `ERROR(("DAA IRQ should not have been cleared")); - `INFO(("Writing DA 1")); + `FATAL(("DAA IRQ should not have been cleared")); + `INFO(("Writing DA 1"), ADI_VERBOSITY_LOW); axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_SDO_FIFO, {24'h0, DEVICE_DA1, ~^DEVICE_DA1[6:0]}); axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_PENDING, 1'b1 << `I3C_REGMAP_IRQ_DAA_PENDING); @@ -863,12 +866,12 @@ task daa_i3c_test(); @(posedge i3c_irq); // Assert 2x32-bit in SDI FIFO (PID+BCR+DCR) if (`DUT_I3C_REGMAP.i_sdi_fifo.m_axis_level != 2) - `ERROR(("Wrong SDI FIFO level")); + `FATAL(("Wrong SDI FIFO level")); dev_char_state <= 1'b1; axi_read (`I3C_CONTROLLER_BA, `I3C_REGMAP_SDI_FIFO, sdi_fifo_data); axi_read (`I3C_CONTROLLER_BA, `I3C_REGMAP_SDI_FIFO, sdi_fifo_data); - `INFO(("Writing DA 2")); + `INFO(("Writing DA 2"), ADI_VERBOSITY_LOW); axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_SDO_FIFO, {24'h0, DEVICE_DA2, ~^DEVICE_DA2[6:0]}); axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_PENDING, 1'b1 << `I3C_REGMAP_IRQ_DAA_PENDING); @@ -885,7 +888,7 @@ task daa_i3c_test(); // Clear all pending IRQs axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_PENDING, irq_pending); - `INFO(("DAA I3C Test Done")); + `INFO(("DAA I3C Test Done"), ADI_VERBOSITY_LOW); endtask //--------------------------------------------------------------------------- @@ -900,7 +903,7 @@ bit [3:0] dev_char_3 = 4'b0011; bit [31:0] dev_char_data = 0; task dev_char_i3c_test(); - `INFO(("Device Characteristics I3C Test Started")); + `INFO(("Device Characteristics I3C Test Started"), ADI_VERBOSITY_LOW); // Write DEV_CHAR of four devices axi_write(`I3C_CONTROLLER_BA, `I3C_REGMAP_DEV_CHAR, {DEVICE_DA1, 1'b1, 4'h0, dev_char_0}); axi_write(`I3C_CONTROLLER_BA, `I3C_REGMAP_DEV_CHAR, {DEVICE_DA2, 1'b1, 4'h0, dev_char_1}); @@ -910,17 +913,17 @@ task dev_char_i3c_test(); // Read first and check value axi_write(`I3C_CONTROLLER_BA, `I3C_REGMAP_DEV_CHAR, {DEVICE_DA1 , 9'h0}); axi_read (`I3C_CONTROLLER_BA, `I3C_REGMAP_DEV_CHAR, dev_char_data); - `INFO(("[%t] Got DEV_CHAR_0 %h", $time, dev_char_data)); + `INFO(("[%t] Got DEV_CHAR_0 %h", $time, dev_char_data), ADI_VERBOSITY_LOW); if (dev_char_data[3:0] != dev_char_0 || dev_char_data[15:9] != DEVICE_DA1) - `ERROR(("DEV_CHAR_0 FAILED")); + `FATAL(("DEV_CHAR_0 FAILED")); // Read second and check value axi_write(`I3C_CONTROLLER_BA, `I3C_REGMAP_DEV_CHAR, {DEVICE_DA2, 9'h0}); axi_read (`I3C_CONTROLLER_BA, `I3C_REGMAP_DEV_CHAR, dev_char_data); - `INFO(("[%t] Got DEV_CHAR_0 %h", $time, dev_char_data)); + `INFO(("[%t] Got DEV_CHAR_0 %h", $time, dev_char_data), ADI_VERBOSITY_LOW); if (dev_char_data[3:0] != dev_char_1 || dev_char_data[15:9] != DEVICE_DA2) - `ERROR(("DEV_CHAR_0 FAILED")); + `FATAL(("DEV_CHAR_0 FAILED")); - `INFO(("Device Characteristics I3C Test Done")); + `INFO(("Device Characteristics I3C Test Done"), ADI_VERBOSITY_LOW); endtask //--------------------------------------------------------------------------- @@ -934,7 +937,7 @@ task offload_i3c_test(); // Mask all interrupts axi_write (`I3C_CONTROLLER_BA, `I3C_REGMAP_IRQ_MASK, 32'h00); - `INFO(("Offload I3C Test Started")); + `INFO(("Offload I3C Test Started"), ADI_VERBOSITY_LOW); offload_trigger_l = 1'b1; #10ns offload_trigger_l = 1'b0; @@ -970,7 +973,7 @@ task offload_i3c_test(); offload_trigger_l = 1'b1; #10ns offload_trigger_l = 1'b0; - `INFO(("Offload I3C Test Done")); + `INFO(("Offload I3C Test Done"), ADI_VERBOSITY_LOW); endtask endprogram diff --git a/testbenches/ip/jesd_loopback/tests/test_program.sv b/testbenches/ip/jesd_loopback/tests/test_program.sv index a9f95de8..b455b544 100644 --- a/testbenches/ip/jesd_loopback/tests/test_program.sv +++ b/testbenches/ip/jesd_loopback/tests/test_program.sv @@ -78,7 +78,8 @@ program test_program; initial begin //creating environment - env = new(`TH.`SYS_CLK.inst.IF, + env = new("JESD Loopback Environment", + `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, `TH.`SYS_RST.inst.IF, @@ -87,7 +88,7 @@ program test_program; #2ps; - setLoggerVerbosity(6); + setLoggerVerbosity(ADI_VERBOSITY_NONE); env.start(); link = new; @@ -146,9 +147,13 @@ program test_program; arm_disarm_test(); - `INFO(("=======================")); - `INFO((" TB DONE ")); - `INFO(("=======================")); + `INFO(("======================="), ADI_VERBOSITY_LOW); + `INFO((" TB DONE "), ADI_VERBOSITY_LOW); + `INFO(("======================="), ADI_VERBOSITY_LOW); + + env.stop(); + $finish; + end // ----------------- @@ -156,9 +161,9 @@ program test_program; // ----------------- task jesd_link_test(); - `INFO(("=======================")); - `INFO((" JESD TEST ")); - `INFO(("=======================")); + `INFO(("======================="), ADI_VERBOSITY_LOW); + `INFO((" JESD TEST "), ADI_VERBOSITY_LOW); + `INFO(("======================="), ADI_VERBOSITY_LOW); // ----------------------- // TX PHY INIT // ----------------------- @@ -294,9 +299,9 @@ program test_program; rx_xcvr.down(); tx_xcvr.down(); - `INFO(("=======================")); - `INFO((" JESD LINK TEST DONE ")); - `INFO(("=======================")); + `INFO(("======================="), ADI_VERBOSITY_LOW); + `INFO((" JESD LINK TEST DONE "), ADI_VERBOSITY_LOW); + `INFO(("======================="), ADI_VERBOSITY_LOW); endtask : jesd_link_test @@ -325,9 +330,9 @@ program test_program; `SET_DAC_COMMON_REG_SYNC_STATUS_DAC_SYNC_STATUS(0)); env.mng.RegReadVerify32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_SYNC_STATUS), `SET_ADC_COMMON_REG_SYNC_STATUS_ADC_SYNC(0)); - `INFO(("=======================")); - `INFO((" ARM-DISARM TEST DONE ")); - `INFO(("=======================")); + `INFO(("======================="), ADI_VERBOSITY_LOW); + `INFO((" ARM-DISARM TEST DONE "), ADI_VERBOSITY_LOW); + `INFO(("======================="), ADI_VERBOSITY_LOW); endtask : arm_disarm_test @@ -340,9 +345,9 @@ program test_program; bit [2:0] rx_out_clk_sel; bit [2:0] tx_out_clk_sel; - `INFO(("=======================")); - `INFO((" PRBS TEST ")); - `INFO(("=======================")); + `INFO(("======================="), ADI_VERBOSITY_LOW); + `INFO((" PRBS TEST "), ADI_VERBOSITY_LOW); + `INFO(("======================="), ADI_VERBOSITY_LOW); // Disable gearbox path for 64b66b mode // PRBS is on the buffer path @@ -459,9 +464,9 @@ program test_program; end - `INFO(("=======================")); - `INFO((" PRBS TEST DONE ")); - `INFO(("=======================")); + `INFO(("======================="), ADI_VERBOSITY_LOW); + `INFO((" PRBS TEST DONE "), ADI_VERBOSITY_LOW); + `INFO(("======================="), ADI_VERBOSITY_LOW); endtask : prbs_test diff --git a/testbenches/ip/jesd_loopback_64b/environment.sv b/testbenches/ip/jesd_loopback_64b/environment.sv deleted file mode 100644 index 24f84ec3..00000000 --- a/testbenches/ip/jesd_loopback_64b/environment.sv +++ /dev/null @@ -1,100 +0,0 @@ -`include "utils.svh" -`include "m_axi_sequencer.sv" - -`ifndef __ENVIRONMENT_SV__ -`define __ENVIRONMENT_SV__ - -import axi_vip_pkg::*; -import axi4stream_vip_pkg::*; -import `PKGIFY(`TH, `MNG_AXI)::*; - -class environment; - - // Agents - `AGENT(`TH, `MNG_AXI, mst_t) mng_agent; - // Sequencers - m_axi_sequencer #(`AGENT(`TH, `MNG_AXI, mst_t)) mng; - - // Register accessors - bit done = 0; - - - //============================================================================ - // Constructor - //============================================================================ - function new( - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(`TH, `MNG_AXI)) mng_vip_if - ); - - // Creating the agents - mng_agent = new("AXI Manager agent", mng_vip_if); - - // Creating the sequencers - mng = new(mng_agent); - - endfunction - - //============================================================================ - // Start environment - // - Connect all the agents to the scoreboard - // - Start the agents - //============================================================================ - task start(); - mng_agent.start_master(); - - endtask - - //============================================================================ - // Start the test - // - start the scoreboard - // - start the sequencers - //============================================================================ - task test(); - fork - - join_none - endtask - - //============================================================================ - // Post test subroutine - //============================================================================ - task post_test(); - // wait until done - wait_done(); - endtask - - //============================================================================ - // Run subroutine - //============================================================================ - task run; - test(); - post_test(); - endtask - - //============================================================================ - // Stop subroutine - //============================================================================ - task stop; - mng_agent.stop_master(); - endtask - - //============================================================================ - // Wait until all component are done - //============================================================================ - task wait_done; - wait (done == 1); - //`INFO(("Shutting down")); - endtask - - //============================================================================ - // Test controller routine - //============================================================================ - task test_c_run(); - done = 1; - endtask - - - -endclass - -`endif diff --git a/testbenches/ip/jesd_loopback_64b/tests/test_program.sv b/testbenches/ip/jesd_loopback_64b/tests/test_program.sv index 9e60d5ec..463a3bbe 100644 --- a/testbenches/ip/jesd_loopback_64b/tests/test_program.sv +++ b/testbenches/ip/jesd_loopback_64b/tests/test_program.sv @@ -68,7 +68,8 @@ program test_program; initial begin //creating environment - env = new(`TH.`SYS_CLK.inst.IF, + env = new("JESD Loopback 64b", + `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, `TH.`SYS_RST.inst.IF, @@ -77,7 +78,7 @@ program test_program; #2ps; - setLoggerVerbosity(6); + setLoggerVerbosity(ADI_VERBOSITY_NONE); env.start(); `TH.`SYS_CLK.inst.IF.start_clock; @@ -198,6 +199,12 @@ program test_program; // Read status back env.mng.RegReadVerify32(`AXI_JESD_RX_BA+GetAddrs(JESD_RX_LINK_STATUS), `SET_JESD_RX_LINK_STATUS_STATUS_STATE(3)); + + `INFO(("Test Done"), ADI_VERBOSITY_NONE); + + env.stop(); + $finish; + end endprogram diff --git a/testbenches/ip/scoreboard/environment.sv b/testbenches/ip/scoreboard/environment.sv index 57f88619..731e2ae9 100644 --- a/testbenches/ip/scoreboard/environment.sv +++ b/testbenches/ip/scoreboard/environment.sv @@ -73,6 +73,8 @@ package environment_pkg; // Constructor //============================================================================ function new ( + input string name, + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if, virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if, virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if, @@ -95,7 +97,8 @@ package environment_pkg; ); // creating the agents - super.new(sys_clk_vip_if, + super.new(name, + sys_clk_vip_if, dma_clk_vip_if, ddr_clk_vip_if, sys_rst_vip_if, @@ -112,30 +115,30 @@ package environment_pkg; // adc_dst_axi_pt_agent_1 = new("ADC Destination AXI Agent 1", adc_dst_axi_pt_vip_if_1); // dac_src_axi_pt_agent_1 = new("DAC Source AXI Agent 1", dac_src_axi_pt_vip_if_1); - adc_src_axis_seq_0 = new(adc_src_axis_agent_0); - dac_dst_axis_seq_0 = new(dac_dst_axis_agent_0); - adc_dst_axi_pt_seq_0 = new(adc_dst_axi_pt_agent_0); - dac_src_axi_pt_seq_0 = new(dac_src_axi_pt_agent_0); - - // adc_src_axis_seq_1 = new(adc_src_axis_agent_1); - // dac_dst_axis_seq_1 = new(dac_dst_axis_agent_1); - // adc_dst_axi_pt_seq_1 = new(adc_dst_axi_pt_agent_1); - // dac_src_axi_pt_seq_1 = new(dac_src_axi_pt_agent_1); - - adc_src_axis_0_mon = new("ADC Source AXIS 0 Transaction Monitor", adc_src_axis_agent_0); - dac_dst_axis_0_mon = new("DAC Destination AXIS 0 Transaction Monitor", dac_dst_axis_agent_0); - adc_dst_axi_pt_0_mon = new("ADC Destination AXI 0 Transaction Monitor", adc_dst_axi_pt_agent_0); - dac_src_axi_pt_0_mon = new("DAC Source AXI 0 Transaction Monitor", dac_src_axi_pt_agent_0); - - // adc_src_axis_1_mon = new("ADC Source AXIS 1 Transaction Monitor", adc_src_axis_agent_1); - // dac_dst_axis_1_mon = new("DAC Destination AXIS 1 Transaction Monitor", dac_dst_axis_agent_1); - // adc_dst_axi_pt_1_mon = new("ADC Destination AXI 1 Transaction Monitor", adc_dst_axi_pt_agent_1); - // dac_src_axi_pt_1_mon = new("DAC Source AXI 1 Transaction Monitor", dac_src_axi_pt_agent_1); - - scoreboard_tx0 = new("Data Offload Verification Environment TX 0 Scoreboard"); - scoreboard_rx0 = new("Data Offload Verification Environment RX 0 Scoreboard"); - // scoreboard_tx1 = new("Data Offload Verification Environment TX 1 Scoreboard"); - // scoreboard_rx1 = new("Data Offload Verification Environment RX 1 Scoreboard"); + adc_src_axis_seq_0 = new("ADC Source AXI Stream Sequencer 0", adc_src_axis_agent_0, this); + dac_dst_axis_seq_0 = new("DAC Destination AXI Stream Sequencer 0", dac_dst_axis_agent_0, this); + adc_dst_axi_pt_seq_0 = new("ADC Destination AXI Sequencer 0", adc_dst_axi_pt_agent_0, this); + dac_src_axi_pt_seq_0 = new("DAC Source AXI Sequencer 0", dac_src_axi_pt_agent_0, this); + + // adc_src_axis_seq_1 = new("ADC Source AXI Stream Sequencer 1", adc_src_axis_agent_1, this); + // dac_dst_axis_seq_1 = new("DAC Destination AXI Stream Sequencer 1", dac_dst_axis_agent_1, this); + // adc_dst_axi_pt_seq_1 = new("ADC Destination AXI Sequencer 1", adc_dst_axi_pt_agent_1, this); + // dac_src_axi_pt_seq_1 = new("DAC Source AXI Sequencer 1", dac_src_axi_pt_agent_1, this); + + adc_src_axis_0_mon = new("ADC Source AXIS 0 Transaction Monitor", adc_src_axis_agent_0, this); + dac_dst_axis_0_mon = new("DAC Destination AXIS 0 Transaction Monitor", dac_dst_axis_agent_0, this); + adc_dst_axi_pt_0_mon = new("ADC Destination AXI 0 Transaction Monitor", adc_dst_axi_pt_agent_0, this); + dac_src_axi_pt_0_mon = new("DAC Source AXI 0 Transaction Monitor", dac_src_axi_pt_agent_0, this); + + // adc_src_axis_1_mon = new("ADC Source AXIS 1 Transaction Monitor", adc_src_axis_agent_1, this); + // dac_dst_axis_1_mon = new("DAC Destination AXIS 1 Transaction Monitor", dac_dst_axis_agent_1, this); + // adc_dst_axi_pt_1_mon = new("ADC Destination AXI 1 Transaction Monitor", adc_dst_axi_pt_agent_1, this); + // dac_src_axi_pt_1_mon = new("DAC Source AXI 1 Transaction Monitor", dac_src_axi_pt_agent_1, this); + + scoreboard_tx0 = new("Data Offload TX 0 Scoreboard", this); + scoreboard_rx0 = new("Data Offload RX 0 Scoreboard", this); + // scoreboard_tx1 = new("Data Offload TX 1 Scoreboard", this); + // scoreboard_rx1 = new("Data Offload RX 1 Scoreboard", this); endfunction diff --git a/testbenches/ip/scoreboard/tests/test_program.sv b/testbenches/ip/scoreboard/tests/test_program.sv index b75ea956..d3069c37 100644 --- a/testbenches/ip/scoreboard/tests/test_program.sv +++ b/testbenches/ip/scoreboard/tests/test_program.sv @@ -64,7 +64,8 @@ program test_program; initial begin // create environment - env = new(`TH.`SYS_CLK.inst.IF, + env = new("Scoreboard Environment", + `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, `TH.`SYS_RST.inst.IF, @@ -98,7 +99,7 @@ program test_program; //========================================================================= - setLoggerVerbosity(250); + setLoggerVerbosity(ADI_VERBOSITY_NONE); env.start(); env.sys_reset(); @@ -106,30 +107,30 @@ program test_program; // configure environment sequencers env.configure(`ADC_TRANSFER_LENGTH); - `INFO(("Bring up IP from reset.")); + `INFO(("Bring up IP from reset."), ADI_VERBOSITY_LOW); systemBringUp(); //do_set_transfer_length(`ADC_TRANSFER_LENGTH); do_set_transfer_length(`ADC_TRANSFER_LENGTH/64); // Start the ADC/DAC stubs - `INFO(("Call the run() ...")); + `INFO(("Call the run() ..."), ADI_VERBOSITY_LOW); env.run(); env.adc_src_axis_seq_0.start(); // env.adc_src_axis_seq_1.start(); // Generate DMA transfers - `INFO(("Start RX DMA ...")); + `INFO(("Start RX DMA ..."), ADI_VERBOSITY_LOW); rx_dma_transfer(dmac_rx_0, 32'h80000000, `ADC_TRANSFER_LENGTH); // rx_dma_transfer(dmac_rx_1, 32'h80000000, `ADC_TRANSFER_LENGTH); env.scoreboard_rx0.wait_until_complete(); - `INFO(("Initialize the memory ...")); + `INFO(("Initialize the memory ..."), ADI_VERBOSITY_LOW); init_mem_64(32'h80000000, 1024); - `INFO(("Start TX DMA ...")); + `INFO(("Start TX DMA ..."), ADI_VERBOSITY_LOW); tx_dma_transfer(dmac_tx_0, 32'h80000000, 1024); // tx_dma_transfer(dmac_tx_1, 32'h80000000, 1024); @@ -138,7 +139,7 @@ program test_program; env.stop(); - `INFO(("Test bench done!")); + `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); $finish(); end @@ -147,14 +148,14 @@ program test_program; // bring up the Data Offload instances from reset - `INFO(("Bring up RX Data Offload 0")); + `INFO(("Bring up RX Data Offload 0"), ADI_VERBOSITY_LOW); do_rx_0.deassert_reset(); - `INFO(("Bring up TX Data Offload 0")); + `INFO(("Bring up TX Data Offload 0"), ADI_VERBOSITY_LOW); do_tx_0.deassert_reset(); - // `INFO(("Bring up RX Data Offload 1")); + // `INFO(("Bring up RX Data Offload 1"), ADI_VERBOSITY_LOW); // do_rx_1.deassert_reset(); - // `INFO(("Bring up TX Data Offload 1")); + // `INFO(("Bring up TX Data Offload 1"), ADI_VERBOSITY_LOW); // do_tx_1.deassert_reset(); // Enable tx oneshot mode @@ -164,14 +165,14 @@ program test_program; // bring up the DMAC instances from reset - `INFO(("Bring up RX DMAC 0")); + `INFO(("Bring up RX DMAC 0"), ADI_VERBOSITY_LOW); dmac_rx_0.enable_dma(); - `INFO(("Bring up TX DMAC 0")); + `INFO(("Bring up TX DMAC 0"), ADI_VERBOSITY_LOW); dmac_tx_0.enable_dma(); - // `INFO(("Bring up RX DMAC 1")); + // `INFO(("Bring up RX DMAC 1"), ADI_VERBOSITY_LOW); // dmac_rx_1.enable_dma(); - // `INFO(("Bring up TX DMAC 1")); + // `INFO(("Bring up TX DMAC 1"), ADI_VERBOSITY_LOW); // dmac_tx_1.enable_dma(); endtask @@ -208,11 +209,11 @@ program test_program; task init_mem_64( input longint unsigned addr, input int byte_length); - `INFO(("Initial address: %x", addr)); + `INFO(("Initial address: %x", addr), ADI_VERBOSITY_LOW); for (int i=0; i= tx_os_sysref_clk && `fmod(tx_sysref_clk, tx_os_sysref_clk) == 0) begin @@ -201,10 +202,10 @@ program test_program; end else if (tx_sysref_clk < tx_os_sysref_clk && `fmod(tx_os_sysref_clk, tx_sysref_clk) == 0) begin common_sysref_clk = tx_sysref_clk; end else begin - `ERROR(("TX_SYSREF_CLK and TX_OS_SYSREF_CLK are not divisible!\n TX_SYSREF_CLK: %f\n TX_OS_SYSREF_CLK: %f\n", tx_sysref_clk, tx_os_sysref_clk)); + `FATAL(("TX_SYSREF_CLK and TX_OS_SYSREF_CLK are not divisible!\n TX_SYSREF_CLK: %f\n TX_OS_SYSREF_CLK: %f\n", tx_sysref_clk, tx_os_sysref_clk)); end end else begin - `ERROR(("RX_SYSREF_CLK and TX_SYSREF_CLK are not divisible!\n RX_SYSREF_CLK: %f\n TX_SYSREF_CLK: %f\n", rx_sysref_clk, tx_sysref_clk)); + `FATAL(("RX_SYSREF_CLK and TX_SYSREF_CLK are not divisible!\n RX_SYSREF_CLK: %f\n TX_SYSREF_CLK: %f\n", rx_sysref_clk, tx_sysref_clk)); end `TH.`SYSREF_CLK.inst.IF.set_clk_frq(.user_frequency(common_sysref_clk)); @@ -238,9 +239,10 @@ program test_program; rx_tpl_test(.use_dds (0)); rx_os_tpl_test(.use_dds (0)); - `INFO(("=======================")); - `INFO((" JESD LINK TEST DONE ")); - `INFO(("=======================")); + env.stop(); + + `INFO(("Test Done"), ADI_VERBOSITY_NONE); + $finish; end @@ -488,7 +490,7 @@ program test_program; first = (first + 8'h01); end - `INFO(("Address 0x%h Expected 0x%h found 0x%h",current_address,reference_word,captured_word)); + `INFO(("Address 0x%h Expected 0x%h found 0x%h",current_address,reference_word,captured_word), ADI_VERBOSITY_LOW); if (i > 20 && captured_word !== reference_word) begin `ERROR(("Address 0x%h Expected 0x%h found 0x%h",current_address,reference_word,captured_word)); diff --git a/testbenches/project/fmcomms2/tests/test_program.sv b/testbenches/project/fmcomms2/tests/test_program.sv index 6f27308e..137b92b0 100644 --- a/testbenches/project/fmcomms2/tests/test_program.sv +++ b/testbenches/project/fmcomms2/tests/test_program.sv @@ -101,7 +101,8 @@ program test_program; initial begin //creating environment - env = new(`TH.`SYS_CLK.inst.IF, + env = new("FMCOMMS2 Environment", + `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, `TH.`SYS_RST.inst.IF, @@ -110,7 +111,7 @@ program test_program; #2ps; - setLoggerVerbosity(6); + setLoggerVerbosity(ADI_VERBOSITY_NONE); env.start(); //set source synchronous interface clock frequency @@ -135,7 +136,10 @@ program test_program; dma_test(); - `INFO(("Test Done")); + env.stop(); + + `INFO(("Test Done"), ADI_VERBOSITY_NONE); + $finish; end @@ -470,7 +474,7 @@ program test_program; if (captured_word !== reference_word) begin `ERROR(("Address 0x%h Expected 0x%h found 0x%h",current_address,reference_word,captured_word)); end else begin - `INFO(("Address 0x%h Expected 0x%h found 0x%h",current_address,reference_word,captured_word)); + `INFO(("Address 0x%h Expected 0x%h found 0x%h",current_address,reference_word,captured_word), ADI_VERBOSITY_LOW); end end end diff --git a/testbenches/project/mxfe/tests/test_program.sv b/testbenches/project/mxfe/tests/test_program.sv index 86e922fb..62866c42 100644 --- a/testbenches/project/mxfe/tests/test_program.sv +++ b/testbenches/project/mxfe/tests/test_program.sv @@ -69,7 +69,8 @@ program test_program; initial begin //creating environment - env = new(`TH.`SYS_CLK.inst.IF, + env = new("MXFE Environment", + `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, `TH.`SYS_RST.inst.IF, @@ -78,7 +79,7 @@ program test_program; #2ps; - setLoggerVerbosity(6); + setLoggerVerbosity(ADI_VERBOSITY_NONE); env.start(); link = new; @@ -149,9 +150,11 @@ program test_program; // ======================= jesd_link_test_ext_sync(0); - `INFO(("=======================")); - `INFO((" TB DONE ")); - `INFO(("=======================")); + env.stop(); + + `INFO(("Test Done"), ADI_VERBOSITY_NONE); + $finish; + end // ----------------- @@ -162,9 +165,9 @@ program test_program; input tx_bypass = 0, input tdd_enabled = 0); - `INFO(("=======================")); - `INFO((" JESD TEST "+(use_dds ? "DDS" : "DMA"))); - `INFO(("=======================")); + `INFO(("======================="), ADI_VERBOSITY_LOW); + `INFO((" JESD TEST "+(use_dds ? "DDS" : "DMA")), ADI_VERBOSITY_LOW); + `INFO(("======================="), ADI_VERBOSITY_LOW); // ----------------------- // TX PHY INIT @@ -333,9 +336,9 @@ program test_program; rx_xcvr.down(); tx_xcvr.down(); - `INFO(("=======================")); - `INFO((" JESD LINK TEST DONE ")); - `INFO(("=======================")); + `INFO(("======================="), ADI_VERBOSITY_LOW); + `INFO((" JESD LINK TEST DONE "), ADI_VERBOSITY_LOW); + `INFO(("======================="), ADI_VERBOSITY_LOW); endtask : jesd_link_test @@ -344,9 +347,9 @@ program test_program; // ----------------- task jesd_link_test_ext_sync(input use_dds = 1); - `INFO(("=======================")); - `INFO((" JESD TEST EXT SYNC "+(use_dds ? "DDS" : "DMA"))); - `INFO(("=======================")); + `INFO(("======================="), ADI_VERBOSITY_LOW); + `INFO((" JESD TEST EXT SYNC "+(use_dds ? "DDS" : "DMA")), ADI_VERBOSITY_LOW); + `INFO(("======================="), ADI_VERBOSITY_LOW); // ----------------------- // TX PHY INIT // ----------------------- @@ -489,9 +492,9 @@ program test_program; rx_xcvr.down(); tx_xcvr.down(); - `INFO(("=======================")); - `INFO((" JESD LINK TEST DONE ")); - `INFO(("=======================")); + `INFO(("======================="), ADI_VERBOSITY_LOW); + `INFO((" JESD LINK TEST DONE "), ADI_VERBOSITY_LOW); + `INFO(("======================="), ADI_VERBOSITY_LOW); endtask : jesd_link_test_ext_sync diff --git a/testbenches/project/pluto/tests/test_program.sv b/testbenches/project/pluto/tests/test_program.sv index 410f2f21..19414756 100644 --- a/testbenches/project/pluto/tests/test_program.sv +++ b/testbenches/project/pluto/tests/test_program.sv @@ -101,7 +101,8 @@ program test_program; initial begin // Creating environment - env = new(`TH.`SYS_CLK.inst.IF, + env = new("Pluto Environment", + `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, `TH.`SYS_RST.inst.IF, @@ -110,7 +111,7 @@ program test_program; #2ps; - setLoggerVerbosity(6); + setLoggerVerbosity(ADI_VERBOSITY_NONE); env.start(); // Set source synchronous interface clock frequency @@ -146,7 +147,10 @@ program test_program; tdd_test(); - `INFO(("Test Done")); + env.stop(); + + `INFO(("Test Done"), ADI_VERBOSITY_NONE); + $finish; end diff --git a/testbenches/project/pulsar_adc_pmdz/tests/test_program.sv b/testbenches/project/pulsar_adc_pmdz/tests/test_program.sv index c10f7cdf..d652b53c 100755 --- a/testbenches/project/pulsar_adc_pmdz/tests/test_program.sv +++ b/testbenches/project/pulsar_adc_pmdz/tests/test_program.sv @@ -133,14 +133,15 @@ endtask initial begin //creating environment - env = new(`TH.`SYS_CLK.inst.IF, + env = new("Pulsar Environment", + `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, `TH.`SYS_RST.inst.IF, `TH.`MNG_AXI.inst.IF, `TH.`DDR_AXI.inst.IF); - setLoggerVerbosity(6); + setLoggerVerbosity(ADI_VERBOSITY_NONE); env.start(); //asserts all the resets for 100 ns @@ -158,8 +159,10 @@ initial begin #100 offload_spi_test(); - `INFO(("Test Done")); + + env.stop(); + `INFO(("Test Done"), ADI_VERBOSITY_NONE); $finish; end @@ -175,7 +178,7 @@ task sanity_test; axi_read_v (`PULSAR_ADC_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_VERSION), pcore_version); axi_write (`PULSAR_ADC_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SCRATCH), 32'hDEADBEEF); axi_read_v (`PULSAR_ADC_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SCRATCH), 32'hDEADBEEF); - `INFO(("Sanity Test Done")); + `INFO(("Sanity Test Done"), ADI_VERBOSITY_LOW); endtask //--------------------------------------------------------------------------- @@ -193,7 +196,7 @@ task generate_transfer_cmd( axi_write (`PULSAR_ADC_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), INST_CS_OFF); // SYNC command to generate interrupt axi_write (`PULSAR_ADC_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (INST_SYNC | sync_id)); - $display("[%t] NOTE: Transfer generation finished.", $time); + `INFO(("Transfer generation finished"), ADI_VERBOSITY_LOW); endtask //--------------------------------------------------------------------------- @@ -211,24 +214,24 @@ initial begin // IRQ launched by Offload SYNC command if (irq_pending & 5'b10000) begin axi_read (`PULSAR_ADC_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SYNC_ID), sync_id); - $display("[%t] NOTE: Offload SYNC %d IRQ. An offload transfer just finished.", $time, sync_id); + `INFO(("Offload SYNC %d IRQ. An offload transfer just finished", sync_id), ADI_VERBOSITY_LOW); end // IRQ launched by SYNC command if (irq_pending & 5'b01000) begin axi_read (`PULSAR_ADC_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SYNC_ID), sync_id); - $display("[%t] NOTE: SYNC %d IRQ. FIFO transfer just finished.", $time, sync_id); + `INFO(("SYNC %d IRQ. FIFO transfer just finished", sync_id), ADI_VERBOSITY_LOW); end // IRQ launched by SDI FIFO if (irq_pending & 5'b00100) begin - $display("[%t] NOTE: SDI FIFO IRQ.", $time); + `INFO(("SDI FIFO IRQ"), ADI_VERBOSITY_LOW); end // IRQ launched by SDO FIFO if (irq_pending & 5'b00010) begin - $display("[%t] NOTE: SDO FIFO IRQ.", $time); + `INFO(("SDO FIFO IRQ"), ADI_VERBOSITY_LOW); end // IRQ launched by SDO FIFO if (irq_pending & 5'b00001) begin - $display("[%t] NOTE: CMD FIFO IRQ.", $time); + `INFO(("CMD FIFO IRQ"), ADI_VERBOSITY_LOW); end // Clear all pending IRQs axi_write (`PULSAR_ADC_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_IRQ_PENDING), irq_pending); @@ -427,14 +430,14 @@ task offload_spi_test(); // Start the offload #100 axi_write (`PULSAR_ADC_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_EN), `SET_AXI_SPI_ENGINE_OFFLOAD0_EN_OFFLOAD0_EN(1)); - $display("[%t] Offload started.", $time); + `INFO(("Offload started"), ADI_VERBOSITY_LOW); wait(offload_transfer_cnt == NUM_OF_TRANSFERS); axi_write (`PULSAR_ADC_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_EN), `SET_AXI_SPI_ENGINE_OFFLOAD0_EN_OFFLOAD0_EN(0)); offload_status = 0; - $display("[%t] Offload stopped.", $time); + `INFO(("Offload stopped"), ADI_VERBOSITY_LOW); #2000 @@ -444,15 +447,15 @@ task offload_spi_test(); end if (irq_pending == 'h0) begin - `ERROR(("IRQ Test FAILED")); + `FATAL(("IRQ Test FAILED")); end else begin - `INFO(("IRQ Test PASSED")); + `INFO(("IRQ Test PASSED"), ADI_VERBOSITY_LOW); end if (offload_captured_word_arr [(NUM_OF_TRANSFERS) - 1:2] != offload_sdi_data_store_arr [(NUM_OF_TRANSFERS) - 1:2]) begin `ERROR(("Offload Test FAILED")); end else begin - `INFO(("Offload Test PASSED")); + `INFO(("Offload Test PASSED"), ADI_VERBOSITY_LOW); end endtask @@ -473,7 +476,7 @@ task fifo_spi_test(); axi_write (`PULSAR_ADC_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_RESET(1)); // PWM_GEN reset in regmap (ACTIVE HIGH) axi_write (`PULSAR_ADC_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_PULSE_X_PERIOD), `SET_AXI_PWM_GEN_REG_PULSE_X_PERIOD_PULSE_X_PERIOD('d121)); // set PWM period axi_write (`PULSAR_ADC_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_LOAD_CONFIG(1)); // load AXI_PWM_GEN configuration - $display("[%t] axi_pwm_gen started.", $time); + `INFO(("Axi_pwm_gen started"), ADI_VERBOSITY_LOW); // Enable SPI Engine axi_write (`PULSAR_ADC_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_ENABLE), `SET_AXI_SPI_ENGINE_ENABLE_ENABLE(0)); @@ -505,12 +508,12 @@ task fifo_spi_test(); axi_read (`PULSAR_ADC_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SDI_FIFO_PEEK), sdi_fifo_data); end + `INFO(("sdi_fifo_data: %x; sdi_fifo_data_store %x", sdi_fifo_data, sdi_fifo_data_store), ADI_VERBOSITY_LOW); + if (sdi_fifo_data != sdi_fifo_data_store) begin - $display("sdi_fifo_data: %x; sdi_fifo_data_store %x", sdi_fifo_data, sdi_fifo_data_store); `ERROR(("Fifo Read Test FAILED")); end else begin - $display("sdi_fifo_data: %x; sdi_fifo_data_store %x", sdi_fifo_data, sdi_fifo_data_store); - `INFO(("Fifo Read Test PASSED")); + `INFO(("Fifo Read Test PASSED"), ADI_VERBOSITY_LOW); end endtask