diff --git a/docs/user_guide/architecture.rst b/docs/user_guide/architecture.rst
index 2fcb2348..d5cd24a1 100644
--- a/docs/user_guide/architecture.rst
+++ b/docs/user_guide/architecture.rst
@@ -8,17 +8,23 @@ File structure of a project
 
 .. tip::
 
-   In ``base/`` you can find a test bench base design.
+   In ``testbenches/ip/base/`` you can find a test bench base design.
 
 Project files for test benches
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 -  ``library`` --- common files that are used in many projects
 
-    -   ``adi_vip`` --- ADI VIPs
-    -   ``ips`` --- IPs
-    -   ``utilities`` --- ADI Utilities
-    -   ``xilinx_vip`` --- Xilinx VIPs
+    -  ``drivers`` --- drivers and APIs used for controlling IPs as well as VIPs;
+       these modules can use register map files, VIPs and other APIs
+    -  ``regmaps`` ---  register map files created for simulations based on the
+       HDL IP register maps along with a couple of utility files; these are macro
+       functions that are used to access a specific IP's register's field in a
+       given variable that is passed to these functions
+    -  ``utilities`` --- common scripts, modules and macros that are used for
+       testbench design and environment creation
+    -  ``vip`` --- ADI verification IPs (VIP) and additional auxiliary classes
+       which are vendor specific
 
 -  ``scripts`` --- used for creating and running the testbenches
 
diff --git a/docs/user_guide/introduction.rst b/docs/user_guide/introduction.rst
index 59f661d8..61174112 100644
--- a/docs/user_guide/introduction.rst
+++ b/docs/user_guide/introduction.rst
@@ -15,10 +15,10 @@ desired). Furthermore, all ADI developed and supported IPs are presented in deta
 At the same time, the user guides are not intended to be a guide for any third
 party tool. To understand and use the HDL framework efficiently the user needs
 to have a **solid understanding on how an FPGA works, to be familiar with all
-the design tools and flows, testbenches, SystemVerilog and classes**. These
-testbenches are not using UVM, however, some ideas are used from the
-verification standard, meaning that a high level overview of UVM can be useful
-in understanding the design structure.
+the design tools and flows, testbenches, SystemVerilog and object-oriented
+programming (OOP)**. These testbenches are not using UVM, however, some ideas
+are used from the verification standard, meaning that a high level overview
+of UVM can be useful in understanding the design structure.
 
 If somebody does not have this knowledge we highly recommend to make some
 general research and go through some basic tutorials with the targeted