From ee6a6d7a4a5bc5b699a7430596dbba67f71589c2 Mon Sep 17 00:00:00 2001 From: IstvanZsSzekely <122256380+IstvanZsSzekely@users.noreply.github.com> Date: Wed, 13 Nov 2024 11:58:15 +0200 Subject: [PATCH] ad7616: Updated FPGA part number (#134) - Using the 7-series Xilinx FPGA part, since the original Ultrascale+ part has different properties and requirements for the MMCM clock generation and the AD7616 project implementation is only available for Zedboard Signed-off-by: Istvan-Zsolt Szekely --- testbenches/project/ad7616/system_project.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbenches/project/ad7616/system_project.tcl b/testbenches/project/ad7616/system_project.tcl index b707397e..9b0c9019 100755 --- a/testbenches/project/ad7616/system_project.tcl +++ b/testbenches/project/ad7616/system_project.tcl @@ -36,7 +36,7 @@ if {[expr {![info exists use_smartconnect]}]} { } # Create the project -adi_sim_project_xilinx $project_name "xcvu9p-flga2104-2L-e" +adi_sim_project_xilinx $project_name "xc7z020clg484-1" # Add test files to the project adi_sim_project_files [list \