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Reformatted, using emacs buffer, dbReadVerilog.tcl. Signed-off-by: An…
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…dy Fox <[email protected]>

Signed-off-by: andyfox-rushc <[email protected]>
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andyfox-rushc committed Apr 24, 2024
1 parent 1fa10ef commit 6640645
Showing 1 changed file with 25 additions and 25 deletions.
50 changes: 25 additions & 25 deletions src/dbSta/src/dbReadVerilog.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -38,29 +38,29 @@
sta::define_cmd_args "read_verilog" {filename}

proc read_verilog { filename } {
ord::read_verilog_cmd [file nativename $filename]
ord::read_verilog_cmd [file nativename $filename]
}

sta::define_cmd_args "link_design" {[top_cell_name][hier]}
proc link_design { {top_cell_name ""} {hier ""}} {
variable current_design_name
variable current_design_name
if { $hier == "-hier" } {
set hierarchy true
} else {
set hierarchy false
}
if { $top_cell_name == "" } {
if { $current_design_name == "" } {
utl::error ORD 2009 "missing top_cell_name argument and no current_design."
return 0
} else {
set top_cell_name $current_design_name
if { $top_cell_name == "" } {
if { $current_design_name == "" } {
utl::error ORD 2009 "missing top_cell_name argument and no current_design."
return 0
} else {
set top_cell_name $current_design_name
}
}
if { ![ord::db_has_tech] } {
utl::error ORD 2010 "no technology has been read."
}
}
if { ![ord::db_has_tech] } {
utl::error ORD 2010 "no technology has been read."
}
ord::link_design_db_cmd $top_cell_name $hierarchy
ord::link_design_db_cmd $top_cell_name $hierarchy
}


Expand All @@ -69,21 +69,21 @@ proc link_design { {top_cell_name ""} {hier ""}} {


sta::define_cmd_args "write_verilog" {[-sort] [-include_pwr_gnd]\
[-remove_cells cells] filename}
[-remove_cells cells] filename}

# Copied from sta/verilog/Verilog.tcl because we don't want sta::read_verilog
# that is in the same file.
proc write_verilog { args } {
sta::parse_key_args "write_verilog" args keys {-remove_cells} \
flags {-sort -include_pwr_gnd}
sta::parse_key_args "write_verilog" args keys {-remove_cells} \
flags {-sort -include_pwr_gnd}

set remove_cells {}
if { [info exists keys(-remove_cells)] } {
set remove_cells [sta::parse_cell_arg $keys(-remove_cells)]
}
set sort [info exists flags(-sort)]
set include_pwr_gnd [info exists flags(-include_pwr_gnd)]
sta::check_argc_eq1 "write_verilog" $args
set filename [file nativename [lindex $args 0]]
sta::write_verilog_cmd $filename $sort $include_pwr_gnd $remove_cells
set remove_cells {}
if { [info exists keys(-remove_cells)] } {
set remove_cells [sta::parse_cell_arg $keys(-remove_cells)]
}
set sort [info exists flags(-sort)]
set include_pwr_gnd [info exists flags(-include_pwr_gnd)]
sta::check_argc_eq1 "write_verilog" $args
set filename [file nativename [lindex $args 0]]
sta::write_verilog_cmd $filename $sort $include_pwr_gnd $remove_cells
}

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