From 66406455fa2a95351b7044fc9dcadd7693e4c4e5 Mon Sep 17 00:00:00 2001
From: andyfox-rushc <andy@rushc.com>
Date: Wed, 24 Apr 2024 08:40:45 -0700
Subject: [PATCH] Reformatted, using emacs buffer, dbReadVerilog.tcl.
 Signed-off-by: Andy Fox <andy@rushc.com>

Signed-off-by: andyfox-rushc <andy@rushc.com>
---
 src/dbSta/src/dbReadVerilog.tcl | 50 ++++++++++++++++-----------------
 1 file changed, 25 insertions(+), 25 deletions(-)

diff --git a/src/dbSta/src/dbReadVerilog.tcl b/src/dbSta/src/dbReadVerilog.tcl
index 7ff97ea63d7..7774b587b41 100644
--- a/src/dbSta/src/dbReadVerilog.tcl
+++ b/src/dbSta/src/dbReadVerilog.tcl
@@ -38,29 +38,29 @@
 sta::define_cmd_args "read_verilog" {filename}
 
 proc read_verilog { filename } {
-  ord::read_verilog_cmd [file nativename $filename]
+    ord::read_verilog_cmd [file nativename $filename]
 }
 
 sta::define_cmd_args "link_design" {[top_cell_name][hier]}
 proc link_design { {top_cell_name ""} {hier ""}} {
-  variable current_design_name
+    variable current_design_name
     if { $hier == "-hier" } {
 	set hierarchy true
     } else {
 	set hierarchy false
     }
-  if { $top_cell_name == "" } {
-    if { $current_design_name == "" } {
-      utl::error ORD 2009 "missing top_cell_name argument and no current_design."
-      return 0
-    } else {
-      set top_cell_name $current_design_name
+    if { $top_cell_name == "" } {
+	if { $current_design_name == "" } {
+	    utl::error ORD 2009 "missing top_cell_name argument and no current_design."
+	    return 0
+	} else {
+	    set top_cell_name $current_design_name
+	}
+    }
+    if { ![ord::db_has_tech] } {
+	utl::error ORD 2010 "no technology has been read."
     }
-  }
-  if { ![ord::db_has_tech] } {
-    utl::error ORD 2010 "no technology has been read."
-  }
-  ord::link_design_db_cmd $top_cell_name $hierarchy
+    ord::link_design_db_cmd $top_cell_name $hierarchy
 }
 
 
@@ -69,21 +69,21 @@ proc link_design { {top_cell_name ""} {hier ""}} {
 
 
 sta::define_cmd_args "write_verilog" {[-sort] [-include_pwr_gnd]\
-                                        [-remove_cells cells] filename}
+					  [-remove_cells cells] filename}
 
 # Copied from sta/verilog/Verilog.tcl because we don't want sta::read_verilog
 # that is in the same file.
 proc write_verilog { args } {
-  sta::parse_key_args "write_verilog" args keys {-remove_cells} \
-    flags {-sort -include_pwr_gnd}
+    sta::parse_key_args "write_verilog" args keys {-remove_cells} \
+	flags {-sort -include_pwr_gnd}
 
-  set remove_cells {}
-  if { [info exists keys(-remove_cells)] } {
-    set remove_cells [sta::parse_cell_arg $keys(-remove_cells)]
-  }
-  set sort [info exists flags(-sort)]
-  set include_pwr_gnd [info exists flags(-include_pwr_gnd)]
-  sta::check_argc_eq1 "write_verilog" $args
-  set filename [file nativename [lindex $args 0]]
-  sta::write_verilog_cmd $filename $sort $include_pwr_gnd $remove_cells
+    set remove_cells {}
+    if { [info exists keys(-remove_cells)] } {
+	set remove_cells [sta::parse_cell_arg $keys(-remove_cells)]
+    }
+    set sort [info exists flags(-sort)]
+    set include_pwr_gnd [info exists flags(-include_pwr_gnd)]
+    sta::check_argc_eq1 "write_verilog" $args
+    set filename [file nativename [lindex $args 0]]
+    sta::write_verilog_cmd $filename $sort $include_pwr_gnd $remove_cells
 }