diff --git a/src/cts/README.md b/src/cts/README.md index 4784a4d67fb..26530355dbc 100644 --- a/src/cts/README.md +++ b/src/cts/README.md @@ -52,6 +52,9 @@ clock_tree_synthesis [-num_static_layers] [-sink_clustering_buffer] [-use_dummy_load] + [-insertion_delay] + [-sink_buffer_max_cap_derate derate_value] + [-delay_buffer_derate derate_value] ``` #### Options @@ -75,8 +78,10 @@ clock_tree_synthesis | `-sink_clustering_buffer` | Set the sink clustering buffer(s) to be used. | | `-obstruction_aware` | Enables obstruction-aware buffering such that clock buffers are not placed on top of blockages or hard macros. This option may reduce legalizer displacement, leading to better latency, skew or timing QoR. The default value is `False`, and the allowed values are bool. | | `-apply_ndr` | Applies 2X spacing non-default rule to all clock nets except leaf-level nets. The default value is `False`. | -| `-insertion_delay` | Considers insertion delays in macro timing models to improve clustering. The default value is `False`. | +| `-insertion_delay` | Considers insertion delays in macro timing models in balancing latencies between macro cells and registers. This option causes construction of separate clock trees for macro cells and registers. The default value is `False`. | | `-use_dummy_load` | Applies dummy buffer or inverter cells at clock tree leaves to balance loads. The default values is `False`. | +| `-sink_buffer_max_cap_derate` | Use this option to control automatic buffer selection. To favor strong(weak) drive strength buffers use a small(large) value. The default value is `0.01`, meaning that buffers are selected by derating max cap limit by 0.01. The value of 1.0 means no derating of max cap limit. | +| `-delay_buffer_derate` | This option is used with -insertion_delay option that balances latencies between macro cells and registers by inserting delay buffers. The default values is `1.0`, meaning all needed delay buffers are inserted. Value of 0.5 means only half of necessary delay buffers are inserted. Value of 0.0 means no insertion of delay buffers. | ### Report CTS diff --git a/src/cts/include/cts/TritonCTS.h b/src/cts/include/cts/TritonCTS.h index a5db901e82b..21de9958136 100644 --- a/src/cts/include/cts/TritonCTS.h +++ b/src/cts/include/cts/TritonCTS.h @@ -54,6 +54,7 @@ class dbNet; class dbITerm; class dbMTerm; class Rect; +class dbMaster; } // namespace odb namespace rsz { @@ -83,6 +84,7 @@ class StaEngine; class TreeBuilder; class Clock; class ClockSubNet; +class HTreeBuilder; class TritonCTS { @@ -143,6 +145,28 @@ class TritonCTS void disconnectAllPinsFromNet(odb::dbNet* net); void checkUpstreamConnections(odb::dbNet* net); void createClockBuffers(Clock& clockNet); + HTreeBuilder* initClockTreeForMacrosAndRegs( + odb::dbNet*& net, + const std::unordered_set& buffer_masters, + Clock& ClockNet, + TreeBuilder* parentBuilder); + bool separateMacroRegSinks( + odb::dbNet*& net, + Clock& clockNet, + const std::unordered_set& buffer_masters, + std::vector>& registerSinks, + std::vector>& macroSinks); + HTreeBuilder* addClockSinks( + Clock& clockNet, + odb::dbNet* physicalNet, + const std::vector>& sinks, + HTreeBuilder* parentBuilder, + const std::string& macrosOrRegs); + Clock forkRegisterClockNetwork( + Clock& clockNet, + const std::vector>& registerSinks, + odb::dbNet*& firstNet, + odb::dbNet*& secondNet); void computeITermPosition(odb::dbITerm* term, int& x, int& y) const; void countSinksPostDbWrite(TreeBuilder* builder, odb::dbNet* net, @@ -164,6 +188,7 @@ class TritonCTS float getInputPinCap(odb::dbITerm* iterm); bool isSink(odb::dbITerm* iterm); ClockInst* getClockFromInst(odb::dbInst* inst); + bool hasInsertionDelay(odb::dbInst* inst, odb::dbMTerm* mterm); double computeInsertionDelay(const std::string& name, odb::dbInst* inst, odb::dbMTerm* mterm); @@ -182,6 +207,15 @@ class TritonCTS ClockSubNet& subNet, ClockInst& dummyClock); void printClockNetwork(const Clock& clockNet) const; + void balanceMacroRegisterLatencies(); + void computeAveSinkArrivals(TreeBuilder* builder); + void adjustLatencies(TreeBuilder* macroBuilder, TreeBuilder* registerBuilder); + void computeTopBufferDelay(TreeBuilder* builder); + odb::dbInst* insertDelayBuffer(odb::dbInst* driver, + int index, + const std::string& clockName, + int locX, + int locY); sta::dbSta* openSta_; sta::dbNetwork* network_; diff --git a/src/cts/src/Clock.h b/src/cts/src/Clock.h index 5d1b51d747a..6f495b95569 100644 --- a/src/cts/src/Clock.h +++ b/src/cts/src/Clock.h @@ -243,6 +243,7 @@ class Clock } std::string getName() const { return netName_; } + std::string getSdcName() const { return sdcClockName_; } unsigned getNumSinks() const { return sinks_.size(); } Box computeSinkRegion(); diff --git a/src/cts/src/CtsOptions.h b/src/cts/src/CtsOptions.h index 67634f31677..c200edebac2 100644 --- a/src/cts/src/CtsOptions.h +++ b/src/cts/src/CtsOptions.h @@ -242,6 +242,8 @@ class CtsOptions { return sinkBufferMaxCapDerateSet_; } + void setDelayBufferDerate(float derate) { delayBufferDerate_ = derate; } + float getDelayBufferDerate() const { return delayBufferDerate_; } void enableDummyLoad(bool dummyLoad) { dummyLoad_ = dummyLoad; } bool dummyLoadEnabled() const { return dummyLoad_; } @@ -300,6 +302,7 @@ class CtsOptions float sinkBufferMaxCapDerateDefault_ = 0.01; float sinkBufferMaxCapDerate_ = sinkBufferMaxCapDerateDefault_; bool dummyLoad_ = false; + float delayBufferDerate_ = 1.0; // no derate }; } // namespace cts diff --git a/src/cts/src/TreeBuilder.h b/src/cts/src/TreeBuilder.h index e7db25afd1d..a93077225fe 100644 --- a/src/cts/src/TreeBuilder.h +++ b/src/cts/src/TreeBuilder.h @@ -73,6 +73,13 @@ struct pointEqual } }; +enum TreeType +{ + regularTree = 0, // regular tree that drives both macros and registers + macroTree = 1, // parent tree that drives only macro cells with ins delays + registerTree = 2 // child tree that drives only registers without ins delays +}; + class TreeBuilder { public: @@ -219,6 +226,14 @@ class TreeBuilder return x.computeDist(y) + getSinkInsertionDelay(x) + getSinkInsertionDelay(y); } + TreeType getTreeType() const { return type_; } + void setTreeType(TreeType type) { type_ = type; } + float getAveSinkArrival() const { return aveArrival_; } + void setAveSinkArrival(float arrival) { aveArrival_ = arrival; } + float getTopBufferDelay() const { return topBufferDelay_; } + void setTopBufferDelay(float delay) { topBufferDelay_ = delay; } + odb::dbInst* getTopBuffer() const { return topBuffer_; } + void setTopBuffer(odb::dbInst* inst) { topBuffer_ = inst; } protected: CtsOptions* options_ = nullptr; @@ -244,6 +259,10 @@ class TreeBuilder // keep track of insertion delays at sink pins boost::unordered_map, double, pointHash, pointEqual> insertionDelays_; + TreeType type_ = regularTree; + float aveArrival_ = 0.0; + float topBufferDelay_ = 0.0; + odb::dbInst* topBuffer_ = nullptr; }; } // namespace cts diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 9789f053e3e..9688e983516 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -100,6 +100,7 @@ void TritonCTS::runTritonCts() checkCharacterization(); buildClockTrees(); writeDataToDb(); + balanceMacroRegisterLatencies(); } } @@ -170,7 +171,10 @@ void TritonCTS::buildClockTrees() if (options_->getBalanceLevels()) { for (TreeBuilder* builder : *builders_) { - if (!builder->getParent() && !builder->getChildren().empty()) { + if (!builder->getParent() + && !builder->getChildren().empty() + // don't balance levels for macro cell tree + && builder->getTreeType() != macroTree) { LevelBalancer balancer( builder, options_, logger_, techChar_->getLengthUnit()); balancer.run(); @@ -190,6 +194,9 @@ void TritonCTS::initOneClockTree(odb::dbNet* driverNet, } else { clockBuilder = initClock(driverNet, sdcClockName, parent); } + // Treat gated clocks as separate clock trees + // TODO: include sinks from gated clocks together with other sinks and build + // one clock tree visitedClockNets_.insert(driverNet); odb::dbITerm* driver = driverNet->getFirstOutput(); odb::dbSet iterms = driverNet->getITerms(); @@ -825,22 +832,22 @@ void TritonCTS::populateTritonCTS() options_->setNumClockRoots(getNumClocks()); } -TreeBuilder* TritonCTS::initClock(odb::dbNet* net, +TreeBuilder* TritonCTS::initClock(odb::dbNet* firstNet, const std::string& sdcClock, TreeBuilder* parentBuilder) { std::string driver; - odb::dbITerm* iterm = net->getFirstOutput(); + odb::dbITerm* iterm = firstNet->getFirstOutput(); int xPin, yPin; if (iterm == nullptr) { - odb::dbBTerm* bterm = net->get1stBTerm(); // Clock pin + odb::dbBTerm* bterm = firstNet->get1stBTerm(); // Clock pin if (bterm == nullptr) { logger_->info( CTS, 122, "Clock net \"{}\" is skipped for CTS because it is not " "connected to any output instance pin or input block terminal.", - net->getName()); + firstNet->getName()); return nullptr; } driver = bterm->getConstName(); @@ -857,7 +864,7 @@ TreeBuilder* TritonCTS::initClock(odb::dbNet* net, } // Initialize clock net - Clock clockNet(net->getConstName(), driver, sdcClock, xPin, yPin); + Clock clockNet(firstNet->getConstName(), driver, sdcClock, xPin, yPin); clockNet.setDriverPin(iterm); // Build a set of all the clock buffers' masters @@ -878,6 +885,122 @@ TreeBuilder* TritonCTS::initClock(odb::dbNet* net, } } + // Build a clock tree to drive macro cells with insertion delays + // separated from registers or leaves without insertion delays + HTreeBuilder* builder = initClockTreeForMacrosAndRegs( + firstNet, buffer_masters, clockNet, parentBuilder); + return builder; +} + +// Build a separate clock tree to pull macro cells with insertion delays +// ahead of cells without insertion delays. If sinks consist of +// both macros and FFs, clock tree for macros is built first. A new net and a +// new buffer are created to drive cells without insertion delays. New +// buffer will be sized later based on macro cell insertion delays. +// +// |----|>----[] cells with insertion delays +// firstNet | +// | |----|>----[] +// v | +// [root]-------| |---|>----[] cells without insertion +// | +// |----|>------------| +// ^ ^ | +// | | | +// new buffer secondNet|---|>----[] +// +HTreeBuilder* TritonCTS::initClockTreeForMacrosAndRegs( + odb::dbNet*& firstNet, + const std::unordered_set& buffer_masters, + Clock& clockNet, + TreeBuilder* parentBuilder) +{ + // Separate sinks into two buckets: one with insertion delays and another + // without + std::vector> macroSinks; + std::vector> registerSinks; + if (!separateMacroRegSinks( + firstNet, clockNet, buffer_masters, registerSinks, macroSinks)) { + return nullptr; + } + + if (!options_->insertionDelayEnabled() || macroSinks.empty() + || registerSinks.empty()) { + // There is no need for separate clock trees + for (odb::dbITerm* iterm : firstNet->getITerms()) { + odb::dbInst* inst = iterm->getInst(); + if (iterm->isInputSignal() && inst->isPlaced()) { + odb::dbMTerm* mterm = iterm->getMTerm(); + std::string name = std::string(inst->getConstName()) + "/" + + std::string(mterm->getConstName()); + int x, y; + computeITermPosition(iterm, x, y); + float insDelay = computeInsertionDelay(name, inst, mterm); + clockNet.addSink(name, x, y, iterm, getInputPinCap(iterm), insDelay); + } + } + if (clockNet.getNumSinks() < 2) { + logger_->warn(CTS, + 41, + "Net \"{}\" has {} sinks. Skipping...", + clockNet.getName(), + clockNet.getNumSinks()); + return nullptr; + } + logger_->info(CTS, + 10, + " Clock net \"{}\" has {} sinks.", + firstNet->getConstName(), + clockNet.getNumSinks()); + int totalSinks = options_->getNumSinks() + clockNet.getNumSinks(); + options_->setNumSinks(totalSinks); + incrementNumClocks(); + clockNet.setNetObj(firstNet); + HTreeBuilder* builder + = new HTreeBuilder(options_, clockNet, parentBuilder, logger_, db_); + addBuilder(builder); + return builder; + } + + // add macro sinks to existing firstNet + HTreeBuilder* firstBuilder + = addClockSinks(clockNet, + firstNet, + macroSinks, + dynamic_cast(parentBuilder), + "macros"); + if (firstBuilder) { + firstBuilder->setTreeType(macroTree); + } + + // create a new net 'secondNet' to drive register sinks + odb::dbNet* secondNet; + Clock clockNet2 + = forkRegisterClockNetwork(clockNet, registerSinks, firstNet, secondNet); + + // add register sinks to secondNet + HTreeBuilder* secondBuilder = addClockSinks( + clockNet2, + secondNet, + registerSinks, + firstBuilder ? firstBuilder : dynamic_cast(parentBuilder), + "registers"); + if (secondBuilder) { + secondBuilder->setTreeType(registerTree); + } + + return secondBuilder; +} + +// Separate sinks into registers (no insertion delay) and macros (insertion +// delay) +bool TritonCTS::separateMacroRegSinks( + odb::dbNet*& net, + Clock& clockNet, + const std::unordered_set& buffer_masters, + std::vector>& registerSinks, + std::vector>& macroSinks) +{ for (odb::dbITerm* iterm : net->getITerms()) { odb::dbInst* inst = iterm->getInst(); @@ -887,47 +1010,111 @@ TreeBuilder* TritonCTS::initClock(odb::dbNet* net, "Net \"{}\" already has clock buffer {}. Skipping...", clockNet.getName(), inst->getName()); - return nullptr; + return false; } if (iterm->isInputSignal() && inst->isPlaced()) { odb::dbMTerm* mterm = iterm->getMTerm(); - std::string name = std::string(inst->getConstName()) + "/" - + std::string(mterm->getConstName()); - int x, y; - computeITermPosition(iterm, x, y); - float insDelay = computeInsertionDelay(name, inst, mterm); - clockNet.addSink(name, x, y, iterm, getInputPinCap(iterm), insDelay); + if (hasInsertionDelay(inst, mterm)) { + macroSinks.emplace_back(inst, mterm); + } else { + registerSinks.emplace_back(inst, mterm); + } } } + return true; +} +HTreeBuilder* TritonCTS::addClockSinks( + Clock& clockNet, + odb::dbNet* physicalNet, + const std::vector>& sinks, + HTreeBuilder* parentBuilder, + const std::string& macrosOrRegs) +{ + for (auto elem : sinks) { + odb::dbInst* inst = elem.first; + odb::dbMTerm* mterm = elem.second; + std::string name = std::string(inst->getConstName()) + "/" + + std::string(mterm->getConstName()); + int x, y; + odb::dbITerm* iterm = inst->getITerm(mterm); + computeITermPosition(iterm, x, y); + float insDelay = computeInsertionDelay(name, inst, mterm); + clockNet.addSink(name, x, y, iterm, getInputPinCap(iterm), insDelay); + } if (clockNet.getNumSinks() < 2) { - logger_->warn(CTS, - 41, - "Net \"{}\" has {} sinks. Skipping...", + logger_->info(CTS, + 42, + " Clock net \"{}\" for {} has {} sinks. Skipping...", clockNet.getName(), + macrosOrRegs, clockNet.getNumSinks()); return nullptr; } - logger_->info(CTS, - 10, - " Clock net \"{}\" has {} sinks.", - net->getConstName(), + 11, + " Clock net \"{}\" for {} has {} sinks.", + physicalNet->getConstName(), + macrosOrRegs, clockNet.getNumSinks()); - int totalSinks = options_->getNumSinks() + clockNet.getNumSinks(); options_->setNumSinks(totalSinks); - incrementNumClocks(); - - clockNet.setNetObj(net); + clockNet.setNetObj(physicalNet); HTreeBuilder* builder = new HTreeBuilder(options_, clockNet, parentBuilder, logger_, db_); addBuilder(builder); return builder; } +Clock TritonCTS::forkRegisterClockNetwork( + Clock& clockNet, + const std::vector>& registerSinks, + odb::dbNet*& firstNet, + odb::dbNet*& secondNet) +{ + // create a new clock net to drive register sinks + std::string newClockName = clockNet.getName() + "_" + "regs"; + secondNet = odb::dbNet::create(block_, newClockName.c_str()); + secondNet->setSigType(odb::dbSigType::CLOCK); + + // move register sinks from previous clock net to new clock net + for (auto elem : registerSinks) { + odb::dbInst* inst = elem.first; + odb::dbMTerm* mterm = elem.second; + odb::dbITerm* iterm = inst->getITerm(mterm); + iterm->disconnect(); + iterm->connect(secondNet); + } + + // create a new clock buffer + odb::dbMaster* master = db_->findMaster(options_->getRootBuffer().c_str()); + std::string cellName = "clkbuf_regs_0_" + clockNet.getSdcName(); + odb::dbInst* clockBuf = odb::dbInst::create(block_, master, cellName.c_str()); + odb::dbITerm* inputTerm = getFirstInput(clockBuf); + odb::dbITerm* outputTerm = clockBuf->getFirstOutput(); + inputTerm->connect(firstNet); + outputTerm->connect(secondNet); + + // place new clock buffer near center of mass for registers + odb::Rect bbox = secondNet->getTermBBox(); + clockBuf->setSourceType(odb::dbSourceType::TIMING); + clockBuf->setLocation(bbox.xCenter(), bbox.yCenter()); + clockBuf->setPlacementStatus(odb::dbPlacementStatus::PLACED); + + // initialize new clock net + std::string driver = std::string(clockBuf->getConstName()) + "/" + + std::string(outputTerm->getMTerm()->getConstName()); + int xPin, yPin; + computeITermPosition(outputTerm, xPin, yPin); + Clock clockNet2( + secondNet->getConstName(), driver, clockNet.getSdcName(), xPin, yPin); + clockNet2.setDriverPin(outputTerm); + + return clockNet2; +} + void TritonCTS::computeITermPosition(odb::dbITerm* term, int& x, int& y) const { odb::dbITermShapeItr itr; @@ -956,6 +1143,14 @@ void TritonCTS::writeClockNetsToDb(Clock& clockNet, disconnectAllSinksFromNet(topClockNet); + // re-connect top buffer that separates macros from registers + std::string topRegBufferName = "clkbuf_regs_0_" + clockNet.getName(); + odb::dbInst* topRegBuffer = block_->findInst(topRegBufferName.c_str()); + if (topRegBuffer) { + odb::dbITerm* topRegBufferInputPin = getFirstInput(topRegBuffer); + topRegBufferInputPin->connect(topClockNet); + } + createClockBuffers(clockNet); // connect top buffer on the clock pin @@ -1323,47 +1518,71 @@ bool TritonCTS::isSink(odb::dbITerm* iterm) return false; } +bool TritonCTS::hasInsertionDelay(odb::dbInst* inst, odb::dbMTerm* mterm) +{ + if (options_->insertionDelayEnabled()) { + sta::LibertyCell* libCell = network_->libertyCell(network_->dbToSta(inst)); + if (libCell) { + sta::LibertyPort* libPort + = libCell->findLibertyPort(mterm->getConstName()); + if (libPort) { + sta::RiseFallMinMax insDelays = libPort->clockTreePathDelays(); + if (insDelays.hasValue()) { + return true; + } + } + } + } + return false; +} + double TritonCTS::computeInsertionDelay(const std::string& name, odb::dbInst* inst, odb::dbMTerm* mterm) { double insDelayPerMicron = 0.0; - if (options_->insertionDelayEnabled()) { - sta::LibertyCell* libCell = network_->libertyCell(network_->dbToSta(inst)); + if (!options_->insertionDelayEnabled()) { + return insDelayPerMicron; + } + + sta::LibertyCell* libCell = network_->libertyCell(network_->dbToSta(inst)); + if (libCell) { sta::LibertyPort* libPort = libCell->findLibertyPort(mterm->getConstName()); - sta::RiseFallMinMax insDelays = libPort->clockTreePathDelays(); - if (insDelays.hasValue()) { - // use average of max rise and max fall - // TODO: do we need to look at min insertion delays? - double delayPerSec - = (insDelays.value(sta::RiseFall::rise(), sta::MinMax::max()) - + insDelays.value(sta::RiseFall::fall(), sta::MinMax::max())) - / 2.0; - // convert delay to length because HTree uses lengths - sta::Corner* corner = openSta_->cmdCorner(); - double capPerMicron = resizer_->wireSignalCapacitance(corner) * 1e-6; - double resPerMicron = resizer_->wireSignalResistance(corner) * 1e-6; - if (sta::fuzzyEqual(capPerMicron, 1e-18) - || sta::fuzzyEqual(resPerMicron, 1e-18)) { - logger_->warn(CTS, - 203, - "Insertion delay cannot be used because unit " - "capacitance or unit resistance is zero. Check " - "layer RC settings."); - return 0.0; + if (libPort) { + sta::RiseFallMinMax insDelays = libPort->clockTreePathDelays(); + if (insDelays.hasValue()) { + // use average of max rise and max fall + // TODO: do we need to look at min insertion delays? + double delayPerSec + = (insDelays.value(sta::RiseFall::rise(), sta::MinMax::max()) + + insDelays.value(sta::RiseFall::fall(), sta::MinMax::max())) + / 2.0; + // convert delay to length because HTree uses lengths + sta::Corner* corner = openSta_->cmdCorner(); + double capPerMicron = resizer_->wireSignalCapacitance(corner) * 1e-6; + double resPerMicron = resizer_->wireSignalResistance(corner) * 1e-6; + if (sta::fuzzyEqual(capPerMicron, 1e-18) + || sta::fuzzyEqual(resPerMicron, 1e-18)) { + logger_->warn(CTS, + 203, + "Insertion delay cannot be used because unit " + "capacitance or unit resistance is zero. Check " + "layer RC settings."); + return 0.0; + } + insDelayPerMicron = delayPerSec / (capPerMicron * resPerMicron); + // clang-format off + debugPrint(logger_, CTS, "clustering", 1, "sink {} has ins " + "delay={:.2e} and micron leng={:0.1f} dbUnits/um={}", + name, delayPerSec, insDelayPerMicron, + block_->getDbUnitsPerMicron()); + debugPrint(logger_, CTS, "clustering", 1, "capPerMicron={:.2e} " + "resPerMicron={:.2e}", capPerMicron, resPerMicron); + // clang-format on } - insDelayPerMicron = delayPerSec / (capPerMicron * resPerMicron); - // clang-format off - debugPrint(logger_, CTS, "clustering", 1, "sink {} has ins delay={:.2e} and " - "micron leng={:0.1f} dbUnits/um={}", name, delayPerSec, - insDelayPerMicron, block_->getDbUnitsPerMicron()); - debugPrint(logger_, CTS, "clustering", 1, "capPerMicron={:.2e} resPerMicron={:.2e}", - capPerMicron, resPerMicron); - // clang-format on } } - return insDelayPerMicron; } @@ -1652,4 +1871,224 @@ void TritonCTS::printClockNetwork(const Clock& clockNet) const }); } +// Balance macro cell latencies with register latencies. +// This is needed only if special insertion delay handling +// is invoked. +void TritonCTS::balanceMacroRegisterLatencies() +{ + if (!options_->insertionDelayEnabled()) { + return; + } + + for (TreeBuilder* registerBuilder : *builders_) { + if (registerBuilder->getTreeType() == registerTree) { + TreeBuilder* macroBuilder = registerBuilder->getParent(); + if (macroBuilder) { + computeAveSinkArrivals(registerBuilder); + computeAveSinkArrivals(macroBuilder); + adjustLatencies(macroBuilder, registerBuilder); + } + } + } +} + +void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder) +{ + Clock clock = builder->getClock(); + // compute average input arrival at all sinks + float arrival = 0.0; + float ins_delay = 0.0; + clock.forEachSink([&](const ClockInst& sink) { + odb::dbITerm* iterm = sink.getDbInputPin(); + odb::dbInst* inst = iterm->getInst(); + sta::Pin* pin = network_->dbToSta(iterm); + // ignore arrival fall (no inverters in current clock tree) + arrival + += openSta_->pinArrival(pin, sta::RiseFall::rise(), sta::MinMax::max()); + // add insertion delay + ins_delay = 0.0; + sta::LibertyCell* libCell = network_->libertyCell(network_->dbToSta(inst)); + odb::dbMTerm* mterm = iterm->getMTerm(); + if (libCell && mterm) { + sta::LibertyPort* libPort + = libCell->findLibertyPort(mterm->getConstName()); + if (libPort) { + sta::RiseFallMinMax insDelays = libPort->clockTreePathDelays(); + if (insDelays.hasValue()) { + ins_delay + = (insDelays.value(sta::RiseFall::rise(), sta::MinMax::max()) + + insDelays.value(sta::RiseFall::fall(), sta::MinMax::max())) + / 2.0; + } + } + } + arrival += ins_delay; + }); + arrival = arrival / (float) clock.getNumSinks(); + builder->setAveSinkArrival(arrival); + debugPrint( + logger_, + CTS, + "insertion delay", + 1, + "{} {}: average sink arrival is {:0.3e}", + (builder->getTreeType() == macroTree) ? "macro tree" : "register tree", + clock.getName(), + builder->getAveSinkArrival()); +} + +// Balance latencies between macro tree and register tree +// by adding delay buffers to one tree +void TritonCTS::adjustLatencies(TreeBuilder* macroBuilder, + TreeBuilder* registerBuilder) +{ + // compute top buffer delays + computeTopBufferDelay(registerBuilder); + computeTopBufferDelay(macroBuilder); + + float latencyDiff = macroBuilder->getAveSinkArrival() + - registerBuilder->getAveSinkArrival(); + int numBuffers = 0; + TreeBuilder* builder = nullptr; + if (latencyDiff > 0) { + // add buffers to register tree + numBuffers = (int) (latencyDiff / registerBuilder->getTopBufferDelay()); + builder = registerBuilder; + } else { + // add buffers to macro tree (not common but why not?) + numBuffers + = (int) (std::abs(latencyDiff) / macroBuilder->getTopBufferDelay()); + builder = macroBuilder; + } + + // We don't want to add more delay buffers than needed because + // wire delays are not considered. The fewer the delay buffers, the better. + numBuffers = numBuffers * options_->getDelayBufferDerate(); + if (numBuffers == 0) { + // clang-format off + debugPrint(logger_, CTS, "insertion delay", 1, "no delay buffers are needed" + " to adjust latencies"); + // clang-format on + return; + } + // clang-format off + debugPrint(logger_, CTS, "insertion delay", 1, "{} delay buffers are needed" + " to adjust latencies at {} tree", numBuffers, + (builder->getTreeType() == macroTree)? "macro" : "register"); + // clang-format on + + // disconnect driver output + odb::dbInst* driver = builder->getTopBuffer(); + odb::dbITerm* driverOutputTerm = driver->getFirstOutput(); + odb::dbNet* outputNet = driverOutputTerm->getNet(); + + // get bbox of current load pins without driver output pin + driverOutputTerm->disconnect(); + odb::Rect bbox = outputNet->getTermBBox(); + int destX = bbox.xCenter(); + int destY = bbox.yCenter(); + int sourceX, sourceY; + driver->getLocation(sourceX, sourceY); + float offsetX = (float) (destX - sourceX) / (numBuffers + 1); + float offsetY = (float) (destY - sourceY) / (numBuffers + 1); + + double scalingFactor = techChar_->getLengthUnit(); + for (int i = 0; i < numBuffers; i++) { + double locX = (double) (sourceX + offsetX * (i + 1)) / scalingFactor; + double locY = (double) (sourceY + offsetY * (i + 1)) / scalingFactor; + Point bufferLoc(locX, locY); + Point legalBufferLoc + = builder->legalizeOneBuffer(bufferLoc, options_->getRootBuffer()); + odb::dbInst* buffer + = insertDelayBuffer(driver, + i, + builder->getClock().getSdcName(), + legalBufferLoc.getX() * scalingFactor, + legalBufferLoc.getY() * scalingFactor); + driver = buffer; + } + // take care of output pin connections + // driver is now the last delay buffer + driverOutputTerm = driver->getFirstOutput(); + driverOutputTerm->disconnect(); + driverOutputTerm->connect(outputNet); +} + +void TritonCTS::computeTopBufferDelay(TreeBuilder* builder) +{ + Clock clock = builder->getClock(); + std::string topBufferName; + if (builder->getTreeType() == registerTree) { + topBufferName = "clkbuf_regs_0_" + clock.getSdcName(); + } else { + topBufferName = "clkbuf_0_" + clock.getName(); + } + odb::dbInst* topBuffer = block_->findInst(topBufferName.c_str()); + if (topBuffer) { + builder->setTopBuffer(topBuffer); + odb::dbITerm* inputTerm = getFirstInput(topBuffer); + odb::dbITerm* outputTerm = topBuffer->getFirstOutput(); + sta::Pin* inputPin = network_->dbToSta(inputTerm); + sta::Pin* outputPin = network_->dbToSta(outputTerm); + + float inputArrival = openSta_->pinArrival( + inputPin, sta::RiseFall::rise(), sta::MinMax::max()); + float outputArrival = openSta_->pinArrival( + outputPin, sta::RiseFall::rise(), sta::MinMax::max()); + float bufferDelay = outputArrival - inputArrival; + builder->setTopBufferDelay(bufferDelay); + debugPrint( + logger_, + CTS, + "insertion delay", + 1, + "top buffer delay for {} {} is {:0.3e}", + (builder->getTreeType() == macroTree) ? "macro tree" : "register tree", + topBuffer->getName(), + builder->getTopBufferDelay()); + } +} + +// Create a new delay buffer and connect output pin of driver to input pin of +// new buffer. Output pin of new buffer will be connected later. +odb::dbInst* TritonCTS::insertDelayBuffer(odb::dbInst* driver, + int index, + const std::string& clockName, + int locX, + int locY) +{ + // creat a new input net + std::string newNetName + = "delaynet_" + std::to_string(index) + "_" + clockName; + odb::dbNet* newNet = odb::dbNet::create(block_, newNetName.c_str()); + newNet->setSigType(odb::dbSigType::CLOCK); + + // create a new delay buffer + std::string newBufName + = "delaybuf_" + std::to_string(index) + "_" + clockName; + odb::dbMaster* master = db_->findMaster(options_->getRootBuffer().c_str()); + odb::dbInst* newBuf = odb::dbInst::create(block_, master, newBufName.c_str()); + newBuf->setSourceType(odb::dbSourceType::TIMING); + newBuf->setLocation(locX, locY); + newBuf->setPlacementStatus(odb::dbPlacementStatus::PLACED); + + // connect driver output with new buffer input + odb::dbITerm* driverOutTerm = driver->getFirstOutput(); + odb::dbITerm* newBufInTerm = getFirstInput(newBuf); + driverOutTerm->disconnect(); + driverOutTerm->connect(newNet); + newBufInTerm->connect(newNet); + + debugPrint(logger_, + CTS, + "insertion delay", + 1, + "new delay buffer {} is inserted at ({} {})", + newBuf->getName(), + locX, + locY); + + return newBuf; +} + } // namespace cts diff --git a/src/cts/src/TritonCTS.i b/src/cts/src/TritonCTS.i index 2e7311787c2..bd846e1d694 100644 --- a/src/cts/src/TritonCTS.i +++ b/src/cts/src/TritonCTS.i @@ -248,6 +248,12 @@ set_dummy_load(bool dummyLoad) getTritonCts()->getParms()->enableDummyLoad(dummyLoad); } +void +set_delay_buffer_derate(float derate) +{ + getTritonCts()->getParms()->setDelayBufferDerate(derate); +} + void run_triton_cts() { diff --git a/src/cts/src/TritonCTS.tcl b/src/cts/src/TritonCTS.tcl index abbc601791c..3bd54e3c25f 100644 --- a/src/cts/src/TritonCTS.tcl +++ b/src/cts/src/TritonCTS.tcl @@ -88,7 +88,8 @@ sta::define_cmd_args "clock_tree_synthesis" {[-wire_unit unit] [-apply_ndr] \ [-insertion_delay] \ [-sink_buffer_max_cap_derate] \ - [-use_dummy_load] + [-use_dummy_load] \ + [-delay_buffer_derate] \ } proc clock_tree_synthesis { args } { @@ -96,7 +97,7 @@ proc clock_tree_synthesis { args } { keys {-root_buf -buf_list -wire_unit -clk_nets -sink_clustering_size -num_static_layers\ -sink_clustering_buffer -distance_between_buffers -branching_point_buffers_distance -clustering_exponent\ -clustering_unbalance_ratio -sink_clustering_max_diameter -sink_clustering_levels -tree_buf\ - -sink_buffer_max_cap_derate}\ + -sink_buffer_max_cap_derate -delay_buffer_derate}\ flags {-post_cts_disable -sink_clustering_enable -balance_levels \ -obstruction_aware -apply_ndr -insertion_delay -use_dummy_load} @@ -197,6 +198,14 @@ proc clock_tree_synthesis { args } { cts::set_sink_buffer_max_cap_derate $derate } + if { [info exists keys(-delay_buffer_derate)] } { + set buffer_derate $keys(-delay_buffer_derate) + if {[expr {$buffer_derate < 0.0 }]} { + utl::error CTS 123 "delay_buffer_derate needs to be greater than or equal to 0." + } + cts::set_delay_buffer_derate $buffer_derate + } + cts::set_obstruction_aware [info exists flags(-obstruction_aware)] cts::set_apply_ndr [info exists flags(-apply_ndr)] diff --git a/src/cts/test/array_ins_delay.ok b/src/cts/test/array_ins_delay.ok index 49c7d4108c8..98c1e024d8d 100644 --- a/src/cts/test/array_ins_delay.ok +++ b/src/cts/test/array_ins_delay.ok @@ -16,77 +16,1129 @@ BUF_X4 [INFO CTS-0049] Characterization buffer is BUF_X4. [INFO CTS-0007] Net "clk" found for clock "clk". -[INFO CTS-0010] Clock net "clk" has 2475 sinks. -[INFO CTS-0008] TritonCTS found 1 clock nets. +[INFO CTS-0011] Clock net "clk" for macros has 225 sinks. +[INFO CTS-0011] Clock net "clk_regs" for registers has 2250 sinks. +[INFO CTS-0008] TritonCTS found 2 clock nets. [INFO CTS-0097] Characterization used 1 buffer(s) types. [INFO CTS-0200] 225 placement blockages have been identified. [INFO CTS-0027] Generating H-Tree topology for net clk. -[INFO CTS-0028] Total number of sinks: 2475. +[INFO CTS-0028] Total number of sinks: 225. [INFO CTS-0029] Sinks will be clustered in groups of up to 20 and with maximum cluster diameter of 100.0 um. [INFO CTS-0030] Number of static layers: 0. [INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). -[INFO CTS-0204] A clustering solution was found from clustering size of 30 and clustering diameter of 100. +[INFO CTS-0204] A clustering solution was found from clustering size of 10 and clustering diameter of 100. [INFO CTS-0205] Better solution may be possible if either -sink_clustering_size, -sink_clustering_max_diameter, or both options are omitted to enable automatic clustering. -[INFO CTS-0019] Total number of sinks after clustering: 279. -[INFO CTS-0024] Normalized sink region: [(1.43857, 3.42643), (716.207, 704.276)]. -[INFO CTS-0025] Width: 714.7683. -[INFO CTS-0026] Height: 700.8493. +[INFO CTS-0019] Total number of sinks after clustering: 225. +[INFO CTS-0024] Normalized sink region: [(1.43857, 44.2757), (661.439, 704.276)]. +[INFO CTS-0025] Width: 660.0000. +[INFO CTS-0026] Height: 660.0000. Level 1 Direction: Horizontal - Sinks per sub-region: 140 - Sub-region size: 357.3841 X 700.8493 -[INFO CTS-0034] Segment length (rounded): 178. + Sinks per sub-region: 113 + Sub-region size: 330.0000 X 660.0000 +[INFO CTS-0034] Segment length (rounded): 166. Level 2 Direction: Vertical - Sinks per sub-region: 70 - Sub-region size: 357.3841 X 350.4246 -[INFO CTS-0034] Segment length (rounded): 176. + Sinks per sub-region: 57 + Sub-region size: 330.0000 X 330.0000 +[INFO CTS-0034] Segment length (rounded): 164. Level 3 Direction: Horizontal - Sinks per sub-region: 35 - Sub-region size: 178.6921 X 350.4246 -[INFO CTS-0034] Segment length (rounded): 90. + Sinks per sub-region: 29 + Sub-region size: 165.0000 X 330.0000 +[INFO CTS-0034] Segment length (rounded): 82. Level 4 Direction: Vertical - Sinks per sub-region: 18 - Sub-region size: 178.6921 X 175.2123 -[INFO CTS-0034] Segment length (rounded): 88. + Sinks per sub-region: 15 + Sub-region size: 165.0000 X 165.0000 +[INFO CTS-0034] Segment length (rounded): 82. Level 5 Direction: Horizontal - Sinks per sub-region: 9 - Sub-region size: 89.3460 X 175.2123 -[INFO CTS-0034] Segment length (rounded): 44. + Sinks per sub-region: 8 + Sub-region size: 82.5000 X 165.0000 +[INFO CTS-0034] Segment length (rounded): 42. [INFO CTS-0032] Stop criterion found. Max number of sinks is 15. -[INFO CTS-0035] Number of sinks covered: 279. -[INFO CTS-0018] Created 235 clock buffers. -[INFO CTS-0012] Minimum number of buffers in the clock path: 19. -[INFO CTS-0013] Maximum number of buffers in the clock path: 20. -[INFO CTS-0015] Created 235 clock nets. -[INFO CTS-0016] Fanout distribution for the current clock = 2:1, 6:5, 7:3, 8:16, 9:5, 10:1, 11:1, 12:8, 14:2, 15:1, 19:1, 20:3, 21:36, 30:45.. +[INFO CTS-0035] Number of sinks covered: 225. +[INFO CTS-0200] 225 placement blockages have been identified. +[INFO CTS-0027] Generating H-Tree topology for net clk_regs. +[INFO CTS-0028] Total number of sinks: 2250. +[INFO CTS-0029] Sinks will be clustered in groups of up to 20 and with maximum cluster diameter of 100.0 um. +[INFO CTS-0030] Number of static layers: 0. +[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). +[INFO CTS-0204] A clustering solution was found from clustering size of 10 and clustering diameter of 100. +[INFO CTS-0205] Better solution may be possible if either -sink_clustering_size, -sink_clustering_max_diameter, or both options are omitted to enable automatic clustering. +[INFO CTS-0019] Total number of sinks after clustering: 227. +[INFO CTS-0024] Normalized sink region: [(189.626, 2.21643), (661.055, 670.416)]. +[INFO CTS-0025] Width: 471.4286. +[INFO CTS-0026] Height: 668.2000. + Level 1 + Direction: Vertical + Sinks per sub-region: 114 + Sub-region size: 471.4286 X 334.1000 +[INFO CTS-0034] Segment length (rounded): 168. + Level 2 + Direction: Horizontal + Sinks per sub-region: 57 + Sub-region size: 235.7143 X 334.1000 +[INFO CTS-0034] Segment length (rounded): 118. + Level 3 + Direction: Vertical + Sinks per sub-region: 29 + Sub-region size: 235.7143 X 167.0500 +[INFO CTS-0034] Segment length (rounded): 84. + Level 4 + Direction: Horizontal + Sinks per sub-region: 15 + Sub-region size: 117.8572 X 167.0500 +[INFO CTS-0034] Segment length (rounded): 58. + Level 5 + Direction: Vertical + Sinks per sub-region: 8 + Sub-region size: 117.8572 X 83.5250 +[INFO CTS-0034] Segment length (rounded): 42. +[INFO CTS-0032] Stop criterion found. Max number of sinks is 15. +[INFO CTS-0035] Number of sinks covered: 227. +[INFO CTS-0018] Created 135 clock buffers. +[INFO CTS-0012] Minimum number of buffers in the clock path: 18. +[INFO CTS-0013] Maximum number of buffers in the clock path: 18. +[INFO CTS-0015] Created 135 clock nets. +[INFO CTS-0016] Fanout distribution for the current clock = 3:1, 5:3, 6:7, 7:3, 8:18.. [INFO CTS-0017] Max level of the clock tree: 5. +[INFO CTS-0018] Created 366 clock buffers. +[INFO CTS-0012] Minimum number of buffers in the clock path: 17. +[INFO CTS-0013] Maximum number of buffers in the clock path: 17. +[INFO CTS-0015] Created 366 clock nets. +[INFO CTS-0016] Fanout distribution for the current clock = 2:1, 4:3, 5:9, 6:5, 7:4, 8:3, 9:4, 10:230.. +[INFO CTS-0017] Max level of the clock tree: 5. +[INFO CTS-0121] Complex cell 'dff_14_13_30' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_31' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_32' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_33' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_34' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_35' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_36' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_37' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_38' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_39' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_40' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_41' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_42' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_43' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_44' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_45' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_46' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_47' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_48' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_49' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_0' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_1' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_2' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_3' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_4' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_5' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_6' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_7' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_8' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_9' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_10' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_11' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_12' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_13' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_14' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_15' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_16' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_17' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_18' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_19' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_20' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_21' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_22' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_23' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_24' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_25' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_26' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_27' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_28' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_29' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_30' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_31' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_32' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_33' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_34' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_35' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_36' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_37' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_38' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_39' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_40' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_41' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_42' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_43' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_44' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_45' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_46' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_47' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_48' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_14_49' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_0' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_1' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_2' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_3' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_4' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_5' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_6' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_7' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_8' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_9' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_10' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_11' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_12' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_13' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_14' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_15' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_16' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_17' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_18' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_19' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_20' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_21' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_22' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_23' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_24' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_25' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_26' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_27' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_28' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_29' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_30' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_31' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_32' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_33' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_34' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_35' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_36' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_37' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_38' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_39' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_40' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_41' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_42' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_43' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_44' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_45' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_46' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_47' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_48' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_12_49' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_49' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_48' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_47' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_46' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_45' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_44' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_43' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_42' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_41' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_40' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_39' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_38' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_37' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_36' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_35' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_34' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_33' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_32' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_31' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_30' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_29' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_28' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_27' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_26' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_25' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_24' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_23' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_22' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_21' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_20' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_19' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_18' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_17' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_16' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_15' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_14' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_13' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_12' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_11' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_10' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_9' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_8' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_7' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_6' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_5' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_4' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_3' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_2' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_1' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_14_0' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_0' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_1' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_2' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_3' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_4' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_5' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_6' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_7' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_8' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_9' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_10' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_11' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_12' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_13' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_14' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_15' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_16' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_17' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_18' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_19' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_20' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_21' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_22' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_23' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_24' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_25' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_26' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_27' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_28' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_13_29' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_49' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_48' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_47' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_46' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_45' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_44' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_43' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_42' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_41' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_40' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_10' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_11' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_12' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_13' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_14' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_15' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_16' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_17' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_18' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_19' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_20' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_21' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_22' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_23' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_24' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_25' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_26' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_27' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_28' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_29' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_30' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_31' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_32' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_33' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_34' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_35' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_36' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_37' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_38' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_39' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_40' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_41' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_42' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_43' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_44' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_45' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_46' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_47' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_48' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_49' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_0' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_1' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_2' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_3' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_4' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_5' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_6' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_7' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_8' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_9' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_10' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_11' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_12' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_13' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_14' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_15' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_16' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_17' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_18' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_19' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_20' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_21' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_22' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_23' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_24' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_25' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_26' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_27' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_28' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_29' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_30' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_31' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_32' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_33' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_34' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_35' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_36' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_37' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_38' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_39' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_40' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_41' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_42' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_43' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_44' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_45' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_46' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_47' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_48' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_11_49' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_0' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_1' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_2' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_3' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_4' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_5' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_6' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_7' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_8' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_9' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_10' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_11' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_12' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_13' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_14' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_15' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_16' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_17' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_18' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_19' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_20' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_21' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_22' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_23' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_24' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_25' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_26' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_27' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_28' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_29' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_30' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_31' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_32' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_33' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_34' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_35' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_36' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_37' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_38' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_39' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_40' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_41' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_42' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_43' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_44' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_45' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_46' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_47' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_48' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_7_49' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_0' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_1' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_2' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_3' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_4' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_5' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_6' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_7' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_8' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_10_9' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_0' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_1' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_2' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_3' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_4' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_5' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_6' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_7' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_8' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_9' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_10' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_11' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_12' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_13' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_14' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_15' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_16' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_17' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_18' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_19' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_20' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_21' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_22' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_23' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_24' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_25' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_26' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_27' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_28' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_29' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_30' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_31' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_32' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_33' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_34' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_35' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_36' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_37' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_38' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_39' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_40' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_41' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_42' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_43' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_44' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_45' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_46' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_47' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_48' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_9_49' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_0' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_1' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_2' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_3' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_4' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_5' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_6' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_7' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_8' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_9' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_10' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_11' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_12' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_13' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_14' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_15' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_16' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_17' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_18' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_19' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_20' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_21' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_22' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_23' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_24' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_25' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_26' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_27' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_28' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_29' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_30' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_31' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_32' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_33' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_34' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_35' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_36' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_37' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_38' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_39' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_40' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_41' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_42' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_43' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_44' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_45' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_46' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_47' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_48' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_14_8_49' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_39' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_38' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_37' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_36' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_35' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_34' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_33' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_32' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_31' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_30' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_29' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_28' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_27' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_26' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_25' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_24' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_23' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_22' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_21' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_20' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_19' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_18' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_17' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_16' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_15' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_14' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_13' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_12' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_11' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_10' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_9' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_8' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_7' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_6' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_5' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_4' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_3' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_2' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_1' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_13_0' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_49' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_48' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_47' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_46' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_45' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_44' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_43' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_42' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_41' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_40' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_39' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_38' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_37' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_36' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_35' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_34' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_33' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_32' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_31' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_30' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_29' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_28' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_27' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_26' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_25' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_24' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_23' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_22' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_21' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_20' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_19' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_18' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_17' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_16' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_15' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_14' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_13' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_12' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_11' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_10' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_9' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_8' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_7' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_6' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_5' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_4' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_3' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_2' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_1' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_12_0' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_49' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_48' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_47' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_46' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_45' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_44' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_43' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_42' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_41' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_40' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_39' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_38' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_37' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_36' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_35' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_34' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_33' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_32' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_31' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_30' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_29' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_28' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_27' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_26' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_25' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_24' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_23' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_22' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_21' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_20' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_19' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_18' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_17' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_16' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_15' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_14' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_13' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_12' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_11' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_10' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_9' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_8' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_7' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_6' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_5' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_4' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_3' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_2' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_1' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_11_0' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_49' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_48' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_47' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_46' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_45' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_44' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_43' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_42' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_41' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_40' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_39' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_38' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_37' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_36' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_35' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_34' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_33' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_32' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_31' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_30' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_29' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_28' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_27' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_26' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_25' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_24' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_23' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_22' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_21' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_20' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_19' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_18' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_17' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_16' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_15' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_14' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_13' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_12' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_11' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_10' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_9' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_8' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_7' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_6' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_5' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_4' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_3' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_2' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_1' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_14_0' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_49' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_48' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_47' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_46' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_45' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_44' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_43' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_42' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_41' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_40' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_39' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_38' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_37' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_36' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_35' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_34' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_33' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_32' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_31' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_30' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_29' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_28' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_27' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_26' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_25' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_24' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_23' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_22' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_21' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_20' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_19' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_18' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_17' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_16' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_15' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_14' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_13' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_12' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_11' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_10' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_9' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_8' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_7' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_6' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_5' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_4' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_3' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_2' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_1' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_13_0' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_49' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_48' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_47' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_46' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_45' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_44' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_43' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_42' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_41' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_40' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_39' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_38' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_37' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_36' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_35' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_34' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_33' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_32' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_31' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_30' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_29' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_28' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_27' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_26' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_25' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_24' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_23' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_22' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_21' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_20' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_19' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_18' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_17' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_16' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_15' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_14' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_13' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_12' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_11' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_10' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_9' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_8' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_7' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_6' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_5' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_4' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_3' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_2' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_1' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_12_0' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_49' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_48' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_47' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_46' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_45' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_44' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_43' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_42' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_41' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_40' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_39' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_38' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_37' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_36' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_35' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_34' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_33' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_32' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_31' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_30' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_29' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_28' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_27' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_26' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_25' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_24' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_23' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_22' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_21' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_20' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_19' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_18' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_17' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_16' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_15' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_14' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_13' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_12' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_11' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_10' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_9' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_8' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_7' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_6' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_5' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_4' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_3' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_2' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_1' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_11_0' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_49' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_48' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_47' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_46' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_45' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_44' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_43' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_42' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_41' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_40' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_39' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_38' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_37' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_36' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_35' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_34' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_33' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_32' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_31' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_30' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_29' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_28' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_27' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_26' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_25' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_24' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_23' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_22' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_21' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_20' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_19' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_18' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_17' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_16' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_15' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_14' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_13' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_12' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_11' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_10' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_9' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_8' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_7' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_6' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_5' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_4' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_3' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_2' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_1' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_10_0' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_49' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_48' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_47' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_46' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_45' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_44' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_43' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_42' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_41' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_40' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_39' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_38' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_37' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_36' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_35' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_34' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_33' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_32' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_31' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_30' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_29' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_28' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_27' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_26' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_25' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_24' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_23' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_22' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_21' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_20' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_19' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_18' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_17' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_16' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_15' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_14' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_13' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_12' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_11' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_10' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_9' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_8' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_7' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_6' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_5' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_4' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_3' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_2' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_1' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_9_0' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_49' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_48' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_47' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_46' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_45' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_44' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_43' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_42' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_41' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_40' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_39' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_38' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_37' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_36' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_35' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_34' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_33' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_32' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_31' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_30' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_29' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_28' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_27' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_26' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_25' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_24' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_23' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_22' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_21' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_20' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_19' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_18' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_17' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_16' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_15' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_14' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_13' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_12' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_11' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_10' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_9' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_8' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_7' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_6' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_5' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_4' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_3' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_2' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_1' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_8_0' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_49' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_48' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_47' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_46' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_45' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_44' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_43' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_42' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_41' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_40' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_39' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_38' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_37' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_36' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_35' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_34' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_33' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_32' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_31' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_30' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_29' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_28' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_27' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_26' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_9_7_25' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_49' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_48' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_47' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_46' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_45' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_44' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_43' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_42' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_41' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_40' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_39' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_38' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_37' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_36' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_35' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_34' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_33' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_32' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_31' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_30' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_29' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_28' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_27' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_26' has unconnected output pin. +[INFO CTS-0121] Complex cell 'dff_4_10_25' has unconnected output pin. +[INFO CTS-0121] message limit reached, this message will no longer print [INFO CTS-0098] Clock net "clk" -[INFO CTS-0099] Sinks 2475 -[INFO CTS-0100] Leaf buffers 96 -[INFO CTS-0101] Average sink wire length 9853.26 um -[INFO CTS-0102] Path depth 19 - 20 +[INFO CTS-0099] Sinks 225 +[INFO CTS-0100] Leaf buffers 0 +[INFO CTS-0101] Average sink wire length 9141.90 um +[INFO CTS-0102] Path depth 18 - 18 +[INFO CTS-0098] Clock net "clk_regs" +[INFO CTS-0099] Sinks 2250 +[INFO CTS-0100] Leaf buffers 227 +[INFO CTS-0101] Average sink wire length 4903.60 um +[INFO CTS-0102] Path depth 17 - 17 [INFO RSZ-0058] Using max wire length 707um. -[INFO RSZ-0047] Found 34 long wires. -[INFO RSZ-0048] Inserted 96 buffers in 34 nets. +[INFO RSZ-0047] Found 54 long wires. +[INFO RSZ-0048] Inserted 108 buffers in 54 nets. Placement Analysis --------------------------------- -total displacement 2633.1 u -average displacement 0.9 u -max displacement 106.8 u -original HPWL 150232.5 u -legalized HPWL 150349.8 u +total displacement 3004.1 u +average displacement 1.0 u +max displacement 94.3 u +original HPWL 185798.0 u +legalized HPWL 186303.3 u delta HPWL 0 % Clock clk Latency CRPR Skew -inst_8_4/clk ^ - 1.32 -inst_10_4/clk ^ - 1.16 0.00 0.16 +inst_7_9/clk ^ + 1.27 +inst_8_9/clk ^ + 1.10 0.00 0.17 Startpoint: inst_1_1 (rising edge-triggered flip-flop clocked by clk) Endpoint: inst_2_1 (rising edge-triggered flip-flop clocked by clk) @@ -98,77 +1150,75 @@ Path Type: max 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock source latency 0.00 0.00 ^ clk (in) - 0.04 0.04 ^ wire7/Z (BUF_X8) - 0.06 0.10 ^ wire6/Z (BUF_X16) - 0.06 0.17 ^ wire5/Z (BUF_X32) - 0.06 0.23 ^ wire4/Z (BUF_X32) - 0.06 0.29 ^ wire3/Z (BUF_X32) - 0.06 0.36 ^ wire2/Z (BUF_X32) - 0.06 0.42 ^ wire1/Z (BUF_X32) - 0.07 0.49 ^ clkbuf_0_clk/Z (BUF_X4) - 0.03 0.52 ^ clkbuf_1_0_0_clk/Z (BUF_X4) - 0.03 0.55 ^ clkbuf_1_0_1_clk/Z (BUF_X4) - 0.03 0.58 ^ clkbuf_1_0_2_clk/Z (BUF_X4) + 0.05 0.05 ^ wire6/Z (BUF_X16) + 0.06 0.11 ^ wire5/Z (BUF_X16) + 0.07 0.17 ^ wire4/Z (BUF_X32) + 0.06 0.24 ^ wire3/Z (BUF_X32) + 0.06 0.30 ^ wire2/Z (BUF_X32) + 0.06 0.37 ^ wire1/Z (BUF_X32) + 0.07 0.44 ^ clkbuf_0_clk/Z (BUF_X4) + 0.04 0.47 ^ delaybuf_0_clk/Z (BUF_X4) + 0.03 0.51 ^ clkbuf_1_0_0_clk/Z (BUF_X4) + 0.03 0.54 ^ clkbuf_1_0_1_clk/Z (BUF_X4) + 0.03 0.57 ^ clkbuf_1_0_2_clk/Z (BUF_X4) 0.03 0.61 ^ clkbuf_1_0_3_clk/Z (BUF_X4) 0.04 0.65 ^ clkbuf_1_0_4_clk/Z (BUF_X4) - 0.04 0.69 ^ clkbuf_2_0_0_clk/Z (BUF_X4) - 0.03 0.72 ^ clkbuf_2_0_1_clk/Z (BUF_X4) - 0.03 0.76 ^ clkbuf_2_0_2_clk/Z (BUF_X4) - 0.03 0.79 ^ clkbuf_2_0_3_clk/Z (BUF_X4) - 0.03 0.83 ^ clkbuf_2_0_4_clk/Z (BUF_X4) - 0.04 0.86 ^ clkbuf_2_0_5_clk/Z (BUF_X4) - 0.03 0.90 ^ clkbuf_3_0_0_clk/Z (BUF_X4) - 0.03 0.93 ^ clkbuf_3_0_1_clk/Z (BUF_X4) - 0.03 0.97 ^ clkbuf_3_0_2_clk/Z (BUF_X4) - 0.03 1.00 ^ clkbuf_4_0_0_clk/Z (BUF_X4) - 0.04 1.04 ^ clkbuf_4_0_1_clk/Z (BUF_X4) - 0.05 1.08 ^ clkbuf_4_0_2_clk/Z (BUF_X4) - 0.04 1.13 ^ clkbuf_5_0_0_clk/Z (BUF_X4) - 0.04 1.17 ^ max_length9/Z (BUF_X8) - 0.04 1.20 ^ inst_1_1/clk (array_tile) - 0.21 1.42 ^ inst_1_1/e_out (array_tile) - 0.00 1.42 ^ inst_2_1/w_in (array_tile) - 1.42 data arrival time + 0.03 0.68 ^ clkbuf_2_0_0_clk/Z (BUF_X4) + 0.03 0.71 ^ clkbuf_2_0_1_clk/Z (BUF_X4) + 0.03 0.75 ^ clkbuf_2_0_2_clk/Z (BUF_X4) + 0.03 0.78 ^ clkbuf_2_0_3_clk/Z (BUF_X4) + 0.04 0.82 ^ clkbuf_2_0_4_clk/Z (BUF_X4) + 0.03 0.85 ^ clkbuf_3_0_0_clk/Z (BUF_X4) + 0.03 0.88 ^ clkbuf_3_0_1_clk/Z (BUF_X4) + 0.04 0.93 ^ clkbuf_3_0_2_clk/Z (BUF_X4) + 0.03 0.95 ^ clkbuf_4_0_0_clk/Z (BUF_X4) + 0.03 0.98 ^ clkbuf_4_0_1_clk/Z (BUF_X4) + 0.05 1.03 ^ clkbuf_4_0_2_clk/Z (BUF_X4) + 0.04 1.07 ^ clkbuf_5_0_0_clk/Z (BUF_X4) + 0.03 1.10 ^ max_length7/Z (BUF_X8) + 0.04 1.14 ^ inst_1_1/clk (array_tile) + 0.21 1.35 ^ inst_1_1/e_out (array_tile) + 0.00 1.35 ^ inst_2_1/w_in (array_tile) + 1.35 data arrival time 5.00 5.00 clock clk (rise edge) 0.00 5.00 clock source latency 0.00 5.00 ^ clk (in) - 0.04 5.04 ^ wire7/Z (BUF_X8) - 0.06 5.10 ^ wire6/Z (BUF_X16) - 0.06 5.17 ^ wire5/Z (BUF_X32) - 0.06 5.23 ^ wire4/Z (BUF_X32) - 0.06 5.29 ^ wire3/Z (BUF_X32) - 0.06 5.36 ^ wire2/Z (BUF_X32) - 0.06 5.42 ^ wire1/Z (BUF_X32) - 0.07 5.49 ^ clkbuf_0_clk/Z (BUF_X4) - 0.03 5.52 ^ clkbuf_1_0_0_clk/Z (BUF_X4) - 0.03 5.55 ^ clkbuf_1_0_1_clk/Z (BUF_X4) - 0.03 5.58 ^ clkbuf_1_0_2_clk/Z (BUF_X4) + 0.05 5.05 ^ wire6/Z (BUF_X16) + 0.06 5.11 ^ wire5/Z (BUF_X16) + 0.07 5.17 ^ wire4/Z (BUF_X32) + 0.06 5.24 ^ wire3/Z (BUF_X32) + 0.06 5.30 ^ wire2/Z (BUF_X32) + 0.06 5.37 ^ wire1/Z (BUF_X32) + 0.07 5.44 ^ clkbuf_0_clk/Z (BUF_X4) + 0.04 5.47 ^ delaybuf_0_clk/Z (BUF_X4) + 0.03 5.51 ^ clkbuf_1_0_0_clk/Z (BUF_X4) + 0.03 5.54 ^ clkbuf_1_0_1_clk/Z (BUF_X4) + 0.03 5.57 ^ clkbuf_1_0_2_clk/Z (BUF_X4) 0.03 5.61 ^ clkbuf_1_0_3_clk/Z (BUF_X4) 0.04 5.65 ^ clkbuf_1_0_4_clk/Z (BUF_X4) - 0.04 5.69 ^ clkbuf_2_0_0_clk/Z (BUF_X4) - 0.03 5.72 ^ clkbuf_2_0_1_clk/Z (BUF_X4) - 0.03 5.76 ^ clkbuf_2_0_2_clk/Z (BUF_X4) - 0.03 5.79 ^ clkbuf_2_0_3_clk/Z (BUF_X4) - 0.03 5.83 ^ clkbuf_2_0_4_clk/Z (BUF_X4) - 0.04 5.86 ^ clkbuf_2_0_5_clk/Z (BUF_X4) - 0.03 5.90 ^ clkbuf_3_0_0_clk/Z (BUF_X4) - 0.03 5.93 ^ clkbuf_3_0_1_clk/Z (BUF_X4) - 0.03 5.97 ^ clkbuf_3_0_2_clk/Z (BUF_X4) - 0.03 6.00 ^ clkbuf_4_0_0_clk/Z (BUF_X4) - 0.04 6.04 ^ clkbuf_4_0_1_clk/Z (BUF_X4) - 0.05 6.08 ^ clkbuf_4_0_2_clk/Z (BUF_X4) - 0.04 6.12 ^ clkbuf_5_1_0_clk/Z (BUF_X4) - 0.04 6.16 ^ max_length14/Z (BUF_X8) - 0.04 6.20 ^ inst_2_1/clk (array_tile) - 0.00 6.20 clock reconvergence pessimism - -0.05 6.15 library setup time - 6.15 data required time + 0.03 5.68 ^ clkbuf_2_0_0_clk/Z (BUF_X4) + 0.03 5.71 ^ clkbuf_2_0_1_clk/Z (BUF_X4) + 0.03 5.75 ^ clkbuf_2_0_2_clk/Z (BUF_X4) + 0.03 5.78 ^ clkbuf_2_0_3_clk/Z (BUF_X4) + 0.04 5.82 ^ clkbuf_2_0_4_clk/Z (BUF_X4) + 0.03 5.85 ^ clkbuf_3_0_0_clk/Z (BUF_X4) + 0.03 5.88 ^ clkbuf_3_0_1_clk/Z (BUF_X4) + 0.04 5.93 ^ clkbuf_3_0_2_clk/Z (BUF_X4) + 0.03 5.95 ^ clkbuf_4_0_0_clk/Z (BUF_X4) + 0.03 5.98 ^ clkbuf_4_0_1_clk/Z (BUF_X4) + 0.05 6.03 ^ clkbuf_4_0_2_clk/Z (BUF_X4) + 0.04 6.07 ^ clkbuf_5_1_0_clk/Z (BUF_X4) + 0.03 6.10 ^ max_length12/Z (BUF_X8) + 0.04 6.14 ^ inst_2_1/clk (array_tile) + 0.00 6.14 clock reconvergence pessimism + -0.05 6.09 library setup time + 6.09 data required time --------------------------------------------------------- - 6.15 data required time - -1.42 data arrival time + 6.09 data required time + -1.35 data arrival time --------------------------------------------------------- - 4.73 slack (MET) + 4.74 slack (MET) Startpoint: inst_2_1 (rising edge-triggered flip-flop clocked by clk) @@ -181,75 +1231,73 @@ Path Type: max 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock source latency 0.00 0.00 ^ clk (in) - 0.04 0.04 ^ wire7/Z (BUF_X8) - 0.06 0.10 ^ wire6/Z (BUF_X16) - 0.06 0.17 ^ wire5/Z (BUF_X32) - 0.06 0.23 ^ wire4/Z (BUF_X32) - 0.06 0.29 ^ wire3/Z (BUF_X32) - 0.06 0.36 ^ wire2/Z (BUF_X32) - 0.06 0.42 ^ wire1/Z (BUF_X32) - 0.07 0.49 ^ clkbuf_0_clk/Z (BUF_X4) - 0.03 0.52 ^ clkbuf_1_0_0_clk/Z (BUF_X4) - 0.03 0.55 ^ clkbuf_1_0_1_clk/Z (BUF_X4) - 0.03 0.58 ^ clkbuf_1_0_2_clk/Z (BUF_X4) + 0.05 0.05 ^ wire6/Z (BUF_X16) + 0.06 0.11 ^ wire5/Z (BUF_X16) + 0.07 0.17 ^ wire4/Z (BUF_X32) + 0.06 0.24 ^ wire3/Z (BUF_X32) + 0.06 0.30 ^ wire2/Z (BUF_X32) + 0.06 0.37 ^ wire1/Z (BUF_X32) + 0.07 0.44 ^ clkbuf_0_clk/Z (BUF_X4) + 0.04 0.47 ^ delaybuf_0_clk/Z (BUF_X4) + 0.03 0.51 ^ clkbuf_1_0_0_clk/Z (BUF_X4) + 0.03 0.54 ^ clkbuf_1_0_1_clk/Z (BUF_X4) + 0.03 0.57 ^ clkbuf_1_0_2_clk/Z (BUF_X4) 0.03 0.61 ^ clkbuf_1_0_3_clk/Z (BUF_X4) 0.04 0.65 ^ clkbuf_1_0_4_clk/Z (BUF_X4) - 0.04 0.69 ^ clkbuf_2_0_0_clk/Z (BUF_X4) - 0.03 0.72 ^ clkbuf_2_0_1_clk/Z (BUF_X4) - 0.03 0.76 ^ clkbuf_2_0_2_clk/Z (BUF_X4) - 0.03 0.79 ^ clkbuf_2_0_3_clk/Z (BUF_X4) - 0.03 0.83 ^ clkbuf_2_0_4_clk/Z (BUF_X4) - 0.04 0.86 ^ clkbuf_2_0_5_clk/Z (BUF_X4) - 0.03 0.90 ^ clkbuf_3_0_0_clk/Z (BUF_X4) - 0.03 0.93 ^ clkbuf_3_0_1_clk/Z (BUF_X4) - 0.03 0.97 ^ clkbuf_3_0_2_clk/Z (BUF_X4) - 0.03 1.00 ^ clkbuf_4_0_0_clk/Z (BUF_X4) - 0.04 1.04 ^ clkbuf_4_0_1_clk/Z (BUF_X4) - 0.05 1.08 ^ clkbuf_4_0_2_clk/Z (BUF_X4) - 0.04 1.12 ^ clkbuf_5_1_0_clk/Z (BUF_X4) - 0.04 1.16 ^ max_length14/Z (BUF_X8) - 0.04 1.20 ^ inst_2_1/clk (array_tile) - 0.21 1.41 ^ inst_2_1/w_out (array_tile) - 0.00 1.41 ^ inst_1_1/e_in (array_tile) - 1.41 data arrival time + 0.03 0.68 ^ clkbuf_2_0_0_clk/Z (BUF_X4) + 0.03 0.71 ^ clkbuf_2_0_1_clk/Z (BUF_X4) + 0.03 0.75 ^ clkbuf_2_0_2_clk/Z (BUF_X4) + 0.03 0.78 ^ clkbuf_2_0_3_clk/Z (BUF_X4) + 0.04 0.82 ^ clkbuf_2_0_4_clk/Z (BUF_X4) + 0.03 0.85 ^ clkbuf_3_0_0_clk/Z (BUF_X4) + 0.03 0.88 ^ clkbuf_3_0_1_clk/Z (BUF_X4) + 0.04 0.93 ^ clkbuf_3_0_2_clk/Z (BUF_X4) + 0.03 0.95 ^ clkbuf_4_0_0_clk/Z (BUF_X4) + 0.03 0.98 ^ clkbuf_4_0_1_clk/Z (BUF_X4) + 0.05 1.03 ^ clkbuf_4_0_2_clk/Z (BUF_X4) + 0.04 1.07 ^ clkbuf_5_1_0_clk/Z (BUF_X4) + 0.03 1.10 ^ max_length12/Z (BUF_X8) + 0.04 1.14 ^ inst_2_1/clk (array_tile) + 0.21 1.35 ^ inst_2_1/w_out (array_tile) + 0.00 1.35 ^ inst_1_1/e_in (array_tile) + 1.35 data arrival time 5.00 5.00 clock clk (rise edge) 0.00 5.00 clock source latency 0.00 5.00 ^ clk (in) - 0.04 5.04 ^ wire7/Z (BUF_X8) - 0.06 5.10 ^ wire6/Z (BUF_X16) - 0.06 5.17 ^ wire5/Z (BUF_X32) - 0.06 5.23 ^ wire4/Z (BUF_X32) - 0.06 5.29 ^ wire3/Z (BUF_X32) - 0.06 5.36 ^ wire2/Z (BUF_X32) - 0.06 5.42 ^ wire1/Z (BUF_X32) - 0.07 5.49 ^ clkbuf_0_clk/Z (BUF_X4) - 0.03 5.52 ^ clkbuf_1_0_0_clk/Z (BUF_X4) - 0.03 5.55 ^ clkbuf_1_0_1_clk/Z (BUF_X4) - 0.03 5.58 ^ clkbuf_1_0_2_clk/Z (BUF_X4) + 0.05 5.05 ^ wire6/Z (BUF_X16) + 0.06 5.11 ^ wire5/Z (BUF_X16) + 0.07 5.17 ^ wire4/Z (BUF_X32) + 0.06 5.24 ^ wire3/Z (BUF_X32) + 0.06 5.30 ^ wire2/Z (BUF_X32) + 0.06 5.37 ^ wire1/Z (BUF_X32) + 0.07 5.44 ^ clkbuf_0_clk/Z (BUF_X4) + 0.04 5.47 ^ delaybuf_0_clk/Z (BUF_X4) + 0.03 5.51 ^ clkbuf_1_0_0_clk/Z (BUF_X4) + 0.03 5.54 ^ clkbuf_1_0_1_clk/Z (BUF_X4) + 0.03 5.57 ^ clkbuf_1_0_2_clk/Z (BUF_X4) 0.03 5.61 ^ clkbuf_1_0_3_clk/Z (BUF_X4) 0.04 5.65 ^ clkbuf_1_0_4_clk/Z (BUF_X4) - 0.04 5.69 ^ clkbuf_2_0_0_clk/Z (BUF_X4) - 0.03 5.72 ^ clkbuf_2_0_1_clk/Z (BUF_X4) - 0.03 5.76 ^ clkbuf_2_0_2_clk/Z (BUF_X4) - 0.03 5.79 ^ clkbuf_2_0_3_clk/Z (BUF_X4) - 0.03 5.83 ^ clkbuf_2_0_4_clk/Z (BUF_X4) - 0.04 5.86 ^ clkbuf_2_0_5_clk/Z (BUF_X4) - 0.03 5.90 ^ clkbuf_3_0_0_clk/Z (BUF_X4) - 0.03 5.93 ^ clkbuf_3_0_1_clk/Z (BUF_X4) - 0.03 5.97 ^ clkbuf_3_0_2_clk/Z (BUF_X4) - 0.03 6.00 ^ clkbuf_4_0_0_clk/Z (BUF_X4) - 0.04 6.04 ^ clkbuf_4_0_1_clk/Z (BUF_X4) - 0.05 6.08 ^ clkbuf_4_0_2_clk/Z (BUF_X4) - 0.04 6.13 ^ clkbuf_5_0_0_clk/Z (BUF_X4) - 0.04 6.17 ^ max_length9/Z (BUF_X8) - 0.04 6.20 ^ inst_1_1/clk (array_tile) - 0.00 6.20 clock reconvergence pessimism - -0.05 6.15 library setup time - 6.15 data required time + 0.03 5.68 ^ clkbuf_2_0_0_clk/Z (BUF_X4) + 0.03 5.71 ^ clkbuf_2_0_1_clk/Z (BUF_X4) + 0.03 5.75 ^ clkbuf_2_0_2_clk/Z (BUF_X4) + 0.03 5.78 ^ clkbuf_2_0_3_clk/Z (BUF_X4) + 0.04 5.82 ^ clkbuf_2_0_4_clk/Z (BUF_X4) + 0.03 5.85 ^ clkbuf_3_0_0_clk/Z (BUF_X4) + 0.03 5.88 ^ clkbuf_3_0_1_clk/Z (BUF_X4) + 0.04 5.93 ^ clkbuf_3_0_2_clk/Z (BUF_X4) + 0.03 5.95 ^ clkbuf_4_0_0_clk/Z (BUF_X4) + 0.03 5.98 ^ clkbuf_4_0_1_clk/Z (BUF_X4) + 0.05 6.03 ^ clkbuf_4_0_2_clk/Z (BUF_X4) + 0.04 6.07 ^ clkbuf_5_0_0_clk/Z (BUF_X4) + 0.03 6.10 ^ max_length7/Z (BUF_X8) + 0.04 6.14 ^ inst_1_1/clk (array_tile) + 0.00 6.14 clock reconvergence pessimism + -0.05 6.09 library setup time + 6.09 data required time --------------------------------------------------------- - 6.15 data required time - -1.41 data arrival time + 6.09 data required time + -1.35 data arrival time --------------------------------------------------------- 4.74 slack (MET) diff --git a/src/cts/test/insertion_delay.ok b/src/cts/test/insertion_delay.ok index 55c64932ddf..59db24818f2 100644 --- a/src/cts/test/insertion_delay.ok +++ b/src/cts/test/insertion_delay.ok @@ -16,13 +16,14 @@ CLKBUF_X3 [INFO CTS-0049] Characterization buffer is CLKBUF_X3. [INFO CTS-0007] Net "clk" found for clock "clk". -[INFO CTS-0010] Clock net "clk" has 279 sinks. +[INFO CTS-0042] Clock net "clk" for macros has 1 sinks. Skipping... +[INFO CTS-0011] Clock net "clk_regs" for registers has 278 sinks. [INFO CTS-0008] TritonCTS found 1 clock nets. [INFO CTS-0097] Characterization used 1 buffer(s) types. [INFO CTS-0200] 0 placement blockages have been identified. [INFO CTS-0201] 1 placed hard macros will be treated like blockages. -[INFO CTS-0027] Generating H-Tree topology for net clk. -[INFO CTS-0028] Total number of sinks: 279. +[INFO CTS-0027] Generating H-Tree topology for net clk_regs. +[INFO CTS-0028] Total number of sinks: 278. [INFO CTS-0029] Sinks will be clustered in groups of up to 10 and with maximum cluster diameter of 60.0 um. [INFO CTS-0030] Number of static layers: 1. [INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). @@ -30,13 +31,13 @@ [INFO CTS-0204] A clustering solution was found from clustering size of 10 and clustering diameter of 60. [INFO CTS-0205] Better solution may be possible if either -sink_clustering_size, -sink_clustering_max_diameter, or both options are omitted to enable automatic clustering. [INFO CTS-0019] Total number of sinks after clustering: 28. -[INFO CTS-0024] Normalized sink region: [(1.26757, 0.956587), (13.4493, 11.6927)]. -[INFO CTS-0025] Width: 12.1817. -[INFO CTS-0026] Height: 10.7361. +[INFO CTS-0024] Normalized sink region: [(1.34629, 0.912143), (13.4493, 11.6927)]. +[INFO CTS-0025] Width: 12.1030. +[INFO CTS-0026] Height: 10.7806. Level 1 Direction: Horizontal Sinks per sub-region: 14 - Sub-region size: 6.0909 X 10.7361 + Sub-region size: 6.0515 X 10.7806 [INFO CTS-0034] Segment length (rounded): 4. [INFO CTS-0032] Stop criterion found. Max number of sinks is 15. [INFO CTS-0035] Number of sinks covered: 28. @@ -44,11 +45,11 @@ [INFO CTS-0012] Minimum number of buffers in the clock path: 3. [INFO CTS-0013] Maximum number of buffers in the clock path: 3. [INFO CTS-0015] Created 31 clock nets. -[INFO CTS-0016] Fanout distribution for the current clock = 9:1, 10:27, 13:1, 15:1.. +[INFO CTS-0016] Fanout distribution for the current clock = 8:1, 10:27, 14:2.. [INFO CTS-0017] Max level of the clock tree: 1. -[INFO CTS-0098] Clock net "clk" -[INFO CTS-0099] Sinks 279 +[INFO CTS-0098] Clock net "clk_regs" +[INFO CTS-0099] Sinks 278 [INFO CTS-0100] Leaf buffers 28 -[INFO CTS-0101] Average sink wire length 128.47 um +[INFO CTS-0101] Average sink wire length 74.51 um [INFO CTS-0102] Path depth 3 - 3 Found 0 unconnected buffers. diff --git a/src/gui/src/clockWidget.cpp b/src/gui/src/clockWidget.cpp index ca59af31d1e..ccc6b09b2ca 100644 --- a/src/gui/src/clockWidget.cpp +++ b/src/gui/src/clockWidget.cpp @@ -564,7 +564,7 @@ QPainterPath ClockRootNodeGraphicsViewItem::shape() const //////////////// -ClockRegisterNodeGraphicsViewItem::ClockRegisterNodeGraphicsViewItem( +ClockLeafNodeGraphicsViewItem::ClockLeafNodeGraphicsViewItem( odb::dbITerm* iterm, QGraphicsItem* parent) : ClockNodeGraphicsViewItem(parent), @@ -576,7 +576,7 @@ ClockRegisterNodeGraphicsViewItem::ClockRegisterNodeGraphicsViewItem( menu_.addAction(highlight_path_); } -QPolygonF ClockRegisterNodeGraphicsViewItem::getClockInputPolygon() const +QPolygonF ClockLeafNodeGraphicsViewItem::getClockInputPolygon() const { const qreal size = getSize(); QPolygonF poly; @@ -587,7 +587,7 @@ QPolygonF ClockRegisterNodeGraphicsViewItem::getClockInputPolygon() const return poly; } -QRectF ClockRegisterNodeGraphicsViewItem::getOutlineRect() const +QRectF ClockLeafNodeGraphicsViewItem::getOutlineRect() const { const qreal size = getSize(); const QPointF ll(-size / 2, size); @@ -596,17 +596,17 @@ QRectF ClockRegisterNodeGraphicsViewItem::getOutlineRect() const return rect.normalized(); } -QRectF ClockRegisterNodeGraphicsViewItem::boundingRect() const +QRectF ClockLeafNodeGraphicsViewItem::boundingRect() const { return getOutlineRect(); } -void ClockRegisterNodeGraphicsViewItem::paint( +void ClockLeafNodeGraphicsViewItem::paint( QPainter* painter, const QStyleOptionGraphicsItem* option, QWidget* widget) { - const QColor outline = leaf_color_; + const QColor outline = getColor(); const QColor fill(outline.lighter()); QPen pen(outline); @@ -627,7 +627,7 @@ void ClockRegisterNodeGraphicsViewItem::paint( painter->drawPolygon(getClockInputPolygon()); } -void ClockRegisterNodeGraphicsViewItem::contextMenuEvent( +void ClockLeafNodeGraphicsViewItem::contextMenuEvent( QGraphicsSceneContextMenuEvent* event) { event->accept(); @@ -1155,12 +1155,36 @@ ClockNodeGraphicsViewItem* ClockTreeView::addLeafToScene( odb::dbBTerm* bterm; network->staToDb(input_pin.pin, iterm, bterm); - ClockRegisterNodeGraphicsViewItem* node - = new ClockRegisterNodeGraphicsViewItem(iterm); + // distinguish between registers and macros + ClockLeafNodeGraphicsViewItem* node; + odb::dbInst* inst = iterm->getInst(); + if (inst->getMaster()->getType().isBlock()) { + node = new ClockMacroNodeGraphicsViewItem(iterm); + } else { + node = new ClockRegisterNodeGraphicsViewItem(iterm); + } node->scaleSize(leaf_scale_); - node->setPos({x, convertDelayToY(input_pin.delay)}); - node->setExtraToolTip("Arrival: " + convertDelayToString(input_pin.delay)); + // add insertion delay at macro cell input pin + float ins_delay = 0.0; + sta::LibertyCell* libCell = network->libertyCell(network->dbToSta(inst)); + odb::dbMTerm* mterm = iterm->getMTerm(); + if (libCell && mterm) { + sta::LibertyPort* libPort = libCell->findLibertyPort(mterm->getConstName()); + if (libPort) { + sta::RiseFallMinMax insDelays = libPort->clockTreePathDelays(); + if (insDelays.hasValue()) { + ins_delay + = (insDelays.value(sta::RiseFall::rise(), sta::MinMax::max()) + + insDelays.value(sta::RiseFall::fall(), sta::MinMax::max())) + / 2.0; + } + } + } + + node->setPos({x, convertDelayToY(input_pin.delay + ins_delay)}); + node->setExtraToolTip("Arrival: " + + convertDelayToString(input_pin.delay + ins_delay)); scene_->addItem(node); connect(node->getHighlightAction(), &QAction::triggered, [this, iterm]() { diff --git a/src/gui/src/clockWidget.h b/src/gui/src/clockWidget.h index 9b6646e7d8f..c60b1d17aa8 100644 --- a/src/gui/src/clockWidget.h +++ b/src/gui/src/clockWidget.h @@ -182,7 +182,8 @@ class ClockNodeGraphicsViewItem : public QGraphicsItem constexpr static Qt::GlobalColor root_color_ = Qt::red; constexpr static Qt::GlobalColor clock_gate_color_ = Qt::magenta; constexpr static Qt::GlobalColor unknown_color_ = Qt::darkGray; - constexpr static Qt::GlobalColor leaf_color_ = Qt::red; + constexpr static Qt::GlobalColor leaf_register_color_ = Qt::red; + constexpr static Qt::GlobalColor leaf_macro_color_ = Qt::darkCyan; constexpr static qreal default_size_ = 100.0; @@ -256,16 +257,16 @@ class ClockBufferNodeGraphicsViewItem : public ClockNodeGraphicsViewItem constexpr static qreal bar_scale_size_ = 0.1; }; -// Handles drawing the register node for a tree -class ClockRegisterNodeGraphicsViewItem : public ClockNodeGraphicsViewItem +// Handles drawing macro or register leaf cell +class ClockLeafNodeGraphicsViewItem : public ClockNodeGraphicsViewItem { public: - ClockRegisterNodeGraphicsViewItem(odb::dbITerm* iterm, - QGraphicsItem* parent = nullptr); - ~ClockRegisterNodeGraphicsViewItem() {} + ClockLeafNodeGraphicsViewItem(odb::dbITerm* iterm, + QGraphicsItem* parent = nullptr); + ~ClockLeafNodeGraphicsViewItem() override = default; - virtual QString getType() const override { return "Register"; } - virtual QColor getColor() const override { return leaf_color_; } + QString getType() const override = 0; + QColor getColor() const override = 0; QRectF boundingRect() const override; void paint(QPainter* painter, @@ -276,8 +277,6 @@ class ClockRegisterNodeGraphicsViewItem : public ClockNodeGraphicsViewItem protected: void contextMenuEvent(QGraphicsSceneContextMenuEvent* event) override; - - private: QMenu menu_; QAction* highlight_path_; @@ -285,6 +284,34 @@ class ClockRegisterNodeGraphicsViewItem : public ClockNodeGraphicsViewItem QPolygonF getClockInputPolygon() const; }; +// Handles drawing register cell node for a tree +class ClockRegisterNodeGraphicsViewItem : public ClockLeafNodeGraphicsViewItem +{ + public: + ClockRegisterNodeGraphicsViewItem(odb::dbITerm* iterm, + QGraphicsItem* parent = nullptr) + : ClockLeafNodeGraphicsViewItem(iterm, parent) + { + } + ~ClockRegisterNodeGraphicsViewItem() override = default; + QString getType() const override { return "Register"; } + QColor getColor() const override { return leaf_register_color_; } +}; + +// Handles drawing macro cell node for a tree +class ClockMacroNodeGraphicsViewItem : public ClockLeafNodeGraphicsViewItem +{ + public: + ClockMacroNodeGraphicsViewItem(odb::dbITerm* iterm, + QGraphicsItem* parent = nullptr) + : ClockLeafNodeGraphicsViewItem(iterm, parent) + { + } + ~ClockMacroNodeGraphicsViewItem() override = default; + QString getType() const override { return "Macro"; } + QColor getColor() const override { return leaf_macro_color_; } +}; + // Handles drawing the clock gate and non-inverter/buffers nodes in the tree class ClockGateNodeGraphicsViewItem : public ClockNodeGraphicsViewItem {