diff --git a/src/cts/test/simple_test_hier.ok b/src/cts/test/simple_test_hier.ok
index 24368801950..f79c95934ba 100644
--- a/src/cts/test/simple_test_hier.ok
+++ b/src/cts/test/simple_test_hier.ok
@@ -1,5 +1,4 @@
 [INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
-[INFO ODB-0227] LEF file: dummy_pads.lef, created 25 library cells
 [INFO IFP-0001] Added 857 rows of 210 site FreePDK45_38x28_10R_NP_162NW_34O.
 [INFO GPL-0002] DBU: 2000
 [INFO GPL-0003] SiteSize: (  0.190  1.400 ) um
diff --git a/src/cts/test/simple_test_hier.tcl b/src/cts/test/simple_test_hier.tcl
index 6b6c3ccc463..ed65c2e645e 100644
--- a/src/cts/test/simple_test_hier.tcl
+++ b/src/cts/test/simple_test_hier.tcl
@@ -1,17 +1,17 @@
 source "helpers.tcl"
 read_lef Nangate45/Nangate45.lef
-read_lef dummy_pads.lef
+#read_lef dummy_pads.lef
 read_liberty Nangate45/Nangate45_typ.lib
 read_verilog simple_test_hier.v
 link test_16_sinks -hier
 
 initialize_floorplan -die_area "0 0 40 1200"   -core_area "0 0 40 1200" -site FreePDK45_38x28_10R_NP_162NW_34O
-make_io_sites -horizontal_site IOSITE -vertical_site IOSITE -corner_site IOSITE -offset 15
+#make_io_sites -horizontal_site IOSITE -vertical_site IOSITE -corner_site IOSITE -offset 15
 
 source Nangate45/Nangate45.vars
 source Nangate45/Nangate45.rc
 
-place_pad -master PADCELL_SIG_V -row IO_EAST -location 500 "clk"
+#place_pad -master PADCELL_SIG_V -row IO_EAST -location 500 "clk"
 
 global_placement -skip_nesterov_place 
 detailed_placement
diff --git a/src/cts/test/simple_test_hier_out.vok b/src/cts/test/simple_test_hier_out.vok
index 7e7fe595ab5..a6687933212 100644
--- a/src/cts/test/simple_test_hier_out.vok
+++ b/src/cts/test/simple_test_hier_out.vok
@@ -9,7 +9,6 @@ module test_16_sinks (clk);
     .Z(clknet_1_0__leaf_clk));
  CLKBUF_X3 clkbuf_0_clk (.A(clk),
     .Z(clknet_0_clk));
- PADCELL_SIG_V clk ();
  flop_pair U1 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk),
     .clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk),
     .origclk(clk));