diff --git a/src/dbSta/include/db_sta/dbNetwork.hh b/src/dbSta/include/db_sta/dbNetwork.hh index 2f59cd234f7..31fd109d186 100644 --- a/src/dbSta/include/db_sta/dbNetwork.hh +++ b/src/dbSta/include/db_sta/dbNetwork.hh @@ -132,6 +132,7 @@ class dbNetwork : public ConcreteNetwork dbNet* staToDb(const Net* net) const; void staToDb(const Net* net, dbNet*& dnet, dbModNet*& modnet) const; + dbNet* flatNet(const Net* pin) const; dbBTerm* staToDb(const Term* term) const; void staToDb(const Term* term, @@ -239,6 +240,8 @@ class dbNetwork : public ConcreteNetwork Instance* instance(const Pin* pin) const override; Net* net(const Pin* pin) const override; void net(const Pin* pin, dbNet*& db_net, dbModNet*& db_modnet) const; + dbNet* flatNet(const Pin* pin) const; + Term* term(const Pin* pin) const override; PortDirection* direction(const Pin* pin) const override; VertexId vertexId(const Pin* pin) const override; diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc index f4becd8ddf8..e3c42b2cc84 100644 --- a/src/dbSta/src/dbNetwork.cc +++ b/src/dbSta/src/dbNetwork.cc @@ -1188,6 +1188,18 @@ Net* dbNetwork::net(const Pin* pin) const return nullptr; } +/* +Get the db net (flat net) for the pin +*/ + +dbNet* dbNetwork::flatNet(const Pin* pin) const +{ + dbNet* db_net; + dbModNet* db_modnet; + net(pin, db_net, db_modnet); + return db_net; +} + /* Get the dbnet or the moddbnet for a pin Sometimes a pin can be hooked to both and we want to expose them @@ -1234,16 +1246,7 @@ Term* dbNetwork::term(const Pin* pin) const return dbToStaTerm(bterm); } if (moditerm) { - // get the mod bterm - std::string port_name_str = moditerm->getName(); - size_t last_idx = port_name_str.find_last_of('/'); - if (last_idx != string::npos) { - port_name_str = port_name_str.substr(last_idx + 1); - } - const char* port_name = port_name_str.c_str(); - dbModInst* mod_inst = moditerm->getParent(); - dbModule* module = mod_inst->getMaster(); - dbModBTerm* mod_port = module->findModBTerm(port_name); + dbModBTerm* mod_port = moditerm->getChildModBTerm(); if (mod_port) { Term* ret = dbToStaTerm(mod_port); return ret; @@ -2193,6 +2196,18 @@ dbNet* dbNetwork::staToDb(const Net* net) const return reinterpret_cast(const_cast(net)); } +dbNet* dbNetwork::flatNet(const Net* net) const +{ + if (net) { + dbObject* obj = reinterpret_cast(const_cast(net)); + dbObjectType type = obj->getObjectType(); + if (type == odb::dbNetObj) { + return static_cast(obj); + } + } + return nullptr; +} + void dbNetwork::staToDb(const Net* net, dbNet*& dnet, dbModNet*& modnet) const { dnet = nullptr; @@ -2851,16 +2866,9 @@ void PinModuleConnection::operator()(const Pin* pin) (void) (bterm); (void) (modbterm); if (moditerm) { - std::string port_name_str = moditerm->getName(); - size_t last_idx = port_name_str.find_last_of('/'); - if (last_idx != string::npos) { - port_name_str = port_name_str.substr(last_idx + 1); - } - const char* port_name = port_name_str.c_str(); - dbModInst* mod_inst = moditerm->getParent(); - dbModule* module = mod_inst->getMaster(); - if (module == target_module_) { - dest_modbterm_ = module->findModBTerm(port_name); + dbModBTerm* modbterm = moditerm->getChildModBTerm(); + if (modbterm->getParent() == target_module_) { + dest_modbterm_ = modbterm; } } } diff --git a/src/dbSta/src/dbReadVerilog.cc b/src/dbSta/src/dbReadVerilog.cc index 0aa3dd7d882..6b657699386 100644 --- a/src/dbSta/src/dbReadVerilog.cc +++ b/src/dbSta/src/dbReadVerilog.cc @@ -430,13 +430,29 @@ void Verilog2db::makeDbModule( } } module->getModBTerms().reverse(); - // make the instance iterms + + // make the instance iterms and set up their reference + // to the child ports (dbModBTerms). + InstancePinIterator* ip_iter = network_->pinIterator(inst); while (ip_iter->hasNext()) { Pin* cur_pin = ip_iter->next(); std::string pin_name_string = network_->portName(cur_pin); + // + // we do not need to store the pin names.. But they are + // assumed to exist in the STA world. + // dbModITerm* moditerm = dbModITerm::create(modinst, pin_name_string.c_str()); + dbModBTerm* modbterm; + std::string port_name_str = pin_name_string; + size_t last_idx = port_name_str.find_last_of('/'); + if (last_idx != string::npos) { + port_name_str = port_name_str.substr(last_idx + 1); + } + dbModule* module = modinst->getMaster(); + modbterm = module->findModBTerm(port_name_str.c_str()); + moditerm->setChildModBTerm(modbterm); (void) moditerm; debugPrint(logger_, utl::ODB, diff --git a/src/odb/include/odb/db.h b/src/odb/include/odb/db.h index 4e35dfb6d14..178322f23b2 100644 --- a/src/odb/include/odb/db.h +++ b/src/odb/include/odb/db.h @@ -8152,7 +8152,7 @@ class dbModNet : public dbObject dbSet getBTerms(); const char* getName() const; - void reName(const char* new_name); + void rename(const char* new_name); static dbModNet* getModNet(dbBlock* block, uint id); static dbModNet* create(dbModule* parentModule, const char* name); static void destroy(dbModNet*); diff --git a/src/odb/src/db/dbJournal.cpp b/src/odb/src/db/dbJournal.cpp index d2651f40683..281bbc20007 100644 --- a/src/odb/src/db/dbJournal.cpp +++ b/src/odb/src/db/dbJournal.cpp @@ -1634,7 +1634,7 @@ void dbJournal::undo_connectObject() dbITerm* iterm = dbITerm::getITerm(_block, iterm_id); uint net_id; _log.pop(net_id); - // disconnects everything modnet and bnet) + // disconnects everything: modnet and dbnet iterm->disconnect(); break; } diff --git a/src/odb/src/db/dbModNet.cpp b/src/odb/src/db/dbModNet.cpp index 211bc412547..a4c22f17581 100644 --- a/src/odb/src/db/dbModNet.cpp +++ b/src/odb/src/db/dbModNet.cpp @@ -230,13 +230,14 @@ const char* dbModNet::getName() const // // Support for renaming hierarchical nets // -void dbModNet::reName(const char* new_name) +void dbModNet::rename(const char* new_name) { _dbModNet* obj = (_dbModNet*) this; - delete (obj->_name); - obj->_name = strdup(new_name); _dbBlock* block = (_dbBlock*) obj->getOwner(); _dbModule* parent = block->_module_tbl->getPtr(obj->_parent); + parent->_modnet_hash.erase(obj->_name); + free(obj->_name); + obj->_name = strdup(new_name); parent->_modnet_hash[new_name] = obj->getOID(); } diff --git a/src/rsz/src/EstimateWireParasitics.cc b/src/rsz/src/EstimateWireParasitics.cc index 1e3f722778b..6df73debb03 100644 --- a/src/rsz/src/EstimateWireParasitics.cc +++ b/src/rsz/src/EstimateWireParasitics.cc @@ -743,10 +743,7 @@ bool Resizer::isPad(const Instance* inst) const void Resizer::parasiticsInvalid(const Net* net) { - odb::dbNet* db_net = nullptr; - odb::dbModNet* db_modnet = nullptr; - db_network_->staToDb(net, db_net, db_modnet); - + odb::dbNet* db_net = db_network_->flatNet(net); if (haveEstimatedParasitics()) { debugPrint(logger_, RSZ, @@ -754,7 +751,7 @@ void Resizer::parasiticsInvalid(const Net* net) 2, "parasitics invalid {}", network_->pathName(net)); - parasitics_invalid_.insert(net); + parasitics_invalid_.insert(db_network_->dbToSta(db_net)); } } diff --git a/src/rsz/src/OdbCallBack.cc b/src/rsz/src/OdbCallBack.cc index 4e0dc402484..9a6c44319e0 100644 --- a/src/rsz/src/OdbCallBack.cc +++ b/src/rsz/src/OdbCallBack.cc @@ -150,10 +150,8 @@ void OdbCallBack::inDbInstSwapMasterAfter(dbInst* inst) while (pin_iter->hasNext()) { Pin* pin = pin_iter->next(); Net* net = network_->net(pin); - // we can only update parasitics for low level net - odb::dbNet* db_net = nullptr; - odb::dbModNet* db_modnet = nullptr; - db_network_->staToDb(net, db_net, db_modnet); + // we can only update parasitics for flat net + odb::dbNet* db_net = db_network_->flatNet(net); resizer_->parasiticsInvalid(db_network_->dbToSta(db_net)); } } diff --git a/src/rsz/src/Rebuffer.cc b/src/rsz/src/Rebuffer.cc index 0e81fe878f0..3bdabb4b392 100644 --- a/src/rsz/src/Rebuffer.cc +++ b/src/rsz/src/Rebuffer.cc @@ -145,7 +145,7 @@ int RepairSetup::rebuffer(const Pin* drvr_pin) //(the dbNet name now exposed is the same as the modnet name) // so we uniquify the modnet name std::string new_name = resizer_->makeUniqueNetName(); - db_modnet->reName(new_name.c_str()); + db_modnet->rename(new_name.c_str()); } inserted_buffer_count = rebufferTopDown(best_option, diff --git a/src/rsz/src/RepairSetup.cc b/src/rsz/src/RepairSetup.cc index 0b559644b14..839d657768d 100644 --- a/src/rsz/src/RepairSetup.cc +++ b/src/rsz/src/RepairSetup.cc @@ -56,13 +56,6 @@ #include "sta/VerilogWriter.hh" #include "utl/Logger.h" -/*void -writeVerilog(const char *filename, - bool sort, - bool include_pwr_gnd, - sta::CellSeq *remove_cells, - sta::Network *network); -*/ namespace rsz { using std::max; diff --git a/src/rsz/src/SteinerTree.cc b/src/rsz/src/SteinerTree.cc index 77ccfa9e422..eb78db41aa4 100644 --- a/src/rsz/src/SteinerTree.cc +++ b/src/rsz/src/SteinerTree.cc @@ -69,16 +69,8 @@ SteinerTree* Resizer::makeSteinerTree(const Pin* drvr_pin) /* Handle hierarchy. Make sure all traversal on dbNets. */ - odb::dbITerm* iterm; - odb::dbBTerm* bterm; - odb::dbModITerm* moditerm; - odb::dbModBTerm* modbterm; - - db_network_->staToDb(drvr_pin, iterm, bterm, moditerm, modbterm); - odb::dbNet* db_net; - odb::dbModNet* db_mod_net; - db_network_->net(drvr_pin, db_net, db_mod_net); + db_net = db_network_->flatNet(drvr_pin); Net* net = network_->isTopLevelPort(drvr_pin)