Regression fixes: propagation of bus ports. Signed-off-by: Andy Fox <…

…[email protected]> Signed-off-by: andyfox-rushc <[email protected]>
andyfox-rushc · May 2, 2024 · a930c60 · a930c60
1 parent 47c17a3
commit a930c60
Show file tree

Hide file tree

Showing 2 changed files with 2 additions and 8 deletions.
diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc
@@ -502,12 +502,8 @@ void dbNetwork::makeVerilogCell(Library* library, dbModInst* mod_inst)
       }
     } else if (ccport->isBundle()) {
       ;
-      //      printf("Bundle %s\n",
-      //             reinterpret_cast<const ConcretePort*>(cport)->name());
     } else if (ccport->isBusBit()) {
       ;
-      // printf("Busbit %s\n",
-      //             reinterpret_cast<const ConcretePort*>(cport)->name());
     } else {
       dbModBTerm* modbterm = name2modbterm[port_name];
       modbterm->staSetPort(cport);
@@ -530,9 +526,6 @@ Cell* dbNetwork::cell(const Instance* instance) const
   }
   if (mod_inst) {
     dbModule* master = mod_inst->getMaster();
-#ifdef DEBUG_DBNWK
-    printf("Mod inst Master is %s\n", master->getName());
-#endif
     // look up the cell in the verilog library.
     return dbToSta(master);
   }

diff --git a/src/dbSta/src/dbReadVerilog.cc b/src/dbSta/src/dbReadVerilog.cc
@@ -266,10 +266,11 @@ void Verilog2db::recordBusPortsOrder()
     Port* port = bus_iter->next();
     if (network_->isBus(port)) {
       const char* port_name = network_->name(port);
+      const char* cell_name = network_->name(top_cell);
       int from = network_->fromIndex(port);
       int to = network_->toIndex(port);
       string key = "bus_msb_first ";
-      key += port_name;
+      key = key + port_name + " " + cell_name;
       odb::dbBoolProperty::create(block_, key.c_str(), from > to);
     }
   }