From a930c60aa72297c0882da88c69f309d84c5267f5 Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Wed, 1 May 2024 22:36:49 -0700 Subject: [PATCH] Regression fixes: propagation of bus ports. Signed-off-by: Andy Fox Signed-off-by: andyfox-rushc --- src/dbSta/src/dbNetwork.cc | 7 ------- src/dbSta/src/dbReadVerilog.cc | 3 ++- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc index 9350dd15fa4..278fdbcfb9a 100644 --- a/src/dbSta/src/dbNetwork.cc +++ b/src/dbSta/src/dbNetwork.cc @@ -502,12 +502,8 @@ void dbNetwork::makeVerilogCell(Library* library, dbModInst* mod_inst) } } else if (ccport->isBundle()) { ; - // printf("Bundle %s\n", - // reinterpret_cast(cport)->name()); } else if (ccport->isBusBit()) { ; - // printf("Busbit %s\n", - // reinterpret_cast(cport)->name()); } else { dbModBTerm* modbterm = name2modbterm[port_name]; modbterm->staSetPort(cport); @@ -530,9 +526,6 @@ Cell* dbNetwork::cell(const Instance* instance) const } if (mod_inst) { dbModule* master = mod_inst->getMaster(); -#ifdef DEBUG_DBNWK - printf("Mod inst Master is %s\n", master->getName()); -#endif // look up the cell in the verilog library. return dbToSta(master); } diff --git a/src/dbSta/src/dbReadVerilog.cc b/src/dbSta/src/dbReadVerilog.cc index 5649a90f892..90e2525fd91 100644 --- a/src/dbSta/src/dbReadVerilog.cc +++ b/src/dbSta/src/dbReadVerilog.cc @@ -266,10 +266,11 @@ void Verilog2db::recordBusPortsOrder() Port* port = bus_iter->next(); if (network_->isBus(port)) { const char* port_name = network_->name(port); + const char* cell_name = network_->name(top_cell); int from = network_->fromIndex(port); int to = network_->toIndex(port); string key = "bus_msb_first "; - key += port_name; + key = key + port_name + " " + cell_name; odb::dbBoolProperty::create(block_, key.c_str(), from > to); } }