From 3b5802b5198b5a4b0a1841287f304dd42a9f6697 Mon Sep 17 00:00:00 2001 From: luis201420 Date: Fri, 22 Nov 2024 22:51:25 +0000 Subject: [PATCH 01/98] ant: Initialize map keys to prevent data races Signed-off-by: luis201420 --- src/ant/src/AntennaChecker.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/ant/src/AntennaChecker.cc b/src/ant/src/AntennaChecker.cc index b982234ef3d..d8199cc0985 100644 --- a/src/ant/src/AntennaChecker.cc +++ b/src/ant/src/AntennaChecker.cc @@ -1111,6 +1111,7 @@ int AntennaChecker::checkAntennas(odb::dbNet* net, for (odb::dbNet* net : block_->getNets()) { if (!net->isSpecial()) { nets_.push_back(net); + net_to_report_[net]; } } omp_set_num_threads(num_threads); From f2e77f975d317e60cebd221fa545267c8b1948d0 Mon Sep 17 00:00:00 2001 From: Felipe Garay Date: Thu, 8 Aug 2024 14:59:28 -0700 Subject: [PATCH 02/98] dft: refactor clock domain Now we don't force dependencies on scan architect when using ClockDomain Signed-off-by: Felipe Garay --- src/dft/src/architect/CMakeLists.txt | 1 + src/dft/src/architect/ScanArchitect.cpp | 1 + src/dft/src/clock_domain/CMakeLists.txt | 17 +++++- src/dft/src/clock_domain/ClockDomain.cpp | 19 ------- src/dft/src/clock_domain/ClockDomain.hh | 20 ------- src/dft/src/clock_domain/ClockDomainHash.cpp | 56 ++++++++++++++++++++ src/dft/src/clock_domain/ClockDomainHash.hh | 56 ++++++++++++++++++++ 7 files changed, 129 insertions(+), 41 deletions(-) create mode 100644 src/dft/src/clock_domain/ClockDomainHash.cpp create mode 100644 src/dft/src/clock_domain/ClockDomainHash.hh diff --git a/src/dft/src/architect/CMakeLists.txt b/src/dft/src/architect/CMakeLists.txt index 1d8f0ca12a3..556071c6b29 100644 --- a/src/dft/src/architect/CMakeLists.txt +++ b/src/dft/src/architect/CMakeLists.txt @@ -10,6 +10,7 @@ target_link_libraries(dft_architect_lib PRIVATE dft_base_scan_cell_lib dft_clock_domain_lib + dft_clock_domain_hash_lib dft_config_lib dft_utils_scan_pin_lib ) diff --git a/src/dft/src/architect/ScanArchitect.cpp b/src/dft/src/architect/ScanArchitect.cpp index 33bc4cccca9..faa6a519714 100644 --- a/src/dft/src/architect/ScanArchitect.cpp +++ b/src/dft/src/architect/ScanArchitect.cpp @@ -33,6 +33,7 @@ #include "ScanArchitect.hh" #include "ClockDomain.hh" +#include "ClockDomainHash.hh" #include "ScanArchitectHeuristic.hh" namespace dft { diff --git a/src/dft/src/clock_domain/CMakeLists.txt b/src/dft/src/clock_domain/CMakeLists.txt index 0d902f87477..999d3e7eada 100644 --- a/src/dft/src/clock_domain/CMakeLists.txt +++ b/src/dft/src/clock_domain/CMakeLists.txt @@ -2,14 +2,27 @@ add_library(dft_clock_domain_lib # Keep sorted ClockDomain.cpp ) - target_include_directories(dft_clock_domain_lib PUBLIC ${CMAKE_CURRENT_LIST_DIR} ) - target_link_libraries(dft_clock_domain_lib PRIVATE utl_lib dft_config_lib ) + +add_library(dft_clock_domain_hash_lib + # Keep sorted + ClockDomainHash.cpp +) +target_include_directories(dft_clock_domain_hash_lib + PUBLIC + ${CMAKE_CURRENT_LIST_DIR} +) +target_link_libraries(dft_clock_domain_hash_lib + PRIVATE + utl_lib + dft_config_lib + dft_clock_domain_lib +) diff --git a/src/dft/src/clock_domain/ClockDomain.cpp b/src/dft/src/clock_domain/ClockDomain.cpp index dbabacd0e06..17ccff4489d 100644 --- a/src/dft/src/clock_domain/ClockDomain.cpp +++ b/src/dft/src/clock_domain/ClockDomain.cpp @@ -34,25 +34,6 @@ namespace dft { -std::function GetClockDomainHashFn( - const ScanArchitectConfig& config, - utl::Logger* logger) -{ - switch (config.getClockMixing()) { - // For NoMix, every clock domain is different - case ScanArchitectConfig::ClockMixing::NoMix: - return [](const ClockDomain& clock_domain) { - return std::hash{}(clock_domain.getClockName()) - ^ std::hash{}(clock_domain.getClockEdge()); - }; - case ScanArchitectConfig::ClockMixing::ClockMix: - return [](const ClockDomain& clock_domain) { return 1; }; - default: - // Not implemented - logger->error(utl::DFT, 4, "Clock mix config requested is not supported"); - } -} - ClockDomain::ClockDomain(const std::string& clock_name, ClockEdge clock_edge) : clock_name_(clock_name), clock_edge_(clock_edge) { diff --git a/src/dft/src/clock_domain/ClockDomain.hh b/src/dft/src/clock_domain/ClockDomain.hh index 30235306edf..d8e0bc07a0e 100644 --- a/src/dft/src/clock_domain/ClockDomain.hh +++ b/src/dft/src/clock_domain/ClockDomain.hh @@ -31,12 +31,7 @@ // POSSIBILITY OF SUCH DAMAGE. #pragma once -#include -#include #include -#include - -#include "ScanArchitectConfig.hh" namespace dft { @@ -67,19 +62,4 @@ class ClockDomain ClockEdge clock_edge_; }; -// Depending on the ScanArchitectConfig's clock mixing setting, there are -// different ways to calculate the hash of the clock domain. -// -// For No Mix clock, we will generate a different hash value for all the clock -// domains. -// -// If we want to mix all the clocks, then the hash will be the same for all the -// clock doamins. -// -// We refer to the generated hash from a ClockDomain as Hash Domain. -// -std::function GetClockDomainHashFn( - const ScanArchitectConfig& config, - utl::Logger* logger); - } // namespace dft diff --git a/src/dft/src/clock_domain/ClockDomainHash.cpp b/src/dft/src/clock_domain/ClockDomainHash.cpp new file mode 100644 index 00000000000..159308942bf --- /dev/null +++ b/src/dft/src/clock_domain/ClockDomainHash.cpp @@ -0,0 +1,56 @@ +/////////////////////////////////////////////////////////////////////////////// +// BSD 3-Clause License +// +// Copyright (c) 2024, Google LLC +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#include "ClockDomainHash.hh" + +namespace dft { + +std::function GetClockDomainHashFn( + const ScanArchitectConfig& config, + utl::Logger* logger) +{ + switch (config.getClockMixing()) { + // For NoMix, every clock domain is different + case ScanArchitectConfig::ClockMixing::NoMix: + return [](const ClockDomain& clock_domain) { + return std::hash{}(clock_domain.getClockName()) + ^ std::hash{}(clock_domain.getClockEdge()); + }; + case ScanArchitectConfig::ClockMixing::ClockMix: + return [](const ClockDomain& clock_domain) { return 1; }; + default: + // Not implemented + logger->error(utl::DFT, 4, "Clock mix config requested is not supported"); + } +} + +} // namespace dft diff --git a/src/dft/src/clock_domain/ClockDomainHash.hh b/src/dft/src/clock_domain/ClockDomainHash.hh new file mode 100644 index 00000000000..293fe4a1c8d --- /dev/null +++ b/src/dft/src/clock_domain/ClockDomainHash.hh @@ -0,0 +1,56 @@ +/////////////////////////////////////////////////////////////////////////////// +// BSD 3-Clause License +// +// Copyright (c) 2024, Google LLC +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +#pragma once + +#include + +#include "ClockDomain.hh" +#include "ScanArchitectConfig.hh" + +namespace dft { + +// Depending on the ScanArchitectConfig's clock mixing setting, there are +// different ways to calculate the hash of the clock domain. +// +// For No Mix clock, we will generate a different hash value for all the clock +// domains. +// +// If we want to mix all the clocks, then the hash will be the same for all the +// clock doamins. +// +// We refer to the generated hash from a ClockDomain as Hash Domain. +// +std::function GetClockDomainHashFn( + const ScanArchitectConfig& config, + utl::Logger* logger); + +} // namespace dft From 7d3c754815badc244f0e0eb55b5199cbd17f75f3 Mon Sep 17 00:00:00 2001 From: luis201420 Date: Mon, 25 Nov 2024 03:04:26 +0000 Subject: [PATCH 03/98] ant: cleaning up net reports Signed-off-by: luis201420 --- src/ant/src/AntennaChecker.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ant/src/AntennaChecker.cc b/src/ant/src/AntennaChecker.cc index d8199cc0985..23c13d7a669 100644 --- a/src/ant/src/AntennaChecker.cc +++ b/src/ant/src/AntennaChecker.cc @@ -1055,6 +1055,7 @@ Violations AntennaChecker::getAntennaViolations(odb::dbNet* net, pin_violation_count, antenna_violations); + net_to_report_.clear(); return antenna_violations; } @@ -1111,7 +1112,6 @@ int AntennaChecker::checkAntennas(odb::dbNet* net, for (odb::dbNet* net : block_->getNets()) { if (!net->isSpecial()) { nets_.push_back(net); - net_to_report_[net]; } } omp_set_num_threads(num_threads); @@ -1145,7 +1145,7 @@ int AntennaChecker::checkAntennas(odb::dbNet* net, writeReport(report_file, verbose); report_file.close(); } - net_to_report_.clear(); + //net_to_report_.clear(); if (use_grt_routes) { global_route_source_->destroyNetWires(); From dcee9d590bf9ce5bf5dabde2597a5913c282cab6 Mon Sep 17 00:00:00 2001 From: luis201420 Date: Mon, 25 Nov 2024 03:07:01 +0000 Subject: [PATCH 04/98] ant: adding debug print Signed-off-by: luis201420 --- src/ant/src/AntennaChecker.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/ant/src/AntennaChecker.cc b/src/ant/src/AntennaChecker.cc index 23c13d7a669..0b737e65afd 100644 --- a/src/ant/src/AntennaChecker.cc +++ b/src/ant/src/AntennaChecker.cc @@ -1063,6 +1063,7 @@ int AntennaChecker::checkAntennas(odb::dbNet* net, const int num_threads, bool verbose) { + printf("Start to checkAntenna\n"); net_to_report_.clear(); initAntennaRules(); From 36a67591666da5536339b14a7c1fad89c38fc697 Mon Sep 17 00:00:00 2001 From: luis201420 Date: Wed, 27 Nov 2024 04:10:26 +0000 Subject: [PATCH 05/98] ant: Protect map access with mutex Signed-off-by: luis201420 --- src/ant/include/ant/AntennaChecker.hh | 17 ++++-- src/ant/src/AntennaChecker.cc | 74 ++++++++++++++++----------- 2 files changed, 55 insertions(+), 36 deletions(-) diff --git a/src/ant/include/ant/AntennaChecker.hh b/src/ant/include/ant/AntennaChecker.hh index 3f09b2d6468..2a8cf4f79eb 100644 --- a/src/ant/include/ant/AntennaChecker.hh +++ b/src/ant/include/ant/AntennaChecker.hh @@ -34,6 +34,7 @@ #include #include #include +#include #include "odb/db.h" #include "odb/dbWireGraph.h" @@ -198,7 +199,8 @@ class AntennaChecker NodeInfo& node_info, float ratio_margin, bool verbose, - bool report); + bool report, + ViolationReport& net_report); void writeReport(std::ofstream& report_file, bool verbose); void printReport(); int checkGates(odb::dbNet* db_net, @@ -216,23 +218,27 @@ class AntennaChecker NodeInfo& info, float ratio_margin, bool verbose, - bool report); + bool report, + ViolationReport& net_report); bool checkPSR(odb::dbNet* db_net, odb::dbTechLayer* tech_layer, NodeInfo& info, float ratio_margin, bool verbose, - bool report); + bool report, + ViolationReport& net_report); bool checkCAR(odb::dbNet* db_net, odb::dbTechLayer* tech_layer, const NodeInfo& info, bool verbose, - bool report); + bool report, + ViolationReport& net_report); bool checkCSR(odb::dbNet* db_net, odb::dbTechLayer* tech_layer, const NodeInfo& info, bool verbose, - bool report); + bool report, + ViolationReport& net_report); odb::dbDatabase* db_{nullptr}; odb::dbBlock* block_{nullptr}; @@ -243,6 +249,7 @@ class AntennaChecker std::string report_file_name_; std::vector nets_; std::map net_to_report_; + std::mutex mapMutex; // consts static constexpr int max_diode_count_per_gate = 10; }; diff --git a/src/ant/src/AntennaChecker.cc b/src/ant/src/AntennaChecker.cc index 0b737e65afd..a3afd9de279 100644 --- a/src/ant/src/AntennaChecker.cc +++ b/src/ant/src/AntennaChecker.cc @@ -527,7 +527,8 @@ bool AntennaChecker::checkPAR(odb::dbNet* db_net, NodeInfo& info, const float ratio_margin, bool verbose, - bool report) + bool report, + ViolationReport& net_report) { // get rules const odb::dbTechLayerAntennaRule* antenna_rule @@ -554,7 +555,7 @@ bool AntennaChecker::checkPAR(odb::dbNet* db_net, info.PAR, PAR_ratio, violation ? "(VIOLATED)" : ""); - net_to_report_.at(db_net).report += par_report + "\n"; + net_report.report += par_report + "\n"; } } else { if (diff_PAR_PWL_ratio != 0) { @@ -570,7 +571,7 @@ bool AntennaChecker::checkPAR(odb::dbNet* db_net, info.diff_PAR, diff_PAR_PWL_ratio, violation ? "(VIOLATED)" : ""); - net_to_report_.at(db_net).report += diff_par_report + "\n"; + net_report.report += diff_par_report + "\n"; } } return violation; @@ -581,7 +582,8 @@ bool AntennaChecker::checkPSR(odb::dbNet* db_net, NodeInfo& info, const float ratio_margin, bool verbose, - bool report) + bool report, + ViolationReport& net_report) { // get rules const odb::dbTechLayerAntennaRule* antenna_rule @@ -609,7 +611,7 @@ bool AntennaChecker::checkPSR(odb::dbNet* db_net, info.PSR, PSR_ratio, violation ? "(VIOLATED)" : ""); - net_to_report_.at(db_net).report += psr_report + "\n"; + net_report.report += psr_report + "\n"; } } else { if (diff_PSR_PWL_ratio != 0) { @@ -625,7 +627,7 @@ bool AntennaChecker::checkPSR(odb::dbNet* db_net, info.diff_PSR, diff_PSR_PWL_ratio, violation ? "(VIOLATED)" : ""); - net_to_report_.at(db_net).report += diff_psr_report + "\n"; + net_report.report += diff_psr_report + "\n"; } } return violation; @@ -635,7 +637,8 @@ bool AntennaChecker::checkCAR(odb::dbNet* db_net, odb::dbTechLayer* tech_layer, const NodeInfo& info, bool verbose, - bool report) + bool report, + ViolationReport& net_report) { // get rules const odb::dbTechLayerAntennaRule* antenna_rule @@ -658,7 +661,7 @@ bool AntennaChecker::checkCAR(odb::dbNet* db_net, info.CAR, CAR_ratio, violation ? "(VIOLATED)" : ""); - net_to_report_.at(db_net).report += car_report + "\n"; + net_report.report += car_report + "\n"; } } else { if (diff_CAR_PWL_ratio != 0) { @@ -672,7 +675,7 @@ bool AntennaChecker::checkCAR(odb::dbNet* db_net, info.diff_CAR, diff_CAR_PWL_ratio, violation ? "(VIOLATED)" : ""); - net_to_report_.at(db_net).report += diff_car_report + "\n"; + net_report.report += diff_car_report + "\n"; } } return violation; @@ -682,7 +685,8 @@ bool AntennaChecker::checkCSR(odb::dbNet* db_net, odb::dbTechLayer* tech_layer, const NodeInfo& info, bool verbose, - bool report) + bool report, + ViolationReport& net_report) { // get rules const odb::dbTechLayerAntennaRule* antenna_rule @@ -705,7 +709,7 @@ bool AntennaChecker::checkCSR(odb::dbNet* db_net, info.CSR, CSR_ratio, violation ? "(VIOLATED)" : ""); - net_to_report_.at(db_net).report += csr_report + "\n"; + net_report.report += csr_report + "\n"; } } else { if (diff_CSR_PWL_ratio != 0) { @@ -719,7 +723,7 @@ bool AntennaChecker::checkCSR(odb::dbNet* db_net, info.diff_CSR, diff_CSR_PWL_ratio, violation ? "(VIOLATED)" : ""); - net_to_report_.at(db_net).report += diff_csr_report + "\n"; + net_report.report += diff_csr_report + "\n"; } } return violation; @@ -730,15 +734,16 @@ bool AntennaChecker::checkRatioViolations(odb::dbNet* db_net, NodeInfo& node_info, const float ratio_margin, bool verbose, - bool report) + bool report, + ViolationReport& net_report) { bool node_has_violation - = checkPAR(db_net, layer, node_info, ratio_margin, verbose, report) - || checkCAR(db_net, layer, node_info, verbose, report); + = checkPAR(db_net, layer, node_info, ratio_margin, verbose, report, net_report) + || checkCAR(db_net, layer, node_info, verbose, report, net_report); if (layer->getRoutingLevel() != 0) { bool psr_violation - = checkPSR(db_net, layer, node_info, ratio_margin, verbose, report); - bool csr_violation = checkCSR(db_net, layer, node_info, verbose, report); + = checkPSR(db_net, layer, node_info, ratio_margin, verbose, report, net_report); + bool csr_violation = checkCSR(db_net, layer, node_info, verbose, report, net_report); node_has_violation = node_has_violation || psr_violation || csr_violation; } @@ -776,8 +781,9 @@ int AntennaChecker::checkGates(odb::dbNet* db_net, GateToViolationLayers gates_with_violations; + ViolationReport net_report; std::string net_name = fmt::format("Net: {}", db_net->getConstName()); - net_to_report_.at(db_net).report += net_name + "\n"; + net_report.report += net_name + "\n"; for (auto& [node, layer_to_node] : gate_info) { bool pin_has_violation = false; @@ -787,30 +793,33 @@ int AntennaChecker::checkGates(odb::dbNet* db_net, node->getInst()->getConstName(), mterm->getConstName(), mterm->getMaster()->getConstName()); - net_to_report_.at(db_net).report += pin_name + "\n"; + net_report.report += pin_name + "\n"; for (auto& [layer, node_info] : layer_to_node) { if (layer->hasDefaultAntennaRule()) { std::string layer_name = fmt::format(" Layer: {}", layer->getConstName()); - net_to_report_.at(db_net).report += layer_name + "\n"; + net_report.report += layer_name + "\n"; bool node_has_violation = checkRatioViolations( - db_net, layer, node_info, ratio_margin, verbose, true); + db_net, layer, node_info, ratio_margin, verbose, true, net_report); - net_to_report_.at(db_net).report += "\n"; + net_report.report += "\n"; if (node_has_violation) { pin_has_violation = true; gates_with_violations[node].insert(layer); - net_to_report_.at(db_net).violated = true; + net_report.violated = true; } } } if (pin_has_violation) { pin_violation_count++; } - net_to_report_.at(db_net).report += "\n"; + net_report.report += "\n"; } + // Write report on map + std::lock_guard lock(mapMutex); + net_to_report_.at(db_net) = net_report; std::map> pin_added; // if checkGates is used by repair antennas @@ -833,13 +842,15 @@ int AntennaChecker::checkGates(odb::dbNet* db_net, violation_info, ratio_margin, false, - false); + false, + net_report); bool psr_violation = checkPSR(db_net, violation_layer, violation_info, ratio_margin, false, - false); + false, + net_report); bool violated = par_violation || psr_violation; double excess_ratio = 1.0; if (violated) { @@ -860,13 +871,15 @@ int AntennaChecker::checkGates(odb::dbNet* db_net, violation_info, ratio_margin, false, - false); + false, + net_report); psr_violation = checkPSR(db_net, violation_layer, violation_info, ratio_margin, false, - false); + false, + net_report); if (diode_count_per_gate > max_diode_count_per_gate) { debugPrint(logger_, ANT, @@ -892,9 +905,9 @@ int AntennaChecker::checkGates(odb::dbNet* db_net, } bool car_violation - = checkCAR(db_net, violation_layer, violation_info, false, false); + = checkCAR(db_net, violation_layer, violation_info, false, false, net_report); bool csr_violation - = checkCSR(db_net, violation_layer, violation_info, false, false); + = checkCSR(db_net, violation_layer, violation_info, false, false, net_report); // naive approach for cumulative area violations. here, all the pins // of the net are included, and placing one diode per pin is not the @@ -1146,7 +1159,6 @@ int AntennaChecker::checkAntennas(odb::dbNet* net, writeReport(report_file, verbose); report_file.close(); } - //net_to_report_.clear(); if (use_grt_routes) { global_route_source_->destroyNetWires(); From 6bb28a68862b2cce5073dd72cc42067d5502b3ca Mon Sep 17 00:00:00 2001 From: luis201420 Date: Fri, 29 Nov 2024 17:04:11 +0000 Subject: [PATCH 06/98] ant: Protect map access with mutex Signed-off-by: luis201420 --- src/ant/src/AntennaChecker.cc | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/src/ant/src/AntennaChecker.cc b/src/ant/src/AntennaChecker.cc index a3afd9de279..7933591a704 100644 --- a/src/ant/src/AntennaChecker.cc +++ b/src/ant/src/AntennaChecker.cc @@ -100,6 +100,7 @@ void AntennaChecker::initAntennaRules() odb::dbTech* tech = db_->getTech(); // initialize nets_to_report_ with all nets to avoid issues with // multithreading + std::lock_guard lock(mapMutex); if (net_to_report_.empty()) { for (odb::dbNet* net : block_->getNets()) { if (!net->isSpecial()) { @@ -752,6 +753,7 @@ bool AntennaChecker::checkRatioViolations(odb::dbNet* db_net, void AntennaChecker::writeReport(std::ofstream& report_file, bool verbose) { + std::lock_guard lock(mapMutex); for (const auto& [net, violation_report] : net_to_report_) { if (verbose || violation_report.violated) { report_file << violation_report.report; @@ -761,6 +763,7 @@ void AntennaChecker::writeReport(std::ofstream& report_file, bool verbose) void AntennaChecker::printReport() { + std::lock_guard lock(mapMutex); for (const auto& [net, violation_report] : net_to_report_) { if (violation_report.violated) { logger_->report("{}", violation_report.report); @@ -818,8 +821,10 @@ int AntennaChecker::checkGates(odb::dbNet* db_net, net_report.report += "\n"; } // Write report on map - std::lock_guard lock(mapMutex); - net_to_report_.at(db_net) = net_report; + { + std::lock_guard lock(mapMutex); + net_to_report_.at(db_net) = net_report; + } std::map> pin_added; // if checkGates is used by repair antennas @@ -1050,8 +1055,11 @@ Violations AntennaChecker::getAntennaViolations(odb::dbNet* net, } // for the case where the check_net_violation api is called directly - if (net_to_report_.find(net) == net_to_report_.end()) { - net_to_report_[net]; + { + std::lock_guard lock(mapMutex); + if (net_to_report_.find(net) == net_to_report_.end()) { + net_to_report_[net]; + } } int net_violation_count, pin_violation_count; @@ -1068,6 +1076,7 @@ Violations AntennaChecker::getAntennaViolations(odb::dbNet* net, pin_violation_count, antenna_violations); + std::lock_guard lock(mapMutex); net_to_report_.clear(); return antenna_violations; } @@ -1077,7 +1086,10 @@ int AntennaChecker::checkAntennas(odb::dbNet* net, bool verbose) { printf("Start to checkAntenna\n"); - net_to_report_.clear(); + { + std::lock_guard lock(mapMutex); + net_to_report_.clear(); + } initAntennaRules(); std::ofstream report_file; @@ -1145,6 +1157,7 @@ int AntennaChecker::checkAntennas(odb::dbNet* net, antenna_violations); } } +#pragma omp barrier if (verbose) { printReport(); From c5418cbd388d8b3c02a101372df4d8b5a3f98052 Mon Sep 17 00:00:00 2001 From: luis201420 Date: Mon, 2 Dec 2024 16:15:39 +0000 Subject: [PATCH 07/98] ant: avoiding using mutex Signed-off-by: luis201420 --- src/ant/src/AntennaChecker.cc | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/ant/src/AntennaChecker.cc b/src/ant/src/AntennaChecker.cc index 7933591a704..2841cad99ea 100644 --- a/src/ant/src/AntennaChecker.cc +++ b/src/ant/src/AntennaChecker.cc @@ -100,7 +100,7 @@ void AntennaChecker::initAntennaRules() odb::dbTech* tech = db_->getTech(); // initialize nets_to_report_ with all nets to avoid issues with // multithreading - std::lock_guard lock(mapMutex); + //std::lock_guard lock(mapMutex); if (net_to_report_.empty()) { for (odb::dbNet* net : block_->getNets()) { if (!net->isSpecial()) { @@ -753,7 +753,7 @@ bool AntennaChecker::checkRatioViolations(odb::dbNet* db_net, void AntennaChecker::writeReport(std::ofstream& report_file, bool verbose) { - std::lock_guard lock(mapMutex); + //std::lock_guard lock(mapMutex); for (const auto& [net, violation_report] : net_to_report_) { if (verbose || violation_report.violated) { report_file << violation_report.report; @@ -763,7 +763,7 @@ void AntennaChecker::writeReport(std::ofstream& report_file, bool verbose) void AntennaChecker::printReport() { - std::lock_guard lock(mapMutex); + //std::lock_guard lock(mapMutex); for (const auto& [net, violation_report] : net_to_report_) { if (violation_report.violated) { logger_->report("{}", violation_report.report); @@ -822,7 +822,7 @@ int AntennaChecker::checkGates(odb::dbNet* db_net, } // Write report on map { - std::lock_guard lock(mapMutex); + //std::lock_guard lock(mapMutex); net_to_report_.at(db_net) = net_report; } @@ -1056,7 +1056,7 @@ Violations AntennaChecker::getAntennaViolations(odb::dbNet* net, // for the case where the check_net_violation api is called directly { - std::lock_guard lock(mapMutex); + //std::lock_guard lock(mapMutex); if (net_to_report_.find(net) == net_to_report_.end()) { net_to_report_[net]; } @@ -1076,7 +1076,7 @@ Violations AntennaChecker::getAntennaViolations(odb::dbNet* net, pin_violation_count, antenna_violations); - std::lock_guard lock(mapMutex); + //std::lock_guard lock(mapMutex); net_to_report_.clear(); return antenna_violations; } @@ -1087,7 +1087,7 @@ int AntennaChecker::checkAntennas(odb::dbNet* net, { printf("Start to checkAntenna\n"); { - std::lock_guard lock(mapMutex); + //std::lock_guard lock(mapMutex); net_to_report_.clear(); } initAntennaRules(); From 8c08cd328d5c09b953ce4b77067cfefec53eeec1 Mon Sep 17 00:00:00 2001 From: luis201420 Date: Tue, 3 Dec 2024 02:46:19 +0000 Subject: [PATCH 08/98] ant: using only mutex to protect map access Signed-off-by: luis201420 --- src/ant/src/AntennaChecker.cc | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/ant/src/AntennaChecker.cc b/src/ant/src/AntennaChecker.cc index 2841cad99ea..1a4dc0ed8d1 100644 --- a/src/ant/src/AntennaChecker.cc +++ b/src/ant/src/AntennaChecker.cc @@ -100,7 +100,7 @@ void AntennaChecker::initAntennaRules() odb::dbTech* tech = db_->getTech(); // initialize nets_to_report_ with all nets to avoid issues with // multithreading - //std::lock_guard lock(mapMutex); + std::lock_guard lock(mapMutex); if (net_to_report_.empty()) { for (odb::dbNet* net : block_->getNets()) { if (!net->isSpecial()) { @@ -753,7 +753,7 @@ bool AntennaChecker::checkRatioViolations(odb::dbNet* db_net, void AntennaChecker::writeReport(std::ofstream& report_file, bool verbose) { - //std::lock_guard lock(mapMutex); + std::lock_guard lock(mapMutex); for (const auto& [net, violation_report] : net_to_report_) { if (verbose || violation_report.violated) { report_file << violation_report.report; @@ -763,7 +763,7 @@ void AntennaChecker::writeReport(std::ofstream& report_file, bool verbose) void AntennaChecker::printReport() { - //std::lock_guard lock(mapMutex); + std::lock_guard lock(mapMutex); for (const auto& [net, violation_report] : net_to_report_) { if (violation_report.violated) { logger_->report("{}", violation_report.report); @@ -822,7 +822,7 @@ int AntennaChecker::checkGates(odb::dbNet* db_net, } // Write report on map { - //std::lock_guard lock(mapMutex); + std::lock_guard lock(mapMutex); net_to_report_.at(db_net) = net_report; } @@ -1056,7 +1056,7 @@ Violations AntennaChecker::getAntennaViolations(odb::dbNet* net, // for the case where the check_net_violation api is called directly { - //std::lock_guard lock(mapMutex); + std::lock_guard lock(mapMutex); if (net_to_report_.find(net) == net_to_report_.end()) { net_to_report_[net]; } @@ -1076,7 +1076,7 @@ Violations AntennaChecker::getAntennaViolations(odb::dbNet* net, pin_violation_count, antenna_violations); - //std::lock_guard lock(mapMutex); + std::lock_guard lock(mapMutex); net_to_report_.clear(); return antenna_violations; } @@ -1087,7 +1087,7 @@ int AntennaChecker::checkAntennas(odb::dbNet* net, { printf("Start to checkAntenna\n"); { - //std::lock_guard lock(mapMutex); + std::lock_guard lock(mapMutex); net_to_report_.clear(); } initAntennaRules(); @@ -1157,7 +1157,7 @@ int AntennaChecker::checkAntennas(odb::dbNet* net, antenna_violations); } } -#pragma omp barrier +//#pragma omp barrier if (verbose) { printReport(); From 9a322807e5eb69f2fc084cb327e6c16d070fca72 Mon Sep 17 00:00:00 2001 From: luis201420 Date: Thu, 5 Dec 2024 15:50:58 +0000 Subject: [PATCH 09/98] ant: cleaning the code and adding clang-format Signed-off-by: luis201420 --- src/ant/include/ant/AntennaChecker.hh | 12 +++---- src/ant/src/AntennaChecker.cc | 45 ++++++++++++++++----------- 2 files changed, 33 insertions(+), 24 deletions(-) diff --git a/src/ant/include/ant/AntennaChecker.hh b/src/ant/include/ant/AntennaChecker.hh index 2a8cf4f79eb..e73c185a02b 100644 --- a/src/ant/include/ant/AntennaChecker.hh +++ b/src/ant/include/ant/AntennaChecker.hh @@ -32,9 +32,9 @@ #pragma once #include +#include #include #include -#include #include "odb/db.h" #include "odb/dbWireGraph.h" @@ -200,7 +200,7 @@ class AntennaChecker float ratio_margin, bool verbose, bool report, - ViolationReport& net_report); + ViolationReport& net_report); void writeReport(std::ofstream& report_file, bool verbose); void printReport(); int checkGates(odb::dbNet* db_net, @@ -219,26 +219,26 @@ class AntennaChecker float ratio_margin, bool verbose, bool report, - ViolationReport& net_report); + ViolationReport& net_report); bool checkPSR(odb::dbNet* db_net, odb::dbTechLayer* tech_layer, NodeInfo& info, float ratio_margin, bool verbose, bool report, - ViolationReport& net_report); + ViolationReport& net_report); bool checkCAR(odb::dbNet* db_net, odb::dbTechLayer* tech_layer, const NodeInfo& info, bool verbose, bool report, - ViolationReport& net_report); + ViolationReport& net_report); bool checkCSR(odb::dbNet* db_net, odb::dbTechLayer* tech_layer, const NodeInfo& info, bool verbose, bool report, - ViolationReport& net_report); + ViolationReport& net_report); odb::dbDatabase* db_{nullptr}; odb::dbBlock* block_{nullptr}; diff --git a/src/ant/src/AntennaChecker.cc b/src/ant/src/AntennaChecker.cc index 1a4dc0ed8d1..339d1d4b58b 100644 --- a/src/ant/src/AntennaChecker.cc +++ b/src/ant/src/AntennaChecker.cc @@ -529,7 +529,7 @@ bool AntennaChecker::checkPAR(odb::dbNet* db_net, const float ratio_margin, bool verbose, bool report, - ViolationReport& net_report) + ViolationReport& net_report) { // get rules const odb::dbTechLayerAntennaRule* antenna_rule @@ -584,7 +584,7 @@ bool AntennaChecker::checkPSR(odb::dbNet* db_net, const float ratio_margin, bool verbose, bool report, - ViolationReport& net_report) + ViolationReport& net_report) { // get rules const odb::dbTechLayerAntennaRule* antenna_rule @@ -639,7 +639,7 @@ bool AntennaChecker::checkCAR(odb::dbNet* db_net, const NodeInfo& info, bool verbose, bool report, - ViolationReport& net_report) + ViolationReport& net_report) { // get rules const odb::dbTechLayerAntennaRule* antenna_rule @@ -687,7 +687,7 @@ bool AntennaChecker::checkCSR(odb::dbNet* db_net, const NodeInfo& info, bool verbose, bool report, - ViolationReport& net_report) + ViolationReport& net_report) { // get rules const odb::dbTechLayerAntennaRule* antenna_rule @@ -736,15 +736,17 @@ bool AntennaChecker::checkRatioViolations(odb::dbNet* db_net, const float ratio_margin, bool verbose, bool report, - ViolationReport& net_report) + ViolationReport& net_report) { bool node_has_violation - = checkPAR(db_net, layer, node_info, ratio_margin, verbose, report, net_report) + = checkPAR( + db_net, layer, node_info, ratio_margin, verbose, report, net_report) || checkCAR(db_net, layer, node_info, verbose, report, net_report); if (layer->getRoutingLevel() != 0) { - bool psr_violation - = checkPSR(db_net, layer, node_info, ratio_margin, verbose, report, net_report); - bool csr_violation = checkCSR(db_net, layer, node_info, verbose, report, net_report); + bool psr_violation = checkPSR( + db_net, layer, node_info, ratio_margin, verbose, report, net_report); + bool csr_violation + = checkCSR(db_net, layer, node_info, verbose, report, net_report); node_has_violation = node_has_violation || psr_violation || csr_violation; } @@ -848,14 +850,14 @@ int AntennaChecker::checkGates(odb::dbNet* db_net, ratio_margin, false, false, - net_report); + net_report); bool psr_violation = checkPSR(db_net, violation_layer, violation_info, ratio_margin, false, false, - net_report); + net_report); bool violated = par_violation || psr_violation; double excess_ratio = 1.0; if (violated) { @@ -877,14 +879,14 @@ int AntennaChecker::checkGates(odb::dbNet* db_net, ratio_margin, false, false, - net_report); + net_report); psr_violation = checkPSR(db_net, violation_layer, violation_info, ratio_margin, false, false, - net_report); + net_report); if (diode_count_per_gate > max_diode_count_per_gate) { debugPrint(logger_, ANT, @@ -909,10 +911,18 @@ int AntennaChecker::checkGates(odb::dbNet* db_net, excess_ratio}); } - bool car_violation - = checkCAR(db_net, violation_layer, violation_info, false, false, net_report); - bool csr_violation - = checkCSR(db_net, violation_layer, violation_info, false, false, net_report); + bool car_violation = checkCAR(db_net, + violation_layer, + violation_info, + false, + false, + net_report); + bool csr_violation = checkCSR(db_net, + violation_layer, + violation_info, + false, + false, + net_report); // naive approach for cumulative area violations. here, all the pins // of the net are included, and placing one diode per pin is not the @@ -1157,7 +1167,6 @@ int AntennaChecker::checkAntennas(odb::dbNet* net, antenna_violations); } } -//#pragma omp barrier if (verbose) { printReport(); From 176e276fa159e9b8679fcce029361f425df08631 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Mon, 2 Dec 2024 21:54:22 -0700 Subject: [PATCH 10/98] testing: convert ctest to use singular script for tcl and python Signed-off-by: Peter Gadfort --- src/ant/test/CMakeLists.txt | 10 +-- src/cmake/testing.cmake | 119 ++++++++++++++++++++++++++++++---- src/cts/test/CMakeLists.txt | 11 +--- src/dbSta/test/CMakeLists.txt | 10 +-- src/dft/test/CMakeLists.txt | 11 +--- src/dpl/test/CMakeLists.txt | 11 +--- src/dpo/test/CMakeLists.txt | 10 +-- src/drt/test/CMakeLists.txt | 12 ++-- src/fin/test/CMakeLists.txt | 10 +-- src/gpl/test/CMakeLists.txt | 10 +-- src/grt/test/CMakeLists.txt | 10 +-- src/gui/test/CMakeLists.txt | 10 +-- src/ifp/test/CMakeLists.txt | 10 +-- src/mpl/test/CMakeLists.txt | 10 +-- src/mpl2/test/CMakeLists.txt | 10 +-- src/odb/test/CMakeLists.txt | 15 +++-- src/pad/test/CMakeLists.txt | 10 +-- src/par/test/CMakeLists.txt | 10 +-- src/pdn/test/CMakeLists.txt | 5 -- src/ppl/test/CMakeLists.txt | 10 +-- src/psm/test/CMakeLists.txt | 10 +-- src/rcx/test/CMakeLists.txt | 12 ++-- src/rmp/test/CMakeLists.txt | 10 +-- src/rsz/test/CMakeLists.txt | 12 ++-- src/stt/test/CMakeLists.txt | 10 +-- src/tap/test/CMakeLists.txt | 10 +-- src/upf/test/CMakeLists.txt | 10 +-- src/utl/test/CMakeLists.txt | 12 ++-- test/CMakeLists.txt | 10 +-- test/regression_test.sh | 28 ++++++++ test/regression_tool.sh | 9 +++ 31 files changed, 238 insertions(+), 209 deletions(-) create mode 100644 test/regression_test.sh create mode 100755 test/regression_tool.sh diff --git a/src/ant/test/CMakeLists.txt b/src/ant/test/CMakeLists.txt index fa07071728e..52663dd740e 100644 --- a/src/ant/test/CMakeLists.txt +++ b/src/ant/test/CMakeLists.txt @@ -1,6 +1,6 @@ -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "ant" + TESTS ant_check ant_report check_api1 @@ -11,7 +11,3 @@ set(TEST_NAMES # Skipped #ant_man_tcl_check #ant_readme_msgs_check - -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("ant" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() diff --git a/src/cmake/testing.cmake b/src/cmake/testing.cmake index 7b74a4e8fc2..b503acfc28c 100644 --- a/src/cmake/testing.cmake +++ b/src/cmake/testing.cmake @@ -1,19 +1,110 @@ -function(or_integration_test tool_name test_name regression_binary) - add_test ( - NAME ${tool_name}.${test_name} - COMMAND ${BASH_PROGRAM} ${regression_binary} ${test_name} - WORKING_DIRECTORY ${CMAKE_CURRENT_LIST_DIR} - ) +function(or_integration_test_single tool_name test_name test_type check_log check_passfail) + unset(TEST_FOUND PARENT_SCOPE) + + if (${test_type} STREQUAL "tcl") + set(TEST_EXT tcl) + elseif (${test_type} STREQUAL "python") + set(TEST_EXT py) + else() + message(FATAL_ERROR "${test_type} is not supported by testing") + endif() + + set(TEST_FILE "${CMAKE_CURRENT_LIST_DIR}/${test_name}.${TEST_EXT}") + set(TEST_NAME "${tool_name}.${test_name}.${TEST_EXT}") + + if(EXISTS "${TEST_FILE}") + add_test( + NAME ${TEST_NAME} + COMMAND ${BASH_PROGRAM} ${OpenROAD_SOURCE_DIR}/test/regression_test.sh + WORKING_DIRECTORY ${CMAKE_CURRENT_LIST_DIR} + ) + + string( + CONCAT ENV + "OPENROAD_EXE=$;" + "TEST_NAME=${test_name};" + "TEST_EXT=${TEST_EXT};" + "TEST_TYPE=${test_type};" + "TEST_CHECK_LOG=${check_log};" + "TEST_CHECK_PASSFAIL=${check_passfail};" + ) + + set_property( + TEST ${TEST_NAME} + PROPERTY ENVIRONMENT ${ENV} + ) + + set(LABELS "IntegrationTest ${test_type} ${tool_name}") + if(check_log STREQUAL "True") + set(LABELS "${LABELS} log_compare") + endif() + if(check_passfail STREQUAL "True") + set(LABELS "${LABELS} passfail") + endif() + + set_tests_properties( + ${TEST_NAME} + PROPERTIES LABELS "${LABELS}" + ) + set(TEST_FOUND TRUE PARENT_SCOPE) + else() + set(TEST_FOUND FALSE PARENT_SCOPE) + # message(WARNING "Test ${TEST_FILE} is missing") + endif() + +endfunction() - string(CONCAT ENV - "TEST_TYPE=compare_logfile;" - "CTEST_TESTNAME=${test_name};" - "DIFF_LOCATION=${CMAKE_CURRENT_LIST_DIR}/results/${test_name}.diff" +function(or_integration_tests tool_name) + + # Parse args + set(options "") + set(oneValueArgs "") + set(multiValueArgs TESTS PASSFAIL_TESTS) + + cmake_parse_arguments( + ARG # prefix on the parsed args + "${options}" + "${oneValueArgs}" + "${multiValueArgs}" + ${ARGN} ) - set_property(TEST ${tool_name}.${test_name} - PROPERTY ENVIRONMENT ${ENV}) + if (DEFINED ARG_UNPARSED_ARGUMENTS) + message(FATAL_ERROR "Unknown argument(s) to or_integration_tests: ${ARG_UNPARSED_ARGUMENTS}") + endif() + + if (DEFINED ARG_KEYWORDS_MISSING_VALUES) + message(FATAL_ERROR "Missing value for argument(s) to or_integration_tests: ${ARG_KEYWORDS_MISSING_VALUES}") + endif() + + if (DEFINED ARG_TESTS) + foreach(TEST_NAME IN LISTS ARG_TESTS) + + or_integration_test_single(${tool_name} ${TEST_NAME} tcl True False) + set(tcl_found ${TEST_FOUND}) + or_integration_test_single(${tool_name} ${TEST_NAME} python True False) + set(py_found ${TEST_FOUND}) + + if(NOT tcl_found AND NOT py_found) + message(FATAL_ERROR "Test ${TEST_NAME} is missing for ${tool_name}") + endif() + + endforeach() + endif() + + if (DEFINED ARG_PASSFAIL_TESTS) + foreach(TEST_NAME IN LISTS ARG_PASSFAIL_TESTS) + + or_integration_test_single(${tool_name} ${TEST_NAME} tcl False True) + set(tcl_found ${TEST_FOUND}) + or_integration_test_single(${tool_name} ${TEST_NAME} python False True) + set(py_found ${TEST_FOUND}) + + if(NOT tcl_found AND NOT py_found) + message(FATAL_ERROR "Test ${TEST_NAME} is missing for ${tool_name}") + endif() + + endforeach() + endif() - set_tests_properties(${tool_name}.${test_name} - PROPERTIES LABELS "IntegrationTest") endfunction() diff --git a/src/cts/test/CMakeLists.txt b/src/cts/test/CMakeLists.txt index b99b128e632..f70d8a429e7 100644 --- a/src/cts/test/CMakeLists.txt +++ b/src/cts/test/CMakeLists.txt @@ -4,9 +4,9 @@ # license that can be found in the LICENSE file or at # https://developers.google.com/open-source/licenses/bsd -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "cts" + TESTS array array_ins_delay array_no_blockages @@ -35,11 +35,6 @@ set(TEST_NAMES # Skipped #cts_man_tcl_check #cts_readme_msgs_check - -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("cts" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() - add_executable(cts_unittest cts_unittest.cc) target_include_directories(cts_unittest PUBLIC diff --git a/src/dbSta/test/CMakeLists.txt b/src/dbSta/test/CMakeLists.txt index 803b103e2fe..2e7f7c0b433 100644 --- a/src/dbSta/test/CMakeLists.txt +++ b/src/dbSta/test/CMakeLists.txt @@ -1,6 +1,6 @@ -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "dbSta" + TESTS block_sta1 constant1 find_clks1 @@ -45,7 +45,3 @@ set(TEST_NAMES write_verilog7 write_verilog8 ) - -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("dbSta" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() diff --git a/src/dft/test/CMakeLists.txt b/src/dft/test/CMakeLists.txt index 595a57c8e1c..0b00300b919 100644 --- a/src/dft/test/CMakeLists.txt +++ b/src/dft/test/CMakeLists.txt @@ -1,7 +1,6 @@ -# Tests -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "dft" + TESTS max_chain_count_sky130 one_cell_nangate45 one_cell_sky130 @@ -18,9 +17,5 @@ set(TEST_NAMES #dft_man_tcl_check #dft_readme_msgs_check -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("dft" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() - find_package(Boost) add_subdirectory(cpp) diff --git a/src/dpl/test/CMakeLists.txt b/src/dpl/test/CMakeLists.txt index da30927787f..e21af3352a8 100644 --- a/src/dpl/test/CMakeLists.txt +++ b/src/dpl/test/CMakeLists.txt @@ -4,9 +4,9 @@ # license that can be found in the LICENSE file or at # https://developers.google.com/open-source/licenses/bsd -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "dpl" + TESTS aes blockage01 cell_on_block1 @@ -77,11 +77,6 @@ set(TEST_NAMES # Skipped #dpl_man_tcl_check #dpl_readme_msgs_check - -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("dpl" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() - add_executable(dpl_test dpl_test.cc) target_link_libraries(dpl_test diff --git a/src/dpo/test/CMakeLists.txt b/src/dpo/test/CMakeLists.txt index 57a985bb249..f69d8d8cf22 100644 --- a/src/dpo/test/CMakeLists.txt +++ b/src/dpo/test/CMakeLists.txt @@ -1,6 +1,6 @@ -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "dpo" + TESTS aes blockage1 gcd @@ -10,7 +10,3 @@ set(TEST_NAMES regions1 regions2 ) - -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("dpo" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() diff --git a/src/drt/test/CMakeLists.txt b/src/drt/test/CMakeLists.txt index c787d8d99a2..36cfae5575b 100644 --- a/src/drt/test/CMakeLists.txt +++ b/src/drt/test/CMakeLists.txt @@ -1,6 +1,6 @@ -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "drt" + TESTS drc_test ispd18_sample ispd18_sample_incr @@ -12,12 +12,10 @@ set(TEST_NAMES ta_pin_aligned top_level_term top_level_term2 + PASSFAIL_TESTS + gc_test ) # Skipped #drt_man_tcl_check #drt_readme_msgs_check - -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("drt" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() diff --git a/src/fin/test/CMakeLists.txt b/src/fin/test/CMakeLists.txt index b4f6aae14e6..5a3fd723ad2 100644 --- a/src/fin/test/CMakeLists.txt +++ b/src/fin/test/CMakeLists.txt @@ -1,13 +1,9 @@ -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "fin" + TESTS gcd_fill ) # Skipped #fin_man_tcl_check #fin_readme_msgs_check - -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("fin" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() diff --git a/src/gpl/test/CMakeLists.txt b/src/gpl/test/CMakeLists.txt index 97132620f9d..734ffb3cd9d 100644 --- a/src/gpl/test/CMakeLists.txt +++ b/src/gpl/test/CMakeLists.txt @@ -1,6 +1,6 @@ -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "gpl" + TESTS ar01 ar02 clust01 @@ -38,10 +38,6 @@ set(TEST_NAMES #gpl_man_tcl_check #gpl_readme_msgs_check -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("gpl" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() - add_executable(fft_test fft_test.cc) target_include_directories(fft_test diff --git a/src/grt/test/CMakeLists.txt b/src/grt/test/CMakeLists.txt index 92bbdfbeb9c..da46aaa0f03 100644 --- a/src/grt/test/CMakeLists.txt +++ b/src/grt/test/CMakeLists.txt @@ -1,6 +1,6 @@ -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "grt" + TESTS bus_route clock_route clock_route_alpha @@ -81,7 +81,3 @@ set(TEST_NAMES # Skipped #grt_man_tcl_check #grt_readme_msgs_check - -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("grt" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() diff --git a/src/gui/test/CMakeLists.txt b/src/gui/test/CMakeLists.txt index 87207ffad69..257b9c03467 100644 --- a/src/gui/test/CMakeLists.txt +++ b/src/gui/test/CMakeLists.txt @@ -1,13 +1,9 @@ -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "gui" + TESTS supported ) # Skipped #gui_man_tcl_check #gui_readme_msgs_check - -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("gui" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() diff --git a/src/ifp/test/CMakeLists.txt b/src/ifp/test/CMakeLists.txt index 26246c1abc1..dac9461afb0 100644 --- a/src/ifp/test/CMakeLists.txt +++ b/src/ifp/test/CMakeLists.txt @@ -1,6 +1,6 @@ -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "ifp" + TESTS hybrid_rows hybrid_rows2 init_floorplan1 @@ -34,7 +34,3 @@ set(TEST_NAMES # Skipped #ifp_man_tcl_check #ifp_readme_msgs_check - -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("ifp" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() diff --git a/src/mpl/test/CMakeLists.txt b/src/mpl/test/CMakeLists.txt index 5b37b5ba7db..871e2a4161b 100644 --- a/src/mpl/test/CMakeLists.txt +++ b/src/mpl/test/CMakeLists.txt @@ -1,6 +1,6 @@ -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "mpl" + TESTS east_west1 east_west2 level3_01 @@ -11,7 +11,3 @@ set(TEST_NAMES # Skipped #mpl_man_tcl_check #mpl_readme_msgs_check - -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("mpl" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() diff --git a/src/mpl2/test/CMakeLists.txt b/src/mpl2/test/CMakeLists.txt index 936b53f0f06..6b561e01d0e 100644 --- a/src/mpl2/test/CMakeLists.txt +++ b/src/mpl2/test/CMakeLists.txt @@ -1,6 +1,6 @@ -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "mpl2" + TESTS macro_only no_unfixed_macros ) @@ -9,8 +9,4 @@ set(TEST_NAMES #mpl2_man_tcl_check #mpl2_readme_msgs_check -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("mpl2" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() - add_subdirectory(cpp) diff --git a/src/odb/test/CMakeLists.txt b/src/odb/test/CMakeLists.txt index 6ec160e4427..05d7ac46a68 100644 --- a/src/odb/test/CMakeLists.txt +++ b/src/odb/test/CMakeLists.txt @@ -1,6 +1,6 @@ -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "odb" + TESTS abstract_origin bterm_hier_create check_routing_tracks @@ -48,14 +48,15 @@ set(TEST_NAMES write_lef_and_def write_lef_polygon write_macro_placement + PASSFAIL_TESTS + cpp_tests + dump_netlists + dump_netlists_withfill + parser_unit_test ) # Skipped #odb_man_tcl_check #odb_readme_msgs_check -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("odb" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() - add_subdirectory(cpp) diff --git a/src/pad/test/CMakeLists.txt b/src/pad/test/CMakeLists.txt index 256da867458..f62d7feabee 100644 --- a/src/pad/test/CMakeLists.txt +++ b/src/pad/test/CMakeLists.txt @@ -1,6 +1,6 @@ -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "pad" + TESTS assign_bumps assign_bumps_two_pins bump_array_make @@ -49,7 +49,3 @@ set(TEST_NAMES # Skipped #pad_man_tcl_check #pad_readme_msgs_check - -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("pad" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() diff --git a/src/par/test/CMakeLists.txt b/src/par/test/CMakeLists.txt index e5d6dc9ce01..44124476962 100644 --- a/src/par/test/CMakeLists.txt +++ b/src/par/test/CMakeLists.txt @@ -1,6 +1,6 @@ -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "par" + TESTS partition_gcd read_part ) @@ -8,7 +8,3 @@ set(TEST_NAMES # Skipped #par_man_tcl_check #par_readme_msgs_check - -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("par" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() diff --git a/src/pdn/test/CMakeLists.txt b/src/pdn/test/CMakeLists.txt index ebbb0a92f85..740c6211e8a 100644 --- a/src/pdn/test/CMakeLists.txt +++ b/src/pdn/test/CMakeLists.txt @@ -16,7 +16,6 @@ set(TEST_NAMES asap7_vias_fixed_vias asap7_vias_max_rows_columns bpin_removal - convert core_grid core_grid_adjacentcuts core_grid_auto_domain @@ -107,7 +106,3 @@ set(TEST_NAMES # Skipped #pdn_man_tcl_check #pdn_readme_msgs_check - -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("pdn" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() diff --git a/src/ppl/test/CMakeLists.txt b/src/ppl/test/CMakeLists.txt index 7ebbeb562dc..3043ae986aa 100644 --- a/src/ppl/test/CMakeLists.txt +++ b/src/ppl/test/CMakeLists.txt @@ -1,6 +1,6 @@ -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "ppl" + TESTS add_constraint1 add_constraint2 add_constraint3 @@ -124,7 +124,3 @@ set(TEST_NAMES # Skipped #ppl_man_tcl_check #ppl_readme_msgs_check - -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("ppl" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() diff --git a/src/psm/test/CMakeLists.txt b/src/psm/test/CMakeLists.txt index c4f292a4348..cf9d4541068 100644 --- a/src/psm/test/CMakeLists.txt +++ b/src/psm/test/CMakeLists.txt @@ -1,6 +1,6 @@ -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "psm" + TESTS aes_asap7_vdd aes_test_bterms aes_test_multiple_bterms @@ -34,7 +34,3 @@ set(TEST_NAMES # Skipped #psm_man_tcl_check #psm_readme_msgs_check - -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("psm" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() diff --git a/src/rcx/test/CMakeLists.txt b/src/rcx/test/CMakeLists.txt index 8704105df1b..b41746b11b4 100644 --- a/src/rcx/test/CMakeLists.txt +++ b/src/rcx/test/CMakeLists.txt @@ -1,18 +1,16 @@ -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "rcx" + TESTS 45_gcd ext_pattern gcd generate_pattern names + PASSFAIL_TESTS + rcx_unit_test ) # Skipped #generate_rules #rcx_man_tcl_check #rcx_readme_msgs_check - -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("rcx" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() diff --git a/src/rmp/test/CMakeLists.txt b/src/rmp/test/CMakeLists.txt index ced225373dd..68d28edf5a5 100644 --- a/src/rmp/test/CMakeLists.txt +++ b/src/rmp/test/CMakeLists.txt @@ -1,6 +1,6 @@ -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "rmp" + TESTS blif_reader blif_reader_const blif_reader_sequential @@ -17,10 +17,6 @@ set(TEST_NAMES #rmp_man_tcl_check #rmp_readme_msgs_check -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("rmp" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() - if (ENABLE_TESTS) add_subdirectory(cpp) endif() diff --git a/src/rsz/test/CMakeLists.txt b/src/rsz/test/CMakeLists.txt index b1bb1d049c4..5bef11e139b 100644 --- a/src/rsz/test/CMakeLists.txt +++ b/src/rsz/test/CMakeLists.txt @@ -1,6 +1,6 @@ -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "rsz" + TESTS buffer_ports1 buffer_ports3 buffer_ports4 @@ -127,14 +127,12 @@ set(TEST_NAMES set_dont_touch1 set_dont_use1 split_load_hier + PASSFAIL_TESTS + cpp_tests ) # Skipped #rsz_man_tcl_check #rsz_readme_msgs_check -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("rsz" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() - add_subdirectory(cpp) diff --git a/src/stt/test/CMakeLists.txt b/src/stt/test/CMakeLists.txt index 547004286ed..5ee1347862c 100644 --- a/src/stt/test/CMakeLists.txt +++ b/src/stt/test/CMakeLists.txt @@ -1,6 +1,6 @@ -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "stt" + TESTS check flute1 flute_gcd @@ -13,7 +13,3 @@ set(TEST_NAMES # Skipped #stt_man_tcl_check #stt_readme_msgs_check - -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("stt" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() diff --git a/src/tap/test/CMakeLists.txt b/src/tap/test/CMakeLists.txt index ad3973677ac..b98df0fe492 100644 --- a/src/tap/test/CMakeLists.txt +++ b/src/tap/test/CMakeLists.txt @@ -1,6 +1,6 @@ -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "tap" + TESTS aes_gf180 avoid_overlap boundary_macros @@ -29,7 +29,3 @@ set(TEST_NAMES # Skipped #tap_man_tcl_check #tap_readme_msgs_check - -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("tap" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() diff --git a/src/upf/test/CMakeLists.txt b/src/upf/test/CMakeLists.txt index 9493df25e7c..970c2e461fa 100644 --- a/src/upf/test/CMakeLists.txt +++ b/src/upf/test/CMakeLists.txt @@ -1,6 +1,6 @@ -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "upf" + TESTS levelshifter write ) @@ -8,7 +8,3 @@ set(TEST_NAMES # Skipped #upf_man_tcl_check #upf_readme_msgs_check - -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("upf" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() diff --git a/src/utl/test/CMakeLists.txt b/src/utl/test/CMakeLists.txt index f2fb4e5debb..f58d2ef31bf 100644 --- a/src/utl/test/CMakeLists.txt +++ b/src/utl/test/CMakeLists.txt @@ -1,6 +1,6 @@ -include("openroad") - -set(TEST_NAMES +or_integration_tests( + "utl" + TESTS logger_max_messages logger_redirection logger_redirection_nonewline @@ -10,6 +10,8 @@ set(TEST_NAMES test_info test_metrics test_suppress_message + PASSFAIL_TESTS + cpp_tests ) # Skipped @@ -17,8 +19,4 @@ set(TEST_NAMES #utl_man_tcl_check #utl_readme_msgs_check -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("utl" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() - add_subdirectory(cpp) diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt index f052ffab681..8fdc84989dd 100644 --- a/test/CMakeLists.txt +++ b/test/CMakeLists.txt @@ -1,4 +1,6 @@ -set(TEST_NAMES +or_integration_tests( + "openroad" + TESTS error1 get_core_die_areas timing_api @@ -8,8 +10,6 @@ set(TEST_NAMES two_designs upf_test upf_aes + PASSFAIL_TESTS + commands_without_load ) - -foreach(TEST_NAME IN LISTS TEST_NAMES) - or_integration_test("openroad" ${TEST_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/regression) -endforeach() diff --git a/test/regression_test.sh b/test/regression_test.sh new file mode 100644 index 00000000000..99d5ee07257 --- /dev/null +++ b/test/regression_test.sh @@ -0,0 +1,28 @@ +#!/usr/bin/env bash + +set -e + +mkdir -p results + +LOG_FILE=results/$TEST_NAME-$TEST_EXT.log + +ORD_ARGS="" +if [ "$TEST_TYPE" == "python" ]; then + ORD_ARGS="-python" +fi + +echo "Directory: ${PWD}" +echo "Command: $OPENROAD_EXE $ORD_ARGS -no_splash -no_init -exit $TEST_NAME.$TEST_EXT > $LOG_FILE" + +$OPENROAD_EXE $ORD_ARGS -no_splash -no_init -exit $TEST_NAME.$TEST_EXT > $LOG_FILE + +echo "Exitcode: $?" + +if [ "$TEST_CHECK_LOG" == "True" ]; then + echo "Diff: ${PWD}/results/$TEST_NAME-$TEST_EXT.diff" + diff $LOG_FILE $TEST_NAME.ok > results/$TEST_NAME-$TEST_EXT.diff +fi + +if [ "$TEST_CHECK_PASSFAIL" == "True" ]; then + tail -n1 $LOG_FILE | grep -G '^pass$' +fi diff --git a/test/regression_tool.sh b/test/regression_tool.sh new file mode 100755 index 00000000000..e669c69c1fc --- /dev/null +++ b/test/regression_tool.sh @@ -0,0 +1,9 @@ +#!/usr/bin/env bash + +set -e + +tool=$(basename $(dirname $PWD)) + +cd ../../../build + +ctest -L $tool ${@:1} From 827a0782eca3bae748c1b0686affd650093807b7 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Wed, 4 Dec 2024 15:51:17 -0700 Subject: [PATCH 11/98] rmp: fix rmp tests Signed-off-by: Peter Gadfort --- src/rmp/test/const_cell_removal.ok | 8 ++++---- src/rmp/test/const_cell_removal.py | 1 + src/rmp/test/gcd_restructure.ok | 8 ++++---- src/rmp/test/gcd_restructure.py | 4 ++-- src/rmp/test/rmp_aux.py | 2 ++ 5 files changed, 13 insertions(+), 10 deletions(-) diff --git a/src/rmp/test/const_cell_removal.ok b/src/rmp/test/const_cell_removal.ok index 4ef4ac96bd1..580ef4245f4 100644 --- a/src/rmp/test/const_cell_removal.ok +++ b/src/rmp/test/const_cell_removal.ok @@ -11,10 +11,10 @@ Found 129 pins in extracted logic. Found 41 instances for restructuring. [INFO RMP-0002] Blif writer successfully dumped file with 41 instances. Warning: Detected 2 multi-output gates (for example, "FA_X1"). -Fraiging part 1 (out of 1) PI = 8. PO = 14. And = 43. Lev = 8. -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> Warning: Detected 2 multi-output gates (for example, "FA_X1"). -Fraiging part 1 (out of 1) PI = 8. PO = 14. And = 43. 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------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> Fraiging part 1 (out of 1) PI = 8. PO = 14. And = 53. Lev = 8. -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> Warning: Detected 2 multi-output gates (for example, "FA_X1"). -Fraiging part 1 (out of 1) PI = 8. PO = 14. And = 103. Lev = 8. Warning: The choice nodes in the original AIG are removed by strashing. --> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> Fraiging part 1 (out of 1) PI = 8. PO = 14. And = 91. Lev = 8. -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> Fraiging part 1 (out of 1) PI = 8. PO = 14. And = 58. Lev = 8. -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> Reading ABC log results/abc_rcon.log0. +Fraiging part 1 (out of 1) PI = 8. PO = 14. And = 43. Lev = 8. -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> Warning: Detected 2 multi-output gates (for example, "FA_X1"). +Fraiging part 1 (out of 1) PI = 8. PO = 14. And = 43. Lev = 8. -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> Fraiging part 1 (out of 1) PI = 8. PO = 14. And = 53. Lev = 8. -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> Warning: Detected 2 multi-output gates (for example, "FA_X1"). +Fraiging part 1 (out of 1) PI = 8. PO = 14. And = 103. Lev = 8. Warning: The choice nodes in the original AIG are removed by strashing. +-> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> Fraiging part 1 (out of 1) PI = 8. PO = 14. And = 91. Lev = 8. -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> Fraiging part 1 (out of 1) PI = 8. PO = 14. And = 58. Lev = 8. -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> Reading ABC log results/abc_rcon.log0. Optimized to 36 instances in iteration 0 with max path depth decrease of 0, delay of 3.4028235e+38. Reading ABC log results/abc_rcon.log1. Optimized to 37 instances in iteration 1 with max path depth decrease of 0, delay of 3.4028235e+38. diff --git a/src/rmp/test/const_cell_removal.py b/src/rmp/test/const_cell_removal.py index 49184c2b638..25de9ad58d9 100644 --- a/src/rmp/test/const_cell_removal.py +++ b/src/rmp/test/const_cell_removal.py @@ -18,6 +18,7 @@ design, liberty_file_name="Nangate45/Nangate45_typ.lib", target="area", + workdir_name="results/python/const", abc_logfile="results/abc_rcon.log", tielo_port=tielo, tiehi_port=tiehi, diff --git a/src/rmp/test/gcd_restructure.ok b/src/rmp/test/gcd_restructure.ok index 839aacf26a9..a95b19e2873 100644 --- a/src/rmp/test/gcd_restructure.ok +++ b/src/rmp/test/gcd_restructure.ok @@ -14,10 +14,10 @@ Found 1290 pins in extracted logic. Found 422 instances for restructuring. [INFO RMP-0002] Blif writer successfully dumped file with 422 instances. Warning: Detected 2 multi-output gates (for example, "FA_X1"). -Fraiging part 1 (out of 1) PI = 89. PO = 52. And = 1073. Lev = 20. -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> Warning: Detected 2 multi-output gates (for example, "FA_X1"). -Fraiging part 1 (out of 1) PI = 89. PO = 52. And = 1073. Lev = 20. -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> Fraiging part 1 (out of 1) PI = 89. PO = 52. And = 1097. Lev = 20. -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> Warning: Detected 2 multi-output gates (for example, "FA_X1"). -Fraiging part 1 (out of 1) PI = 89. PO = 52. And = 1514. Lev = 20. Warning: The choice nodes in the original AIG are removed by strashing. --> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> Fraiging part 1 (out of 1) PI = 89. PO = 52. And = 1455. Lev = 20. -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> 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-----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> Fraiging part 1 (out of 1) PI = 89. PO = 52. And = 1397. Lev = 20. -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> Reading ABC log results/abc_rcon.log0. +Fraiging part 1 (out of 1) PI = 89. PO = 52. And = 1073. Lev = 20. -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> Warning: Detected 2 multi-output gates (for example, "FA_X1"). +Fraiging part 1 (out of 1) PI = 89. PO = 52. And = 1073. Lev = 20. -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> 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------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> 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-----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> Fraiging part 1 (out of 1) PI = 89. PO = 52. And = 1097. Lev = 20. -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> Warning: Detected 2 multi-output gates (for example, "FA_X1"). +Fraiging part 1 (out of 1) PI = 89. PO = 52. And = 1514. Lev = 20. Warning: The choice nodes in the original AIG are removed by strashing. +-> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> 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------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> 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----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> Fraiging part 1 (out of 1) PI = 89. PO = 52. And = 1455. Lev = 20. -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> ------------------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> 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--------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> 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-----------------------------------------------------------------------> -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> ---------------------------------------------------------> ----------------------------------------------------------------> -----------------------------------------------------------------------> Fraiging part 1 (out of 1) PI = 89. PO = 52. And = 1397. Lev = 20. -> --------> ---------------> ----------------------> -----------------------------> ------------------------------------> -------------------------------------------> --------------------------------------------------> Reading ABC log results/abc_rcon.log0. Optimized to 256 instances in iteration 0 with max path depth decrease of 0, delay of 3.4028235e+38. Reading ABC log results/abc_rcon.log1. Optimized to 250 instances in iteration 1 with max path depth decrease of 0, delay of 3.4028235e+38. diff --git a/src/rmp/test/gcd_restructure.py b/src/rmp/test/gcd_restructure.py index aecdb3395a4..3da21e9ac44 100644 --- a/src/rmp/test/gcd_restructure.py +++ b/src/rmp/test/gcd_restructure.py @@ -27,10 +27,10 @@ design, liberty_file_name="Nangate45/Nangate45_typ.lib", target="area", + workdir_name="results/python/gcd", abc_logfile="results/abc_rcon.log", tielo_port=tielo, - tiehi_port=tiehi, - workdir_name="./results", + tiehi_port=tiehi ) design.evalTclString("report_design_area") diff --git a/src/rmp/test/rmp_aux.py b/src/rmp/test/rmp_aux.py index fbca107bac8..b2381cbc01e 100644 --- a/src/rmp/test/rmp_aux.py +++ b/src/rmp/test/rmp_aux.py @@ -1,6 +1,7 @@ import utl from string import Template import rmp +import os # So, getting back objects from evalTclString is not supported and we # end up with this... These lib pins appear to be Liberty lib pins, @@ -54,6 +55,7 @@ def restructure( tiehi_port=None, abc_logfile="" ): + os.makedirs(workdir_name, exist_ok=True) rst = design.getRestructure() set_tielo(design, tielo_port) set_tiehi(design, tiehi_port) From 615de6c213c05dccb2d4509b08421aab56f897cc Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 08:23:51 -0700 Subject: [PATCH 12/98] test: add replacement helper scripts for use with ctest Signed-off-by: Peter Gadfort --- test/regression_tool.sh | 9 ------- test/shared/regression.sh | 44 +++++++++++++++++++++++++++++++++ test/shared/save_defok.sh | 51 +++++++++++++++++++++++++++++++++++++++ test/shared/save_ok.sh | 51 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 146 insertions(+), 9 deletions(-) delete mode 100755 test/regression_tool.sh create mode 100755 test/shared/regression.sh create mode 100755 test/shared/save_defok.sh create mode 100755 test/shared/save_ok.sh diff --git a/test/regression_tool.sh b/test/regression_tool.sh deleted file mode 100755 index e669c69c1fc..00000000000 --- a/test/regression_tool.sh +++ /dev/null @@ -1,9 +0,0 @@ -#!/usr/bin/env bash - -set -e - -tool=$(basename $(dirname $PWD)) - -cd ../../../build - -ctest -L $tool ${@:1} diff --git a/test/shared/regression.sh b/test/shared/regression.sh new file mode 100755 index 00000000000..6c1dd13bbec --- /dev/null +++ b/test/shared/regression.sh @@ -0,0 +1,44 @@ +#!/usr/bin/env bash + +############################################################################ +## +## Copyright (c) 2024, The Regents of the University of California +## All rights reserved. +## +## BSD 3-Clause License +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, this +## list of conditions and the following disclaimer. +## +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## +## * Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from +## this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. +## +############################################################################ + +set -e + +tool=$(basename $(dirname $PWD)) + +cd ../../../build + +ctest -L $tool ${@:1} diff --git a/test/shared/save_defok.sh b/test/shared/save_defok.sh new file mode 100755 index 00000000000..107d73fe011 --- /dev/null +++ b/test/shared/save_defok.sh @@ -0,0 +1,51 @@ +#!/usr/bin/env bash + +############################################################################ +## +## Copyright (c) 2024, The Regents of the University of California +## All rights reserved. +## +## BSD 3-Clause License +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, this +## list of conditions and the following disclaimer. +## +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## +## * Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from +## this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. +## +############################################################################ + +set -e + +for test_name in "${@:1}" +do + if [ -f "results/${test_name}-tcl.def" ]; then + cp "results/${test_name}-tcl.def" "${test_name}.defok" + echo "${test_name}" + elif [ -f "results/${test_name}-py.def" ]; then + cp "results/${test_name}-py.def" "${test_name}.defok" + echo "${test_name}" + else + echo "\"${test_name}\" def file not found" + fi +done diff --git a/test/shared/save_ok.sh b/test/shared/save_ok.sh new file mode 100755 index 00000000000..a119a6fe9b9 --- /dev/null +++ b/test/shared/save_ok.sh @@ -0,0 +1,51 @@ +#!/usr/bin/env bash + +############################################################################ +## +## Copyright (c) 2024, The Regents of the University of California +## All rights reserved. +## +## BSD 3-Clause License +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, this +## list of conditions and the following disclaimer. +## +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## +## * Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from +## this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. +## +############################################################################ + +set -e + +for test_name in "${@:1}" +do + if [ -f "results/${test_name}-tcl.log" ]; then + cp "results/${test_name}-tcl.log" "${test_name}.ok" + echo "${test_name}" + elif [ -f "results/${test_name}-py.log" ]; then + cp "results/${test_name}-py.log" "${test_name}.ok" + echo "${test_name}" + else + echo "\"${test_name}\" log file not found" + fi +done From e45055d4155be52efbdc7f27d0c2ef9118902ac8 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 08:59:30 -0700 Subject: [PATCH 13/98] ant: switch to ctest Signed-off-by: Peter Gadfort --- src/ant/test/regression | 2 +- src/ant/test/regression_tests.tcl | 9 --------- src/ant/test/save_ok | 2 +- test/regression | 1 - 4 files changed, 2 insertions(+), 12 deletions(-) delete mode 100644 src/ant/test/regression_tests.tcl diff --git a/src/ant/test/regression b/src/ant/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/ant/test/regression +++ b/src/ant/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/ant/test/regression_tests.tcl b/src/ant/test/regression_tests.tcl deleted file mode 100644 index 6ba3a28fd3e..00000000000 --- a/src/ant/test/regression_tests.tcl +++ /dev/null @@ -1,9 +0,0 @@ -record_tests { - check_api1 - check_drt1 - check_grt1 - ant_check - ant_report - #ant_readme_msgs_check - #ant_man_tcl_check -} diff --git a/src/ant/test/save_ok b/src/ant/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/ant/test/save_ok +++ b/src/ant/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index 3dd79466533..21fa8885a43 100755 --- a/test/regression +++ b/test/regression @@ -51,7 +51,6 @@ define_tool_script "cts" "src/cts/test/regression" define_tool_script "dpl" "src/dpl/test/regression" define_tool_script "dpo" "src/dpo/test/regression" define_tool_script "grt" "src/grt/test/regression" -define_tool_script "ant" "src/ant/test/regression" define_tool_script "rcx" "src/rcx/test/regression" define_tool_script "psm" "src/psm/test/regression" define_tool_script "drt" "src/drt/test/regression" From 30e543f5ec360b5e9c67476920ce0563629ef2af Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:10:29 -0700 Subject: [PATCH 14/98] cts: move to ctest Signed-off-by: Peter Gadfort --- src/cts/test/regression | 2 +- src/cts/test/regression_tests.tcl | 27 --------------------------- src/cts/test/save_ok | 2 +- test/regression | 1 - 4 files changed, 2 insertions(+), 30 deletions(-) delete mode 100644 src/cts/test/regression_tests.tcl diff --git a/src/cts/test/regression b/src/cts/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/cts/test/regression +++ b/src/cts/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/cts/test/regression_tests.tcl b/src/cts/test/regression_tests.tcl deleted file mode 100644 index 9bd42c02e2f..00000000000 --- a/src/cts/test/regression_tests.tcl +++ /dev/null @@ -1,27 +0,0 @@ -record_tests { - simple_test_hier - array - array_no_blockages - array_ins_delay - balance_levels - check_buffers - check_buffers_blockages - check_charBuf - check_max_fanout1 - check_max_fanout2 - check_wire_rc_cts - dummy_load - find_clock - find_clock_pad - insertion_delay - max_cap - no_clocks - no_sinks - post_cts_opt - simple_test - simple_test_clustered - simple_test_clustered_max_cap - lvt_lib - #cts_readme_msgs_check - #cts_man_tcl_check -} diff --git a/src/cts/test/save_ok b/src/cts/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/cts/test/save_ok +++ b/src/cts/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index 21fa8885a43..1b8eb203e4c 100755 --- a/test/regression +++ b/test/regression @@ -47,7 +47,6 @@ define_tool_script "mpl2" "src/mpl2/test/regression" define_tool_script "par" "src/par/test/regression" define_tool_script "gpl" "src/gpl/test/regression" define_tool_script "rsz" "src/rsz/test/regression" -define_tool_script "cts" "src/cts/test/regression" define_tool_script "dpl" "src/dpl/test/regression" define_tool_script "dpo" "src/dpo/test/regression" define_tool_script "grt" "src/grt/test/regression" From 216e0f1af85f479213a6d97445dd30683520668f Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:11:04 -0700 Subject: [PATCH 15/98] dbSta: move to ctest Signed-off-by: Peter Gadfort --- src/dbSta/test/regression | 2 +- src/dbSta/test/regression_tests.tcl | 50 ----------------------------- src/dbSta/test/save_defok | 2 +- src/dbSta/test/save_ok | 2 +- test/regression | 1 - 5 files changed, 3 insertions(+), 54 deletions(-) delete mode 100644 src/dbSta/test/regression_tests.tcl diff --git a/src/dbSta/test/regression b/src/dbSta/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/dbSta/test/regression +++ b/src/dbSta/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/dbSta/test/regression_tests.tcl b/src/dbSta/test/regression_tests.tcl deleted file mode 100644 index a52f411d8e3..00000000000 --- a/src/dbSta/test/regression_tests.tcl +++ /dev/null @@ -1,50 +0,0 @@ -record_tests { - hierclock - hier2 - readdb_hier - constant1 - make_port - network_edit1 - sdc_names1 - sdc_names2 - sdc_get1 - sta1 - sta2 - sta3 - sta4 - sta5 - block_sta1 - find_clks1 - find_clks2 - report_json1 - power1 - - read_liberty1 - - read_verilog1 - read_verilog2 - read_verilog3 - read_verilog4 - read_verilog5 - read_verilog6 - read_verilog7 - read_verilog8 - read_verilog9 - read_verilog10 - read_verilog11 - - report_cell_usage - report_cell_usage_modinsts - report_cell_usage_modinsts_metrics - - write_verilog1 - write_verilog2 - write_verilog3 - write_verilog4 - write_verilog5 - write_verilog6 - write_verilog7 - write_verilog8 - - write_sdc1 -} diff --git a/src/dbSta/test/save_defok b/src/dbSta/test/save_defok index 899db325246..7ee49ae334f 120000 --- a/src/dbSta/test/save_defok +++ b/src/dbSta/test/save_defok @@ -1 +1 @@ -../../../test/shared/save_defok \ No newline at end of file +../../../test/shared/save_defok.sh \ No newline at end of file diff --git a/src/dbSta/test/save_ok b/src/dbSta/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/dbSta/test/save_ok +++ b/src/dbSta/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index 1b8eb203e4c..405462d0361 100755 --- a/test/regression +++ b/test/regression @@ -35,7 +35,6 @@ proc define_tool_script { tool script } { # roughly flow order define_tool_script "OpenDB" "src/odb/test/regression" -define_tool_script "dbSta" "src/dbSta/test/regression" define_tool_script "stt" "src/stt/test/regression" define_tool_script "ifp" "src/ifp/test/regression" define_tool_script "tap" "src/tap/test/regression" From 93ecb48d304cb36815a4a387737785d298512462 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:12:16 -0700 Subject: [PATCH 16/98] dft: move to ctest Signed-off-by: Peter Gadfort --- src/dft/test/regression | 2 +- src/dft/test/regression_tests.tcl | 14 -------------- src/dft/test/save_ok | 2 +- test/regression | 1 - 4 files changed, 2 insertions(+), 17 deletions(-) delete mode 100644 src/dft/test/regression_tests.tcl diff --git a/src/dft/test/regression b/src/dft/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/dft/test/regression +++ b/src/dft/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/dft/test/regression_tests.tcl b/src/dft/test/regression_tests.tcl deleted file mode 100644 index a2deb1e4928..00000000000 --- a/src/dft/test/regression_tests.tcl +++ /dev/null @@ -1,14 +0,0 @@ -record_tests { - one_cell_sky130 - one_cell_nangate45 - sub_modules_sky130 - place_sort_sky130 - scan_architect_no_mix_sky130 - scan_architect_clock_mix_sky130 - scan_architect_register_bank_no_clock_mix_sky130 - scandef_sky130 - scandef_core_sky130 - max_chain_count_sky130 - #dft_man_tcl_check - #dft_readme_msgs_check -} diff --git a/src/dft/test/save_ok b/src/dft/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/dft/test/save_ok +++ b/src/dft/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index 405462d0361..0723d2cec54 100755 --- a/test/regression +++ b/test/regression @@ -56,7 +56,6 @@ define_tool_script "rmp" "src/rmp/test/regression" define_tool_script "upf" "src/upf/test/regression" define_tool_script "utl" "src/utl/test/regression" define_tool_script "fin" "src/fin/test/regression" -define_tool_script "dft" "src/dft/test/regression" define_tool_script "gui" "src/gui/test/regression" proc run_openroad_tests { } { From be37880f80d6502a1aece1bc7fb50136dfc17c08 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:13:10 -0700 Subject: [PATCH 17/98] dpl: move to ctest Signed-off-by: Peter Gadfort --- src/dpl/test/regression | 2 +- src/dpl/test/regression_tests.tcl | 69 ------------------------------- src/dpl/test/save_defok | 2 +- src/dpl/test/save_ok | 2 +- test/regression | 1 - 5 files changed, 3 insertions(+), 73 deletions(-) delete mode 100644 src/dpl/test/regression_tests.tcl diff --git a/src/dpl/test/regression b/src/dpl/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/dpl/test/regression +++ b/src/dpl/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/dpl/test/regression_tests.tcl b/src/dpl/test/regression_tests.tcl deleted file mode 100644 index b0333d32121..00000000000 --- a/src/dpl/test/regression_tests.tcl +++ /dev/null @@ -1,69 +0,0 @@ -record_tests { - aes - cell_on_block1 - cell_on_block2 - check1 - check2 - check3 - check4 - check5 - check6 - check7 - check8 - check9 - fence01 - fence02 - fence03 - fillers1 - fillers2 - fillers3 - fillers4 - fillers5 - fillers6 - fillers7 - fillers8 - fillers9 - fillers2_verbose - fillers9_verbose - fragmented_row01 - fragmented_row02 - fragmented_row03 - fragmented_row04 - gcd - hybrid_cells - hybrid_cells2 - ibex - max_disp1 - mirror1 - mirror2 - mirror3 - multi_height_one_site_gap_disallow - multi_height_rows - obstruction1 - obstruction2 - one_site_gap_disallow - pad01 - pad02 - pad03 - pad04 - pad05 - pad06 - pad07 - pad08 - regions1 - regions2 - regions3 - report_failures - simple01 - simple02 - simple03 - simple04 - simple05 - simple07 - simple08 - simple09 - simple10 - blockage01 - #dpl_man_tcl_check - #dpl_readme_msgs_check -} diff --git a/src/dpl/test/save_defok b/src/dpl/test/save_defok index 899db325246..7ee49ae334f 120000 --- a/src/dpl/test/save_defok +++ b/src/dpl/test/save_defok @@ -1 +1 @@ -../../../test/shared/save_defok \ No newline at end of file +../../../test/shared/save_defok.sh \ No newline at end of file diff --git a/src/dpl/test/save_ok b/src/dpl/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/dpl/test/save_ok +++ b/src/dpl/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index 0723d2cec54..3de032d4955 100755 --- a/test/regression +++ b/test/regression @@ -46,7 +46,6 @@ define_tool_script "mpl2" "src/mpl2/test/regression" define_tool_script "par" "src/par/test/regression" define_tool_script "gpl" "src/gpl/test/regression" define_tool_script "rsz" "src/rsz/test/regression" -define_tool_script "dpl" "src/dpl/test/regression" define_tool_script "dpo" "src/dpo/test/regression" define_tool_script "grt" "src/grt/test/regression" define_tool_script "rcx" "src/rcx/test/regression" From 3c1b3c27c81807f48f67956b0f14893916334dd6 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:13:56 -0700 Subject: [PATCH 18/98] utl: move to ctest Signed-off-by: Peter Gadfort --- src/utl/test/regression | 2 +- src/utl/test/regression_tests.tcl | 32 ------------------------------- src/utl/test/save_ok | 2 +- test/regression | 1 - 4 files changed, 2 insertions(+), 35 deletions(-) delete mode 100644 src/utl/test/regression_tests.tcl diff --git a/src/utl/test/regression b/src/utl/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/utl/test/regression +++ b/src/utl/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/utl/test/regression_tests.tcl b/src/utl/test/regression_tests.tcl deleted file mode 100644 index d0e83dd56ac..00000000000 --- a/src/utl/test/regression_tests.tcl +++ /dev/null @@ -1,32 +0,0 @@ -record_tests { - test_info - test_error - test_suppress_message - test_metrics - logger_max_messages - logger_redirection - logger_redirection_nonewline - tee - tee_fails - #utl_man_tcl_check - #utl_readme_msgs_check - #test_error_exception -} - -record_pass_fail_tests { - cpp_tests -} - -# future_tests -# # test_clear_metrics_stage -# # test_critical -# # test_error -# # test_metric -# # test_metric_float -# # test_metric_integer -# # test_open_metrics -# # test_pop_metrics_stage -# # test_push_metrics_stage -# # test_report -# # test_set_metrics_stage -# # test_warn diff --git a/src/utl/test/save_ok b/src/utl/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/utl/test/save_ok +++ b/src/utl/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index 3de032d4955..98880b7d61a 100755 --- a/test/regression +++ b/test/regression @@ -53,7 +53,6 @@ define_tool_script "psm" "src/psm/test/regression" define_tool_script "drt" "src/drt/test/regression" define_tool_script "rmp" "src/rmp/test/regression" define_tool_script "upf" "src/upf/test/regression" -define_tool_script "utl" "src/utl/test/regression" define_tool_script "fin" "src/fin/test/regression" define_tool_script "gui" "src/gui/test/regression" From 96b0362cb1a42eeb479f612643722da90e30cd46 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:14:24 -0700 Subject: [PATCH 19/98] upf: move to ctest Signed-off-by: Peter Gadfort --- src/upf/test/regression | 2 +- src/upf/test/regression_tests.tcl | 6 ------ src/upf/test/save_ok | 2 +- test/regression | 1 - 4 files changed, 2 insertions(+), 9 deletions(-) delete mode 100644 src/upf/test/regression_tests.tcl diff --git a/src/upf/test/regression b/src/upf/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/upf/test/regression +++ b/src/upf/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/upf/test/regression_tests.tcl b/src/upf/test/regression_tests.tcl deleted file mode 100644 index a019a1e4d65..00000000000 --- a/src/upf/test/regression_tests.tcl +++ /dev/null @@ -1,6 +0,0 @@ -record_tests { - levelshifter - write - #upf_man_tcl_check - #upf_readme_msgs_check -} diff --git a/src/upf/test/save_ok b/src/upf/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/upf/test/save_ok +++ b/src/upf/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index 98880b7d61a..0d43b6e0041 100755 --- a/test/regression +++ b/test/regression @@ -52,7 +52,6 @@ define_tool_script "rcx" "src/rcx/test/regression" define_tool_script "psm" "src/psm/test/regression" define_tool_script "drt" "src/drt/test/regression" define_tool_script "rmp" "src/rmp/test/regression" -define_tool_script "upf" "src/upf/test/regression" define_tool_script "fin" "src/fin/test/regression" define_tool_script "gui" "src/gui/test/regression" From b8ecebb4e378961fd2e6ed8abd233cde4b83665f Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:15:09 -0700 Subject: [PATCH 20/98] tap: move to ctest Signed-off-by: Peter Gadfort --- src/tap/test/regression | 2 +- src/tap/test/regression_tests.tcl | 27 --------------------------- src/tap/test/save_defok | 2 +- src/tap/test/save_ok | 2 +- test/regression | 1 - 5 files changed, 3 insertions(+), 31 deletions(-) delete mode 100644 src/tap/test/regression_tests.tcl diff --git a/src/tap/test/regression b/src/tap/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/tap/test/regression +++ b/src/tap/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/tap/test/regression_tests.tcl b/src/tap/test/regression_tests.tcl deleted file mode 100644 index ec4945c1c8e..00000000000 --- a/src/tap/test/regression_tests.tcl +++ /dev/null @@ -1,27 +0,0 @@ -record_tests { - aes_gf180 - avoid_overlap - boundary_macros - boundary_macros_auto_select - boundary_macros_separate - boundary_macros_tapcell - cut_rows - cut_rows_min_width - cut_rows_with_endcaps - disallow_one_site_gaps - gcd_asap7 - gcd_fakeram - gcd_nangate45 - gcd_prefix - gcd_ripup - gcd_sky130 - gcd_sky130_separate - invalid_cells - jpeg_gf180 - multiple_calls - no_endcap - region1 - symmetry - #tap_man_tcl_check - #tap_readme_msgs_check -} diff --git a/src/tap/test/save_defok b/src/tap/test/save_defok index 899db325246..7ee49ae334f 120000 --- a/src/tap/test/save_defok +++ b/src/tap/test/save_defok @@ -1 +1 @@ -../../../test/shared/save_defok \ No newline at end of file +../../../test/shared/save_defok.sh \ No newline at end of file diff --git a/src/tap/test/save_ok b/src/tap/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/tap/test/save_ok +++ b/src/tap/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index 0d43b6e0041..fa4e8aa46ed 100755 --- a/test/regression +++ b/test/regression @@ -37,7 +37,6 @@ proc define_tool_script { tool script } { define_tool_script "OpenDB" "src/odb/test/regression" define_tool_script "stt" "src/stt/test/regression" define_tool_script "ifp" "src/ifp/test/regression" -define_tool_script "tap" "src/tap/test/regression" define_tool_script "ppl" "src/ppl/test/regression" define_tool_script "pdn" "src/pdn/test/regression" define_tool_script "pad" "src/pad/test/regression" From ef28bafc3ab567ba7e024bf2e06f8b4b8464e329 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:15:47 -0700 Subject: [PATCH 21/98] stt: move to ctest Signed-off-by: Peter Gadfort --- src/stt/test/regression | 2 +- src/stt/test/regression_tests.tcl | 11 ----------- src/stt/test/save_ok | 2 +- test/regression | 1 - 4 files changed, 2 insertions(+), 14 deletions(-) delete mode 100644 src/stt/test/regression_tests.tcl diff --git a/src/stt/test/regression b/src/stt/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/stt/test/regression +++ b/src/stt/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/stt/test/regression_tests.tcl b/src/stt/test/regression_tests.tcl deleted file mode 100644 index c2ebe68d0e9..00000000000 --- a/src/stt/test/regression_tests.tcl +++ /dev/null @@ -1,11 +0,0 @@ -record_tests { - flute1 - flute_gcd - check - parse_clocks - pd1 - pd2 - pd_gcd - #stt_man_tcl_check - #stt_readme_msgs_check -} diff --git a/src/stt/test/save_ok b/src/stt/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/stt/test/save_ok +++ b/src/stt/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index fa4e8aa46ed..a0c598b8fc3 100755 --- a/test/regression +++ b/test/regression @@ -35,7 +35,6 @@ proc define_tool_script { tool script } { # roughly flow order define_tool_script "OpenDB" "src/odb/test/regression" -define_tool_script "stt" "src/stt/test/regression" define_tool_script "ifp" "src/ifp/test/regression" define_tool_script "ppl" "src/ppl/test/regression" define_tool_script "pdn" "src/pdn/test/regression" From 00ccb3d601008da04505fdbd2b0fb31deeb7ee0a Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:16:28 -0700 Subject: [PATCH 22/98] rsz: move to ctest Signed-off-by: Peter Gadfort --- src/rsz/test/regression | 2 +- src/rsz/test/regression_tests.tcl | 134 ------------------------------ src/rsz/test/save_defok | 2 +- src/rsz/test/save_ok | 2 +- test/regression | 1 - 5 files changed, 3 insertions(+), 138 deletions(-) delete mode 100644 src/rsz/test/regression_tests.tcl diff --git a/src/rsz/test/regression b/src/rsz/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/rsz/test/regression +++ b/src/rsz/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/rsz/test/regression_tests.tcl b/src/rsz/test/regression_tests.tcl deleted file mode 100644 index aaece0e74bf..00000000000 --- a/src/rsz/test/regression_tests.tcl +++ /dev/null @@ -1,134 +0,0 @@ -record_tests { - clone_flat - clone_hier - pinswap_flat - pinswap_hier - split_load_hier - resize1_hier - repair_hold1_hier - buffer_ports1 - buffer_ports3 - buffer_ports4 - buffer_ports5 - buffer_ports6 - buffer_ports7 - buffer_ports8 - buffer_varying_lengths - eliminate_dead_logic1 - eqy_repair_setup2 - eqy_repair_setup5 - fanin_fanout1 - gain_buffering1 - make_parasitics1 - make_parasitics2 - make_parasitics3 - make_parasitics4 - make_parasitics5 - make_parasitics6 - pin_swap1 - resize1 - resize4 - resize5 - resize6 - resize_slack1 - resize_slack2 - resize_slack3 - remove_buffers1 - remove_buffers2 - remove_buffers3 - repair_clk_nets1 - repair_clk_inverters1 - repair_cap1 - repair_cap2 - repair_cap3 - repair_design1 - repair_design2 - repair_design3 - repair_design4 - repair_design5 - repair_fanout1 - repair_fanout2 - repair_fanout3 - repair_fanout4 - repair_fanout5 - repair_fanout6 - repair_fanout7 - repair_fanout8 - repair_hold1 - repair_hold2 - repair_hold3 - repair_hold4 - repair_hold5 - repair_hold6 - repair_hold7 - repair_hold8 - repair_hold9 - repair_hold10 - repair_hold11 - repair_hold12 - repair_hold13 - repair_hold14 - repair_hold15 - repair_setup1 - repair_setup2 - repair_setup3 - repair_setup4 - repair_setup4_hier - repair_setup4_flat - repair_setup5 - repair_setup6 - repair_setup7 - repair_setup8 - repair_slew1 - repair_slew2 - repair_slew3 - repair_slew4 - repair_slew5 - repair_slew6 - repair_slew7 - repair_slew8 - repair_slew9 - repair_slew10 - repair_slew11 - repair_slew12 - repair_slew13 - repair_slew14 - repair_slew15 - repair_slew16 - repair_slew17 - report_floating_nets1 - report_floating_nets2 - report_floating_nets3 - repair_tie1 - repair_tie2 - repair_tie3 - repair_tie4 - repair_tie5 - repair_tie6 - repair_tie7 - repair_tie8 - repair_wire1 - repair_wire2 - repair_wire3 - repair_wire4 - repair_wire5 - repair_wire6 - repair_wire7 - repair_wire8 - repair_wire9 - repair_wire10 - repair_wire11 - gcd_resize - repair_design3_verbose - repair_setup4_verbose - repair_hold9_verbose - set_dont_touch1 - set_dont_use1 - repair_setup_undo - #rsz_man_tcl_check - #rsz_readme_msgs_check -} - -record_pass_fail_tests { - cpp_tests -} diff --git a/src/rsz/test/save_defok b/src/rsz/test/save_defok index 899db325246..7ee49ae334f 120000 --- a/src/rsz/test/save_defok +++ b/src/rsz/test/save_defok @@ -1 +1 @@ -../../../test/shared/save_defok \ No newline at end of file +../../../test/shared/save_defok.sh \ No newline at end of file diff --git a/src/rsz/test/save_ok b/src/rsz/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/rsz/test/save_ok +++ b/src/rsz/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index a0c598b8fc3..a565472b727 100755 --- a/test/regression +++ b/test/regression @@ -43,7 +43,6 @@ define_tool_script "mpl" "src/mpl/test/regression" define_tool_script "mpl2" "src/mpl2/test/regression" define_tool_script "par" "src/par/test/regression" define_tool_script "gpl" "src/gpl/test/regression" -define_tool_script "rsz" "src/rsz/test/regression" define_tool_script "dpo" "src/dpo/test/regression" define_tool_script "grt" "src/grt/test/regression" define_tool_script "rcx" "src/rcx/test/regression" From 33ba4fc21dde1fbf507094afb5259de8b3150c94 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:17:00 -0700 Subject: [PATCH 23/98] rmp: move to ctest Signed-off-by: Peter Gadfort --- src/rmp/test/regression | 2 +- src/rmp/test/regression_tests.tcl | 14 -------------- src/rmp/test/save_ok | 2 +- test/regression | 1 - 4 files changed, 2 insertions(+), 17 deletions(-) delete mode 100644 src/rmp/test/regression_tests.tcl diff --git a/src/rmp/test/regression b/src/rmp/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/rmp/test/regression +++ b/src/rmp/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/rmp/test/regression_tests.tcl b/src/rmp/test/regression_tests.tcl deleted file mode 100644 index 8d3b33aae53..00000000000 --- a/src/rmp/test/regression_tests.tcl +++ /dev/null @@ -1,14 +0,0 @@ -record_tests { - gcd_restructure - const_cell_removal - blif_writer - blif_writer_input_output - blif_writer_consts - blif_writer_hanging - blif_writer_sequential - blif_reader - blif_reader_const - blif_reader_sequential - #rmp_man_tcl_check - #rmp_readme_msgs_check -} diff --git a/src/rmp/test/save_ok b/src/rmp/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/rmp/test/save_ok +++ b/src/rmp/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index a565472b727..d50ddf77585 100755 --- a/test/regression +++ b/test/regression @@ -48,7 +48,6 @@ define_tool_script "grt" "src/grt/test/regression" define_tool_script "rcx" "src/rcx/test/regression" define_tool_script "psm" "src/psm/test/regression" define_tool_script "drt" "src/drt/test/regression" -define_tool_script "rmp" "src/rmp/test/regression" define_tool_script "fin" "src/fin/test/regression" define_tool_script "gui" "src/gui/test/regression" From 6d0aa5183b1d969fad733d43f8c195648d33dc3d Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:17:24 -0700 Subject: [PATCH 24/98] rcx: move to ctest Signed-off-by: Peter Gadfort --- src/rcx/test/regression | 2 +- src/rcx/test/regression_tests.tcl | 13 ------------- src/rcx/test/save_ok | 2 +- test/regression | 1 - 4 files changed, 2 insertions(+), 16 deletions(-) delete mode 100644 src/rcx/test/regression_tests.tcl diff --git a/src/rcx/test/regression b/src/rcx/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/rcx/test/regression +++ b/src/rcx/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/rcx/test/regression_tests.tcl b/src/rcx/test/regression_tests.tcl deleted file mode 100644 index c200c7d4027..00000000000 --- a/src/rcx/test/regression_tests.tcl +++ /dev/null @@ -1,13 +0,0 @@ -record_tests { - generate_pattern - #generate_rules - ext_pattern - gcd - 45_gcd - names - #rcx_man_tcl_check - #rcx_readme_msgs_check -} -record_pass_fail_tests { - rcx_unit_test -} diff --git a/src/rcx/test/save_ok b/src/rcx/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/rcx/test/save_ok +++ b/src/rcx/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index d50ddf77585..c303b19f7ac 100755 --- a/test/regression +++ b/test/regression @@ -45,7 +45,6 @@ define_tool_script "par" "src/par/test/regression" define_tool_script "gpl" "src/gpl/test/regression" define_tool_script "dpo" "src/dpo/test/regression" define_tool_script "grt" "src/grt/test/regression" -define_tool_script "rcx" "src/rcx/test/regression" define_tool_script "psm" "src/psm/test/regression" define_tool_script "drt" "src/drt/test/regression" define_tool_script "fin" "src/fin/test/regression" From 7ed5e111dd136167e374c0ee177c0c4a3eeaa2fd Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:17:54 -0700 Subject: [PATCH 25/98] psm: move to ctest Signed-off-by: Peter Gadfort --- src/psm/test/regression | 2 +- src/psm/test/regression_tests.tcl | 32 ------------------------------- src/psm/test/save_defok | 2 +- src/psm/test/save_ok | 2 +- test/regression | 1 - 5 files changed, 3 insertions(+), 36 deletions(-) delete mode 100644 src/psm/test/regression_tests.tcl diff --git a/src/psm/test/regression b/src/psm/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/psm/test/regression +++ b/src/psm/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/psm/test/regression_tests.tcl b/src/psm/test/regression_tests.tcl deleted file mode 100644 index a4e7481508e..00000000000 --- a/src/psm/test/regression_tests.tcl +++ /dev/null @@ -1,32 +0,0 @@ -record_tests { - aes_test_vdd - aes_test_vss - gcd_test_vdd - gcd_no_vsrc - gcd_write_sp_test_vdd - gcd_all_vss - gcd_em_test_vdd - gcd_vss_no_vsrc - gcd_sky130_vdd - aes_asap7_vdd - check_power_grid - check_power_grid_floorplanning - check_power_grid_disconnected - check_power_grid_ok_disconnected - check_power_grid_macros - check_power_grid_disconnected_macro - corners - aes_test_bterms - aes_test_multiple_bterms - zerosoc_pads - zerosoc_pads_check_only - zerosoc_pads_check_only_disconnected - pad_connected_by_abutment - switch_top_grid - top_grid_settings - insert_decap1 - insert_decap2 - insert_decap_with_padding1 - #psm_man_tcl_check - #psm_readme_msgs_check -} diff --git a/src/psm/test/save_defok b/src/psm/test/save_defok index 899db325246..7ee49ae334f 120000 --- a/src/psm/test/save_defok +++ b/src/psm/test/save_defok @@ -1 +1 @@ -../../../test/shared/save_defok \ No newline at end of file +../../../test/shared/save_defok.sh \ No newline at end of file diff --git a/src/psm/test/save_ok b/src/psm/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/psm/test/save_ok +++ b/src/psm/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index c303b19f7ac..07123145dfc 100755 --- a/test/regression +++ b/test/regression @@ -45,7 +45,6 @@ define_tool_script "par" "src/par/test/regression" define_tool_script "gpl" "src/gpl/test/regression" define_tool_script "dpo" "src/dpo/test/regression" define_tool_script "grt" "src/grt/test/regression" -define_tool_script "psm" "src/psm/test/regression" define_tool_script "drt" "src/drt/test/regression" define_tool_script "fin" "src/fin/test/regression" define_tool_script "gui" "src/gui/test/regression" From 0866d922e02df4e8fd7fa4bd8ae28a98708f2fda Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:18:29 -0700 Subject: [PATCH 26/98] ppl: move to ctest Signed-off-by: Peter Gadfort --- src/ppl/test/regression | 2 +- src/ppl/test/regression_tests.tcl | 122 ------------------------------ src/ppl/test/save_defok | 2 +- src/ppl/test/save_ok | 2 +- test/regression | 1 - 5 files changed, 3 insertions(+), 126 deletions(-) delete mode 100644 src/ppl/test/regression_tests.tcl diff --git a/src/ppl/test/regression b/src/ppl/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/ppl/test/regression +++ b/src/ppl/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/ppl/test/regression_tests.tcl b/src/ppl/test/regression_tests.tcl deleted file mode 100644 index 18b9c573dcd..00000000000 --- a/src/ppl/test/regression_tests.tcl +++ /dev/null @@ -1,122 +0,0 @@ -record_tests { - add_constraint_debug - add_constraint1 - add_constraint2 - add_constraint3 - add_constraint4 - add_constraint5 - add_constraint6 - add_constraint7 - add_constraint8 - add_constraint9 - add_constraint10 - add_constraint11 - add_constraint12 - add_constraint13 - add_constraint14 - add_constraint15 - add_constraint16 - add_constraint_error1 - add_constraint_error2 - add_constraint_error3 - add_constraint_error4 - add_constraint_error5 - add_constraint_error6 - add_constraint_error7 - add_constraint_error8 - add_constraint_error9 - annealing1 - annealing2 - annealing3 - annealing4 - annealing_constraint1 - annealing_constraint2 - annealing_constraint3 - annealing_constraint4 - annealing_constraint5 - annealing_constraint6 - annealing_constraint7 - annealing_constraint8 - annealing_large_groups1 - annealing_large_groups2 - annealing_mirrored1 - annealing_mirrored2 - annealing_mirrored3 - annealing_mirrored4 - annealing_mirrored5 - blocked_region - cells_not_placed - exclude1 - exclude2 - exclude3 - gcd - group_pins1 - group_pins2 - group_pins3 - group_pins4 - group_pins5 - group_pins6 - group_pins7 - group_pins8 - group_pins9 - group_pins10 - group_pins_error1 - group_pins_warn1 - invalid_layer - large_groups1 - large_groups2 - large_groups3 - large_groups4 - macro_not_placed - macro_not_placed_random - min_dist_in_tracks1 - min_dist_in_tracks2 - multi_layers - multiple_calls - no_instance_pins - no_pins - no_tracks - on_grid - partial_tracks_error - partial_tracks - pin_length - pin_length_error - pin_extension - pin_thick_multiplier - place_pin1 - place_pin2 - place_pin3 - place_pin4 - place_pin5 - place_pin6 - place_pin7 - place_pin_error1 - place_pin_error2 - place_pin_error3 - random1 - random2 - random3 - random4 - random5 - random6 - random7 - random8 - random9 - top_layer1 - top_layer2 - top_layer3 - top_layer4 - top_layer5 - top_layer6 - top_layer7 - top_layer_error - top_layer_error2 - write_pin_placement1 - write_pin_placement2 - write_pin_placement3 - write_pin_placement4 - write_pin_placement5 - write_pin_placement6 - #ppl_man_tcl_check - #ppl_readme_msgs_check -} diff --git a/src/ppl/test/save_defok b/src/ppl/test/save_defok index 899db325246..7ee49ae334f 120000 --- a/src/ppl/test/save_defok +++ b/src/ppl/test/save_defok @@ -1 +1 @@ -../../../test/shared/save_defok \ No newline at end of file +../../../test/shared/save_defok.sh \ No newline at end of file diff --git a/src/ppl/test/save_ok b/src/ppl/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/ppl/test/save_ok +++ b/src/ppl/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index 07123145dfc..f1345cec87e 100755 --- a/test/regression +++ b/test/regression @@ -36,7 +36,6 @@ proc define_tool_script { tool script } { # roughly flow order define_tool_script "OpenDB" "src/odb/test/regression" define_tool_script "ifp" "src/ifp/test/regression" -define_tool_script "ppl" "src/ppl/test/regression" define_tool_script "pdn" "src/pdn/test/regression" define_tool_script "pad" "src/pad/test/regression" define_tool_script "mpl" "src/mpl/test/regression" From 26f635355c06507d353bc14f389457ffc7319732 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:19:21 -0700 Subject: [PATCH 27/98] pdn: move to ctest Signed-off-by: Peter Gadfort --- src/pdn/test/regression | 2 +- src/pdn/test/regression_tests.tcl | 124 ------------------------------ src/pdn/test/save_defok | 2 +- src/pdn/test/save_ok | 2 +- test/regression | 1 - 5 files changed, 3 insertions(+), 128 deletions(-) delete mode 100644 src/pdn/test/regression_tests.tcl diff --git a/src/pdn/test/regression b/src/pdn/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/pdn/test/regression +++ b/src/pdn/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/pdn/test/regression_tests.tcl b/src/pdn/test/regression_tests.tcl deleted file mode 100644 index fc3b3c2a6a9..00000000000 --- a/src/pdn/test/regression_tests.tcl +++ /dev/null @@ -1,124 +0,0 @@ -# Record tests in /test -record_tests { - reset - report - ripup - names - - min_width - max_width - min_spacing - widthtable - design_width - offgrid - - core_grid - core_grid_with_rings - core_grid_start_power - core_grid_start_power_strap_ground - core_grid_with_rings_with_straps - core_grid_with_single_layer_rings - core_grid_dual_followpins - core_grid_dual_followpins_error - core_grid_with_dual_rings - core_grid_with_rings_connect - core_grid_cut_pitch - core_grid_snap - core_grid_via_snap - core_grid_split_cuts - core_grid_with_rings_with_straps_rings_over_core - core_grid_with_routing_obstructions - core_grid_adjacentcuts - core_grid_with_fixed_pins - core_grid_bad_metal_specs - - core_grid_obstruction - - core_grid_auto_domain - core_grid_auto_domain_multiple_nets - - core_grid_extend_to_boundary - core_grid_extend_to_boundary_no_pins - core_grid_with_M7_pins - core_grid_with_M6_min_area - - core_grid_strap_count - - core_grid_no_trim - - core_grid_offset_strap - core_grid_with_rings_with_limit_straps - - core_grid_failed_via_report - - macros - macros_with_halo - macros_cells - macros_cells_orient - macros_with_rings - macros_narrow_channel - macros_narrow_channel_large_spacing - macros_narrow_channel_repair_overlap - macros_narrow_channel_overlap - macros_add_twice - macros_cells_extend_boundary - macros_cells_no_grid - macros_narrow_channel_jog - macros_different_nets - macros_grid_through - macros_grid_through_without_middle - macros_cells_dont_touch - macros_cells_overlapping_ports - macros_cells_not_fixed - macros_cells_via_failure - repair_channel_inf_loop - - region_temp_sensor - region_secondary_nets - region_non_rect - - pads_black_parrot - pads_black_parrot_offset - pads_black_parrot_no_connect - pads_black_parrot_limit_connect - pads_black_parrot_flipchip - pads_black_parrot_flipchip_connect_bumps - pads_black_parrot_flipchip_connect_overpads - pads_black_parrot_max_width - - asap7_vias - asap7_vias_cutclass - asap7_no_via_generate - asap7_vias_arrayspacing - asap7_vias_arrayspacing_notfirst - asap7_vias_arrayspacing_partial - asap7_vias_arrayspacing_3_layer - asap7_vias_max_rows_columns - asap7_vias_dont_use - asap7_taper - asap7_offcenter_via - asap7_no_via_generate_v1_snapped - asap7_failed_macro_grid - asap7_vias_fixed_vias - - existing - - power_switch - power_switch_star - power_switch_daisy - power_switch_regions - power_switch_cut_rows - power_switch_upf_error - power_switch_upf_star - power_switch_upf_daisy - power_switch_upf_regions - - repair_vias - - sroute_test - - bpin_removal - - #pdn_man_tcl_check - #pdn_readme_msgs_check -} diff --git a/src/pdn/test/save_defok b/src/pdn/test/save_defok index 899db325246..7ee49ae334f 120000 --- a/src/pdn/test/save_defok +++ b/src/pdn/test/save_defok @@ -1 +1 @@ -../../../test/shared/save_defok \ No newline at end of file +../../../test/shared/save_defok.sh \ No newline at end of file diff --git a/src/pdn/test/save_ok b/src/pdn/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/pdn/test/save_ok +++ b/src/pdn/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index f1345cec87e..56656695924 100755 --- a/test/regression +++ b/test/regression @@ -36,7 +36,6 @@ proc define_tool_script { tool script } { # roughly flow order define_tool_script "OpenDB" "src/odb/test/regression" define_tool_script "ifp" "src/ifp/test/regression" -define_tool_script "pdn" "src/pdn/test/regression" define_tool_script "pad" "src/pad/test/regression" define_tool_script "mpl" "src/mpl/test/regression" define_tool_script "mpl2" "src/mpl2/test/regression" From 553b61acfb76afec50811b053bcc5cd5286db2de Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:19:46 -0700 Subject: [PATCH 28/98] par: move to ctest Signed-off-by: Peter Gadfort --- src/par/test/regression | 2 +- src/par/test/regression_tests.tcl | 6 ------ src/par/test/save_ok | 2 +- test/regression | 1 - 4 files changed, 2 insertions(+), 9 deletions(-) delete mode 100644 src/par/test/regression_tests.tcl diff --git a/src/par/test/regression b/src/par/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/par/test/regression +++ b/src/par/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/par/test/regression_tests.tcl b/src/par/test/regression_tests.tcl deleted file mode 100644 index b060e799383..00000000000 --- a/src/par/test/regression_tests.tcl +++ /dev/null @@ -1,6 +0,0 @@ -record_tests { - read_part - partition_gcd - #par_man_tcl_check - #par_readme_msgs_check -} diff --git a/src/par/test/save_ok b/src/par/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/par/test/save_ok +++ b/src/par/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index 56656695924..1ad66cb71f5 100755 --- a/test/regression +++ b/test/regression @@ -39,7 +39,6 @@ define_tool_script "ifp" "src/ifp/test/regression" define_tool_script "pad" "src/pad/test/regression" define_tool_script "mpl" "src/mpl/test/regression" define_tool_script "mpl2" "src/mpl2/test/regression" -define_tool_script "par" "src/par/test/regression" define_tool_script "gpl" "src/gpl/test/regression" define_tool_script "dpo" "src/dpo/test/regression" define_tool_script "grt" "src/grt/test/regression" From 5aef1885a48ff6e3eccb9846cd3bab5c5404f043 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:20:33 -0700 Subject: [PATCH 29/98] pad: move to ctest Signed-off-by: Peter Gadfort --- src/pad/test/regression | 2 +- src/pad/test/regression_tests.tcl | 54 ------------------------------- src/pad/test/save_defok | 2 +- src/pad/test/save_ok | 2 +- test/regression | 1 - 5 files changed, 3 insertions(+), 58 deletions(-) delete mode 100644 src/pad/test/regression_tests.tcl diff --git a/src/pad/test/regression b/src/pad/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/pad/test/regression +++ b/src/pad/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/pad/test/regression_tests.tcl b/src/pad/test/regression_tests.tcl deleted file mode 100644 index f2d45a2386f..00000000000 --- a/src/pad/test/regression_tests.tcl +++ /dev/null @@ -1,54 +0,0 @@ -record_tests { - bump_array_make - bump_array_remove - bump_array_remove_single - bump_array_make_single_pitch - bump_array_make_error - - make_corner_sites - make_io_sites - make_io_sites_different_sites - make_io_sites_rotations - non_top_layer - place_pad - place_pad_hv - place_pad_with_bumps - place_pad_outsideofrow - place_bondpad - place_bondpad_stagger - place_pad_no_master - place_pad_wrong_master - assign_bumps - assign_bumps_two_pins - - connect_by_abutment - connect_by_abutment_with_single_pinnet - - rdl_route - rdl_route_ports - rdl_route_failed - rdl_route_max_iterations - rdl_route_assignments - rdl_route_45 - rdl_route_45_cost - rdl_route_45_separate - rdl_route_via - rdl_route_bump_via - rdl_route_invalid - rdl_route_45_with_2port_bump - rdl_route_45_with_oct_bump - rdl_route_single_target - rdl_route_bump_to_bump_only - - skywater130_overlapping_filler - - skywater130_caravel - skywater130_coyote_tc - - place_pads_uniform - place_pads_too_many - place_pads_bumps - - #pad_man_tcl_check - #pad_readme_msgs_check -} diff --git a/src/pad/test/save_defok b/src/pad/test/save_defok index 899db325246..7ee49ae334f 120000 --- a/src/pad/test/save_defok +++ b/src/pad/test/save_defok @@ -1 +1 @@ -../../../test/shared/save_defok \ No newline at end of file +../../../test/shared/save_defok.sh \ No newline at end of file diff --git a/src/pad/test/save_ok b/src/pad/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/pad/test/save_ok +++ b/src/pad/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index 1ad66cb71f5..e8f3d4fda0a 100755 --- a/test/regression +++ b/test/regression @@ -36,7 +36,6 @@ proc define_tool_script { tool script } { # roughly flow order define_tool_script "OpenDB" "src/odb/test/regression" define_tool_script "ifp" "src/ifp/test/regression" -define_tool_script "pad" "src/pad/test/regression" define_tool_script "mpl" "src/mpl/test/regression" define_tool_script "mpl2" "src/mpl2/test/regression" define_tool_script "gpl" "src/gpl/test/regression" From d2682d60288e177372bfb94b588340a26511972b Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:21:05 -0700 Subject: [PATCH 30/98] odb: move to ctest Signed-off-by: Peter Gadfort --- src/odb/test/regression | 2 +- src/odb/test/regression_tests.tcl | 59 ------------------------------- src/odb/test/save_defok | 2 +- src/odb/test/save_ok | 2 +- test/regression | 1 - 5 files changed, 3 insertions(+), 63 deletions(-) delete mode 100644 src/odb/test/regression_tests.tcl diff --git a/src/odb/test/regression b/src/odb/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/odb/test/regression +++ b/src/odb/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/odb/test/regression_tests.tcl b/src/odb/test/regression_tests.tcl deleted file mode 100644 index acad24b085b..00000000000 --- a/src/odb/test/regression_tests.tcl +++ /dev/null @@ -1,59 +0,0 @@ -record_tests { - bterm_hier_create - multi_tech - transform - rounding - sky130hd_multi_patterned - dont_touch - import_package - read_lef - read_db - read_zipped - create_sboxes - dump_via_rules - dump_vias - read_def - read_def58 - write_def58 - dump_nets - lef_mask - write_lef_and_def - write_lef_polygon - lef_data_access - gcd_def_access - gcd_pdn_def_access - edit_def - wire_encoder - edit_via_params - row_settings - db_read_write - check_routing_tracks - polygon - def_parser - ndr - gcd_abstract_lef - gcd_abstract_lef_with_power - read_abstract_lef - abstract_origin - write_macro_placement - smash_vias - floorplan_initialize - replace_design1 - replace_design2 - replace_design3 - design_is_routed1 - design_is_routed2 - design_is_routed3 - design_is_routed_fail1 - design_is_routed_fail2 - #odb_man_tcl_check - #odb_readme_msgs_check -} - -record_pass_fail_tests { - cpp_tests - dump_netlists - dump_netlists_withfill - parser_unit_test -} - diff --git a/src/odb/test/save_defok b/src/odb/test/save_defok index 899db325246..7ee49ae334f 120000 --- a/src/odb/test/save_defok +++ b/src/odb/test/save_defok @@ -1 +1 @@ -../../../test/shared/save_defok \ No newline at end of file +../../../test/shared/save_defok.sh \ No newline at end of file diff --git a/src/odb/test/save_ok b/src/odb/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/odb/test/save_ok +++ b/src/odb/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index e8f3d4fda0a..4f2d8f5a237 100755 --- a/test/regression +++ b/test/regression @@ -34,7 +34,6 @@ proc define_tool_script { tool script } { } # roughly flow order -define_tool_script "OpenDB" "src/odb/test/regression" define_tool_script "ifp" "src/ifp/test/regression" define_tool_script "mpl" "src/mpl/test/regression" define_tool_script "mpl2" "src/mpl2/test/regression" From ad46c64c0fda37ebc266368c0fa7c1e176c2ea08 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:21:32 -0700 Subject: [PATCH 31/98] mpl*: move to ctest Signed-off-by: Peter Gadfort --- src/mpl/test/regression | 2 +- src/mpl/test/regression_tests.tcl | 9 --------- src/mpl/test/save_defok | 2 +- src/mpl/test/save_ok | 2 +- src/mpl2/test/regression | 2 +- src/mpl2/test/regression_tests.tcl | 6 ------ src/mpl2/test/save_defok | 2 +- src/mpl2/test/save_ok | 2 +- test/regression | 2 -- 9 files changed, 6 insertions(+), 23 deletions(-) delete mode 100644 src/mpl/test/regression_tests.tcl delete mode 100644 src/mpl2/test/regression_tests.tcl diff --git a/src/mpl/test/regression b/src/mpl/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/mpl/test/regression +++ b/src/mpl/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/mpl/test/regression_tests.tcl b/src/mpl/test/regression_tests.tcl deleted file mode 100644 index 7644022c18b..00000000000 --- a/src/mpl/test/regression_tests.tcl +++ /dev/null @@ -1,9 +0,0 @@ -record_tests { - level3_01 - level3_02 - east_west1 - east_west2 - snap_layer1 - #mpl_man_tcl_check - #mpl_readme_msgs_check -} diff --git a/src/mpl/test/save_defok b/src/mpl/test/save_defok index 899db325246..7ee49ae334f 120000 --- a/src/mpl/test/save_defok +++ b/src/mpl/test/save_defok @@ -1 +1 @@ -../../../test/shared/save_defok \ No newline at end of file +../../../test/shared/save_defok.sh \ No newline at end of file diff --git a/src/mpl/test/save_ok b/src/mpl/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/mpl/test/save_ok +++ b/src/mpl/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/src/mpl2/test/regression b/src/mpl2/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/mpl2/test/regression +++ b/src/mpl2/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/mpl2/test/regression_tests.tcl b/src/mpl2/test/regression_tests.tcl deleted file mode 100644 index 16585a3f170..00000000000 --- a/src/mpl2/test/regression_tests.tcl +++ /dev/null @@ -1,6 +0,0 @@ -record_tests { - macro_only - no_unfixed_macros - #mpl2_man_tcl_check - #mpl2_readme_msgs_check -} diff --git a/src/mpl2/test/save_defok b/src/mpl2/test/save_defok index 899db325246..7ee49ae334f 120000 --- a/src/mpl2/test/save_defok +++ b/src/mpl2/test/save_defok @@ -1 +1 @@ -../../../test/shared/save_defok \ No newline at end of file +../../../test/shared/save_defok.sh \ No newline at end of file diff --git a/src/mpl2/test/save_ok b/src/mpl2/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/mpl2/test/save_ok +++ b/src/mpl2/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index 4f2d8f5a237..db9472f64be 100755 --- a/test/regression +++ b/test/regression @@ -35,8 +35,6 @@ proc define_tool_script { tool script } { # roughly flow order define_tool_script "ifp" "src/ifp/test/regression" -define_tool_script "mpl" "src/mpl/test/regression" -define_tool_script "mpl2" "src/mpl2/test/regression" define_tool_script "gpl" "src/gpl/test/regression" define_tool_script "dpo" "src/dpo/test/regression" define_tool_script "grt" "src/grt/test/regression" From 41e72e10fe6663b5dc23836a8dd1f4c22d1e19cb Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:22:01 -0700 Subject: [PATCH 32/98] ifp: move to ctest Signed-off-by: Peter Gadfort --- src/ifp/test/regression | 2 +- src/ifp/test/regression_tests.tcl | 33 ------------------------------- src/ifp/test/save_defok | 2 +- src/ifp/test/save_ok | 2 +- test/regression | 1 - 5 files changed, 3 insertions(+), 37 deletions(-) delete mode 100644 src/ifp/test/regression_tests.tcl diff --git a/src/ifp/test/regression b/src/ifp/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/ifp/test/regression +++ b/src/ifp/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/ifp/test/regression_tests.tcl b/src/ifp/test/regression_tests.tcl deleted file mode 100644 index 65912ce12e8..00000000000 --- a/src/ifp/test/regression_tests.tcl +++ /dev/null @@ -1,33 +0,0 @@ -record_tests { - hybrid_rows - hybrid_rows2 - init_floorplan1 - init_floorplan2 - init_floorplan3 - init_floorplan4 - init_floorplan5 - init_floorplan6 - init_floorplan7 - init_floorplan8 - init_floorplan9 - make_tracks1 - make_tracks2 - make_tracks3 - make_tracks4 - make_tracks5 - make_tracks6 - make_tracks7 - multi_height1 - multi_height2 - placement_blockage1 - placement_blockage2 - tiecells - upf_test - upf_shifter_test - init_floorplan_even_rows - init_floorplan_odd_rows - init_floorplan_flip_sites - #ifp_man_tcl_check - #ifp_readme_msgs_check -} - diff --git a/src/ifp/test/save_defok b/src/ifp/test/save_defok index 899db325246..7ee49ae334f 120000 --- a/src/ifp/test/save_defok +++ b/src/ifp/test/save_defok @@ -1 +1 @@ -../../../test/shared/save_defok \ No newline at end of file +../../../test/shared/save_defok.sh \ No newline at end of file diff --git a/src/ifp/test/save_ok b/src/ifp/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/ifp/test/save_ok +++ b/src/ifp/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index db9472f64be..1af62e7a84d 100755 --- a/test/regression +++ b/test/regression @@ -34,7 +34,6 @@ proc define_tool_script { tool script } { } # roughly flow order -define_tool_script "ifp" "src/ifp/test/regression" define_tool_script "gpl" "src/gpl/test/regression" define_tool_script "dpo" "src/dpo/test/regression" define_tool_script "grt" "src/grt/test/regression" From 0bfbac1857c506eb1ce17d88db24d83dbd974a1f Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:22:24 -0700 Subject: [PATCH 33/98] gui: move to ctest Signed-off-by: Peter Gadfort --- src/gui/test/regression | 2 +- src/gui/test/regression_tests.tcl | 5 ----- src/gui/test/save_ok | 2 +- test/regression | 1 - 4 files changed, 2 insertions(+), 8 deletions(-) delete mode 100644 src/gui/test/regression_tests.tcl diff --git a/src/gui/test/regression b/src/gui/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/gui/test/regression +++ b/src/gui/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/gui/test/regression_tests.tcl b/src/gui/test/regression_tests.tcl deleted file mode 100644 index ec21c551435..00000000000 --- a/src/gui/test/regression_tests.tcl +++ /dev/null @@ -1,5 +0,0 @@ -record_tests { - supported - #gui_man_tcl_check - #gui_readme_msgs_check -} diff --git a/src/gui/test/save_ok b/src/gui/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/gui/test/save_ok +++ b/src/gui/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index 1af62e7a84d..fce5152bbfe 100755 --- a/test/regression +++ b/test/regression @@ -39,7 +39,6 @@ define_tool_script "dpo" "src/dpo/test/regression" define_tool_script "grt" "src/grt/test/regression" define_tool_script "drt" "src/drt/test/regression" define_tool_script "fin" "src/fin/test/regression" -define_tool_script "gui" "src/gui/test/regression" proc run_openroad_tests { } { global tool_errors From 3bc207c40e7926109b6aa510bfd26601a55f9357 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:24:29 -0700 Subject: [PATCH 34/98] grt: move to ctest Signed-off-by: Peter Gadfort --- src/grt/test/regression | 2 +- src/grt/test/regression_tests.tcl | 79 ---------------------------- src/grt/test/save_defok | 2 +- src/grt/test/save_guideok | 87 ++++++++----------------------- src/grt/test/save_ok | 2 +- test/regression | 1 - 6 files changed, 25 insertions(+), 148 deletions(-) delete mode 100644 src/grt/test/regression_tests.tcl diff --git a/src/grt/test/regression b/src/grt/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/grt/test/regression +++ b/src/grt/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/grt/test/regression_tests.tcl b/src/grt/test/regression_tests.tcl deleted file mode 100644 index ad98c2e48f2..00000000000 --- a/src/grt/test/regression_tests.tcl +++ /dev/null @@ -1,79 +0,0 @@ -record_tests { - bus_route - clock_route - clock_route_alpha - clock_route_error1 - clock_route_error2 - congestion1 - congestion2 - congestion3 - congestion4 - congestion5 - congestion6 - congestion7 - critical_nets_percentage - est_rc1 - est_rc2 - est_rc3 - est_rc4 - gcd - gcd_flute - inst_pin_out_of_die - invalid_routing_layer - invalid_pin_placement - macro_obs_not_aligned - modeling_instance_obs - multiple_calls - ndr_1w_3s - ndr_2w_3s - no_tracks - obstruction - obs_out_of_die - overlapping_edges - pd1 - pd2 - pd3 - pd4 - pin_access1 - pin_access2 - pin_edge - pin_track_not_aligned - pre_routed1 - read_segments1 - read_segments2 - read_segments3 - read_segments4 - read_segments_error1 - read_segments_error2 - read_segments_error3 - region_adjustment - remove_buffers1 - remove_buffers2 - repair_antennas1 - repair_antennas2 - repair_antennas3 - repair_antennas4 - repair_antennas_error1 - repair_antennas_error2 - report_wire_length1 - report_wire_length2 - report_wire_length3 - report_wire_length4 - report_wire_length5 - report_wire_length6 - set_nets_to_route1 - silence - single_row - top_level_term1 - top_level_term2 - top_level_term3 - tracks1 - tracks2 - tracks3 - unplaced_inst - upper_layer_net - write_segments1 - write_segments2 - #grt_man_tcl_check - #grt_readme_msgs_check -} diff --git a/src/grt/test/save_defok b/src/grt/test/save_defok index 899db325246..7ee49ae334f 120000 --- a/src/grt/test/save_defok +++ b/src/grt/test/save_defok @@ -1 +1 @@ -../../../test/shared/save_defok \ No newline at end of file +../../../test/shared/save_defok.sh \ No newline at end of file diff --git a/src/grt/test/save_guideok b/src/grt/test/save_guideok index 528339a6cd7..373da20e960 100755 --- a/src/grt/test/save_guideok +++ b/src/grt/test/save_guideok @@ -1,14 +1,12 @@ -#!/bin/sh -# The next line is executed by /bin/sh, but not Tcl \ -exec tclsh $0 ${1+"$@"} +#!/usr/bin/env bash -############################################################################### +############################################################################ ## -## BSD 3-Clause License -## -## Copyright (c) 2019, Parallax Software, Inc. +## Copyright (c) 2024, The Regents of the University of California ## All rights reserved. ## +## BSD 3-Clause License +## ## Redistribution and use in source and binary forms, with or without ## modification, are permitted provided that the following conditions are met: ## @@ -17,7 +15,7 @@ exec tclsh $0 ${1+"$@"} ## ## * Redistributions in binary form must reproduce the above copyright notice, ## this list of conditions and the following disclaimer in the documentation -## and#or other materials provided with the distribution. +## and/or other materials provided with the distribution. ## ## * Neither the name of the copyright holder nor the names of its ## contributors may be used to endorse or promote products derived from @@ -35,60 +33,19 @@ exec tclsh $0 ${1+"$@"} ## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ## POSSIBILITY OF SUCH DAMAGE. ## -############################################################################### - -# Usage: save_guideok test1 [test2...] | failures -# Where test1 is all or the name of a tcl script in /test -# Wildcard matching with '*' and '?' in test names is supported. - -# Directory containing tests. -set test_dir [file dirname [file normalize [info script]]] -set openroad_dir [file dirname [file dirname [file dirname $test_dir]]] - -source [file join $openroad_dir "test" "regression.tcl"] -source [file join $test_dir "regression_tests.tcl"] - -proc save_guideok_main {} { - global argv - if { $argv == "help" || $argv == "-help" } { - puts {Usage: save_guideok [failures] test1 [test2]...} - } else { - if { $argv == "failures" } { - set tests [failed_tests] - } else { - set tests $argv - } - foreach test $tests { - if { [lsearch [group_tests "all"] $test] == -1 } { - puts "Error: test $test not found." - } else { - save_guideok $test - } - } - } -} - -proc save_guideok { test } { - set guideok_file [test_guideok_file $test] - set guide_file [test_guide_result_file $test] - if { [file exists $guide_file] } { - file copy -force $guide_file $guideok_file - } -} - -proc test_guideok_file { test } { - global test_dir - return [file join $test_dir "$test.guideok"] -} - -proc test_guide_result_file { test } { - global result_dir - set lang [result_lang $test] - return [file join $result_dir "$test-$lang.guide"] -} - -save_guideok_main - -# Local Variables: -# mode:tcl -# End: +############################################################################ + +set -e + +for test_name in "${@:1}" +do + if [ -f "results/${test_name}-tcl.guide" ]; then + cp "results/${test_name}-tcl.guide" "${test_name}.guideok" + echo "${test_name}" + elif [ -f "results/${test_name}-py.guide" ]; then + cp "results/${test_name}-py.guide" "${test_name}.guideok" + echo "${test_name}" + else + echo "\"${test_name}\" guide file not found" + fi +done diff --git a/src/grt/test/save_ok b/src/grt/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/grt/test/save_ok +++ b/src/grt/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index fce5152bbfe..66c7d7cc2a6 100755 --- a/test/regression +++ b/test/regression @@ -36,7 +36,6 @@ proc define_tool_script { tool script } { # roughly flow order define_tool_script "gpl" "src/gpl/test/regression" define_tool_script "dpo" "src/dpo/test/regression" -define_tool_script "grt" "src/grt/test/regression" define_tool_script "drt" "src/drt/test/regression" define_tool_script "fin" "src/fin/test/regression" From 189180c586e189989589e9e56a51b22e710e527a Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:25:07 -0700 Subject: [PATCH 35/98] gpl: move to ctest Signed-off-by: Peter Gadfort --- src/gpl/test/regression | 2 +- src/gpl/test/regression_tests.tcl | 36 ------------------------------- src/gpl/test/save_defok | 2 +- src/gpl/test/save_ok | 2 +- test/regression | 1 - 5 files changed, 3 insertions(+), 40 deletions(-) delete mode 100644 src/gpl/test/regression_tests.tcl diff --git a/src/gpl/test/regression b/src/gpl/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/gpl/test/regression +++ b/src/gpl/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/gpl/test/regression_tests.tcl b/src/gpl/test/regression_tests.tcl deleted file mode 100644 index 8a29aaa51e0..00000000000 --- a/src/gpl/test/regression_tests.tcl +++ /dev/null @@ -1,36 +0,0 @@ -record_tests { - simple01 - simple01-obs - simple01-td - simple01-td-tune - simple01-uniform - simple01-ref - simple01-skip-io - simple01-rd - simple02-rd - simple03-rd - simple04-rd - simple02 - simple03 - simple04 - simple05 - simple06 - simple07 - simple08 - simple09 - simple10 - core01 - ar01 - ar02 - incremental01 - incremental02 - error01 - diverge01 - density01 - convergence01 - nograd01 - clust01 - #gpl_man_tcl_check - #gpl_readme_msgs_check -} -# clust02 diff --git a/src/gpl/test/save_defok b/src/gpl/test/save_defok index 899db325246..7ee49ae334f 120000 --- a/src/gpl/test/save_defok +++ b/src/gpl/test/save_defok @@ -1 +1 @@ -../../../test/shared/save_defok \ No newline at end of file +../../../test/shared/save_defok.sh \ No newline at end of file diff --git a/src/gpl/test/save_ok b/src/gpl/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/gpl/test/save_ok +++ b/src/gpl/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index 66c7d7cc2a6..86e0841c29d 100755 --- a/test/regression +++ b/test/regression @@ -34,7 +34,6 @@ proc define_tool_script { tool script } { } # roughly flow order -define_tool_script "gpl" "src/gpl/test/regression" define_tool_script "dpo" "src/dpo/test/regression" define_tool_script "drt" "src/drt/test/regression" define_tool_script "fin" "src/fin/test/regression" From 95887ffa30395f22529ce43a81678c85b1ed0246 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:25:40 -0700 Subject: [PATCH 36/98] fin: move to ctest Signed-off-by: Peter Gadfort --- src/fin/test/regression | 2 +- src/fin/test/regression_tests.tcl | 5 ----- src/fin/test/save_ok | 2 +- test/regression | 1 - 4 files changed, 2 insertions(+), 8 deletions(-) delete mode 100644 src/fin/test/regression_tests.tcl diff --git a/src/fin/test/regression b/src/fin/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/fin/test/regression +++ b/src/fin/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/fin/test/regression_tests.tcl b/src/fin/test/regression_tests.tcl deleted file mode 100644 index 15c0d6fd25c..00000000000 --- a/src/fin/test/regression_tests.tcl +++ /dev/null @@ -1,5 +0,0 @@ -record_tests { - gcd_fill - #fin_man_tcl_check - #fin_readme_msgs_check -} diff --git a/src/fin/test/save_ok b/src/fin/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/fin/test/save_ok +++ b/src/fin/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index 86e0841c29d..be9cf26f2a7 100755 --- a/test/regression +++ b/test/regression @@ -36,7 +36,6 @@ proc define_tool_script { tool script } { # roughly flow order define_tool_script "dpo" "src/dpo/test/regression" define_tool_script "drt" "src/drt/test/regression" -define_tool_script "fin" "src/fin/test/regression" proc run_openroad_tests { } { global tool_errors From 1cc327ef5f7b6356d4fa622e401b92b8b22a44c0 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:26:06 -0700 Subject: [PATCH 37/98] drt: move to ctest Signed-off-by: Peter Gadfort --- src/drt/test/regression | 2 +- src/drt/test/regression_tests.tcl | 18 ------------------ src/drt/test/save_defok | 2 +- src/drt/test/save_ok | 2 +- 4 files changed, 3 insertions(+), 21 deletions(-) delete mode 100644 src/drt/test/regression_tests.tcl diff --git a/src/drt/test/regression b/src/drt/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/drt/test/regression +++ b/src/drt/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/drt/test/regression_tests.tcl b/src/drt/test/regression_tests.tcl deleted file mode 100644 index 9beaf8bfa9e..00000000000 --- a/src/drt/test/regression_tests.tcl +++ /dev/null @@ -1,18 +0,0 @@ -record_tests { - ispd18_sample - ispd18_sample_incr - ndr_vias1 - ndr_vias2 - obstruction - single_step - ta_ap_aligned - ta_pin_aligned - top_level_term - top_level_term2 - drc_test - #drt_man_tcl_check - #drt_readme_msgs_check -} -record_pass_fail_tests { - gc_test -} diff --git a/src/drt/test/save_defok b/src/drt/test/save_defok index 899db325246..7ee49ae334f 120000 --- a/src/drt/test/save_defok +++ b/src/drt/test/save_defok @@ -1 +1 @@ -../../../test/shared/save_defok \ No newline at end of file +../../../test/shared/save_defok.sh \ No newline at end of file diff --git a/src/drt/test/save_ok b/src/drt/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/drt/test/save_ok +++ b/src/drt/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file From d92d8c4a10e9b17897b51cbd2447f999fdf2606f Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:26:35 -0700 Subject: [PATCH 38/98] dpo: move to ctest Signed-off-by: Peter Gadfort --- src/dpo/test/regression | 2 +- src/dpo/test/regression_tests.tcl | 10 ---------- src/dpo/test/save_ok | 2 +- test/regression | 4 ---- 4 files changed, 2 insertions(+), 16 deletions(-) delete mode 100644 src/dpo/test/regression_tests.tcl diff --git a/src/dpo/test/regression b/src/dpo/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/dpo/test/regression +++ b/src/dpo/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/dpo/test/regression_tests.tcl b/src/dpo/test/regression_tests.tcl deleted file mode 100644 index 713b3ea49a3..00000000000 --- a/src/dpo/test/regression_tests.tcl +++ /dev/null @@ -1,10 +0,0 @@ -record_tests { - aes - blockage1 - gcd - ibex - multi_height1 - gcd_no_one_site_gaps - regions1 - regions2 -} diff --git a/src/dpo/test/save_ok b/src/dpo/test/save_ok index 4f5b707628d..c3cdfd3c124 120000 --- a/src/dpo/test/save_ok +++ b/src/dpo/test/save_ok @@ -1 +1 @@ -../../../test/save_ok \ No newline at end of file +../../../test/shared/save_ok.sh \ No newline at end of file diff --git a/test/regression b/test/regression index be9cf26f2a7..65c7bc30ded 100755 --- a/test/regression +++ b/test/regression @@ -33,10 +33,6 @@ proc define_tool_script { tool script } { dict set tool_scripts [string tolower $tool] $script } -# roughly flow order -define_tool_script "dpo" "src/dpo/test/regression" -define_tool_script "drt" "src/drt/test/regression" - proc run_openroad_tests { } { global tool_errors From e159b5ce3df2890618777ebe677016d45aef1666 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:28:42 -0700 Subject: [PATCH 39/98] dst: add to CI Signed-off-by: Peter Gadfort --- src/dst/CMakeLists.txt | 4 +--- src/dst/test/CMakeLists.txt | 9 +++++++++ src/dst/test/regression | 2 +- src/dst/test/regression_tests.tcl | 8 -------- 4 files changed, 11 insertions(+), 12 deletions(-) create mode 100644 src/dst/test/CMakeLists.txt delete mode 100644 src/dst/test/regression_tests.tcl diff --git a/src/dst/CMakeLists.txt b/src/dst/CMakeLists.txt index 45052cc80e7..4324309c977 100644 --- a/src/dst/CMakeLists.txt +++ b/src/dst/CMakeLists.txt @@ -76,6 +76,4 @@ messages( TARGET dst ) -if(ENABLE_TESTS) - add_subdirectory(test/cpp) -endif() +add_subdirectory(test) diff --git a/src/dst/test/CMakeLists.txt b/src/dst/test/CMakeLists.txt new file mode 100644 index 00000000000..ba5e7601b30 --- /dev/null +++ b/src/dst/test/CMakeLists.txt @@ -0,0 +1,9 @@ +or_integration_tests( + "dst" + PASSFAIL_TESTS + cpp_tests +) + +if(ENABLE_TESTS) + add_subdirectory(cpp) +endif() diff --git a/src/dst/test/regression b/src/dst/test/regression index 9dd00c591a9..683895a42de 120000 --- a/src/dst/test/regression +++ b/src/dst/test/regression @@ -1 +1 @@ -../../../test/shared/regression \ No newline at end of file +../../../test/shared/regression.sh \ No newline at end of file diff --git a/src/dst/test/regression_tests.tcl b/src/dst/test/regression_tests.tcl deleted file mode 100644 index 74750e19aec..00000000000 --- a/src/dst/test/regression_tests.tcl +++ /dev/null @@ -1,8 +0,0 @@ -record_tests { - -} - -record_pass_fail_tests { - cpp_tests -} - From bc4518957493c7b1cfd8b7ca255282951fee0cc8 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 10:32:54 -0700 Subject: [PATCH 40/98] ord: move to ctest for all but flow tests Signed-off-by: Peter Gadfort --- test/regression | 43 +-------------------------------------- test/regression_tests.tcl | 29 -------------------------- 2 files changed, 1 insertion(+), 71 deletions(-) diff --git a/test/regression b/test/regression index 65c7bc30ded..0ffc1e6c1c7 100755 --- a/test/regression +++ b/test/regression @@ -33,30 +33,6 @@ proc define_tool_script { tool script } { dict set tool_scripts [string tolower $tool] $script } -proc run_openroad_tests { } { - global tool_errors - - puts "------------------------------------------------------" - puts "OpenROAD" - # Skip flow tests until triton route is installed on CI machines - incr tool_errors [regression_body "non_flow"] -} - -proc run_tool_tests { tool } { - global tool_errors openroad_dir tool_scripts - - puts "------------------------------------------------------" - puts $tool - set script [dict get $tool_scripts $tool] - set test [file join $openroad_dir $script] - if { ![file exists $test] } { - puts "Error: $script not found." - incr tool_errors - } elseif { [catch "exec $test >@stdout"] } { - incr tool_errors - } -} - proc run_flow_tests { } { global tool_errors @@ -74,20 +50,11 @@ set tool_errors 0 if { $argv == {} } { # Run all tool Unit tests - dict for {tool script} $tool_scripts { - run_tool_tests $tool - } - run_openroad_tests + puts "Nothing specified" } else { foreach arg $argv { set arg [string tolower $arg] set matched 0 - # openroad - if { [string equal -nocase $arg "openroad"] } { - run_openroad_tests - set matched 1 - } - # flow if { [string equal -nocase $arg "flow"] } { run_flow_tests @@ -106,14 +73,6 @@ if { $argv == {} } { incr tool_errors [regression_body $ord_tests] } - # - dict for {tool script} $tool_scripts { - if { [string match -nocase $arg $tool] } { - run_tool_tests $tool - set matched 1 - } - } - if { !$matched } { puts "$arg is not an openroad test or tool name." incr tool_errors diff --git a/test/regression_tests.tcl b/test/regression_tests.tcl index d7fd1feb41d..f0bfc8592ef 100644 --- a/test/regression_tests.tcl +++ b/test/regression_tests.tcl @@ -1,32 +1,3 @@ -record_tests { - error1 - get_core_die_areas - timing_api - timing_api_2 - timing_api_3 - timing_api_4 - upf_test - upf_aes - two_designs -} - -record_pass_fail_tests { - commands_without_load -} - -define_test_group "non_flow" { - error1 - get_core_die_areas - timing_api - timing_api_2 - timing_api_3 - timing_api_4 - upf_test - upf_aes - two_designs - commands_without_load -} - # Flow tests only check the last line in the log (pass/fail). # Ordered by instance count. record_flow_tests { From 6e4338d237858253c632e37628c7edc5e0881c37 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 14:08:48 -0700 Subject: [PATCH 41/98] dst: disable tests as they are failing Signed-off-by: Peter Gadfort --- src/dst/test/CMakeLists.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/dst/test/CMakeLists.txt b/src/dst/test/CMakeLists.txt index ba5e7601b30..3d05f0753cd 100644 --- a/src/dst/test/CMakeLists.txt +++ b/src/dst/test/CMakeLists.txt @@ -1,7 +1,7 @@ or_integration_tests( "dst" - PASSFAIL_TESTS - cpp_tests + # PASSFAIL_TESTS + # cpp_tests ) if(ENABLE_TESTS) From 7a5b892e4f5c78b5274caee634d752746a0c871b Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 14:10:15 -0700 Subject: [PATCH 42/98] rmp: fix python formatting Signed-off-by: Peter Gadfort --- src/rmp/test/gcd_restructure.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/rmp/test/gcd_restructure.py b/src/rmp/test/gcd_restructure.py index 3da21e9ac44..857588e3fcf 100644 --- a/src/rmp/test/gcd_restructure.py +++ b/src/rmp/test/gcd_restructure.py @@ -30,7 +30,7 @@ workdir_name="results/python/gcd", abc_logfile="results/abc_rcon.log", tielo_port=tielo, - tiehi_port=tiehi + tiehi_port=tiehi, ) design.evalTclString("report_design_area") From f25a17ab0caadcba9dc29b73abf0d7f2c499c8ab Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 5 Dec 2024 19:38:30 -0700 Subject: [PATCH 43/98] test: remove unit tests tcl and ensure results are uploaded from ctest Signed-off-by: Peter Gadfort --- Jenkinsfile | 29 ++--------------------------- 1 file changed, 2 insertions(+), 27 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 8f47f404aab..14252f5e6e7 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -20,33 +20,8 @@ def baseTests(String image) { currentBuild.result = 'FAILURE'; } sh label: 'Save ctest results', script: 'tar zcvf results-ctest.tgz build/Testing'; - archiveArtifacts artifacts: 'results-ctest.tgz'; - } - } - } - - base_tests['Unit Tests Tcl'] = { - node { - withDockerContainer(args: '-u root', image: image) { - stage('Setup Tcl Tests') { - sh label: 'Configure git', script: "git config --system --add safe.directory '*'"; - checkout scm; - unstash 'install'; - } - stage('Unit Tests TCL') { - try { - catchError(buildResult: 'FAILURE', stageResult: 'FAILURE') { - timeout(time: 30, unit: 'MINUTES') { - sh label: 'Tcl regression', script: './test/regression'; - } - } - } catch (e) { - echo 'Failed regressions'; - currentBuild.result = 'FAILURE'; - } - sh label: 'Save Tcl results', script: "find . -name results -type d -exec tar zcvf {}.tgz {} ';'"; - archiveArtifacts artifacts: '**/results.tgz'; - } + sh label: 'Save results', script: "find . -name results -type d -exec tar zcvf {}.tgz {} ';'"; + archiveArtifacts artifacts: 'results-ctest.tgz, **/results.tgz'; } } } From d16512258eb29fcc5cbfc63187e7b31174f68c07 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 11 Dec 2024 14:47:33 +0100 Subject: [PATCH 44/98] gui: Add option to set title from Tcl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Martin Povišer --- src/gui/include/gui/gui.h | 5 +++++ src/gui/src/gui.cpp | 13 +++++++++++++ src/gui/src/gui.i | 7 +++++++ src/gui/src/mainWindow.cpp | 22 +++++++++++++++++++--- src/gui/src/mainWindow.h | 8 ++++++-- 5 files changed, 50 insertions(+), 5 deletions(-) diff --git a/src/gui/include/gui/gui.h b/src/gui/include/gui/gui.h index 0eeb6c6c58a..f158588d5bd 100644 --- a/src/gui/include/gui/gui.h +++ b/src/gui/include/gui/gui.h @@ -731,6 +731,9 @@ class Gui const std::string& option); void dumpHeatMap(const std::string& name, const std::string& file); + void setMainWindowTitle(std::string title); + std::string getMainWindowTitle(); + void selectHelp(const std::string& item); void selectChart(const std::string& name); void updateTimingReport(); @@ -812,6 +815,8 @@ class Gui std::unique_ptr placement_density_heat_map_; static Gui* singleton_; + + std::string main_window_title_ = "OpenROAD"; }; // The main entry point diff --git a/src/gui/src/gui.cpp b/src/gui/src/gui.cpp index d1b9de94c2f..5af79f7add9 100644 --- a/src/gui/src/gui.cpp +++ b/src/gui/src/gui.cpp @@ -1002,6 +1002,19 @@ void Gui::dumpHeatMap(const std::string& name, const std::string& file) source->dumpToFile(file); } +void Gui::setMainWindowTitle(std::string title) +{ + main_window_title_ = title; + if (main_window) { + main_window->setTitle(title); + } +} + +std::string Gui::getMainWindowTitle() +{ + return main_window_title_; +} + Renderer::~Renderer() { gui::Gui::get()->unregisterRenderer(this); diff --git a/src/gui/src/gui.i b/src/gui/src/gui.i index 93d74cafb18..3edd3a16084 100644 --- a/src/gui/src/gui.i +++ b/src/gui/src/gui.i @@ -767,4 +767,11 @@ void update_timing_report() auto gui = gui::Gui::get(); gui->updateTimingReport(); } + +void set_title(std::string title) +{ + auto gui = gui::Gui::get(); + gui->setMainWindowTitle(title); +} + %} // inline diff --git a/src/gui/src/mainWindow.cpp b/src/gui/src/mainWindow.cpp index 8c1475e4046..db1a301e9f7 100644 --- a/src/gui/src/mainWindow.cpp +++ b/src/gui/src/mainWindow.cpp @@ -112,7 +112,8 @@ MainWindow::MainWindow(bool load_settings, QWidget* parent) charts_widget_(new ChartsWidget(this)), help_widget_(new HelpWidget(this)), find_dialog_(new FindObjectDialog(this)), - goto_dialog_(new GotoLocationDialog(this, viewers_)) + goto_dialog_(new GotoLocationDialog(this, viewers_)), + window_title_(Gui::get()->getMainWindowTitle()) { // Size and position the window QSize size = QDesktopWidget().availableGeometry(this).size(); @@ -420,7 +421,7 @@ MainWindow::MainWindow(bool load_settings, QWidget* parent) // load resources and set window icon and title loadQTResources(); setWindowIcon(QIcon(":/icon.png")); - setWindowTitle(window_title_); + updateTitle(); Descriptor::Property::convert_dbu = [this](int value, bool add_units) -> std::string { @@ -449,13 +450,28 @@ void MainWindow::setDatabase(odb::dbDatabase* db) db_ = db; } -void MainWindow::setBlock(odb::dbBlock* block) +void MainWindow::setTitle(std::string title) +{ + window_title_ = title; + updateTitle(); +} + +void MainWindow::updateTitle() { + odb::dbBlock* block = getBlock(); if (block != nullptr) { const std::string title = fmt::format("{} - {}", window_title_, block->getName()); setWindowTitle(QString::fromStdString(title)); + } else { + setWindowTitle(QString::fromStdString(window_title_)); + } +} +void MainWindow::setBlock(odb::dbBlock* block) +{ + updateTitle(); + if (block != nullptr) { save_->setEnabled(true); } for (auto* heat_map : Gui::get()->getHeatMaps()) { diff --git a/src/gui/src/mainWindow.h b/src/gui/src/mainWindow.h index b900ff64859..c68d5e41a0b 100644 --- a/src/gui/src/mainWindow.h +++ b/src/gui/src/mainWindow.h @@ -113,6 +113,8 @@ class MainWindow : public QMainWindow, public ord::OpenRoadObserver std::vector getRestoreTclCommands(); + void setTitle(std::string title); + signals: // Signaled when we get a postRead callback to tell the sub-widgets // to update @@ -300,6 +302,8 @@ class MainWindow : public QMainWindow, public ord::OpenRoadObserver std::string convertDBUToString(int value, bool add_units) const; int convertStringToDBU(const std::string& value, bool* ok) const; + void updateTitle(); + odb::dbDatabase* db_; utl::Logger* logger_; SelectionSet selected_; @@ -325,6 +329,8 @@ class MainWindow : public QMainWindow, public ord::OpenRoadObserver FindObjectDialog* find_dialog_; GotoLocationDialog* goto_dialog_; + std::string window_title_; + QMenu* file_menu_; QMenu* view_menu_; QMenu* tools_menu_; @@ -366,8 +372,6 @@ class MainWindow : public QMainWindow, public ord::OpenRoadObserver // heat map actions std::map heatmap_actions_; - - static constexpr const char* window_title_ = "OpenROAD"; }; } // namespace gui From f7d032ee6cfadeb884c920de5ba33fff225c7ba8 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Wed, 11 Dec 2024 13:59:45 -0700 Subject: [PATCH 45/98] rsz: use masters for report_dont_use to avoid listing cells by corner Signed-off-by: Peter Gadfort --- src/rsz/src/Resizer.cc | 8 +++++++- src/rsz/src/Resizer.i | 1 + src/rsz/test/CMakeLists.txt | 1 + src/rsz/test/regression_tests.tcl | 1 + src/rsz/test/report_dont_use.ok | 4 ++-- src/rsz/test/report_dont_use_corners.ok | 18 ++++++++++++++++++ src/rsz/test/report_dont_use_corners.tcl | 16 ++++++++++++++++ 7 files changed, 46 insertions(+), 3 deletions(-) create mode 100644 src/rsz/test/report_dont_use_corners.ok create mode 100644 src/rsz/test/report_dont_use_corners.tcl diff --git a/src/rsz/src/Resizer.cc b/src/rsz/src/Resizer.cc index f0cb307a8c9..0141d3b79e0 100644 --- a/src/rsz/src/Resizer.cc +++ b/src/rsz/src/Resizer.cc @@ -1810,8 +1810,14 @@ void Resizer::reportDontUse() const if (dont_use_.empty()) { logger_->report(" none"); } else { + std::set cells; + for (auto* cell : dont_use_) { - logger_->report(" {}", cell->name()); + cells.insert(db_network_->staToDb(cell)); + } + + for (auto* cell : cells) { + logger_->report(" {}", cell->getName()); } } } diff --git a/src/rsz/src/Resizer.i b/src/rsz/src/Resizer.i index 13ec292f9b9..85f06ce12c9 100644 --- a/src/rsz/src/Resizer.i +++ b/src/rsz/src/Resizer.i @@ -460,6 +460,7 @@ set_dont_touch_instance(Instance *inst, void report_dont_use() { + ensureLinked(); Resizer *resizer = getResizer(); resizer->reportDontUse(); } diff --git a/src/rsz/test/CMakeLists.txt b/src/rsz/test/CMakeLists.txt index a1c146ef0fd..f29d739a8a6 100644 --- a/src/rsz/test/CMakeLists.txt +++ b/src/rsz/test/CMakeLists.txt @@ -116,6 +116,7 @@ set(TEST_NAMES repair_wire11 report_dont_touch report_dont_use + report_dont_use_corners report_floating_nets1 report_floating_nets2 report_floating_nets3 diff --git a/src/rsz/test/regression_tests.tcl b/src/rsz/test/regression_tests.tcl index 53d195b02c1..1f67dc0fa35 100644 --- a/src/rsz/test/regression_tests.tcl +++ b/src/rsz/test/regression_tests.tcl @@ -99,6 +99,7 @@ record_tests { repair_slew17 report_dont_touch report_dont_use + report_dont_use_corners report_floating_nets1 report_floating_nets2 report_floating_nets3 diff --git a/src/rsz/test/report_dont_use.ok b/src/rsz/test/report_dont_use.ok index f6b907cee8d..7fcca46dc20 100644 --- a/src/rsz/test/report_dont_use.ok +++ b/src/rsz/test/report_dont_use.ok @@ -11,8 +11,8 @@ Don't Use Cells: CLKBUF_X2 CLKBUF_X3 INV_X1 + INV_X16 INV_X2 + INV_X32 INV_X4 INV_X8 - INV_X16 - INV_X32 diff --git a/src/rsz/test/report_dont_use_corners.ok b/src/rsz/test/report_dont_use_corners.ok new file mode 100644 index 00000000000..7fcca46dc20 --- /dev/null +++ b/src/rsz/test/report_dont_use_corners.ok @@ -0,0 +1,18 @@ +[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells +[INFO ODB-0128] Design: gcd +[INFO ODB-0130] Created 54 pins. +[INFO ODB-0131] Created 571 components and 2554 component-terminals. +[INFO ODB-0132] Created 5 special nets and 1142 connections. +[INFO ODB-0133] Created 528 nets and 1412 connections. +Don't Use Cells: + none +Don't Use Cells: + CLKBUF_X1 + CLKBUF_X2 + CLKBUF_X3 + INV_X1 + INV_X16 + INV_X2 + INV_X32 + INV_X4 + INV_X8 diff --git a/src/rsz/test/report_dont_use_corners.tcl b/src/rsz/test/report_dont_use_corners.tcl new file mode 100644 index 00000000000..2842fab6123 --- /dev/null +++ b/src/rsz/test/report_dont_use_corners.tcl @@ -0,0 +1,16 @@ +# check for report_dont_use with corners + +source "helpers.tcl" + +define_corners slow fast +read_liberty -corner slow Nangate45/Nangate45_slow.lib +read_liberty -corner fast Nangate45/Nangate45_fast.lib +read_lef Nangate45/Nangate45.lef +read_def "gcd_nangate45_placed.def" + +report_dont_use + +set_dont_use "CLKBUF*" +set_dont_use "INV*" + +report_dont_use From 34b6d549e8b7b37c3160b61f169ebba1e4bab405 Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Thu, 12 Dec 2024 17:06:37 -0300 Subject: [PATCH 46/98] rsz: fix pin delimiter when writing spef file from estimate_parasitics Signed-off-by: Eder Monteiro --- src/rsz/src/SpefWriter.cc | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/src/rsz/src/SpefWriter.cc b/src/rsz/src/SpefWriter.cc index 61708568d69..51e6b304198 100644 --- a/src/rsz/src/SpefWriter.cc +++ b/src/rsz/src/SpefWriter.cc @@ -81,6 +81,20 @@ std::string escapeDollarSign(const char* name) return escapeDollarSign(std::string(name)); } +// Quick fix for wrong pin delimiter. +// TODO: save the parasitics data to odb and use the existing write_spef +// mechanism to produce the spef files from estimate_parasitics. +std::string fixPinDelimiter(const std::string& name) +{ + const char delimiter = '/'; + std::string result = name; + size_t pos = result.find_last_of(delimiter); + if (pos != std::string::npos) { + result.replace(pos, 1, ":"); + } + return result; +} + void SpefWriter::writeHeader() { for (auto [_, it] : spef_streams_) { @@ -192,7 +206,9 @@ void SpefWriter::writeNet(Corner* corner, const Net* net, Parasitic* parasitic) network_->staToDb(pin, iterm, bterm, moditerm, modbterm); if (iterm != nullptr) { - stream << "*I " << escapeDollarSign(parasitics_->name(node)) << " "; + stream << "*I " + << fixPinDelimiter(escapeDollarSign(parasitics_->name(node))) + << " "; stream << getIoDirectionText(iterm->getIoType()); stream << " *D " << iterm->getInst()->getMaster()->getName(); stream << '\n'; @@ -248,9 +264,9 @@ void SpefWriter::writeNet(Corner* corner, const Net* net, Parasitic* parasitic) stream << count++ << " "; auto n1 = parasitics_->node1(res); - stream << escapeDollarSign(parasitics_->name(n1)) << " "; + stream << fixPinDelimiter(escapeDollarSign(parasitics_->name(n1))) << " "; auto n2 = parasitics_->node2(res); - stream << escapeDollarSign(parasitics_->name(n2)) << " "; + stream << fixPinDelimiter(escapeDollarSign(parasitics_->name(n2))) << " "; stream << parasitics_->value(res) / res_scale << '\n'; } From 7f17d9e39517cb4a2f6ce027d3dc0acd26cdbfaf Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Thu, 12 Dec 2024 17:06:50 -0300 Subject: [PATCH 47/98] rsz: update ok files Signed-off-by: Eder Monteiro --- src/rsz/test/make_parasitics6_ff.spefok | 64 ++++++++++++------------- src/rsz/test/make_parasitics6_ss.spefok | 64 ++++++++++++------------- 2 files changed, 64 insertions(+), 64 deletions(-) diff --git a/src/rsz/test/make_parasitics6_ff.spefok b/src/rsz/test/make_parasitics6_ff.spefok index ab0c1f8004c..e6caa072bba 100644 --- a/src/rsz/test/make_parasitics6_ff.spefok +++ b/src/rsz/test/make_parasitics6_ff.spefok @@ -20,9 +20,9 @@ out O *D_NET in1 19.314 *CONN -*I r1/D I *D DFF_X1 +*I r1:D I *D DFF_X1 *P in1 I -*I r2/D I *D DFF_X1 +*I r2:D I *D DFF_X1 *CAP 1 in1:0 4.8466 2 in1:1 2.4052 @@ -33,9 +33,9 @@ out O 2 in1:0 in1 1e-06 3 in1:0 in1 1e-06 4 in1:1 in1:3 0.4344 -5 in1:1 r1/D 1e-06 +5 in1:1 r1:D 1e-06 6 in1:2 in1:3 0.4344 -7 in1:2 r2/D 1e-06 +7 in1:2 r2:D 1e-06 8 in1:3 in1:0 0.875338 9 in1:0 in1 1e-06 *END @@ -43,80 +43,80 @@ out O *D_NET out 22.6329 *CONN *P out O -*I r3/Q O *D DFF_X1 +*I r3:Q O *D DFF_X1 *CAP 1 out:0 11.3165 2 out:1 11.3165 *RES 1 out:0 out:1 2.04385 2 out:0 out 1e-06 -3 out:1 r3/Q 1e-06 +3 out:1 r3:Q 1e-06 4 out:1 out:1 1e-06 -5 out:1 r3/Q 1e-06 -6 out:1 r3/Q 1e-06 +5 out:1 r3:Q 1e-06 +6 out:1 r3:Q 1e-06 *END *D_NET r1q 9.76174 *CONN -*I r1/Q O *D DFF_X1 -*I u2/A1 I *D AND2_X1 +*I r1:Q O *D DFF_X1 +*I u2:A1 I *D AND2_X1 *CAP 1 r1q:0 4.88087 2 r1q:1 4.88087 *RES 1 r1q:0 r1q:1 0.881528 -2 r1q:0 u2/A1 1e-06 -3 r1q:1 r1/Q 1e-06 +2 r1q:0 u2:A1 1e-06 +3 r1q:1 r1:Q 1e-06 4 r1q:1 r1q:1 1e-06 -5 r1q:1 r1/Q 1e-06 -6 r1q:1 r1/Q 1e-06 +5 r1q:1 r1:Q 1e-06 +6 r1q:1 r1:Q 1e-06 *END *D_NET r2q 9.47998 *CONN -*I r2/Q O *D DFF_X1 -*I u1/A I *D BUF_X1 +*I r2:Q O *D DFF_X1 +*I u1:A I *D BUF_X1 *CAP 1 r2q:0 4.73999 2 r2q:1 4.73999 *RES 1 r2q:0 r2q:0 1e-06 -2 r2q:0 r2/Q 1e-06 -3 r2q:0 r2/Q 1e-06 +2 r2q:0 r2:Q 1e-06 +3 r2q:0 r2:Q 1e-06 4 r2q:1 r2q:0 0.856083 -5 r2q:1 u1/A 1e-06 -6 r2q:0 r2/Q 1e-06 +5 r2q:1 u1:A 1e-06 +6 r2q:0 r2:Q 1e-06 *END *D_NET u1z 28.8647 *CONN -*I u1/Z O *D BUF_X1 -*I u2/A2 I *D AND2_X1 +*I u1:Z O *D BUF_X1 +*I u2:A2 I *D AND2_X1 *CAP 1 u1z:0 14.4323 2 u1z:1 14.4323 *RES 1 u1z:0 u1z:1 2.60661 -2 u1z:0 u2/A2 1e-06 -3 u1z:1 u1/Z 1e-06 +2 u1z:0 u2:A2 1e-06 +3 u1z:1 u1:Z 1e-06 4 u1z:1 u1z:1 1e-06 -5 u1z:1 u1/Z 1e-06 -6 u1z:1 u1/Z 1e-06 +5 u1z:1 u1:Z 1e-06 +6 u1z:1 u1:Z 1e-06 *END *D_NET u2z 14.4476 *CONN -*I r3/D I *D DFF_X1 -*I u2/ZN O *D AND2_X1 +*I r3:D I *D DFF_X1 +*I u2:ZN O *D AND2_X1 *CAP 1 u2z:0 7.22378 2 u2z:1 7.22378 *RES 1 u2z:0 u2z:0 1e-06 -2 u2z:0 u2/ZN 1e-06 -3 u2z:0 u2/ZN 1e-06 +2 u2z:0 u2:ZN 1e-06 +3 u2z:0 u2:ZN 1e-06 4 u2z:1 u2z:0 1.30468 -5 u2z:1 r3/D 1e-06 -6 u2z:0 u2/ZN 1e-06 +5 u2z:1 r3:D 1e-06 +6 u2z:0 u2:ZN 1e-06 *END diff --git a/src/rsz/test/make_parasitics6_ss.spefok b/src/rsz/test/make_parasitics6_ss.spefok index 2c42b40d1fc..5831faa8a5d 100644 --- a/src/rsz/test/make_parasitics6_ss.spefok +++ b/src/rsz/test/make_parasitics6_ss.spefok @@ -20,9 +20,9 @@ out O *D_NET in1 28.971 *CONN -*I r1/D I *D DFF_X1 +*I r1:D I *D DFF_X1 *P in1 I -*I r2/D I *D DFF_X1 +*I r2:D I *D DFF_X1 *CAP 1 in1:0 7.2699 2 in1:1 3.6078 @@ -33,9 +33,9 @@ out O 2 in1:0 in1 1e-06 3 in1:0 in1 1e-06 4 in1:1 in1:3 0.6516 -5 in1:1 r1/D 1e-06 +5 in1:1 r1:D 1e-06 6 in1:2 in1:3 0.6516 -7 in1:2 r2/D 1e-06 +7 in1:2 r2:D 1e-06 8 in1:3 in1:0 1.31301 9 in1:0 in1 1e-06 *END @@ -43,80 +43,80 @@ out O *D_NET out 33.9494 *CONN *P out O -*I r3/Q O *D DFF_X1 +*I r3:Q O *D DFF_X1 *CAP 1 out:0 16.9747 2 out:1 16.9747 *RES 1 out:0 out:1 3.06578 2 out:0 out 1e-06 -3 out:1 r3/Q 1e-06 +3 out:1 r3:Q 1e-06 4 out:1 out:1 1e-06 -5 out:1 r3/Q 1e-06 -6 out:1 r3/Q 1e-06 +5 out:1 r3:Q 1e-06 +6 out:1 r3:Q 1e-06 *END *D_NET r1q 14.6426 *CONN -*I r1/Q O *D DFF_X1 -*I u2/A1 I *D AND2_X1 +*I r1:Q O *D DFF_X1 +*I u2:A1 I *D AND2_X1 *CAP 1 r1q:0 7.32131 2 r1q:1 7.32131 *RES 1 r1q:0 r1q:1 1.32229 -2 r1q:0 u2/A1 1e-06 -3 r1q:1 r1/Q 1e-06 +2 r1q:0 u2:A1 1e-06 +3 r1q:1 r1:Q 1e-06 4 r1q:1 r1q:1 1e-06 -5 r1q:1 r1/Q 1e-06 -6 r1q:1 r1/Q 1e-06 +5 r1q:1 r1:Q 1e-06 +6 r1q:1 r1:Q 1e-06 *END *D_NET r2q 14.22 *CONN -*I r2/Q O *D DFF_X1 -*I u1/A I *D BUF_X1 +*I r2:Q O *D DFF_X1 +*I u1:A I *D BUF_X1 *CAP 1 r2q:0 7.10998 2 r2q:1 7.10998 *RES 1 r2q:0 r2q:0 1e-06 -2 r2q:0 r2/Q 1e-06 -3 r2q:0 r2/Q 1e-06 +2 r2q:0 r2:Q 1e-06 +3 r2q:0 r2:Q 1e-06 4 r2q:1 r2q:0 1.28412 -5 r2q:1 u1/A 1e-06 -6 r2q:0 r2/Q 1e-06 +5 r2q:1 u1:A 1e-06 +6 r2q:0 r2:Q 1e-06 *END *D_NET u1z 43.297 *CONN -*I u1/Z O *D BUF_X1 -*I u2/A2 I *D AND2_X1 +*I u1:Z O *D BUF_X1 +*I u2:A2 I *D AND2_X1 *CAP 1 u1z:0 21.6485 2 u1z:1 21.6485 *RES 1 u1z:0 u1z:1 3.90991 -2 u1z:0 u2/A2 1e-06 -3 u1z:1 u1/Z 1e-06 +2 u1z:0 u2:A2 1e-06 +3 u1z:1 u1:Z 1e-06 4 u1z:1 u1z:1 1e-06 -5 u1z:1 u1/Z 1e-06 -6 u1z:1 u1/Z 1e-06 +5 u1z:1 u1:Z 1e-06 +6 u1z:1 u1:Z 1e-06 *END *D_NET u2z 21.6713 *CONN -*I r3/D I *D DFF_X1 -*I u2/ZN O *D AND2_X1 +*I r3:D I *D DFF_X1 +*I u2:ZN O *D AND2_X1 *CAP 1 u2z:0 10.8357 2 u2z:1 10.8357 *RES 1 u2z:0 u2z:0 1e-06 -2 u2z:0 u2/ZN 1e-06 -3 u2z:0 u2/ZN 1e-06 +2 u2z:0 u2:ZN 1e-06 +3 u2z:0 u2:ZN 1e-06 4 u2z:1 u2z:0 1.95702 -5 u2z:1 r3/D 1e-06 -6 u2z:0 u2/ZN 1e-06 +5 u2z:1 r3:D 1e-06 +6 u2z:0 u2:ZN 1e-06 *END From 14879e7d7522cf6831f26cd02c379c974bcfb04a Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Thu, 12 Dec 2024 17:57:24 -0300 Subject: [PATCH 48/98] grt: update ok files Signed-off-by: Eder Monteiro --- src/grt/test/est_rc4_corner0.spefok | 5928 +++++++++++++-------------- src/grt/test/est_rc4_corner1.spefok | 5928 +++++++++++++-------------- 2 files changed, 5928 insertions(+), 5928 deletions(-) diff --git a/src/grt/test/est_rc4_corner0.spefok b/src/grt/test/est_rc4_corner0.spefok index 1326240c82a..db5b1c0e9a9 100644 --- a/src/grt/test/est_rc4_corner0.spefok +++ b/src/grt/test/est_rc4_corner0.spefok @@ -72,41 +72,41 @@ resp_val O *D_NET clk 330.569 *CONN *P clk I -*I _858_/CK I *D DFF_X1 -*I _859_/CK I *D DFF_X1 -*I _860_/CK I *D DFF_X1 -*I _861_/CK I *D DFF_X1 -*I _862_/CK I *D DFF_X1 -*I _863_/CK I *D DFF_X1 -*I _864_/CK I *D DFF_X1 -*I _865_/CK I *D DFF_X1 -*I _866_/CK I *D DFF_X1 -*I _867_/CK I *D DFF_X1 -*I _868_/CK I *D DFF_X1 -*I _869_/CK I *D DFF_X1 -*I _870_/CK I *D DFF_X1 -*I _871_/CK I *D DFF_X1 -*I _872_/CK I *D DFF_X1 -*I _873_/CK I *D DFF_X1 -*I _874_/CK I *D DFF_X1 -*I _875_/CK I *D DFF_X1 -*I _876_/CK I *D DFF_X1 -*I _877_/CK I *D DFF_X1 -*I _878_/CK I *D DFF_X1 -*I _879_/CK I *D DFF_X1 -*I _880_/CK I *D DFF_X1 -*I _881_/CK I *D DFF_X1 -*I _882_/CK I *D DFF_X1 -*I _883_/CK I *D DFF_X1 -*I _884_/CK I *D DFF_X1 -*I _885_/CK I *D DFF_X1 -*I _886_/CK I *D DFF_X1 -*I _887_/CK I *D DFF_X1 -*I _888_/CK I *D DFF_X1 -*I _889_/CK I *D DFF_X1 -*I _890_/CK I *D DFF_X1 -*I _891_/CK I *D DFF_X1 -*I _892_/CK I *D DFF_X1 +*I _858_:CK I *D DFF_X1 +*I _859_:CK I *D DFF_X1 +*I _860_:CK I *D DFF_X1 +*I _861_:CK I *D DFF_X1 +*I _862_:CK I *D DFF_X1 +*I _863_:CK I *D DFF_X1 +*I _864_:CK I *D DFF_X1 +*I _865_:CK I *D DFF_X1 +*I _866_:CK I *D DFF_X1 +*I _867_:CK I *D DFF_X1 +*I _868_:CK I *D DFF_X1 +*I _869_:CK I *D DFF_X1 +*I _870_:CK I *D DFF_X1 +*I _871_:CK I *D DFF_X1 +*I _872_:CK I *D DFF_X1 +*I _873_:CK I *D DFF_X1 +*I _874_:CK I *D DFF_X1 +*I _875_:CK I *D DFF_X1 +*I _876_:CK I *D DFF_X1 +*I _877_:CK I *D DFF_X1 +*I _878_:CK I *D DFF_X1 +*I _879_:CK I *D DFF_X1 +*I _880_:CK I *D DFF_X1 +*I _881_:CK I *D DFF_X1 +*I _882_:CK I *D DFF_X1 +*I _883_:CK I *D DFF_X1 +*I _884_:CK I *D DFF_X1 +*I _885_:CK I *D DFF_X1 +*I _886_:CK I *D DFF_X1 +*I _887_:CK I *D DFF_X1 +*I _888_:CK I *D DFF_X1 +*I _889_:CK I *D DFF_X1 +*I _890_:CK I *D DFF_X1 +*I _891_:CK I *D DFF_X1 +*I _892_:CK I *D DFF_X1 *CAP 1 clk:1 3.15 2 clk:2 1.605 @@ -316,48 +316,48 @@ resp_val O 101 clk:101 clk:102 0.003 102 clk:102 clk:103 0.003 103 clk:103 clk:104 0.0063 -104 _858_/CK clk:53 1.465 -105 _859_/CK clk:2 2.225 -106 _860_/CK clk:56 2.585 -107 _861_/CK clk:4 2.345 -108 _862_/CK clk:5 2.125 -109 _863_/CK clk:69 1.285 -110 _864_/CK clk:95 3.225 -111 _865_/CK clk:14 1.505 -112 _866_/CK clk:3 2.525 -113 _867_/CK clk:20 2.905 -114 _868_/CK clk:84 2.245 -115 _869_/CK clk:40 1.445 -116 _870_/CK clk:71 1.845 -117 _871_/CK clk:75 0.725 -118 _872_/CK clk:16 1.445 -119 _873_/CK clk:23 4.305 -120 _874_/CK clk:46 0.905 -121 _875_/CK clk:26 3.005 -122 _876_/CK clk:28 1.725 -123 _877_/CK clk:22 2.265 -124 _878_/CK clk:59 2.765 -125 _879_/CK clk:63 1.185 -126 _880_/CK clk:12 2.845 -127 _881_/CK clk:15 0.785 -128 _882_/CK clk:88 0.985 -129 _883_/CK clk:32 1.425 -130 _884_/CK clk:89 1.505 -131 _885_/CK clk:39 1.085 -132 _886_/CK clk:70 2.245 -133 _887_/CK clk:94 1.505 -134 _888_/CK clk:42 2.645 -135 _889_/CK clk:43 3.005 -136 _890_/CK clk:49 1.285 -137 _891_/CK clk:80 1.545 -138 _892_/CK clk:50 1.665 +104 _858_:CK clk:53 1.465 +105 _859_:CK clk:2 2.225 +106 _860_:CK clk:56 2.585 +107 _861_:CK clk:4 2.345 +108 _862_:CK clk:5 2.125 +109 _863_:CK clk:69 1.285 +110 _864_:CK clk:95 3.225 +111 _865_:CK clk:14 1.505 +112 _866_:CK clk:3 2.525 +113 _867_:CK clk:20 2.905 +114 _868_:CK clk:84 2.245 +115 _869_:CK clk:40 1.445 +116 _870_:CK clk:71 1.845 +117 _871_:CK clk:75 0.725 +118 _872_:CK clk:16 1.445 +119 _873_:CK clk:23 4.305 +120 _874_:CK clk:46 0.905 +121 _875_:CK clk:26 3.005 +122 _876_:CK clk:28 1.725 +123 _877_:CK clk:22 2.265 +124 _878_:CK clk:59 2.765 +125 _879_:CK clk:63 1.185 +126 _880_:CK clk:12 2.845 +127 _881_:CK clk:15 0.785 +128 _882_:CK clk:88 0.985 +129 _883_:CK clk:32 1.425 +130 _884_:CK clk:89 1.505 +131 _885_:CK clk:39 1.085 +132 _886_:CK clk:70 2.245 +133 _887_:CK clk:94 1.505 +134 _888_:CK clk:42 2.645 +135 _889_:CK clk:43 3.005 +136 _890_:CK clk:49 1.285 +137 _891_:CK clk:80 1.545 +138 _892_:CK clk:50 1.665 139 clk clk:104 0.0019275 *END *D_NET req_msg[31] 17.8664 *CONN *P req_msg[31] I -*I buffer1/A I *D BUF_X4 +*I buffer1:A I *D BUF_X4 *CAP 1 req_msg[31]:1 2.4825 2 req_msg[31]:2 2.1 @@ -381,14 +381,14 @@ resp_val O 8 req_msg[31]:8 req_msg[31]:9 0.003 9 req_msg[31]:9 req_msg[31]:10 0.003 10 req_msg[31]:10 req_msg[31]:11 0.0063 -11 buffer1/A req_msg[31]:1 1.535 +11 buffer1:A req_msg[31]:1 1.535 12 req_msg[31] req_msg[31]:11 0.0029025 *END *D_NET req_msg[30] 7.15073 *CONN *P req_msg[30] I -*I buffer2/A I *D BUF_X4 +*I buffer2:A I *D BUF_X4 *CAP 1 req_msg[30]:1 3.4475 2 req_msg[30]:2 3.15 @@ -404,14 +404,14 @@ resp_val O 4 req_msg[30]:4 req_msg[30]:5 0.003 5 req_msg[30]:5 req_msg[30]:6 0.003 6 req_msg[30]:6 req_msg[30]:7 0.0063 -7 buffer2/A req_msg[30]:1 1.195 +7 buffer2:A req_msg[30]:1 1.195 8 req_msg[30] req_msg[30]:7 0.0015075 *END *D_NET req_msg[29] 7.77142 *CONN *P req_msg[29] I -*I buffer3/A I *D BUF_X4 +*I buffer3:A I *D BUF_X4 *CAP 1 req_msg[29]:1 3.15 2 req_msg[29]:2 3.735 @@ -427,14 +427,14 @@ resp_val O 4 req_msg[29]:4 req_msg[29]:5 0.003 5 req_msg[29]:5 req_msg[29]:5 0.003 6 req_msg[29]:6 req_msg[29]:7 0.0063 -7 buffer3/A req_msg[29]:2 2.345 +7 buffer3:A req_msg[29]:2 2.345 8 req_msg[29] req_msg[29]:6 0.0029025 *END *D_NET req_msg[28] 8.26106 *CONN *P req_msg[28] I -*I buffer4/A I *D BUF_X4 +*I buffer4:A I *D BUF_X4 *CAP 1 req_msg[28]:1 2.1 2 req_msg[28]:2 2.1 @@ -450,14 +450,14 @@ resp_val O 4 req_msg[28]:1 req_msg[28]:5 0.005 5 req_msg[28]:5 req_msg[28]:5 0.003 6 req_msg[28]:6 req_msg[28]:7 0.0063 -7 buffer4/A req_msg[28]:4 3.845 +7 buffer4:A req_msg[28]:4 3.845 8 req_msg[28] req_msg[28]:6 0.00294 *END *D_NET req_msg[27] 7.19515 *CONN *P req_msg[27] I -*I buffer5/A I *D BUF_X4 +*I buffer5:A I *D BUF_X4 *CAP 1 req_msg[27]:1 3.4675 2 req_msg[27]:2 3.15 @@ -473,14 +473,14 @@ resp_val O 4 req_msg[27]:4 req_msg[27]:5 0.003 5 req_msg[27]:5 req_msg[27]:6 0.003 6 req_msg[27]:6 req_msg[27]:7 0.0063 -7 buffer5/A req_msg[27]:1 1.275 +7 buffer5:A req_msg[27]:1 1.275 8 req_msg[27] req_msg[27]:7 0.0016425 *END *D_NET req_msg[26] 7.69454 *CONN *P req_msg[26] I -*I buffer6/A I *D BUF_X4 +*I buffer6:A I *D BUF_X4 *CAP 1 req_msg[26]:1 3.15 2 req_msg[26]:2 3.7 @@ -496,14 +496,14 @@ resp_val O 4 req_msg[26]:4 req_msg[26]:5 0.003 5 req_msg[26]:5 req_msg[26]:5 0.003 6 req_msg[26]:6 req_msg[26]:7 0.0063 -7 buffer6/A req_msg[26]:2 2.205 +7 buffer6:A req_msg[26]:2 2.205 8 req_msg[26] req_msg[26]:6 0.0026925 *END *D_NET req_msg[25] 7.44891 *CONN *P req_msg[25] I -*I buffer7/A I *D BUF_X4 +*I buffer7:A I *D BUF_X4 *CAP 1 req_msg[25]:1 3.5875 2 req_msg[25]:2 3.15 @@ -519,14 +519,14 @@ resp_val O 4 req_msg[25]:4 req_msg[25]:5 0.003 5 req_msg[25]:5 req_msg[25]:6 0.003 6 req_msg[25]:6 req_msg[25]:7 0.0063 -7 buffer7/A req_msg[25]:1 1.755 +7 buffer7:A req_msg[25]:1 1.755 8 req_msg[25] req_msg[25]:7 0.0020625 *END *D_NET req_msg[24] 9.99967 *CONN *P req_msg[24] I -*I buffer8/A I *D BUF_X4 +*I buffer8:A I *D BUF_X4 *CAP 1 req_msg[24]:1 1.825 2 req_msg[24]:2 1.05 @@ -542,14 +542,14 @@ resp_val O 4 req_msg[24]:4 req_msg[24]:5 0.005 5 req_msg[24]:5 req_msg[24]:6 0.003 6 req_msg[24]:6 req_msg[24]:7 0.0063 -7 buffer8/A req_msg[24]:1 3.105 +7 buffer8:A req_msg[24]:1 3.105 8 req_msg[24] req_msg[24]:7 0.004875 *END *D_NET req_msg[23] 7.71579 *CONN *P req_msg[23] I -*I buffer9/A I *D BUF_X4 +*I buffer9:A I *D BUF_X4 *CAP 1 req_msg[23]:1 3.7175 2 req_msg[23]:2 3.15 @@ -565,14 +565,14 @@ resp_val O 4 req_msg[23]:4 req_msg[23]:5 0.003 5 req_msg[23]:5 req_msg[23]:6 0.003 6 req_msg[23]:6 req_msg[23]:7 0.0063 -7 buffer9/A req_msg[23]:1 2.275 +7 buffer9:A req_msg[23]:1 2.275 8 req_msg[23] req_msg[23]:7 0.0022725 *END *D_NET req_msg[22] 17.3287 *CONN *P req_msg[22] I -*I buffer10/A I *D BUF_X4 +*I buffer10:A I *D BUF_X4 *CAP 1 req_msg[22]:1 4.2 2 req_msg[22]:2 4.44 @@ -588,14 +588,14 @@ resp_val O 4 req_msg[22]:4 req_msg[22]:5 0.005 5 req_msg[22]:5 req_msg[22]:6 0.003 6 req_msg[22]:6 req_msg[22]:7 0.0063 -7 buffer10/A req_msg[22]:2 0.965 +7 buffer10:A req_msg[22]:2 0.965 8 req_msg[22] req_msg[22]:7 0.004665 *END *D_NET req_msg[21] 7.37373 *CONN *P req_msg[21] I -*I buffer11/A I *D BUF_X4 +*I buffer11:A I *D BUF_X4 *CAP 1 req_msg[21]:1 0.5125 2 req_msg[21]:2 3.15 @@ -609,14 +609,14 @@ resp_val O 3 req_msg[21]:3 req_msg[21]:4 0.005 4 req_msg[21]:4 req_msg[21]:5 0.003 5 req_msg[21]:5 req_msg[21]:6 0.0063 -6 buffer11/A req_msg[21]:1 2.055 +6 buffer11:A req_msg[21]:1 2.055 7 req_msg[21] req_msg[21]:6 0.004665 *END *D_NET req_msg[20] 9.54387 *CONN *P req_msg[20] I -*I buffer12/A I *D BUF_X4 +*I buffer12:A I *D BUF_X4 *CAP 1 req_msg[20]:1 1.05 2 req_msg[20]:2 1.05 @@ -640,14 +640,14 @@ resp_val O 8 req_msg[20]:8 req_msg[20]:9 0.003 9 req_msg[20]:9 req_msg[20]:9 0.003 10 req_msg[20]:10 req_msg[20]:11 0.0063 -11 buffer12/A req_msg[20]:6 1.685 +11 buffer12:A req_msg[20]:6 1.685 12 req_msg[20] req_msg[20]:10 0.0029775 *END *D_NET req_msg[19] 7.46203 *CONN *P req_msg[19] I -*I buffer13/A I *D BUF_X4 +*I buffer13:A I *D BUF_X4 *CAP 1 req_msg[19]:1 3.5975 2 req_msg[19]:2 3.15 @@ -663,14 +663,14 @@ resp_val O 4 req_msg[19]:4 req_msg[19]:5 0.003 5 req_msg[19]:5 req_msg[19]:6 0.003 6 req_msg[19]:6 req_msg[19]:7 0.0063 -7 buffer13/A req_msg[19]:1 1.795 +7 buffer13:A req_msg[19]:1 1.795 8 req_msg[19] req_msg[19]:7 0.0018525 *END *D_NET req_msg[18] 7.67136 *CONN *P req_msg[18] I -*I buffer14/A I *D BUF_X4 +*I buffer14:A I *D BUF_X4 *CAP 1 req_msg[18]:1 3.6975 2 req_msg[18]:2 3.15 @@ -686,14 +686,14 @@ resp_val O 4 req_msg[18]:4 req_msg[18]:5 0.003 5 req_msg[18]:5 req_msg[18]:6 0.003 6 req_msg[18]:6 req_msg[18]:7 0.0063 -7 buffer14/A req_msg[18]:1 2.195 +7 buffer14:A req_msg[18]:1 2.195 8 req_msg[18] req_msg[18]:7 0.0021375 *END *D_NET req_msg[17] 7.01906 *CONN *P req_msg[17] I -*I buffer15/A I *D BUF_X4 +*I buffer15:A I *D BUF_X4 *CAP 1 req_msg[17]:1 0.3375 2 req_msg[17]:2 3.15 @@ -707,14 +707,14 @@ resp_val O 3 req_msg[17]:3 req_msg[17]:4 0.005 4 req_msg[17]:4 req_msg[17]:5 0.003 5 req_msg[17]:5 req_msg[17]:6 0.0063 -6 buffer15/A req_msg[17]:1 1.355 +6 buffer15:A req_msg[17]:1 1.355 7 req_msg[17] req_msg[17]:6 0.003615 *END *D_NET req_msg[16] 7.90954 *CONN *P req_msg[16] I -*I buffer16/A I *D BUF_X4 +*I buffer16:A I *D BUF_X4 *CAP 1 req_msg[16]:1 3.8075 2 req_msg[16]:2 3.15 @@ -730,14 +730,14 @@ resp_val O 4 req_msg[16]:4 req_msg[16]:5 0.003 5 req_msg[16]:5 req_msg[16]:6 0.003 6 req_msg[16]:6 req_msg[16]:7 0.0063 -7 buffer16/A req_msg[16]:1 2.635 +7 buffer16:A req_msg[16]:1 2.635 8 req_msg[16] req_msg[16]:7 0.0026925 *END *D_NET req_msg[15] 18.4476 *CONN *P req_msg[15] I -*I buffer17/A I *D BUF_X4 +*I buffer17:A I *D BUF_X4 *CAP 1 req_msg[15]:1 3.15 2 req_msg[15]:2 3.15 @@ -759,14 +759,14 @@ resp_val O 7 req_msg[15]:7 req_msg[15]:8 0.003 8 req_msg[15]:8 req_msg[15]:9 0.003 9 req_msg[15]:9 req_msg[15]:10 0.0063 -10 buffer17/A req_msg[15]:5 2.775 +10 buffer17:A req_msg[15]:5 2.775 11 req_msg[15] req_msg[15]:10 0.0017175 *END *D_NET req_msg[14] 7.05703 *CONN *P req_msg[14] I -*I buffer18/A I *D BUF_X4 +*I buffer18:A I *D BUF_X4 *CAP 1 req_msg[14]:1 3.15 2 req_msg[14]:2 3.395 @@ -782,14 +782,14 @@ resp_val O 4 req_msg[14]:4 req_msg[14]:5 0.003 5 req_msg[14]:5 req_msg[14]:5 0.003 6 req_msg[14]:6 req_msg[14]:7 0.0063 -7 buffer18/A req_msg[14]:2 0.985 +7 buffer18:A req_msg[14]:2 0.985 8 req_msg[14] req_msg[14]:6 0.0018525 *END *D_NET req_msg[13] 7.51766 *CONN *P req_msg[13] I -*I buffer19/A I *D BUF_X4 +*I buffer19:A I *D BUF_X4 *CAP 1 req_msg[13]:1 3.15 2 req_msg[13]:2 3.615 @@ -805,14 +805,14 @@ resp_val O 4 req_msg[13]:4 req_msg[13]:5 0.003 5 req_msg[13]:5 req_msg[13]:5 0.003 6 req_msg[13]:6 req_msg[13]:7 0.0063 -7 buffer19/A req_msg[13]:2 1.865 +7 buffer19:A req_msg[13]:2 1.865 8 req_msg[13] req_msg[13]:6 0.0024825 *END *D_NET req_msg[12] 7.7228 *CONN *P req_msg[12] I -*I buffer20/A I *D BUF_X4 +*I buffer20:A I *D BUF_X4 *CAP 1 req_msg[12]:1 0.6875 2 req_msg[12]:2 3.15 @@ -826,14 +826,14 @@ resp_val O 3 req_msg[12]:3 req_msg[12]:4 0.005 4 req_msg[12]:4 req_msg[12]:5 0.003 5 req_msg[12]:5 req_msg[12]:6 0.0063 -6 buffer20/A req_msg[12]:1 2.755 +6 buffer20:A req_msg[12]:1 2.755 7 req_msg[12] req_msg[12]:6 0.004455 *END *D_NET req_msg[11] 7.61012 *CONN *P req_msg[11] I -*I buffer21/A I *D BUF_X4 +*I buffer21:A I *D BUF_X4 *CAP 1 req_msg[11]:1 3.15 2 req_msg[11]:2 3.66 @@ -849,14 +849,14 @@ resp_val O 4 req_msg[11]:4 req_msg[11]:5 0.003 5 req_msg[11]:5 req_msg[11]:5 0.003 6 req_msg[11]:6 req_msg[11]:7 0.0063 -7 buffer21/A req_msg[11]:2 2.045 +7 buffer21:A req_msg[11]:2 2.045 8 req_msg[11] req_msg[11]:6 0.0025575 *END *D_NET req_msg[10] 7.92512 *CONN *P req_msg[10] I -*I buffer22/A I *D BUF_X4 +*I buffer22:A I *D BUF_X4 *CAP 1 req_msg[10]:1 3.8175 2 req_msg[10]:2 3.15 @@ -872,14 +872,14 @@ resp_val O 4 req_msg[10]:4 req_msg[10]:5 0.003 5 req_msg[10]:5 req_msg[10]:6 0.003 6 req_msg[10]:6 req_msg[10]:7 0.0063 -7 buffer22/A req_msg[10]:1 2.675 +7 buffer22:A req_msg[10]:1 2.675 8 req_msg[10] req_msg[10]:7 0.0025575 *END *D_NET req_msg[9] 5.4564 *CONN *P req_msg[9] I -*I buffer23/A I *D BUF_X4 +*I buffer23:A I *D BUF_X4 *CAP 1 req_msg[9]:1 2.1 2 req_msg[9]:2 2.1 @@ -893,14 +893,14 @@ resp_val O 3 req_msg[9]:1 req_msg[9]:4 0.005 4 req_msg[9]:4 req_msg[9]:4 0.003 5 req_msg[9]:5 req_msg[9]:6 0.0063 -6 buffer23/A req_msg[9]:3 2.445 +6 buffer23:A req_msg[9]:3 2.445 7 req_msg[9] req_msg[9]:5 0.00189 *END *D_NET req_msg[8] 11.8095 *CONN *P req_msg[8] I -*I buffer24/A I *D BUF_X4 +*I buffer24:A I *D BUF_X4 *CAP 1 req_msg[8]:1 3.15 2 req_msg[8]:2 3.15 @@ -922,14 +922,14 @@ resp_val O 7 req_msg[8]:7 req_msg[8]:8 0.003 8 req_msg[8]:8 req_msg[8]:9 0.003 9 req_msg[8]:9 req_msg[8]:10 0.0063 -10 buffer24/A req_msg[8]:5 2.035 +10 buffer24:A req_msg[8]:5 2.035 11 req_msg[8] req_msg[8]:10 0.0026925 *END *D_NET req_msg[7] 7.19593 *CONN *P req_msg[7] I -*I buffer25/A I *D BUF_X4 +*I buffer25:A I *D BUF_X4 *CAP 1 req_msg[7]:1 0.425 2 req_msg[7]:2 3.15 @@ -943,14 +943,14 @@ resp_val O 3 req_msg[7]:3 req_msg[7]:4 0.005 4 req_msg[7]:4 req_msg[7]:5 0.003 5 req_msg[7]:5 req_msg[7]:6 0.0063 -6 buffer25/A req_msg[7]:1 1.705 +6 buffer25:A req_msg[7]:1 1.705 7 req_msg[7] req_msg[7]:6 0.004035 *END *D_NET req_msg[6] 5.63513 *CONN *P req_msg[6] I -*I buffer26/A I *D BUF_X4 +*I buffer26:A I *D BUF_X4 *CAP 1 req_msg[6]:1 2.1 2 req_msg[6]:2 2.1 @@ -964,14 +964,14 @@ resp_val O 3 req_msg[6]:1 req_msg[6]:4 0.005 4 req_msg[6]:4 req_msg[6]:4 0.003 5 req_msg[6]:5 req_msg[6]:6 0.0063 -6 buffer26/A req_msg[6]:3 2.795 +6 buffer26:A req_msg[6]:3 2.795 7 req_msg[6] req_msg[6]:5 0.00273 *END *D_NET req_msg[5] 14.417 *CONN *P req_msg[5] I -*I buffer27/A I *D BUF_X4 +*I buffer27:A I *D BUF_X4 *CAP 1 req_msg[5]:1 4.2 2 req_msg[5]:2 4.975 @@ -995,14 +995,14 @@ resp_val O 8 req_msg[5]:8 req_msg[5]:9 0.003 9 req_msg[5]:9 req_msg[5]:9 0.003 10 req_msg[5]:10 req_msg[5]:11 0.0063 -11 buffer27/A req_msg[5]:2 3.105 +11 buffer27:A req_msg[5]:2 3.105 12 req_msg[5] req_msg[5]:10 0.0018525 *END *D_NET req_msg[4] 9.99593 *CONN *P req_msg[4] I -*I buffer28/A I *D BUF_X4 +*I buffer28:A I *D BUF_X4 *CAP 1 req_msg[4]:1 1.825 2 req_msg[4]:2 1.05 @@ -1018,14 +1018,14 @@ resp_val O 4 req_msg[4]:4 req_msg[4]:5 0.005 5 req_msg[4]:5 req_msg[4]:6 0.003 6 req_msg[4]:6 req_msg[4]:7 0.0063 -7 buffer28/A req_msg[4]:1 3.105 +7 buffer28:A req_msg[4]:1 3.105 8 req_msg[4] req_msg[4]:7 0.004035 *END *D_NET req_msg[3] 7.5564 *CONN *P req_msg[3] I -*I buffer29/A I *D BUF_X4 +*I buffer29:A I *D BUF_X4 *CAP 1 req_msg[3]:1 1.05 2 req_msg[3]:2 1.05 @@ -1045,14 +1045,14 @@ resp_val O 6 req_msg[3]:6 req_msg[3]:7 0.005 7 req_msg[3]:7 req_msg[3]:7 0.003 8 req_msg[3]:8 req_msg[3]:9 0.0063 -9 buffer29/A req_msg[3]:5 2.445 +9 buffer29:A req_msg[3]:5 2.445 10 req_msg[3] req_msg[3]:8 0.00189 *END *D_NET req_msg[2] 18.5207 *CONN *P req_msg[2] I -*I buffer30/A I *D BUF_X4 +*I buffer30:A I *D BUF_X4 *CAP 1 req_msg[2]:1 2.8325 2 req_msg[2]:2 2.1 @@ -1076,14 +1076,14 @@ resp_val O 8 req_msg[2]:8 req_msg[2]:9 0.003 9 req_msg[2]:9 req_msg[2]:10 0.003 10 req_msg[2]:10 req_msg[2]:11 0.0063 -11 buffer30/A req_msg[2]:1 2.935 +11 buffer30:A req_msg[2]:1 2.935 12 req_msg[2] req_msg[2]:11 0.0015075 *END *D_NET req_msg[1] 7.27948 *CONN *P req_msg[1] I -*I buffer31/A I *D BUF_X4 +*I buffer31:A I *D BUF_X4 *CAP 1 req_msg[1]:1 3.15 2 req_msg[1]:2 3.505 @@ -1099,14 +1099,14 @@ resp_val O 4 req_msg[1]:4 req_msg[1]:5 0.003 5 req_msg[1]:5 req_msg[1]:5 0.003 6 req_msg[1]:6 req_msg[1]:7 0.0063 -7 buffer31/A req_msg[1]:2 1.425 +7 buffer31:A req_msg[1]:2 1.425 8 req_msg[1] req_msg[1]:6 0.0019275 *END *D_NET req_msg[0] 7.195 *CONN *P req_msg[0] I -*I buffer32/A I *D BUF_X4 +*I buffer32:A I *D BUF_X4 *CAP 1 req_msg[0]:1 0.425 2 req_msg[0]:2 3.15 @@ -1120,14 +1120,14 @@ resp_val O 3 req_msg[0]:3 req_msg[0]:4 0.005 4 req_msg[0]:4 req_msg[0]:5 0.003 5 req_msg[0]:5 req_msg[0]:6 0.0063 -6 buffer32/A req_msg[0]:1 1.705 +6 buffer32:A req_msg[0]:1 1.705 7 req_msg[0] req_msg[0]:6 0.003825 *END *D_NET req_rdy 17.9833 *CONN *P req_rdy O -*I buffer36/Z O *D BUF_X4 +*I buffer36:Z O *D BUF_X4 *CAP 1 req_rdy:1 3.15 2 req_rdy:2 3.15 @@ -1149,14 +1149,14 @@ resp_val O 7 req_rdy:7 req_rdy:8 0.003 8 req_rdy:8 req_rdy:8 0.003 9 req_rdy:9 req_rdy:10 0.0063 -10 buffer36/Z req_rdy:5 1.755 +10 buffer36:Z req_rdy:5 1.755 11 req_rdy req_rdy:9 0.0031125 *END *D_NET req_val 13.3019 *CONN *P req_val I -*I buffer33/A I *D BUF_X4 +*I buffer33:A I *D BUF_X4 *CAP 1 req_val:1 2.4275 2 req_val:2 2.1 @@ -1172,14 +1172,14 @@ resp_val O 4 req_val:4 req_val:5 0.005 5 req_val:5 req_val:6 0.003 6 req_val:6 req_val:7 0.0063 -7 buffer33/A req_val:1 1.315 +7 buffer33:A req_val:1 1.315 8 req_val req_val:7 0.004245 *END *D_NET reset 5.9842 *CONN *P reset I -*I buffer34/A I *D BUF_X4 +*I buffer34:A I *D BUF_X4 *CAP 1 reset:1 2.1 2 reset:2 2.1 @@ -1193,14 +1193,14 @@ resp_val O 3 reset:1 reset:4 0.005 4 reset:4 reset:4 0.003 5 reset:5 reset:6 0.0063 -6 buffer34/A reset:3 3.495 +6 buffer34:A reset:3 3.495 7 reset reset:5 0.00252 *END *D_NET resp_msg[15] 14.4351 *CONN *P resp_msg[15] O -*I buffer37/Z O *D BUF_X4 +*I buffer37:Z O *D BUF_X4 *CAP 1 resp_msg[15]:1 3.15 2 resp_msg[15]:2 3.15 @@ -1224,14 +1224,14 @@ resp_val O 8 resp_msg[15]:8 resp_msg[15]:9 0.003 9 resp_msg[15]:9 resp_msg[15]:9 0.003 10 resp_msg[15]:10 resp_msg[15]:11 0.0063 -11 buffer37/Z resp_msg[15]:6 3.155 +11 buffer37:Z resp_msg[15]:6 3.155 12 resp_msg[15] resp_msg[15]:10 0.0016425 *END *D_NET resp_msg[14] 9.82824 *CONN *P resp_msg[14] O -*I buffer38/Z O *D BUF_X4 +*I buffer38:Z O *D BUF_X4 *CAP 1 resp_msg[14]:1 1.05 2 resp_msg[14]:2 1.05 @@ -1255,14 +1255,14 @@ resp_val O 8 resp_msg[14]:8 resp_msg[14]:9 0.003 9 resp_msg[14]:9 resp_msg[14]:9 0.003 10 resp_msg[14]:10 resp_msg[14]:11 0.0063 -11 buffer38/Z resp_msg[14]:6 2.295 +11 buffer38:Z resp_msg[14]:6 2.295 12 resp_msg[14] resp_msg[14]:10 0.0023475 *END *D_NET resp_msg[13] 5.49093 *CONN *P resp_msg[13] O -*I buffer39/Z O *D BUF_X4 +*I buffer39:Z O *D BUF_X4 *CAP 1 resp_msg[13]:1 0.6225 2 resp_msg[13]:2 2.1 @@ -1276,14 +1276,14 @@ resp_val O 3 resp_msg[13]:3 resp_msg[13]:4 0.005 4 resp_msg[13]:4 resp_msg[13]:5 0.003 5 resp_msg[13]:5 resp_msg[13]:6 0.0063 -6 buffer39/Z resp_msg[13]:1 2.495 +6 buffer39:Z resp_msg[13]:1 2.495 7 resp_msg[13] resp_msg[13]:6 0.004035 *END *D_NET resp_msg[12] 16.942 *CONN *P resp_msg[12] O -*I buffer40/Z O *D BUF_X4 +*I buffer40:Z O *D BUF_X4 *CAP 1 resp_msg[12]:1 3.15 2 resp_msg[12]:2 4.1225 @@ -1307,14 +1307,14 @@ resp_val O 8 resp_msg[12]:8 resp_msg[12]:9 0.003 9 resp_msg[12]:9 resp_msg[12]:9 0.003 10 resp_msg[12]:10 resp_msg[12]:11 0.0063 -11 buffer40/Z resp_msg[12]:2 3.895 +11 buffer40:Z resp_msg[12]:2 3.895 12 resp_msg[12] resp_msg[12]:10 0.0027675 *END *D_NET resp_msg[11] 6.1956 *CONN *P resp_msg[11] O -*I buffer41/Z O *D BUF_X4 +*I buffer41:Z O *D BUF_X4 *CAP 1 resp_msg[11]:1 0.9725 2 resp_msg[11]:2 2.1 @@ -1328,14 +1328,14 @@ resp_val O 3 resp_msg[11]:3 resp_msg[11]:4 0.005 4 resp_msg[11]:4 resp_msg[11]:5 0.003 5 resp_msg[11]:5 resp_msg[11]:6 0.0063 -6 buffer41/Z resp_msg[11]:1 3.895 +6 buffer41:Z resp_msg[11]:1 3.895 7 resp_msg[11] resp_msg[11]:6 0.005085 *END *D_NET resp_msg[10] 7.21606 *CONN *P resp_msg[10] O -*I buffer42/Z O *D BUF_X4 +*I buffer42:Z O *D BUF_X4 *CAP 1 resp_msg[10]:1 3.15 2 resp_msg[10]:2 3.15 @@ -1349,14 +1349,14 @@ resp_val O 3 resp_msg[10]:1 resp_msg[10]:4 0.005 4 resp_msg[10]:4 resp_msg[10]:4 0.003 5 resp_msg[10]:5 resp_msg[10]:6 0.0063 -6 buffer42/Z resp_msg[10]:3 1.755 +6 buffer42:Z resp_msg[10]:3 1.755 7 resp_msg[10] resp_msg[10]:5 0.00294 *END *D_NET resp_msg[9] 6.82578 *CONN *P resp_msg[9] O -*I buffer43/Z O *D BUF_X4 +*I buffer43:Z O *D BUF_X4 *CAP 1 resp_msg[9]:1 3.15 2 resp_msg[9]:2 3.2725 @@ -1372,14 +1372,14 @@ resp_val O 4 resp_msg[9]:4 resp_msg[9]:5 0.003 5 resp_msg[9]:5 resp_msg[9]:5 0.003 6 resp_msg[9]:6 resp_msg[9]:7 0.0063 -7 buffer43/Z resp_msg[9]:2 0.495 +7 buffer43:Z resp_msg[9]:2 0.495 8 resp_msg[9] resp_msg[9]:6 0.0022725 *END *D_NET resp_msg[8] 7.91327 *CONN *P resp_msg[8] O -*I buffer44/Z O *D BUF_X4 +*I buffer44:Z O *D BUF_X4 *CAP 1 resp_msg[8]:1 3.15 2 resp_msg[8]:2 3.15 @@ -1393,14 +1393,14 @@ resp_val O 3 resp_msg[8]:1 resp_msg[8]:4 0.005 4 resp_msg[8]:4 resp_msg[8]:4 0.003 5 resp_msg[8]:5 resp_msg[8]:6 0.0063 -6 buffer44/Z resp_msg[8]:3 3.155 +6 buffer44:Z resp_msg[8]:3 3.155 7 resp_msg[8] resp_msg[8]:5 0.00231 *END *D_NET resp_msg[7] 16.997 *CONN *P resp_msg[7] O -*I buffer45/Z O *D BUF_X4 +*I buffer45:Z O *D BUF_X4 *CAP 1 resp_msg[7]:1 3.0725 2 resp_msg[7]:2 2.1 @@ -1424,14 +1424,14 @@ resp_val O 8 resp_msg[7]:8 resp_msg[7]:9 0.003 9 resp_msg[7]:9 resp_msg[7]:10 0.003 10 resp_msg[7]:10 resp_msg[7]:11 0.0063 -11 buffer45/Z resp_msg[7]:1 3.895 +11 buffer45:Z resp_msg[7]:1 3.895 12 resp_msg[7] resp_msg[7]:11 0.0044475 *END *D_NET resp_msg[6] 10.7114 *CONN *P resp_msg[6] O -*I buffer46/Z O *D BUF_X4 +*I buffer46:Z O *D BUF_X4 *CAP 1 resp_msg[6]:1 3.15 2 resp_msg[6]:2 3.15 @@ -1447,14 +1447,14 @@ resp_val O 4 resp_msg[6]:1 resp_msg[6]:5 0.005 5 resp_msg[6]:5 resp_msg[6]:5 0.003 6 resp_msg[6]:6 resp_msg[6]:7 0.0063 -7 buffer46/Z resp_msg[6]:4 4.555 +7 buffer46:Z resp_msg[6]:4 4.555 8 resp_msg[6] resp_msg[6]:6 0.00189 *END *D_NET resp_msg[5] 8.9928 *CONN *P resp_msg[5] O -*I buffer47/Z O *D BUF_X4 +*I buffer47:Z O *D BUF_X4 *CAP 1 resp_msg[5]:1 2.3725 2 resp_msg[5]:2 1.05 @@ -1470,14 +1470,14 @@ resp_val O 4 resp_msg[5]:4 resp_msg[5]:5 0.005 5 resp_msg[5]:5 resp_msg[5]:6 0.003 6 resp_msg[5]:6 resp_msg[5]:7 0.0063 -7 buffer47/Z resp_msg[5]:1 5.295 +7 buffer47:Z resp_msg[5]:1 5.295 8 resp_msg[5] resp_msg[5]:7 0.004455 *END *D_NET resp_msg[4] 13.1405 *CONN *P resp_msg[4] O -*I buffer48/Z O *D BUF_X4 +*I buffer48:Z O *D BUF_X4 *CAP 1 resp_msg[4]:1 4.2 2 resp_msg[4]:2 4.2 @@ -1493,14 +1493,14 @@ resp_val O 4 resp_msg[4]:1 resp_msg[4]:5 0.005 5 resp_msg[4]:5 resp_msg[4]:5 0.003 6 resp_msg[4]:6 resp_msg[4]:7 0.0063 -7 buffer48/Z resp_msg[4]:4 1.015 +7 buffer48:Z resp_msg[4]:4 1.015 8 resp_msg[4] resp_msg[4]:6 0.00168 *END *D_NET resp_msg[3] 9.53888 *CONN *P resp_msg[3] O -*I buffer49/Z O *D BUF_X4 +*I buffer49:Z O *D BUF_X4 *CAP 1 resp_msg[3]:1 1.05 2 resp_msg[3]:2 1.05 @@ -1524,14 +1524,14 @@ resp_val O 8 resp_msg[3]:8 resp_msg[3]:9 0.003 9 resp_msg[3]:9 resp_msg[3]:9 0.003 10 resp_msg[3]:10 resp_msg[3]:11 0.0063 -11 buffer49/Z resp_msg[3]:6 1.675 +11 buffer49:Z resp_msg[3]:6 1.675 12 resp_msg[3] resp_msg[3]:10 0.0029775 *END *D_NET resp_msg[2] 10.0133 *CONN *P resp_msg[2] O -*I buffer50/Z O *D BUF_X4 +*I buffer50:Z O *D BUF_X4 *CAP 1 resp_msg[2]:1 3.15 2 resp_msg[2]:2 3.15 @@ -1547,14 +1547,14 @@ resp_val O 4 resp_msg[2]:1 resp_msg[2]:5 0.005 5 resp_msg[2]:5 resp_msg[2]:5 0.003 6 resp_msg[2]:6 resp_msg[2]:7 0.0063 -7 buffer50/Z resp_msg[2]:4 3.155 +7 buffer50:Z resp_msg[2]:4 3.155 8 resp_msg[2] resp_msg[2]:6 0.00231 *END *D_NET resp_msg[1] 7.2142 *CONN *P resp_msg[1] O -*I buffer51/Z O *D BUF_X4 +*I buffer51:Z O *D BUF_X4 *CAP 1 resp_msg[1]:1 3.15 2 resp_msg[1]:2 3.15 @@ -1568,14 +1568,14 @@ resp_val O 3 resp_msg[1]:1 resp_msg[1]:4 0.005 4 resp_msg[1]:4 resp_msg[1]:4 0.003 5 resp_msg[1]:5 resp_msg[1]:6 0.0063 -6 buffer51/Z resp_msg[1]:3 1.755 +6 buffer51:Z resp_msg[1]:3 1.755 7 resp_msg[1] resp_msg[1]:5 0.00252 *END *D_NET resp_msg[0] 10.7161 *CONN *P resp_msg[0] O -*I buffer52/Z O *D BUF_X4 +*I buffer52:Z O *D BUF_X4 *CAP 1 resp_msg[0]:1 3.15 2 resp_msg[0]:2 3.15 @@ -1591,14 +1591,14 @@ resp_val O 4 resp_msg[0]:1 resp_msg[0]:5 0.005 5 resp_msg[0]:5 resp_msg[0]:5 0.003 6 resp_msg[0]:6 resp_msg[0]:7 0.0063 -7 buffer52/Z resp_msg[0]:4 4.555 +7 buffer52:Z resp_msg[0]:4 4.555 8 resp_msg[0] resp_msg[0]:6 0.00294 *END *D_NET resp_rdy 11.9351 *CONN *P resp_rdy I -*I buffer35/A I *D BUF_X4 +*I buffer35:A I *D BUF_X4 *CAP 1 resp_rdy:1 3.15 2 resp_rdy:2 3.15 @@ -1618,14 +1618,14 @@ resp_val O 6 resp_rdy:6 resp_rdy:7 0.005 7 resp_rdy:7 resp_rdy:7 0.003 8 resp_rdy:8 resp_rdy:9 0.0063 -9 buffer35/A resp_rdy:5 2.795 +9 buffer35:A resp_rdy:5 2.795 10 resp_rdy resp_rdy:8 0.00273 *END *D_NET resp_val 8.98907 *CONN *P resp_val O -*I buffer53/Z O *D BUF_X4 +*I buffer53:Z O *D BUF_X4 *CAP 1 resp_val:1 2.3725 2 resp_val:2 1.05 @@ -1641,14 +1641,14 @@ resp_val O 4 resp_val:4 resp_val:5 0.005 5 resp_val:5 resp_val:6 0.003 6 resp_val:6 resp_val:7 0.0063 -7 buffer53/Z resp_val:1 5.295 +7 buffer53:Z resp_val:1 5.295 8 resp_val resp_val:7 0.003615 *END *D_NET _000_ 6.02 *CONN -*I _762_/Z O *D CLKBUF_X1 -*I _858_/D I *D DFF_X1 +*I _762_:Z O *D CLKBUF_X1 +*I _858_:D I *D DFF_X1 *CAP 1 _000_:1 1.41 2 _000_:2 1.05 @@ -1660,14 +1660,14 @@ resp_val O 2 _000_:2 _000_:3 0.005 3 _000_:3 _000_:4 4.2 4 _000_:4 _000_:5 0.005 -5 _762_/Z _000_:5 2.205 -6 _858_/D _000_:1 1.445 +5 _762_:Z _000_:5 2.205 +6 _858_:D _000_:1 1.445 *END *D_NET _001_ 3.9 *CONN -*I _758_/Z O *D CLKBUF_X1 -*I _859_/D I *D DFF_X1 +*I _758_:Z O *D CLKBUF_X1 +*I _859_:D I *D DFF_X1 *CAP 1 _001_:1 0.18 2 _001_:2 1.05 @@ -1677,51 +1677,51 @@ resp_val O 1 _001_:1 _001_:2 0.005 2 _001_:2 _001_:3 4.2 3 _001_:3 _001_:4 0.005 -4 _758_/Z _001_:4 2.885 -5 _859_/D _001_:1 0.725 +4 _758_:Z _001_:4 2.885 +5 _859_:D _001_:1 0.725 *END *D_NET _002_ 6.01 *CONN -*I _761_/Z O *D CLKBUF_X1 -*I _860_/D I *D DFF_X1 +*I _761_:Z O *D CLKBUF_X1 +*I _860_:D I *D DFF_X1 *CAP 1 _002_:1 1.985 2 _002_:2 2.07 *RES 1 _002_:2 _002_:1 4.2 -2 _761_/Z _002_:1 3.745 -3 _860_/D _002_:2 4.085 +2 _761_:Z _002_:1 3.745 +3 _860_:D _002_:2 4.085 *END *D_NET _003_ 1.88 *CONN -*I _757_/A I *D CLKBUF_X1 -*I _859_/QN O *D DFF_X1 +*I _757_:A I *D CLKBUF_X1 +*I _859_:QN O *D DFF_X1 *CAP 1 _003_:1 0.94 *RES 1 _003_:1 _003_:1 0.005 -2 _757_/A _003_:1 2.535 -3 _859_/QN _003_:1 1.235 +2 _757_:A _003_:1 2.535 +3 _859_:QN _003_:1 1.235 *END *D_NET _004_ 2.77 *CONN -*I _756_/A I *D CLKBUF_X1 -*I _860_/QN O *D DFF_X1 +*I _756_:A I *D CLKBUF_X1 +*I _860_:QN O *D DFF_X1 *CAP 1 _004_:1 1.385 *RES 1 _004_:1 _004_:1 0.005 -2 _756_/A _004_:1 1.435 -3 _860_/QN _004_:1 4.115 +2 _756_:A _004_:1 1.435 +3 _860_:QN _004_:1 4.115 *END *D_NET _005_ 4.035 *CONN -*I _720_/A I *D BUF_X1 -*I _858_/QN O *D DFF_X1 +*I _720_:A I *D BUF_X1 +*I _858_:QN O *D DFF_X1 *CAP 1 _005_:1 0.4125 2 _005_:2 1.05 @@ -1731,26 +1731,26 @@ resp_val O 1 _005_:1 _005_:2 0.005 2 _005_:2 _005_:3 4.2 3 _005_:3 _005_:4 0.005 -4 _720_/A _005_:4 2.225 -5 _858_/QN _005_:1 1.655 +4 _720_:A _005_:4 2.225 +5 _858_:QN _005_:1 1.655 *END *D_NET _006_ 1.73 *CONN -*I _763_/A I *D CLKBUF_X1 -*I _877_/QN O *D DFF_X1 +*I _763_:A I *D CLKBUF_X1 +*I _877_:QN O *D DFF_X1 *CAP 1 _006_:1 0.865 *RES 1 _006_:1 _006_:1 0.005 -2 _763_/A _006_:1 3.265 -3 _877_/QN _006_:1 0.205 +2 _763_:A _006_:1 3.265 +3 _877_:QN _006_:1 0.205 *END *D_NET _007_ 5.95 *CONN -*I _766_/A I *D CLKBUF_X1 -*I _878_/QN O *D DFF_X1 +*I _766_:A I *D CLKBUF_X1 +*I _878_:QN O *D DFF_X1 *CAP 1 _007_:1 1.2475 2 _007_:2 1.05 @@ -1762,14 +1762,14 @@ resp_val O 2 _007_:2 _007_:3 0.005 3 _007_:3 _007_:4 4.2 4 _007_:4 _007_:5 0.005 -5 _766_/A _007_:5 2.715 -6 _878_/QN _007_:1 0.795 +5 _766_:A _007_:5 2.715 +6 _878_:QN _007_:1 0.795 *END *D_NET _008_ 6.88 *CONN -*I _769_/A I *D CLKBUF_X1 -*I _879_/QN O *D DFF_X1 +*I _769_:A I *D CLKBUF_X1 +*I _879_:QN O *D DFF_X1 *CAP 1 _008_:1 1.56 2 _008_:2 1.05 @@ -1781,14 +1781,14 @@ resp_val O 2 _008_:2 _008_:3 0.005 3 _008_:3 _008_:4 4.2 4 _008_:4 _008_:5 0.005 -5 _769_/A _008_:1 2.045 -6 _879_/QN _008_:5 3.325 +5 _769_:A _008_:1 2.045 +6 _879_:QN _008_:5 3.325 *END *D_NET _009_ 4.02 *CONN -*I _772_/A I *D CLKBUF_X1 -*I _880_/QN O *D DFF_X1 +*I _772_:A I *D CLKBUF_X1 +*I _880_:QN O *D DFF_X1 *CAP 1 _009_:1 0.615 2 _009_:2 1.05 @@ -1798,14 +1798,14 @@ resp_val O 1 _009_:1 _009_:2 0.005 2 _009_:2 _009_:3 4.2 3 _009_:3 _009_:4 0.005 -4 _772_/A _009_:4 1.385 -5 _880_/QN _009_:1 2.465 +4 _772_:A _009_:4 1.385 +5 _880_:QN _009_:1 2.465 *END *D_NET _010_ 8.07 *CONN -*I _775_/A I *D CLKBUF_X1 -*I _881_/QN O *D DFF_X1 +*I _775_:A I *D CLKBUF_X1 +*I _881_:QN O *D DFF_X1 *CAP 1 _010_:1 0.1775 2 _010_:2 2.1 @@ -1817,14 +1817,14 @@ resp_val O 2 _010_:2 _010_:3 8.4 3 _010_:3 _010_:4 0.005 4 _010_:4 _010_:5 4.2 -5 _775_/A _010_:1 0.715 -6 _881_/QN _010_:5 2.835 +5 _775_:A _010_:1 0.715 +6 _881_:QN _010_:5 2.835 *END *D_NET _011_ 8.63 *CONN -*I _778_/A I *D CLKBUF_X1 -*I _882_/QN O *D DFF_X1 +*I _778_:A I *D CLKBUF_X1 +*I _882_:QN O *D DFF_X1 *CAP 1 _011_:1 1.6825 2 _011_:2 1.05 @@ -1836,27 +1836,27 @@ resp_val O 2 _011_:2 _011_:3 0.005 3 _011_:3 _011_:4 8.4 4 _011_:4 _011_:5 0.005 -5 _778_/A _011_:1 2.535 -6 _882_/QN _011_:5 2.135 +5 _778_:A _011_:1 2.535 +6 _882_:QN _011_:5 2.135 *END *D_NET _012_ 4.12 *CONN -*I _781_/A I *D CLKBUF_X1 -*I _883_/QN O *D DFF_X1 +*I _781_:A I *D CLKBUF_X1 +*I _883_:QN O *D DFF_X1 *CAP 1 _012_:1 1.6675 2 _012_:2 1.4425 *RES 1 _012_:2 _012_:1 4.2 -2 _781_/A _012_:2 1.575 -3 _883_/QN _012_:1 2.475 +2 _781_:A _012_:2 1.575 +3 _883_:QN _012_:1 2.475 *END *D_NET _013_ 7.52 *CONN -*I _784_/A I *D CLKBUF_X1 -*I _884_/QN O *D DFF_X1 +*I _784_:A I *D CLKBUF_X1 +*I _884_:QN O *D DFF_X1 *CAP 1 _013_:1 1.43 2 _013_:2 1.05 @@ -1868,27 +1868,27 @@ resp_val O 2 _013_:2 _013_:3 0.005 3 _013_:3 _013_:4 8.4 4 _013_:4 _013_:5 0.005 -5 _784_/A _013_:1 1.525 -6 _884_/QN _013_:5 0.925 +5 _784_:A _013_:1 1.525 +6 _884_:QN _013_:5 0.925 *END *D_NET _014_ 3.3 *CONN -*I _787_/A I *D CLKBUF_X1 -*I _885_/QN O *D DFF_X1 +*I _787_:A I *D CLKBUF_X1 +*I _885_:QN O *D DFF_X1 *CAP 1 _014_:1 1.385 2 _014_:2 1.315 *RES 1 _014_:1 _014_:2 4.2 -2 _787_/A _014_:2 1.065 -3 _885_/QN _014_:1 1.345 +2 _787_:A _014_:2 1.065 +3 _885_:QN _014_:1 1.345 *END *D_NET _015_ 3.95 *CONN -*I _790_/A I *D CLKBUF_X1 -*I _886_/QN O *D DFF_X1 +*I _790_:A I *D CLKBUF_X1 +*I _886_:QN O *D DFF_X1 *CAP 1 _015_:1 0.3025 2 _015_:2 1.05 @@ -1898,14 +1898,14 @@ resp_val O 1 _015_:1 _015_:2 0.005 2 _015_:2 _015_:3 4.2 3 _015_:3 _015_:4 0.005 -4 _790_/A _015_:4 2.495 -5 _886_/QN _015_:1 1.215 +4 _790_:A _015_:4 2.495 +5 _886_:QN _015_:1 1.215 *END *D_NET _016_ 7.15 *CONN -*I _793_/A I *D CLKBUF_X1 -*I _887_/QN O *D DFF_X1 +*I _793_:A I *D CLKBUF_X1 +*I _887_:QN O *D DFF_X1 *CAP 1 _016_:1 0.615 2 _016_:2 1.05 @@ -1917,27 +1917,27 @@ resp_val O 2 _016_:2 _016_:3 4.2 3 _016_:3 _016_:4 0.005 4 _016_:5 _016_:4 4.2 -5 _793_/A _016_:1 2.465 -6 _887_/QN _016_:5 3.445 +5 _793_:A _016_:1 2.465 +6 _887_:QN _016_:5 3.445 *END *D_NET _017_ 6.095 *CONN -*I _796_/A I *D CLKBUF_X1 -*I _888_/QN O *D DFF_X1 +*I _796_:A I *D CLKBUF_X1 +*I _888_:QN O *D DFF_X1 *CAP 1 _017_:1 2.655 2 _017_:2 2.4925 *RES 1 _017_:1 _017_:2 8.4 -2 _796_/A _017_:2 1.575 -3 _888_/QN _017_:1 2.225 +2 _796_:A _017_:2 1.575 +3 _888_:QN _017_:1 2.225 *END *D_NET _018_ 3.88 *CONN -*I _799_/A I *D CLKBUF_X1 -*I _889_/QN O *D DFF_X1 +*I _799_:A I *D CLKBUF_X1 +*I _889_:QN O *D DFF_X1 *CAP 1 _018_:1 0.425 2 _018_:2 1.05 @@ -1947,14 +1947,14 @@ resp_val O 1 _018_:1 _018_:2 0.005 2 _018_:2 _018_:3 4.2 3 _018_:3 _018_:4 0.005 -4 _799_/A _018_:1 1.705 -5 _889_/QN _018_:4 1.865 +4 _799_:A _018_:1 1.705 +5 _889_:QN _018_:4 1.865 *END *D_NET _019_ 6.16 *CONN -*I _802_/A I *D CLKBUF_X1 -*I _890_/QN O *D DFF_X1 +*I _802_:A I *D CLKBUF_X1 +*I _890_:QN O *D DFF_X1 *CAP 1 _019_:1 0.695 2 _019_:2 1.05 @@ -1966,14 +1966,14 @@ resp_val O 2 _019_:2 _019_:3 4.2 3 _019_:3 _019_:4 0.005 4 _019_:5 _019_:4 4.2 -5 _802_/A _019_:1 2.785 -6 _890_/QN _019_:5 1.145 +5 _802_:A _019_:1 2.785 +6 _890_:QN _019_:5 1.145 *END *D_NET _020_ 6.3 *CONN -*I _805_/A I *D CLKBUF_X1 -*I _891_/QN O *D DFF_X1 +*I _805_:A I *D CLKBUF_X1 +*I _891_:QN O *D DFF_X1 *CAP 1 _020_:1 1.5125 2 _020_:2 1.05 @@ -1985,14 +1985,14 @@ resp_val O 2 _020_:2 _020_:3 0.005 3 _020_:3 _020_:4 4.2 4 _020_:4 _020_:5 0.005 -5 _805_/A _020_:1 1.855 -6 _891_/QN _020_:5 2.355 +5 _805_:A _020_:1 1.855 +6 _891_:QN _020_:5 2.355 *END *D_NET _021_ 7.19 *CONN -*I _808_/A I *D CLKBUF_X1 -*I _892_/QN O *D DFF_X1 +*I _808_:A I *D CLKBUF_X1 +*I _892_:QN O *D DFF_X1 *CAP 1 _021_:1 1.87 2 _021_:2 1.05 @@ -2004,77 +2004,77 @@ resp_val O 2 _021_:2 _021_:3 0.005 3 _021_:3 _021_:4 4.2 4 _021_:4 _021_:5 0.005 -5 _808_/A _021_:5 2.705 -6 _892_/QN _021_:1 3.285 +5 _808_:A _021_:5 2.705 +6 _892_:QN _021_:1 3.285 *END *D_NET _022_ 3.07 *CONN -*I _765_/Z O *D CLKBUF_X1 -*I _861_/D I *D DFF_X1 +*I _765_:Z O *D CLKBUF_X1 +*I _861_:D I *D DFF_X1 *CAP 1 _022_:1 1.535 *RES 1 _022_:1 _022_:1 0.005 -2 _765_/Z _022_:1 5.065 -3 _861_/D _022_:1 1.085 +2 _765_:Z _022_:1 5.065 +3 _861_:D _022_:1 1.085 *END *D_NET _023_ 2.92 *CONN -*I _795_/Z O *D CLKBUF_X1 -*I _871_/D I *D DFF_X1 +*I _795_:Z O *D CLKBUF_X1 +*I _871_:D I *D DFF_X1 *CAP 1 _023_:1 1.46 *RES 1 _023_:1 _023_:1 0.005 -2 _795_/Z _023_:1 4.345 -3 _871_/D _023_:1 1.505 +2 _795_:Z _023_:1 4.345 +3 _871_:D _023_:1 1.505 *END *D_NET _024_ 4.8 *CONN -*I _798_/Z O *D CLKBUF_X1 -*I _872_/D I *D DFF_X1 +*I _798_:Z O *D CLKBUF_X1 +*I _872_:D I *D DFF_X1 *CAP 1 _024_:1 1.905 2 _024_:2 1.545 *RES 1 _024_:2 _024_:1 4.2 -2 _798_/Z _024_:1 3.425 -3 _872_/D _024_:2 1.985 +2 _798_:Z _024_:1 3.425 +3 _872_:D _024_:2 1.985 *END *D_NET _025_ 4.42 *CONN -*I _801_/Z O *D CLKBUF_X1 -*I _873_/D I *D DFF_X1 +*I _801_:Z O *D CLKBUF_X1 +*I _873_:D I *D DFF_X1 *CAP 1 _025_:1 1.56 2 _025_:2 1.7 *RES 1 _025_:1 _025_:2 4.2 -2 _801_/Z _025_:1 2.045 -3 _873_/D _025_:2 2.605 +2 _801_:Z _025_:1 2.045 +3 _873_:D _025_:2 2.605 *END *D_NET _026_ 4.82 *CONN -*I _804_/Z O *D CLKBUF_X1 -*I _874_/D I *D DFF_X1 +*I _804_:Z O *D CLKBUF_X1 +*I _874_:D I *D DFF_X1 *CAP 1 _026_:1 1.81 2 _026_:2 1.65 *RES 1 _026_:2 _026_:1 4.2 -2 _804_/Z _026_:1 3.045 -3 _874_/D _026_:2 2.405 +2 _804_:Z _026_:1 3.045 +3 _874_:D _026_:2 2.405 *END *D_NET _027_ 6.01 *CONN -*I _807_/Z O *D CLKBUF_X1 -*I _875_/D I *D DFF_X1 +*I _807_:Z O *D CLKBUF_X1 +*I _875_:D I *D DFF_X1 *CAP 1 _027_:1 0.1 2 _027_:2 1.05 @@ -2086,27 +2086,27 @@ resp_val O 2 _027_:2 _027_:3 4.2 3 _027_:3 _027_:4 0.005 4 _027_:5 _027_:4 4.2 -5 _807_/Z _027_:1 0.405 -6 _875_/D _027_:5 3.225 +5 _807_:Z _027_:1 0.405 +6 _875_:D _027_:5 3.225 *END *D_NET _028_ 3.88 *CONN -*I _810_/Z O *D CLKBUF_X1 -*I _876_/D I *D DFF_X1 +*I _810_:Z O *D CLKBUF_X1 +*I _876_:D I *D DFF_X1 *CAP 1 _028_:1 1.345 2 _028_:2 1.645 *RES 1 _028_:1 _028_:2 4.2 -2 _810_/Z _028_:1 1.185 -3 _876_/D _028_:2 2.385 +2 _810_:Z _028_:1 1.185 +3 _876_:D _028_:2 2.385 *END *D_NET _029_ 5.72 *CONN -*I _768_/Z O *D CLKBUF_X1 -*I _862_/D I *D DFF_X1 +*I _768_:Z O *D CLKBUF_X1 +*I _862_:D I *D DFF_X1 *CAP 1 _029_:1 1.205 2 _029_:2 1.05 @@ -2118,26 +2118,26 @@ resp_val O 2 _029_:2 _029_:3 0.005 3 _029_:3 _029_:4 4.2 4 _029_:4 _029_:5 0.005 -5 _768_/Z _029_:5 2.425 -6 _862_/D _029_:1 0.625 +5 _768_:Z _029_:5 2.425 +6 _862_:D _029_:1 0.625 *END *D_NET _030_ 2.72 *CONN -*I _771_/Z O *D CLKBUF_X1 -*I _863_/D I *D DFF_X1 +*I _771_:Z O *D CLKBUF_X1 +*I _863_:D I *D DFF_X1 *CAP 1 _030_:1 1.36 *RES 1 _030_:1 _030_:1 0.005 -2 _771_/Z _030_:1 4.505 -3 _863_/D _030_:1 0.945 +2 _771_:Z _030_:1 4.505 +3 _863_:D _030_:1 0.945 *END *D_NET _031_ 8.87 *CONN -*I _774_/Z O *D CLKBUF_X1 -*I _864_/D I *D DFF_X1 +*I _774_:Z O *D CLKBUF_X1 +*I _864_:D I *D DFF_X1 *CAP 1 _031_:1 2.1 2 _031_:2 3.02 @@ -2149,14 +2149,14 @@ resp_val O 2 _031_:1 _031_:3 0.005 3 _031_:3 _031_:4 4.2 4 _031_:4 _031_:5 0.005 -5 _774_/Z _031_:5 1.465 -6 _864_/D _031_:2 3.685 +5 _774_:Z _031_:5 1.465 +6 _864_:D _031_:2 3.685 *END *D_NET _032_ 6.45 *CONN -*I _777_/Z O *D CLKBUF_X1 -*I _865_/D I *D DFF_X1 +*I _777_:Z O *D CLKBUF_X1 +*I _865_:D I *D DFF_X1 *CAP 1 _032_:1 1.425 2 _032_:2 1.05 @@ -2168,52 +2168,52 @@ resp_val O 2 _032_:2 _032_:3 0.005 3 _032_:3 _032_:4 4.2 4 _032_:4 _032_:5 0.005 -5 _777_/Z _032_:1 1.505 -6 _865_/D _032_:5 3.005 +5 _777_:Z _032_:1 1.505 +6 _865_:D _032_:5 3.005 *END *D_NET _033_ 2.98 *CONN -*I _780_/Z O *D CLKBUF_X1 -*I _866_/D I *D DFF_X1 +*I _780_:Z O *D CLKBUF_X1 +*I _866_:D I *D DFF_X1 *CAP 1 _033_:1 1.235 2 _033_:2 1.305 *RES 1 _033_:1 _033_:2 4.2 -2 _780_/Z _033_:1 0.745 -3 _866_/D _033_:2 1.025 +2 _780_:Z _033_:1 0.745 +3 _866_:D _033_:2 1.025 *END *D_NET _034_ 3.15 *CONN -*I _783_/Z O *D CLKBUF_X1 -*I _867_/D I *D DFF_X1 +*I _783_:Z O *D CLKBUF_X1 +*I _867_:D I *D DFF_X1 *CAP 1 _034_:1 1.575 *RES 1 _034_:1 _034_:1 0.005 -2 _783_/Z _034_:1 2.985 -3 _867_/D _034_:1 3.325 +2 _783_:Z _034_:1 2.985 +3 _867_:D _034_:1 3.325 *END *D_NET _035_ 3.38 *CONN -*I _786_/Z O *D CLKBUF_X1 -*I _868_/D I *D DFF_X1 +*I _786_:Z O *D CLKBUF_X1 +*I _868_:D I *D DFF_X1 *CAP 1 _035_:1 1.505 2 _035_:2 1.235 *RES 1 _035_:1 _035_:2 4.2 -2 _786_/Z _035_:1 1.825 -3 _868_/D _035_:2 0.745 +2 _786_:Z _035_:1 1.825 +3 _868_:D _035_:2 0.745 *END *D_NET _036_ 7.03 *CONN -*I _789_/Z O *D CLKBUF_X1 -*I _869_/D I *D DFF_X1 +*I _789_:Z O *D CLKBUF_X1 +*I _869_:D I *D DFF_X1 *CAP 1 _036_:1 1.585 2 _036_:2 1.05 @@ -2225,14 +2225,14 @@ resp_val O 2 _036_:2 _036_:3 0.005 3 _036_:3 _036_:4 4.2 4 _036_:4 _036_:5 0.005 -5 _789_/Z _036_:5 3.525 -6 _869_/D _036_:1 2.145 +5 _789_:Z _036_:5 3.525 +6 _869_:D _036_:1 2.145 *END *D_NET _037_ 5.79 *CONN -*I _792_/Z O *D CLKBUF_X1 -*I _870_/D I *D DFF_X1 +*I _792_:Z O *D CLKBUF_X1 +*I _870_:D I *D DFF_X1 *CAP 1 _037_:1 0.265 2 _037_:2 1.05 @@ -2244,27 +2244,27 @@ resp_val O 2 _037_:2 _037_:3 4.2 3 _037_:3 _037_:4 0.005 4 _037_:5 _037_:4 4.2 -5 _792_/Z _037_:5 2.125 -6 _870_/D _037_:1 1.065 +5 _792_:Z _037_:5 2.125 +6 _870_:D _037_:1 1.065 *END *D_NET _038_ 3.58 *CONN -*I _812_/Z O *D CLKBUF_X1 -*I _877_/D I *D DFF_X1 +*I _812_:Z O *D CLKBUF_X1 +*I _877_:D I *D DFF_X1 *CAP 1 _038_:1 1.6 2 _038_:2 1.24 *RES 1 _038_:2 _038_:1 4.2 -2 _812_/Z _038_:1 2.205 -3 _877_/D _038_:2 0.765 +2 _812_:Z _038_:1 2.205 +3 _877_:D _038_:2 0.765 *END *D_NET _039_ 7.32 *CONN -*I _832_/Z O *D CLKBUF_X1 -*I _887_/D I *D DFF_X1 +*I _832_:Z O *D CLKBUF_X1 +*I _887_:D I *D DFF_X1 *CAP 1 _039_:1 1.8 2 _039_:2 1.05 @@ -2276,39 +2276,39 @@ resp_val O 2 _039_:2 _039_:3 0.005 3 _039_:3 _039_:4 4.2 4 _039_:4 _039_:5 0.005 -5 _832_/Z _039_:5 3.245 -6 _887_/D _039_:1 3.005 +5 _832_:Z _039_:5 3.245 +6 _887_:D _039_:1 3.005 *END *D_NET _040_ 2.73 *CONN -*I _834_/Z O *D CLKBUF_X1 -*I _888_/D I *D DFF_X1 +*I _834_:Z O *D CLKBUF_X1 +*I _888_:D I *D DFF_X1 *CAP 1 _040_:1 1.365 *RES 1 _040_:1 _040_:1 0.005 -2 _834_/Z _040_:1 3.085 -3 _888_/D _040_:1 2.385 +2 _834_:Z _040_:1 3.085 +3 _888_:D _040_:1 2.385 *END *D_NET _041_ 3.56 *CONN -*I _836_/Z O *D CLKBUF_X1 -*I _889_/D I *D DFF_X1 +*I _836_:Z O *D CLKBUF_X1 +*I _889_:D I *D DFF_X1 *CAP 1 _041_:1 1.275 2 _041_:2 1.555 *RES 1 _041_:2 _041_:1 4.2 -2 _836_/Z _041_:1 0.905 -3 _889_/D _041_:2 2.025 +2 _836_:Z _041_:1 0.905 +3 _889_:D _041_:2 2.025 *END *D_NET _042_ 8.15 *CONN -*I _838_/Z O *D CLKBUF_X1 -*I _890_/D I *D DFF_X1 +*I _838_:Z O *D CLKBUF_X1 +*I _890_:D I *D DFF_X1 *CAP 1 _042_:1 0.235 2 _042_:2 2.1 @@ -2320,14 +2320,14 @@ resp_val O 2 _042_:2 _042_:3 8.4 3 _042_:3 _042_:4 0.005 4 _042_:4 _042_:5 4.2 -5 _838_/Z _042_:5 2.765 -6 _890_/D _042_:1 0.945 +5 _838_:Z _042_:5 2.765 +6 _890_:D _042_:1 0.945 *END *D_NET _043_ 8.19 *CONN -*I _840_/Z O *D CLKBUF_X1 -*I _891_/D I *D DFF_X1 +*I _840_:Z O *D CLKBUF_X1 +*I _891_:D I *D DFF_X1 *CAP 1 _043_:1 1.69 2 _043_:2 1.05 @@ -2339,27 +2339,27 @@ resp_val O 2 _043_:2 _043_:3 0.005 3 _043_:3 _043_:4 8.4 4 _043_:4 _043_:5 0.005 -5 _840_/Z _043_:5 1.225 -6 _891_/D _043_:1 2.565 +5 _840_:Z _043_:5 1.225 +6 _891_:D _043_:1 2.565 *END *D_NET _044_ 5.56 *CONN -*I _842_/Z O *D CLKBUF_X1 -*I _892_/D I *D DFF_X1 +*I _842_:Z O *D CLKBUF_X1 +*I _892_:D I *D DFF_X1 *CAP 1 _044_:1 1.99 2 _044_:2 1.84 *RES 1 _044_:2 _044_:1 4.2 -2 _842_/Z _044_:1 3.765 -3 _892_/D _044_:2 3.165 +2 _842_:Z _044_:1 3.765 +3 _892_:D _044_:2 3.165 *END *D_NET _045_ 6.38 *CONN -*I _814_/Z O *D CLKBUF_X1 -*I _878_/D I *D DFF_X1 +*I _814_:Z O *D CLKBUF_X1 +*I _878_:D I *D DFF_X1 *CAP 1 _045_:1 0.335 2 _045_:2 1.05 @@ -2371,14 +2371,14 @@ resp_val O 2 _045_:2 _045_:3 4.2 3 _045_:3 _045_:4 0.005 4 _045_:5 _045_:4 4.2 -5 _814_/Z _045_:5 3.025 -6 _878_/D _045_:1 1.345 +5 _814_:Z _045_:5 3.025 +6 _878_:D _045_:1 1.345 *END *D_NET _046_ 7.48 *CONN -*I _816_/Z O *D CLKBUF_X1 -*I _879_/D I *D DFF_X1 +*I _816_:Z O *D CLKBUF_X1 +*I _879_:D I *D DFF_X1 *CAP 1 _046_:1 1.65 2 _046_:2 1.05 @@ -2390,14 +2390,14 @@ resp_val O 2 _046_:2 _046_:3 0.005 3 _046_:3 _046_:4 4.2 4 _046_:4 _046_:5 0.005 -5 _816_/Z _046_:5 4.165 -6 _879_/D _046_:1 2.405 +5 _816_:Z _046_:5 4.165 +6 _879_:D _046_:1 2.405 *END *D_NET _047_ 9.03 *CONN -*I _818_/Z O *D CLKBUF_X1 -*I _880_/D I *D DFF_X1 +*I _818_:Z O *D CLKBUF_X1 +*I _880_:D I *D DFF_X1 *CAP 1 _047_:1 1.895 2 _047_:2 1.05 @@ -2411,39 +2411,39 @@ resp_val O 3 _047_:3 _047_:4 4.2 4 _047_:4 _047_:5 0.005 5 _047_:5 _047_:6 4.2 -6 _818_/Z _047_:6 2.085 -7 _880_/D _047_:1 3.385 +6 _818_:Z _047_:6 2.085 +7 _880_:D _047_:1 3.385 *END *D_NET _048_ 2.38 *CONN -*I _820_/Z O *D CLKBUF_X1 -*I _881_/D I *D DFF_X1 +*I _820_:Z O *D CLKBUF_X1 +*I _881_:D I *D DFF_X1 *CAP 1 _048_:1 1.19 *RES 1 _048_:1 _048_:1 0.005 -2 _820_/Z _048_:1 2.485 -3 _881_/D _048_:1 2.285 +2 _820_:Z _048_:1 2.485 +3 _881_:D _048_:1 2.285 *END *D_NET _049_ 3.59 *CONN -*I _822_/Z O *D CLKBUF_X1 -*I _882_/D I *D DFF_X1 +*I _822_:Z O *D CLKBUF_X1 +*I _882_:D I *D DFF_X1 *CAP 1 _049_:1 1.315 2 _049_:2 1.53 *RES 1 _049_:1 _049_:2 4.2 -2 _822_/Z _049_:1 1.065 -3 _882_/D _049_:2 1.925 +2 _822_:Z _049_:1 1.065 +3 _882_:D _049_:2 1.925 *END *D_NET _050_ 6.29 *CONN -*I _824_/Z O *D CLKBUF_X1 -*I _883_/D I *D DFF_X1 +*I _824_:Z O *D CLKBUF_X1 +*I _883_:D I *D DFF_X1 *CAP 1 _050_:1 1.365 2 _050_:2 1.05 @@ -2455,14 +2455,14 @@ resp_val O 2 _050_:2 _050_:3 0.005 3 _050_:3 _050_:4 4.2 4 _050_:4 _050_:5 0.005 -5 _824_/Z _050_:1 1.265 -6 _883_/D _050_:5 2.925 +5 _824_:Z _050_:1 1.265 +6 _883_:D _050_:5 2.925 *END *D_NET _051_ 4.23 *CONN -*I _826_/Z O *D CLKBUF_X1 -*I _884_/D I *D DFF_X1 +*I _826_:Z O *D CLKBUF_X1 +*I _884_:D I *D DFF_X1 *CAP 1 _051_:1 0.18 2 _051_:2 1.05 @@ -2472,27 +2472,27 @@ resp_val O 1 _051_:1 _051_:2 0.005 2 _051_:2 _051_:3 4.2 3 _051_:3 _051_:4 0.005 -4 _826_/Z _051_:4 3.545 -5 _884_/D _051_:1 0.725 +4 _826_:Z _051_:4 3.545 +5 _884_:D _051_:1 0.725 *END *D_NET _052_ 4.32 *CONN -*I _828_/Z O *D CLKBUF_X1 -*I _885_/D I *D DFF_X1 +*I _828_:Z O *D CLKBUF_X1 +*I _885_:D I *D DFF_X1 *CAP 1 _052_:1 1.875 2 _052_:2 1.335 *RES 1 _052_:2 _052_:1 4.2 -2 _828_/Z _052_:1 3.305 -3 _885_/D _052_:2 1.145 +2 _828_:Z _052_:1 3.305 +3 _885_:D _052_:2 1.145 *END *D_NET _053_ 5.7 *CONN -*I _830_/Z O *D CLKBUF_X1 -*I _886_/D I *D DFF_X1 +*I _830_:Z O *D CLKBUF_X1 +*I _886_:D I *D DFF_X1 *CAP 1 _053_:1 0.185 2 _053_:2 1.05 @@ -2504,14 +2504,14 @@ resp_val O 2 _053_:2 _053_:3 4.2 3 _053_:3 _053_:4 0.005 4 _053_:5 _053_:4 4.2 -5 _830_/Z _053_:5 2.265 -6 _886_/D _053_:1 0.745 +5 _830_:Z _053_:5 2.265 +6 _886_:D _053_:1 0.745 *END *D_NET _054_ 9.575 *CONN -*I _465_/ZN O *D OR3_X1 -*I _762_/A I *D CLKBUF_X1 +*I _465_:ZN O *D OR3_X1 +*I _762_:A I *D CLKBUF_X1 *CAP 1 _054_:1 0.3525 2 _054_:2 2.1 @@ -2523,14 +2523,14 @@ resp_val O 2 _054_:2 _054_:3 8.4 3 _054_:3 _054_:4 0.005 4 _054_:4 _054_:5 4.2 -5 _465_/ZN _054_:5 5.145 -6 _762_/A _054_:1 1.415 +5 _465_:ZN _054_:5 5.145 +6 _762_:A _054_:1 1.415 *END *D_NET _055_ 9.035 *CONN -*I _455_/ZN O *D NAND2_X1 -*I _758_/A I *D CLKBUF_X1 +*I _455_:ZN O *D NAND2_X1 +*I _758_:A I *D CLKBUF_X1 *CAP 1 _055_:1 0.8275 2 _055_:2 3.15 @@ -2540,14 +2540,14 @@ resp_val O 1 _055_:1 _055_:2 0.005 2 _055_:2 _055_:3 12.6 3 _055_:3 _055_:4 0.005 -4 _455_/ZN _055_:4 2.165 -5 _758_/A _055_:1 3.315 +4 _455_:ZN _055_:4 2.165 +5 _758_:A _055_:1 3.315 *END *D_NET _056_ 4.63 *CONN -*I _461_/ZN O *D NAND2_X1 -*I _761_/A I *D CLKBUF_X1 +*I _461_:ZN O *D NAND2_X1 +*I _761_:A I *D CLKBUF_X1 *CAP 1 _056_:1 0.545 2 _056_:2 1.05 @@ -2557,15 +2557,15 @@ resp_val O 1 _056_:1 _056_:2 0.005 2 _056_:2 _056_:3 4.2 3 _056_:3 _056_:4 0.005 -4 _461_/ZN _056_:4 2.885 -5 _761_/A _056_:1 2.185 +4 _461_:ZN _056_:4 2.885 +5 _761_:A _056_:1 2.185 *END *D_NET _057_ 5.545 *CONN -*I _454_/A3 I *D OR3_X1 -*I _463_/A2 I *D NOR2_X1 -*I _757_/Z O *D CLKBUF_X1 +*I _454_:A3 I *D OR3_X1 +*I _463_:A2 I *D NOR2_X1 +*I _757_:Z O *D CLKBUF_X1 *CAP 1 _057_:1 0.635 2 _057_:2 1.05 @@ -2575,15 +2575,15 @@ resp_val O 1 _057_:1 _057_:2 0.005 2 _057_:2 _057_:3 4.2 3 _057_:3 _057_:4 0.005 -4 _454_/A3 _057_:4 2.895 -5 _463_/A2 _057_:4 1.465 -6 _757_/Z _057_:1 2.545 +4 _454_:A3 _057_:4 2.895 +5 _463_:A2 _057_:4 1.465 +6 _757_:Z _057_:1 2.545 *END *D_NET _058_ 5.71 *CONN -*I _451_/A I *D INV_X1 -*I _756_/Z O *D CLKBUF_X1 +*I _451_:A I *D INV_X1 +*I _756_:Z O *D CLKBUF_X1 *CAP 1 _058_:1 1.61 2 _058_:2 1.05 @@ -2595,18 +2595,18 @@ resp_val O 2 _058_:2 _058_:3 0.005 3 _058_:3 _058_:4 4.2 4 _058_:4 _058_:5 0.005 -5 _451_/A _058_:5 0.785 -6 _756_/Z _058_:1 2.245 +5 _451_:A _058_:5 0.785 +6 _756_:Z _058_:1 2.245 *END *D_NET _059_ 26.42 *CONN -*I _439_/A3 I *D AND3_X1 -*I _457_/A I *D INV_X2 -*I _464_/B I *D AOI211_X1 -*I _531_/A2 I *D AND2_X1 -*I _684_/A2 I *D NAND2_X2 -*I _720_/Z O *D BUF_X1 +*I _439_:A3 I *D AND3_X1 +*I _457_:A I *D INV_X2 +*I _464_:B I *D AOI211_X1 +*I _531_:A2 I *D AND2_X1 +*I _684_:A2 I *D NAND2_X2 +*I _720_:Z O *D BUF_X1 *CAP 1 _059_:1 2.8425 2 _059_:2 2.0175 @@ -2630,31 +2630,31 @@ resp_val O 8 _059_:9 _059_:10 0.005 9 _059_:10 _059_:11 16.8 10 _059_:11 _059_:4 0.005 -11 _439_/A3 _059_:1 2.975 -12 _457_/A _059_:9 2.495 -13 _464_/B _059_:2 3.875 -14 _531_/A2 _059_:4 2.415 -15 _684_/A2 _059_:3 2.125 -16 _720_/Z _059_:5 1.185 +11 _439_:A3 _059_:1 2.975 +12 _457_:A _059_:9 2.495 +13 _464_:B _059_:2 3.875 +14 _531_:A2 _059_:4 2.415 +15 _684_:A2 _059_:3 2.125 +16 _720_:Z _059_:5 1.185 *END *D_NET _060_ 5.565 *CONN -*I _547_/C2 I *D OAI211_X1 -*I _763_/Z O *D CLKBUF_X1 +*I _547_:C2 I *D OAI211_X1 +*I _763_:Z O *D CLKBUF_X1 *CAP 1 _060_:1 2.325 2 _060_:2 1.5075 *RES 1 _060_:2 _060_:1 4.2 -2 _547_/C2 _060_:2 1.835 -3 _763_/Z _060_:1 5.105 +2 _547_:C2 _060_:2 1.835 +3 _763_:Z _060_:1 5.105 *END *D_NET _061_ 7.115 *CONN -*I _559_/C2 I *D OAI211_X1 -*I _766_/Z O *D CLKBUF_X1 +*I _559_:C2 I *D OAI211_X1 +*I _766_:Z O *D CLKBUF_X1 *CAP 1 _061_:1 0.675 2 _061_:2 2.1 @@ -2664,14 +2664,14 @@ resp_val O 1 _061_:1 _061_:2 0.005 2 _061_:2 _061_:3 8.4 3 _061_:3 _061_:4 0.005 -4 _559_/C2 _061_:4 3.135 -5 _766_/Z _061_:1 2.705 +4 _559_:C2 _061_:4 3.135 +5 _766_:Z _061_:1 2.705 *END *D_NET _062_ 6.595 *CONN -*I _565_/C2 I *D OAI211_X1 -*I _769_/Z O *D CLKBUF_X1 +*I _565_:C2 I *D OAI211_X1 +*I _769_:Z O *D CLKBUF_X1 *CAP 1 _062_:1 2.0075 2 _062_:2 1.05 @@ -2683,14 +2683,14 @@ resp_val O 2 _062_:2 _062_:3 0.005 3 _062_:3 _062_:4 4.2 4 _062_:4 _062_:5 0.005 -5 _565_/C2 _062_:1 3.835 -6 _769_/Z _062_:5 0.965 +5 _565_:C2 _062_:1 3.835 +6 _769_:Z _062_:5 0.965 *END *D_NET _063_ 4.11 *CONN -*I _574_/C2 I *D OAI211_X1 -*I _772_/Z O *D CLKBUF_X1 +*I _574_:C2 I *D OAI211_X1 +*I _772_:Z O *D CLKBUF_X1 *CAP 1 _063_:1 0.465 2 _063_:2 1.05 @@ -2700,14 +2700,14 @@ resp_val O 1 _063_:1 _063_:2 0.005 2 _063_:2 _063_:3 4.2 3 _063_:3 _063_:4 0.005 -4 _574_/C2 _063_:4 2.165 -5 _772_/Z _063_:1 1.865 +4 _574_:C2 _063_:4 2.165 +5 _772_:Z _063_:1 1.865 *END *D_NET _064_ 3.605 *CONN -*I _583_/C2 I *D OAI211_X1 -*I _775_/Z O *D CLKBUF_X1 +*I _583_:C2 I *D OAI211_X1 +*I _775_:Z O *D CLKBUF_X1 *CAP 1 _064_:1 0.3725 2 _064_:2 1.05 @@ -2717,14 +2717,14 @@ resp_val O 1 _064_:1 _064_:2 0.005 2 _064_:2 _064_:3 4.2 3 _064_:3 _064_:4 0.005 -4 _583_/C2 _064_:1 1.495 -5 _775_/Z _064_:4 1.525 +4 _583_:C2 _064_:1 1.495 +5 _775_:Z _064_:4 1.525 *END *D_NET _065_ 10 *CONN -*I _591_/C2 I *D OAI211_X1 -*I _778_/Z O *D CLKBUF_X1 +*I _591_:C2 I *D OAI211_X1 +*I _778_:Z O *D CLKBUF_X1 *CAP 1 _065_:1 1.96 2 _065_:2 1.05 @@ -2736,14 +2736,14 @@ resp_val O 2 _065_:2 _065_:3 0.005 3 _065_:3 _065_:4 8.4 4 _065_:4 _065_:5 0.005 -5 _591_/C2 _065_:1 3.645 -6 _778_/Z _065_:5 3.765 +5 _591_:C2 _065_:1 3.645 +6 _778_:Z _065_:5 3.765 *END *D_NET _066_ 4.94 *CONN -*I _599_/C2 I *D OAI211_X1 -*I _781_/Z O *D CLKBUF_X1 +*I _599_:C2 I *D OAI211_X1 +*I _781_:Z O *D CLKBUF_X1 *CAP 1 _066_:1 0.595 2 _066_:2 1.05 @@ -2753,14 +2753,14 @@ resp_val O 1 _066_:1 _066_:2 0.005 2 _066_:2 _066_:3 4.2 3 _066_:3 _066_:4 0.005 -4 _599_/C2 _066_:4 3.305 -5 _781_/Z _066_:1 2.385 +4 _599_:C2 _066_:4 3.305 +5 _781_:Z _066_:1 2.385 *END *D_NET _067_ 6.395 *CONN -*I _608_/C2 I *D OAI211_X1 -*I _784_/Z O *D CLKBUF_X1 +*I _608_:C2 I *D OAI211_X1 +*I _784_:Z O *D CLKBUF_X1 *CAP 1 _067_:1 1.3075 2 _067_:2 1.05 @@ -2772,14 +2772,14 @@ resp_val O 2 _067_:2 _067_:3 0.005 3 _067_:3 _067_:4 4.2 4 _067_:4 _067_:5 0.005 -5 _608_/C2 _067_:1 1.035 -6 _784_/Z _067_:5 3.365 +5 _608_:C2 _067_:1 1.035 +6 _784_:Z _067_:5 3.365 *END *D_NET _068_ 7.48 *CONN -*I _617_/C2 I *D OAI211_X1 -*I _787_/Z O *D CLKBUF_X1 +*I _617_:C2 I *D OAI211_X1 +*I _787_:Z O *D CLKBUF_X1 *CAP 1 _068_:1 0.725 2 _068_:2 1.05 @@ -2791,14 +2791,14 @@ resp_val O 2 _068_:2 _068_:3 4.2 3 _068_:3 _068_:4 0.005 4 _068_:5 _068_:4 4.2 -5 _617_/C2 _068_:5 3.665 -6 _787_/Z _068_:1 2.905 +5 _617_:C2 _068_:5 3.665 +6 _787_:Z _068_:1 2.905 *END *D_NET _069_ 3.15 *CONN -*I _626_/C2 I *D OAI211_X1 -*I _790_/Z O *D CLKBUF_X1 +*I _626_:C2 I *D OAI211_X1 +*I _790_:Z O *D CLKBUF_X1 *CAP 1 _069_:1 0.255 2 _069_:2 1.05 @@ -2808,14 +2808,14 @@ resp_val O 1 _069_:1 _069_:2 0.005 2 _069_:2 _069_:3 4.2 3 _069_:3 _069_:4 0.005 -4 _626_/C2 _069_:4 1.085 -5 _790_/Z _069_:1 1.025 +4 _626_:C2 _069_:4 1.085 +5 _790_:Z _069_:1 1.025 *END *D_NET _070_ 7.255 *CONN -*I _635_/C2 I *D OAI211_X1 -*I _793_/Z O *D CLKBUF_X1 +*I _635_:C2 I *D OAI211_X1 +*I _793_:Z O *D CLKBUF_X1 *CAP 1 _070_:1 1.5025 2 _070_:2 1.05 @@ -2827,27 +2827,27 @@ resp_val O 2 _070_:2 _070_:3 0.005 3 _070_:3 _070_:4 4.2 4 _070_:4 _070_:5 0.005 -5 _635_/C2 _070_:1 1.815 -6 _793_/Z _070_:5 4.305 +5 _635_:C2 _070_:1 1.815 +6 _793_:Z _070_:5 4.305 *END *D_NET _071_ 5.33 *CONN -*I _638_/B2 I *D OAI21_X1 -*I _796_/Z O *D CLKBUF_X1 +*I _638_:B2 I *D OAI21_X1 +*I _796_:Z O *D CLKBUF_X1 *CAP 1 _071_:1 1.82 2 _071_:2 1.895 *RES 1 _071_:1 _071_:2 4.2 -2 _638_/B2 _071_:2 3.385 -3 _796_/Z _071_:1 3.085 +2 _638_:B2 _071_:2 3.385 +3 _796_:Z _071_:1 3.085 *END *D_NET _072_ 10.795 *CONN -*I _655_/C2 I *D OAI211_X1 -*I _799_/Z O *D CLKBUF_X1 +*I _655_:C2 I *D OAI211_X1 +*I _799_:Z O *D CLKBUF_X1 *CAP 1 _072_:1 2.7925 2 _072_:2 2.1 @@ -2859,15 +2859,15 @@ resp_val O 2 _072_:2 _072_:3 0.005 3 _072_:3 _072_:4 8.4 4 _072_:4 _072_:5 0.005 -5 _655_/C2 _072_:1 2.775 -6 _799_/Z _072_:5 2.025 +5 _655_:C2 _072_:1 2.775 +6 _799_:Z _072_:5 2.025 *END *D_NET _073_ 13.705 *CONN -*I _663_/C1 I *D OAI211_X1 -*I _667_/B2 I *D AOI22_X1 -*I _802_/Z O *D CLKBUF_X1 +*I _663_:C1 I *D OAI211_X1 +*I _667_:B2 I *D AOI22_X1 +*I _802_:Z O *D CLKBUF_X1 *CAP 1 _073_:1 0.41 2 _073_:2 1.05 @@ -2885,15 +2885,15 @@ resp_val O 5 _073_:3 _073_:6 8.4 6 _073_:6 _073_:7 0.005 7 _073_:8 _073_:7 4.2 -8 _663_/C1 _073_:1 1.645 -9 _667_/B2 _073_:5 1.675 -10 _802_/Z _073_:8 3.105 +8 _663_:C1 _073_:1 1.645 +9 _667_:B2 _073_:5 1.675 +10 _802_:Z _073_:8 3.105 *END *D_NET _074_ 5.03 *CONN -*I _673_/C1 I *D OAI211_X1 -*I _805_/Z O *D CLKBUF_X1 +*I _673_:C1 I *D OAI211_X1 +*I _805_:Z O *D CLKBUF_X1 *CAP 1 _074_:1 0.88 2 _074_:2 1.05 @@ -2903,40 +2903,40 @@ resp_val O 1 _074_:1 _074_:2 0.005 2 _074_:2 _074_:3 4.2 3 _074_:3 _074_:4 0.005 -4 _673_/C1 _074_:1 3.525 -5 _805_/Z _074_:4 2.345 +4 _673_:C1 _074_:1 3.525 +5 _805_:Z _074_:4 2.345 *END *D_NET _075_ 4.23 *CONN -*I _680_/B2 I *D OAI21_X1 -*I _808_/Z O *D CLKBUF_X1 +*I _680_:B2 I *D OAI21_X1 +*I _808_:Z O *D CLKBUF_X1 *CAP 1 _075_:1 1.885 2 _075_:2 1.28 *RES 1 _075_:1 _075_:2 4.2 -2 _680_/B2 _075_:2 0.925 -3 _808_/Z _075_:1 3.345 +2 _680_:B2 _075_:2 0.925 +3 _808_:Z _075_:1 3.345 *END *D_NET _076_ 5.02 *CONN -*I _551_/Z O *D MUX2_X1 -*I _765_/A I *D CLKBUF_X1 +*I _551_:Z O *D MUX2_X1 +*I _765_:A I *D CLKBUF_X1 *CAP 1 _076_:1 1.705 2 _076_:2 1.855 *RES 1 _076_:1 _076_:2 4.2 -2 _551_/Z _076_:1 2.625 -3 _765_/A _076_:2 3.225 +2 _551_:Z _076_:1 2.625 +3 _765_:A _076_:2 3.225 *END *D_NET _077_ 6.9 *CONN -*I _636_/Z O *D MUX2_X1 -*I _795_/A I *D CLKBUF_X1 +*I _636_:Z O *D MUX2_X1 +*I _795_:A I *D CLKBUF_X1 *CAP 1 _077_:1 0.625 2 _077_:2 1.05 @@ -2948,27 +2948,27 @@ resp_val O 2 _077_:2 _077_:3 4.2 3 _077_:3 _077_:4 0.005 4 _077_:5 _077_:4 4.2 -5 _636_/Z _077_:5 2.905 -6 _795_/A _077_:1 2.505 +5 _636_:Z _077_:5 2.905 +6 _795_:A _077_:1 2.505 *END *D_NET _078_ 3.235 *CONN -*I _646_/ZN O *D OAI21_X1 -*I _798_/A I *D CLKBUF_X1 +*I _646_:ZN O *D OAI21_X1 +*I _798_:A I *D CLKBUF_X1 *CAP 1 _078_:1 1.2225 2 _078_:2 1.445 *RES 1 _078_:2 _078_:1 4.2 -2 _646_/ZN _078_:1 0.695 -3 _798_/A _078_:2 1.585 +2 _646_:ZN _078_:1 0.695 +3 _798_:A _078_:2 1.585 *END *D_NET _079_ 3.895 *CONN -*I _656_/Z O *D MUX2_X1 -*I _801_/A I *D CLKBUF_X1 +*I _656_:Z O *D MUX2_X1 +*I _801_:A I *D CLKBUF_X1 *CAP 1 _079_:1 0.385 2 _079_:2 1.05 @@ -2978,27 +2978,27 @@ resp_val O 1 _079_:1 _079_:2 0.005 2 _079_:2 _079_:3 4.2 3 _079_:3 _079_:4 0.005 -4 _656_/Z _079_:1 1.545 -5 _801_/A _079_:4 2.055 +4 _656_:Z _079_:1 1.545 +5 _801_:A _079_:4 2.055 *END *D_NET _080_ 5.13 *CONN -*I _664_/Z O *D MUX2_X1 -*I _804_/A I *D CLKBUF_X1 +*I _664_:Z O *D MUX2_X1 +*I _804_:A I *D CLKBUF_X1 *CAP 1 _080_:1 1.885 2 _080_:2 1.73 *RES 1 _080_:2 _080_:1 4.2 -2 _664_/Z _080_:1 3.345 -3 _804_/A _080_:2 2.725 +2 _664_:Z _080_:1 3.345 +3 _804_:A _080_:2 2.725 *END *D_NET _081_ 6.22 *CONN -*I _674_/Z O *D MUX2_X1 -*I _807_/A I *D CLKBUF_X1 +*I _674_:Z O *D MUX2_X1 +*I _807_:A I *D CLKBUF_X1 *CAP 1 _081_:1 1.42 2 _081_:2 1.05 @@ -3010,14 +3010,14 @@ resp_val O 2 _081_:2 _081_:3 0.005 3 _081_:3 _081_:4 4.2 4 _081_:4 _081_:5 0.005 -5 _674_/Z _081_:5 2.565 -6 _807_/A _081_:1 1.485 +5 _674_:Z _081_:5 2.565 +6 _807_:A _081_:1 1.485 *END *D_NET _082_ 4.61 *CONN -*I _682_/ZN O *D OAI21_X1 -*I _810_/A I *D CLKBUF_X1 +*I _682_:ZN O *D OAI21_X1 +*I _810_:A I *D CLKBUF_X1 *CAP 1 _082_:1 0.6725 2 _082_:2 1.05 @@ -3027,14 +3027,14 @@ resp_val O 1 _082_:1 _082_:2 0.005 2 _082_:2 _082_:3 4.2 3 _082_:3 _082_:4 0.005 -4 _682_/ZN _082_:1 2.695 -5 _810_/A _082_:4 2.335 +4 _682_:ZN _082_:1 2.695 +5 _810_:A _082_:4 2.335 *END *D_NET _083_ 7.35 *CONN -*I _560_/Z O *D MUX2_X1 -*I _768_/A I *D CLKBUF_X1 +*I _560_:Z O *D MUX2_X1 +*I _768_:A I *D CLKBUF_X1 *CAP 1 _083_:1 1.255 2 _083_:2 1.05 @@ -3046,52 +3046,52 @@ resp_val O 2 _083_:2 _083_:3 0.005 3 _083_:3 _083_:4 8.4 4 _083_:4 _083_:5 0.005 -5 _560_/Z _083_:5 1.285 -6 _768_/A _083_:1 0.825 +5 _560_:Z _083_:5 1.285 +6 _768_:A _083_:1 0.825 *END *D_NET _084_ 6.55 *CONN -*I _566_/Z O *D MUX2_X1 -*I _771_/A I *D CLKBUF_X1 +*I _566_:Z O *D MUX2_X1 +*I _771_:A I *D CLKBUF_X1 *CAP 1 _084_:1 2.23 2 _084_:2 3.145 *RES 1 _084_:1 _084_:2 8.4 -2 _566_/Z _084_:1 0.525 -3 _771_/A _084_:2 4.185 +2 _566_:Z _084_:1 0.525 +3 _771_:A _084_:2 4.185 *END *D_NET _085_ 3.2 *CONN -*I _575_/Z O *D MUX2_X1 -*I _774_/A I *D CLKBUF_X1 +*I _575_:Z O *D MUX2_X1 +*I _774_:A I *D CLKBUF_X1 *CAP 1 _085_:1 1.6 *RES 1 _085_:1 _085_:1 0.005 -2 _575_/Z _085_:1 3.865 -3 _774_/A _085_:1 2.545 +2 _575_:Z _085_:1 3.865 +3 _774_:A _085_:1 2.545 *END *D_NET _086_ 3.56 *CONN -*I _584_/Z O *D MUX2_X1 -*I _777_/A I *D CLKBUF_X1 +*I _584_:Z O *D MUX2_X1 +*I _777_:A I *D CLKBUF_X1 *CAP 1 _086_:1 1.515 2 _086_:2 1.315 *RES 1 _086_:2 _086_:1 4.2 -2 _584_/Z _086_:1 1.865 -3 _777_/A _086_:2 1.065 +2 _584_:Z _086_:1 1.865 +3 _777_:A _086_:2 1.065 *END *D_NET _087_ 3.185 *CONN -*I _592_/Z O *D MUX2_X1 -*I _780_/A I *D CLKBUF_X1 +*I _592_:Z O *D MUX2_X1 +*I _780_:A I *D CLKBUF_X1 *CAP 1 _087_:1 0.35 2 _087_:2 1.05 @@ -3101,39 +3101,39 @@ resp_val O 1 _087_:1 _087_:2 0.005 2 _087_:2 _087_:3 4.2 3 _087_:3 _087_:4 0.005 -4 _592_/Z _087_:1 1.405 -5 _780_/A _087_:4 0.775 +4 _592_:Z _087_:1 1.405 +5 _780_:A _087_:4 0.775 *END *D_NET _088_ 2.86 *CONN -*I _600_/Z O *D MUX2_X1 -*I _783_/A I *D CLKBUF_X1 +*I _600_:Z O *D MUX2_X1 +*I _783_:A I *D CLKBUF_X1 *CAP 1 _088_:1 1.145 2 _088_:2 1.335 *RES 1 _088_:2 _088_:1 4.2 -2 _600_/Z _088_:1 0.385 -3 _783_/A _088_:2 1.145 +2 _600_:Z _088_:1 0.385 +3 _783_:A _088_:2 1.145 *END *D_NET _089_ 2.725 *CONN -*I _609_/Z O *D MUX2_X1 -*I _786_/A I *D CLKBUF_X1 +*I _609_:Z O *D MUX2_X1 +*I _786_:A I *D CLKBUF_X1 *CAP 1 _089_:1 1.3625 *RES 1 _089_:1 _089_:1 0.005 -2 _609_/Z _089_:1 3.645 -3 _786_/A _089_:1 1.815 +2 _609_:Z _089_:1 3.645 +3 _786_:A _089_:1 1.815 *END *D_NET _090_ 8.97 *CONN -*I _618_/Z O *D MUX2_X1 -*I _789_/A I *D CLKBUF_X1 +*I _618_:Z O *D MUX2_X1 +*I _789_:A I *D CLKBUF_X1 *CAP 1 _090_:1 1.85 2 _090_:2 1.05 @@ -3145,14 +3145,14 @@ resp_val O 2 _090_:2 _090_:3 0.005 3 _090_:3 _090_:4 8.4 4 _090_:4 _090_:5 0.005 -5 _618_/Z _090_:5 2.145 -6 _789_/A _090_:1 3.205 +5 _618_:Z _090_:5 2.145 +6 _789_:A _090_:1 3.205 *END *D_NET _091_ 9.945 *CONN -*I _627_/Z O *D MUX2_X1 -*I _792_/A I *D CLKBUF_X1 +*I _627_:Z O *D MUX2_X1 +*I _792_:A I *D CLKBUF_X1 *CAP 1 _091_:1 1.9575 2 _091_:2 1.05 @@ -3166,14 +3166,14 @@ resp_val O 3 _091_:3 _091_:4 4.2 4 _091_:4 _091_:5 0.005 5 _091_:5 _091_:6 4.2 -6 _627_/Z _091_:6 3.665 -7 _792_/A _091_:1 3.635 +6 _627_:Z _091_:6 3.665 +7 _792_:A _091_:1 3.635 *END *D_NET _092_ 9.35 *CONN -*I _686_/Z O *D MUX2_X1 -*I _812_/A I *D CLKBUF_X1 +*I _686_:Z O *D MUX2_X1 +*I _812_:A I *D CLKBUF_X1 *CAP 1 _092_:1 0.26 2 _092_:2 2.1 @@ -3185,14 +3185,14 @@ resp_val O 2 _092_:2 _092_:3 8.4 3 _092_:3 _092_:4 0.005 4 _092_:4 _092_:5 4.2 -5 _686_/Z _092_:5 5.065 -6 _812_/A _092_:1 1.045 +5 _686_:Z _092_:5 5.065 +6 _812_:A _092_:1 1.045 *END *D_NET _093_ 6.69 *CONN -*I _706_/Z O *D MUX2_X1 -*I _832_/A I *D CLKBUF_X1 +*I _706_:Z O *D MUX2_X1 +*I _832_:A I *D CLKBUF_X1 *CAP 1 _093_:1 0.73 2 _093_:2 1.05 @@ -3204,52 +3204,52 @@ resp_val O 2 _093_:2 _093_:3 4.2 3 _093_:3 _093_:4 0.005 4 _093_:5 _093_:4 4.2 -5 _706_/Z _093_:5 2.065 -6 _832_/A _093_:1 2.925 +5 _706_:Z _093_:5 2.065 +6 _832_:A _093_:1 2.925 *END *D_NET _094_ 2.58 *CONN -*I _708_/Z O *D MUX2_X1 -*I _834_/A I *D CLKBUF_X1 +*I _708_:Z O *D MUX2_X1 +*I _834_:A I *D CLKBUF_X1 *CAP 1 _094_:1 1.29 *RES 1 _094_:1 _094_:1 0.005 -2 _708_/Z _094_:1 3.925 -3 _834_/A _094_:1 1.245 +2 _708_:Z _094_:1 3.925 +3 _834_:A _094_:1 1.245 *END *D_NET _095_ 4.14 *CONN -*I _710_/Z O *D MUX2_X1 -*I _836_/A I *D CLKBUF_X1 +*I _710_:Z O *D MUX2_X1 +*I _836_:A I *D CLKBUF_X1 *CAP 1 _095_:1 1.835 2 _095_:2 1.285 *RES 1 _095_:2 _095_:1 4.2 -2 _710_/Z _095_:1 3.145 -3 _836_/A _095_:2 0.945 +2 _710_:Z _095_:1 3.145 +3 _836_:A _095_:2 0.945 *END *D_NET _096_ 4.58 *CONN -*I _712_/Z O *D MUX2_X1 -*I _838_/A I *D CLKBUF_X1 +*I _712_:Z O *D MUX2_X1 +*I _838_:A I *D CLKBUF_X1 *CAP 1 _096_:1 1.68 2 _096_:2 1.66 *RES 1 _096_:2 _096_:1 4.2 -2 _712_/Z _096_:1 2.525 -3 _838_/A _096_:2 2.445 +2 _712_:Z _096_:1 2.525 +3 _838_:A _096_:2 2.445 *END *D_NET _097_ 6.695 *CONN -*I _714_/Z O *D MUX2_X1 -*I _840_/A I *D CLKBUF_X1 +*I _714_:Z O *D MUX2_X1 +*I _840_:A I *D CLKBUF_X1 *CAP 1 _097_:1 0.4825 2 _097_:2 1.05 @@ -3261,14 +3261,14 @@ resp_val O 2 _097_:2 _097_:3 4.2 3 _097_:3 _097_:4 0.005 4 _097_:5 _097_:4 4.2 -5 _714_/Z _097_:5 3.065 -6 _840_/A _097_:1 1.935 +5 _714_:Z _097_:5 3.065 +6 _840_:A _097_:1 1.935 *END *D_NET _098_ 6.52 *CONN -*I _716_/Z O *D MUX2_X1 -*I _842_/A I *D CLKBUF_X1 +*I _716_:Z O *D MUX2_X1 +*I _842_:A I *D CLKBUF_X1 *CAP 1 _098_:1 1.35 2 _098_:2 1.05 @@ -3280,14 +3280,14 @@ resp_val O 2 _098_:2 _098_:3 0.005 3 _098_:3 _098_:4 4.2 4 _098_:4 _098_:5 0.005 -5 _716_/Z _098_:1 1.205 -6 _842_/A _098_:5 3.445 +5 _716_:Z _098_:1 1.205 +6 _842_:A _098_:5 3.445 *END *D_NET _099_ 4.645 *CONN -*I _688_/Z O *D MUX2_X1 -*I _814_/A I *D CLKBUF_X1 +*I _688_:Z O *D MUX2_X1 +*I _814_:A I *D CLKBUF_X1 *CAP 1 _099_:1 0.7925 2 _099_:2 1.05 @@ -3297,14 +3297,14 @@ resp_val O 1 _099_:1 _099_:2 0.005 2 _099_:2 _099_:3 4.2 3 _099_:3 _099_:4 0.005 -4 _688_/Z _099_:4 1.925 -5 _814_/A _099_:1 3.175 +4 _688_:Z _099_:4 1.925 +5 _814_:A _099_:1 3.175 *END *D_NET _100_ 7.12 *CONN -*I _690_/Z O *D MUX2_X1 -*I _816_/A I *D CLKBUF_X1 +*I _690_:Z O *D MUX2_X1 +*I _816_:A I *D CLKBUF_X1 *CAP 1 _100_:1 0.96 2 _100_:2 1.05 @@ -3316,27 +3316,27 @@ resp_val O 2 _100_:2 _100_:3 4.2 3 _100_:3 _100_:4 0.005 4 _100_:5 _100_:4 4.2 -5 _690_/Z _100_:5 2.005 -6 _816_/A _100_:1 3.845 +5 _690_:Z _100_:5 2.005 +6 _816_:A _100_:1 3.845 *END *D_NET _101_ 3.865 *CONN -*I _692_/Z O *D MUX2_X1 -*I _818_/A I *D CLKBUF_X1 +*I _692_:Z O *D MUX2_X1 +*I _818_:A I *D CLKBUF_X1 *CAP 1 _101_:1 1.41 2 _101_:2 1.5725 *RES 1 _101_:1 _101_:2 4.2 -2 _692_/Z _101_:1 1.445 -3 _818_/A _101_:2 2.095 +2 _692_:Z _101_:1 1.445 +3 _818_:A _101_:2 2.095 *END *D_NET _102_ 9.395 *CONN -*I _694_/Z O *D MUX2_X1 -*I _820_/A I *D CLKBUF_X1 +*I _694_:Z O *D MUX2_X1 +*I _820_:A I *D CLKBUF_X1 *CAP 1 _102_:1 1.6675 2 _102_:2 1.05 @@ -3350,65 +3350,65 @@ resp_val O 3 _102_:3 _102_:4 4.2 4 _102_:4 _102_:5 0.005 5 _102_:5 _102_:6 4.2 -6 _694_/Z _102_:6 3.725 -7 _820_/A _102_:1 2.475 +6 _694_:Z _102_:6 3.725 +7 _820_:A _102_:1 2.475 *END *D_NET _103_ 2.595 *CONN -*I _696_/Z O *D MUX2_X1 -*I _822_/A I *D CLKBUF_X1 +*I _696_:Z O *D MUX2_X1 +*I _822_:A I *D CLKBUF_X1 *CAP 1 _103_:1 1.2975 *RES 1 _103_:1 _103_:1 0.005 -2 _696_/Z _103_:1 2.625 -3 _822_/A _103_:1 2.575 +2 _696_:Z _103_:1 2.625 +3 _822_:A _103_:1 2.575 *END *D_NET _104_ 6.145 *CONN -*I _698_/Z O *D MUX2_X1 -*I _824_/A I *D CLKBUF_X1 +*I _698_:Z O *D MUX2_X1 +*I _824_:A I *D CLKBUF_X1 *CAP 1 _104_:1 2.2125 2 _104_:2 2.96 *RES 1 _104_:1 _104_:2 8.4 -2 _698_/Z _104_:2 3.445 -3 _824_/A _104_:1 0.455 +2 _698_:Z _104_:2 3.445 +3 _824_:A _104_:1 0.455 *END *D_NET _105_ 5.53 *CONN -*I _700_/Z O *D MUX2_X1 -*I _826_/A I *D CLKBUF_X1 +*I _700_:Z O *D MUX2_X1 +*I _826_:A I *D CLKBUF_X1 *CAP 1 _105_:1 1.96 2 _105_:2 1.855 *RES 1 _105_:2 _105_:1 4.2 -2 _700_/Z _105_:1 3.645 -3 _826_/A _105_:2 3.225 +2 _700_:Z _105_:1 3.645 +3 _826_:A _105_:2 3.225 *END *D_NET _106_ 3.96 *CONN -*I _702_/Z O *D MUX2_X1 -*I _828_/A I *D CLKBUF_X1 +*I _702_:Z O *D MUX2_X1 +*I _828_:A I *D CLKBUF_X1 *CAP 1 _106_:1 1.325 2 _106_:2 1.705 *RES 1 _106_:1 _106_:2 4.2 -2 _702_/Z _106_:1 1.105 -3 _828_/A _106_:2 2.625 +2 _702_:Z _106_:1 1.105 +3 _828_:A _106_:2 2.625 *END *D_NET _107_ 8.705 *CONN -*I _704_/Z O *D MUX2_X1 -*I _830_/A I *D CLKBUF_X1 +*I _704_:Z O *D MUX2_X1 +*I _830_:A I *D CLKBUF_X1 *CAP 1 _107_:1 0.4825 2 _107_:2 2.1 @@ -3420,30 +3420,30 @@ resp_val O 2 _107_:2 _107_:3 8.4 3 _107_:3 _107_:4 0.005 4 _107_:4 _107_:5 4.2 -5 _704_/Z _107_:5 2.885 -6 _830_/A _107_:1 1.935 +5 _704_:Z _107_:5 2.885 +6 _830_:A _107_:1 1.935 *END *D_NET _108_ 6.115 *CONN -*I _439_/A2 I *D AND3_X1 -*I _719_/Z O *D CLKBUF_X1 +*I _439_:A2 I *D AND3_X1 +*I _719_:Z O *D CLKBUF_X1 *CAP 1 _108_:1 2.32 2 _108_:2 1.7875 *RES 1 _108_:2 _108_:1 4.2 -2 _439_/A2 _108_:2 2.955 -3 _719_/Z _108_:1 5.085 +2 _439_:A2 _108_:2 2.955 +3 _719_:Z _108_:1 5.085 *END *D_NET _109_ 11.76 *CONN -*I _438_/A I *D INV_X2 -*I _531_/A1 I *D AND2_X1 -*I _544_/A2 I *D NAND2_X1 -*I _548_/A1 I *D OR2_X1 -*I _718_/Z O *D CLKBUF_X1 +*I _438_:A I *D INV_X2 +*I _531_:A1 I *D AND2_X1 +*I _544_:A2 I *D NAND2_X1 +*I _548_:A1 I *D OR2_X1 +*I _718_:Z O *D CLKBUF_X1 *CAP 1 _109_:1 1.6975 2 _109_:2 1.05 @@ -3457,20 +3457,20 @@ resp_val O 3 _109_:3 _109_:4 0.005 4 _109_:6 _109_:5 4.2 5 _109_:1 _109_:6 4.2 -6 _438_/A _109_:6 1.165 -7 _531_/A1 _109_:4 2.035 -8 _544_/A2 _109_:4 2.505 -9 _548_/A1 _109_:1 2.595 -10 _718_/Z _109_:5 2.645 +6 _438_:A _109_:6 1.165 +7 _531_:A1 _109_:4 2.035 +8 _544_:A2 _109_:4 2.505 +9 _548_:A1 _109_:1 2.595 +10 _718_:Z _109_:5 2.645 *END *D_NET _110_ 35.005 *CONN -*I _440_/A I *D XOR2_X1 -*I _483_/A I *D INV_X1 -*I _551_/A I *D MUX2_X1 -*I _683_/A I *D MUX2_X1 -*I _753_/Z O *D CLKBUF_X1 +*I _440_:A I *D XOR2_X1 +*I _483_:A I *D INV_X1 +*I _551_:A I *D MUX2_X1 +*I _683_:A I *D MUX2_X1 +*I _753_:Z O *D CLKBUF_X1 *CAP 1 _110_:1 2.4075 2 _110_:2 2.7925 @@ -3492,20 +3492,20 @@ resp_val O 7 _110_:8 _110_:9 4.2 8 _110_:9 _110_:10 0.005 9 _110_:6 _110_:8 4.2 -10 _440_/A _110_:2 2.775 -11 _483_/A _110_:1 1.235 -12 _551_/A _110_:3 2.865 -13 _683_/A _110_:7 1.775 -14 _753_/Z _110_:10 2.585 +10 _440_:A _110_:2 2.775 +11 _483_:A _110_:1 1.235 +12 _551_:A _110_:3 2.865 +13 _683_:A _110_:7 1.775 +14 _753_:Z _110_:10 2.585 *END *D_NET _111_ 18.6 *CONN -*I _501_/A I *D XNOR2_X1 -*I _524_/A I *D INV_X1 -*I _636_/A I *D MUX2_X1 -*I _705_/A I *D MUX2_X1 -*I _733_/Z O *D CLKBUF_X1 +*I _501_:A I *D XNOR2_X1 +*I _524_:A I *D INV_X1 +*I _636_:A I *D MUX2_X1 +*I _705_:A I *D MUX2_X1 +*I _733_:Z O *D CLKBUF_X1 *CAP 1 _111_:1 0.525 2 _111_:2 1.05 @@ -3529,19 +3529,19 @@ resp_val O 8 _111_:9 _111_:10 0.005 9 _111_:9 _111_:11 4.2 10 _111_:11 _111_:6 0.005 -11 _501_/A _111_:10 3.275 -12 _524_/A _111_:6 2.525 -13 _636_/A _111_:1 2.105 -14 _705_/A _111_:5 2.175 -15 _733_/Z _111_:4 1.945 +11 _501_:A _111_:10 3.275 +12 _524_:A _111_:6 2.525 +13 _636_:A _111_:1 2.105 +14 _705_:A _111_:5 2.175 +15 _733_:Z _111_:4 1.945 *END *D_NET _112_ 20.325 *CONN -*I _502_/A I *D XNOR2_X1 -*I _522_/A I *D INV_X1 -*I _707_/A I *D MUX2_X1 -*I _731_/Z O *D CLKBUF_X1 +*I _502_:A I *D XNOR2_X1 +*I _522_:A I *D INV_X1 +*I _707_:A I *D MUX2_X1 +*I _731_:Z O *D CLKBUF_X1 *CAP 1 _112_:1 1.5175 2 _112_:2 1.05 @@ -3563,19 +3563,19 @@ resp_val O 7 _112_:8 _112_:9 4.2 8 _112_:9 _112_:10 0.005 9 _112_:4 _112_:8 12.6 -10 _502_/A _112_:1 1.875 -11 _522_/A _112_:6 2.865 -12 _707_/A _112_:5 2.685 -13 _731_/Z _112_:10 3.845 +10 _502_:A _112_:1 1.875 +11 _522_:A _112_:6 2.865 +12 _707_:A _112_:5 2.685 +13 _731_:Z _112_:10 3.845 *END *D_NET _113_ 25.235 *CONN -*I _512_/A I *D XNOR2_X1 -*I _534_/A I *D INV_X1 -*I _656_/A I *D MUX2_X1 -*I _709_/A I *D MUX2_X1 -*I _729_/Z O *D CLKBUF_X1 +*I _512_:A I *D XNOR2_X1 +*I _534_:A I *D INV_X1 +*I _656_:A I *D MUX2_X1 +*I _709_:A I *D MUX2_X1 +*I _729_:Z O *D CLKBUF_X1 *CAP 1 _113_:1 2.5775 2 _113_:2 1.365 @@ -3599,21 +3599,21 @@ resp_val O 8 _113_:9 _113_:10 4.2 9 _113_:10 _113_:11 0.005 10 _113_:10 _113_:5 4.2 -11 _512_/A _113_:1 1.915 -12 _534_/A _113_:2 1.265 -13 _656_/A _113_:11 3.465 -14 _709_/A _113_:4 3.865 -15 _729_/Z _113_:7 2.185 +11 _512_:A _113_:1 1.915 +12 _534_:A _113_:2 1.265 +13 _656_:A _113_:11 3.465 +14 _709_:A _113_:4 3.865 +15 _729_:Z _113_:7 2.185 *END *D_NET _114_ 30.385 *CONN -*I _510_/A I *D XNOR2_X2 -*I _532_/A I *D INV_X1 -*I _664_/A I *D MUX2_X1 -*I _667_/B1 I *D AOI22_X1 -*I _711_/A I *D MUX2_X1 -*I _727_/Z O *D BUF_X1 +*I _510_:A I *D XNOR2_X2 +*I _532_:A I *D INV_X1 +*I _664_:A I *D MUX2_X1 +*I _667_:B1 I *D AOI22_X1 +*I _711_:A I *D MUX2_X1 +*I _727_:Z O *D BUF_X1 *CAP 1 _114_:1 2.685 2 _114_:2 3.15 @@ -3637,21 +3637,21 @@ resp_val O 8 _114_:8 _114_:9 0.005 9 _114_:10 _114_:11 12.6 10 _114_:4 _114_:10 4.2 -11 _510_/A _114_:10 0.885 -12 _532_/A _114_:11 2.425 -13 _664_/A _114_:5 3.395 -14 _667_/B1 _114_:7 2.055 -15 _711_/A _114_:9 3.495 -16 _727_/Z _114_:1 2.345 +11 _510_:A _114_:10 0.885 +12 _532_:A _114_:11 2.425 +13 _664_:A _114_:5 3.395 +14 _667_:B1 _114_:7 2.055 +15 _711_:A _114_:9 3.495 +16 _727_:Z _114_:1 2.345 *END *D_NET _115_ 21.71 *CONN -*I _507_/A I *D XNOR2_X1 -*I _528_/A I *D INV_X1 -*I _674_/A I *D MUX2_X1 -*I _713_/A I *D MUX2_X1 -*I _725_/Z O *D CLKBUF_X1 +*I _507_:A I *D XNOR2_X1 +*I _528_:A I *D INV_X1 +*I _674_:A I *D MUX2_X1 +*I _713_:A I *D MUX2_X1 +*I _725_:Z O *D CLKBUF_X1 *CAP 1 _115_:1 4.6125 2 _115_:2 1.49 @@ -3671,19 +3671,19 @@ resp_val O 6 _115_:8 _115_:1 12.6 7 _115_:6 _115_:9 8.4 8 _115_:9 _115_:8 0.005 -9 _507_/A _115_:1 1.655 -10 _528_/A _115_:2 1.765 -11 _674_/A _115_:3 2.555 -12 _713_/A _115_:7 1.885 -13 _725_/Z _115_:8 1.985 +9 _507_:A _115_:1 1.655 +10 _528_:A _115_:2 1.765 +11 _674_:A _115_:3 2.555 +12 _713_:A _115_:7 1.885 +13 _725_:Z _115_:8 1.985 *END *D_NET _116_ 20.69 *CONN -*I _468_/A I *D INV_X1 -*I _508_/A I *D XNOR2_X2 -*I _715_/A I *D MUX2_X1 -*I _723_/Z O *D CLKBUF_X1 +*I _468_:A I *D INV_X1 +*I _508_:A I *D XNOR2_X2 +*I _715_:A I *D MUX2_X1 +*I _723_:Z O *D CLKBUF_X1 *CAP 1 _116_:1 4.815 2 _116_:2 4.53 @@ -3699,20 +3699,20 @@ resp_val O 4 _116_:5 _116_:6 0.005 5 _116_:2 _116_:7 0.005 6 _116_:7 _116_:4 8.4 -7 _468_/A _116_:3 2.405 -8 _508_/A _116_:1 2.465 -9 _715_/A _116_:2 1.325 -10 _723_/Z _116_:6 1.605 +7 _468_:A _116_:3 2.405 +8 _508_:A _116_:1 2.465 +9 _715_:A _116_:2 1.325 +10 _723_:Z _116_:6 1.605 *END *D_NET _117_ 25.13 *CONN -*I _481_/A2 I *D AND2_X1 -*I _482_/A2 I *D NOR2_X1 -*I _540_/A I *D XNOR2_X2 -*I _560_/A I *D MUX2_X1 -*I _687_/A I *D MUX2_X1 -*I _751_/Z O *D BUF_X1 +*I _481_:A2 I *D AND2_X1 +*I _482_:A2 I *D NOR2_X1 +*I _540_:A I *D XNOR2_X2 +*I _560_:A I *D MUX2_X1 +*I _687_:A I *D MUX2_X1 +*I _751_:Z O *D BUF_X1 *CAP 1 _117_:1 1.05 2 _117_:2 4.2 @@ -3738,22 +3738,22 @@ resp_val O 9 _117_:11 _117_:5 0.005 10 _117_:12 _117_:5 8.4 11 _117_:1 _117_:12 4.2 -12 _481_/A2 _117_:4 2.055 -13 _482_/A2 _117_:4 2.075 -14 _540_/A _117_:12 2.465 -15 _560_/A _117_:6 1.735 -16 _687_/A _117_:7 2.155 -17 _751_/Z _117_:9 2.005 +12 _481_:A2 _117_:4 2.055 +13 _482_:A2 _117_:4 2.075 +14 _540_:A _117_:12 2.465 +15 _560_:A _117_:6 1.735 +16 _687_:A _117_:7 2.155 +17 _751_:Z _117_:9 2.005 *END *D_NET _118_ 35.71 *CONN -*I _474_/A I *D XNOR2_X1 -*I _498_/A I *D AOI211_X1 -*I _566_/A I *D MUX2_X1 -*I _570_/A2 I *D AND2_X1 -*I _689_/A I *D MUX2_X1 -*I _749_/Z O *D CLKBUF_X1 +*I _474_:A I *D XNOR2_X1 +*I _498_:A I *D AOI211_X1 +*I _566_:A I *D MUX2_X1 +*I _570_:A2 I *D AND2_X1 +*I _689_:A I *D MUX2_X1 +*I _749_:Z O *D CLKBUF_X1 *CAP 1 _118_:1 1.5275 2 _118_:2 1.05 @@ -3787,23 +3787,23 @@ resp_val O 13 _118_:15 _118_:2 0.005 14 _118_:15 _118_:16 4.2 15 _118_:16 _118_:12 0.005 -16 _474_/A _118_:1 1.915 -17 _498_/A _118_:3 2.255 -18 _566_/A _118_:5 2.405 -19 _570_/A2 _118_:11 3.885 -20 _689_/A _118_:13 2.245 -21 _749_/Z _118_:14 4.145 +16 _474_:A _118_:1 1.915 +17 _498_:A _118_:3 2.255 +18 _566_:A _118_:5 2.405 +19 _570_:A2 _118_:11 3.885 +20 _689_:A _118_:13 2.245 +21 _749_:Z _118_:14 4.145 *END *D_NET _119_ 37.99 *CONN -*I _473_/A I *D XNOR2_X1 -*I _497_/A2 I *D NOR2_X1 -*I _498_/C1 I *D AOI211_X1 -*I _575_/A I *D MUX2_X1 -*I _578_/B1 I *D AOI21_X1 -*I _691_/A I *D MUX2_X1 -*I _747_/Z O *D BUF_X1 +*I _473_:A I *D XNOR2_X1 +*I _497_:A2 I *D NOR2_X1 +*I _498_:C1 I *D AOI211_X1 +*I _575_:A I *D MUX2_X1 +*I _578_:B1 I *D AOI21_X1 +*I _691_:A I *D MUX2_X1 +*I _747_:Z O *D BUF_X1 *CAP 1 _119_:1 5.25 2 _119_:2 2.7125 @@ -3839,22 +3839,22 @@ resp_val O 14 _119_:8 _119_:1 12.6 15 _119_:17 _119_:12 4.2 16 _119_:3 _119_:8 4.2 -17 _473_/A _119_:9 3.755 -18 _497_/A2 _119_:4 2.135 -19 _498_/C1 _119_:5 1.545 -20 _575_/A _119_:11 3.355 -21 _578_/B1 _119_:3 1.505 -22 _691_/A _119_:2 2.455 -23 _747_/Z _119_:15 2.465 +17 _473_:A _119_:9 3.755 +18 _497_:A2 _119_:4 2.135 +19 _498_:C1 _119_:5 1.545 +20 _575_:A _119_:11 3.355 +21 _578_:B1 _119_:3 1.505 +22 _691_:A _119_:2 2.455 +23 _747_:Z _119_:15 2.465 *END *D_NET _120_ 28.92 *CONN -*I _477_/A I *D XNOR2_X1 -*I _486_/A I *D INV_X1 -*I _584_/A I *D MUX2_X1 -*I _693_/A I *D MUX2_X1 -*I _745_/Z O *D CLKBUF_X1 +*I _477_:A I *D XNOR2_X1 +*I _486_:A I *D INV_X1 +*I _584_:A I *D MUX2_X1 +*I _693_:A I *D MUX2_X1 +*I _745_:Z O *D CLKBUF_X1 *CAP 1 _120_:1 4.435 2 _120_:2 4.2 @@ -3876,20 +3876,20 @@ resp_val O 7 _120_:8 _120_:9 0.005 8 _120_:8 _120_:10 8.4 9 _120_:10 _120_:2 0.005 -10 _477_/A _120_:3 1.615 -11 _486_/A _120_:9 1.795 -12 _584_/A _120_:4 3.625 -13 _693_/A _120_:5 3.685 -14 _745_/Z _120_:1 5.145 +10 _477_:A _120_:3 1.615 +11 _486_:A _120_:9 1.795 +12 _584_:A _120_:4 3.625 +13 _693_:A _120_:5 3.685 +14 _745_:Z _120_:1 5.145 *END *D_NET _121_ 23.025 *CONN -*I _476_/A I *D XNOR2_X2 -*I _488_/A I *D INV_X1 -*I _592_/A I *D MUX2_X1 -*I _695_/A I *D MUX2_X1 -*I _743_/Z O *D CLKBUF_X1 +*I _476_:A I *D XNOR2_X2 +*I _488_:A I *D INV_X1 +*I _592_:A I *D MUX2_X1 +*I _695_:A I *D MUX2_X1 +*I _743_:Z O *D CLKBUF_X1 *CAP 1 _121_:1 2.66 2 _121_:2 1.7675 @@ -3909,20 +3909,20 @@ resp_val O 6 _121_:4 _121_:8 0.005 7 _121_:8 _121_:9 8.4 8 _121_:9 _121_:6 0.005 -9 _476_/A _121_:2 2.875 -10 _488_/A _121_:1 2.245 -11 _592_/A _121_:3 1.135 -12 _695_/A _121_:5 1.555 -13 _743_/Z _121_:7 0.465 +9 _476_:A _121_:2 2.875 +10 _488_:A _121_:1 2.245 +11 _592_:A _121_:3 1.135 +12 _695_:A _121_:5 1.555 +13 _743_:Z _121_:7 0.465 *END *D_NET _122_ 23.18 *CONN -*I _471_/A I *D XNOR2_X1 -*I _494_/A I *D INV_X1 -*I _600_/A I *D MUX2_X1 -*I _697_/A I *D MUX2_X1 -*I _741_/Z O *D CLKBUF_X1 +*I _471_:A I *D XNOR2_X1 +*I _494_:A I *D INV_X1 +*I _600_:A I *D MUX2_X1 +*I _697_:A I *D MUX2_X1 +*I _741_:Z O *D CLKBUF_X1 *CAP 1 _122_:1 1.385 2 _122_:2 1.4725 @@ -3942,21 +3942,21 @@ resp_val O 6 _122_:1 _122_:8 0.005 7 _122_:8 _122_:9 12.6 8 _122_:9 _122_:4 0.005 -9 _471_/A _122_:4 2.195 -10 _494_/A _122_:2 1.695 -11 _600_/A _122_:3 2.545 -12 _697_/A _122_:1 1.345 -13 _741_/Z _122_:7 0.805 +9 _471_:A _122_:4 2.195 +10 _494_:A _122_:2 1.695 +11 _600_:A _122_:3 2.545 +12 _697_:A _122_:1 1.345 +13 _741_:Z _122_:7 0.805 *END *D_NET _123_ 26.89 *CONN -*I _470_/A I *D XNOR2_X2 -*I _492_/A2 I *D NOR2_X1 -*I _609_/A I *D MUX2_X1 -*I _613_/B1 I *D AOI221_X1 -*I _699_/A I *D MUX2_X1 -*I _739_/Z O *D BUF_X1 +*I _470_:A I *D XNOR2_X2 +*I _492_:A2 I *D NOR2_X1 +*I _609_:A I *D MUX2_X1 +*I _613_:B1 I *D AOI221_X1 +*I _699_:A I *D MUX2_X1 +*I _739_:Z O *D BUF_X1 *CAP 1 _123_:1 1.05 2 _123_:2 2.1 @@ -3982,21 +3982,21 @@ resp_val O 9 _123_:10 _123_:11 4.2 10 _123_:6 _123_:12 0.005 11 _123_:12 _123_:2 4.2 -12 _470_/A _123_:4 2.565 -13 _492_/A2 _123_:6 0.785 -14 _609_/A _123_:7 1.165 -15 _613_/B1 _123_:5 3.595 -16 _699_/A _123_:10 2.915 -17 _739_/Z _123_:11 0.785 +12 _470_:A _123_:4 2.565 +13 _492_:A2 _123_:6 0.785 +14 _609_:A _123_:7 1.165 +15 _613_:B1 _123_:5 3.595 +16 _699_:A _123_:10 2.915 +17 _739_:Z _123_:11 0.785 *END *D_NET _124_ 18.53 *CONN -*I _505_/A I *D XNOR2_X1 -*I _517_/A I *D INV_X1 -*I _618_/A I *D MUX2_X1 -*I _701_/A I *D MUX2_X1 -*I _737_/Z O *D CLKBUF_X1 +*I _505_:A I *D XNOR2_X1 +*I _517_:A I *D INV_X1 +*I _618_:A I *D MUX2_X1 +*I _701_:A I *D MUX2_X1 +*I _737_:Z O *D CLKBUF_X1 *CAP 1 _124_:1 1.61 2 _124_:2 1.6275 @@ -4014,20 +4014,20 @@ resp_val O 5 _124_:6 _124_:7 0.005 6 _124_:6 _124_:8 8.4 7 _124_:8 _124_:2 0.005 -8 _505_/A _124_:2 2.315 -9 _517_/A _124_:1 2.245 -10 _618_/A _124_:7 2.975 -11 _701_/A _124_:4 1.045 -12 _737_/Z _124_:7 3.305 +8 _505_:A _124_:2 2.315 +9 _517_:A _124_:1 2.245 +10 _618_:A _124_:7 2.975 +11 _701_:A _124_:4 1.045 +12 _737_:Z _124_:7 3.305 *END *D_NET _125_ 15.92 *CONN -*I _504_/A I *D XNOR2_X2 -*I _519_/A I *D INV_X1 -*I _627_/A I *D MUX2_X1 -*I _703_/A I *D MUX2_X1 -*I _735_/Z O *D CLKBUF_X1 +*I _504_:A I *D XNOR2_X2 +*I _519_:A I *D INV_X1 +*I _627_:A I *D MUX2_X1 +*I _703_:A I *D MUX2_X1 +*I _735_:Z O *D CLKBUF_X1 *CAP 1 _125_:1 1.4125 2 _125_:2 1.05 @@ -4047,21 +4047,21 @@ resp_val O 6 _125_:8 _125_:3 4.2 7 _125_:7 _125_:9 4.2 8 _125_:9 _125_:4 0.005 -9 _504_/A _125_:4 2.485 -10 _519_/A _125_:3 2.575 -11 _627_/A _125_:1 1.455 -12 _703_/A _125_:5 3.205 -13 _735_/Z _125_:8 1.145 +9 _504_:A _125_:4 2.485 +10 _519_:A _125_:3 2.575 +11 _627_:A _125_:1 1.455 +12 _703_:A _125_:5 3.205 +13 _735_:Z _125_:8 1.145 *END *D_NET _126_ 31.635 *CONN -*I _440_/B I *D XOR2_X1 -*I _444_/A2 I *D NOR2_X1 -*I _484_/A3 I *D NOR3_X1 -*I _556_/A2 I *D NAND2_X1 -*I _686_/A I *D MUX2_X1 -*I _754_/Z O *D BUF_X1 +*I _440_:B I *D XOR2_X1 +*I _444_:A2 I *D NOR2_X1 +*I _484_:A3 I *D NOR3_X1 +*I _556_:A2 I *D NAND2_X1 +*I _686_:A I *D MUX2_X1 +*I _754_:Z O *D BUF_X1 *CAP 1 _126_:1 4.805 2 _126_:2 2.1375 @@ -4075,22 +4075,22 @@ resp_val O 3 _126_:4 _126_:5 33.6 4 _126_:5 _126_:6 0.005 5 _126_:1 _126_:3 12.6 -6 _440_/B _126_:3 1.775 -7 _444_/A2 _126_:2 3.075 -8 _484_/A3 _126_:2 1.285 -9 _556_/A2 _126_:1 2.425 -10 _686_/A _126_:6 2.155 -11 _754_/Z _126_:6 2.185 +6 _440_:B _126_:3 1.775 +7 _444_:A2 _126_:2 3.075 +8 _484_:A3 _126_:2 1.285 +9 _556_:A2 _126_:1 2.425 +10 _686_:A _126_:6 2.155 +11 _754_:Z _126_:6 2.185 *END *D_NET _127_ 16.995 *CONN -*I _446_/A2 I *D NOR4_X1 -*I _501_/B I *D XNOR2_X1 -*I _525_/B2 I *D AOI22_X1 -*I _640_/A2 I *D NOR2_X1 -*I _706_/A I *D MUX2_X1 -*I _734_/Z O *D BUF_X1 +*I _446_:A2 I *D NOR4_X1 +*I _501_:B I *D XNOR2_X1 +*I _525_:B2 I *D AOI22_X1 +*I _640_:A2 I *D NOR2_X1 +*I _706_:A I *D MUX2_X1 +*I _734_:Z O *D BUF_X1 *CAP 1 _127_:1 1.2 2 _127_:2 1.05 @@ -4110,22 +4110,22 @@ resp_val O 6 _127_:6 _127_:7 4.2 7 _127_:9 _127_:8 4.2 8 _127_:1 _127_:9 4.2 -9 _446_/A2 _127_:8 0.765 -10 _501_/B _127_:9 3.785 -11 _525_/B2 _127_:7 3.555 -12 _640_/A2 _127_:7 1.365 -13 _706_/A _127_:4 2.945 -14 _734_/Z _127_:1 0.605 +9 _446_:A2 _127_:8 0.765 +10 _501_:B _127_:9 3.785 +11 _525_:B2 _127_:7 3.555 +12 _640_:A2 _127_:7 1.365 +13 _706_:A _127_:4 2.945 +14 _734_:Z _127_:1 0.605 *END *D_NET _128_ 27.88 *CONN -*I _446_/A1 I *D NOR4_X1 -*I _502_/B I *D XNOR2_X1 -*I _523_/A2 I *D NOR2_X1 -*I _525_/A2 I *D AOI22_X1 -*I _708_/A I *D MUX2_X1 -*I _732_/Z O *D BUF_X1 +*I _446_:A1 I *D NOR4_X1 +*I _502_:B I *D XNOR2_X1 +*I _523_:A2 I *D NOR2_X1 +*I _525_:A2 I *D AOI22_X1 +*I _708_:A I *D MUX2_X1 +*I _732_:Z O *D BUF_X1 *CAP 1 _128_:1 0.6325 2 _128_:2 4.2 @@ -4157,22 +4157,22 @@ resp_val O 12 _128_:13 _128_:14 0.005 13 _128_:14 _128_:15 4.2 14 _128_:3 _128_:7 8.4 -15 _446_/A1 _128_:10 1.295 -16 _502_/B _128_:6 2.385 -17 _523_/A2 _128_:5 1.225 -18 _525_/A2 _128_:1 2.535 -19 _708_/A _128_:9 0.885 -20 _732_/Z _128_:15 1.265 +15 _446_:A1 _128_:10 1.295 +16 _502_:B _128_:6 2.385 +17 _523_:A2 _128_:5 1.225 +18 _525_:A2 _128_:1 2.535 +19 _708_:A _128_:9 0.885 +20 _732_:Z _128_:15 1.265 *END *D_NET _129_ 27.33 *CONN -*I _447_/A4 I *D NOR4_X1 -*I _512_/B I *D XNOR2_X1 -*I _535_/B2 I *D AOI22_X1 -*I _658_/A2 I *D NOR2_X1 -*I _710_/A I *D MUX2_X1 -*I _730_/Z O *D BUF_X1 +*I _447_:A4 I *D NOR4_X1 +*I _512_:B I *D XNOR2_X1 +*I _535_:B2 I *D AOI22_X1 +*I _658_:A2 I *D NOR2_X1 +*I _710_:A I *D MUX2_X1 +*I _730_:Z O *D BUF_X1 *CAP 1 _129_:1 2.1 2 _129_:2 2.97 @@ -4200,22 +4200,22 @@ resp_val O 10 _129_:11 _129_:7 0.005 11 _129_:11 _129_:12 8.4 12 _129_:12 _129_:13 0.005 -13 _447_/A4 _129_:2 3.485 -14 _512_/B _129_:10 2.585 -15 _535_/B2 _129_:5 0.885 -16 _658_/A2 _129_:6 3.075 -17 _710_/A _129_:8 1.975 -18 _730_/Z _129_:13 0.685 +13 _447_:A4 _129_:2 3.485 +14 _512_:B _129_:10 2.585 +15 _535_:B2 _129_:5 0.885 +16 _658_:A2 _129_:6 3.075 +17 _710_:A _129_:8 1.975 +18 _730_:Z _129_:13 0.685 *END *D_NET _130_ 32.37 *CONN -*I _447_/A3 I *D NOR4_X1 -*I _510_/B I *D XNOR2_X2 -*I _533_/A2 I *D NOR2_X1 -*I _535_/A2 I *D AOI22_X1 -*I _712_/A I *D MUX2_X1 -*I _728_/Z O *D CLKBUF_X2 +*I _447_:A3 I *D NOR4_X1 +*I _510_:B I *D XNOR2_X2 +*I _533_:A2 I *D NOR2_X1 +*I _535_:A2 I *D AOI22_X1 +*I _712_:A I *D MUX2_X1 +*I _728_:Z O *D CLKBUF_X2 *CAP 1 _130_:1 2.1 2 _130_:2 3.065 @@ -4243,22 +4243,22 @@ resp_val O 10 _130_:11 _130_:12 0.005 11 _130_:9 _130_:5 16.8 12 _130_:13 _130_:12 4.2 -13 _447_/A3 _130_:2 3.865 -14 _510_/B _130_:9 2.035 -15 _533_/A2 _130_:8 3.155 -16 _535_/A2 _130_:5 2.015 -17 _712_/A _130_:12 0.885 -18 _728_/Z _130_:13 2.415 +13 _447_:A3 _130_:2 3.865 +14 _510_:B _130_:9 2.035 +15 _533_:A2 _130_:8 3.155 +16 _535_:A2 _130_:5 2.015 +17 _712_:A _130_:12 0.885 +18 _728_:Z _130_:13 2.415 *END *D_NET _131_ 27.085 *CONN -*I _447_/A2 I *D NOR4_X1 -*I _507_/B I *D XNOR2_X1 -*I _529_/A3 I *D NAND3_X1 -*I _675_/A2 I *D NOR2_X1 -*I _714_/A I *D MUX2_X1 -*I _726_/Z O *D BUF_X1 +*I _447_:A2 I *D NOR4_X1 +*I _507_:B I *D XNOR2_X1 +*I _529_:A3 I *D NAND3_X1 +*I _675_:A2 I *D NOR2_X1 +*I _714_:A I *D MUX2_X1 +*I _726_:Z O *D BUF_X1 *CAP 1 _131_:1 1.83 2 _131_:2 2.1 @@ -4292,21 +4292,21 @@ resp_val O 13 _131_:10 _131_:15 4.2 14 _131_:15 _131_:16 0.005 15 _131_:16 _131_:12 4.2 -16 _447_/A2 _131_:4 4.165 -17 _507_/B _131_:10 2.325 -18 _529_/A3 _131_:1 3.125 -19 _675_/A2 _131_:11 1.155 -20 _714_/A _131_:5 2.425 -21 _726_/Z _131_:6 3.205 +16 _447_:A2 _131_:4 4.165 +17 _507_:B _131_:10 2.325 +18 _529_:A3 _131_:1 3.125 +19 _675_:A2 _131_:11 1.155 +20 _714_:A _131_:5 2.425 +21 _726_:Z _131_:6 3.205 *END *D_NET _132_ 22.775 *CONN -*I _447_/A1 I *D NOR4_X1 -*I _469_/A2 I *D NAND2_X1 -*I _508_/B I *D XNOR2_X2 -*I _716_/A I *D MUX2_X1 -*I _724_/Z O *D BUF_X1 +*I _447_:A1 I *D NOR4_X1 +*I _469_:A2 I *D NAND2_X1 +*I _508_:B I *D XNOR2_X2 +*I _716_:A I *D MUX2_X1 +*I _724_:Z O *D BUF_X1 *CAP 1 _132_:1 3.1025 2 _132_:2 1.9275 @@ -4328,20 +4328,20 @@ resp_val O 7 _132_:9 _132_:10 0.005 8 _132_:10 _132_:6 4.2 9 _132_:5 _132_:3 8.4 -10 _447_/A1 _132_:2 3.515 -11 _469_/A2 _132_:4 3.835 -12 _508_/B _132_:1 4.015 -13 _716_/A _132_:3 3.805 -14 _724_/Z _132_:8 1.005 +10 _447_:A1 _132_:2 3.515 +11 _469_:A2 _132_:4 3.835 +12 _508_:B _132_:1 4.015 +13 _716_:A _132_:3 3.805 +14 _724_:Z _132_:8 1.005 *END *D_NET _133_ 21.755 *CONN -*I _444_/A1 I *D NOR2_X1 -*I _480_/A I *D INV_X1 -*I _540_/B I *D XNOR2_X2 -*I _688_/A I *D MUX2_X1 -*I _752_/Z O *D BUF_X1 +*I _444_:A1 I *D NOR2_X1 +*I _480_:A I *D INV_X1 +*I _540_:B I *D XNOR2_X2 +*I _688_:A I *D MUX2_X1 +*I _752_:Z O *D BUF_X1 *CAP 1 _133_:1 1.0025 2 _133_:2 3.15 @@ -4363,19 +4363,19 @@ resp_val O 7 _133_:9 _133_:8 4.2 8 _133_:9 _133_:10 0.005 9 _133_:10 _133_:7 4.2 -10 _444_/A1 _133_:4 3.725 -11 _480_/A _133_:5 3.005 -12 _540_/B _133_:1 4.015 -13 _688_/A _133_:9 2.725 -14 _752_/Z _133_:8 4.865 +10 _444_:A1 _133_:4 3.725 +11 _480_:A _133_:5 3.005 +12 _540_:B _133_:1 4.015 +13 _688_:A _133_:9 2.725 +14 _752_:Z _133_:8 4.865 *END *D_NET _134_ 15.01 *CONN -*I _443_/A I *D INV_X1 -*I _474_/B I *D XNOR2_X1 -*I _690_/A I *D MUX2_X1 -*I _750_/Z O *D CLKBUF_X1 +*I _443_:A I *D INV_X1 +*I _474_:B I *D XNOR2_X1 +*I _690_:A I *D MUX2_X1 +*I _750_:Z O *D CLKBUF_X1 *CAP 1 _134_:1 2.7225 2 _134_:2 3.15 @@ -4391,18 +4391,18 @@ resp_val O 4 _134_:5 _134_:2 0.005 5 _134_:6 _134_:3 4.2 6 _134_:2 _134_:7 4.2 -7 _443_/A _134_:1 2.495 -8 _474_/B _134_:6 2.425 -9 _690_/A _134_:7 3.195 -10 _750_/Z _134_:3 0.925 +7 _443_:A _134_:1 2.495 +8 _474_:B _134_:6 2.425 +9 _690_:A _134_:7 3.195 +10 _750_:Z _134_:3 0.925 *END *D_NET _135_ 18.43 *CONN -*I _442_/A I *D INV_X1 -*I _473_/B I *D XNOR2_X1 -*I _692_/A I *D MUX2_X1 -*I _748_/Z O *D CLKBUF_X1 +*I _442_:A I *D INV_X1 +*I _473_:B I *D XNOR2_X1 +*I _692_:A I *D MUX2_X1 +*I _748_:Z O *D CLKBUF_X1 *CAP 1 _135_:1 2.1 2 _135_:2 2.1 @@ -4422,20 +4422,20 @@ resp_val O 6 _135_:6 _135_:8 0.005 7 _135_:8 _135_:2 4.2 8 _135_:1 _135_:9 4.2 -9 _442_/A _135_:4 3.925 -10 _473_/B _135_:5 3.145 -11 _692_/A _135_:7 1.965 -12 _748_/Z _135_:9 2.645 +9 _442_:A _135_:4 3.925 +10 _473_:B _135_:5 3.145 +11 _692_:A _135_:7 1.965 +12 _748_:Z _135_:9 2.645 *END *D_NET _136_ 29.505 *CONN -*I _441_/A4 I *D NOR4_X1 -*I _477_/B I *D XNOR2_X1 -*I _487_/A3 I *D AND3_X1 -*I _587_/A2 I *D NOR2_X1 -*I _694_/A I *D MUX2_X1 -*I _746_/Z O *D CLKBUF_X1 +*I _441_:A4 I *D NOR4_X1 +*I _477_:B I *D XNOR2_X1 +*I _487_:A3 I *D AND3_X1 +*I _587_:A2 I *D NOR2_X1 +*I _694_:A I *D MUX2_X1 +*I _746_:Z O *D CLKBUF_X1 *CAP 1 _136_:1 1.0975 2 _136_:2 2.1 @@ -4467,22 +4467,22 @@ resp_val O 12 _136_:13 _136_:14 4.2 13 _136_:14 _136_:15 0.005 14 _136_:11 _136_:2 4.2 -15 _441_/A4 _136_:8 3.315 -16 _477_/B _136_:6 2.025 -17 _487_/A3 _136_:1 1.515 -18 _587_/A2 _136_:1 2.885 -19 _694_/A _136_:5 1.395 -20 _746_/Z _136_:15 1.705 +15 _441_:A4 _136_:8 3.315 +16 _477_:B _136_:6 2.025 +17 _487_:A3 _136_:1 1.515 +18 _587_:A2 _136_:1 2.885 +19 _694_:A _136_:5 1.395 +20 _746_:Z _136_:15 1.705 *END *D_NET _137_ 25.865 *CONN -*I _441_/A3 I *D NOR4_X1 -*I _476_/B I *D XNOR2_X2 -*I _489_/A2 I *D AND2_X1 -*I _595_/B2 I *D OAI21_X1 -*I _696_/A I *D MUX2_X1 -*I _744_/Z O *D BUF_X1 +*I _441_:A3 I *D NOR4_X1 +*I _476_:B I *D XNOR2_X2 +*I _489_:A2 I *D AND2_X1 +*I _595_:B2 I *D OAI21_X1 +*I _696_:A I *D MUX2_X1 +*I _744_:Z O *D BUF_X1 *CAP 1 _137_:1 0.9225 2 _137_:2 2.1 @@ -4508,23 +4508,23 @@ resp_val O 9 _137_:10 _137_:11 0.005 10 _137_:11 _137_:12 8.4 11 _137_:3 _137_:6 4.2 -12 _441_/A3 _137_:1 3.695 -13 _476_/B _137_:9 2.495 -14 _489_/A2 _137_:4 3.655 -15 _595_/B2 _137_:4 2.605 -16 _696_/A _137_:8 2.185 -17 _744_/Z _137_:12 3.525 +12 _441_:A3 _137_:1 3.695 +13 _476_:B _137_:9 2.495 +14 _489_:A2 _137_:4 3.655 +15 _595_:B2 _137_:4 2.605 +16 _696_:A _137_:8 2.185 +17 _744_:Z _137_:12 3.525 *END *D_NET _138_ 34.405 *CONN -*I _441_/A2 I *D NOR4_X1 -*I _471_/B I *D XNOR2_X1 -*I _495_/A3 I *D NAND3_X1 -*I _602_/A2 I *D AND2_X1 -*I _603_/A2 I *D NOR2_X1 -*I _698_/A I *D MUX2_X1 -*I _742_/Z O *D BUF_X1 +*I _441_:A2 I *D NOR4_X1 +*I _471_:B I *D XNOR2_X1 +*I _495_:A3 I *D NAND3_X1 +*I _602_:A2 I *D AND2_X1 +*I _603_:A2 I *D NOR2_X1 +*I _698_:A I *D MUX2_X1 +*I _742_:Z O *D BUF_X1 *CAP 1 _138_:1 3.15 2 _138_:2 4.2 @@ -4550,22 +4550,22 @@ resp_val O 9 _138_:11 _138_:12 0.005 10 _138_:12 _138_:2 8.4 11 _138_:9 _138_:11 4.2 -12 _441_/A2 _138_:4 3.635 -13 _471_/B _138_:5 1.025 -14 _495_/A3 _138_:11 1.365 -15 _602_/A2 _138_:9 3.345 -16 _603_/A2 _138_:6 1.995 -17 _698_/A _138_:10 3.935 -18 _742_/Z _138_:5 3.145 +12 _441_:A2 _138_:4 3.635 +13 _471_:B _138_:5 1.025 +14 _495_:A3 _138_:11 1.365 +15 _602_:A2 _138_:9 3.345 +16 _603_:A2 _138_:6 1.995 +17 _698_:A _138_:10 3.935 +18 _742_:Z _138_:5 3.145 *END *D_NET _139_ 22.73 *CONN -*I _441_/A1 I *D NOR4_X1 -*I _470_/B I *D XNOR2_X2 -*I _491_/A I *D INV_X1 -*I _700_/A I *D MUX2_X1 -*I _740_/Z O *D BUF_X1 +*I _441_:A1 I *D NOR4_X1 +*I _470_:B I *D XNOR2_X2 +*I _491_:A I *D INV_X1 +*I _700_:A I *D MUX2_X1 +*I _740_:Z O *D BUF_X1 *CAP 1 _139_:1 2.845 2 _139_:2 4.2 @@ -4589,21 +4589,21 @@ resp_val O 8 _139_:9 _139_:10 4.2 9 _139_:10 _139_:11 0.005 10 _139_:7 _139_:9 4.2 -11 _441_/A1 _139_:1 2.985 -12 _470_/B _139_:3 3.715 -13 _491_/A _139_:5 2.255 -14 _700_/A _139_:8 0.725 -15 _740_/Z _139_:11 2.205 +11 _441_:A1 _139_:1 2.985 +12 _470_:B _139_:3 3.715 +13 _491_:A _139_:5 2.255 +14 _700_:A _139_:8 0.725 +15 _740_:Z _139_:11 2.205 *END *D_NET _140_ 35.15 *CONN -*I _446_/A4 I *D NOR4_X1 -*I _505_/B I *D XNOR2_X1 -*I _518_/A3 I *D AND3_X1 -*I _622_/A2 I *D NOR2_X1 -*I _702_/A I *D MUX2_X1 -*I _738_/Z O *D CLKBUF_X1 +*I _446_:A4 I *D NOR4_X1 +*I _505_:B I *D XNOR2_X1 +*I _518_:A3 I *D AND3_X1 +*I _622_:A2 I *D NOR2_X1 +*I _702_:A I *D MUX2_X1 +*I _738_:Z O *D CLKBUF_X1 *CAP 1 _140_:1 3.62 2 _140_:2 2.1 @@ -4631,22 +4631,22 @@ resp_val O 10 _140_:11 _140_:12 12.6 11 _140_:12 _140_:13 0.005 12 _140_:6 _140_:13 8.4 -13 _446_/A4 _140_:5 1.525 -14 _505_/B _140_:13 1.745 -15 _518_/A3 _140_:1 1.885 -16 _622_/A2 _140_:6 2.875 -17 _702_/A _140_:9 1.915 -18 _738_/Z _140_:8 1.585 +13 _446_:A4 _140_:5 1.525 +14 _505_:B _140_:13 1.745 +15 _518_:A3 _140_:1 1.885 +16 _622_:A2 _140_:6 2.875 +17 _702_:A _140_:9 1.915 +18 _738_:Z _140_:8 1.585 *END *D_NET _141_ 25.13 *CONN -*I _446_/A3 I *D NOR4_X1 -*I _504_/B I *D XNOR2_X2 -*I _520_/A2 I *D AND2_X1 -*I _629_/A2 I *D NOR2_X1 -*I _704_/A I *D MUX2_X1 -*I _736_/Z O *D BUF_X1 +*I _446_:A3 I *D NOR4_X1 +*I _504_:B I *D XNOR2_X2 +*I _520_:A2 I *D AND2_X1 +*I _629_:A2 I *D NOR2_X1 +*I _704_:A I *D MUX2_X1 +*I _736_:Z O *D BUF_X1 *CAP 1 _141_:1 0.725 2 _141_:2 2.1 @@ -4678,25 +4678,25 @@ resp_val O 12 _141_:13 _141_:14 4.2 13 _141_:14 _141_:15 0.005 14 _141_:14 _141_:8 4.2 -15 _446_/A3 _141_:5 1.145 -16 _504_/B _141_:15 2.595 -17 _520_/A2 _141_:1 2.905 -18 _629_/A2 _141_:6 2.175 -19 _704_/A _141_:10 1.445 -20 _736_/Z _141_:11 2.225 +15 _446_:A3 _141_:5 1.145 +16 _504_:B _141_:15 2.595 +17 _520_:A2 _141_:1 2.905 +18 _629_:A2 _141_:6 2.175 +19 _704_:A _141_:10 1.445 +20 _736_:Z _141_:11 2.225 *END *D_NET _142_ 72.8 *CONN -*I _438_/ZN O *D INV_X2 -*I _439_/A1 I *D AND3_X1 -*I _466_/A I *D BUF_X2 -*I _610_/B1 I *D OAI21_X1 -*I _619_/B1 I *D OAI21_X1 -*I _628_/B1 I *D OAI21_X1 -*I _654_/B1 I *D OAI21_X1 -*I _662_/B1 I *D OAI21_X1 -*I _672_/B1 I *D OAI21_X1 +*I _438_:ZN O *D INV_X2 +*I _439_:A1 I *D AND3_X1 +*I _466_:A I *D BUF_X2 +*I _610_:B1 I *D OAI21_X1 +*I _619_:B1 I *D OAI21_X1 +*I _628_:B1 I *D OAI21_X1 +*I _654_:B1 I *D OAI21_X1 +*I _662_:B1 I *D OAI21_X1 +*I _672_:B1 I *D OAI21_X1 *CAP 1 _142_:1 6.3 2 _142_:2 1.6925 @@ -4728,21 +4728,21 @@ resp_val O 12 _142_:13 _142_:14 21 13 _142_:14 _142_:15 0.005 14 _142_:8 _142_:15 8.4 -15 _438_/ZN _142_:3 0.485 -16 _439_/A1 _142_:2 2.575 -17 _466_/A _142_:6 1.965 -18 _610_/B1 _142_:7 2.675 -19 _619_/B1 _142_:11 2.625 -20 _628_/B1 _142_:12 2.785 -21 _654_/B1 _142_:8 2.785 -22 _662_/B1 _142_:9 1.635 -23 _672_/B1 _142_:12 2.115 +15 _438_:ZN _142_:3 0.485 +16 _439_:A1 _142_:2 2.575 +17 _466_:A _142_:6 1.965 +18 _610_:B1 _142_:7 2.675 +19 _619_:B1 _142_:11 2.625 +20 _628_:B1 _142_:12 2.785 +21 _654_:B1 _142_:8 2.785 +22 _662_:B1 _142_:9 1.635 +23 _672_:B1 _142_:12 2.115 *END *D_NET _143_ 23.36 *CONN -*I _441_/ZN O *D NOR4_X1 -*I _445_/A1 I *D NAND4_X1 +*I _441_:ZN O *D NOR4_X1 +*I _445_:A1 I *D NAND4_X1 *CAP 1 _143_:1 0.3575 2 _143_:2 6.3 @@ -4754,17 +4754,17 @@ resp_val O 2 _143_:2 _143_:3 25.2 3 _143_:3 _143_:4 0.005 4 _143_:5 _143_:4 16.8 -5 _441_/ZN _143_:5 3.295 -6 _445_/A1 _143_:1 1.435 +5 _441_:ZN _143_:5 3.295 +6 _445_:A1 _143_:1 1.435 *END *D_NET _144_ 21.71 *CONN -*I _442_/ZN O *D INV_X1 -*I _445_/A2 I *D NAND4_X1 -*I _497_/A1 I *D NOR2_X1 -*I _498_/C2 I *D AOI211_X1 -*I _578_/B2 I *D AOI21_X1 +*I _442_:ZN O *D INV_X1 +*I _445_:A2 I *D NAND4_X1 +*I _497_:A1 I *D NOR2_X1 +*I _498_:C2 I *D AOI211_X1 +*I _578_:B2 I *D AOI21_X1 *CAP 1 _144_:1 1.42 2 _144_:2 1.255 @@ -4784,19 +4784,19 @@ resp_val O 6 _144_:6 _144_:7 0.005 7 _144_:7 _144_:8 12.6 8 _144_:3 _144_:9 4.2 -9 _442_/ZN _144_:8 4.685 -10 _445_/A2 _144_:3 2.005 -11 _497_/A1 _144_:1 1.485 -12 _498_/C2 _144_:9 0.845 -13 _578_/B2 _144_:2 0.825 +9 _442_:ZN _144_:8 4.685 +10 _445_:A2 _144_:3 2.005 +11 _497_:A1 _144_:1 1.485 +12 _498_:C2 _144_:9 0.845 +13 _578_:B2 _144_:2 0.825 *END *D_NET _145_ 13.755 *CONN -*I _443_/ZN O *D INV_X1 -*I _445_/A3 I *D NAND4_X1 -*I _498_/B I *D AOI211_X1 -*I _570_/A1 I *D AND2_X1 +*I _443_:ZN O *D INV_X1 +*I _445_:A3 I *D NAND4_X1 +*I _498_:B I *D AOI211_X1 +*I _570_:A1 I *D AND2_X1 *CAP 1 _145_:1 3.6175 2 _145_:2 1.645 @@ -4810,16 +4810,16 @@ resp_val O 3 _145_:4 _145_:5 4.2 4 _145_:5 _145_:6 0.005 5 _145_:1 _145_:3 8.4 -6 _443_/ZN _145_:3 2.205 -7 _445_/A3 _145_:2 2.385 -8 _498_/B _145_:1 1.875 -9 _570_/A1 _145_:6 4.265 +6 _443_:ZN _145_:3 2.205 +7 _445_:A3 _145_:2 2.385 +8 _498_:B _145_:1 1.875 +9 _570_:A1 _145_:6 4.265 *END *D_NET _146_ 8.43 *CONN -*I _444_/ZN O *D NOR2_X1 -*I _445_/A4 I *D NAND4_X1 +*I _444_:ZN O *D NOR2_X1 +*I _445_:A4 I *D NAND4_X1 *CAP 1 _146_:1 1.425 2 _146_:2 1.05 @@ -4831,15 +4831,15 @@ resp_val O 2 _146_:2 _146_:3 4.2 3 _146_:3 _146_:4 0.005 4 _146_:5 _146_:4 4.2 -5 _444_/ZN _146_:1 5.705 -6 _445_/A4 _146_:5 2.765 +5 _444_:ZN _146_:1 5.705 +6 _445_:A4 _146_:5 2.765 *END *D_NET _147_ 23.8 *CONN -*I _445_/ZN O *D NAND4_X1 -*I _449_/A1 I *D NOR2_X1 -*I _456_/C1 I *D OAI211_X1 +*I _445_:ZN O *D NAND4_X1 +*I _449_:A1 I *D NOR2_X1 +*I _456_:C1 I *D OAI211_X1 *CAP 1 _147_:1 0.7825 2 _147_:2 1.05 @@ -4853,15 +4853,15 @@ resp_val O 3 _147_:3 _147_:4 0.005 4 _147_:3 _147_:5 33.6 5 _147_:5 _147_:6 0.005 -6 _445_/ZN _147_:6 3.595 -7 _449_/A1 _147_:4 3.085 -8 _456_/C1 _147_:1 3.135 +6 _445_:ZN _147_:6 3.595 +7 _449_:A1 _147_:4 3.085 +8 _456_:C1 _147_:1 3.135 *END *D_NET _148_ 6.22 *CONN -*I _446_/ZN O *D NOR4_X1 -*I _448_/A1 I *D NAND2_X1 +*I _446_:ZN O *D NOR4_X1 +*I _448_:A1 I *D NAND2_X1 *CAP 1 _148_:1 0.43 2 _148_:2 1.05 @@ -4873,14 +4873,14 @@ resp_val O 2 _148_:2 _148_:3 4.2 3 _148_:3 _148_:4 0.005 4 _148_:5 _148_:4 4.2 -5 _446_/ZN _148_:1 1.725 -6 _448_/A1 _148_:5 2.325 +5 _446_:ZN _148_:1 1.725 +6 _448_:A1 _148_:5 2.325 *END *D_NET _149_ 13.995 *CONN -*I _447_/ZN O *D NOR4_X1 -*I _448_/A2 I *D NAND2_X1 +*I _447_:ZN O *D NOR4_X1 +*I _448_:A2 I *D NAND2_X1 *CAP 1 _149_:1 1.7925 2 _149_:2 1.05 @@ -4892,15 +4892,15 @@ resp_val O 2 _149_:2 _149_:3 0.005 3 _149_:3 _149_:4 16.8 4 _149_:4 _149_:5 0.005 -5 _447_/ZN _149_:5 4.025 -6 _448_/A2 _149_:1 2.975 +5 _447_:ZN _149_:5 4.025 +6 _448_:A2 _149_:1 2.975 *END *D_NET _150_ 30.865 *CONN -*I _448_/ZN O *D NAND2_X1 -*I _449_/A2 I *D NOR2_X1 -*I _456_/C2 I *D OAI211_X1 +*I _448_:ZN O *D NAND2_X1 +*I _449_:A2 I *D NOR2_X1 +*I _456_:C2 I *D OAI211_X1 *CAP 1 _150_:1 0.6125 2 _150_:2 1.05 @@ -4912,15 +4912,15 @@ resp_val O 2 _150_:2 _150_:3 4.2 3 _150_:3 _150_:4 0.005 4 _150_:5 _150_:4 50.4 -5 _448_/ZN _150_:5 2.255 -6 _449_/A2 _150_:4 2.435 -7 _456_/C2 _150_:1 2.455 +5 _448_:ZN _150_:5 2.255 +6 _449_:A2 _150_:4 2.435 +7 _456_:C2 _150_:1 2.455 *END *D_NET _151_ 10.235 *CONN -*I _449_/ZN O *D NOR2_X1 -*I _452_/A1 I *D NAND3_X1 +*I _449_:ZN O *D NOR2_X1 +*I _452_:A1 I *D NAND3_X1 *CAP 1 _151_:1 0.9025 2 _151_:2 2.1 @@ -4932,17 +4932,17 @@ resp_val O 2 _151_:2 _151_:3 8.4 3 _151_:3 _151_:4 0.005 4 _151_:4 _151_:5 4.2 -5 _449_/ZN _151_:5 4.265 -6 _452_/A1 _151_:1 3.615 +5 _449_:ZN _151_:5 4.265 +6 _452_:A1 _151_:1 3.615 *END *D_NET _152_ 16.855 *CONN -*I _450_/ZN O *D INV_X1 -*I _452_/A2 I *D NAND3_X1 -*I _456_/A I *D OAI211_X1 -*I _460_/A1 I *D NAND4_X1 -*I _462_/A2 I *D NAND3_X1 +*I _450_:ZN O *D INV_X1 +*I _452_:A2 I *D NAND3_X1 +*I _456_:A I *D OAI211_X1 +*I _460_:A1 I *D NAND4_X1 +*I _462_:A2 I *D NAND3_X1 *CAP 1 _152_:1 0.87 2 _152_:2 2.1 @@ -4964,18 +4964,18 @@ resp_val O 7 _152_:8 _152_:9 0.005 8 _152_:8 _152_:2 4.2 9 _152_:10 _152_:6 4.2 -10 _450_/ZN _152_:10 1.485 -11 _452_/A2 _152_:9 3.235 -12 _456_/A _152_:1 3.485 -13 _460_/A1 _152_:5 2.035 -14 _462_/A2 _152_:6 2.495 +10 _450_:ZN _152_:10 1.485 +11 _452_:A2 _152_:9 3.235 +12 _456_:A _152_:1 3.485 +13 _460_:A1 _152_:5 2.035 +14 _462_:A2 _152_:6 2.495 *END *D_NET _153_ 8.55 *CONN -*I _451_/ZN O *D INV_X1 -*I _452_/A3 I *D NAND3_X1 -*I _456_/B I *D OAI211_X1 +*I _451_:ZN O *D INV_X1 +*I _452_:A3 I *D NAND3_X1 +*I _456_:B I *D OAI211_X1 *CAP 1 _153_:1 0.7125 2 _153_:2 2.1 @@ -4985,15 +4985,15 @@ resp_val O 1 _153_:1 _153_:2 0.005 2 _153_:2 _153_:3 8.4 3 _153_:3 _153_:4 0.005 -4 _451_/ZN _153_:4 2.065 -5 _452_/A3 _153_:1 2.855 -6 _456_/B _153_:4 3.795 +4 _451_:ZN _153_:4 2.065 +5 _452_:A3 _153_:1 2.855 +6 _456_:B _153_:4 3.795 *END *D_NET _154_ 6.54 *CONN -*I _452_/ZN O *D NAND3_X1 -*I _455_/A1 I *D NAND2_X1 +*I _452_:ZN O *D NAND3_X1 +*I _455_:A1 I *D NAND2_X1 *CAP 1 _154_:1 1.3825 2 _154_:2 1.05 @@ -5005,27 +5005,27 @@ resp_val O 2 _154_:2 _154_:3 0.005 3 _154_:3 _154_:4 4.2 4 _154_:4 _154_:5 0.005 -5 _452_/ZN _154_:5 3.355 -6 _455_/A1 _154_:1 1.335 +5 _452_:ZN _154_:5 3.355 +6 _455_:A1 _154_:1 1.335 *END *D_NET _155_ 4.295 *CONN -*I _453_/ZN O *D AND2_X1 -*I _454_/A1 I *D OR3_X1 +*I _453_:ZN O *D AND2_X1 +*I _454_:A1 I *D OR3_X1 *CAP 1 _155_:1 1.615 2 _155_:2 1.5825 *RES 1 _155_:2 _155_:1 4.2 -2 _453_/ZN _155_:1 2.265 -3 _454_/A1 _155_:2 2.135 +2 _453_:ZN _155_:1 2.265 +3 _454_:A1 _155_:2 2.135 *END *D_NET _156_ 3.89 *CONN -*I _454_/ZN O *D OR3_X1 -*I _455_/A2 I *D NAND2_X1 +*I _454_:ZN O *D OR3_X1 +*I _455_:A2 I *D NAND2_X1 *CAP 1 _156_:1 0.715 2 _156_:2 1.05 @@ -5035,35 +5035,35 @@ resp_val O 1 _156_:1 _156_:2 0.005 2 _156_:2 _156_:3 4.2 3 _156_:3 _156_:4 0.005 -4 _454_/ZN _156_:1 2.865 -5 _455_/A2 _156_:4 0.725 +4 _454_:ZN _156_:1 2.865 +5 _455_:A2 _156_:4 0.725 *END *D_NET _157_ 5.13 *CONN -*I _456_/ZN O *D OAI211_X1 -*I _461_/A1 I *D NAND2_X1 +*I _456_:ZN O *D OAI211_X1 +*I _461_:A1 I *D NAND2_X1 *CAP 1 _157_:1 2.0525 2 _157_:2 1.5625 *RES 1 _157_:2 _157_:1 4.2 -2 _456_/ZN _157_:1 4.015 -3 _461_/A1 _157_:2 2.055 +2 _456_:ZN _157_:1 4.015 +3 _461_:A1 _157_:2 2.055 *END *D_NET _158_ 80.855 *CONN -*I _457_/ZN O *D INV_X2 -*I _458_/A I *D BUF_X2 -*I _545_/A2 I *D OR2_X2 -*I _601_/B2 I *D OAI21_X1 -*I _610_/B2 I *D OAI21_X1 -*I _619_/B2 I *D OAI21_X1 -*I _628_/B2 I *D OAI21_X1 -*I _654_/B2 I *D OAI21_X1 -*I _662_/B2 I *D OAI21_X1 -*I _672_/B2 I *D OAI21_X1 +*I _457_:ZN O *D INV_X2 +*I _458_:A I *D BUF_X2 +*I _545_:A2 I *D OR2_X2 +*I _601_:B2 I *D OAI21_X1 +*I _610_:B2 I *D OAI21_X1 +*I _619_:B2 I *D OAI21_X1 +*I _628_:B2 I *D OAI21_X1 +*I _654_:B2 I *D OAI21_X1 +*I _662_:B2 I *D OAI21_X1 +*I _672_:B2 I *D OAI21_X1 *CAP 1 _158_:1 2.1 2 _158_:2 3.18 @@ -5111,31 +5111,31 @@ resp_val O 20 _158_:22 _158_:21 8.4 21 _158_:22 _158_:23 0.005 22 _158_:23 _158_:9 16.8 -23 _457_/ZN _158_:2 4.325 -24 _458_/A _158_:3 2.675 -25 _545_/A2 _158_:13 3.905 -26 _601_/B2 _158_:7 2.395 -27 _610_/B2 _158_:14 3.325 -28 _619_/B2 _158_:18 3.275 -29 _628_/B2 _158_:21 2.135 -30 _654_/B2 _158_:8 2.875 -31 _662_/B2 _158_:12 0.985 -32 _672_/B2 _158_:21 1.465 +23 _457_:ZN _158_:2 4.325 +24 _458_:A _158_:3 2.675 +25 _545_:A2 _158_:13 3.905 +26 _601_:B2 _158_:7 2.395 +27 _610_:B2 _158_:14 3.325 +28 _619_:B2 _158_:18 3.275 +29 _628_:B2 _158_:21 2.135 +30 _654_:B2 _158_:8 2.875 +31 _662_:B2 _158_:12 0.985 +32 _672_:B2 _158_:21 1.465 *END *D_NET _159_ 111.975 *CONN -*I _458_/Z O *D BUF_X2 -*I _460_/A2 I *D NAND4_X1 -*I _467_/B2 I *D OAI21_X1 -*I _552_/B2 I *D OAI21_X1 -*I _561_/B2 I *D OAI21_X1 -*I _567_/B2 I *D OAI21_X1 -*I _576_/B2 I *D OAI21_X1 -*I _585_/B2 I *D OAI21_X1 -*I _593_/B2 I *D OAI21_X1 -*I _637_/B2 I *D OAI21_X1 -*I _679_/B2 I *D OAI21_X1 +*I _458_:Z O *D BUF_X2 +*I _460_:A2 I *D NAND4_X1 +*I _467_:B2 I *D OAI21_X1 +*I _552_:B2 I *D OAI21_X1 +*I _561_:B2 I *D OAI21_X1 +*I _567_:B2 I *D OAI21_X1 +*I _576_:B2 I *D OAI21_X1 +*I _585_:B2 I *D OAI21_X1 +*I _593_:B2 I *D OAI21_X1 +*I _637_:B2 I *D OAI21_X1 +*I _679_:B2 I *D OAI21_X1 *CAP 1 _159_:1 0.6525 2 _159_:2 1.05 @@ -5199,32 +5199,32 @@ resp_val O 28 _159_:25 _159_:30 16.8 29 _159_:22 _159_:31 0.005 30 _159_:31 _159_:24 25.2 -31 _458_/Z _159_:1 2.615 -32 _460_/A2 _159_:5 2.765 -33 _467_/B2 _159_:9 1.085 -34 _552_/B2 _159_:21 2.405 -35 _561_/B2 _159_:22 2.775 -36 _567_/B2 _159_:16 2.855 -37 _576_/B2 _159_:15 2.845 -38 _585_/B2 _159_:13 3.675 -39 _593_/B2 _159_:14 2.175 -40 _637_/B2 _159_:25 1.325 -41 _679_/B2 _159_:23 2.085 +31 _458_:Z _159_:1 2.615 +32 _460_:A2 _159_:5 2.765 +33 _467_:B2 _159_:9 1.085 +34 _552_:B2 _159_:21 2.405 +35 _561_:B2 _159_:22 2.775 +36 _567_:B2 _159_:16 2.855 +37 _576_:B2 _159_:15 2.845 +38 _585_:B2 _159_:13 3.675 +39 _593_:B2 _159_:14 2.175 +40 _637_:B2 _159_:25 1.325 +41 _679_:B2 _159_:23 2.085 *END *D_NET _160_ 131.025 *CONN -*I _459_/Z O *D BUF_X2 -*I _460_/A3 I *D NAND4_X1 -*I _464_/C1 I *D AOI211_X1 -*I _683_/S I *D MUX2_X1 -*I _687_/S I *D MUX2_X1 -*I _689_/S I *D MUX2_X1 -*I _691_/S I *D MUX2_X1 -*I _693_/S I *D MUX2_X1 -*I _695_/S I *D MUX2_X1 -*I _697_/S I *D MUX2_X1 -*I _699_/S I *D MUX2_X1 +*I _459_:Z O *D BUF_X2 +*I _460_:A3 I *D NAND4_X1 +*I _464_:C1 I *D AOI211_X1 +*I _683_:S I *D MUX2_X1 +*I _687_:S I *D MUX2_X1 +*I _689_:S I *D MUX2_X1 +*I _691_:S I *D MUX2_X1 +*I _693_:S I *D MUX2_X1 +*I _695_:S I *D MUX2_X1 +*I _697_:S I *D MUX2_X1 +*I _699_:S I *D MUX2_X1 *CAP 1 _160_:1 0.655 2 _160_:2 2.1 @@ -5280,23 +5280,23 @@ resp_val O 24 _160_:23 _160_:18 46.2 25 _160_:27 _160_:27 0.005 26 _160_:27 _160_:9 21 -27 _459_/Z _160_:19 5.295 -28 _460_/A3 _160_:1 2.625 -29 _464_/C1 _160_:6 3.545 -30 _683_/S _160_:13 2.155 -31 _687_/S _160_:5 1.775 -32 _689_/S _160_:14 2.615 -33 _691_/S _160_:18 2.835 -34 _693_/S _160_:22 4.335 -35 _695_/S _160_:22 1.935 -36 _697_/S _160_:24 1.455 -37 _699_/S _160_:9 2.535 +27 _459_:Z _160_:19 5.295 +28 _460_:A3 _160_:1 2.625 +29 _464_:C1 _160_:6 3.545 +30 _683_:S _160_:13 2.155 +31 _687_:S _160_:5 1.775 +32 _689_:S _160_:14 2.615 +33 _691_:S _160_:18 2.835 +34 _693_:S _160_:22 4.335 +35 _695_:S _160_:22 1.935 +36 _697_:S _160_:24 1.455 +37 _699_:S _160_:9 2.535 *END *D_NET _161_ 6.295 *CONN -*I _460_/ZN O *D NAND4_X1 -*I _461_/A2 I *D NAND2_X1 +*I _460_:ZN O *D NAND4_X1 +*I _461_:A2 I *D NAND2_X1 *CAP 1 _161_:1 1.4 2 _161_:2 1.05 @@ -5308,14 +5308,14 @@ resp_val O 2 _161_:2 _161_:3 0.005 3 _161_:3 _161_:4 4.2 4 _161_:4 _161_:5 0.005 -5 _460_/ZN _161_:5 2.795 -6 _461_/A2 _161_:1 1.405 +5 _460_:ZN _161_:5 2.795 +6 _461_:A2 _161_:1 1.405 *END *D_NET _162_ 6.56 *CONN -*I _462_/ZN O *D NAND3_X1 -*I _463_/A1 I *D NOR2_X1 +*I _462_:ZN O *D NAND3_X1 +*I _463_:A1 I *D NOR2_X1 *CAP 1 _162_:1 1.5775 2 _162_:2 1.05 @@ -5327,27 +5327,27 @@ resp_val O 2 _162_:2 _162_:3 0.005 3 _162_:3 _162_:4 4.2 4 _162_:4 _162_:5 0.005 -5 _462_/ZN _162_:5 2.615 -6 _463_/A1 _162_:1 2.115 +5 _462_:ZN _162_:5 2.615 +6 _463_:A1 _162_:1 2.115 *END *D_NET _163_ 4.795 *CONN -*I _463_/ZN O *D NOR2_X1 -*I _465_/A1 I *D OR3_X1 +*I _463_:ZN O *D NOR2_X1 +*I _465_:A1 I *D OR3_X1 *CAP 1 _163_:1 1.6825 2 _163_:2 1.765 *RES 1 _163_:2 _163_:1 4.2 -2 _463_/ZN _163_:1 2.535 -3 _465_/A1 _163_:2 2.865 +2 _463_:ZN _163_:1 2.535 +3 _465_:A1 _163_:2 2.865 *END *D_NET _164_ 5.96 *CONN -*I _464_/ZN O *D AOI211_X1 -*I _465_/A3 I *D OR3_X1 +*I _464_:ZN O *D AOI211_X1 +*I _465_:A3 I *D OR3_X1 *CAP 1 _164_:1 0.905 2 _164_:2 1.05 @@ -5357,23 +5357,23 @@ resp_val O 1 _164_:1 _164_:2 0.005 2 _164_:2 _164_:3 4.2 3 _164_:3 _164_:4 0.005 -4 _464_/ZN _164_:4 4.105 -5 _465_/A3 _164_:1 3.625 +4 _464_:ZN _164_:4 4.105 +5 _465_:A3 _164_:1 3.625 *END *D_NET _165_ 103.09 *CONN -*I _466_/Z O *D BUF_X2 -*I _467_/B1 I *D OAI21_X1 -*I _552_/B1 I *D OAI21_X1 -*I _561_/B1 I *D OAI21_X1 -*I _567_/B1 I *D OAI21_X1 -*I _576_/B1 I *D OAI21_X1 -*I _585_/B1 I *D OAI21_X1 -*I _593_/B1 I *D OAI21_X1 -*I _601_/B1 I *D OAI21_X1 -*I _637_/B1 I *D OAI21_X1 -*I _679_/B1 I *D OAI21_X1 +*I _466_:Z O *D BUF_X2 +*I _467_:B1 I *D OAI21_X1 +*I _552_:B1 I *D OAI21_X1 +*I _561_:B1 I *D OAI21_X1 +*I _567_:B1 I *D OAI21_X1 +*I _576_:B1 I *D OAI21_X1 +*I _585_:B1 I *D OAI21_X1 +*I _593_:B1 I *D OAI21_X1 +*I _601_:B1 I *D OAI21_X1 +*I _637_:B1 I *D OAI21_X1 +*I _679_:B1 I *D OAI21_X1 *CAP 1 _165_:1 0.2125 2 _165_:2 1.05 @@ -5433,23 +5433,23 @@ resp_val O 26 _165_:28 _165_:29 0.005 27 _165_:29 _165_:25 4.2 28 _165_:7 _165_:23 21 -29 _466_/Z _165_:1 0.855 -30 _467_/B1 _165_:9 1.735 -31 _552_/B1 _165_:20 2.555 -32 _561_/B1 _165_:5 3.425 -33 _567_/B1 _165_:16 2.205 -34 _576_/B1 _165_:14 2.195 -35 _585_/B1 _165_:13 3.025 -36 _593_/B1 _165_:15 1.525 -37 _601_/B1 _165_:21 1.745 -38 _637_/B1 _165_:24 0.735 -39 _679_/B1 _165_:22 1.435 +29 _466_:Z _165_:1 0.855 +30 _467_:B1 _165_:9 1.735 +31 _552_:B1 _165_:20 2.555 +32 _561_:B1 _165_:5 3.425 +33 _567_:B1 _165_:16 2.205 +34 _576_:B1 _165_:14 2.195 +35 _585_:B1 _165_:13 3.025 +36 _593_:B1 _165_:15 1.525 +37 _601_:B1 _165_:21 1.745 +38 _637_:B1 _165_:24 0.735 +39 _679_:B1 _165_:22 1.435 *END *D_NET _166_ 8.595 *CONN -*I _467_/ZN O *D OAI21_X1 -*I _547_/A I *D OAI211_X1 +*I _467_:ZN O *D OAI21_X1 +*I _547_:A I *D OAI211_X1 *CAP 1 _166_:1 1.765 2 _166_:2 1.05 @@ -5463,15 +5463,15 @@ resp_val O 3 _166_:3 _166_:4 4.2 4 _166_:4 _166_:5 0.005 5 _166_:5 _166_:6 4.2 -6 _467_/ZN _166_:6 1.735 -7 _547_/A _166_:1 2.865 +6 _467_:ZN _166_:6 1.735 +7 _547_:A _166_:1 2.865 *END *D_NET _167_ 6.725 *CONN -*I _468_/ZN O *D INV_X1 -*I _469_/A1 I *D NAND2_X1 -*I _682_/B1 I *D OAI21_X1 +*I _468_:ZN O *D INV_X1 +*I _469_:A1 I *D NAND2_X1 +*I _682_:B1 I *D OAI21_X1 *CAP 1 _167_:1 1.585 2 _167_:2 1.05 @@ -5481,15 +5481,15 @@ resp_val O 1 _167_:1 _167_:2 0.005 2 _167_:2 _167_:3 4.2 3 _167_:3 _167_:4 0.005 -4 _468_/ZN _167_:1 3.165 -5 _469_/A1 _167_:1 3.185 -6 _682_/B1 _167_:4 2.915 +4 _468_:ZN _167_:1 3.165 +5 _469_:A1 _167_:1 3.185 +6 _682_:B1 _167_:4 2.915 *END *D_NET _168_ 8.515 *CONN -*I _469_/ZN O *D NAND2_X1 -*I _530_/A1 I *D AND4_X1 +*I _469_:ZN O *D NAND2_X1 +*I _530_:A1 I *D AND4_X1 *CAP 1 _168_:1 1.38 2 _168_:2 1.05 @@ -5501,17 +5501,17 @@ resp_val O 2 _168_:2 _168_:3 0.005 3 _168_:3 _168_:4 8.4 4 _168_:4 _168_:5 0.005 -5 _469_/ZN _168_:5 3.115 -6 _530_/A1 _168_:1 1.325 +5 _469_:ZN _168_:5 3.115 +6 _530_:A1 _168_:1 1.325 *END *D_NET _169_ 17.43 *CONN -*I _470_/ZN O *D XNOR2_X2 -*I _472_/A1 I *D AND2_X1 -*I _495_/A1 I *D NAND3_X1 -*I _606_/B I *D XNOR2_X1 -*I _612_/A1 I *D AND2_X1 +*I _470_:ZN O *D XNOR2_X2 +*I _472_:A1 I *D AND2_X1 +*I _495_:A1 I *D NAND3_X1 +*I _606_:B I *D XNOR2_X1 +*I _612_:A1 I *D AND2_X1 *CAP 1 _169_:1 1.1525 2 _169_:2 1.05 @@ -5535,18 +5535,18 @@ resp_val O 8 _169_:5 _169_:9 4.2 9 _169_:9 _169_:10 0.005 10 _169_:10 _169_:11 4.2 -11 _470_/ZN _169_:11 1.595 -12 _472_/A1 _169_:1 0.415 -13 _495_/A1 _169_:7 0.805 -14 _606_/B _169_:6 1.665 -15 _612_/A1 _169_:3 1.005 +11 _470_:ZN _169_:11 1.595 +12 _472_:A1 _169_:1 0.415 +13 _495_:A1 _169_:7 0.805 +14 _606_:B _169_:6 1.665 +15 _612_:A1 _169_:3 1.005 *END *D_NET _170_ 5.795 *CONN -*I _471_/ZN O *D XNOR2_X1 -*I _472_/A2 I *D AND2_X1 -*I _597_/B I *D XNOR2_X1 +*I _471_:ZN O *D XNOR2_X1 +*I _472_:A2 I *D AND2_X1 +*I _597_:B I *D XNOR2_X1 *CAP 1 _170_:1 2.52 2 _170_:2 1.2475 @@ -5554,19 +5554,19 @@ resp_val O *RES 1 _170_:1 _170_:2 4.2 2 _170_:3 _170_:1 4.2 -3 _471_/ZN _170_:3 0.725 -4 _472_/A2 _170_:2 0.795 -5 _597_/B _170_:1 1.685 +3 _471_:ZN _170_:3 0.725 +4 _472_:A2 _170_:2 0.795 +5 _597_:B _170_:1 1.685 *END *D_NET _171_ 25.735 *CONN -*I _472_/ZN O *D AND2_X1 -*I _479_/A1 I *D NAND3_X1 -*I _490_/A I *D OAI21_X1 -*I _499_/A I *D OAI211_X1 -*I _538_/A1 I *D AND2_X1 -*I _613_/C2 I *D AOI221_X1 +*I _472_:ZN O *D AND2_X1 +*I _479_:A1 I *D NAND3_X1 +*I _490_:A I *D OAI21_X1 +*I _499_:A I *D OAI211_X1 +*I _538_:A1 I *D AND2_X1 +*I _613_:C2 I *D AOI221_X1 *CAP 1 _171_:1 1.7575 2 _171_:2 6.3 @@ -5584,20 +5584,20 @@ resp_val O 5 _171_:5 _171_:7 0.005 6 _171_:7 _171_:2 16.8 7 _171_:8 _171_:1 4.2 -8 _472_/ZN _171_:8 1.485 -9 _479_/A1 _171_:5 3.895 -10 _490_/A _171_:4 1.175 -11 _499_/A _171_:6 2.985 -12 _538_/A1 _171_:5 1.325 -13 _613_/C2 _171_:1 2.835 +8 _472_:ZN _171_:8 1.485 +9 _479_:A1 _171_:5 3.895 +10 _490_:A _171_:4 1.175 +11 _499_:A _171_:6 2.985 +12 _538_:A1 _171_:5 1.325 +13 _613_:C2 _171_:1 2.835 *END *D_NET _172_ 11.975 *CONN -*I _473_/ZN O *D XNOR2_X1 -*I _475_/A1 I *D AND2_X1 -*I _572_/B I *D XNOR2_X1 -*I _577_/A1 I *D AND2_X1 +*I _473_:ZN O *D XNOR2_X1 +*I _475_:A1 I *D AND2_X1 +*I _572_:B I *D XNOR2_X1 +*I _577_:A1 I *D AND2_X1 *CAP 1 _172_:1 0.395 2 _172_:2 2.1 @@ -5615,18 +5615,18 @@ resp_val O 5 _172_:7 _172_:6 4.2 6 _172_:7 _172_:8 0.005 7 _172_:8 _172_:2 4.2 -8 _473_/ZN _172_:5 2.045 -9 _475_/A1 _172_:6 2.055 -10 _572_/B _172_:5 1.485 -11 _577_/A1 _172_:1 1.585 +8 _473_:ZN _172_:5 2.045 +9 _475_:A1 _172_:6 2.055 +10 _572_:B _172_:5 1.485 +11 _577_:A1 _172_:1 1.585 *END *D_NET _173_ 15.425 *CONN -*I _474_/ZN O *D XNOR2_X1 -*I _475_/A2 I *D AND2_X1 -*I _563_/B I *D XNOR2_X1 -*I _569_/A2 I *D AND2_X1 +*I _474_:ZN O *D XNOR2_X1 +*I _475_:A2 I *D AND2_X1 +*I _563_:B I *D XNOR2_X1 +*I _569_:A2 I *D AND2_X1 *CAP 1 _173_:1 1.92 2 _173_:2 1.4675 @@ -5644,18 +5644,18 @@ resp_val O 5 _173_:5 _173_:7 4.2 6 _173_:7 _173_:2 0.005 7 _173_:6 _173_:8 8.4 -8 _474_/ZN _173_:8 2.405 -9 _475_/A2 _173_:2 1.675 -10 _563_/B _173_:3 2.305 -11 _569_/A2 _173_:1 3.485 +8 _474_:ZN _173_:8 2.405 +9 _475_:A2 _173_:2 1.675 +10 _563_:B _173_:3 2.305 +11 _569_:A2 _173_:1 3.485 *END *D_NET _174_ 23.94 *CONN -*I _475_/ZN O *D AND2_X1 -*I _479_/A2 I *D NAND3_X1 -*I _539_/A4 I *D NAND4_X1 -*I _579_/A2 I *D NAND2_X1 +*I _475_:ZN O *D AND2_X1 +*I _479_:A2 I *D NAND3_X1 +*I _539_:A4 I *D NAND4_X1 +*I _579_:A2 I *D NAND2_X1 *CAP 1 _174_:1 0.585 2 _174_:2 2.1 @@ -5673,20 +5673,20 @@ resp_val O 5 _174_:5 _174_:6 0.005 6 _174_:6 _174_:7 12.6 7 _174_:7 _174_:8 12.6 -8 _475_/ZN _174_:8 1.825 -9 _479_/A2 _174_:4 3.435 -10 _539_/A4 _174_:1 2.345 -11 _579_/A2 _174_:7 2.495 +8 _475_:ZN _174_:8 1.825 +9 _479_:A2 _174_:4 3.435 +10 _539_:A4 _174_:1 2.345 +11 _579_:A2 _174_:7 2.495 *END *D_NET _175_ 20.41 *CONN -*I _476_/ZN O *D XNOR2_X2 -*I _478_/A1 I *D AND2_X1 -*I _487_/A1 I *D AND3_X1 -*I _588_/A2 I *D NOR3_X1 -*I _589_/B1 I *D AOI221_X4 -*I _594_/A1 I *D NAND2_X1 +*I _476_:ZN O *D XNOR2_X2 +*I _478_:A1 I *D AND2_X1 +*I _487_:A1 I *D AND3_X1 +*I _588_:A2 I *D NOR3_X1 +*I _589_:B1 I *D AOI221_X4 +*I _594_:A1 I *D NAND2_X1 *CAP 1 _175_:1 1.6875 2 _175_:2 2.045 @@ -5710,20 +5710,20 @@ resp_val O 8 _175_:10 _175_:11 4.2 9 _175_:11 _175_:4 0.005 10 _175_:11 _175_:6 4.2 -11 _476_/ZN _175_:9 2.655 -12 _478_/A1 _175_:1 2.555 -13 _487_/A1 _175_:5 2.275 -14 _588_/A2 _175_:3 2.575 -15 _589_/B1 _175_:2 3.985 -16 _594_/A1 _175_:4 1.605 +11 _476_:ZN _175_:9 2.655 +12 _478_:A1 _175_:1 2.555 +13 _487_:A1 _175_:5 2.275 +14 _588_:A2 _175_:3 2.575 +15 _589_:B1 _175_:2 3.985 +16 _594_:A1 _175_:4 1.605 *END *D_NET _176_ 8.39 *CONN -*I _477_/ZN O *D XNOR2_X1 -*I _478_/A2 I *D AND2_X1 -*I _581_/B I *D XOR2_X1 -*I _586_/A2 I *D AND2_X1 +*I _477_:ZN O *D XNOR2_X1 +*I _478_:A2 I *D AND2_X1 +*I _581_:B I *D XOR2_X1 +*I _586_:A2 I *D AND2_X1 *CAP 1 _176_:1 2.0275 2 _176_:2 1.5925 @@ -5735,20 +5735,20 @@ resp_val O 2 _176_:1 _176_:3 0.005 3 _176_:3 _176_:4 4.2 4 _176_:4 _176_:5 0.005 -5 _477_/ZN _176_:5 2.305 -6 _478_/A2 _176_:2 2.175 -7 _581_/B _176_:1 2.815 -8 _586_/A2 _176_:1 1.105 +5 _477_:ZN _176_:5 2.305 +6 _478_:A2 _176_:2 2.175 +7 _581_:B _176_:1 2.815 +8 _586_:A2 _176_:1 1.105 *END *D_NET _177_ 29.195 *CONN -*I _478_/ZN O *D AND2_X1 -*I _479_/A3 I *D NAND3_X1 -*I _499_/B I *D OAI211_X1 -*I _538_/A2 I *D AND2_X1 -*I _589_/C1 I *D AOI221_X4 -*I _596_/B2 I *D AOI21_X1 +*I _478_:ZN O *D AND2_X1 +*I _479_:A3 I *D NAND3_X1 +*I _499_:B I *D OAI211_X1 +*I _538_:A2 I *D AND2_X1 +*I _589_:C1 I *D AOI221_X4 +*I _596_:B2 I *D AOI21_X1 *CAP 1 _177_:1 0.235 2 _177_:2 2.1 @@ -5778,18 +5778,18 @@ resp_val O 11 _177_:3 _177_:13 16.8 12 _177_:13 _177_:14 0.005 13 _177_:10 _177_:14 4.2 -14 _478_/ZN _177_:8 2.125 -15 _479_/A3 _177_:6 3.055 -16 _499_/B _177_:5 2.895 -17 _538_/A2 _177_:1 0.945 -18 _589_/C1 _177_:9 2.505 -19 _596_/B2 _177_:10 0.695 +14 _478_:ZN _177_:8 2.125 +15 _479_:A3 _177_:6 3.055 +16 _499_:B _177_:5 2.895 +17 _538_:A2 _177_:1 0.945 +18 _589_:C1 _177_:9 2.505 +19 _596_:B2 _177_:10 0.695 *END *D_NET _178_ 9.595 *CONN -*I _479_/ZN O *D NAND3_X1 -*I _485_/A1 I *D OR3_X1 +*I _479_:ZN O *D NAND3_X1 +*I _485_:A1 I *D OR3_X1 *CAP 1 _178_:1 2.1 2 _178_:2 2.86 @@ -5801,15 +5801,15 @@ resp_val O 2 _178_:1 _178_:3 0.005 3 _178_:3 _178_:4 4.2 4 _178_:4 _178_:5 0.005 -5 _479_/ZN _178_:5 3.555 -6 _485_/A1 _178_:2 3.045 +5 _479_:ZN _178_:5 3.555 +6 _485_:A1 _178_:2 3.045 *END *D_NET _179_ 10.485 *CONN -*I _480_/ZN O *D INV_X1 -*I _481_/A1 I *D AND2_X1 -*I _482_/A1 I *D NOR2_X1 +*I _480_:ZN O *D INV_X1 +*I _481_:A1 I *D AND2_X1 +*I _482_:A1 I *D NOR2_X1 *CAP 1 _179_:1 0.6075 2 _179_:2 3.15 @@ -5823,16 +5823,16 @@ resp_val O 3 _179_:3 _179_:4 0.005 4 _179_:5 _179_:6 0.005 5 _179_:6 _179_:2 8.4 -6 _480_/ZN _179_:5 3.765 -7 _481_/A1 _179_:1 2.435 -8 _482_/A1 _179_:4 2.185 +6 _480_:ZN _179_:5 3.765 +7 _481_:A1 _179_:1 2.435 +8 _482_:A1 _179_:4 2.185 *END *D_NET _180_ 7.58 *CONN -*I _481_/ZN O *D AND2_X1 -*I _485_/A2 I *D OR3_X1 -*I _562_/A I *D AOI21_X1 +*I _481_:ZN O *D AND2_X1 +*I _485_:A2 I *D OR3_X1 +*I _562_:A I *D AOI21_X1 *CAP 1 _180_:1 1.375 2 _180_:2 1.05 @@ -5844,29 +5844,29 @@ resp_val O 2 _180_:2 _180_:3 4.2 3 _180_:3 _180_:4 0.005 4 _180_:1 _180_:5 4.2 -5 _481_/ZN _180_:1 1.305 -6 _485_/A2 _180_:4 3.425 -7 _562_/A _180_:5 2.045 +5 _481_:ZN _180_:1 1.305 +6 _485_:A2 _180_:4 3.425 +7 _562_:A _180_:5 2.045 *END *D_NET _181_ 3.79 *CONN -*I _482_/ZN O *D NOR2_X1 -*I _484_/A1 I *D NOR3_X1 +*I _482_:ZN O *D NOR2_X1 +*I _484_:A1 I *D NOR3_X1 *CAP 1 _181_:1 1.675 2 _181_:2 1.27 *RES 1 _181_:1 _181_:2 4.2 -2 _482_/ZN _181_:1 2.505 -3 _484_/A1 _181_:2 0.885 +2 _482_:ZN _181_:1 2.505 +3 _484_:A1 _181_:2 0.885 *END *D_NET _182_ 6.695 *CONN -*I _483_/ZN O *D INV_X1 -*I _484_/A2 I *D NOR3_X1 -*I _556_/A1 I *D NAND2_X1 +*I _483_:ZN O *D INV_X1 +*I _484_:A2 I *D NOR3_X1 +*I _556_:A1 I *D NAND2_X1 *CAP 1 _182_:1 2.5425 2 _182_:2 1.275 @@ -5874,28 +5874,28 @@ resp_val O *RES 1 _182_:2 _182_:1 4.2 2 _182_:1 _182_:3 4.2 -3 _483_/ZN _182_:3 2.325 -4 _484_/A2 _182_:2 0.905 -5 _556_/A1 _182_:1 1.775 +3 _483_:ZN _182_:3 2.325 +4 _484_:A2 _182_:2 0.905 +5 _556_:A1 _182_:1 1.775 *END *D_NET _183_ 4.19 *CONN -*I _484_/ZN O *D NOR3_X1 -*I _485_/A3 I *D OR3_X1 +*I _484_:ZN O *D NOR3_X1 +*I _485_:A3 I *D OR3_X1 *CAP 1 _183_:1 1.145 2 _183_:2 2 *RES 1 _183_:2 _183_:1 4.2 -2 _484_/ZN _183_:1 0.385 -3 _485_/A3 _183_:2 3.805 +2 _484_:ZN _183_:1 0.385 +3 _485_:A3 _183_:2 3.805 *END *D_NET _184_ 9.82 *CONN -*I _485_/ZN O *D OR3_X1 -*I _500_/A1 I *D NAND3_X1 +*I _485_:ZN O *D OR3_X1 +*I _500_:A1 I *D NAND3_X1 *CAP 1 _184_:1 2.1 2 _184_:2 3.34 @@ -5907,29 +5907,29 @@ resp_val O 2 _184_:1 _184_:3 0.005 3 _184_:3 _184_:4 4.2 4 _184_:4 _184_:5 0.005 -5 _485_/ZN _184_:2 4.965 -6 _500_/A1 _184_:5 2.085 +5 _485_:ZN _184_:2 4.965 +6 _500_:A1 _184_:5 2.085 *END *D_NET _185_ 5.6 *CONN -*I _486_/ZN O *D INV_X1 -*I _487_/A2 I *D AND3_X1 -*I _587_/A1 I *D NOR2_X1 +*I _486_:ZN O *D INV_X1 +*I _487_:A2 I *D AND3_X1 +*I _587_:A1 I *D NOR2_X1 *CAP 1 _185_:1 1.77 2 _185_:2 2.08 *RES 1 _185_:1 _185_:2 4.2 -2 _486_/ZN _185_:1 2.885 -3 _487_/A2 _185_:2 1.895 -4 _587_/A1 _185_:2 2.235 +2 _486_:ZN _185_:1 2.885 +3 _487_:A2 _185_:2 1.895 +4 _587_:A1 _185_:2 2.235 *END *D_NET _186_ 7.495 *CONN -*I _487_/ZN O *D AND3_X1 -*I _490_/B1 I *D OAI21_X1 +*I _487_:ZN O *D AND3_X1 +*I _490_:B1 I *D OAI21_X1 *CAP 1 _186_:1 1.4375 2 _186_:2 1.05 @@ -5941,15 +5941,15 @@ resp_val O 2 _186_:2 _186_:3 0.005 3 _186_:3 _186_:4 8.4 4 _186_:4 _186_:5 0.005 -5 _487_/ZN _186_:5 0.845 -6 _490_/B1 _186_:1 1.555 +5 _487_:ZN _186_:5 0.845 +6 _490_:B1 _186_:1 1.555 *END *D_NET _187_ 9.91 *CONN -*I _488_/ZN O *D INV_X1 -*I _489_/A1 I *D AND2_X1 -*I _595_/B1 I *D OAI21_X1 +*I _488_:ZN O *D INV_X1 +*I _489_:A1 I *D AND2_X1 +*I _595_:B1 I *D OAI21_X1 *CAP 1 _187_:1 0.9175 2 _187_:2 1.05 @@ -5965,15 +5965,15 @@ resp_val O 4 _187_:3 _187_:5 4.2 5 _187_:5 _187_:6 0.005 6 _187_:6 _187_:7 4.2 -7 _488_/ZN _187_:7 1.605 -8 _489_/A1 _187_:1 3.675 -9 _595_/B1 _187_:4 1.955 +7 _488_:ZN _187_:7 1.605 +8 _489_:A1 _187_:1 3.675 +9 _595_:B1 _187_:4 1.955 *END *D_NET _188_ 7.45 *CONN -*I _489_/ZN O *D AND2_X1 -*I _490_/B2 I *D OAI21_X1 +*I _489_:ZN O *D AND2_X1 +*I _490_:B2 I *D OAI21_X1 *CAP 1 _188_:1 1.6 2 _188_:2 1.05 @@ -5985,14 +5985,14 @@ resp_val O 2 _188_:2 _188_:3 0.005 3 _188_:3 _188_:4 4.2 4 _188_:4 _188_:5 0.005 -5 _489_/ZN _188_:5 4.305 -6 _490_/B2 _188_:1 2.205 +5 _489_:ZN _188_:5 4.305 +6 _490_:B2 _188_:1 2.205 *END *D_NET _189_ 12.795 *CONN -*I _490_/ZN O *D OAI21_X1 -*I _496_/A1 I *D AND3_X1 +*I _490_:ZN O *D OAI21_X1 +*I _496_:A1 I *D AND3_X1 *CAP 1 _189_:1 1.675 2 _189_:2 1.05 @@ -6004,15 +6004,15 @@ resp_val O 2 _189_:2 _189_:3 0.005 3 _189_:3 _189_:4 16.8 4 _189_:4 _189_:5 0.005 -5 _490_/ZN _189_:5 2.095 -6 _496_/A1 _189_:1 2.505 +5 _490_:ZN _189_:5 2.095 +6 _496_:A1 _189_:1 2.505 *END *D_NET _190_ 10.67 *CONN -*I _491_/ZN O *D INV_X1 -*I _492_/A1 I *D NOR2_X1 -*I _613_/B2 I *D AOI221_X1 +*I _491_:ZN O *D INV_X1 +*I _492_:A1 I *D NOR2_X1 +*I _613_:B2 I *D AOI221_X1 *CAP 1 _190_:1 2.1 2 _190_:2 1.885 @@ -6026,15 +6026,15 @@ resp_val O 3 _190_:4 _190_:5 4.2 4 _190_:5 _190_:1 0.005 5 _190_:6 _190_:1 4.2 -6 _491_/ZN _190_:2 3.345 -7 _492_/A1 _190_:3 1.435 -8 _613_/B2 _190_:6 3.975 +6 _491_:ZN _190_:2 3.345 +7 _492_:A1 _190_:3 1.435 +8 _613_:B2 _190_:6 3.975 *END *D_NET _191_ 5.29 *CONN -*I _492_/ZN O *D NOR2_X1 -*I _493_/A I *D INV_X1 +*I _492_:ZN O *D NOR2_X1 +*I _493_:A I *D INV_X1 *CAP 1 _191_:1 0.4275 2 _191_:2 1.05 @@ -6046,29 +6046,29 @@ resp_val O 2 _191_:2 _191_:3 4.2 3 _191_:3 _191_:4 0.005 4 _191_:5 _191_:4 4.2 -5 _492_/ZN _191_:5 0.475 -6 _493_/A _191_:1 1.715 +5 _492_:ZN _191_:5 0.475 +6 _493_:A _191_:1 1.715 *END *D_NET _192_ 4.22 *CONN -*I _493_/ZN O *D INV_X1 -*I _496_/A2 I *D AND3_X1 +*I _493_:ZN O *D INV_X1 +*I _496_:A2 I *D AND3_X1 *CAP 1 _192_:1 1.58 2 _192_:2 1.58 *RES 1 _192_:2 _192_:1 4.2 -2 _493_/ZN _192_:1 2.125 -3 _496_/A2 _192_:2 2.125 +2 _493_:ZN _192_:1 2.125 +3 _496_:A2 _192_:2 2.125 *END *D_NET _193_ 10.45 *CONN -*I _494_/ZN O *D INV_X1 -*I _495_/A2 I *D NAND3_X1 -*I _602_/A1 I *D AND2_X1 -*I _603_/A1 I *D NOR2_X1 +*I _494_:ZN O *D INV_X1 +*I _495_:A2 I *D NAND3_X1 +*I _602_:A1 I *D AND2_X1 +*I _603_:A1 I *D NOR2_X1 *CAP 1 _193_:1 2.355 2 _193_:2 1.295 @@ -6082,29 +6082,29 @@ resp_val O 3 _193_:4 _193_:5 0.005 4 _193_:5 _193_:6 4.2 5 _193_:6 _193_:1 0.005 -6 _494_/ZN _193_:3 2.105 -7 _495_/A2 _193_:2 0.985 -8 _602_/A1 _193_:1 2.965 -9 _603_/A1 _193_:1 2.265 +6 _494_:ZN _193_:3 2.105 +7 _495_:A2 _193_:2 0.985 +8 _602_:A1 _193_:1 2.965 +9 _603_:A1 _193_:1 2.265 *END *D_NET _194_ 4.025 *CONN -*I _495_/ZN O *D NAND3_X1 -*I _496_/A3 I *D AND3_X1 +*I _495_:ZN O *D NAND3_X1 +*I _496_:A3 I *D AND3_X1 *CAP 1 _194_:1 1.5775 2 _194_:2 1.485 *RES 1 _194_:1 _194_:2 4.2 -2 _495_/ZN _194_:1 2.115 -3 _496_/A3 _194_:2 1.745 +2 _495_:ZN _194_:1 2.115 +3 _496_:A3 _194_:2 1.745 *END *D_NET _195_ 6.215 *CONN -*I _496_/ZN O *D AND3_X1 -*I _500_/A2 I *D NAND3_X1 +*I _496_:ZN O *D AND3_X1 +*I _500_:A2 I *D NAND3_X1 *CAP 1 _195_:1 0.615 2 _195_:2 2.1 @@ -6114,14 +6114,14 @@ resp_val O 1 _195_:1 _195_:2 0.005 2 _195_:2 _195_:3 8.4 3 _195_:3 _195_:4 0.005 -4 _496_/ZN _195_:4 1.575 -5 _500_/A2 _195_:1 2.465 +4 _496_:ZN _195_:4 1.575 +5 _500_:A2 _195_:1 2.465 *END *D_NET _196_ 6.415 *CONN -*I _497_/ZN O *D NOR2_X1 -*I _499_/C1 I *D OAI211_X1 +*I _497_:ZN O *D NOR2_X1 +*I _499_:C1 I *D OAI211_X1 *CAP 1 _196_:1 1.7075 2 _196_:2 1.05 @@ -6133,40 +6133,40 @@ resp_val O 2 _196_:2 _196_:3 0.005 3 _196_:3 _196_:4 4.2 4 _196_:4 _196_:5 0.005 -5 _497_/ZN _196_:5 1.805 -6 _499_/C1 _196_:1 2.635 +5 _497_:ZN _196_:5 1.805 +6 _499_:C1 _196_:1 2.635 *END *D_NET _197_ 7.625 *CONN -*I _498_/ZN O *D AOI211_X1 -*I _499_/C2 I *D OAI211_X1 +*I _498_:ZN O *D AOI211_X1 +*I _499_:C2 I *D OAI211_X1 *CAP 1 _197_:1 3.6375 2 _197_:2 3.325 *RES 1 _197_:1 _197_:2 12.6 -2 _498_/ZN _197_:2 0.705 -3 _499_/C2 _197_:1 1.955 +2 _498_:ZN _197_:2 0.705 +3 _499_:C2 _197_:1 1.955 *END *D_NET _198_ 4.925 *CONN -*I _499_/ZN O *D OAI211_X1 -*I _500_/A3 I *D NAND3_X1 +*I _499_:ZN O *D OAI211_X1 +*I _500_:A3 I *D NAND3_X1 *CAP 1 _198_:1 1.7525 2 _198_:2 1.76 *RES 1 _198_:2 _198_:1 4.2 -2 _499_/ZN _198_:1 2.815 -3 _500_/A3 _198_:2 2.845 +2 _499_:ZN _198_:1 2.815 +3 _500_:A3 _198_:2 2.845 *END *D_NET _199_ 10.775 *CONN -*I _500_/ZN O *D NAND3_X1 -*I _516_/A1 I *D NAND2_X1 +*I _500_:ZN O *D NAND3_X1 +*I _516_:A1 I *D NAND2_X1 *CAP 1 _199_:1 2.74 2 _199_:2 2.1 @@ -6178,16 +6178,16 @@ resp_val O 2 _199_:2 _199_:3 0.005 3 _199_:3 _199_:4 8.4 4 _199_:4 _199_:5 0.005 -5 _500_/ZN _199_:5 2.195 -6 _516_/A1 _199_:1 2.565 +5 _500_:ZN _199_:5 2.195 +6 _516_:A1 _199_:1 2.565 *END *D_NET _200_ 15.36 *CONN -*I _501_/ZN O *D XNOR2_X1 -*I _503_/A1 I *D AND2_X1 -*I _633_/B I *D XNOR2_X1 -*I _639_/A I *D OAI21_X1 +*I _501_:ZN O *D XNOR2_X1 +*I _503_:A1 I *D AND2_X1 +*I _633_:B I *D XNOR2_X1 +*I _639_:A I *D OAI21_X1 *CAP 1 _200_:1 2.035 2 _200_:2 1.05 @@ -6207,18 +6207,18 @@ resp_val O 6 _200_:4 _200_:8 4.2 7 _200_:8 _200_:9 0.005 8 _200_:9 _200_:6 4.2 -9 _501_/ZN _200_:5 3.765 -10 _503_/A1 _200_:6 0.785 -11 _633_/B _200_:1 3.945 -12 _639_/A _200_:7 1.245 +9 _501_:ZN _200_:5 3.765 +10 _503_:A1 _200_:6 0.785 +11 _633_:B _200_:1 3.945 +12 _639_:A _200_:7 1.245 *END *D_NET _201_ 16.57 *CONN -*I _502_/ZN O *D XNOR2_X1 -*I _503_/A2 I *D AND2_X1 -*I _643_/B I *D XNOR2_X1 -*I _650_/B1 I *D AOI21_X1 +*I _502_:ZN O *D XNOR2_X1 +*I _503_:A2 I *D AND2_X1 +*I _643_:B I *D XNOR2_X1 +*I _650_:B1 I *D AOI21_X1 *CAP 1 _201_:1 0.25 2 _201_:2 2.1 @@ -6234,18 +6234,18 @@ resp_val O 4 _201_:5 _201_:6 4.2 5 _201_:3 _201_:7 12.6 6 _201_:7 _201_:6 0.005 -7 _502_/ZN _201_:5 2.365 -8 _503_/A2 _201_:1 1.005 -9 _643_/B _201_:6 3.325 -10 _650_/B1 _201_:4 1.265 +7 _502_:ZN _201_:5 2.365 +8 _503_:A2 _201_:1 1.005 +9 _643_:B _201_:6 3.325 +10 _650_:B1 _201_:4 1.265 *END *D_NET _202_ 13.71 *CONN -*I _503_/ZN O *D AND2_X1 -*I _506_/A1 I *D AND3_X1 -*I _521_/A I *D OAI21_X1 -*I _649_/A2 I *D NAND2_X1 +*I _503_:ZN O *D AND2_X1 +*I _506_:A1 I *D AND3_X1 +*I _521_:A I *D OAI21_X1 +*I _649_:A2 I *D NAND2_X1 *CAP 1 _202_:1 4.035 2 _202_:2 1.5075 @@ -6259,21 +6259,21 @@ resp_val O 3 _202_:4 _202_:5 4.2 4 _202_:5 _202_:1 0.005 5 _202_:6 _202_:1 8.4 -6 _503_/ZN _202_:6 1.425 -7 _506_/A1 _202_:2 1.835 -8 _521_/A _202_:3 3.835 -9 _649_/A2 _202_:1 3.545 +6 _503_:ZN _202_:6 1.425 +7 _506_:A1 _202_:2 1.835 +8 _521_:A _202_:3 3.835 +9 _649_:A2 _202_:1 3.545 *END *D_NET _203_ 18.055 *CONN -*I _504_/ZN O *D XNOR2_X2 -*I _506_/A2 I *D AND3_X1 -*I _518_/A1 I *D AND3_X1 -*I _620_/A2 I *D AND3_X1 -*I _623_/A2 I *D NOR3_X1 -*I _624_/C1 I *D AOI211_X1 -*I _630_/B1 I *D AOI21_X1 +*I _504_:ZN O *D XNOR2_X2 +*I _506_:A2 I *D AND3_X1 +*I _518_:A1 I *D AND3_X1 +*I _620_:A2 I *D AND3_X1 +*I _623_:A2 I *D NOR3_X1 +*I _624_:C1 I *D AOI211_X1 +*I _630_:B1 I *D AOI21_X1 *CAP 1 _203_:1 0.8175 2 _203_:2 2.1 @@ -6295,22 +6295,22 @@ resp_val O 7 _203_:8 _203_:9 0.005 8 _203_:9 _203_:10 8.4 9 _203_:10 _203_:5 0.005 -10 _504_/ZN _203_:8 3.455 -11 _506_/A2 _203_:4 2.055 -12 _518_/A1 _203_:6 2.645 -13 _620_/A2 _203_:1 2.075 -14 _623_/A2 _203_:6 2.475 -15 _624_/C1 _203_:1 1.205 -16 _630_/B1 _203_:5 1.235 +10 _504_:ZN _203_:8 3.455 +11 _506_:A2 _203_:4 2.055 +12 _518_:A1 _203_:6 2.645 +13 _620_:A2 _203_:1 2.075 +14 _623_:A2 _203_:6 2.475 +15 _624_:C1 _203_:1 1.205 +16 _630_:B1 _203_:5 1.235 *END *D_NET _204_ 13.415 *CONN -*I _505_/ZN O *D XNOR2_X1 -*I _506_/A3 I *D AND3_X1 -*I _615_/B I *D XOR2_X1 -*I _620_/A3 I *D AND3_X1 -*I _621_/A2 I *D AND2_X1 +*I _505_:ZN O *D XNOR2_X1 +*I _506_:A3 I *D AND3_X1 +*I _615_:B I *D XOR2_X1 +*I _620_:A3 I *D AND3_X1 +*I _621_:A2 I *D AND2_X1 *CAP 1 _204_:1 1.6625 2 _204_:2 1.05 @@ -6330,19 +6330,19 @@ resp_val O 6 _204_:7 _204_:8 0.005 7 _204_:1 _204_:9 4.2 8 _204_:9 _204_:8 4.2 -9 _505_/ZN _204_:5 2.465 -10 _506_/A3 _204_:4 2.435 -11 _615_/B _204_:8 1.675 -12 _620_/A3 _204_:1 2.455 -13 _621_/A2 _204_:9 1.025 +9 _505_:ZN _204_:5 2.465 +10 _506_:A3 _204_:4 2.435 +11 _615_:B _204_:8 1.675 +12 _620_:A3 _204_:1 2.455 +13 _621_:A2 _204_:9 1.025 *END *D_NET _205_ 24.785 *CONN -*I _506_/ZN O *D AND3_X1 -*I _515_/A1 I *D AND2_X1 -*I _539_/A1 I *D NAND4_X1 -*I _647_/A2 I *D AND2_X1 +*I _506_:ZN O *D AND3_X1 +*I _515_:A1 I *D AND2_X1 +*I _539_:A1 I *D NAND4_X1 +*I _647_:A2 I *D AND2_X1 *CAP 1 _205_:1 0.955 2 _205_:2 4.2 @@ -6366,17 +6366,17 @@ resp_val O 8 _205_:9 _205_:10 0.005 9 _205_:10 _205_:11 8.4 10 _205_:11 _205_:6 0.005 -11 _506_/ZN _205_:9 4.605 -12 _515_/A1 _205_:1 3.825 -13 _539_/A1 _205_:5 1.775 -14 _647_/A2 _205_:6 1.585 +11 _506_:ZN _205_:9 4.605 +12 _515_:A1 _205_:1 3.825 +13 _539_:A1 _205_:5 1.775 +14 _647_:A2 _205_:6 1.585 *END *D_NET _206_ 11.425 *CONN -*I _507_/ZN O *D XNOR2_X1 -*I _509_/A1 I *D NAND2_X1 -*I _666_/A I *D INV_X1 +*I _507_:ZN O *D XNOR2_X1 +*I _509_:A1 I *D NAND2_X1 +*I _666_:A I *D INV_X1 *CAP 1 _206_:1 0.65 2 _206_:2 1.05 @@ -6392,17 +6392,17 @@ resp_val O 4 _206_:3 _206_:5 8.4 5 _206_:5 _206_:6 0.005 6 _206_:7 _206_:4 4.2 -7 _507_/ZN _206_:1 2.605 -8 _509_/A1 _206_:6 2.095 -9 _666_/A _206_:7 1.365 +7 _507_:ZN _206_:1 2.605 +8 _509_:A1 _206_:6 2.095 +9 _666_:A _206_:7 1.365 *END *D_NET _207_ 16.705 *CONN -*I _508_/ZN O *D XNOR2_X2 -*I _509_/A2 I *D NAND2_X1 -*I _529_/A1 I *D NAND3_X1 -*I _677_/B I *D XNOR2_X1 +*I _508_:ZN O *D XNOR2_X2 +*I _509_:A2 I *D NAND2_X1 +*I _529_:A1 I *D NAND3_X1 +*I _677_:B I *D XNOR2_X1 *CAP 1 _207_:1 2.785 2 _207_:2 2.1 @@ -6422,17 +6422,17 @@ resp_val O 6 _207_:5 _207_:7 4.2 7 _207_:7 _207_:8 0.005 8 _207_:8 _207_:9 4.2 -9 _508_/ZN _207_:9 1.095 -10 _509_/A2 _207_:1 2.745 -11 _529_/A1 _207_:3 3.885 -12 _677_/B _207_:6 0.505 +9 _508_:ZN _207_:9 1.095 +10 _509_:A2 _207_:1 2.745 +11 _529_:A1 _207_:3 3.885 +12 _677_:B _207_:6 0.505 *END *D_NET _208_ 9.895 *CONN -*I _509_/ZN O *D NAND2_X1 -*I _514_/A1 I *D NOR3_X1 -*I _536_/A1 I *D OR3_X1 +*I _509_:ZN O *D NAND2_X1 +*I _514_:A1 I *D NOR3_X1 +*I _536_:A1 I *D OR3_X1 *CAP 1 _208_:1 0.5 2 _208_:2 2.1 @@ -6448,17 +6448,17 @@ resp_val O 4 _208_:4 _208_:5 4.2 5 _208_:6 _208_:7 0.005 6 _208_:7 _208_:2 4.2 -7 _509_/ZN _208_:6 2.065 -8 _514_/A1 _208_:1 2.005 -9 _536_/A1 _208_:5 3.135 +7 _509_:ZN _208_:6 2.065 +8 _514_:A1 _208_:1 2.005 +9 _536_:A1 _208_:5 3.135 *END *D_NET _209_ 14.22 *CONN -*I _510_/ZN O *D XNOR2_X2 -*I _511_/A I *D INV_X1 -*I _660_/B I *D XNOR2_X1 -*I _667_/A1 I *D AOI22_X1 +*I _510_:ZN O *D XNOR2_X2 +*I _511_:A I *D INV_X1 +*I _660_:B I *D XNOR2_X1 +*I _667_:A1 I *D AOI22_X1 *CAP 1 _209_:1 2.1 2 _209_:2 1.995 @@ -6478,17 +6478,17 @@ resp_val O 6 _209_:7 _209_:8 4.2 7 _209_:8 _209_:9 0.005 8 _209_:6 _209_:1 4.2 -9 _510_/ZN _209_:9 2.575 -10 _511_/A _209_:2 3.785 -11 _660_/B _209_:6 2.385 -12 _667_/A1 _209_:3 2.915 +9 _510_:ZN _209_:9 2.575 +10 _511_:A _209_:2 3.785 +11 _660_:B _209_:6 2.385 +12 _667_:A1 _209_:3 2.915 *END *D_NET _210_ 10.18 *CONN -*I _511_/ZN O *D INV_X1 -*I _514_/A2 I *D NOR3_X1 -*I _665_/A2 I *D OR3_X1 +*I _511_:ZN O *D INV_X1 +*I _514_:A2 I *D NOR3_X1 +*I _665_:A2 I *D OR3_X1 *CAP 1 _210_:1 2.185 2 _210_:2 2.1 @@ -6502,16 +6502,16 @@ resp_val O 3 _210_:4 _210_:5 0.005 4 _210_:5 _210_:6 4.2 5 _210_:6 _210_:2 0.005 -6 _511_/ZN _210_:1 4.545 -7 _514_/A2 _210_:3 2.385 -8 _665_/A2 _210_:4 0.845 +6 _511_:ZN _210_:1 4.545 +7 _514_:A2 _210_:3 2.385 +8 _665_:A2 _210_:4 0.845 *END *D_NET _211_ 10.18 *CONN -*I _512_/ZN O *D XNOR2_X1 -*I _513_/A I *D INV_X1 -*I _652_/B I *D XNOR2_X1 +*I _512_:ZN O *D XNOR2_X1 +*I _513_:A I *D INV_X1 +*I _652_:B I *D XNOR2_X1 *CAP 1 _211_:1 2.1 2 _211_:2 1.765 @@ -6525,17 +6525,17 @@ resp_val O 3 _211_:4 _211_:5 4.2 4 _211_:5 _211_:1 0.005 5 _211_:6 _211_:1 4.2 -6 _512_/ZN _211_:2 2.865 -7 _513_/A _211_:3 2.025 -8 _652_/B _211_:6 2.885 +6 _512_:ZN _211_:2 2.865 +7 _513_:A _211_:3 2.025 +8 _652_:B _211_:6 2.885 *END *D_NET _212_ 12.655 *CONN -*I _513_/ZN O *D INV_X1 -*I _514_/A3 I *D NOR3_X1 -*I _657_/A2 I *D NOR2_X1 -*I _665_/A3 I *D OR3_X1 +*I _513_:ZN O *D INV_X1 +*I _514_:A3 I *D NOR3_X1 +*I _657_:A2 I *D NOR2_X1 +*I _665_:A3 I *D OR3_X1 *CAP 1 _212_:1 2.1 2 _212_:2 2.1 @@ -6553,18 +6553,18 @@ resp_val O 5 _212_:6 _212_:7 0.005 6 _212_:7 _212_:2 4.2 7 _212_:8 _212_:1 4.2 -8 _513_/ZN _212_:4 2.785 -9 _514_/A3 _212_:5 2.765 -10 _657_/A2 _212_:8 2.035 -11 _665_/A3 _212_:6 0.945 +8 _513_:ZN _212_:4 2.785 +9 _514_:A3 _212_:5 2.765 +10 _657_:A2 _212_:8 2.035 +11 _665_:A3 _212_:6 0.945 *END *D_NET _213_ 35.285 *CONN -*I _514_/ZN O *D NOR3_X1 -*I _515_/A2 I *D AND2_X1 -*I _527_/A2 I *D NAND2_X1 -*I _539_/A3 I *D NAND4_X1 +*I _514_:ZN O *D NOR3_X1 +*I _515_:A2 I *D AND2_X1 +*I _527_:A2 I *D NAND2_X1 +*I _539_:A3 I *D NAND4_X1 *CAP 1 _213_:1 0.4725 2 _213_:2 1.05 @@ -6584,16 +6584,16 @@ resp_val O 6 _213_:7 _213_:8 0.005 7 _213_:8 _213_:5 12.6 8 _213_:9 _213_:4 29.4 -9 _514_/ZN _213_:9 2.965 -10 _515_/A2 _213_:5 4.205 -11 _527_/A2 _213_:1 1.895 -12 _539_/A3 _213_:6 2.725 +9 _514_:ZN _213_:9 2.965 +10 _515_:A2 _213_:5 4.205 +11 _527_:A2 _213_:1 1.895 +12 _539_:A3 _213_:6 2.725 *END *D_NET _214_ 6.235 *CONN -*I _515_/ZN O *D AND2_X1 -*I _516_/A2 I *D NAND2_X1 +*I _515_:ZN O *D AND2_X1 +*I _516_:A2 I *D NAND2_X1 *CAP 1 _214_:1 0.4225 2 _214_:2 1.05 @@ -6605,14 +6605,14 @@ resp_val O 2 _214_:2 _214_:3 4.2 3 _214_:3 _214_:4 0.005 4 _214_:5 _214_:4 4.2 -5 _515_/ZN _214_:5 2.385 -6 _516_/A2 _214_:1 1.695 +5 _515_:ZN _214_:5 2.385 +6 _516_:A2 _214_:1 1.695 *END *D_NET _215_ 10.115 *CONN -*I _516_/ZN O *D NAND2_X1 -*I _530_/A2 I *D AND4_X1 +*I _516_:ZN O *D NAND2_X1 +*I _530_:A2 I *D AND4_X1 *CAP 1 _215_:1 2.525 2 _215_:2 2.1 @@ -6624,15 +6624,15 @@ resp_val O 2 _215_:2 _215_:3 0.005 3 _215_:3 _215_:4 8.4 4 _215_:4 _215_:5 0.005 -5 _516_/ZN _215_:5 1.735 -6 _530_/A2 _215_:1 1.705 +5 _516_:ZN _215_:5 1.735 +6 _530_:A2 _215_:1 1.705 *END *D_NET _216_ 7.89 *CONN -*I _517_/ZN O *D INV_X1 -*I _518_/A2 I *D AND3_X1 -*I _622_/A1 I *D NOR2_X1 +*I _517_:ZN O *D INV_X1 +*I _518_:A2 I *D AND3_X1 +*I _622_:A1 I *D NOR2_X1 *CAP 1 _216_:1 1.93 2 _216_:2 1.05 @@ -6644,15 +6644,15 @@ resp_val O 2 _216_:2 _216_:3 4.2 3 _216_:3 _216_:4 0.005 4 _216_:1 _216_:5 4.2 -5 _517_/ZN _216_:5 1.605 -6 _518_/A2 _216_:4 2.265 -7 _622_/A1 _216_:1 3.525 +5 _517_:ZN _216_:5 1.605 +6 _518_:A2 _216_:4 2.265 +7 _622_:A1 _216_:1 3.525 *END *D_NET _217_ 6.23 *CONN -*I _518_/ZN O *D AND3_X1 -*I _521_/B1 I *D OAI21_X1 +*I _518_:ZN O *D AND3_X1 +*I _521_:B1 I *D OAI21_X1 *CAP 1 _217_:1 0.1525 2 _217_:2 1.05 @@ -6664,15 +6664,15 @@ resp_val O 2 _217_:2 _217_:3 4.2 3 _217_:3 _217_:4 0.005 4 _217_:5 _217_:4 4.2 -5 _518_/ZN _217_:1 0.615 -6 _521_/B1 _217_:5 3.455 +5 _518_:ZN _217_:1 0.615 +6 _521_:B1 _217_:5 3.455 *END *D_NET _218_ 11.18 *CONN -*I _519_/ZN O *D INV_X1 -*I _520_/A1 I *D AND2_X1 -*I _629_/A1 I *D NOR2_X1 +*I _519_:ZN O *D INV_X1 +*I _520_:A1 I *D AND2_X1 +*I _629_:A1 I *D NOR2_X1 *CAP 1 _218_:1 0.705 2 _218_:2 2.1 @@ -6688,15 +6688,15 @@ resp_val O 4 _218_:4 _218_:5 4.2 5 _218_:6 _218_:7 0.005 6 _218_:7 _218_:2 4.2 -7 _519_/ZN _218_:6 3.665 -8 _520_/A1 _218_:5 3.285 -9 _629_/A1 _218_:1 2.825 +7 _519_:ZN _218_:6 3.665 +8 _520_:A1 _218_:5 3.285 +9 _629_:A1 _218_:1 2.825 *END *D_NET _219_ 6.14 *CONN -*I _520_/ZN O *D AND2_X1 -*I _521_/B2 I *D OAI21_X1 +*I _520_:ZN O *D AND2_X1 +*I _521_:B2 I *D OAI21_X1 *CAP 1 _219_:1 1.32 2 _219_:2 1.05 @@ -6708,14 +6708,14 @@ resp_val O 2 _219_:2 _219_:3 0.005 3 _219_:3 _219_:4 4.2 4 _219_:4 _219_:5 0.005 -5 _520_/ZN _219_:1 1.085 -6 _521_/B2 _219_:5 2.805 +5 _520_:ZN _219_:1 1.085 +6 _521_:B2 _219_:5 2.805 *END *D_NET _220_ 13.13 *CONN -*I _521_/ZN O *D OAI21_X1 -*I _526_/A I *D OAI21_X1 +*I _521_:ZN O *D OAI21_X1 +*I _526_:A I *D OAI21_X1 *CAP 1 _220_:1 0.7275 2 _220_:2 4.2 @@ -6727,16 +6727,16 @@ resp_val O 2 _220_:2 _220_:3 16.8 3 _220_:3 _220_:4 0.005 4 _220_:4 _220_:5 4.2 -5 _521_/ZN _220_:1 2.915 -6 _526_/A _220_:5 2.355 +5 _521_:ZN _220_:1 2.915 +6 _526_:A _220_:5 2.355 *END *D_NET _221_ 22.935 *CONN -*I _522_/ZN O *D INV_X1 -*I _523_/A1 I *D NOR2_X1 -*I _525_/A1 I *D AOI22_X1 -*I _646_/B1 I *D OAI21_X1 +*I _522_:ZN O *D INV_X1 +*I _523_:A1 I *D NOR2_X1 +*I _525_:A1 I *D AOI22_X1 +*I _646_:B1 I *D OAI21_X1 *CAP 1 _221_:1 1.7775 2 _221_:2 1.05 @@ -6754,17 +6754,17 @@ resp_val O 5 _221_:4 _221_:6 25.2 6 _221_:6 _221_:7 0.005 7 _221_:8 _221_:7 4.2 -8 _522_/ZN _221_:8 3.625 -9 _523_/A1 _221_:5 0.835 -10 _525_/A1 _221_:1 2.915 -11 _646_/B1 _221_:7 0.715 +8 _522_:ZN _221_:8 3.625 +9 _523_:A1 _221_:5 0.835 +10 _525_:A1 _221_:1 2.915 +11 _646_:B1 _221_:7 0.715 *END *D_NET _222_ 8.545 *CONN -*I _523_/ZN O *D NOR2_X1 -*I _526_/B1 I *D OAI21_X1 -*I _650_/A I *D AOI21_X1 +*I _523_:ZN O *D NOR2_X1 +*I _526_:B1 I *D OAI21_X1 +*I _650_:A I *D AOI21_X1 *CAP 1 _222_:1 2.1375 2 _222_:2 2.7825 @@ -6776,16 +6776,16 @@ resp_val O 2 _222_:3 _222_:4 0.005 3 _222_:4 _222_:5 4.2 4 _222_:5 _222_:1 0.005 -5 _523_/ZN _222_:1 0.155 -6 _526_/B1 _222_:2 2.735 -7 _650_/A _222_:3 1.615 +5 _523_:ZN _222_:1 0.155 +6 _526_:B1 _222_:2 2.735 +7 _650_:A _222_:3 1.615 *END *D_NET _223_ 6.91 *CONN -*I _524_/ZN O *D INV_X1 -*I _525_/B1 I *D AOI22_X1 -*I _640_/A1 I *D NOR2_X1 +*I _524_:ZN O *D INV_X1 +*I _525_:B1 I *D AOI22_X1 +*I _640_:A1 I *D NOR2_X1 *CAP 1 _223_:1 1.4625 2 _223_:2 1.05 @@ -6795,15 +6795,15 @@ resp_val O 1 _223_:1 _223_:2 0.005 2 _223_:2 _223_:3 4.2 3 _223_:3 _223_:4 0.005 -4 _524_/ZN _223_:1 3.845 -5 _525_/B1 _223_:4 3.775 -6 _640_/A1 _223_:1 2.015 +4 _524_:ZN _223_:1 3.845 +5 _525_:B1 _223_:4 3.775 +6 _640_:A1 _223_:1 2.015 *END *D_NET _224_ 10.41 *CONN -*I _525_/ZN O *D AOI22_X1 -*I _526_/B2 I *D OAI21_X1 +*I _525_:ZN O *D AOI22_X1 +*I _526_:B2 I *D OAI21_X1 *CAP 1 _224_:1 2.26 2 _224_:2 1.05 @@ -6817,41 +6817,41 @@ resp_val O 3 _224_:3 _224_:4 4.2 4 _224_:4 _224_:5 0.005 5 _224_:5 _224_:6 4.2 -6 _525_/ZN _224_:1 4.845 -7 _526_/B2 _224_:6 3.385 +6 _525_:ZN _224_:1 4.845 +7 _526_:B2 _224_:6 3.385 *END *D_NET _225_ 6.695 *CONN -*I _526_/ZN O *D OAI21_X1 -*I _527_/A1 I *D NAND2_X1 +*I _526_:ZN O *D OAI21_X1 +*I _527_:A1 I *D NAND2_X1 *CAP 1 _225_:1 2.7825 2 _225_:2 2.665 *RES 1 _225_:1 _225_:2 8.4 -2 _526_/ZN _225_:1 2.735 -3 _527_/A1 _225_:2 2.265 +2 _526_:ZN _225_:1 2.735 +3 _527_:A1 _225_:2 2.265 *END *D_NET _226_ 3.965 *CONN -*I _527_/ZN O *D NAND2_X1 -*I _530_/A3 I *D AND4_X1 +*I _527_:ZN O *D NAND2_X1 +*I _530_:A3 I *D AND4_X1 *CAP 1 _226_:1 1.4625 2 _226_:2 1.57 *RES 1 _226_:1 _226_:2 4.2 -2 _527_/ZN _226_:1 1.655 -3 _530_/A3 _226_:2 2.085 +2 _527_:ZN _226_:1 1.655 +3 _530_:A3 _226_:2 2.085 *END *D_NET _227_ 11.85 *CONN -*I _528_/ZN O *D INV_X1 -*I _529_/A2 I *D NAND3_X1 -*I _675_/A1 I *D NOR2_X1 +*I _528_:ZN O *D INV_X1 +*I _529_:A2 I *D NAND3_X1 +*I _675_:A1 I *D NOR2_X1 *CAP 1 _227_:1 0.4 2 _227_:2 2.1 @@ -6869,15 +6869,15 @@ resp_val O 5 _227_:6 _227_:7 4.2 6 _227_:7 _227_:8 0.005 7 _227_:8 _227_:2 4.2 -8 _528_/ZN _227_:6 1.805 -9 _529_/A2 _227_:5 3.505 -10 _675_/A1 _227_:1 1.605 +8 _528_:ZN _227_:6 1.805 +9 _529_:A2 _227_:5 3.505 +10 _675_:A1 _227_:1 1.605 *END *D_NET _228_ 19.215 *CONN -*I _529_/ZN O *D NAND3_X1 -*I _530_/A4 I *D AND4_X1 +*I _529_:ZN O *D NAND3_X1 +*I _530_:A4 I *D AND4_X1 *CAP 1 _228_:1 3.7425 2 _228_:2 3.15 @@ -6891,15 +6891,15 @@ resp_val O 3 _228_:3 _228_:4 4.2 4 _228_:4 _228_:5 0.005 5 _228_:5 _228_:6 16.8 -6 _529_/ZN _228_:1 2.375 -7 _530_/A4 _228_:6 2.465 +6 _529_:ZN _228_:1 2.375 +7 _530_:A4 _228_:6 2.465 *END *D_NET _229_ 16.06 *CONN -*I _530_/ZN O *D AND4_X1 -*I _537_/A1 I *D NAND4_X1 -*I _543_/B1 I *D AOI21_X1 +*I _530_:ZN O *D AND4_X1 +*I _537_:A1 I *D NAND4_X1 +*I _543_:B1 I *D AOI21_X1 *CAP 1 _229_:1 3.15 2 _229_:2 2.1 @@ -6917,16 +6917,16 @@ resp_val O 5 _229_:6 _229_:7 0.005 6 _229_:7 _229_:2 4.2 7 _229_:8 _229_:1 12.6 -8 _530_/ZN _229_:8 2.125 -9 _537_/A1 _229_:5 1.375 -10 _543_/B1 _229_:6 3.435 +8 _530_:ZN _229_:8 2.125 +9 _537_:A1 _229_:5 1.375 +10 _543_:B1 _229_:6 3.435 *END *D_NET _230_ 14.79 *CONN -*I _531_/ZN O *D AND2_X1 -*I _537_/A3 I *D NAND4_X1 -*I _553_/A I *D INV_X1 +*I _531_:ZN O *D AND2_X1 +*I _537_:A3 I *D NAND4_X1 +*I _553_:A I *D INV_X1 *CAP 1 _230_:1 1.05 2 _230_:2 4.2 @@ -6942,16 +6942,16 @@ resp_val O 4 _230_:5 _230_:1 4.2 5 _230_:6 _230_:7 0.005 6 _230_:7 _230_:2 8.4 -7 _531_/ZN _230_:6 4.505 -8 _537_/A3 _230_:4 2.485 -9 _553_/A _230_:5 1.605 +7 _531_:ZN _230_:6 4.505 +8 _537_:A3 _230_:4 2.485 +9 _553_:A _230_:5 1.605 *END *D_NET _231_ 10.335 *CONN -*I _532_/ZN O *D INV_X1 -*I _533_/A1 I *D NOR2_X1 -*I _535_/A1 I *D AOI22_X1 +*I _532_:ZN O *D INV_X1 +*I _533_:A1 I *D NOR2_X1 +*I _535_:A1 I *D AOI22_X1 *CAP 1 _231_:1 2.035 2 _231_:2 2.1 @@ -6965,15 +6965,15 @@ resp_val O 3 _231_:4 _231_:5 0.005 4 _231_:5 _231_:6 4.2 5 _231_:6 _231_:2 0.005 -6 _532_/ZN _231_:1 3.945 -7 _533_/A1 _231_:3 2.505 -8 _535_/A1 _231_:4 1.635 +6 _532_:ZN _231_:1 3.945 +7 _533_:A1 _231_:3 2.505 +8 _535_:A1 _231_:4 1.635 *END *D_NET _232_ 5.235 *CONN -*I _533_/ZN O *D NOR2_X1 -*I _536_/A2 I *D OR3_X1 +*I _533_:ZN O *D NOR2_X1 +*I _536_:A2 I *D OR3_X1 *CAP 1 _232_:1 0.6875 2 _232_:2 1.05 @@ -6983,15 +6983,15 @@ resp_val O 1 _232_:1 _232_:2 0.005 2 _232_:2 _232_:3 4.2 3 _232_:3 _232_:4 0.005 -4 _533_/ZN _232_:4 3.525 -5 _536_/A2 _232_:1 2.755 +4 _533_:ZN _232_:4 3.525 +5 _536_:A2 _232_:1 2.755 *END *D_NET _233_ 6.51 *CONN -*I _534_/ZN O *D INV_X1 -*I _535_/B1 I *D AOI22_X1 -*I _658_/A1 I *D NOR2_X1 +*I _534_:ZN O *D INV_X1 +*I _535_:B1 I *D AOI22_X1 +*I _658_:A1 I *D NOR2_X1 *CAP 1 _233_:1 1.655 2 _233_:2 1.275 @@ -7003,29 +7003,29 @@ resp_val O 2 _233_:2 _233_:3 0.005 3 _233_:3 _233_:4 4.2 4 _233_:4 _233_:5 0.005 -5 _534_/ZN _233_:5 1.305 -6 _535_/B1 _233_:2 0.905 -7 _658_/A1 _233_:1 2.425 +5 _534_:ZN _233_:5 1.305 +6 _535_:B1 _233_:2 0.905 +7 _658_:A1 _233_:1 2.425 *END *D_NET _234_ 3.83 *CONN -*I _535_/ZN O *D AOI22_X1 -*I _536_/A3 I *D OR3_X1 +*I _535_:ZN O *D AOI22_X1 +*I _536_:A3 I *D OR3_X1 *CAP 1 _234_:1 1.3225 2 _234_:2 1.6425 *RES 1 _234_:1 _234_:2 4.2 -2 _535_/ZN _234_:1 1.095 -3 _536_/A3 _234_:2 2.375 +2 _535_:ZN _234_:1 1.095 +3 _536_:A3 _234_:2 2.375 *END *D_NET _235_ 31.305 *CONN -*I _536_/ZN O *D OR3_X1 -*I _537_/A4 I *D NAND4_X1 -*I _543_/B2 I *D AOI21_X1 +*I _536_:ZN O *D OR3_X1 +*I _537_:A4 I *D NAND4_X1 +*I _543_:B2 I *D AOI21_X1 *CAP 1 _235_:1 11.55 2 _235_:2 1.765 @@ -7039,15 +7039,15 @@ resp_val O 3 _235_:4 _235_:5 8.4 4 _235_:5 _235_:1 0.005 5 _235_:6 _235_:1 42 -6 _536_/ZN _235_:6 2.405 -7 _537_/A4 _235_:2 2.865 -8 _543_/B2 _235_:3 2.755 +6 _536_:ZN _235_:6 2.405 +7 _537_:A4 _235_:2 2.865 +8 _543_:B2 _235_:3 2.755 *END *D_NET _236_ 34.07 *CONN -*I _537_/ZN O *D NAND4_X1 -*I _547_/B I *D OAI211_X1 +*I _537_:ZN O *D NAND4_X1 +*I _547_:B I *D OAI211_X1 *CAP 1 _236_:1 5.7825 2 _236_:2 5.25 @@ -7059,15 +7059,15 @@ resp_val O 2 _236_:2 _236_:3 0.005 3 _236_:3 _236_:4 42 4 _236_:4 _236_:5 0.005 -5 _537_/ZN _236_:1 2.135 -6 _547_/B _236_:5 3.015 +5 _537_:ZN _236_:1 2.135 +6 _547_:B _236_:5 3.015 *END *D_NET _237_ 11.965 *CONN -*I _538_/ZN O *D AND2_X1 -*I _539_/A2 I *D NAND4_X1 -*I _611_/A2 I *D NAND2_X1 +*I _538_:ZN O *D AND2_X1 +*I _539_:A2 I *D NAND4_X1 +*I _611_:A2 I *D NAND2_X1 *CAP 1 _237_:1 0.585 2 _237_:2 2.1 @@ -7083,15 +7083,15 @@ resp_val O 4 _237_:3 _237_:5 4.2 5 _237_:5 _237_:6 0.005 6 _237_:7 _237_:6 4.2 -7 _538_/ZN _237_:4 2.285 -8 _539_/A2 _237_:1 2.345 -9 _611_/A2 _237_:7 2.515 +7 _538_:ZN _237_:4 2.285 +8 _539_:A2 _237_:1 2.345 +9 _611_:A2 _237_:7 2.515 *END *D_NET _238_ 5.6 *CONN -*I _539_/ZN O *D NAND4_X1 -*I _542_/A1 I *D NOR3_X1 +*I _539_:ZN O *D NAND4_X1 +*I _542_:A1 I *D NOR3_X1 *CAP 1 _238_:1 0.7675 2 _238_:2 1.05 @@ -7101,16 +7101,16 @@ resp_val O 1 _238_:1 _238_:2 0.005 2 _238_:2 _238_:3 4.2 3 _238_:3 _238_:4 0.005 -4 _539_/ZN _238_:4 3.935 -5 _542_/A1 _238_:1 3.075 +4 _539_:ZN _238_:4 3.935 +5 _542_:A1 _238_:1 3.075 *END *D_NET _239_ 11.94 *CONN -*I _540_/ZN O *D XNOR2_X2 -*I _541_/A I *D INV_X1 -*I _557_/A I *D XOR2_X1 -*I _562_/B1 I *D AOI21_X1 +*I _540_:ZN O *D XNOR2_X2 +*I _541_:A I *D INV_X1 +*I _557_:A I *D XOR2_X1 +*I _562_:B1 I *D AOI21_X1 *CAP 1 _239_:1 2.4125 2 _239_:2 3.7475 @@ -7124,29 +7124,29 @@ resp_val O 3 _239_:4 _239_:5 0.005 4 _239_:5 _239_:6 4.2 5 _239_:6 _239_:2 0.005 -6 _540_/ZN _239_:4 1.095 -7 _541_/A _239_:1 1.255 -8 _557_/A _239_:3 2.355 -9 _562_/B1 _239_:2 2.395 +6 _540_:ZN _239_:4 1.095 +7 _541_:A _239_:1 1.255 +8 _557_:A _239_:3 2.355 +9 _562_:B1 _239_:2 2.395 *END *D_NET _240_ 7.285 *CONN -*I _541_/ZN O *D INV_X1 -*I _542_/A3 I *D NOR3_X1 +*I _541_:ZN O *D INV_X1 +*I _542_:A3 I *D NOR3_X1 *CAP 1 _240_:1 3.0575 2 _240_:2 2.685 *RES 1 _240_:1 _240_:2 8.4 -2 _541_/ZN _240_:2 2.345 -3 _542_/A3 _240_:1 3.835 +2 _541_:ZN _240_:2 2.345 +3 _542_:A3 _240_:1 3.835 *END *D_NET _241_ 5.425 *CONN -*I _542_/ZN O *D NOR3_X1 -*I _543_/A I *D AOI21_X1 +*I _542_:ZN O *D NOR3_X1 +*I _543_:A I *D AOI21_X1 *CAP 1 _241_:1 0.98 2 _241_:2 1.05 @@ -7156,15 +7156,15 @@ resp_val O 1 _241_:1 _241_:2 0.005 2 _241_:2 _241_:3 4.2 3 _241_:3 _241_:4 0.005 -4 _542_/ZN _241_:4 2.735 -5 _543_/A _241_:1 3.925 +4 _542_:ZN _241_:4 2.735 +5 _543_:A _241_:1 3.925 *END *D_NET _242_ 7.165 *CONN -*I _543_/ZN O *D AOI21_X1 -*I _544_/A1 I *D NAND2_X1 -*I _554_/A1 I *D NOR2_X2 +*I _543_:ZN O *D AOI21_X1 +*I _544_:A1 I *D NAND2_X1 +*I _554_:A1 I *D NOR2_X2 *CAP 1 _242_:1 0.6125 2 _242_:2 1.05 @@ -7176,16 +7176,16 @@ resp_val O 2 _242_:2 _242_:3 4.2 3 _242_:3 _242_:4 0.005 4 _242_:5 _242_:4 4.2 -5 _543_/ZN _242_:4 2.825 -6 _544_/A1 _242_:1 2.455 -7 _554_/A1 _242_:5 0.665 +5 _543_:ZN _242_:4 2.825 +6 _544_:A1 _242_:1 2.455 +7 _554_:A1 _242_:5 0.665 *END *D_NET _243_ 8.665 *CONN -*I _544_/ZN O *D NAND2_X1 -*I _545_/A1 I *D OR2_X2 -*I _684_/A1 I *D NAND2_X2 +*I _544_:ZN O *D NAND2_X1 +*I _545_:A1 I *D OR2_X2 +*I _684_:A1 I *D NAND2_X2 *CAP 1 _243_:1 2.3275 2 _243_:2 1.05 @@ -7197,21 +7197,21 @@ resp_val O 2 _243_:2 _243_:3 0.005 3 _243_:3 _243_:4 4.2 4 _243_:4 _243_:5 0.005 -5 _544_/ZN _243_:5 3.825 -6 _545_/A1 _243_:1 3.525 -7 _684_/A1 _243_:1 1.595 +5 _544_:ZN _243_:5 3.825 +6 _545_:A1 _243_:1 3.525 +7 _684_:A1 _243_:1 1.595 *END *D_NET _244_ 82.485 *CONN -*I _545_/ZN O *D OR2_X2 -*I _546_/A I *D BUF_X2 -*I _617_/C1 I *D OAI211_X1 -*I _626_/C1 I *D OAI211_X1 -*I _635_/C1 I *D OAI211_X1 -*I _655_/C1 I *D OAI211_X1 -*I _663_/C2 I *D OAI211_X1 -*I _673_/C2 I *D OAI211_X1 +*I _545_:ZN O *D OR2_X2 +*I _546_:A I *D BUF_X2 +*I _617_:C1 I *D OAI211_X1 +*I _626_:C1 I *D OAI211_X1 +*I _635_:C1 I *D OAI211_X1 +*I _655_:C1 I *D OAI211_X1 +*I _663_:C2 I *D OAI211_X1 +*I _673_:C2 I *D OAI211_X1 *CAP 1 _244_:1 1.2175 2 _244_:2 7.35 @@ -7253,29 +7253,29 @@ resp_val O 17 _244_:19 _244_:16 12.6 18 _244_:19 _244_:20 0.005 19 _244_:20 _244_:18 4.2 -20 _545_/ZN _244_:1 4.875 -21 _546_/A _244_:4 4.185 -22 _617_/C1 _244_:11 2.985 -23 _626_/C1 _244_:13 1.765 -24 _635_/C1 _244_:16 2.495 -25 _655_/C1 _244_:9 2.095 -26 _663_/C2 _244_:10 0.965 -27 _673_/C2 _244_:17 2.845 +20 _545_:ZN _244_:1 4.875 +21 _546_:A _244_:4 4.185 +22 _617_:C1 _244_:11 2.985 +23 _626_:C1 _244_:13 1.765 +24 _635_:C1 _244_:16 2.495 +25 _655_:C1 _244_:9 2.095 +26 _663_:C2 _244_:10 0.965 +27 _673_:C2 _244_:17 2.845 *END *D_NET _245_ 101.86 *CONN -*I _546_/Z O *D BUF_X2 -*I _547_/C1 I *D OAI211_X1 -*I _559_/C1 I *D OAI211_X1 -*I _565_/C1 I *D OAI211_X1 -*I _574_/C1 I *D OAI211_X1 -*I _583_/C1 I *D OAI211_X1 -*I _591_/C1 I *D OAI211_X1 -*I _599_/C1 I *D OAI211_X1 -*I _608_/C1 I *D OAI211_X1 -*I _638_/B1 I *D OAI21_X1 -*I _680_/B1 I *D OAI21_X1 +*I _546_:Z O *D BUF_X2 +*I _547_:C1 I *D OAI211_X1 +*I _559_:C1 I *D OAI211_X1 +*I _565_:C1 I *D OAI211_X1 +*I _574_:C1 I *D OAI211_X1 +*I _583_:C1 I *D OAI211_X1 +*I _591_:C1 I *D OAI211_X1 +*I _599_:C1 I *D OAI211_X1 +*I _608_:C1 I *D OAI211_X1 +*I _638_:B1 I *D OAI21_X1 +*I _680_:B1 I *D OAI21_X1 *CAP 1 _245_:1 3.15 2 _245_:2 3.7775 @@ -7331,23 +7331,23 @@ resp_val O 24 _245_:26 _245_:27 8.4 25 _245_:27 _245_:22 0.005 26 _245_:25 _245_:14 16.8 -27 _546_/Z _245_:25 4.475 -28 _547_/C1 _245_:2 2.515 -29 _559_/C1 _245_:7 2.455 -30 _565_/C1 _245_:8 3.155 -31 _574_/C1 _245_:13 1.485 -32 _583_/C1 _245_:12 0.815 -33 _591_/C1 _245_:17 2.965 -34 _599_/C1 _245_:9 3.985 -35 _608_/C1 _245_:3 0.355 -36 _638_/B1 _245_:18 4.035 -37 _680_/B1 _245_:22 1.135 +27 _546_:Z _245_:25 4.475 +28 _547_:C1 _245_:2 2.515 +29 _559_:C1 _245_:7 2.455 +30 _565_:C1 _245_:8 3.155 +31 _574_:C1 _245_:13 1.485 +32 _583_:C1 _245_:12 0.815 +33 _591_:C1 _245_:17 2.965 +34 _599_:C1 _245_:9 3.985 +35 _608_:C1 _245_:3 0.355 +36 _638_:B1 _245_:18 4.035 +37 _680_:B1 _245_:22 1.135 *END *D_NET _246_ 7.545 *CONN -*I _547_/ZN O *D OAI211_X1 -*I _551_/B I *D MUX2_X1 +*I _547_:ZN O *D OAI211_X1 +*I _551_:B I *D MUX2_X1 *CAP 1 _246_:1 1.7225 2 _246_:2 1.05 @@ -7359,14 +7359,14 @@ resp_val O 2 _246_:2 _246_:3 0.005 3 _246_:3 _246_:4 4.2 4 _246_:4 _246_:5 0.005 -5 _547_/ZN _246_:1 2.695 -6 _551_/B _246_:5 4.005 +5 _547_:ZN _246_:1 2.695 +6 _551_:B _246_:5 4.005 *END *D_NET _247_ 3.825 *CONN -*I _548_/ZN O *D OR2_X1 -*I _549_/A I *D BUF_X2 +*I _548_:ZN O *D OR2_X1 +*I _549_:A I *D BUF_X2 *CAP 1 _247_:1 0.5475 2 _247_:2 1.05 @@ -7376,22 +7376,22 @@ resp_val O 1 _247_:1 _247_:2 0.005 2 _247_:2 _247_:3 4.2 3 _247_:3 _247_:4 0.005 -4 _548_/ZN _247_:4 1.265 -5 _549_/A _247_:1 2.195 +4 _548_:ZN _247_:4 1.265 +5 _549_:A _247_:1 2.195 *END *D_NET _248_ 137.53 *CONN -*I _549_/Z O *D BUF_X2 -*I _550_/A I *D BUF_X2 -*I _600_/S I *D MUX2_X1 -*I _609_/S I *D MUX2_X1 -*I _618_/S I *D MUX2_X1 -*I _627_/S I *D MUX2_X1 -*I _636_/S I *D MUX2_X1 -*I _656_/S I *D MUX2_X1 -*I _664_/S I *D MUX2_X1 -*I _674_/S I *D MUX2_X1 +*I _549_:Z O *D BUF_X2 +*I _550_:A I *D BUF_X2 +*I _600_:S I *D MUX2_X1 +*I _609_:S I *D MUX2_X1 +*I _618_:S I *D MUX2_X1 +*I _627_:S I *D MUX2_X1 +*I _636_:S I *D MUX2_X1 +*I _656_:S I *D MUX2_X1 +*I _664_:S I *D MUX2_X1 +*I _674_:S I *D MUX2_X1 *CAP 1 _248_:1 0.3825 2 _248_:2 2.1 @@ -7457,31 +7457,31 @@ resp_val O 29 _248_:30 _248_:31 4.2 30 _248_:31 _248_:32 0.005 31 _248_:26 _248_:32 21 -32 _549_/Z _248_:14 1.375 -33 _550_/A _248_:1 1.535 -34 _600_/S _248_:5 2.655 -35 _609_/S _248_:13 1.055 -36 _618_/S _248_:17 2.595 -37 _627_/S _248_:21 1.075 -38 _636_/S _248_:25 2.755 -39 _656_/S _248_:10 4.115 -40 _664_/S _248_:6 3.775 -41 _674_/S _248_:26 2.175 +32 _549_:Z _248_:14 1.375 +33 _550_:A _248_:1 1.535 +34 _600_:S _248_:5 2.655 +35 _609_:S _248_:13 1.055 +36 _618_:S _248_:17 2.595 +37 _627_:S _248_:21 1.075 +38 _636_:S _248_:25 2.755 +39 _656_:S _248_:10 4.115 +40 _664_:S _248_:6 3.775 +41 _674_:S _248_:26 2.175 *END *D_NET _249_ 102.535 *CONN -*I _550_/Z O *D BUF_X2 -*I _551_/S I *D MUX2_X1 -*I _560_/S I *D MUX2_X1 -*I _566_/S I *D MUX2_X1 -*I _575_/S I *D MUX2_X1 -*I _584_/S I *D MUX2_X1 -*I _592_/S I *D MUX2_X1 -*I _645_/A I *D OAI21_X1 -*I _646_/B2 I *D OAI21_X1 -*I _681_/A I *D OAI21_X1 -*I _682_/B2 I *D OAI21_X1 +*I _550_:Z O *D BUF_X2 +*I _551_:S I *D MUX2_X1 +*I _560_:S I *D MUX2_X1 +*I _566_:S I *D MUX2_X1 +*I _575_:S I *D MUX2_X1 +*I _584_:S I *D MUX2_X1 +*I _592_:S I *D MUX2_X1 +*I _645_:A I *D OAI21_X1 +*I _646_:B2 I *D OAI21_X1 +*I _681_:A I *D OAI21_X1 +*I _682_:B2 I *D OAI21_X1 *CAP 1 _249_:1 2.4375 2 _249_:2 2.1 @@ -7539,23 +7539,23 @@ resp_val O 25 _249_:15 _249_:27 12.6 26 _249_:27 _249_:28 0.005 27 _249_:11 _249_:28 4.2 -28 _550_/Z _249_:22 3.095 -29 _551_/S _249_:17 2.755 -30 _560_/S _249_:1 1.355 -31 _566_/S _249_:5 2.515 -32 _575_/S _249_:19 3.675 -33 _584_/S _249_:25 2.975 -34 _592_/S _249_:9 1.515 -35 _645_/A _249_:11 2.585 -36 _646_/B2 _249_:10 1.345 -37 _681_/A _249_:16 0.665 -38 _682_/B2 _249_:12 2.045 +28 _550_:Z _249_:22 3.095 +29 _551_:S _249_:17 2.755 +30 _560_:S _249_:1 1.355 +31 _566_:S _249_:5 2.515 +32 _575_:S _249_:19 3.675 +33 _584_:S _249_:25 2.975 +34 _592_:S _249_:9 1.515 +35 _645_:A _249_:11 2.585 +36 _646_:B2 _249_:10 1.345 +37 _681_:A _249_:16 0.665 +38 _682_:B2 _249_:12 2.045 *END *D_NET _250_ 19.395 *CONN -*I _552_/ZN O *D OAI21_X1 -*I _559_/A I *D OAI211_X1 +*I _552_:ZN O *D OAI21_X1 +*I _559_:A I *D OAI211_X1 *CAP 1 _250_:1 6.3 2 _250_:2 6.825 @@ -7567,32 +7567,32 @@ resp_val O 2 _250_:1 _250_:3 0.005 3 _250_:3 _250_:4 8.4 4 _250_:4 _250_:5 0.005 -5 _552_/ZN _250_:5 3.095 -6 _559_/A _250_:2 2.105 +5 _552_:ZN _250_:5 3.095 +6 _559_:A _250_:2 2.105 *END *D_NET _251_ 3.96 *CONN -*I _553_/ZN O *D INV_X1 -*I _554_/A2 I *D NOR2_X2 +*I _553_:ZN O *D INV_X1 +*I _554_:A2 I *D NOR2_X2 *CAP 1 _251_:1 1.64 2 _251_:2 1.39 *RES 1 _251_:2 _251_:1 4.2 -2 _553_/ZN _251_:1 2.365 -3 _554_/A2 _251_:2 1.365 +2 _553_:ZN _251_:1 2.365 +3 _554_:A2 _251_:2 1.365 *END *D_NET _252_ 66.405 *CONN -*I _554_/ZN O *D NOR2_X2 -*I _555_/A I *D CLKBUF_X2 -*I _625_/A2 I *D NAND2_X1 -*I _634_/A1 I *D NAND2_X1 -*I _653_/A2 I *D NAND2_X1 -*I _661_/A2 I *D NAND2_X1 -*I _671_/A2 I *D NAND2_X1 +*I _554_:ZN O *D NOR2_X2 +*I _555_:A I *D CLKBUF_X2 +*I _625_:A2 I *D NAND2_X1 +*I _634_:A1 I *D NAND2_X1 +*I _653_:A2 I *D NAND2_X1 +*I _661_:A2 I *D NAND2_X1 +*I _671_:A2 I *D NAND2_X1 *CAP 1 _252_:1 0.5225 2 _252_:2 2.1 @@ -7634,28 +7634,28 @@ resp_val O 17 _252_:20 _252_:6 16.8 18 _252_:19 _252_:4 25.2 19 _252_:4 _252_:16 12.6 -20 _554_/ZN _252_:15 1.465 -21 _555_/A _252_:11 1.135 -22 _625_/A2 _252_:16 2.315 -23 _634_/A1 _252_:1 2.095 -24 _653_/A2 _252_:9 3.825 -25 _661_/A2 _252_:10 2.655 -26 _671_/A2 _252_:19 1.755 +20 _554_:ZN _252_:15 1.465 +21 _555_:A _252_:11 1.135 +22 _625_:A2 _252_:16 2.315 +23 _634_:A1 _252_:1 2.095 +24 _653_:A2 _252_:9 3.825 +25 _661_:A2 _252_:10 2.655 +26 _671_:A2 _252_:19 1.755 *END *D_NET _253_ 113.44 *CONN -*I _555_/Z O *D CLKBUF_X2 -*I _558_/A1 I *D NAND2_X1 -*I _564_/A1 I *D NAND2_X1 -*I _573_/A1 I *D NAND2_X1 -*I _582_/A1 I *D NAND2_X1 -*I _590_/A1 I *D NAND2_X1 -*I _598_/A1 I *D NAND2_X1 -*I _607_/A1 I *D NAND2_X1 -*I _616_/A1 I *D NAND2_X1 -*I _644_/A2 I *D AND2_X1 -*I _678_/A2 I *D AND2_X1 +*I _555_:Z O *D CLKBUF_X2 +*I _558_:A1 I *D NAND2_X1 +*I _564_:A1 I *D NAND2_X1 +*I _573_:A1 I *D NAND2_X1 +*I _582_:A1 I *D NAND2_X1 +*I _590_:A1 I *D NAND2_X1 +*I _598_:A1 I *D NAND2_X1 +*I _607_:A1 I *D NAND2_X1 +*I _616_:A1 I *D NAND2_X1 +*I _644_:A2 I *D AND2_X1 +*I _678_:A2 I *D AND2_X1 *CAP 1 _253_:1 0.36 2 _253_:2 5.25 @@ -7717,24 +7717,24 @@ resp_val O 27 _253_:29 _253_:30 0.005 28 _253_:30 _253_:24 4.2 29 _253_:27 _253_:17 16.8 -30 _555_/Z _253_:14 2.455 -31 _558_/A1 _253_:18 3.135 -32 _564_/A1 _253_:21 1.785 -33 _573_/A1 _253_:23 2.535 -34 _582_/A1 _253_:4 0.645 -35 _590_/A1 _253_:9 3.085 -36 _598_/A1 _253_:1 1.445 -37 _607_/A1 _253_:5 3.245 -38 _616_/A1 _253_:10 0.905 -39 _644_/A2 _253_:24 3.365 -40 _678_/A2 _253_:27 2.735 +30 _555_:Z _253_:14 2.455 +31 _558_:A1 _253_:18 3.135 +32 _564_:A1 _253_:21 1.785 +33 _573_:A1 _253_:23 2.535 +34 _582_:A1 _253_:4 0.645 +35 _590_:A1 _253_:9 3.085 +36 _598_:A1 _253_:1 1.445 +37 _607_:A1 _253_:5 3.245 +38 _616_:A1 _253_:10 0.905 +39 _644_:A2 _253_:24 3.365 +40 _678_:A2 _253_:27 2.735 *END *D_NET _254_ 6.99 *CONN -*I _556_/ZN O *D NAND2_X1 -*I _557_/B I *D XOR2_X1 -*I _562_/B2 I *D AOI21_X1 +*I _556_:ZN O *D NAND2_X1 +*I _557_:B I *D XOR2_X1 +*I _562_:B2 I *D AOI21_X1 *CAP 1 _254_:1 1.8175 2 _254_:2 1.2425 @@ -7746,15 +7746,15 @@ resp_val O 2 _254_:2 _254_:3 0.005 3 _254_:3 _254_:4 4.2 4 _254_:4 _254_:5 0.005 -5 _556_/ZN _254_:5 1.745 -6 _557_/B _254_:2 0.775 -7 _562_/B2 _254_:1 3.075 +5 _556_:ZN _254_:5 1.745 +6 _557_:B _254_:2 0.775 +7 _562_:B2 _254_:1 3.075 *END *D_NET _255_ 7.285 *CONN -*I _558_/ZN O *D NAND2_X1 -*I _559_/B I *D OAI211_X1 +*I _558_:ZN O *D NAND2_X1 +*I _559_:B I *D OAI211_X1 *CAP 1 _255_:1 1.125 2 _255_:2 1.05 @@ -7766,14 +7766,14 @@ resp_val O 2 _255_:2 _255_:3 4.2 3 _255_:3 _255_:4 0.005 4 _255_:5 _255_:4 4.2 -5 _558_/ZN _255_:1 4.505 -6 _559_/B _255_:5 1.675 +5 _558_:ZN _255_:1 4.505 +6 _559_:B _255_:5 1.675 *END *D_NET _256_ 6.83 *CONN -*I _559_/ZN O *D OAI211_X1 -*I _560_/B I *D MUX2_X1 +*I _559_:ZN O *D OAI211_X1 +*I _560_:B I *D MUX2_X1 *CAP 1 _256_:1 0.5075 2 _256_:2 1.05 @@ -7785,14 +7785,14 @@ resp_val O 2 _256_:2 _256_:3 4.2 3 _256_:3 _256_:4 0.005 4 _256_:5 _256_:4 4.2 -5 _559_/ZN _256_:5 3.235 -6 _560_/B _256_:1 2.035 +5 _559_:ZN _256_:5 3.235 +6 _560_:B _256_:1 2.035 *END *D_NET _257_ 11.965 *CONN -*I _561_/ZN O *D OAI21_X1 -*I _565_/A I *D OAI211_X1 +*I _561_:ZN O *D OAI21_X1 +*I _565_:A I *D OAI211_X1 *CAP 1 _257_:1 2.1325 2 _257_:2 1.05 @@ -7804,15 +7804,15 @@ resp_val O 2 _257_:2 _257_:3 0.005 3 _257_:3 _257_:4 12.6 4 _257_:4 _257_:5 0.005 -5 _561_/ZN _257_:1 4.335 -6 _565_/A _257_:5 2.805 +5 _561_:ZN _257_:1 4.335 +6 _565_:A _257_:5 2.805 *END *D_NET _258_ 14.335 *CONN -*I _562_/ZN O *D AOI21_X1 -*I _563_/A I *D XNOR2_X1 -*I _568_/A I *D INV_X1 +*I _562_:ZN O *D AOI21_X1 +*I _563_:A I *D XNOR2_X1 +*I _568_:A I *D INV_X1 *CAP 1 _258_:1 2.1 2 _258_:2 2.8275 @@ -7830,40 +7830,40 @@ resp_val O 5 _258_:6 _258_:7 4.2 6 _258_:7 _258_:8 0.005 7 _258_:8 _258_:3 4.2 -8 _562_/ZN _258_:6 2.325 -9 _563_/A _258_:2 2.915 -10 _568_/A _258_:5 2.445 +8 _562_:ZN _258_:6 2.325 +9 _563_:A _258_:2 2.915 +10 _568_:A _258_:5 2.445 *END *D_NET _259_ 4.14 *CONN -*I _564_/ZN O *D NAND2_X1 -*I _565_/B I *D OAI211_X1 +*I _564_:ZN O *D NAND2_X1 +*I _565_:B I *D OAI211_X1 *CAP 1 _259_:1 1.4775 2 _259_:2 1.6425 *RES 1 _259_:1 _259_:2 4.2 -2 _564_/ZN _259_:1 1.715 -3 _565_/B _259_:2 2.375 +2 _564_:ZN _259_:1 1.715 +3 _565_:B _259_:2 2.375 *END *D_NET _260_ 2.945 *CONN -*I _565_/ZN O *D OAI211_X1 -*I _566_/B I *D MUX2_X1 +*I _565_:ZN O *D OAI211_X1 +*I _566_:B I *D MUX2_X1 *CAP 1 _260_:1 1.4725 *RES 1 _260_:1 _260_:1 0.005 -2 _565_/ZN _260_:1 4.635 -3 _566_/B _260_:1 1.265 +2 _565_:ZN _260_:1 4.635 +3 _566_:B _260_:1 1.265 *END *D_NET _261_ 6.59 *CONN -*I _567_/ZN O *D OAI21_X1 -*I _574_/A I *D OAI211_X1 +*I _567_:ZN O *D OAI21_X1 +*I _574_:A I *D OAI211_X1 *CAP 1 _261_:1 1.3325 2 _261_:2 1.05 @@ -7875,15 +7875,15 @@ resp_val O 2 _261_:2 _261_:3 0.005 3 _261_:3 _261_:4 4.2 4 _261_:4 _261_:5 0.005 -5 _567_/ZN _261_:5 3.655 -6 _574_/A _261_:1 1.135 +5 _567_:ZN _261_:5 3.655 +6 _574_:A _261_:1 1.135 *END *D_NET _262_ 14.25 *CONN -*I _568_/ZN O *D INV_X1 -*I _569_/A1 I *D AND2_X1 -*I _579_/A1 I *D NAND2_X1 +*I _568_:ZN O *D INV_X1 +*I _569_:A1 I *D AND2_X1 +*I _579_:A1 I *D NAND2_X1 *CAP 1 _262_:1 0.45 2 _262_:2 1.05 @@ -7897,15 +7897,15 @@ resp_val O 3 _262_:3 _262_:4 0.005 4 _262_:4 _262_:5 8.4 5 _262_:6 _262_:4 8.4 -6 _568_/ZN _262_:1 1.805 -7 _569_/A1 _262_:5 3.865 -8 _579_/A1 _262_:6 1.845 +6 _568_:ZN _262_:1 1.805 +7 _569_:A1 _262_:5 3.865 +8 _579_:A1 _262_:6 1.845 *END *D_NET _263_ 4.22 *CONN -*I _569_/ZN O *D AND2_X1 -*I _571_/A1 I *D NOR2_X1 +*I _569_:ZN O *D AND2_X1 +*I _571_:A1 I *D NOR2_X1 *CAP 1 _263_:1 0.415 2 _263_:2 1.05 @@ -7915,29 +7915,29 @@ resp_val O 1 _263_:1 _263_:2 0.005 2 _263_:2 _263_:3 4.2 3 _263_:3 _263_:4 0.005 -4 _569_/ZN _263_:1 1.665 -5 _571_/A1 _263_:4 2.585 +4 _569_:ZN _263_:1 1.665 +5 _571_:A1 _263_:4 2.585 *END *D_NET _264_ 5.075 *CONN -*I _570_/ZN O *D AND2_X1 -*I _571_/A2 I *D NOR2_X1 -*I _577_/A2 I *D AND2_X1 +*I _570_:ZN O *D AND2_X1 +*I _571_:A2 I *D NOR2_X1 +*I _577_:A2 I *D AND2_X1 *CAP 1 _264_:1 2.0475 2 _264_:2 1.54 *RES 1 _264_:2 _264_:1 4.2 -2 _570_/ZN _264_:1 2.065 -3 _571_/A2 _264_:1 1.935 -4 _577_/A2 _264_:2 1.965 +2 _570_:ZN _264_:1 2.065 +3 _571_:A2 _264_:1 1.935 +4 _577_:A2 _264_:2 1.965 *END *D_NET _265_ 4.655 *CONN -*I _571_/ZN O *D NOR2_X1 -*I _572_/A I *D XNOR2_X1 +*I _571_:ZN O *D NOR2_X1 +*I _572_:A I *D XNOR2_X1 *CAP 1 _265_:1 0.765 2 _265_:2 1.05 @@ -7947,39 +7947,39 @@ resp_val O 1 _265_:1 _265_:2 0.005 2 _265_:2 _265_:3 4.2 3 _265_:3 _265_:4 0.005 -4 _571_/ZN _265_:1 3.065 -5 _572_/A _265_:4 2.055 +4 _571_:ZN _265_:1 3.065 +5 _572_:A _265_:4 2.055 *END *D_NET _266_ 4.4 *CONN -*I _573_/ZN O *D NAND2_X1 -*I _574_/B I *D OAI211_X1 +*I _573_:ZN O *D NAND2_X1 +*I _574_:B I *D OAI211_X1 *CAP 1 _266_:1 2.025 2 _266_:2 1.225 *RES 1 _266_:1 _266_:2 4.2 -2 _573_/ZN _266_:1 3.905 -3 _574_/B _266_:2 0.705 +2 _573_:ZN _266_:1 3.905 +3 _574_:B _266_:2 0.705 *END *D_NET _267_ 2.65 *CONN -*I _574_/ZN O *D OAI211_X1 -*I _575_/B I *D MUX2_X1 +*I _574_:ZN O *D OAI211_X1 +*I _575_:B I *D MUX2_X1 *CAP 1 _267_:1 1.325 *RES 1 _267_:1 _267_:1 0.005 -2 _574_/ZN _267_:1 2.095 -3 _575_/B _267_:1 3.215 +2 _574_:ZN _267_:1 2.095 +3 _575_:B _267_:1 3.215 *END *D_NET _268_ 5.525 *CONN -*I _576_/ZN O *D OAI21_X1 -*I _583_/A I *D OAI211_X1 +*I _576_:ZN O *D OAI21_X1 +*I _583_:A I *D OAI211_X1 *CAP 1 _268_:1 1.5975 2 _268_:2 1.05 @@ -7991,40 +7991,40 @@ resp_val O 2 _268_:2 _268_:3 0.005 3 _268_:3 _268_:4 4.2 4 _268_:4 _268_:5 0.005 -5 _576_/ZN _268_:1 2.195 -6 _583_/A _268_:5 0.465 +5 _576_:ZN _268_:1 2.195 +6 _583_:A _268_:5 0.465 *END *D_NET _269_ 4.215 *CONN -*I _577_/ZN O *D AND2_X1 -*I _578_/A I *D AOI21_X1 +*I _577_:ZN O *D AND2_X1 +*I _578_:A I *D AOI21_X1 *CAP 1 _269_:1 1.645 2 _269_:2 1.5125 *RES 1 _269_:2 _269_:1 4.2 -2 _577_/ZN _269_:1 2.385 -3 _578_/A _269_:2 1.855 +2 _577_:ZN _269_:1 2.385 +3 _578_:A _269_:2 1.855 *END *D_NET _270_ 4.935 *CONN -*I _578_/ZN O *D AOI21_X1 -*I _580_/A1 I *D NAND2_X1 +*I _578_:ZN O *D AOI21_X1 +*I _580_:A1 I *D NAND2_X1 *CAP 1 _270_:1 1.565 2 _270_:2 1.9525 *RES 1 _270_:2 _270_:1 4.2 -2 _578_/ZN _270_:1 2.065 -3 _580_/A1 _270_:2 3.615 +2 _578_:ZN _270_:1 2.065 +3 _580_:A1 _270_:2 3.615 *END *D_NET _271_ 5.115 *CONN -*I _579_/ZN O *D NAND2_X1 -*I _580_/A2 I *D NAND2_X1 +*I _579_:ZN O *D NAND2_X1 +*I _580_:A2 I *D NAND2_X1 *CAP 1 _271_:1 0.4425 2 _271_:2 1.05 @@ -8034,18 +8034,18 @@ resp_val O 1 _271_:1 _271_:2 0.005 2 _271_:2 _271_:3 4.2 3 _271_:3 _271_:4 0.005 -4 _579_/ZN _271_:1 1.775 -5 _580_/A2 _271_:4 4.265 +4 _579_:ZN _271_:1 1.775 +5 _580_:A2 _271_:4 4.265 *END *D_NET _272_ 32.775 *CONN -*I _580_/ZN O *D NAND2_X1 -*I _581_/A I *D XOR2_X1 -*I _586_/A1 I *D AND2_X1 -*I _589_/C2 I *D AOI221_X4 -*I _596_/B1 I *D AOI21_X1 -*I _611_/A1 I *D NAND2_X1 +*I _580_:ZN O *D NAND2_X1 +*I _581_:A I *D XOR2_X1 +*I _586_:A1 I *D AND2_X1 +*I _589_:C2 I *D AOI221_X4 +*I _596_:B1 I *D AOI21_X1 +*I _611_:A1 I *D NAND2_X1 *CAP 1 _272_:1 3.33 2 _272_:2 1.97 @@ -8065,18 +8065,18 @@ resp_val O 6 _272_:7 _272_:8 0.005 7 _272_:8 _272_:5 16.8 8 _272_:7 _272_:9 16.8 -9 _580_/ZN _272_:9 4.985 -10 _581_/A _272_:2 3.685 -11 _586_/A1 _272_:1 0.725 -12 _589_/C2 _272_:3 3.225 -13 _596_/B1 _272_:4 0.695 -14 _611_/A1 _272_:7 1.865 +9 _580_:ZN _272_:9 4.985 +10 _581_:A _272_:2 3.685 +11 _586_:A1 _272_:1 0.725 +12 _589_:C2 _272_:3 3.225 +13 _596_:B1 _272_:4 0.695 +14 _611_:A1 _272_:7 1.865 *END *D_NET _273_ 2.45 *CONN -*I _582_/ZN O *D NAND2_X1 -*I _583_/B I *D OAI211_X1 +*I _582_:ZN O *D NAND2_X1 +*I _583_:B I *D OAI211_X1 *CAP 1 _273_:1 0.0075 2 _273_:2 1.05 @@ -8086,14 +8086,14 @@ resp_val O 1 _273_:1 _273_:2 0.005 2 _273_:2 _273_:3 4.2 3 _273_:3 _273_:4 0.005 -4 _582_/ZN _273_:1 0.035 -5 _583_/B _273_:4 0.675 +4 _582_:ZN _273_:1 0.035 +5 _583_:B _273_:4 0.675 *END *D_NET _274_ 4.365 *CONN -*I _583_/ZN O *D OAI211_X1 -*I _584_/B I *D MUX2_X1 +*I _583_:ZN O *D OAI211_X1 +*I _584_:B I *D MUX2_X1 *CAP 1 _274_:1 0.2225 2 _274_:2 1.05 @@ -8103,27 +8103,27 @@ resp_val O 1 _274_:1 _274_:2 0.005 2 _274_:2 _274_:3 4.2 3 _274_:3 _274_:4 0.005 -4 _583_/ZN _274_:1 0.895 -5 _584_/B _274_:4 3.645 +4 _583_:ZN _274_:1 0.895 +5 _584_:B _274_:4 3.645 *END *D_NET _275_ 7.74 *CONN -*I _585_/ZN O *D OAI21_X1 -*I _591_/A I *D OAI211_X1 +*I _585_:ZN O *D OAI21_X1 +*I _591_:A I *D OAI211_X1 *CAP 1 _275_:1 2.7525 2 _275_:2 3.2175 *RES 1 _275_:1 _275_:2 8.4 -2 _585_/ZN _275_:2 4.475 -3 _591_/A _275_:1 2.615 +2 _585_:ZN _275_:2 4.475 +3 _591_:A _275_:1 2.615 *END *D_NET _276_ 6.055 *CONN -*I _586_/ZN O *D AND2_X1 -*I _588_/A1 I *D NOR3_X1 +*I _586_:ZN O *D AND2_X1 +*I _588_:A1 I *D NOR3_X1 *CAP 1 _276_:1 1.43 2 _276_:2 1.05 @@ -8135,16 +8135,16 @@ resp_val O 2 _276_:2 _276_:3 0.005 3 _276_:3 _276_:4 4.2 4 _276_:4 _276_:5 0.005 -5 _586_/ZN _276_:1 1.525 -6 _588_/A1 _276_:5 2.195 +5 _586_:ZN _276_:1 1.525 +6 _588_:A1 _276_:5 2.195 *END *D_NET _277_ 9.705 *CONN -*I _587_/ZN O *D NOR2_X1 -*I _588_/A3 I *D NOR3_X1 -*I _589_/B2 I *D AOI221_X4 -*I _594_/A2 I *D NAND2_X1 +*I _587_:ZN O *D NOR2_X1 +*I _588_:A3 I *D NOR3_X1 +*I _589_:B2 I *D AOI221_X4 +*I _594_:A2 I *D NAND2_X1 *CAP 1 _277_:1 1.7875 2 _277_:2 2.6125 @@ -8156,16 +8156,16 @@ resp_val O 2 _277_:1 _277_:3 0.005 3 _277_:3 _277_:4 4.2 4 _277_:4 _277_:5 0.005 -5 _587_/ZN _277_:5 1.815 -6 _588_/A3 _277_:1 2.955 -7 _589_/B2 _277_:2 4.005 -8 _594_/A2 _277_:2 2.255 +5 _587_:ZN _277_:5 1.815 +6 _588_:A3 _277_:1 2.955 +7 _589_:B2 _277_:2 4.005 +8 _594_:A2 _277_:2 2.255 *END *D_NET _278_ 7.675 *CONN -*I _588_/ZN O *D NOR3_X1 -*I _589_/A I *D AOI221_X4 +*I _588_:ZN O *D NOR3_X1 +*I _589_:A I *D AOI221_X4 *CAP 1 _278_:1 0.9 2 _278_:2 1.05 @@ -8177,40 +8177,40 @@ resp_val O 2 _278_:2 _278_:3 4.2 3 _278_:3 _278_:4 0.005 4 _278_:5 _278_:4 4.2 -5 _588_/ZN _278_:5 3.355 -6 _589_/A _278_:1 3.605 +5 _588_:ZN _278_:5 3.355 +6 _589_:A _278_:1 3.605 *END *D_NET _279_ 5.035 *CONN -*I _590_/ZN O *D NAND2_X1 -*I _591_/B I *D OAI211_X1 +*I _590_:ZN O *D NAND2_X1 +*I _591_:B I *D OAI211_X1 *CAP 1 _279_:1 1.9725 2 _279_:2 1.595 *RES 1 _279_:1 _279_:2 4.2 -2 _590_/ZN _279_:1 3.695 -3 _591_/B _279_:2 2.185 +2 _590_:ZN _279_:1 3.695 +3 _591_:B _279_:2 2.185 *END *D_NET _280_ 3.93 *CONN -*I _591_/ZN O *D OAI211_X1 -*I _592_/B I *D MUX2_X1 +*I _591_:ZN O *D OAI211_X1 +*I _592_:B I *D MUX2_X1 *CAP 1 _280_:1 1.7875 2 _280_:2 1.2275 *RES 1 _280_:1 _280_:2 4.2 -2 _591_/ZN _280_:1 2.955 -3 _592_/B _280_:2 0.715 +2 _591_:ZN _280_:1 2.955 +3 _592_:B _280_:2 0.715 *END *D_NET _281_ 7.37 *CONN -*I _593_/ZN O *D OAI21_X1 -*I _599_/A I *D OAI211_X1 +*I _593_:ZN O *D OAI21_X1 +*I _599_:A I *D OAI211_X1 *CAP 1 _281_:1 1.0175 2 _281_:2 1.05 @@ -8222,28 +8222,28 @@ resp_val O 2 _281_:2 _281_:3 4.2 3 _281_:3 _281_:4 0.005 4 _281_:5 _281_:4 4.2 -5 _593_/ZN _281_:5 2.275 -6 _599_/A _281_:1 4.075 +5 _593_:ZN _281_:5 2.275 +6 _599_:A _281_:1 4.075 *END *D_NET _282_ 3.65 *CONN -*I _594_/ZN O *D NAND2_X1 -*I _595_/A I *D OAI21_X1 +*I _594_:ZN O *D NAND2_X1 +*I _595_:A I *D OAI21_X1 *CAP 1 _282_:1 1.4325 2 _282_:2 1.4425 *RES 1 _282_:1 _282_:2 4.2 -2 _594_/ZN _282_:1 1.535 -3 _595_/A _282_:2 1.575 +2 _594_:ZN _282_:1 1.535 +3 _595_:A _282_:2 1.575 *END *D_NET _283_ 11.255 *CONN -*I _595_/ZN O *D OAI21_X1 -*I _596_/A I *D AOI21_X1 -*I _613_/C1 I *D AOI221_X1 +*I _595_:ZN O *D OAI21_X1 +*I _596_:A I *D AOI21_X1 +*I _613_:C1 I *D AOI221_X1 *CAP 1 _283_:1 1.31 2 _283_:2 1.05 @@ -8259,16 +8259,16 @@ resp_val O 4 _283_:5 _283_:2 0.005 5 _283_:5 _283_:6 8.4 6 _283_:6 _283_:7 0.005 -7 _595_/ZN _283_:7 2.495 -8 _596_/A _283_:1 1.045 -9 _613_/C1 _283_:3 2.185 +7 _595_:ZN _283_:7 2.495 +8 _596_:A _283_:1 1.045 +9 _613_:C1 _283_:3 2.185 *END *D_NET _284_ 8.31 *CONN -*I _596_/ZN O *D AOI21_X1 -*I _597_/A I *D XNOR2_X1 -*I _604_/A1 I *D NOR3_X1 +*I _596_:ZN O *D AOI21_X1 +*I _597_:A I *D XNOR2_X1 +*I _604_:A1 I *D NOR3_X1 *CAP 1 _284_:1 1.05 2 _284_:2 2.1 @@ -8284,15 +8284,15 @@ resp_val O 4 _284_:5 _284_:1 4.2 5 _284_:6 _284_:7 0.005 6 _284_:7 _284_:2 4.2 -7 _596_/ZN _284_:4 0.085 -8 _597_/A _284_:5 2.915 -9 _604_/A1 _284_:6 1.035 +7 _596_:ZN _284_:4 0.085 +8 _597_:A _284_:5 2.915 +9 _604_:A1 _284_:6 1.035 *END *D_NET _285_ 4.335 *CONN -*I _598_/ZN O *D NAND2_X1 -*I _599_/B I *D OAI211_X1 +*I _598_:ZN O *D NAND2_X1 +*I _599_:B I *D OAI211_X1 *CAP 1 _285_:1 0.2075 2 _285_:2 1.05 @@ -8302,14 +8302,14 @@ resp_val O 1 _285_:1 _285_:2 0.005 2 _285_:2 _285_:3 4.2 3 _285_:3 _285_:4 0.005 -4 _598_/ZN _285_:1 0.835 -5 _599_/B _285_:4 3.645 +4 _598_:ZN _285_:1 0.835 +5 _599_:B _285_:4 3.645 *END *D_NET _286_ 7.105 *CONN -*I _599_/ZN O *D OAI211_X1 -*I _600_/B I *D MUX2_X1 +*I _599_:ZN O *D OAI211_X1 +*I _600_:B I *D MUX2_X1 *CAP 1 _286_:1 1.4 2 _286_:2 1.05 @@ -8321,14 +8321,14 @@ resp_val O 2 _286_:2 _286_:3 0.005 3 _286_:3 _286_:4 4.2 4 _286_:4 _286_:5 0.005 -5 _599_/ZN _286_:5 4.415 -6 _600_/B _286_:1 1.405 +5 _599_:ZN _286_:5 4.415 +6 _600_:B _286_:1 1.405 *END *D_NET _287_ 18.045 *CONN -*I _601_/ZN O *D OAI21_X1 -*I _608_/A I *D OAI211_X1 +*I _601_:ZN O *D OAI21_X1 +*I _608_:A I *D OAI211_X1 *CAP 1 _287_:1 0.4475 2 _287_:2 8.4 @@ -8338,14 +8338,14 @@ resp_val O 1 _287_:1 _287_:2 0.005 2 _287_:2 _287_:3 33.6 3 _287_:3 _287_:4 0.005 -4 _601_/ZN _287_:1 1.795 -5 _608_/A _287_:4 0.705 +4 _601_:ZN _287_:1 1.795 +5 _608_:A _287_:4 0.705 *END *D_NET _288_ 6.385 *CONN -*I _602_/ZN O *D AND2_X1 -*I _604_/A2 I *D NOR3_X1 +*I _602_:ZN O *D AND2_X1 +*I _604_:A2 I *D NOR3_X1 *CAP 1 _288_:1 1.79 2 _288_:2 1.05 @@ -8357,16 +8357,16 @@ resp_val O 2 _288_:2 _288_:3 0.005 3 _288_:3 _288_:4 4.2 4 _288_:4 _288_:5 0.005 -5 _602_/ZN _288_:1 2.965 -6 _604_/A2 _288_:5 1.415 +5 _602_:ZN _288_:1 2.965 +6 _604_:A2 _288_:5 1.415 *END *D_NET _289_ 8.75 *CONN -*I _603_/ZN O *D NOR2_X1 -*I _604_/A3 I *D NOR3_X1 -*I _605_/A2 I *D NOR2_X1 -*I _612_/A2 I *D AND2_X1 +*I _603_:ZN O *D NOR2_X1 +*I _604_:A3 I *D NOR3_X1 +*I _605_:A2 I *D NOR2_X1 +*I _612_:A2 I *D AND2_X1 *CAP 1 _289_:1 1.4975 2 _289_:2 2.2325 @@ -8378,68 +8378,68 @@ resp_val O 2 _289_:3 _289_:4 0.005 3 _289_:4 _289_:5 4.2 4 _289_:5 _289_:1 0.005 -5 _603_/ZN _289_:3 2.585 -6 _604_/A3 _289_:1 1.795 -7 _605_/A2 _289_:2 3.955 -8 _612_/A2 _289_:2 0.785 +5 _603_:ZN _289_:3 2.585 +6 _604_:A3 _289_:1 1.795 +7 _605_:A2 _289_:2 3.955 +8 _612_:A2 _289_:2 0.785 *END *D_NET _290_ 4.495 *CONN -*I _604_/ZN O *D NOR3_X1 -*I _605_/A1 I *D NOR2_X1 +*I _604_:ZN O *D NOR3_X1 +*I _605_:A1 I *D NOR2_X1 *CAP 1 _290_:1 1.4225 2 _290_:2 1.875 *RES 1 _290_:1 _290_:2 4.2 -2 _604_/ZN _290_:1 1.495 -3 _605_/A1 _290_:2 3.305 +2 _604_:ZN _290_:1 1.495 +3 _605_:A1 _290_:2 3.305 *END *D_NET _291_ 6.055 *CONN -*I _605_/ZN O *D NOR2_X1 -*I _606_/A I *D XNOR2_X1 +*I _605_:ZN O *D NOR2_X1 +*I _606_:A I *D XNOR2_X1 *CAP 1 _291_:1 2.305 2 _291_:2 1.7725 *RES 1 _291_:1 _291_:2 4.2 -2 _605_/ZN _291_:1 5.025 -3 _606_/A _291_:2 2.895 +2 _605_:ZN _291_:1 5.025 +3 _606_:A _291_:2 2.895 *END *D_NET _292_ 3.98 *CONN -*I _607_/ZN O *D NAND2_X1 -*I _608_/B I *D OAI211_X1 +*I _607_:ZN O *D NAND2_X1 +*I _608_:B I *D OAI211_X1 *CAP 1 _292_:1 1.7075 2 _292_:2 1.3325 *RES 1 _292_:2 _292_:1 4.2 -2 _607_/ZN _292_:1 2.635 -3 _608_/B _292_:2 1.135 +2 _607_:ZN _292_:1 2.635 +3 _608_:B _292_:2 1.135 *END *D_NET _293_ 3.465 *CONN -*I _608_/ZN O *D OAI211_X1 -*I _609_/B I *D MUX2_X1 +*I _608_:ZN O *D OAI211_X1 +*I _609_:B I *D MUX2_X1 *CAP 1 _293_:1 1.1575 2 _293_:2 1.625 *RES 1 _293_:1 _293_:2 4.2 -2 _608_/ZN _293_:1 0.435 -3 _609_/B _293_:2 2.305 +2 _608_:ZN _293_:1 0.435 +3 _609_:B _293_:2 2.305 *END *D_NET _294_ 8.95 *CONN -*I _610_/ZN O *D OAI21_X1 -*I _617_/A I *D OAI211_X1 +*I _610_:ZN O *D OAI21_X1 +*I _617_:A I *D OAI211_X1 *CAP 1 _294_:1 1.7075 2 _294_:2 1.05 @@ -8451,14 +8451,14 @@ resp_val O 2 _294_:2 _294_:3 0.005 3 _294_:3 _294_:4 8.4 4 _294_:4 _294_:5 0.005 -5 _610_/ZN _294_:5 2.675 -6 _617_/A _294_:1 2.635 +5 _610_:ZN _294_:5 2.675 +6 _617_:A _294_:1 2.635 *END *D_NET _295_ 3.535 *CONN -*I _611_/ZN O *D NAND2_X1 -*I _614_/A1 I *D NAND2_X1 +*I _611_:ZN O *D NAND2_X1 +*I _614_:A1 I *D NAND2_X1 *CAP 1 _295_:1 0.27 2 _295_:2 1.05 @@ -8468,14 +8468,14 @@ resp_val O 1 _295_:1 _295_:2 0.005 2 _295_:2 _295_:3 4.2 3 _295_:3 _295_:4 0.005 -4 _611_/ZN _295_:4 1.795 -5 _614_/A1 _295_:1 1.085 +4 _611_:ZN _295_:4 1.795 +5 _614_:A1 _295_:1 1.085 *END *D_NET _296_ 5.005 *CONN -*I _612_/ZN O *D AND2_X1 -*I _613_/A I *D AOI221_X1 +*I _612_:ZN O *D AND2_X1 +*I _613_:A I *D AOI221_X1 *CAP 1 _296_:1 0.65 2 _296_:2 1.05 @@ -8485,14 +8485,14 @@ resp_val O 1 _296_:1 _296_:2 0.005 2 _296_:2 _296_:3 4.2 3 _296_:3 _296_:4 0.005 -4 _612_/ZN _296_:1 2.605 -5 _613_/A _296_:4 3.215 +4 _612_:ZN _296_:1 2.605 +5 _613_:A _296_:4 3.215 *END *D_NET _297_ 12.61 *CONN -*I _613_/ZN O *D AOI221_X1 -*I _614_/A2 I *D NAND2_X1 +*I _613_:ZN O *D AOI221_X1 +*I _614_:A2 I *D NAND2_X1 *CAP 1 _297_:1 0.4325 2 _297_:2 4.2 @@ -8504,17 +8504,17 @@ resp_val O 2 _297_:2 _297_:3 16.8 3 _297_:3 _297_:4 0.005 4 _297_:4 _297_:5 4.2 -5 _613_/ZN _297_:5 2.495 -6 _614_/A2 _297_:1 1.735 +5 _613_:ZN _297_:5 2.495 +6 _614_:A2 _297_:1 1.735 *END *D_NET _298_ 33.995 *CONN -*I _614_/ZN O *D NAND2_X1 -*I _615_/A I *D XOR2_X1 -*I _620_/A1 I *D AND3_X1 -*I _621_/A1 I *D AND2_X1 -*I _647_/A1 I *D AND2_X1 +*I _614_:ZN O *D NAND2_X1 +*I _615_:A I *D XOR2_X1 +*I _620_:A1 I *D AND3_X1 +*I _621_:A1 I *D AND2_X1 +*I _647_:A1 I *D AND2_X1 *CAP 1 _298_:1 3.34 2 _298_:2 3.0125 @@ -8534,17 +8534,17 @@ resp_val O 6 _298_:5 _298_:7 25.2 7 _298_:7 _298_:8 0.005 8 _298_:8 _298_:9 8.4 -9 _614_/ZN _298_:9 1.015 -10 _615_/A _298_:2 3.655 -11 _620_/A1 _298_:3 1.815 -12 _621_/A1 _298_:1 0.765 -13 _647_/A1 _298_:6 1.965 +9 _614_:ZN _298_:9 1.015 +10 _615_:A _298_:2 3.655 +11 _620_:A1 _298_:3 1.815 +12 _621_:A1 _298_:1 0.765 +13 _647_:A1 _298_:6 1.965 *END *D_NET _299_ 3.615 *CONN -*I _616_/ZN O *D NAND2_X1 -*I _617_/B I *D OAI211_X1 +*I _616_:ZN O *D NAND2_X1 +*I _617_:B I *D OAI211_X1 *CAP 1 _299_:1 0.55 2 _299_:2 1.05 @@ -8554,14 +8554,14 @@ resp_val O 1 _299_:1 _299_:2 0.005 2 _299_:2 _299_:3 4.2 3 _299_:3 _299_:4 0.005 -4 _616_/ZN _299_:4 0.835 -5 _617_/B _299_:1 2.205 +4 _616_:ZN _299_:4 0.835 +5 _617_:B _299_:1 2.205 *END *D_NET _300_ 6.78 *CONN -*I _617_/ZN O *D OAI211_X1 -*I _618_/B I *D MUX2_X1 +*I _617_:ZN O *D OAI211_X1 +*I _618_:B I *D MUX2_X1 *CAP 1 _300_:1 0.5475 2 _300_:2 2.1 @@ -8571,29 +8571,29 @@ resp_val O 1 _300_:1 _300_:2 0.005 2 _300_:2 _300_:3 8.4 3 _300_:3 _300_:4 0.005 -4 _617_/ZN _300_:4 2.975 -5 _618_/B _300_:1 2.195 +4 _617_:ZN _300_:4 2.975 +5 _618_:B _300_:1 2.195 *END *D_NET _301_ 5.19 *CONN -*I _619_/ZN O *D OAI21_X1 -*I _626_/A I *D OAI211_X1 +*I _619_:ZN O *D OAI21_X1 +*I _626_:A I *D OAI211_X1 *CAP 1 _301_:1 2.0675 2 _301_:2 1.5775 *RES 1 _301_:2 _301_:1 4.2 -2 _619_/ZN _301_:1 4.075 -3 _626_/A _301_:2 2.115 +2 _619_:ZN _301_:1 4.075 +3 _626_:A _301_:2 2.115 *END *D_NET _302_ 16.83 *CONN -*I _620_/ZN O *D AND3_X1 -*I _624_/A I *D AOI211_X1 -*I _632_/A1 I *D NOR2_X1 -*I _639_/B1 I *D OAI21_X1 +*I _620_:ZN O *D AND3_X1 +*I _624_:A I *D AOI211_X1 +*I _632_:A1 I *D NOR2_X1 +*I _639_:B1 I *D OAI21_X1 *CAP 1 _302_:1 1.3775 2 _302_:2 1.05 @@ -8613,16 +8613,16 @@ resp_val O 6 _302_:6 _302_:7 0.005 7 _302_:9 _302_:8 4.2 8 _302_:5 _302_:9 8.4 -9 _620_/ZN _302_:8 4.625 -10 _624_/A _302_:9 0.915 -11 _632_/A1 _302_:1 1.315 -12 _639_/B1 _302_:7 1.625 +9 _620_:ZN _302_:8 4.625 +10 _624_:A _302_:9 0.915 +11 _632_:A1 _302_:1 1.315 +12 _639_:B1 _302_:7 1.625 *END *D_NET _303_ 6.345 *CONN -*I _621_/ZN O *D AND2_X1 -*I _623_/A1 I *D NOR3_X1 +*I _621_:ZN O *D AND2_X1 +*I _623_:A1 I *D NOR3_X1 *CAP 1 _303_:1 1.7625 2 _303_:2 1.05 @@ -8634,16 +8634,16 @@ resp_val O 2 _303_:2 _303_:3 0.005 3 _303_:3 _303_:4 4.2 4 _303_:4 _303_:5 0.005 -5 _621_/ZN _303_:5 1.445 -6 _623_/A1 _303_:1 2.855 +5 _621_:ZN _303_:5 1.445 +6 _623_:A1 _303_:1 2.855 *END *D_NET _304_ 15.8 *CONN -*I _622_/ZN O *D NOR2_X1 -*I _623_/A3 I *D NOR3_X1 -*I _624_/C2 I *D AOI211_X1 -*I _630_/B2 I *D AOI21_X1 +*I _622_:ZN O *D NOR2_X1 +*I _623_:A3 I *D NOR3_X1 +*I _624_:C2 I *D AOI211_X1 +*I _630_:B2 I *D AOI21_X1 *CAP 1 _304_:1 1.05 2 _304_:2 2.1 @@ -8663,16 +8663,16 @@ resp_val O 6 _304_:7 _304_:2 4.2 7 _304_:8 _304_:9 4.2 8 _304_:9 _304_:1 4.2 -9 _622_/ZN _304_:6 4.705 -10 _623_/A3 _304_:9 2.095 -11 _624_/C2 _304_:5 1.905 -12 _630_/B2 _304_:8 1.915 +9 _622_:ZN _304_:6 4.705 +10 _623_:A3 _304_:9 2.095 +11 _624_:C2 _304_:5 1.905 +12 _630_:B2 _304_:8 1.915 *END *D_NET _305_ 3.38 *CONN -*I _623_/ZN O *D NOR3_X1 -*I _624_/B I *D AOI211_X1 +*I _623_:ZN O *D NOR3_X1 +*I _624_:B I *D AOI211_X1 *CAP 1 _305_:1 0.4225 2 _305_:2 1.05 @@ -8682,14 +8682,14 @@ resp_val O 1 _305_:1 _305_:2 0.005 2 _305_:2 _305_:3 4.2 3 _305_:3 _305_:4 0.005 -4 _623_/ZN _305_:1 1.695 -5 _624_/B _305_:4 0.875 +4 _623_:ZN _305_:1 1.695 +5 _624_:B _305_:4 0.875 *END *D_NET _306_ 10.465 *CONN -*I _625_/ZN O *D NAND2_X1 -*I _626_/B I *D OAI211_X1 +*I _625_:ZN O *D NAND2_X1 +*I _626_:B I *D OAI211_X1 *CAP 1 _306_:1 1.685 2 _306_:2 1.05 @@ -8701,14 +8701,14 @@ resp_val O 2 _306_:2 _306_:3 0.005 3 _306_:3 _306_:4 12.6 4 _306_:4 _306_:5 0.005 -5 _625_/ZN _306_:5 1.595 -6 _626_/B _306_:1 2.545 +5 _625_:ZN _306_:5 1.595 +6 _626_:B _306_:1 2.545 *END *D_NET _307_ 8.48 *CONN -*I _626_/ZN O *D OAI211_X1 -*I _627_/B I *D MUX2_X1 +*I _626_:ZN O *D OAI211_X1 +*I _627_:B I *D MUX2_X1 *CAP 1 _307_:1 1.6975 2 _307_:2 1.05 @@ -8722,27 +8722,27 @@ resp_val O 3 _307_:3 _307_:4 4.2 4 _307_:4 _307_:5 0.005 5 _307_:5 _307_:6 4.2 -6 _626_/ZN _307_:6 1.775 -7 _627_/B _307_:1 2.595 +6 _626_:ZN _307_:6 1.775 +7 _627_:B _307_:1 2.595 *END *D_NET _308_ 5.365 *CONN -*I _628_/ZN O *D OAI21_X1 -*I _635_/A I *D OAI211_X1 +*I _628_:ZN O *D OAI21_X1 +*I _635_:A I *D OAI211_X1 *CAP 1 _308_:1 1.9725 2 _308_:2 1.76 *RES 1 _308_:1 _308_:2 4.2 -2 _628_/ZN _308_:1 3.695 -3 _635_/A _308_:2 2.845 +2 _628_:ZN _308_:1 3.695 +3 _635_:A _308_:2 2.845 *END *D_NET _309_ 6.29 *CONN -*I _629_/ZN O *D NOR2_X1 -*I _630_/A I *D AOI21_X1 +*I _629_:ZN O *D NOR2_X1 +*I _630_:A I *D AOI21_X1 *CAP 1 _309_:1 1.875 2 _309_:2 1.05 @@ -8754,29 +8754,29 @@ resp_val O 2 _309_:2 _309_:3 0.005 3 _309_:3 _309_:4 4.2 4 _309_:4 _309_:5 0.005 -5 _629_/ZN _309_:1 3.305 -6 _630_/A _309_:5 0.885 +5 _629_:ZN _309_:1 3.305 +6 _630_:A _309_:5 0.885 *END *D_NET _310_ 3.565 *CONN -*I _630_/ZN O *D AOI21_X1 -*I _631_/A I *D INV_X1 +*I _630_:ZN O *D AOI21_X1 +*I _631_:A I *D INV_X1 *CAP 1 _310_:1 1.34 2 _310_:2 1.4925 *RES 1 _310_:2 _310_:1 4.2 -2 _630_/ZN _310_:1 1.165 -3 _631_/A _310_:2 1.775 +2 _630_:ZN _310_:1 1.165 +3 _631_:A _310_:2 1.775 *END *D_NET _311_ 15.54 *CONN -*I _631_/ZN O *D INV_X1 -*I _632_/A2 I *D NOR2_X1 -*I _639_/B2 I *D OAI21_X1 -*I _649_/A1 I *D NAND2_X1 +*I _631_:ZN O *D INV_X1 +*I _632_:A2 I *D NOR2_X1 +*I _639_:B2 I *D OAI21_X1 +*I _649_:A1 I *D NAND2_X1 *CAP 1 _311_:1 1.235 2 _311_:2 1.765 @@ -8794,55 +8794,55 @@ resp_val O 5 _311_:6 _311_:7 4.2 6 _311_:2 _311_:8 0.005 7 _311_:8 _311_:4 8.4 -8 _631_/ZN _311_:2 2.865 -9 _632_/A2 _311_:1 0.745 -10 _639_/B2 _311_:3 2.275 -11 _649_/A1 _311_:7 4.215 +8 _631_:ZN _311_:2 2.865 +9 _632_:A2 _311_:1 0.745 +10 _639_:B2 _311_:3 2.275 +11 _649_:A1 _311_:7 4.215 *END *D_NET _312_ 4.24 *CONN -*I _632_/ZN O *D NOR2_X1 -*I _633_/A I *D XNOR2_X1 +*I _632_:ZN O *D NOR2_X1 +*I _633_:A I *D XNOR2_X1 *CAP 1 _312_:1 1.1375 2 _312_:2 2.0325 *RES 1 _312_:2 _312_:1 4.2 -2 _632_/ZN _312_:1 0.355 -3 _633_/A _312_:2 3.935 +2 _632_:ZN _312_:1 0.355 +3 _633_:A _312_:2 3.935 *END *D_NET _313_ 7.175 *CONN -*I _634_/ZN O *D NAND2_X1 -*I _635_/B I *D OAI211_X1 +*I _634_:ZN O *D NAND2_X1 +*I _635_:B I *D OAI211_X1 *CAP 1 _313_:1 2.8575 2 _313_:2 2.83 *RES 1 _313_:1 _313_:2 8.4 -2 _634_/ZN _313_:2 2.925 -3 _635_/B _313_:1 3.035 +2 _634_:ZN _313_:2 2.925 +3 _635_:B _313_:1 3.035 *END *D_NET _314_ 5.055 *CONN -*I _635_/ZN O *D OAI211_X1 -*I _636_/B I *D MUX2_X1 +*I _635_:ZN O *D OAI211_X1 +*I _636_:B I *D MUX2_X1 *CAP 1 _314_:1 1.7175 2 _314_:2 1.86 *RES 1 _314_:1 _314_:2 4.2 -2 _635_/ZN _314_:1 2.675 -3 _636_/B _314_:2 3.245 +2 _635_:ZN _314_:1 2.675 +3 _636_:B _314_:2 3.245 *END *D_NET _315_ 6.8 *CONN -*I _637_/ZN O *D OAI21_X1 -*I _638_/A I *D OAI21_X1 +*I _637_:ZN O *D OAI21_X1 +*I _638_:A I *D OAI21_X1 *CAP 1 _315_:1 0.3025 2 _315_:2 1.05 @@ -8854,26 +8854,26 @@ resp_val O 2 _315_:2 _315_:3 4.2 3 _315_:3 _315_:4 0.005 4 _315_:5 _315_:4 4.2 -5 _637_/ZN _315_:1 1.215 -6 _638_/A _315_:5 3.995 +5 _637_:ZN _315_:1 1.215 +6 _638_:A _315_:5 3.995 *END *D_NET _316_ 3.285 *CONN -*I _638_/ZN O *D OAI21_X1 -*I _645_/B1 I *D OAI21_X1 +*I _638_:ZN O *D OAI21_X1 +*I _645_:B1 I *D OAI21_X1 *CAP 1 _316_:1 1.6425 *RES 1 _316_:1 _316_:1 0.005 -2 _638_/ZN _316_:1 4.375 -3 _645_/B1 _316_:1 2.205 +2 _638_:ZN _316_:1 4.375 +3 _645_:B1 _316_:1 2.205 *END *D_NET _317_ 13.39 *CONN -*I _639_/ZN O *D OAI21_X1 -*I _642_/A1 I *D AND2_X1 +*I _639_:ZN O *D OAI21_X1 +*I _642_:A1 I *D AND2_X1 *CAP 1 _317_:1 1.6425 2 _317_:2 1.05 @@ -8887,15 +8887,15 @@ resp_val O 3 _317_:3 _317_:4 12.6 4 _317_:4 _317_:5 0.005 5 _317_:6 _317_:5 4.2 -6 _639_/ZN _317_:1 2.375 -7 _642_/A1 _317_:6 3.415 +6 _639_:ZN _317_:1 2.375 +7 _642_:A1 _317_:6 3.415 *END *D_NET _318_ 11.93 *CONN -*I _640_/ZN O *D NOR2_X1 -*I _641_/A I *D INV_X1 -*I _650_/B2 I *D AOI21_X1 +*I _640_:ZN O *D NOR2_X1 +*I _641_:A I *D INV_X1 +*I _650_:B2 I *D AOI21_X1 *CAP 1 _318_:1 0.6075 2 _318_:2 1.05 @@ -8911,15 +8911,15 @@ resp_val O 4 _318_:3 _318_:5 8.4 5 _318_:5 _318_:6 0.005 6 _318_:4 _318_:7 4.2 -7 _640_/ZN _318_:1 2.435 -8 _641_/A _318_:6 3.815 -9 _650_/B2 _318_:7 0.825 +7 _640_:ZN _318_:1 2.435 +8 _641_:A _318_:6 3.815 +9 _650_:B2 _318_:7 0.825 *END *D_NET _319_ 8.175 *CONN -*I _641_/ZN O *D INV_X1 -*I _642_/A2 I *D AND2_X1 +*I _641_:ZN O *D INV_X1 +*I _642_:A2 I *D AND2_X1 *CAP 1 _319_:1 1.8075 2 _319_:2 1.05 @@ -8931,14 +8931,14 @@ resp_val O 2 _319_:2 _319_:3 0.005 3 _319_:3 _319_:4 4.2 4 _319_:4 _319_:5 0.005 -5 _641_/ZN _319_:5 4.925 -6 _642_/A2 _319_:1 3.035 +5 _641_:ZN _319_:5 4.925 +6 _642_:A2 _319_:1 3.035 *END *D_NET _320_ 9.795 *CONN -*I _642_/ZN O *D AND2_X1 -*I _643_/A I *D XNOR2_X1 +*I _642_:ZN O *D AND2_X1 +*I _643_:A I *D XNOR2_X1 *CAP 1 _320_:1 1.97 2 _320_:2 1.05 @@ -8950,65 +8950,65 @@ resp_val O 2 _320_:2 _320_:3 0.005 3 _320_:3 _320_:4 8.4 4 _320_:4 _320_:5 0.005 -5 _642_/ZN _320_:1 3.685 -6 _643_/A _320_:5 3.315 +5 _642_:ZN _320_:1 3.685 +6 _643_:A _320_:5 3.315 *END *D_NET _321_ 2.265 *CONN -*I _644_/ZN O *D AND2_X1 -*I _645_/B2 I *D OAI21_X1 +*I _644_:ZN O *D AND2_X1 +*I _645_:B2 I *D OAI21_X1 *CAP 1 _321_:1 1.1325 *RES 1 _321_:1 _321_:1 0.005 -2 _644_/ZN _321_:1 2.985 -3 _645_/B2 _321_:1 1.555 +2 _644_:ZN _321_:1 2.985 +3 _645_:B2 _321_:1 1.555 *END *D_NET _322_ 3.85 *CONN -*I _645_/ZN O *D OAI21_X1 -*I _646_/A I *D OAI21_X1 +*I _645_:ZN O *D OAI21_X1 +*I _646_:A I *D OAI21_X1 *CAP 1 _322_:1 1.6525 2 _322_:2 1.3225 *RES 1 _322_:2 _322_:1 4.2 -2 _645_/ZN _322_:1 2.415 -3 _646_/A _322_:2 1.095 +2 _645_:ZN _322_:1 2.415 +3 _646_:A _322_:2 1.095 *END *D_NET _323_ 2.98 *CONN -*I _647_/ZN O *D AND2_X1 -*I _648_/A I *D INV_X1 +*I _647_:ZN O *D AND2_X1 +*I _648_:A I *D INV_X1 *CAP 1 _323_:1 1.19 2 _323_:2 1.35 *RES 1 _323_:2 _323_:1 4.2 -2 _647_/ZN _323_:1 0.565 -3 _648_/A _323_:2 1.205 +2 _647_:ZN _323_:1 0.565 +3 _648_:A _323_:2 1.205 *END *D_NET _324_ 4.76 *CONN -*I _648_/ZN O *D INV_X1 -*I _651_/A1 I *D AND3_X1 +*I _648_:ZN O *D INV_X1 +*I _651_:A1 I *D AND3_X1 *CAP 1 _324_:1 1.54 2 _324_:2 1.89 *RES 1 _324_:2 _324_:1 4.2 -2 _648_/ZN _324_:1 1.965 -3 _651_/A1 _324_:2 3.365 +2 _648_:ZN _324_:1 1.965 +3 _651_:A1 _324_:2 3.365 *END *D_NET _325_ 8.2 *CONN -*I _649_/ZN O *D NAND2_X1 -*I _651_/A2 I *D AND3_X1 +*I _649_:ZN O *D NAND2_X1 +*I _651_:A2 I *D AND3_X1 *CAP 1 _325_:1 1.255 2 _325_:2 2.1 @@ -9018,29 +9018,29 @@ resp_val O 1 _325_:1 _325_:2 0.005 2 _325_:2 _325_:3 8.4 3 _325_:3 _325_:4 0.005 -4 _649_/ZN _325_:1 5.025 -5 _651_/A2 _325_:4 2.985 +4 _649_:ZN _325_:1 5.025 +5 _651_:A2 _325_:4 2.985 *END *D_NET _326_ 5.71 *CONN -*I _650_/ZN O *D AOI21_X1 -*I _651_/A3 I *D AND3_X1 +*I _650_:ZN O *D AOI21_X1 +*I _651_:A3 I *D AND3_X1 *CAP 1 _326_:1 2.205 2 _326_:2 2.75 *RES 1 _326_:1 _326_:2 8.4 -2 _650_/ZN _326_:1 0.425 -3 _651_/A3 _326_:2 2.605 +2 _650_:ZN _326_:1 0.425 +3 _651_:A3 _326_:2 2.605 *END *D_NET _327_ 30.64 *CONN -*I _651_/ZN O *D AND3_X1 -*I _652_/A I *D XNOR2_X1 -*I _657_/A1 I *D NOR2_X1 -*I _665_/A1 I *D OR3_X1 +*I _651_:ZN O *D AND3_X1 +*I _652_:A I *D XNOR2_X1 +*I _657_:A1 I *D NOR2_X1 +*I _665_:A1 I *D OR3_X1 *CAP 1 _327_:1 1.05 2 _327_:2 3.15 @@ -9064,29 +9064,29 @@ resp_val O 8 _327_:9 _327_:10 29.4 9 _327_:9 _327_:11 0.005 10 _327_:11 _327_:8 4.2 -11 _651_/ZN _327_:10 1.775 -12 _652_/A _327_:5 2.315 -13 _657_/A1 _327_:6 1.385 -14 _665_/A1 _327_:7 1.225 +11 _651_:ZN _327_:10 1.775 +12 _652_:A _327_:5 2.315 +13 _657_:A1 _327_:6 1.385 +14 _665_:A1 _327_:7 1.225 *END *D_NET _328_ 5.62 *CONN -*I _653_/ZN O *D NAND2_X1 -*I _655_/A I *D OAI211_X1 +*I _653_:ZN O *D NAND2_X1 +*I _655_:A I *D OAI211_X1 *CAP 1 _328_:1 2.375 2 _328_:2 1.485 *RES 1 _328_:2 _328_:1 4.2 -2 _653_/ZN _328_:1 5.305 -3 _655_/A _328_:2 1.745 +2 _653_:ZN _328_:1 5.305 +3 _655_:A _328_:2 1.745 *END *D_NET _329_ 12.92 *CONN -*I _654_/ZN O *D OAI21_X1 -*I _655_/B I *D OAI211_X1 +*I _654_:ZN O *D OAI21_X1 +*I _655_:B I *D OAI211_X1 *CAP 1 _329_:1 0.8825 2 _329_:2 5.25 @@ -9096,14 +9096,14 @@ resp_val O 1 _329_:1 _329_:2 0.005 2 _329_:2 _329_:3 21 3 _329_:3 _329_:4 0.005 -4 _654_/ZN _329_:1 3.535 -5 _655_/B _329_:4 1.315 +4 _654_:ZN _329_:1 3.535 +5 _655_:B _329_:4 1.315 *END *D_NET _330_ 6.795 *CONN -*I _655_/ZN O *D OAI211_X1 -*I _656_/B I *D MUX2_X1 +*I _655_:ZN O *D OAI211_X1 +*I _656_:B I *D MUX2_X1 *CAP 1 _330_:1 1.7675 2 _330_:2 1.05 @@ -9115,14 +9115,14 @@ resp_val O 2 _330_:2 _330_:3 0.005 3 _330_:3 _330_:4 4.2 4 _330_:4 _330_:5 0.005 -5 _655_/ZN _330_:1 2.875 -6 _656_/B _330_:5 2.325 +5 _655_:ZN _330_:1 2.875 +6 _656_:B _330_:5 2.325 *END *D_NET _331_ 4.715 *CONN -*I _657_/ZN O *D NOR2_X1 -*I _659_/A1 I *D NOR2_X1 +*I _657_:ZN O *D NOR2_X1 +*I _659_:A1 I *D NOR2_X1 *CAP 1 _331_:1 0.425 2 _331_:2 1.05 @@ -9132,15 +9132,15 @@ resp_val O 1 _331_:1 _331_:2 0.005 2 _331_:2 _331_:3 4.2 3 _331_:3 _331_:4 0.005 -4 _657_/ZN _331_:1 1.705 -5 _659_/A1 _331_:4 3.535 +4 _657_:ZN _331_:1 1.705 +5 _659_:A1 _331_:4 3.535 *END *D_NET _332_ 14.275 *CONN -*I _658_/ZN O *D NOR2_X1 -*I _659_/A2 I *D NOR2_X1 -*I _667_/A2 I *D AOI22_X1 +*I _658_:ZN O *D NOR2_X1 +*I _659_:A2 I *D NOR2_X1 +*I _667_:A2 I *D AOI22_X1 *CAP 1 _332_:1 1.9075 2 _332_:2 1.05 @@ -9154,15 +9154,15 @@ resp_val O 3 _332_:3 _332_:4 4.2 4 _332_:4 _332_:5 0.005 5 _332_:5 _332_:6 8.4 -6 _658_/ZN _332_:6 4.145 -7 _659_/A2 _332_:5 4.185 -8 _667_/A2 _332_:1 3.435 +6 _658_:ZN _332_:6 4.145 +7 _659_:A2 _332_:5 4.185 +8 _667_:A2 _332_:1 3.435 *END *D_NET _333_ 7.53 *CONN -*I _659_/ZN O *D NOR2_X1 -*I _660_/A I *D XNOR2_X1 +*I _659_:ZN O *D NOR2_X1 +*I _660_:A I *D XNOR2_X1 *CAP 1 _333_:1 1.9375 2 _333_:2 1.05 @@ -9174,14 +9174,14 @@ resp_val O 2 _333_:2 _333_:3 0.005 3 _333_:3 _333_:4 4.2 4 _333_:4 _333_:5 0.005 -5 _659_/ZN _333_:5 3.115 -6 _660_/A _333_:1 3.555 +5 _659_:ZN _333_:5 3.115 +6 _660_:A _333_:1 3.555 *END *D_NET _334_ 6.16 *CONN -*I _661_/ZN O *D NAND2_X1 -*I _663_/A I *D OAI211_X1 +*I _661_:ZN O *D NAND2_X1 +*I _663_:A I *D OAI211_X1 *CAP 1 _334_:1 0.4975 2 _334_:2 1.05 @@ -9193,14 +9193,14 @@ resp_val O 2 _334_:2 _334_:3 4.2 3 _334_:3 _334_:4 0.005 4 _334_:5 _334_:4 4.2 -5 _661_/ZN _334_:5 1.935 -6 _663_/A _334_:1 1.995 +5 _661_:ZN _334_:5 1.935 +6 _663_:A _334_:1 1.995 *END *D_NET _335_ 3.855 *CONN -*I _662_/ZN O *D OAI21_X1 -*I _663_/B I *D OAI211_X1 +*I _662_:ZN O *D OAI21_X1 +*I _663_:B I *D OAI211_X1 *CAP 1 _335_:1 0.2725 2 _335_:2 1.05 @@ -9210,28 +9210,28 @@ resp_val O 1 _335_:1 _335_:2 0.005 2 _335_:2 _335_:3 4.2 3 _335_:3 _335_:4 0.005 -4 _662_/ZN _335_:1 1.095 -5 _663_/B _335_:4 2.425 +4 _662_:ZN _335_:1 1.095 +5 _663_:B _335_:4 2.425 *END *D_NET _336_ 3.74 *CONN -*I _663_/ZN O *D OAI211_X1 -*I _664_/B I *D MUX2_X1 +*I _663_:ZN O *D OAI211_X1 +*I _664_:B I *D MUX2_X1 *CAP 1 _336_:1 1.3075 2 _336_:2 1.6125 *RES 1 _336_:2 _336_:1 4.2 -2 _663_/ZN _336_:1 1.035 -3 _664_/B _336_:2 2.255 +2 _663_:ZN _336_:1 1.035 +3 _664_:B _336_:2 2.255 *END *D_NET _337_ 9.5 *CONN -*I _665_/ZN O *D OR3_X1 -*I _668_/A1 I *D AND3_X1 -*I _669_/B1 I *D AOI21_X1 +*I _665_:ZN O *D OR3_X1 +*I _668_:A1 I *D AND3_X1 +*I _669_:B1 I *D AOI21_X1 *CAP 1 _337_:1 0.3225 2 _337_:2 1.05 @@ -9247,16 +9247,16 @@ resp_val O 4 _337_:3 _337_:5 4.2 5 _337_:5 _337_:6 0.005 6 _337_:6 _337_:7 4.2 -7 _665_/ZN _337_:7 2.745 -8 _668_/A1 _337_:4 2.375 -9 _669_/B1 _337_:1 1.295 +7 _665_:ZN _337_:7 2.745 +8 _668_:A1 _337_:4 2.375 +9 _669_:B1 _337_:1 1.295 *END *D_NET _338_ 7.065 *CONN -*I _666_/ZN O *D INV_X1 -*I _668_/A2 I *D AND3_X1 -*I _669_/A I *D AOI21_X1 +*I _666_:ZN O *D INV_X1 +*I _668_:A2 I *D AND3_X1 +*I _669_:A I *D AOI21_X1 *CAP 1 _338_:1 1.285 2 _338_:2 1.05 @@ -9268,16 +9268,16 @@ resp_val O 2 _338_:2 _338_:3 4.2 3 _338_:3 _338_:4 0.005 4 _338_:1 _338_:5 4.2 -5 _666_/ZN _338_:5 2.805 -6 _668_/A2 _338_:4 1.995 -7 _669_/A _338_:1 0.945 +5 _666_:ZN _338_:5 2.805 +6 _668_:A2 _338_:4 1.995 +7 _669_:A _338_:1 0.945 *END *D_NET _339_ 9.68 *CONN -*I _667_/ZN O *D AOI22_X1 -*I _668_/A3 I *D AND3_X1 -*I _669_/B2 I *D AOI21_X1 +*I _667_:ZN O *D AOI22_X1 +*I _668_:A3 I *D AND3_X1 +*I _669_:B2 I *D AOI21_X1 *CAP 1 _339_:1 0.4925 2 _339_:2 1.05 @@ -9293,15 +9293,15 @@ resp_val O 4 _339_:3 _339_:5 4.2 5 _339_:5 _339_:6 0.005 6 _339_:7 _339_:6 4.2 -7 _667_/ZN _339_:7 3.185 -8 _668_/A3 _339_:4 1.615 -9 _669_/B2 _339_:1 1.975 +7 _667_:ZN _339_:7 3.185 +8 _668_:A3 _339_:4 1.615 +9 _669_:B2 _339_:1 1.975 *END *D_NET _340_ 4.465 *CONN -*I _668_/ZN O *D AND3_X1 -*I _670_/A1 I *D NOR2_X1 +*I _668_:ZN O *D AND3_X1 +*I _670_:A1 I *D NOR2_X1 *CAP 1 _340_:1 0.9475 2 _340_:2 1.05 @@ -9311,29 +9311,29 @@ resp_val O 1 _340_:1 _340_:2 0.005 2 _340_:2 _340_:3 4.2 3 _340_:3 _340_:4 0.005 -4 _668_/ZN _340_:4 0.945 -5 _670_/A1 _340_:1 3.795 +4 _668_:ZN _340_:4 0.945 +5 _670_:A1 _340_:1 3.795 *END *D_NET _341_ 7.385 *CONN -*I _669_/ZN O *D AOI21_X1 -*I _670_/A2 I *D NOR2_X1 -*I _676_/A1 I *D NOR2_X1 +*I _669_:ZN O *D AOI21_X1 +*I _670_:A2 I *D NOR2_X1 +*I _676_:A1 I *D NOR2_X1 *CAP 1 _341_:1 3.19 2 _341_:2 2.6025 *RES 1 _341_:1 _341_:2 8.4 -2 _669_/ZN _341_:1 1.225 -3 _670_/A2 _341_:1 3.145 -4 _676_/A1 _341_:2 2.015 +2 _669_:ZN _341_:1 1.225 +3 _670_:A2 _341_:1 3.145 +4 _676_:A1 _341_:2 2.015 *END *D_NET _342_ 9.47 *CONN -*I _671_/ZN O *D NAND2_X1 -*I _673_/A I *D OAI211_X1 +*I _671_:ZN O *D NAND2_X1 +*I _673_:A I *D OAI211_X1 *CAP 1 _342_:1 2.0175 2 _342_:2 1.05 @@ -9345,14 +9345,14 @@ resp_val O 2 _342_:2 _342_:3 0.005 3 _342_:3 _342_:4 8.4 4 _342_:4 _342_:5 0.005 -5 _671_/ZN _342_:5 2.475 -6 _673_/A _342_:1 3.875 +5 _671_:ZN _342_:5 2.475 +6 _673_:A _342_:1 3.875 *END *D_NET _343_ 9.405 *CONN -*I _672_/ZN O *D OAI21_X1 -*I _673_/B I *D OAI211_X1 +*I _672_:ZN O *D OAI21_X1 +*I _673_:B I *D OAI211_X1 *CAP 1 _343_:1 1.5775 2 _343_:2 1.05 @@ -9364,14 +9364,14 @@ resp_val O 2 _343_:2 _343_:3 0.005 3 _343_:3 _343_:4 8.4 4 _343_:4 _343_:5 0.005 -5 _672_/ZN _343_:1 2.115 -6 _673_/B _343_:5 4.105 +5 _672_:ZN _343_:1 2.115 +6 _673_:B _343_:5 4.105 *END *D_NET _344_ 4.86 *CONN -*I _673_/ZN O *D OAI211_X1 -*I _674_/B I *D MUX2_X1 +*I _673_:ZN O *D OAI211_X1 +*I _674_:B I *D MUX2_X1 *CAP 1 _344_:1 0.7275 2 _344_:2 1.05 @@ -9381,27 +9381,27 @@ resp_val O 1 _344_:1 _344_:2 0.005 2 _344_:2 _344_:3 4.2 3 _344_:3 _344_:4 0.005 -4 _673_/ZN _344_:1 2.915 -5 _674_/B _344_:4 2.615 +4 _673_:ZN _344_:1 2.915 +5 _674_:B _344_:4 2.615 *END *D_NET _345_ 3.82 *CONN -*I _675_/ZN O *D NOR2_X1 -*I _676_/A2 I *D NOR2_X1 +*I _675_:ZN O *D NOR2_X1 +*I _676_:A2 I *D NOR2_X1 *CAP 1 _345_:1 1.57 2 _345_:2 1.39 *RES 1 _345_:2 _345_:1 4.2 -2 _675_/ZN _345_:1 2.085 -3 _676_/A2 _345_:2 1.365 +2 _675_:ZN _345_:1 2.085 +3 _676_:A2 _345_:2 1.365 *END *D_NET _346_ 5.51 *CONN -*I _676_/ZN O *D NOR2_X1 -*I _677_/A I *D XNOR2_X1 +*I _676_:ZN O *D NOR2_X1 +*I _677_:A I *D XNOR2_X1 *CAP 1 _346_:1 1.3125 2 _346_:2 1.05 @@ -9413,14 +9413,14 @@ resp_val O 2 _346_:2 _346_:3 0.005 3 _346_:3 _346_:4 4.2 4 _346_:4 _346_:5 0.005 -5 _676_/ZN _346_:1 1.055 -6 _677_/A _346_:5 1.575 +5 _676_:ZN _346_:1 1.055 +6 _677_:A _346_:5 1.575 *END *D_NET _347_ 8.16 *CONN -*I _678_/ZN O *D AND2_X1 -*I _681_/B1 I *D OAI21_X1 +*I _678_:ZN O *D AND2_X1 +*I _681_:B1 I *D OAI21_X1 *CAP 1 _347_:1 0.67 2 _347_:2 2.1 @@ -9432,14 +9432,14 @@ resp_val O 2 _347_:2 _347_:3 8.4 3 _347_:3 _347_:4 0.005 4 _347_:4 _347_:5 4.2 -5 _678_/ZN _347_:1 2.685 -6 _681_/B1 _347_:5 1.045 +5 _678_:ZN _347_:1 2.685 +6 _681_:B1 _347_:5 1.045 *END *D_NET _348_ 29.04 *CONN -*I _679_/ZN O *D OAI21_X1 -*I _680_/A I *D OAI21_X1 +*I _679_:ZN O *D OAI21_X1 +*I _680_:A I *D OAI21_X1 *CAP 1 _348_:1 12.9775 2 _348_:2 12.6 @@ -9451,14 +9451,14 @@ resp_val O 2 _348_:2 _348_:3 0.005 3 _348_:3 _348_:4 4.2 4 _348_:4 _348_:5 0.005 -5 _679_/ZN _348_:5 1.975 -6 _680_/A _348_:1 1.515 +5 _679_:ZN _348_:5 1.975 +6 _680_:A _348_:1 1.515 *END *D_NET _349_ 5.61 *CONN -*I _680_/ZN O *D OAI21_X1 -*I _681_/B2 I *D OAI21_X1 +*I _680_:ZN O *D OAI21_X1 +*I _681_:B2 I *D OAI21_X1 *CAP 1 _349_:1 1.4725 2 _349_:2 1.05 @@ -9470,27 +9470,27 @@ resp_val O 2 _349_:2 _349_:3 0.005 3 _349_:3 _349_:4 4.2 4 _349_:4 _349_:5 0.005 -5 _680_/ZN _349_:5 1.135 -6 _681_/B2 _349_:1 1.695 +5 _680_:ZN _349_:5 1.135 +6 _681_:B2 _349_:1 1.695 *END *D_NET _350_ 3.91 *CONN -*I _681_/ZN O *D OAI21_X1 -*I _682_/A I *D OAI21_X1 +*I _681_:ZN O *D OAI21_X1 +*I _682_:A I *D OAI21_X1 *CAP 1 _350_:1 1.3225 2 _350_:2 1.6825 *RES 1 _350_:1 _350_:2 4.2 -2 _681_/ZN _350_:1 1.095 -3 _682_/A _350_:2 2.535 +2 _681_:ZN _350_:1 1.095 +3 _682_:A _350_:2 2.535 *END *D_NET _351_ 10.425 *CONN -*I _683_/Z O *D MUX2_X1 -*I _686_/B I *D MUX2_X1 +*I _683_:Z O *D MUX2_X1 +*I _686_:B I *D MUX2_X1 *CAP 1 _351_:1 0.8225 2 _351_:2 2.1 @@ -9502,20 +9502,20 @@ resp_val O 2 _351_:2 _351_:3 8.4 3 _351_:3 _351_:4 0.005 4 _351_:4 _351_:5 4.2 -5 _683_/Z _351_:5 4.965 -6 _686_/B _351_:1 3.295 +5 _683_:Z _351_:5 4.965 +6 _686_:B _351_:1 3.295 *END *D_NET _352_ 76.225 *CONN -*I _684_/ZN O *D NAND2_X2 -*I _685_/A I *D BUF_X2 -*I _706_/S I *D MUX2_X1 -*I _708_/S I *D MUX2_X1 -*I _710_/S I *D MUX2_X1 -*I _712_/S I *D MUX2_X1 -*I _714_/S I *D MUX2_X1 -*I _716_/S I *D MUX2_X1 +*I _684_:ZN O *D NAND2_X2 +*I _685_:A I *D BUF_X2 +*I _706_:S I *D MUX2_X1 +*I _708_:S I *D MUX2_X1 +*I _710_:S I *D MUX2_X1 +*I _712_:S I *D MUX2_X1 +*I _714_:S I *D MUX2_X1 +*I _716_:S I *D MUX2_X1 *CAP 1 _352_:1 6.4575 2 _352_:2 7.35 @@ -9561,29 +9561,29 @@ resp_val O 19 _352_:14 _352_:21 12.6 20 _352_:21 _352_:22 0.005 21 _352_:20 _352_:22 12.6 -22 _684_/ZN _352_:11 2.125 -23 _685_/A _352_:15 2.075 -24 _706_/S _352_:3 3.595 -25 _708_/S _352_:19 1.175 -26 _710_/S _352_:10 1.595 -27 _712_/S _352_:1 0.635 -28 _714_/S _352_:16 2.435 -29 _716_/S _352_:20 4.455 +22 _684_:ZN _352_:11 2.125 +23 _685_:A _352_:15 2.075 +24 _706_:S _352_:3 3.595 +25 _708_:S _352_:19 1.175 +26 _710_:S _352_:10 1.595 +27 _712_:S _352_:1 0.635 +28 _714_:S _352_:16 2.435 +29 _716_:S _352_:20 4.455 *END *D_NET _353_ 145.685 *CONN -*I _685_/Z O *D BUF_X2 -*I _686_/S I *D MUX2_X1 -*I _688_/S I *D MUX2_X1 -*I _690_/S I *D MUX2_X1 -*I _692_/S I *D MUX2_X1 -*I _694_/S I *D MUX2_X1 -*I _696_/S I *D MUX2_X1 -*I _698_/S I *D MUX2_X1 -*I _700_/S I *D MUX2_X1 -*I _702_/S I *D MUX2_X1 -*I _704_/S I *D MUX2_X1 +*I _685_:Z O *D BUF_X2 +*I _686_:S I *D MUX2_X1 +*I _688_:S I *D MUX2_X1 +*I _690_:S I *D MUX2_X1 +*I _692_:S I *D MUX2_X1 +*I _694_:S I *D MUX2_X1 +*I _696_:S I *D MUX2_X1 +*I _698_:S I *D MUX2_X1 +*I _700_:S I *D MUX2_X1 +*I _702_:S I *D MUX2_X1 +*I _704_:S I *D MUX2_X1 *CAP 1 _353_:1 4.5325 2 _353_:2 4.6425 @@ -9649,48 +9649,48 @@ resp_val O 29 _353_:30 _353_:31 29.4 30 _353_:31 _353_:32 0.005 31 _353_:32 _353_:13 8.4 -32 _685_/Z _353_:13 3.635 -33 _686_/S _353_:2 1.775 -34 _688_/S _353_:14 3.375 -35 _690_/S _353_:3 3.575 -36 _692_/S _353_:7 1.315 -37 _694_/S _353_:22 1.095 -38 _696_/S _353_:23 2.075 -39 _698_/S _353_:18 5.015 -40 _700_/S _353_:1 1.335 -41 _702_/S _353_:8 1.535 -42 _704_/S _353_:12 2.095 +32 _685_:Z _353_:13 3.635 +33 _686_:S _353_:2 1.775 +34 _688_:S _353_:14 3.375 +35 _690_:S _353_:3 3.575 +36 _692_:S _353_:7 1.315 +37 _694_:S _353_:22 1.095 +38 _696_:S _353_:23 2.075 +39 _698_:S _353_:18 5.015 +40 _700_:S _353_:1 1.335 +41 _702_:S _353_:8 1.535 +42 _704_:S _353_:12 2.095 *END *D_NET _354_ 3.32 *CONN -*I _687_/Z O *D MUX2_X1 -*I _688_/B I *D MUX2_X1 +*I _687_:Z O *D MUX2_X1 +*I _688_:B I *D MUX2_X1 *CAP 1 _354_:1 1.265 2 _354_:2 1.445 *RES 1 _354_:1 _354_:2 4.2 -2 _687_/Z _354_:1 0.865 -3 _688_/B _354_:2 1.585 +2 _687_:Z _354_:1 0.865 +3 _688_:B _354_:2 1.585 *END *D_NET _355_ 2.545 *CONN -*I _689_/Z O *D MUX2_X1 -*I _690_/B I *D MUX2_X1 +*I _689_:Z O *D MUX2_X1 +*I _690_:B I *D MUX2_X1 *CAP 1 _355_:1 1.2725 *RES 1 _355_:1 _355_:1 0.005 -2 _689_/Z _355_:1 3.045 -3 _690_/B _355_:1 2.055 +2 _689_:Z _355_:1 3.045 +3 _690_:B _355_:1 2.055 *END *D_NET _356_ 6.54 *CONN -*I _691_/Z O *D MUX2_X1 -*I _692_/B I *D MUX2_X1 +*I _691_:Z O *D MUX2_X1 +*I _692_:B I *D MUX2_X1 *CAP 1 _356_:1 0.545 2 _356_:2 1.05 @@ -9702,14 +9702,14 @@ resp_val O 2 _356_:2 _356_:3 4.2 3 _356_:3 _356_:4 0.005 4 _356_:5 _356_:4 4.2 -5 _691_/Z _356_:1 2.185 -6 _692_/B _356_:5 2.505 +5 _691_:Z _356_:1 2.185 +6 _692_:B _356_:5 2.505 *END *D_NET _357_ 4.025 *CONN -*I _693_/Z O *D MUX2_X1 -*I _694_/B I *D MUX2_X1 +*I _693_:Z O *D MUX2_X1 +*I _694_:B I *D MUX2_X1 *CAP 1 _357_:1 0.6325 2 _357_:2 1.05 @@ -9719,27 +9719,27 @@ resp_val O 1 _357_:1 _357_:2 0.005 2 _357_:2 _357_:3 4.2 3 _357_:3 _357_:4 0.005 -4 _693_/Z _357_:4 1.325 -5 _694_/B _357_:1 2.535 +4 _693_:Z _357_:4 1.325 +5 _694_:B _357_:1 2.535 *END *D_NET _358_ 3.73 *CONN -*I _695_/Z O *D MUX2_X1 -*I _696_/B I *D MUX2_X1 +*I _695_:Z O *D MUX2_X1 +*I _696_:B I *D MUX2_X1 *CAP 1 _358_:1 1.295 2 _358_:2 1.62 *RES 1 _358_:1 _358_:2 4.2 -2 _695_/Z _358_:1 0.985 -3 _696_/B _358_:2 2.285 +2 _695_:Z _358_:1 0.985 +3 _696_:B _358_:2 2.285 *END *D_NET _359_ 6.385 *CONN -*I _697_/Z O *D MUX2_X1 -*I _698_/B I *D MUX2_X1 +*I _697_:Z O *D MUX2_X1 +*I _698_:B I *D MUX2_X1 *CAP 1 _359_:1 0.395 2 _359_:2 1.05 @@ -9751,14 +9751,14 @@ resp_val O 2 _359_:2 _359_:3 4.2 3 _359_:3 _359_:4 0.005 4 _359_:5 _359_:4 4.2 -5 _697_/Z _359_:1 1.585 -6 _698_/B _359_:5 2.795 +5 _697_:Z _359_:1 1.585 +6 _698_:B _359_:5 2.795 *END *D_NET _360_ 7.28 *CONN -*I _699_/Z O *D MUX2_X1 -*I _700_/B I *D MUX2_X1 +*I _699_:Z O *D MUX2_X1 +*I _700_:B I *D MUX2_X1 *CAP 1 _360_:1 1.515 2 _360_:2 1.05 @@ -9770,14 +9770,14 @@ resp_val O 2 _360_:2 _360_:3 0.005 3 _360_:3 _360_:4 4.2 4 _360_:4 _360_:5 0.005 -5 _699_/Z _360_:5 4.305 -6 _700_/B _360_:1 1.865 +5 _699_:Z _360_:5 4.305 +6 _700_:B _360_:1 1.865 *END *D_NET _361_ 6.765 *CONN -*I _701_/Z O *D MUX2_X1 -*I _702_/B I *D MUX2_X1 +*I _701_:Z O *D MUX2_X1 +*I _702_:B I *D MUX2_X1 *CAP 1 _361_:1 0.82 2 _361_:2 1.05 @@ -9789,14 +9789,14 @@ resp_val O 2 _361_:2 _361_:3 4.2 3 _361_:3 _361_:4 0.005 4 _361_:5 _361_:4 4.2 -5 _701_/Z _361_:1 3.285 -6 _702_/B _361_:5 1.855 +5 _701_:Z _361_:1 3.285 +6 _702_:B _361_:5 1.855 *END *D_NET _362_ 7.75 *CONN -*I _703_/Z O *D MUX2_X1 -*I _704_/B I *D MUX2_X1 +*I _703_:Z O *D MUX2_X1 +*I _704_:B I *D MUX2_X1 *CAP 1 _362_:1 1.5 2 _362_:2 1.05 @@ -9810,14 +9810,14 @@ resp_val O 3 _362_:3 _362_:4 4.2 4 _362_:4 _362_:5 0.005 5 _362_:5 _362_:6 4.2 -6 _703_/Z _362_:1 1.805 -7 _704_/B _362_:6 1.105 +6 _703_:Z _362_:1 1.805 +7 _704_:B _362_:6 1.105 *END *D_NET _363_ 3.72 *CONN -*I _705_/Z O *D MUX2_X1 -*I _706_/B I *D MUX2_X1 +*I _705_:Z O *D MUX2_X1 +*I _706_:B I *D MUX2_X1 *CAP 1 _363_:1 0.6 2 _363_:2 1.05 @@ -9827,39 +9827,39 @@ resp_val O 1 _363_:1 _363_:2 0.005 2 _363_:2 _363_:3 4.2 3 _363_:3 _363_:4 0.005 -4 _705_/Z _363_:4 0.845 -5 _706_/B _363_:1 2.405 +4 _705_:Z _363_:4 0.845 +5 _706_:B _363_:1 2.405 *END *D_NET _364_ 6.37 *CONN -*I _707_/Z O *D MUX2_X1 -*I _708_/B I *D MUX2_X1 +*I _707_:Z O *D MUX2_X1 +*I _708_:B I *D MUX2_X1 *CAP 1 _364_:1 2.68 2 _364_:2 2.605 *RES 1 _364_:1 _364_:2 8.4 -2 _707_/Z _364_:1 2.325 -3 _708_/B _364_:2 2.025 +2 _707_:Z _364_:1 2.325 +3 _708_:B _364_:2 2.025 *END *D_NET _365_ 2.165 *CONN -*I _709_/Z O *D MUX2_X1 -*I _710_/B I *D MUX2_X1 +*I _709_:Z O *D MUX2_X1 +*I _710_:B I *D MUX2_X1 *CAP 1 _365_:1 1.0825 *RES 1 _365_:1 _365_:1 0.005 -2 _709_/Z _365_:1 1.145 -3 _710_/B _365_:1 3.195 +2 _709_:Z _365_:1 1.145 +3 _710_:B _365_:1 3.195 *END *D_NET _366_ 4.73 *CONN -*I _711_/Z O *D MUX2_X1 -*I _712_/B I *D MUX2_X1 +*I _711_:Z O *D MUX2_X1 +*I _712_:B I *D MUX2_X1 *CAP 1 _366_:1 0.505 2 _366_:2 1.05 @@ -9869,14 +9869,14 @@ resp_val O 1 _366_:1 _366_:2 0.005 2 _366_:2 _366_:3 4.2 3 _366_:3 _366_:4 0.005 -4 _711_/Z _366_:4 3.245 -5 _712_/B _366_:1 2.025 +4 _711_:Z _366_:4 3.245 +5 _712_:B _366_:1 2.025 *END *D_NET _367_ 8.6 *CONN -*I _713_/Z O *D MUX2_X1 -*I _714_/B I *D MUX2_X1 +*I _713_:Z O *D MUX2_X1 +*I _714_:B I *D MUX2_X1 *CAP 1 _367_:1 1.31 2 _367_:2 1.05 @@ -9890,14 +9890,14 @@ resp_val O 3 _367_:3 _367_:4 4.2 4 _367_:4 _367_:5 0.005 5 _367_:5 _367_:6 4.2 -6 _713_/Z _367_:1 1.045 -7 _714_/B _367_:6 3.565 +6 _713_:Z _367_:1 1.045 +7 _714_:B _367_:6 3.565 *END *D_NET _368_ 7.27 *CONN -*I _715_/Z O *D MUX2_X1 -*I _716_/B I *D MUX2_X1 +*I _715_:Z O *D MUX2_X1 +*I _716_:B I *D MUX2_X1 *CAP 1 _368_:1 0.87 2 _368_:2 1.05 @@ -9909,14 +9909,14 @@ resp_val O 2 _368_:2 _368_:3 4.2 3 _368_:3 _368_:4 0.005 4 _368_:5 _368_:4 4.2 -5 _715_/Z _368_:1 3.485 -6 _716_/B _368_:5 2.665 +5 _715_:Z _368_:1 3.485 +6 _716_:B _368_:5 2.665 *END *D_NET _369_ 6.735 *CONN -*I _683_/B I *D MUX2_X1 -*I _811_/Z O *D CLKBUF_X1 +*I _683_:B I *D MUX2_X1 +*I _811_:Z O *D CLKBUF_X1 *CAP 1 _369_:1 0.7175 2 _369_:2 2.1 @@ -9926,14 +9926,14 @@ resp_val O 1 _369_:1 _369_:2 0.005 2 _369_:2 _369_:3 8.4 3 _369_:3 _369_:4 0.005 -4 _683_/B _369_:1 2.875 -5 _811_/Z _369_:4 2.205 +4 _683_:B _369_:1 2.875 +5 _811_:Z _369_:4 2.205 *END *D_NET _370_ 73.395 *CONN -*I _705_/B I *D MUX2_X1 -*I _831_/Z O *D CLKBUF_X1 +*I _705_:B I *D MUX2_X1 +*I _831_:Z O *D CLKBUF_X1 *CAP 1 _370_:1 27.6975 2 _370_:2 27.3 @@ -9945,27 +9945,27 @@ resp_val O 2 _370_:2 _370_:3 0.005 3 _370_:3 _370_:4 33.6 4 _370_:4 _370_:5 0.005 -5 _705_/B _370_:1 1.595 -6 _831_/Z _370_:5 2.405 +5 _705_:B _370_:1 1.595 +6 _831_:Z _370_:5 2.405 *END *D_NET _371_ 21.42 *CONN -*I _707_/B I *D MUX2_X1 -*I _833_/Z O *D CLKBUF_X1 +*I _707_:B I *D MUX2_X1 +*I _833_:Z O *D CLKBUF_X1 *CAP 1 _371_:1 10.045 2 _371_:2 10.115 *RES 1 _371_:1 _371_:2 37.8 -2 _707_/B _371_:2 2.665 -3 _833_/Z _371_:1 2.385 +2 _707_:B _371_:2 2.665 +3 _833_:Z _371_:1 2.385 *END *D_NET _372_ 54.31 *CONN -*I _709_/B I *D MUX2_X1 -*I _835_/Z O *D CLKBUF_X1 +*I _709_:B I *D MUX2_X1 +*I _835_:Z O *D CLKBUF_X1 *CAP 1 _372_:1 25.88 2 _372_:2 25.2 @@ -9977,14 +9977,14 @@ resp_val O 2 _372_:2 _372_:3 0.005 3 _372_:3 _372_:4 4.2 4 _372_:4 _372_:5 0.005 -5 _709_/B _372_:1 2.725 -6 _835_/Z _372_:5 0.905 +5 _709_:B _372_:1 2.725 +6 _835_:Z _372_:5 0.905 *END *D_NET _373_ 4.235 *CONN -*I _711_/B I *D MUX2_X1 -*I _837_/Z O *D CLKBUF_X1 +*I _711_:B I *D MUX2_X1 +*I _837_:Z O *D CLKBUF_X1 *CAP 1 _373_:1 0.5875 2 _373_:2 1.05 @@ -9994,14 +9994,14 @@ resp_val O 1 _373_:1 _373_:2 0.005 2 _373_:2 _373_:3 4.2 3 _373_:3 _373_:4 0.005 -4 _711_/B _373_:1 2.355 -5 _837_/Z _373_:4 1.925 +4 _711_:B _373_:1 2.355 +5 _837_:Z _373_:4 1.925 *END *D_NET _374_ 8.51 *CONN -*I _713_/B I *D MUX2_X1 -*I _839_/Z O *D CLKBUF_X1 +*I _713_:B I *D MUX2_X1 +*I _839_:Z O *D CLKBUF_X1 *CAP 1 _374_:1 0.92 2 _374_:2 2.1 @@ -10013,14 +10013,14 @@ resp_val O 2 _374_:2 _374_:3 8.4 3 _374_:3 _374_:4 0.005 4 _374_:4 _374_:5 4.2 -5 _713_/B _374_:5 0.745 -6 _839_/Z _374_:1 3.685 +5 _713_:B _374_:5 0.745 +6 _839_:Z _374_:1 3.685 *END *D_NET _375_ 37.52 *CONN -*I _715_/B I *D MUX2_X1 -*I _841_/Z O *D CLKBUF_X1 +*I _715_:B I *D MUX2_X1 +*I _841_:Z O *D CLKBUF_X1 *CAP 1 _375_:1 0.295 2 _375_:2 17.85 @@ -10030,14 +10030,14 @@ resp_val O 1 _375_:1 _375_:2 0.005 2 _375_:2 _375_:3 71.4 3 _375_:3 _375_:4 0.005 -4 _715_/B _375_:4 2.465 -5 _841_/Z _375_:1 1.185 +4 _715_:B _375_:4 2.465 +5 _841_:Z _375_:1 1.185 *END *D_NET _376_ 25.315 *CONN -*I _467_/A I *D OAI21_X1 -*I _764_/Z O *D CLKBUF_X1 +*I _467_:A I *D OAI21_X1 +*I _764_:Z O *D CLKBUF_X1 *CAP 1 _376_:1 9.9775 2 _376_:2 9.45 @@ -10049,14 +10049,14 @@ resp_val O 2 _376_:2 _376_:3 0.005 3 _376_:3 _376_:4 8.4 4 _376_:4 _376_:5 0.005 -5 _467_/A _376_:1 2.115 -6 _764_/Z _376_:5 2.325 +5 _467_:A _376_:1 2.115 +6 _764_:Z _376_:5 2.325 *END *D_NET _377_ 37.995 *CONN -*I _552_/A I *D OAI21_X1 -*I _767_/Z O *D CLKBUF_X1 +*I _552_:A I *D OAI21_X1 +*I _767_:Z O *D CLKBUF_X1 *CAP 1 _377_:1 2.1 2 _377_:2 2.6425 @@ -10068,14 +10068,14 @@ resp_val O 2 _377_:1 _377_:3 0.005 3 _377_:3 _377_:4 63 4 _377_:4 _377_:5 0.005 -5 _552_/A _377_:2 2.175 -6 _767_/Z _377_:5 2.425 +5 _552_:A _377_:2 2.175 +6 _767_:Z _377_:5 2.425 *END *D_NET _378_ 18.1 *CONN -*I _561_/A I *D OAI21_X1 -*I _770_/Z O *D CLKBUF_X1 +*I _561_:A I *D OAI21_X1 +*I _770_:Z O *D CLKBUF_X1 *CAP 1 _378_:1 1.775 2 _378_:2 1.05 @@ -10089,14 +10089,14 @@ resp_val O 3 _378_:3 _378_:4 21 4 _378_:4 _378_:5 0.005 5 _378_:6 _378_:5 4.2 -6 _561_/A _378_:6 3.905 -7 _770_/Z _378_:1 2.905 +6 _561_:A _378_:6 3.905 +7 _770_:Z _378_:1 2.905 *END *D_NET _379_ 11.84 *CONN -*I _567_/A I *D OAI21_X1 -*I _773_/Z O *D CLKBUF_X1 +*I _567_:A I *D OAI21_X1 +*I _773_:Z O *D CLKBUF_X1 *CAP 1 _379_:1 3.605 2 _379_:2 3.15 @@ -10108,14 +10108,14 @@ resp_val O 2 _379_:2 _379_:3 0.005 3 _379_:3 _379_:4 4.2 4 _379_:4 _379_:5 0.005 -5 _567_/A _379_:1 1.825 -6 _773_/Z _379_:5 5.065 +5 _567_:A _379_:1 1.825 +6 _773_:Z _379_:5 5.065 *END *D_NET _380_ 50.155 *CONN -*I _687_/B I *D MUX2_X1 -*I _813_/Z O *D CLKBUF_X1 +*I _687_:B I *D MUX2_X1 +*I _813_:Z O *D CLKBUF_X1 *CAP 1 _380_:1 22.575 2 _380_:2 22.05 @@ -10127,14 +10127,14 @@ resp_val O 2 _380_:2 _380_:3 0.005 3 _380_:3 _380_:4 8.4 4 _380_:4 _380_:5 0.005 -5 _687_/B _380_:5 1.615 -6 _813_/Z _380_:1 2.105 +5 _687_:B _380_:5 1.615 +6 _813_:Z _380_:1 2.105 *END *D_NET _381_ 58.725 *CONN -*I _576_/A I *D OAI21_X1 -*I _776_/Z O *D CLKBUF_X1 +*I _576_:A I *D OAI21_X1 +*I _776_:Z O *D CLKBUF_X1 *CAP 1 _381_:1 2.515 2 _381_:2 2.1 @@ -10146,14 +10146,14 @@ resp_val O 2 _381_:2 _381_:3 0.005 3 _381_:3 _381_:4 105 4 _381_:4 _381_:5 0.005 -5 _576_/A _381_:5 2.395 -6 _776_/Z _381_:1 1.665 +5 _576_:A _381_:5 2.395 +6 _776_:Z _381_:1 1.665 *END *D_NET _382_ 17.09 *CONN -*I _585_/A I *D OAI21_X1 -*I _779_/Z O *D CLKBUF_X1 +*I _585_:A I *D OAI21_X1 +*I _779_:Z O *D CLKBUF_X1 *CAP 1 _382_:1 0.66 2 _382_:2 6.3 @@ -10165,14 +10165,14 @@ resp_val O 2 _382_:2 _382_:3 25.2 3 _382_:3 _382_:4 0.005 4 _382_:4 _382_:5 4.2 -5 _585_/A _382_:1 2.645 -6 _779_/Z _382_:5 2.145 +5 _585_:A _382_:1 2.645 +6 _779_:Z _382_:5 2.145 *END *D_NET _383_ 7.56 *CONN -*I _593_/A I *D OAI21_X1 -*I _782_/Z O *D CLKBUF_X1 +*I _593_:A I *D OAI21_X1 +*I _782_:Z O *D CLKBUF_X1 *CAP 1 _383_:1 2.1 2 _383_:2 2.385 @@ -10184,14 +10184,14 @@ resp_val O 2 _383_:1 _383_:3 0.005 3 _383_:3 _383_:4 4.2 4 _383_:4 _383_:5 0.005 -5 _593_/A _383_:2 1.145 -6 _782_/Z _383_:5 1.385 +5 _593_:A _383_:2 1.145 +6 _782_:Z _383_:5 1.385 *END *D_NET _384_ 34.61 *CONN -*I _601_/A I *D OAI21_X1 -*I _785_/Z O *D CLKBUF_X1 +*I _601_:A I *D OAI21_X1 +*I _785_:Z O *D CLKBUF_X1 *CAP 1 _384_:1 14.7 2 _384_:2 14.865 @@ -10203,14 +10203,14 @@ resp_val O 2 _384_:1 _384_:3 0.005 3 _384_:3 _384_:4 8.4 4 _384_:4 _384_:5 0.005 -5 _601_/A _384_:5 1.365 -6 _785_/Z _384_:2 0.665 +5 _601_:A _384_:5 1.365 +6 _785_:Z _384_:2 0.665 *END *D_NET _385_ 47.615 *CONN -*I _610_/A I *D OAI21_X1 -*I _788_/Z O *D CLKBUF_X1 +*I _610_:A I *D OAI21_X1 +*I _788_:Z O *D CLKBUF_X1 *CAP 1 _385_:1 0.5725 2 _385_:2 23.1 @@ -10220,14 +10220,14 @@ resp_val O 1 _385_:1 _385_:2 0.005 2 _385_:2 _385_:3 92.4 3 _385_:3 _385_:4 0.005 -4 _610_/A _385_:1 2.295 -5 _788_/Z _385_:4 0.545 +4 _610_:A _385_:1 2.295 +5 _788_:Z _385_:4 0.545 *END *D_NET _386_ 21.78 *CONN -*I _619_/A I *D OAI21_X1 -*I _791_/Z O *D CLKBUF_X1 +*I _619_:A I *D OAI21_X1 +*I _791_:Z O *D CLKBUF_X1 *CAP 1 _386_:1 6.3 2 _386_:2 7.18 @@ -10241,14 +10241,14 @@ resp_val O 3 _386_:3 _386_:4 8.4 4 _386_:4 _386_:5 0.005 5 _386_:6 _386_:5 4.2 -6 _619_/A _386_:6 2.245 -7 _791_/Z _386_:2 3.525 +6 _619_:A _386_:6 2.245 +7 _791_:Z _386_:2 3.525 *END *D_NET _387_ 6.75 *CONN -*I _628_/A I *D OAI21_X1 -*I _794_/Z O *D CLKBUF_X1 +*I _628_:A I *D OAI21_X1 +*I _794_:Z O *D CLKBUF_X1 *CAP 1 _387_:1 1.535 2 _387_:2 1.05 @@ -10260,27 +10260,27 @@ resp_val O 2 _387_:2 _387_:3 0.005 3 _387_:3 _387_:4 4.2 4 _387_:4 _387_:5 0.005 -5 _628_/A _387_:5 3.165 -6 _794_/Z _387_:1 1.945 +5 _628_:A _387_:5 3.165 +6 _794_:Z _387_:1 1.945 *END *D_NET _388_ 45.915 *CONN -*I _637_/A I *D OAI21_X1 -*I _797_/Z O *D CLKBUF_X1 +*I _637_:A I *D OAI21_X1 +*I _797_:Z O *D CLKBUF_X1 *CAP 1 _388_:1 22.3275 2 _388_:2 22.68 *RES 1 _388_:1 _388_:2 88.2 -2 _637_/A _388_:1 1.115 -3 _797_/Z _388_:2 2.525 +2 _637_:A _388_:1 1.115 +3 _797_:Z _388_:2 2.525 *END *D_NET _389_ 37.88 *CONN -*I _654_/A I *D OAI21_X1 -*I _800_/Z O *D CLKBUF_X1 +*I _654_:A I *D OAI21_X1 +*I _800_:Z O *D CLKBUF_X1 *CAP 1 _389_:1 2.59 2 _389_:2 2.1 @@ -10292,27 +10292,27 @@ resp_val O 2 _389_:2 _389_:3 0.005 3 _389_:3 _389_:4 63 4 _389_:4 _389_:5 0.005 -5 _654_/A _389_:5 2.405 -6 _800_/Z _389_:1 1.965 +5 _654_:A _389_:5 2.405 +6 _800_:Z _389_:1 1.965 *END *D_NET _390_ 7.695 *CONN -*I _662_/A I *D OAI21_X1 -*I _803_/Z O *D CLKBUF_X1 +*I _662_:A I *D OAI21_X1 +*I _803_:Z O *D CLKBUF_X1 *CAP 1 _390_:1 3.345 2 _390_:2 2.6025 *RES 1 _390_:1 _390_:2 8.4 -2 _662_/A _390_:2 2.015 -3 _803_/Z _390_:1 4.985 +2 _662_:A _390_:2 2.015 +3 _803_:Z _390_:1 4.985 *END *D_NET _391_ 30.02 *CONN -*I _689_/B I *D MUX2_X1 -*I _815_/Z O *D CLKBUF_X1 +*I _689_:B I *D MUX2_X1 +*I _815_:Z O *D CLKBUF_X1 *CAP 1 _391_:1 1.895 2 _391_:2 1.05 @@ -10324,14 +10324,14 @@ resp_val O 2 _391_:2 _391_:3 0.005 3 _391_:3 _391_:4 50.4 4 _391_:4 _391_:5 0.005 -5 _689_/B _391_:1 3.385 -6 _815_/Z _391_:5 2.065 +5 _689_:B _391_:1 3.385 +6 _815_:Z _391_:5 2.065 *END *D_NET _392_ 73.355 *CONN -*I _672_/A I *D OAI21_X1 -*I _806_/Z O *D CLKBUF_X1 +*I _672_:A I *D OAI21_X1 +*I _806_:Z O *D CLKBUF_X1 *CAP 1 _392_:1 30.45 2 _392_:2 30.805 @@ -10343,14 +10343,14 @@ resp_val O 2 _392_:1 _392_:3 0.005 3 _392_:3 _392_:4 21 4 _392_:4 _392_:5 0.005 -5 _672_/A _392_:5 2.495 -6 _806_/Z _392_:2 1.425 +5 _672_:A _392_:5 2.495 +6 _806_:Z _392_:2 1.425 *END *D_NET _393_ 22.415 *CONN -*I _679_/A I *D OAI21_X1 -*I _809_/Z O *D CLKBUF_X1 +*I _679_:A I *D OAI21_X1 +*I _809_:Z O *D CLKBUF_X1 *CAP 1 _393_:1 0.2625 2 _393_:2 1.05 @@ -10362,14 +10362,14 @@ resp_val O 2 _393_:2 _393_:3 4.2 3 _393_:3 _393_:4 0.005 4 _393_:4 _393_:5 37.8 -5 _679_/A _393_:1 1.055 -6 _809_/Z _393_:5 1.785 +5 _679_:A _393_:1 1.055 +6 _809_:Z _393_:5 1.785 *END *D_NET _394_ 62.145 *CONN -*I _691_/B I *D MUX2_X1 -*I _817_/Z O *D CLKBUF_X1 +*I _691_:B I *D MUX2_X1 +*I _817_:Z O *D CLKBUF_X1 *CAP 1 _394_:1 6.3 2 _394_:2 6.595 @@ -10381,14 +10381,14 @@ resp_val O 2 _394_:1 _394_:3 0.005 3 _394_:3 _394_:4 96.6 4 _394_:4 _394_:5 0.005 -5 _691_/B _394_:5 1.315 -6 _817_/Z _394_:2 1.185 +5 _691_:B _394_:5 1.315 +6 _817_:Z _394_:2 1.185 *END *D_NET _395_ 8.7 *CONN -*I _693_/B I *D MUX2_X1 -*I _819_/Z O *D CLKBUF_X1 +*I _693_:B I *D MUX2_X1 +*I _819_:Z O *D CLKBUF_X1 *CAP 1 _395_:1 0.635 2 _395_:2 2.1 @@ -10400,14 +10400,14 @@ resp_val O 2 _395_:2 _395_:3 8.4 3 _395_:3 _395_:4 0.005 4 _395_:4 _395_:5 4.2 -5 _693_/B _395_:1 2.545 -6 _819_/Z _395_:5 2.265 +5 _693_:B _395_:1 2.545 +6 _819_:Z _395_:5 2.265 *END *D_NET _396_ 41.245 *CONN -*I _695_/B I *D MUX2_X1 -*I _821_/Z O *D CLKBUF_X1 +*I _695_:B I *D MUX2_X1 +*I _821_:Z O *D CLKBUF_X1 *CAP 1 _396_:1 17.85 2 _396_:2 17.9525 @@ -10419,14 +10419,14 @@ resp_val O 2 _396_:1 _396_:3 0.005 3 _396_:3 _396_:4 8.4 4 _396_:4 _396_:5 0.005 -5 _695_/B _396_:2 0.415 -6 _821_/Z _396_:5 2.285 +5 _695_:B _396_:2 0.415 +6 _821_:Z _396_:5 2.285 *END *D_NET _397_ 63.57 *CONN -*I _697_/B I *D MUX2_X1 -*I _823_/Z O *D CLKBUF_X1 +*I _697_:B I *D MUX2_X1 +*I _823_:Z O *D CLKBUF_X1 *CAP 1 _397_:1 7.335 2 _397_:2 6.3 @@ -10438,14 +10438,14 @@ resp_val O 2 _397_:2 _397_:3 0.005 3 _397_:3 _397_:4 96.6 4 _397_:4 _397_:5 0.005 -5 _697_/B _397_:5 1.205 -6 _823_/Z _397_:1 4.145 +5 _697_:B _397_:5 1.205 +6 _823_:Z _397_:1 4.145 *END *D_NET _398_ 25.295 *CONN -*I _699_/B I *D MUX2_X1 -*I _825_/Z O *D CLKBUF_X1 +*I _699_:B I *D MUX2_X1 +*I _825_:Z O *D CLKBUF_X1 *CAP 1 _398_:1 0.9125 2 _398_:2 7.35 @@ -10457,14 +10457,14 @@ resp_val O 2 _398_:2 _398_:3 29.4 3 _398_:3 _398_:4 0.005 4 _398_:4 _398_:5 12.6 -5 _699_/B _398_:1 3.655 -6 _825_/Z _398_:5 4.945 +5 _699_:B _398_:1 3.655 +6 _825_:Z _398_:5 4.945 *END *D_NET _399_ 4.08 *CONN -*I _701_/B I *D MUX2_X1 -*I _827_/Z O *D CLKBUF_X1 +*I _701_:B I *D MUX2_X1 +*I _827_:Z O *D CLKBUF_X1 *CAP 1 _399_:1 0.615 2 _399_:2 1.05 @@ -10474,14 +10474,14 @@ resp_val O 1 _399_:1 _399_:2 0.005 2 _399_:2 _399_:3 4.2 3 _399_:3 _399_:4 0.005 -4 _701_/B _399_:4 1.505 -5 _827_/Z _399_:1 2.465 +4 _701_:B _399_:4 1.505 +5 _827_:Z _399_:1 2.465 *END *D_NET _400_ 20.96 *CONN -*I _703_/B I *D MUX2_X1 -*I _829_/Z O *D CLKBUF_X1 +*I _703_:B I *D MUX2_X1 +*I _829_:Z O *D CLKBUF_X1 *CAP 1 _400_:1 0.495 2 _400_:2 8.4 @@ -10493,23 +10493,23 @@ resp_val O 2 _400_:2 _400_:3 33.6 3 _400_:3 _400_:4 0.005 4 _400_:4 _400_:5 4.2 -5 _703_/B _400_:5 2.145 -6 _829_/Z _400_:1 1.985 +5 _703_:B _400_:5 2.145 +6 _829_:Z _400_:1 1.985 *END *D_NET _401_ 132.67 *CONN -*I _459_/A I *D BUF_X2 -*I _548_/A2 I *D OR2_X1 -*I _701_/S I *D MUX2_X1 -*I _703_/S I *D MUX2_X1 -*I _705_/S I *D MUX2_X1 -*I _707_/S I *D MUX2_X1 -*I _709_/S I *D MUX2_X1 -*I _711_/S I *D MUX2_X1 -*I _713_/S I *D MUX2_X1 -*I _715_/S I *D MUX2_X1 -*I _759_/Z O *D BUF_X2 +*I _459_:A I *D BUF_X2 +*I _548_:A2 I *D OR2_X1 +*I _701_:S I *D MUX2_X1 +*I _703_:S I *D MUX2_X1 +*I _705_:S I *D MUX2_X1 +*I _707_:S I *D MUX2_X1 +*I _709_:S I *D MUX2_X1 +*I _711_:S I *D MUX2_X1 +*I _713_:S I *D MUX2_X1 +*I _715_:S I *D MUX2_X1 +*I _759_:Z O *D BUF_X2 *CAP 1 _401_:1 10.0025 2 _401_:2 13.65 @@ -10559,24 +10559,24 @@ resp_val O 21 _401_:18 _401_:1 37.8 22 _401_:18 _401_:24 0.005 23 _401_:24 _401_:9 25.2 -24 _459_/A _401_:5 3.405 -25 _548_/A2 _401_:1 2.215 -26 _701_/S _401_:7 1.695 -27 _703_/S _401_:6 3.855 -28 _705_/S _401_:18 1.795 -29 _707_/S _401_:8 3.335 -30 _709_/S _401_:11 4.515 -31 _711_/S _401_:13 3.875 -32 _713_/S _401_:14 1.995 -33 _715_/S _401_:20 1.215 -34 _759_/Z _401_:22 2.295 +24 _459_:A _401_:5 3.405 +25 _548_:A2 _401_:1 2.215 +26 _701_:S _401_:7 1.695 +27 _703_:S _401_:6 3.855 +28 _705_:S _401_:18 1.795 +29 _707_:S _401_:8 3.335 +30 _709_:S _401_:11 4.515 +31 _711_:S _401_:13 3.875 +32 _713_:S _401_:14 1.995 +33 _715_:S _401_:20 1.215 +34 _759_:Z _401_:22 2.295 *END *D_NET _402_ 19.06 *CONN -*I _460_/A4 I *D NAND4_X1 -*I _464_/C2 I *D AOI211_X1 -*I _760_/Z O *D CLKBUF_X1 +*I _460_:A4 I *D NAND4_X1 +*I _464_:C2 I *D AOI211_X1 +*I _760_:Z O *D CLKBUF_X1 *CAP 1 _402_:1 2.81 2 _402_:2 2.1 @@ -10594,18 +10594,18 @@ resp_val O 5 _402_:4 _402_:6 4.2 6 _402_:6 _402_:7 0.005 7 _402_:7 _402_:8 8.4 -8 _460_/A4 _402_:5 2.245 -9 _464_/C2 _402_:1 2.845 -10 _760_/Z _402_:8 3.645 +8 _460_:A4 _402_:5 2.245 +9 _464_:C2 _402_:1 2.845 +10 _760_:Z _402_:8 3.645 *END *D_NET _403_ 19.205 *CONN -*I _450_/A I *D INV_X1 -*I _454_/A2 I *D OR3_X1 -*I _464_/A I *D AOI211_X1 -*I _465_/A2 I *D OR3_X1 -*I _717_/Z O *D CLKBUF_X1 +*I _450_:A I *D INV_X1 +*I _454_:A2 I *D OR3_X1 +*I _464_:A I *D AOI211_X1 +*I _465_:A2 I *D OR3_X1 +*I _717_:Z O *D CLKBUF_X1 *CAP 1 _403_:1 1.86 2 _403_:2 1.6775 @@ -10627,19 +10627,19 @@ resp_val O 7 _403_:8 _403_:9 4.2 8 _403_:9 _403_:10 0.005 9 _403_:10 _403_:7 8.4 -10 _450_/A _403_:3 1.095 -11 _454_/A2 _403_:2 2.515 -12 _464_/A _403_:6 4.155 -13 _465_/A2 _403_:1 3.245 -14 _717_/Z _403_:8 2.225 +10 _450_:A _403_:3 1.095 +11 _454_:A2 _403_:2 2.515 +12 _464_:A _403_:6 4.155 +13 _465_:A2 _403_:1 3.245 +14 _717_:Z _403_:8 2.225 *END *D_NET _404_ 27.62 *CONN -*I _440_/Z O *D XOR2_X1 -*I _537_/A2 I *D NAND4_X1 -*I _542_/A2 I *D NOR3_X1 -*I _755_/A I *D CLKBUF_X1 +*I _440_:Z O *D XOR2_X1 +*I _537_:A2 I *D NAND4_X1 +*I _542_:A2 I *D NOR3_X1 +*I _755_:A I *D CLKBUF_X1 *CAP 1 _404_:1 7.35 2 _404_:2 3.15 @@ -10657,17 +10657,17 @@ resp_val O 5 _404_:7 _404_:8 0.005 6 _404_:8 _404_:2 8.4 7 _404_:5 _404_:1 29.4 -8 _440_/Z _404_:4 1.125 -9 _537_/A2 _404_:5 2.105 -10 _542_/A2 _404_:6 3.455 -11 _755_/A _404_:7 2.375 +8 _440_:Z _404_:4 1.125 +9 _537_:A2 _404_:5 2.105 +10 _542_:A2 _404_:6 3.455 +11 _755_:A _404_:7 2.375 *END *D_NET _405_ 20.205 *CONN -*I _633_/ZN O *D XNOR2_X1 -*I _634_/A2 I *D NAND2_X1 -*I _852_/A I *D CLKBUF_X1 +*I _633_:ZN O *D XNOR2_X1 +*I _634_:A2 I *D NAND2_X1 +*I _852_:A I *D CLKBUF_X1 *CAP 1 _405_:1 1.05 2 _405_:2 6.3 @@ -10685,16 +10685,16 @@ resp_val O 5 _405_:7 _405_:6 4.2 6 _405_:7 _405_:8 0.005 7 _405_:8 _405_:2 21 -8 _633_/ZN _405_:4 3.105 -9 _634_/A2 _405_:5 1.445 -10 _852_/A _405_:6 2.275 +8 _633_:ZN _405_:4 3.105 +9 _634_:A2 _405_:5 1.445 +10 _852_:A _405_:6 2.275 *END *D_NET _406_ 22.02 *CONN -*I _643_/ZN O *D XNOR2_X1 -*I _644_/A1 I *D AND2_X1 -*I _853_/A I *D CLKBUF_X1 +*I _643_:ZN O *D XNOR2_X1 +*I _644_:A1 I *D AND2_X1 +*I _853_:A I *D CLKBUF_X1 *CAP 1 _406_:1 2.1 2 _406_:2 2.845 @@ -10712,16 +10712,16 @@ resp_val O 5 _406_:6 _406_:5 4.2 6 _406_:7 _406_:8 0.005 7 _406_:8 _406_:3 16.8 -8 _643_/ZN _406_:7 2.485 -9 _644_/A1 _406_:2 2.985 -10 _853_/A _406_:6 0.785 +8 _643_:ZN _406_:7 2.485 +9 _644_:A1 _406_:2 2.985 +10 _853_:A _406_:6 0.785 *END *D_NET _407_ 15.33 *CONN -*I _652_/ZN O *D XNOR2_X1 -*I _653_/A1 I *D NAND2_X1 -*I _854_/A I *D CLKBUF_X1 +*I _652_:ZN O *D XNOR2_X1 +*I _653_:A1 I *D NAND2_X1 +*I _854_:A I *D CLKBUF_X1 *CAP 1 _407_:1 2.6825 2 _407_:2 1.05 @@ -10735,16 +10735,16 @@ resp_val O 3 _407_:3 _407_:4 8.4 4 _407_:4 _407_:5 0.005 5 _407_:6 _407_:5 8.4 -6 _652_/ZN _407_:1 2.605 -7 _653_/A1 _407_:1 3.935 -8 _854_/A _407_:6 3.135 +6 _652_:ZN _407_:1 2.605 +7 _653_:A1 _407_:1 3.935 +8 _854_:A _407_:6 3.135 *END *D_NET _408_ 16.205 *CONN -*I _660_/ZN O *D XNOR2_X1 -*I _661_/A1 I *D NAND2_X1 -*I _855_/A I *D CLKBUF_X1 +*I _660_:ZN O *D XNOR2_X1 +*I _661_:A1 I *D NAND2_X1 +*I _855_:A I *D CLKBUF_X1 *CAP 1 _408_:1 1.55 2 _408_:2 1.05 @@ -10762,16 +10762,16 @@ resp_val O 5 _408_:4 _408_:6 4.2 6 _408_:6 _408_:7 0.005 7 _408_:8 _408_:7 12.6 -8 _660_/ZN _408_:5 2.085 -9 _661_/A1 _408_:1 2.005 -10 _855_/A _408_:8 3.135 +8 _660_:ZN _408_:5 2.085 +9 _661_:A1 _408_:1 2.005 +10 _855_:A _408_:8 3.135 *END *D_NET _409_ 31.365 *CONN -*I _670_/ZN O *D NOR2_X1 -*I _671_/A1 I *D NAND2_X1 -*I _856_/A I *D CLKBUF_X1 +*I _670_:ZN O *D NOR2_X1 +*I _671_:A1 I *D NAND2_X1 +*I _856_:A I *D CLKBUF_X1 *CAP 1 _409_:1 0.6 2 _409_:2 2.1 @@ -10787,16 +10787,16 @@ resp_val O 4 _409_:3 _409_:5 42 5 _409_:5 _409_:6 0.005 6 _409_:7 _409_:6 4.2 -7 _670_/ZN _409_:4 2.835 -8 _671_/A1 _409_:1 2.405 -9 _856_/A _409_:7 2.905 +7 _670_:ZN _409_:4 2.835 +8 _671_:A1 _409_:1 2.405 +9 _856_:A _409_:7 2.905 *END *D_NET _410_ 34.68 *CONN -*I _677_/ZN O *D XNOR2_X1 -*I _678_/A1 I *D AND2_X1 -*I _857_/A I *D CLKBUF_X1 +*I _677_:ZN O *D XNOR2_X1 +*I _678_:A1 I *D AND2_X1 +*I _857_:A I *D CLKBUF_X1 *CAP 1 _410_:1 8.595 2 _410_:2 2.1 @@ -10816,16 +10816,16 @@ resp_val O 6 _410_:7 _410_:8 4.2 7 _410_:8 _410_:9 0.005 8 _410_:9 _410_:1 33.6 -9 _677_/ZN _410_:1 0.785 -10 _678_/A1 _410_:5 3.115 -11 _857_/A _410_:6 2.475 +9 _677_:ZN _410_:1 0.785 +10 _678_:A1 _410_:5 3.115 +11 _857_:A _410_:6 2.475 *END *D_NET _411_ 18.94 *CONN -*I _557_/Z O *D XOR2_X1 -*I _558_/A2 I *D NAND2_X1 -*I _843_/A I *D CLKBUF_X1 +*I _557_:Z O *D XOR2_X1 +*I _558_:A2 I *D NAND2_X1 +*I _843_:A I *D CLKBUF_X1 *CAP 1 _411_:1 2.1 2 _411_:2 2.72 @@ -10843,16 +10843,16 @@ resp_val O 5 _411_:4 _411_:6 4.2 6 _411_:6 _411_:7 0.005 7 _411_:8 _411_:7 8.4 -8 _557_/Z _411_:8 2.225 -9 _558_/A2 _411_:5 3.785 -10 _843_/A _411_:2 2.485 +8 _557_:Z _411_:8 2.225 +9 _558_:A2 _411_:5 3.785 +10 _843_:A _411_:2 2.485 *END *D_NET _412_ 17.3 *CONN -*I _563_/ZN O *D XNOR2_X1 -*I _564_/A2 I *D NAND2_X1 -*I _844_/A I *D CLKBUF_X1 +*I _563_:ZN O *D XNOR2_X1 +*I _564_:A2 I *D NAND2_X1 +*I _844_:A I *D CLKBUF_X1 *CAP 1 _412_:1 0.3925 2 _412_:2 5.25 @@ -10868,16 +10868,16 @@ resp_val O 4 _412_:3 _412_:5 4.2 5 _412_:5 _412_:6 0.005 6 _412_:7 _412_:6 4.2 -7 _563_/ZN _412_:7 1.205 -8 _564_/A2 _412_:4 2.435 -9 _844_/A _412_:1 1.575 +7 _563_:ZN _412_:7 1.205 +8 _564_:A2 _412_:4 2.435 +9 _844_:A _412_:1 1.575 *END *D_NET _413_ 22.69 *CONN -*I _572_/ZN O *D XNOR2_X1 -*I _573_/A2 I *D NAND2_X1 -*I _845_/A I *D CLKBUF_X1 +*I _572_:ZN O *D XNOR2_X1 +*I _573_:A2 I *D NAND2_X1 +*I _845_:A I *D CLKBUF_X1 *CAP 1 _413_:1 1.05 2 _413_:2 1.845 @@ -10895,16 +10895,16 @@ resp_val O 5 _413_:6 _413_:5 4.2 6 _413_:7 _413_:8 0.005 7 _413_:8 _413_:3 8.4 -8 _572_/ZN _413_:7 1.765 -9 _573_/A2 _413_:2 3.185 -10 _845_/A _413_:6 2.645 +8 _572_:ZN _413_:7 1.765 +9 _573_:A2 _413_:2 3.185 +10 _845_:A _413_:6 2.645 *END *D_NET _414_ 18.445 *CONN -*I _581_/Z O *D XOR2_X1 -*I _582_/A2 I *D NAND2_X1 -*I _846_/A I *D CLKBUF_X1 +*I _581_:Z O *D XOR2_X1 +*I _582_:A2 I *D NAND2_X1 +*I _846_:A I *D CLKBUF_X1 *CAP 1 _414_:1 3.855 2 _414_:2 3.15 @@ -10920,16 +10920,16 @@ resp_val O 4 _414_:4 _414_:5 0.005 5 _414_:5 _414_:6 4.2 6 _414_:6 _414_:7 8.4 -7 _581_/Z _414_:7 3.965 -8 _582_/A2 _414_:6 0.715 -9 _846_/A _414_:1 2.825 +7 _581_:Z _414_:7 3.965 +8 _582_:A2 _414_:6 0.715 +9 _846_:A _414_:1 2.825 *END *D_NET _415_ 21.365 *CONN -*I _589_/ZN O *D AOI221_X4 -*I _590_/A2 I *D NAND2_X1 -*I _847_/A I *D CLKBUF_X1 +*I _589_:ZN O *D AOI221_X4 +*I _590_:A2 I *D NAND2_X1 +*I _847_:A I *D CLKBUF_X1 *CAP 1 _415_:1 4.0325 2 _415_:2 3.7925 @@ -10943,16 +10943,16 @@ resp_val O 3 _415_:3 _415_:4 16.8 4 _415_:4 _415_:5 0.005 5 _415_:6 _415_:5 4.2 -6 _589_/ZN _415_:1 3.535 -7 _590_/A2 _415_:2 2.575 -8 _847_/A _415_:6 3.035 +6 _589_:ZN _415_:1 3.535 +7 _590_:A2 _415_:2 2.575 +8 _847_:A _415_:6 3.035 *END *D_NET _416_ 14.485 *CONN -*I _597_/ZN O *D XNOR2_X1 -*I _598_/A2 I *D NAND2_X1 -*I _848_/A I *D CLKBUF_X1 +*I _597_:ZN O *D XNOR2_X1 +*I _598_:A2 I *D NAND2_X1 +*I _848_:A I *D CLKBUF_X1 *CAP 1 _416_:1 1.585 2 _416_:2 1.05 @@ -10968,16 +10968,16 @@ resp_val O 4 _416_:4 _416_:5 0.005 5 _416_:5 _416_:6 4.2 6 _416_:6 _416_:7 12.6 -7 _597_/ZN _416_:7 0.845 -8 _598_/A2 _416_:6 0.795 -9 _848_/A _416_:1 2.145 +7 _597_:ZN _416_:7 0.845 +8 _598_:A2 _416_:6 0.795 +9 _848_:A _416_:1 2.145 *END *D_NET _417_ 23.085 *CONN -*I _606_/ZN O *D XNOR2_X1 -*I _607_/A2 I *D NAND2_X1 -*I _849_/A I *D CLKBUF_X1 +*I _606_:ZN O *D XNOR2_X1 +*I _607_:A2 I *D NAND2_X1 +*I _849_:A I *D CLKBUF_X1 *CAP 1 _417_:1 3.7975 2 _417_:2 1.05 @@ -10991,16 +10991,16 @@ resp_val O 3 _417_:3 _417_:4 29.4 4 _417_:4 _417_:5 0.005 5 _417_:6 _417_:1 8.4 -6 _606_/ZN _417_:6 0.825 -7 _607_/A2 _417_:1 2.595 -8 _849_/A _417_:5 0.765 +6 _606_:ZN _417_:6 0.825 +7 _607_:A2 _417_:1 2.595 +8 _849_:A _417_:5 0.765 *END *D_NET _418_ 14.125 *CONN -*I _615_/Z O *D XOR2_X1 -*I _616_/A2 I *D NAND2_X1 -*I _850_/A I *D CLKBUF_X1 +*I _615_:Z O *D XOR2_X1 +*I _616_:A2 I *D NAND2_X1 +*I _850_:A I *D CLKBUF_X1 *CAP 1 _418_:1 1.695 2 _418_:2 1.05 @@ -11016,16 +11016,16 @@ resp_val O 4 _418_:4 _418_:5 0.005 5 _418_:6 _418_:5 4.2 6 _418_:7 _418_:6 4.2 -7 _615_/Z _418_:7 3.125 -8 _616_/A2 _418_:6 1.555 -9 _850_/A _418_:1 2.585 +7 _615_:Z _418_:7 3.125 +8 _616_:A2 _418_:6 1.555 +9 _850_:A _418_:1 2.585 *END *D_NET _419_ 9.455 *CONN -*I _624_/ZN O *D AOI211_X1 -*I _625_/A1 I *D NAND2_X1 -*I _851_/A I *D CLKBUF_X1 +*I _624_:ZN O *D AOI211_X1 +*I _625_:A1 I *D NAND2_X1 +*I _851_:A I *D CLKBUF_X1 *CAP 1 _419_:1 1.465 2 _419_:2 2.1 @@ -11037,16 +11037,16 @@ resp_val O 2 _419_:2 _419_:3 8.4 3 _419_:3 _419_:4 0.005 4 _419_:1 _419_:5 4.2 -5 _624_/ZN _419_:5 2.305 -6 _625_/A1 _419_:1 1.665 -7 _851_/A _419_:4 2.355 +5 _624_:ZN _419_:5 2.305 +6 _625_:A1 _419_:1 1.665 +7 _851_:A _419_:4 2.355 *END *D_NET _420_ 14.455 *CONN -*I _453_/A2 I *D AND2_X1 -*I _462_/A3 I *D NAND3_X1 -*I _722_/Z O *D CLKBUF_X1 +*I _453_:A2 I *D AND2_X1 +*I _462_:A3 I *D NAND3_X1 +*I _722_:Z O *D CLKBUF_X1 *CAP 1 _420_:1 0.46 2 _420_:2 2.1 @@ -11064,17 +11064,17 @@ resp_val O 5 _420_:6 _420_:7 8.4 6 _420_:6 _420_:8 0.005 7 _420_:8 _420_:2 4.2 -8 _453_/A2 _420_:1 1.845 -9 _462_/A3 _420_:5 2.115 -10 _722_/Z _420_:7 3.965 +8 _453_:A2 _420_:1 1.845 +9 _462_:A3 _420_:5 2.115 +10 _722_:Z _420_:7 3.965 *END *D_NET _421_ 42.555 *CONN -*I _439_/ZN O *D AND3_X1 -*I _453_/A1 I *D AND2_X1 -*I _462_/A1 I *D NAND3_X1 -*I _721_/A I *D CLKBUF_X1 +*I _439_:ZN O *D AND3_X1 +*I _453_:A1 I *D AND2_X1 +*I _462_:A1 I *D NAND3_X1 +*I _721_:A I *D CLKBUF_X1 *CAP 1 _421_:1 0.365 2 _421_:2 1.05 @@ -11098,79 +11098,79 @@ resp_val O 8 _421_:9 _421_:10 0.005 9 _421_:11 _421_:10 4.2 10 _421_:7 _421_:5 8.4 -11 _439_/ZN _421_:7 3.005 -12 _453_/A1 _421_:1 1.465 -13 _462_/A1 _421_:5 2.875 -14 _721_/A _421_:11 2.185 +11 _439_:ZN _421_:7 3.005 +12 _453_:A1 _421_:1 1.465 +13 _462_:A1 _421_:5 2.875 +14 _721_:A _421_:11 2.185 *END *D_NET ctrl.state.out\[1\] 4.9 *CONN -*I _719_/A I *D CLKBUF_X1 -*I _859_/Q O *D DFF_X1 +*I _719_:A I *D CLKBUF_X1 +*I _859_:Q O *D DFF_X1 *CAP 1 ctrl.state.out\[1\]:1 1.54 2 ctrl.state.out\[1\]:2 1.96 *RES 1 ctrl.state.out\[1\]:2 ctrl.state.out\[1\]:1 4.2 -2 _719_/A ctrl.state.out\[1\]:2 3.645 -3 _859_/Q ctrl.state.out\[1\]:1 1.965 +2 _719_:A ctrl.state.out\[1\]:2 3.645 +3 _859_:Q ctrl.state.out\[1\]:1 1.965 *END *D_NET ctrl.state.out\[2\] 5.705 *CONN -*I _718_/A I *D CLKBUF_X1 -*I _860_/Q O *D DFF_X1 +*I _718_:A I *D CLKBUF_X1 +*I _860_:Q O *D DFF_X1 *CAP 1 ctrl.state.out\[2\]:1 2.19 2 ctrl.state.out\[2\]:2 1.7125 *RES 1 ctrl.state.out\[2\]:2 ctrl.state.out\[2\]:1 4.2 -2 _718_/A ctrl.state.out\[2\]:2 2.655 -3 _860_/Q ctrl.state.out\[2\]:1 4.565 +2 _718_:A ctrl.state.out\[2\]:2 2.655 +3 _860_:Q ctrl.state.out\[2\]:1 4.565 *END *D_NET dpath.a_lt_b\$in0\[0\] 3.87 *CONN -*I _753_/A I *D CLKBUF_X1 -*I _861_/Q O *D DFF_X1 +*I _753_:A I *D CLKBUF_X1 +*I _861_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[0\]:1 1.37 2 dpath.a_lt_b\$in0\[0\]:2 1.615 *RES 1 dpath.a_lt_b\$in0\[0\]:1 dpath.a_lt_b\$in0\[0\]:2 4.2 -2 _753_/A dpath.a_lt_b\$in0\[0\]:2 2.265 -3 _861_/Q dpath.a_lt_b\$in0\[0\]:1 1.285 +2 _753_:A dpath.a_lt_b\$in0\[0\]:2 2.265 +3 _861_:Q dpath.a_lt_b\$in0\[0\]:1 1.285 *END *D_NET dpath.a_lt_b\$in0\[10\] 1.595 *CONN -*I _733_/A I *D CLKBUF_X1 -*I _871_/Q O *D DFF_X1 +*I _733_:A I *D CLKBUF_X1 +*I _871_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[10\]:1 0.7975 *RES 1 dpath.a_lt_b\$in0\[10\]:1 dpath.a_lt_b\$in0\[10\]:1 0.005 -2 _733_/A dpath.a_lt_b\$in0\[10\]:1 2.255 -3 _871_/Q dpath.a_lt_b\$in0\[10\]:1 0.945 +2 _733_:A dpath.a_lt_b\$in0\[10\]:1 2.255 +3 _871_:Q dpath.a_lt_b\$in0\[10\]:1 0.945 *END *D_NET dpath.a_lt_b\$in0\[11\] 2.85 *CONN -*I _731_/A I *D CLKBUF_X1 -*I _872_/Q O *D DFF_X1 +*I _731_:A I *D CLKBUF_X1 +*I _872_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[11\]:1 1.425 *RES 1 dpath.a_lt_b\$in0\[11\]:1 dpath.a_lt_b\$in0\[11\]:1 0.005 -2 _731_/A dpath.a_lt_b\$in0\[11\]:1 3.525 -3 _872_/Q dpath.a_lt_b\$in0\[11\]:1 2.185 +2 _731_:A dpath.a_lt_b\$in0\[11\]:1 3.525 +3 _872_:Q dpath.a_lt_b\$in0\[11\]:1 2.185 *END *D_NET dpath.a_lt_b\$in0\[12\] 5.025 *CONN -*I _729_/A I *D CLKBUF_X1 -*I _873_/Q O *D DFF_X1 +*I _729_:A I *D CLKBUF_X1 +*I _873_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[12\]:1 0.5025 2 dpath.a_lt_b\$in0\[12\]:2 1.05 @@ -11180,40 +11180,40 @@ resp_val O 1 dpath.a_lt_b\$in0\[12\]:1 dpath.a_lt_b\$in0\[12\]:2 0.005 2 dpath.a_lt_b\$in0\[12\]:2 dpath.a_lt_b\$in0\[12\]:3 4.2 3 dpath.a_lt_b\$in0\[12\]:3 dpath.a_lt_b\$in0\[12\]:4 0.005 -4 _729_/A dpath.a_lt_b\$in0\[12\]:1 2.015 -5 _873_/Q dpath.a_lt_b\$in0\[12\]:4 3.845 +4 _729_:A dpath.a_lt_b\$in0\[12\]:1 2.015 +5 _873_:Q dpath.a_lt_b\$in0\[12\]:4 3.845 *END *D_NET dpath.a_lt_b\$in0\[13\] 4.01 *CONN -*I _727_/A I *D BUF_X1 -*I _874_/Q O *D DFF_X1 +*I _727_:A I *D BUF_X1 +*I _874_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[13\]:1 1.51 2 dpath.a_lt_b\$in0\[13\]:2 1.545 *RES 1 dpath.a_lt_b\$in0\[13\]:1 dpath.a_lt_b\$in0\[13\]:2 4.2 -2 _727_/A dpath.a_lt_b\$in0\[13\]:2 1.985 -3 _874_/Q dpath.a_lt_b\$in0\[13\]:1 1.845 +2 _727_:A dpath.a_lt_b\$in0\[13\]:2 1.985 +3 _874_:Q dpath.a_lt_b\$in0\[13\]:1 1.845 *END *D_NET dpath.a_lt_b\$in0\[14\] 4.9 *CONN -*I _725_/A I *D CLKBUF_X1 -*I _875_/Q O *D DFF_X1 +*I _725_:A I *D CLKBUF_X1 +*I _875_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[14\]:1 1.815 2 dpath.a_lt_b\$in0\[14\]:2 1.685 *RES 1 dpath.a_lt_b\$in0\[14\]:1 dpath.a_lt_b\$in0\[14\]:2 4.2 -2 _725_/A dpath.a_lt_b\$in0\[14\]:2 2.545 -3 _875_/Q dpath.a_lt_b\$in0\[14\]:1 3.065 +2 _725_:A dpath.a_lt_b\$in0\[14\]:2 2.545 +3 _875_:Q dpath.a_lt_b\$in0\[14\]:1 3.065 *END *D_NET dpath.a_lt_b\$in0\[15\] 6.905 *CONN -*I _723_/A I *D CLKBUF_X1 -*I _876_/Q O *D DFF_X1 +*I _723_:A I *D CLKBUF_X1 +*I _876_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[15\]:1 1.8275 2 dpath.a_lt_b\$in0\[15\]:2 1.05 @@ -11225,51 +11225,51 @@ resp_val O 2 dpath.a_lt_b\$in0\[15\]:2 dpath.a_lt_b\$in0\[15\]:3 0.005 3 dpath.a_lt_b\$in0\[15\]:3 dpath.a_lt_b\$in0\[15\]:4 4.2 4 dpath.a_lt_b\$in0\[15\]:4 dpath.a_lt_b\$in0\[15\]:5 0.005 -5 _723_/A dpath.a_lt_b\$in0\[15\]:1 3.115 -6 _876_/Q dpath.a_lt_b\$in0\[15\]:5 2.305 +5 _723_:A dpath.a_lt_b\$in0\[15\]:1 3.115 +6 _876_:Q dpath.a_lt_b\$in0\[15\]:5 2.305 *END *D_NET dpath.a_lt_b\$in0\[1\] 1.59 *CONN -*I _751_/A I *D BUF_X1 -*I _862_/Q O *D DFF_X1 +*I _751_:A I *D BUF_X1 +*I _862_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[1\]:1 0.795 *RES 1 dpath.a_lt_b\$in0\[1\]:1 dpath.a_lt_b\$in0\[1\]:1 0.005 -2 _751_/A dpath.a_lt_b\$in0\[1\]:1 2.365 -3 _862_/Q dpath.a_lt_b\$in0\[1\]:1 0.825 +2 _751_:A dpath.a_lt_b\$in0\[1\]:1 2.365 +3 _862_:Q dpath.a_lt_b\$in0\[1\]:1 0.825 *END *D_NET dpath.a_lt_b\$in0\[2\] 2.1 *CONN -*I _749_/A I *D CLKBUF_X1 -*I _863_/Q O *D DFF_X1 +*I _749_:A I *D CLKBUF_X1 +*I _863_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[2\]:1 1.05 *RES 1 dpath.a_lt_b\$in0\[2\]:1 dpath.a_lt_b\$in0\[2\]:1 0.005 -2 _749_/A dpath.a_lt_b\$in0\[2\]:1 3.825 -3 _863_/Q dpath.a_lt_b\$in0\[2\]:1 0.385 +2 _749_:A dpath.a_lt_b\$in0\[2\]:1 3.825 +3 _863_:Q dpath.a_lt_b\$in0\[2\]:1 0.385 *END *D_NET dpath.a_lt_b\$in0\[3\] 5.815 *CONN -*I _747_/A I *D BUF_X1 -*I _864_/Q O *D DFF_X1 +*I _747_:A I *D BUF_X1 +*I _864_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[3\]:1 2.28 2 dpath.a_lt_b\$in0\[3\]:2 1.6775 *RES 1 dpath.a_lt_b\$in0\[3\]:2 dpath.a_lt_b\$in0\[3\]:1 4.2 -2 _747_/A dpath.a_lt_b\$in0\[3\]:2 2.515 -3 _864_/Q dpath.a_lt_b\$in0\[3\]:1 4.925 +2 _747_:A dpath.a_lt_b\$in0\[3\]:2 2.515 +3 _864_:Q dpath.a_lt_b\$in0\[3\]:1 4.925 *END *D_NET dpath.a_lt_b\$in0\[4\] 7.57 *CONN -*I _745_/A I *D CLKBUF_X1 -*I _865_/Q O *D DFF_X1 +*I _745_:A I *D CLKBUF_X1 +*I _865_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[4\]:1 0.895 2 dpath.a_lt_b\$in0\[4\]:2 1.05 @@ -11281,40 +11281,40 @@ resp_val O 2 dpath.a_lt_b\$in0\[4\]:2 dpath.a_lt_b\$in0\[4\]:3 4.2 3 dpath.a_lt_b\$in0\[4\]:3 dpath.a_lt_b\$in0\[4\]:4 0.005 4 dpath.a_lt_b\$in0\[4\]:5 dpath.a_lt_b\$in0\[4\]:4 4.2 -5 _745_/A dpath.a_lt_b\$in0\[4\]:1 3.585 -6 _865_/Q dpath.a_lt_b\$in0\[4\]:5 3.165 +5 _745_:A dpath.a_lt_b\$in0\[4\]:1 3.585 +6 _865_:Q dpath.a_lt_b\$in0\[4\]:5 3.165 *END *D_NET dpath.a_lt_b\$in0\[5\] 3.815 *CONN -*I _743_/A I *D CLKBUF_X1 -*I _866_/Q O *D DFF_X1 +*I _743_:A I *D CLKBUF_X1 +*I _866_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[5\]:1 1.615 2 dpath.a_lt_b\$in0\[5\]:2 1.3425 *RES 1 dpath.a_lt_b\$in0\[5\]:2 dpath.a_lt_b\$in0\[5\]:1 4.2 -2 _743_/A dpath.a_lt_b\$in0\[5\]:2 1.175 -3 _866_/Q dpath.a_lt_b\$in0\[5\]:1 2.265 +2 _743_:A dpath.a_lt_b\$in0\[5\]:2 1.175 +3 _866_:Q dpath.a_lt_b\$in0\[5\]:1 2.265 *END *D_NET dpath.a_lt_b\$in0\[6\] 4.2 *CONN -*I _741_/A I *D CLKBUF_X1 -*I _867_/Q O *D DFF_X1 +*I _741_:A I *D CLKBUF_X1 +*I _867_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[6\]:1 1.84 2 dpath.a_lt_b\$in0\[6\]:2 1.31 *RES 1 dpath.a_lt_b\$in0\[6\]:1 dpath.a_lt_b\$in0\[6\]:2 4.2 -2 _741_/A dpath.a_lt_b\$in0\[6\]:2 1.045 -3 _867_/Q dpath.a_lt_b\$in0\[6\]:1 3.165 +2 _741_:A dpath.a_lt_b\$in0\[6\]:2 1.045 +3 _867_:Q dpath.a_lt_b\$in0\[6\]:1 3.165 *END *D_NET dpath.a_lt_b\$in0\[7\] 3.3 *CONN -*I _739_/A I *D BUF_X1 -*I _868_/Q O *D DFF_X1 +*I _739_:A I *D BUF_X1 +*I _868_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[7\]:1 0.145 2 dpath.a_lt_b\$in0\[7\]:2 1.05 @@ -11324,26 +11324,26 @@ resp_val O 1 dpath.a_lt_b\$in0\[7\]:1 dpath.a_lt_b\$in0\[7\]:2 0.005 2 dpath.a_lt_b\$in0\[7\]:2 dpath.a_lt_b\$in0\[7\]:3 4.2 3 dpath.a_lt_b\$in0\[7\]:3 dpath.a_lt_b\$in0\[7\]:4 0.005 -4 _739_/A dpath.a_lt_b\$in0\[7\]:4 1.825 -5 _868_/Q dpath.a_lt_b\$in0\[7\]:1 0.585 +4 _739_:A dpath.a_lt_b\$in0\[7\]:4 1.825 +5 _868_:Q dpath.a_lt_b\$in0\[7\]:1 0.585 *END *D_NET dpath.a_lt_b\$in0\[8\] 2.645 *CONN -*I _737_/A I *D CLKBUF_X1 -*I _869_/Q O *D DFF_X1 +*I _737_:A I *D CLKBUF_X1 +*I _869_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[8\]:1 1.3225 *RES 1 dpath.a_lt_b\$in0\[8\]:1 dpath.a_lt_b\$in0\[8\]:1 0.005 -2 _737_/A dpath.a_lt_b\$in0\[8\]:1 2.995 -3 _869_/Q dpath.a_lt_b\$in0\[8\]:1 2.305 +2 _737_:A dpath.a_lt_b\$in0\[8\]:1 2.995 +3 _869_:Q dpath.a_lt_b\$in0\[8\]:1 2.305 *END *D_NET dpath.a_lt_b\$in0\[9\] 3.3 *CONN -*I _735_/A I *D CLKBUF_X1 -*I _870_/Q O *D DFF_X1 +*I _735_:A I *D CLKBUF_X1 +*I _870_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[9\]:1 0.045 2 dpath.a_lt_b\$in0\[9\]:2 1.05 @@ -11353,40 +11353,40 @@ resp_val O 1 dpath.a_lt_b\$in0\[9\]:1 dpath.a_lt_b\$in0\[9\]:2 0.005 2 dpath.a_lt_b\$in0\[9\]:2 dpath.a_lt_b\$in0\[9\]:3 4.2 3 dpath.a_lt_b\$in0\[9\]:3 dpath.a_lt_b\$in0\[9\]:4 0.005 -4 _735_/A dpath.a_lt_b\$in0\[9\]:4 2.225 -5 _870_/Q dpath.a_lt_b\$in0\[9\]:1 0.185 +4 _735_:A dpath.a_lt_b\$in0\[9\]:4 2.225 +5 _870_:Q dpath.a_lt_b\$in0\[9\]:1 0.185 *END *D_NET dpath.a_lt_b\$in1\[0\] 3.49 *CONN -*I _754_/A I *D BUF_X1 -*I _877_/Q O *D DFF_X1 +*I _754_:A I *D BUF_X1 +*I _877_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[0\]:1 1.29 2 dpath.a_lt_b\$in1\[0\]:2 1.505 *RES 1 dpath.a_lt_b\$in1\[0\]:1 dpath.a_lt_b\$in1\[0\]:2 4.2 -2 _754_/A dpath.a_lt_b\$in1\[0\]:2 1.825 -3 _877_/Q dpath.a_lt_b\$in1\[0\]:1 0.965 +2 _754_:A dpath.a_lt_b\$in1\[0\]:2 1.825 +3 _877_:Q dpath.a_lt_b\$in1\[0\]:1 0.965 *END *D_NET dpath.a_lt_b\$in1\[10\] 4.075 *CONN -*I _734_/A I *D BUF_X1 -*I _887_/Q O *D DFF_X1 +*I _734_:A I *D BUF_X1 +*I _887_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[10\]:1 1.84 2 dpath.a_lt_b\$in1\[10\]:2 1.2475 *RES 1 dpath.a_lt_b\$in1\[10\]:1 dpath.a_lt_b\$in1\[10\]:2 4.2 -2 _734_/A dpath.a_lt_b\$in1\[10\]:2 0.795 -3 _887_/Q dpath.a_lt_b\$in1\[10\]:1 3.165 +2 _734_:A dpath.a_lt_b\$in1\[10\]:2 0.795 +3 _887_:Q dpath.a_lt_b\$in1\[10\]:1 3.165 *END *D_NET dpath.a_lt_b\$in1\[11\] 5.36 *CONN -*I _732_/A I *D BUF_X1 -*I _888_/Q O *D DFF_X1 +*I _732_:A I *D BUF_X1 +*I _888_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[11\]:1 0.215 2 dpath.a_lt_b\$in1\[11\]:2 1.05 @@ -11398,52 +11398,52 @@ resp_val O 2 dpath.a_lt_b\$in1\[11\]:2 dpath.a_lt_b\$in1\[11\]:3 4.2 3 dpath.a_lt_b\$in1\[11\]:3 dpath.a_lt_b\$in1\[11\]:4 0.005 4 dpath.a_lt_b\$in1\[11\]:5 dpath.a_lt_b\$in1\[11\]:4 4.2 -5 _732_/A dpath.a_lt_b\$in1\[11\]:1 0.865 -6 _888_/Q dpath.a_lt_b\$in1\[11\]:5 1.465 +5 _732_:A dpath.a_lt_b\$in1\[11\]:1 0.865 +6 _888_:Q dpath.a_lt_b\$in1\[11\]:5 1.465 *END *D_NET dpath.a_lt_b\$in1\[12\] 3.63 *CONN -*I _730_/A I *D BUF_X1 -*I _889_/Q O *D DFF_X1 +*I _730_:A I *D BUF_X1 +*I _889_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[12\]:1 1.385 2 dpath.a_lt_b\$in1\[12\]:2 1.48 *RES 1 dpath.a_lt_b\$in1\[12\]:1 dpath.a_lt_b\$in1\[12\]:2 4.2 -2 _730_/A dpath.a_lt_b\$in1\[12\]:2 1.725 -3 _889_/Q dpath.a_lt_b\$in1\[12\]:1 1.345 +2 _730_:A dpath.a_lt_b\$in1\[12\]:2 1.725 +3 _889_:Q dpath.a_lt_b\$in1\[12\]:1 1.345 *END *D_NET dpath.a_lt_b\$in1\[13\] 3.31 *CONN -*I _728_/A I *D CLKBUF_X2 -*I _890_/Q O *D DFF_X1 +*I _728_:A I *D CLKBUF_X2 +*I _890_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[13\]:1 1.145 2 dpath.a_lt_b\$in1\[13\]:2 1.56 *RES 1 dpath.a_lt_b\$in1\[13\]:1 dpath.a_lt_b\$in1\[13\]:2 4.2 -2 _728_/A dpath.a_lt_b\$in1\[13\]:2 2.045 -3 _890_/Q dpath.a_lt_b\$in1\[13\]:1 0.385 +2 _728_:A dpath.a_lt_b\$in1\[13\]:2 2.045 +3 _890_:Q dpath.a_lt_b\$in1\[13\]:1 0.385 *END *D_NET dpath.a_lt_b\$in1\[14\] 2.46 *CONN -*I _726_/A I *D BUF_X1 -*I _891_/Q O *D DFF_X1 +*I _726_:A I *D BUF_X1 +*I _891_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[14\]:1 1.23 *RES 1 dpath.a_lt_b\$in1\[14\]:1 dpath.a_lt_b\$in1\[14\]:1 0.005 -2 _726_/A dpath.a_lt_b\$in1\[14\]:1 1.405 -3 _891_/Q dpath.a_lt_b\$in1\[14\]:1 3.525 +2 _726_:A dpath.a_lt_b\$in1\[14\]:1 1.405 +3 _891_:Q dpath.a_lt_b\$in1\[14\]:1 3.525 *END *D_NET dpath.a_lt_b\$in1\[15\] 6.88 *CONN -*I _724_/A I *D BUF_X1 -*I _892_/Q O *D DFF_X1 +*I _724_:A I *D BUF_X1 +*I _892_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[15\]:1 1.56 2 dpath.a_lt_b\$in1\[15\]:2 1.05 @@ -11455,64 +11455,64 @@ resp_val O 2 dpath.a_lt_b\$in1\[15\]:2 dpath.a_lt_b\$in1\[15\]:3 0.005 3 dpath.a_lt_b\$in1\[15\]:3 dpath.a_lt_b\$in1\[15\]:4 4.2 4 dpath.a_lt_b\$in1\[15\]:4 dpath.a_lt_b\$in1\[15\]:5 0.005 -5 _724_/A dpath.a_lt_b\$in1\[15\]:1 2.045 -6 _892_/Q dpath.a_lt_b\$in1\[15\]:5 3.325 +5 _724_:A dpath.a_lt_b\$in1\[15\]:1 2.045 +6 _892_:Q dpath.a_lt_b\$in1\[15\]:5 3.325 *END *D_NET dpath.a_lt_b\$in1\[1\] 4.075 *CONN -*I _752_/A I *D BUF_X1 -*I _878_/Q O *D DFF_X1 +*I _752_:A I *D BUF_X1 +*I _878_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[1\]:1 1.345 2 dpath.a_lt_b\$in1\[1\]:2 1.7425 *RES 1 dpath.a_lt_b\$in1\[1\]:2 dpath.a_lt_b\$in1\[1\]:1 4.2 -2 _752_/A dpath.a_lt_b\$in1\[1\]:2 2.775 -3 _878_/Q dpath.a_lt_b\$in1\[1\]:1 1.185 +2 _752_:A dpath.a_lt_b\$in1\[1\]:2 2.775 +3 _878_:Q dpath.a_lt_b\$in1\[1\]:1 1.185 *END *D_NET dpath.a_lt_b\$in1\[2\] 3.84 *CONN -*I _750_/A I *D CLKBUF_X1 -*I _879_/Q O *D DFF_X1 +*I _750_:A I *D CLKBUF_X1 +*I _879_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[2\]:1 1.69 2 dpath.a_lt_b\$in1\[2\]:2 1.28 *RES 1 dpath.a_lt_b\$in1\[2\]:2 dpath.a_lt_b\$in1\[2\]:1 4.2 -2 _750_/A dpath.a_lt_b\$in1\[2\]:2 0.925 -3 _879_/Q dpath.a_lt_b\$in1\[2\]:1 2.565 +2 _750_:A dpath.a_lt_b\$in1\[2\]:2 0.925 +3 _879_:Q dpath.a_lt_b\$in1\[2\]:1 2.565 *END *D_NET dpath.a_lt_b\$in1\[3\] 2.01 *CONN -*I _748_/A I *D CLKBUF_X1 -*I _880_/Q O *D DFF_X1 +*I _748_:A I *D CLKBUF_X1 +*I _880_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[3\]:1 1.005 *RES 1 dpath.a_lt_b\$in1\[3\]:1 dpath.a_lt_b\$in1\[3\]:1 0.005 -2 _748_/A dpath.a_lt_b\$in1\[3\]:1 0.805 -3 _880_/Q dpath.a_lt_b\$in1\[3\]:1 3.225 +2 _748_:A dpath.a_lt_b\$in1\[3\]:1 0.805 +3 _880_:Q dpath.a_lt_b\$in1\[3\]:1 3.225 *END *D_NET dpath.a_lt_b\$in1\[4\] 2.285 *CONN -*I _746_/A I *D CLKBUF_X1 -*I _881_/Q O *D DFF_X1 +*I _746_:A I *D CLKBUF_X1 +*I _881_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[4\]:1 1.1425 *RES 1 dpath.a_lt_b\$in1\[4\]:1 dpath.a_lt_b\$in1\[4\]:1 0.005 -2 _746_/A dpath.a_lt_b\$in1\[4\]:1 1.815 -3 _881_/Q dpath.a_lt_b\$in1\[4\]:1 2.765 +2 _746_:A dpath.a_lt_b\$in1\[4\]:1 1.815 +3 _881_:Q dpath.a_lt_b\$in1\[4\]:1 2.765 *END *D_NET dpath.a_lt_b\$in1\[5\] 5.765 *CONN -*I _744_/A I *D BUF_X1 -*I _882_/Q O *D DFF_X1 +*I _744_:A I *D BUF_X1 +*I _882_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[5\]:1 0.5325 2 dpath.a_lt_b\$in1\[5\]:2 1.05 @@ -11524,26 +11524,26 @@ resp_val O 2 dpath.a_lt_b\$in1\[5\]:2 dpath.a_lt_b\$in1\[5\]:3 4.2 3 dpath.a_lt_b\$in1\[5\]:3 dpath.a_lt_b\$in1\[5\]:4 0.005 4 dpath.a_lt_b\$in1\[5\]:5 dpath.a_lt_b\$in1\[5\]:4 4.2 -5 _744_/A dpath.a_lt_b\$in1\[5\]:1 2.135 -6 _882_/Q dpath.a_lt_b\$in1\[5\]:5 1.005 +5 _744_:A dpath.a_lt_b\$in1\[5\]:1 2.135 +6 _882_:Q dpath.a_lt_b\$in1\[5\]:5 1.005 *END *D_NET dpath.a_lt_b\$in1\[6\] 2.925 *CONN -*I _742_/A I *D BUF_X1 -*I _883_/Q O *D DFF_X1 +*I _742_:A I *D BUF_X1 +*I _883_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[6\]:1 1.4625 *RES 1 dpath.a_lt_b\$in1\[6\]:1 dpath.a_lt_b\$in1\[6\]:1 0.005 -2 _742_/A dpath.a_lt_b\$in1\[6\]:1 2.455 -3 _883_/Q dpath.a_lt_b\$in1\[6\]:1 3.405 +2 _742_:A dpath.a_lt_b\$in1\[6\]:1 2.455 +3 _883_:Q dpath.a_lt_b\$in1\[6\]:1 3.405 *END *D_NET dpath.a_lt_b\$in1\[7\] 4.2 *CONN -*I _740_/A I *D BUF_X1 -*I _884_/Q O *D DFF_X1 +*I _740_:A I *D BUF_X1 +*I _884_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[7\]:1 0.05 2 dpath.a_lt_b\$in1\[7\]:2 1.05 @@ -11553,14 +11553,14 @@ resp_val O 1 dpath.a_lt_b\$in1\[7\]:1 dpath.a_lt_b\$in1\[7\]:2 0.005 2 dpath.a_lt_b\$in1\[7\]:2 dpath.a_lt_b\$in1\[7\]:3 4.2 3 dpath.a_lt_b\$in1\[7\]:3 dpath.a_lt_b\$in1\[7\]:4 0.005 -4 _740_/A dpath.a_lt_b\$in1\[7\]:4 4.005 -5 _884_/Q dpath.a_lt_b\$in1\[7\]:1 0.205 +4 _740_:A dpath.a_lt_b\$in1\[7\]:4 4.005 +5 _884_:Q dpath.a_lt_b\$in1\[7\]:1 0.205 *END *D_NET dpath.a_lt_b\$in1\[8\] 3.535 *CONN -*I _738_/A I *D CLKBUF_X1 -*I _885_/Q O *D DFF_X1 +*I _738_:A I *D CLKBUF_X1 +*I _885_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[8\]:1 0.145 2 dpath.a_lt_b\$in1\[8\]:2 1.05 @@ -11570,27 +11570,27 @@ resp_val O 1 dpath.a_lt_b\$in1\[8\]:1 dpath.a_lt_b\$in1\[8\]:2 0.005 2 dpath.a_lt_b\$in1\[8\]:2 dpath.a_lt_b\$in1\[8\]:3 4.2 3 dpath.a_lt_b\$in1\[8\]:3 dpath.a_lt_b\$in1\[8\]:4 0.005 -4 _738_/A dpath.a_lt_b\$in1\[8\]:4 2.295 -5 _885_/Q dpath.a_lt_b\$in1\[8\]:1 0.585 +4 _738_:A dpath.a_lt_b\$in1\[8\]:4 2.295 +5 _885_:Q dpath.a_lt_b\$in1\[8\]:1 0.585 *END *D_NET dpath.a_lt_b\$in1\[9\] 3.855 *CONN -*I _736_/A I *D BUF_X1 -*I _886_/Q O *D DFF_X1 +*I _736_:A I *D BUF_X1 +*I _886_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[9\]:1 1.545 2 dpath.a_lt_b\$in1\[9\]:2 1.4325 *RES 1 dpath.a_lt_b\$in1\[9\]:2 dpath.a_lt_b\$in1\[9\]:1 4.2 -2 _736_/A dpath.a_lt_b\$in1\[9\]:2 1.535 -3 _886_/Q dpath.a_lt_b\$in1\[9\]:1 1.985 +2 _736_:A dpath.a_lt_b\$in1\[9\]:2 1.535 +3 _886_:Q dpath.a_lt_b\$in1\[9\]:1 1.985 *END *D_NET net1 27.845 *CONN -*I _809_/A I *D CLKBUF_X1 -*I buffer1/Z O *D BUF_X4 +*I _809_:A I *D CLKBUF_X1 +*I buffer1:Z O *D BUF_X4 *CAP 1 net1:1 1.765 2 net1:2 1.05 @@ -11602,14 +11602,14 @@ resp_val O 2 net1:2 net1:3 0.005 3 net1:3 net1:4 46.2 4 net1:4 net1:5 0.005 -5 _809_/A net1:1 2.865 -6 buffer1/Z net1:5 2.435 +5 _809_:A net1:1 2.865 +6 buffer1:Z net1:5 2.435 *END *D_NET net10 37.65 *CONN -*I _782_/A I *D CLKBUF_X1 -*I buffer10/Z O *D BUF_X4 +*I _782_:A I *D CLKBUF_X1 +*I buffer10:Z O *D BUF_X4 *CAP 1 net10:1 11.55 2 net10:2 12.0825 @@ -11621,14 +11621,14 @@ resp_val O 2 net10:1 net10:3 0.005 3 net10:3 net10:4 25.2 4 net10:4 net10:5 0.005 -5 _782_/A net10:2 2.135 -6 buffer10/Z net10:5 1.775 +5 _782_:A net10:2 2.135 +6 buffer10:Z net10:5 1.775 *END *D_NET net11 6.995 *CONN -*I _779_/A I *D CLKBUF_X1 -*I buffer11/Z O *D BUF_X4 +*I _779_:A I *D CLKBUF_X1 +*I buffer11:Z O *D BUF_X4 *CAP 1 net11:1 1.475 2 net11:2 1.05 @@ -11640,14 +11640,14 @@ resp_val O 2 net11:2 net11:3 0.005 3 net11:3 net11:4 4.2 4 net11:4 net11:5 0.005 -5 _779_/A net11:1 1.705 -6 buffer11/Z net11:5 3.895 +5 _779_:A net11:1 1.705 +6 buffer11:Z net11:5 3.895 *END *D_NET net12 28.175 *CONN -*I _776_/A I *D CLKBUF_X1 -*I buffer12/Z O *D BUF_X4 +*I _776_:A I *D CLKBUF_X1 +*I buffer12:Z O *D BUF_X4 *CAP 1 net12:1 12.7325 2 net12:2 12.6 @@ -11659,14 +11659,14 @@ resp_val O 2 net12:2 net12:3 0.005 3 net12:3 net12:4 4.2 4 net12:4 net12:5 0.005 -5 _776_/A net12:5 1.225 -6 buffer12/Z net12:1 0.535 +5 _776_:A net12:5 1.225 +6 buffer12:Z net12:1 0.535 *END *D_NET net13 19.715 *CONN -*I _773_/A I *D CLKBUF_X1 -*I buffer13/Z O *D BUF_X4 +*I _773_:A I *D CLKBUF_X1 +*I buffer13:Z O *D BUF_X4 *CAP 1 net13:1 4.065 2 net13:2 3.15 @@ -11680,14 +11680,14 @@ resp_val O 3 net13:3 net13:4 4.2 4 net13:4 net13:5 0.005 5 net13:5 net13:6 16.8 -6 _773_/A net13:1 3.665 -7 buffer13/Z net13:6 2.175 +6 _773_:A net13:1 3.665 +7 buffer13:Z net13:6 2.175 *END *D_NET net14 21.47 *CONN -*I _770_/A I *D CLKBUF_X1 -*I buffer14/Z O *D BUF_X4 +*I _770_:A I *D CLKBUF_X1 +*I buffer14:Z O *D BUF_X4 *CAP 1 net14:1 4.2 2 net14:2 5.1375 @@ -11701,14 +11701,14 @@ resp_val O 3 net14:3 net14:4 4.2 4 net14:4 net14:5 0.005 5 net14:6 net14:5 16.8 -6 _770_/A net14:6 1.395 -7 buffer14/Z net14:2 3.755 +6 _770_:A net14:6 1.395 +7 buffer14:Z net14:2 3.755 *END *D_NET net15 10.24 *CONN -*I _767_/A I *D CLKBUF_X1 -*I buffer15/Z O *D BUF_X4 +*I _767_:A I *D CLKBUF_X1 +*I buffer15:Z O *D BUF_X4 *CAP 1 net15:1 2.1 2 net15:2 2.3975 @@ -11722,14 +11722,14 @@ resp_val O 3 net15:3 net15:4 4.2 4 net15:4 net15:5 0.005 5 net15:6 net15:5 4.2 -6 _767_/A net15:2 1.195 -7 buffer15/Z net15:6 2.495 +6 _767_:A net15:2 1.195 +7 buffer15:Z net15:6 2.495 *END *D_NET net16 8.535 *CONN -*I _764_/A I *D CLKBUF_X1 -*I buffer16/Z O *D BUF_X4 +*I _764_:A I *D CLKBUF_X1 +*I buffer16:Z O *D BUF_X4 *CAP 1 net16:1 0.55 2 net16:2 2.1 @@ -11741,14 +11741,14 @@ resp_val O 2 net16:2 net16:3 8.4 3 net16:3 net16:4 0.005 4 net16:4 net16:5 4.2 -5 _764_/A net16:1 2.205 -6 buffer16/Z net16:5 2.275 +5 _764_:A net16:1 2.205 +6 buffer16:Z net16:5 2.275 *END *D_NET net17 50.85 *CONN -*I _841_/A I *D CLKBUF_X1 -*I buffer17/Z O *D BUF_X4 +*I _841_:A I *D CLKBUF_X1 +*I buffer17:Z O *D BUF_X4 *CAP 1 net17:1 23.7725 2 net17:2 23.1 @@ -11760,14 +11760,14 @@ resp_val O 2 net17:2 net17:3 0.005 3 net17:3 net17:4 4.2 4 net17:4 net17:5 0.005 -5 _841_/A net17:1 2.695 -6 buffer17/Z net17:5 2.415 +5 _841_:A net17:1 2.695 +6 buffer17:Z net17:5 2.415 *END *D_NET net18 18.335 *CONN -*I _839_/A I *D CLKBUF_X1 -*I buffer18/Z O *D BUF_X4 +*I _839_:A I *D CLKBUF_X1 +*I buffer18:Z O *D BUF_X4 *CAP 1 net18:1 0.3075 2 net18:2 5.25 @@ -11779,14 +11779,14 @@ resp_val O 2 net18:2 net18:3 21 3 net18:3 net18:4 0.005 4 net18:4 net18:5 12.6 -5 _839_/A net18:5 1.845 -6 buffer18/Z net18:1 1.235 +5 _839_:A net18:5 1.845 +6 buffer18:Z net18:1 1.235 *END *D_NET net19 23.985 *CONN -*I _837_/A I *D CLKBUF_X1 -*I buffer19/Z O *D BUF_X4 +*I _837_:A I *D CLKBUF_X1 +*I buffer19:Z O *D BUF_X4 *CAP 1 net19:1 3.15 2 net19:2 3.48 @@ -11798,14 +11798,14 @@ resp_val O 2 net19:1 net19:3 0.005 3 net19:3 net19:4 33.6 4 net19:4 net19:5 0.005 -5 _837_/A net19:2 1.325 -6 buffer19/Z net19:5 0.455 +5 _837_:A net19:2 1.325 +6 buffer19:Z net19:5 0.455 *END *D_NET net2 9.075 *CONN -*I _806_/A I *D CLKBUF_X1 -*I buffer2/Z O *D BUF_X4 +*I _806_:A I *D CLKBUF_X1 +*I buffer2:Z O *D BUF_X4 *CAP 1 net2:1 1.8125 2 net2:2 1.05 @@ -11817,14 +11817,14 @@ resp_val O 2 net2:2 net2:3 0.005 3 net2:3 net2:4 8.4 4 net2:4 net2:5 0.005 -5 _806_/A net2:5 2.505 -6 buffer2/Z net2:1 3.055 +5 _806_:A net2:5 2.505 +6 buffer2:Z net2:1 3.055 *END *D_NET net20 36.55 *CONN -*I _835_/A I *D CLKBUF_X1 -*I buffer20/Z O *D BUF_X4 +*I _835_:A I *D CLKBUF_X1 +*I buffer20:Z O *D BUF_X4 *CAP 1 net20:1 2.2525 2 net20:2 2.1 @@ -11836,27 +11836,27 @@ resp_val O 2 net20:2 net20:3 0.005 3 net20:3 net20:4 58.8 4 net20:4 net20:5 0.005 -5 _835_/A net20:1 0.615 -6 buffer20/Z net20:5 5.295 +5 _835_:A net20:1 0.615 +6 buffer20:Z net20:5 5.295 *END *D_NET net21 4.37 *CONN -*I _833_/A I *D CLKBUF_X1 -*I buffer21/Z O *D BUF_X4 +*I _833_:A I *D CLKBUF_X1 +*I buffer21:Z O *D BUF_X4 *CAP 1 net21:1 1.5875 2 net21:2 1.6475 *RES 1 net21:1 net21:2 4.2 -2 _833_/A net21:2 2.395 -3 buffer21/Z net21:1 2.155 +2 _833_:A net21:2 2.395 +3 buffer21:Z net21:1 2.155 *END *D_NET net22 8.915 *CONN -*I _831_/A I *D CLKBUF_X1 -*I buffer22/Z O *D BUF_X4 +*I _831_:A I *D CLKBUF_X1 +*I buffer22:Z O *D BUF_X4 *CAP 1 net22:1 0.49 2 net22:2 2.1 @@ -11868,27 +11868,27 @@ resp_val O 2 net22:2 net22:3 8.4 3 net22:3 net22:4 0.005 4 net22:4 net22:5 4.2 -5 _831_/A net22:1 1.965 -6 buffer22/Z net22:5 3.275 +5 _831_:A net22:1 1.965 +6 buffer22:Z net22:5 3.275 *END *D_NET net23 3.97 *CONN -*I _829_/A I *D CLKBUF_X1 -*I buffer23/Z O *D BUF_X4 +*I _829_:A I *D CLKBUF_X1 +*I buffer23:Z O *D BUF_X4 *CAP 1 net23:1 1.4875 2 net23:2 1.5475 *RES 1 net23:1 net23:2 4.2 -2 _829_/A net23:2 1.995 -3 buffer23/Z net23:1 1.755 +2 _829_:A net23:2 1.995 +3 buffer23:Z net23:1 1.755 *END *D_NET net24 51.25 *CONN -*I _827_/A I *D CLKBUF_X1 -*I buffer24/Z O *D BUF_X4 +*I _827_:A I *D CLKBUF_X1 +*I buffer24:Z O *D BUF_X4 *CAP 1 net24:1 18.9 2 net24:2 19.3825 @@ -11900,14 +11900,14 @@ resp_val O 2 net24:1 net24:3 0.005 3 net24:3 net24:4 21 4 net24:4 net24:5 0.005 -5 _827_/A net24:5 3.975 -6 buffer24/Z net24:2 1.935 +5 _827_:A net24:5 3.975 +6 buffer24:Z net24:2 1.935 *END *D_NET net25 17.495 *CONN -*I _825_/A I *D CLKBUF_X1 -*I buffer25/Z O *D BUF_X4 +*I _825_:A I *D CLKBUF_X1 +*I buffer25:Z O *D BUF_X4 *CAP 1 net25:1 3.925 2 net25:2 3.15 @@ -11921,27 +11921,27 @@ resp_val O 3 net25:3 net25:4 4.2 4 net25:4 net25:5 0.005 5 net25:5 net25:6 12.6 -6 _825_/A net25:1 3.105 -7 buffer25/Z net25:6 2.495 +6 _825_:A net25:1 3.105 +7 buffer25:Z net25:6 2.495 *END *D_NET net26 4.825 *CONN -*I _823_/A I *D CLKBUF_X1 -*I buffer26/Z O *D BUF_X4 +*I _823_:A I *D CLKBUF_X1 +*I buffer26:Z O *D BUF_X4 *CAP 1 net26:1 1.8375 2 net26:2 1.625 *RES 1 net26:1 net26:2 4.2 -2 _823_/A net26:2 2.305 -3 buffer26/Z net26:1 3.155 +2 _823_:A net26:2 2.305 +3 buffer26:Z net26:1 3.155 *END *D_NET net27 12.19 *CONN -*I _821_/A I *D CLKBUF_X1 -*I buffer27/Z O *D BUF_X4 +*I _821_:A I *D CLKBUF_X1 +*I buffer27:Z O *D BUF_X4 *CAP 1 net27:1 1.6225 2 net27:2 1.05 @@ -11953,14 +11953,14 @@ resp_val O 2 net27:2 net27:3 0.005 3 net27:3 net27:4 12.6 4 net27:4 net27:5 0.005 -5 _821_/A net27:1 2.295 -6 buffer27/Z net27:5 5.295 +5 _821_:A net27:1 2.295 +6 buffer27:Z net27:5 5.295 *END *D_NET net28 16.215 *CONN -*I _819_/A I *D CLKBUF_X1 -*I buffer28/Z O *D BUF_X4 +*I _819_:A I *D CLKBUF_X1 +*I buffer28:Z O *D BUF_X4 *CAP 1 net28:1 1.535 2 net28:2 1.05 @@ -11974,27 +11974,27 @@ resp_val O 3 net28:3 net28:4 12.6 4 net28:4 net28:5 0.005 5 net28:5 net28:6 8.4 -6 _819_/A net28:1 1.945 -7 buffer28/Z net28:6 5.295 +6 _819_:A net28:1 1.945 +7 buffer28:Z net28:6 5.295 *END *D_NET net29 4.32 *CONN -*I _817_/A I *D CLKBUF_X1 -*I buffer29/Z O *D BUF_X4 +*I _817_:A I *D CLKBUF_X1 +*I buffer29:Z O *D BUF_X4 *CAP 1 net29:1 1.4875 2 net29:2 1.7225 *RES 1 net29:2 net29:1 4.2 -2 _817_/A net29:2 2.695 -3 buffer29/Z net29:1 1.755 +2 _817_:A net29:2 2.695 +3 buffer29:Z net29:1 1.755 *END *D_NET net3 8.335 *CONN -*I _803_/A I *D CLKBUF_X1 -*I buffer3/Z O *D BUF_X4 +*I _803_:A I *D CLKBUF_X1 +*I buffer3:Z O *D BUF_X4 *CAP 1 net3:1 2.1 2 net3:2 2.885 @@ -12006,14 +12006,14 @@ resp_val O 2 net3:1 net3:3 0.005 3 net3:3 net3:4 4.2 4 net3:4 net3:5 0.005 -5 _803_/A net3:2 3.145 -6 buffer3/Z net3:5 0.935 +5 _803_:A net3:2 3.145 +6 buffer3:Z net3:5 0.935 *END *D_NET net30 20.995 *CONN -*I _815_/A I *D CLKBUF_X1 -*I buffer30/Z O *D BUF_X4 +*I _815_:A I *D CLKBUF_X1 +*I buffer30:Z O *D BUF_X4 *CAP 1 net30:1 6.3 2 net30:2 7.0525 @@ -12025,14 +12025,14 @@ resp_val O 2 net30:1 net30:3 0.005 3 net30:3 net30:4 12.6 4 net30:4 net30:5 0.005 -5 _815_/A net30:5 1.185 -6 buffer30/Z net30:2 3.015 +5 _815_:A net30:5 1.185 +6 buffer30:Z net30:2 3.015 *END *D_NET net31 6.34 *CONN -*I _813_/A I *D CLKBUF_X1 -*I buffer31/Z O *D BUF_X4 +*I _813_:A I *D CLKBUF_X1 +*I buffer31:Z O *D BUF_X4 *CAP 1 net31:1 1.7425 2 net31:2 1.05 @@ -12044,14 +12044,14 @@ resp_val O 2 net31:2 net31:3 0.005 3 net31:3 net31:4 4.2 4 net31:4 net31:5 0.005 -5 _813_/A net31:5 1.515 -6 buffer31/Z net31:1 2.775 +5 _813_:A net31:5 1.515 +6 buffer31:Z net31:1 2.775 *END *D_NET net32 15.7 *CONN -*I _811_/A I *D CLKBUF_X1 -*I buffer32/Z O *D BUF_X4 +*I _811_:A I *D CLKBUF_X1 +*I buffer32:Z O *D BUF_X4 *CAP 1 net32:1 0.9275 2 net32:2 5.25 @@ -12063,14 +12063,14 @@ resp_val O 2 net32:2 net32:3 21 3 net32:3 net32:4 0.005 4 net32:4 net32:5 4.2 -5 _811_/A net32:1 3.715 -6 buffer32/Z net32:5 2.495 +5 _811_:A net32:1 3.715 +6 buffer32:Z net32:5 2.495 *END *D_NET net33 70.445 *CONN -*I _760_/A I *D CLKBUF_X1 -*I buffer33/Z O *D BUF_X4 +*I _760_:A I *D CLKBUF_X1 +*I buffer33:Z O *D BUF_X4 *CAP 1 net33:1 12.38 2 net33:2 11.55 @@ -12082,14 +12082,14 @@ resp_val O 2 net33:2 net33:3 0.005 3 net33:3 net33:4 88.2 4 net33:4 net33:5 0.005 -5 _760_/A net33:1 3.325 -6 buffer33/Z net33:5 3.175 +5 _760_:A net33:1 3.325 +6 buffer33:Z net33:5 3.175 *END *D_NET net34 21.87 *CONN -*I _717_/A I *D CLKBUF_X1 -*I buffer34/Z O *D BUF_X4 +*I _717_:A I *D CLKBUF_X1 +*I buffer34:Z O *D BUF_X4 *CAP 1 net34:1 1.1375 2 net34:2 8.4 @@ -12101,14 +12101,14 @@ resp_val O 2 net34:2 net34:3 33.6 3 net34:3 net34:4 0.005 4 net34:4 net34:5 4.2 -5 _717_/A net34:5 1.395 -6 buffer34/Z net34:1 4.555 +5 _717_:A net34:5 1.395 +6 buffer34:Z net34:1 4.555 *END *D_NET net35 44.635 *CONN -*I _722_/A I *D CLKBUF_X1 -*I buffer35/Z O *D BUF_X4 +*I _722_:A I *D CLKBUF_X1 +*I buffer35:Z O *D BUF_X4 *CAP 1 net35:1 11.55 2 net35:2 12.3375 @@ -12120,15 +12120,15 @@ resp_val O 2 net35:1 net35:3 0.005 3 net35:3 net35:4 37.8 4 net35:4 net35:5 0.005 -5 _722_/A net35:5 2.125 -6 buffer35/Z net35:2 3.155 +5 _722_:A net35:5 2.125 +6 buffer35:Z net35:2 3.155 *END *D_NET net36 64.99 *CONN -*I _759_/A I *D BUF_X2 -*I _858_/Q O *D DFF_X1 -*I buffer36/A I *D BUF_X4 +*I _759_:A I *D BUF_X2 +*I _858_:Q O *D DFF_X1 +*I buffer36:A I *D BUF_X4 *CAP 1 net36:1 0.61 2 net36:2 8.4 @@ -12148,15 +12148,15 @@ resp_val O 6 net36:6 net36:7 8.4 7 net36:7 net36:8 0.005 8 net36:8 net36:9 4.2 -9 _759_/A net36:5 1.025 -10 _858_/Q net36:9 0.525 -11 buffer36/A net36:1 2.445 +9 _759_:A net36:5 1.025 +10 _858_:Q net36:9 0.525 +11 buffer36:A net36:1 2.445 *END *D_NET net37 39.005 *CONN -*I _857_/Z O *D CLKBUF_X1 -*I buffer37/A I *D BUF_X4 +*I _857_:Z O *D CLKBUF_X1 +*I buffer37:A I *D BUF_X4 *CAP 1 net37:1 0.6975 2 net37:2 17.85 @@ -12166,14 +12166,14 @@ resp_val O 1 net37:1 net37:2 0.005 2 net37:2 net37:3 71.4 3 net37:3 net37:4 0.005 -4 _857_/Z net37:4 3.825 -5 buffer37/A net37:1 2.795 +4 _857_:Z net37:4 3.825 +5 buffer37:A net37:1 2.795 *END *D_NET net38 12.36 *CONN -*I _856_/Z O *D CLKBUF_X1 -*I buffer38/A I *D BUF_X4 +*I _856_:Z O *D CLKBUF_X1 +*I buffer38:A I *D BUF_X4 *CAP 1 net38:1 4.2 2 net38:2 4.655 @@ -12185,14 +12185,14 @@ resp_val O 2 net38:1 net38:3 0.005 3 net38:3 net38:4 4.2 4 net38:4 net38:5 0.005 -5 _856_/Z net38:2 1.825 -6 buffer38/A net38:5 1.905 +5 _856_:Z net38:2 1.825 +6 buffer38:A net38:5 1.905 *END *D_NET net39 40.21 *CONN -*I _855_/Z O *D CLKBUF_X1 -*I buffer39/A I *D BUF_X4 +*I _855_:Z O *D CLKBUF_X1 +*I buffer39:A I *D BUF_X4 *CAP 1 net39:1 1.83 2 net39:2 1.05 @@ -12204,27 +12204,27 @@ resp_val O 2 net39:2 net39:3 0.005 3 net39:3 net39:4 71.4 4 net39:4 net39:5 0.005 -5 _855_/Z net39:1 3.125 -6 buffer39/A net39:5 1.705 +5 _855_:Z net39:1 3.125 +6 buffer39:A net39:5 1.705 *END *D_NET net4 5.195 *CONN -*I _800_/A I *D CLKBUF_X1 -*I buffer4/Z O *D BUF_X4 +*I _800_:A I *D CLKBUF_X1 +*I buffer4:Z O *D BUF_X4 *CAP 1 net4:1 2.1875 2 net4:2 1.46 *RES 1 net4:1 net4:2 4.2 -2 _800_/A net4:2 1.645 -3 buffer4/Z net4:1 4.555 +2 _800_:A net4:2 1.645 +3 buffer4:Z net4:1 4.555 *END *D_NET net40 35.435 *CONN -*I _854_/Z O *D CLKBUF_X1 -*I buffer40/A I *D BUF_X4 +*I _854_:Z O *D CLKBUF_X1 +*I buffer40:A I *D BUF_X4 *CAP 1 net40:1 2.1 2 net40:2 2.505 @@ -12236,14 +12236,14 @@ resp_val O 2 net40:1 net40:3 0.005 3 net40:3 net40:4 58.8 4 net40:4 net40:5 0.005 -5 _854_/Z net40:2 1.625 -6 buffer40/A net40:5 2.055 +5 _854_:Z net40:2 1.625 +6 buffer40:A net40:5 2.055 *END *D_NET net41 25.26 *CONN -*I _853_/Z O *D CLKBUF_X1 -*I buffer41/A I *D BUF_X4 +*I _853_:Z O *D CLKBUF_X1 +*I buffer41:A I *D BUF_X4 *CAP 1 net41:1 0.655 2 net41:2 11.55 @@ -12253,14 +12253,14 @@ resp_val O 1 net41:1 net41:2 0.005 2 net41:2 net41:3 46.2 3 net41:3 net41:4 0.005 -4 _853_/Z net41:1 2.625 -5 buffer41/A net41:4 1.705 +4 _853_:Z net41:1 2.625 +5 buffer41:A net41:4 1.705 *END *D_NET net42 24.11 *CONN -*I _852_/Z O *D CLKBUF_X1 -*I buffer42/A I *D BUF_X4 +*I _852_:Z O *D CLKBUF_X1 +*I buffer42:A I *D BUF_X4 *CAP 1 net42:1 0.61 2 net42:2 7.35 @@ -12272,14 +12272,14 @@ resp_val O 2 net42:2 net42:3 29.4 3 net42:3 net42:4 0.005 4 net42:5 net42:4 12.6 -5 _852_/Z net42:5 3.785 -6 buffer42/A net42:1 2.445 +5 _852_:Z net42:5 3.785 +6 buffer42:A net42:1 2.445 *END *D_NET net43 47.88 *CONN -*I _851_/Z O *D CLKBUF_X1 -*I buffer43/A I *D BUF_X4 +*I _851_:Z O *D CLKBUF_X1 +*I buffer43:A I *D BUF_X4 *CAP 1 net43:1 14.7 2 net43:2 15.11 @@ -12291,14 +12291,14 @@ resp_val O 2 net43:1 net43:3 0.005 3 net43:3 net43:4 33.6 4 net43:4 net43:5 0.005 -5 _851_/Z net43:2 1.645 -6 buffer43/A net43:5 1.725 +5 _851_:Z net43:2 1.645 +6 buffer43:A net43:5 1.725 *END *D_NET net44 35.79 *CONN -*I _850_/Z O *D CLKBUF_X1 -*I buffer44/A I *D BUF_X4 +*I _850_:Z O *D CLKBUF_X1 +*I buffer44:A I *D BUF_X4 *CAP 1 net44:1 3.15 2 net44:2 3.76 @@ -12310,14 +12310,14 @@ resp_val O 2 net44:1 net44:3 0.005 3 net44:3 net44:4 54.6 4 net44:4 net44:5 0.005 -5 _850_/Z net44:5 1.945 -6 buffer44/A net44:2 2.445 +5 _850_:Z net44:5 1.945 +6 buffer44:A net44:2 2.445 *END *D_NET net45 37.265 *CONN -*I _849_/Z O *D CLKBUF_X1 -*I buffer45/A I *D BUF_X4 +*I _849_:Z O *D CLKBUF_X1 +*I buffer45:A I *D BUF_X4 *CAP 1 net45:1 13.92 2 net45:2 13.65 @@ -12329,14 +12329,14 @@ resp_val O 2 net45:2 net45:3 0.005 3 net45:3 net45:4 16.8 4 net45:4 net45:5 0.005 -5 _849_/Z net45:1 1.085 -6 buffer45/A net45:5 2.055 +5 _849_:Z net45:1 1.085 +6 buffer45:A net45:5 2.055 *END *D_NET net46 69.65 *CONN -*I _848_/Z O *D CLKBUF_X1 -*I buffer46/A I *D BUF_X4 +*I _848_:Z O *D CLKBUF_X1 +*I buffer46:A I *D BUF_X4 *CAP 1 net46:1 7.26 2 net46:2 6.3 @@ -12348,14 +12348,14 @@ resp_val O 2 net46:2 net46:3 0.005 3 net46:3 net46:4 109.2 4 net46:4 net46:5 0.005 -5 _848_/Z net46:5 1.065 -6 buffer46/A net46:1 3.845 +5 _848_:Z net46:5 1.065 +6 buffer46:A net46:1 3.845 *END *D_NET net47 38.585 *CONN -*I _847_/Z O *D CLKBUF_X1 -*I buffer47/A I *D BUF_X4 +*I _847_:Z O *D CLKBUF_X1 +*I buffer47:A I *D BUF_X4 *CAP 1 net47:1 14.7 2 net47:2 15.455 @@ -12367,14 +12367,14 @@ resp_val O 2 net47:1 net47:3 0.005 3 net47:3 net47:4 12.6 4 net47:4 net47:5 0.005 -5 _847_/Z net47:2 3.025 -6 buffer47/A net47:5 2.755 +5 _847_:Z net47:2 3.025 +6 buffer47:A net47:5 2.755 *END *D_NET net48 78.42 *CONN -*I _846_/Z O *D CLKBUF_X1 -*I buffer48/A I *D BUF_X4 +*I _846_:Z O *D CLKBUF_X1 +*I buffer48:A I *D BUF_X4 *CAP 1 net48:1 11.105 2 net48:2 10.5 @@ -12386,14 +12386,14 @@ resp_val O 2 net48:2 net48:3 0.005 3 net48:3 net48:4 109.2 4 net48:4 net48:5 0.005 -5 _846_/Z net48:5 3.225 -6 buffer48/A net48:1 2.425 +5 _846_:Z net48:5 3.225 +6 buffer48:A net48:1 2.425 *END *D_NET net49 56.64 *CONN -*I _845_/Z O *D CLKBUF_X1 -*I buffer49/A I *D BUF_X4 +*I _845_:Z O *D CLKBUF_X1 +*I buffer49:A I *D BUF_X4 *CAP 1 net49:1 25.2 2 net49:2 25.59 @@ -12405,27 +12405,27 @@ resp_val O 2 net49:1 net49:3 0.005 3 net49:3 net49:4 8.4 4 net49:4 net49:5 0.005 -5 _845_/Z net49:2 1.565 -6 buffer49/A net49:5 2.525 +5 _845_:Z net49:2 1.565 +6 buffer49:A net49:5 2.525 *END *D_NET net5 4.445 *CONN -*I _797_/A I *D CLKBUF_X1 -*I buffer5/Z O *D BUF_X4 +*I _797_:A I *D CLKBUF_X1 +*I buffer5:Z O *D BUF_X4 *CAP 1 net5:1 1.7225 2 net5:2 1.55 *RES 1 net5:2 net5:1 4.2 -2 _797_/A net5:2 2.005 -3 buffer5/Z net5:1 2.695 +2 _797_:A net5:2 2.005 +3 buffer5:Z net5:1 2.695 *END *D_NET net50 35.25 *CONN -*I _844_/Z O *D CLKBUF_X1 -*I buffer50/A I *D BUF_X4 +*I _844_:Z O *D CLKBUF_X1 +*I buffer50:A I *D BUF_X4 *CAP 1 net50:1 1.66 2 net50:2 1.05 @@ -12437,14 +12437,14 @@ resp_val O 2 net50:2 net50:3 0.005 3 net50:3 net50:4 63 4 net50:4 net50:5 0.005 -5 _844_/Z net50:5 0.865 -6 buffer50/A net50:1 2.445 +5 _844_:Z net50:5 0.865 +6 buffer50:A net50:1 2.445 *END *D_NET net51 44.065 *CONN -*I _843_/Z O *D CLKBUF_X1 -*I buffer51/A I *D BUF_X4 +*I _843_:Z O *D CLKBUF_X1 +*I buffer51:A I *D BUF_X4 *CAP 1 net51:1 2.1 2 net51:2 2.6225 @@ -12456,14 +12456,14 @@ resp_val O 2 net51:1 net51:3 0.005 3 net51:3 net51:4 75.6 4 net51:4 net51:5 0.005 -5 _843_/Z net51:5 2.045 -6 buffer51/A net51:2 2.095 +5 _843_:Z net51:5 2.045 +6 buffer51:A net51:2 2.095 *END *D_NET net52 55.61 *CONN -*I _755_/Z O *D CLKBUF_X1 -*I buffer52/A I *D BUF_X4 +*I _755_:Z O *D CLKBUF_X1 +*I buffer52:A I *D BUF_X4 *CAP 1 net52:1 7.35 2 net52:2 8.31 @@ -12475,14 +12475,14 @@ resp_val O 2 net52:1 net52:3 0.005 3 net52:3 net52:4 75.6 4 net52:4 net52:5 0.005 -5 _755_/Z net52:5 2.385 -6 buffer52/A net52:2 3.845 +5 _755_:Z net52:5 2.385 +6 buffer52:A net52:2 3.845 *END *D_NET net53 52.945 *CONN -*I _721_/Z O *D CLKBUF_X1 -*I buffer53/A I *D BUF_X4 +*I _721_:Z O *D CLKBUF_X1 +*I buffer53:A I *D BUF_X4 *CAP 1 net53:1 1.635 2 net53:2 1.05 @@ -12494,27 +12494,27 @@ resp_val O 2 net53:2 net53:3 0.005 3 net53:3 net53:4 96.6 4 net53:4 net53:5 0.005 -5 _721_/Z net53:1 2.345 -6 buffer53/A net53:5 2.755 +5 _721_:Z net53:1 2.345 +6 buffer53:A net53:5 2.755 *END *D_NET net6 13.56 *CONN -*I _794_/A I *D CLKBUF_X1 -*I buffer6/Z O *D BUF_X4 +*I _794_:A I *D CLKBUF_X1 +*I buffer6:Z O *D BUF_X4 *CAP 1 net6:1 6.4975 2 net6:2 6.5825 *RES 1 net6:1 net6:2 25.2 -2 _794_/A net6:2 1.135 -3 buffer6/Z net6:1 0.795 +2 _794_:A net6:2 1.135 +3 buffer6:Z net6:1 0.795 *END *D_NET net7 36.305 *CONN -*I _791_/A I *D CLKBUF_X1 -*I buffer7/Z O *D BUF_X4 +*I _791_:A I *D CLKBUF_X1 +*I buffer7:Z O *D BUF_X4 *CAP 1 net7:1 15.75 2 net7:2 16.3025 @@ -12526,14 +12526,14 @@ resp_val O 2 net7:1 net7:3 0.005 3 net7:3 net7:4 4.2 4 net7:4 net7:5 0.005 -5 _791_/A net7:5 3.205 -6 buffer7/Z net7:2 2.215 +5 _791_:A net7:5 3.205 +6 buffer7:Z net7:2 2.215 *END *D_NET net8 5.37 *CONN -*I _788_/A I *D CLKBUF_X1 -*I buffer8/Z O *D BUF_X4 +*I _788_:A I *D CLKBUF_X1 +*I buffer8:Z O *D BUF_X4 *CAP 1 net8:1 0.3125 2 net8:2 1.05 @@ -12543,14 +12543,14 @@ resp_val O 1 net8:1 net8:2 0.005 2 net8:2 net8:3 4.2 3 net8:3 net8:4 0.005 -4 _788_/A net8:1 1.255 -5 buffer8/Z net8:4 5.295 +4 _788_:A net8:1 1.255 +5 buffer8:Z net8:4 5.295 *END *D_NET net9 5.745 *CONN -*I _785_/A I *D CLKBUF_X1 -*I buffer9/Z O *D BUF_X4 +*I _785_:A I *D CLKBUF_X1 +*I buffer9:Z O *D BUF_X4 *CAP 1 net9:1 0.4775 2 net9:2 1.05 @@ -12562,7 +12562,7 @@ resp_val O 2 net9:2 net9:3 4.2 3 net9:3 net9:4 0.005 4 net9:5 net9:4 4.2 -5 _785_/A net9:5 1.185 -6 buffer9/Z net9:1 1.915 +5 _785_:A net9:5 1.185 +6 buffer9:Z net9:1 1.915 *END diff --git a/src/grt/test/est_rc4_corner1.spefok b/src/grt/test/est_rc4_corner1.spefok index 6f485dd40eb..617b10a5629 100644 --- a/src/grt/test/est_rc4_corner1.spefok +++ b/src/grt/test/est_rc4_corner1.spefok @@ -72,41 +72,41 @@ resp_val O *D_NET clk 660.869 *CONN *P clk I -*I _858_/CK I *D DFF_X1 -*I _859_/CK I *D DFF_X1 -*I _860_/CK I *D DFF_X1 -*I _861_/CK I *D DFF_X1 -*I _862_/CK I *D DFF_X1 -*I _863_/CK I *D DFF_X1 -*I _864_/CK I *D DFF_X1 -*I _865_/CK I *D DFF_X1 -*I _866_/CK I *D DFF_X1 -*I _867_/CK I *D DFF_X1 -*I _868_/CK I *D DFF_X1 -*I _869_/CK I *D DFF_X1 -*I _870_/CK I *D DFF_X1 -*I _871_/CK I *D DFF_X1 -*I _872_/CK I *D DFF_X1 -*I _873_/CK I *D DFF_X1 -*I _874_/CK I *D DFF_X1 -*I _875_/CK I *D DFF_X1 -*I _876_/CK I *D DFF_X1 -*I _877_/CK I *D DFF_X1 -*I _878_/CK I *D DFF_X1 -*I _879_/CK I *D DFF_X1 -*I _880_/CK I *D DFF_X1 -*I _881_/CK I *D DFF_X1 -*I _882_/CK I *D DFF_X1 -*I _883_/CK I *D DFF_X1 -*I _884_/CK I *D DFF_X1 -*I _885_/CK I *D DFF_X1 -*I _886_/CK I *D DFF_X1 -*I _887_/CK I *D DFF_X1 -*I _888_/CK I *D DFF_X1 -*I _889_/CK I *D DFF_X1 -*I _890_/CK I *D DFF_X1 -*I _891_/CK I *D DFF_X1 -*I _892_/CK I *D DFF_X1 +*I _858_:CK I *D DFF_X1 +*I _859_:CK I *D DFF_X1 +*I _860_:CK I *D DFF_X1 +*I _861_:CK I *D DFF_X1 +*I _862_:CK I *D DFF_X1 +*I _863_:CK I *D DFF_X1 +*I _864_:CK I *D DFF_X1 +*I _865_:CK I *D DFF_X1 +*I _866_:CK I *D DFF_X1 +*I _867_:CK I *D DFF_X1 +*I _868_:CK I *D DFF_X1 +*I _869_:CK I *D DFF_X1 +*I _870_:CK I *D DFF_X1 +*I _871_:CK I *D DFF_X1 +*I _872_:CK I *D DFF_X1 +*I _873_:CK I *D DFF_X1 +*I _874_:CK I *D DFF_X1 +*I _875_:CK I *D DFF_X1 +*I _876_:CK I *D DFF_X1 +*I _877_:CK I *D DFF_X1 +*I _878_:CK I *D DFF_X1 +*I _879_:CK I *D DFF_X1 +*I _880_:CK I *D DFF_X1 +*I _881_:CK I *D DFF_X1 +*I _882_:CK I *D DFF_X1 +*I _883_:CK I *D DFF_X1 +*I _884_:CK I *D DFF_X1 +*I _885_:CK I *D DFF_X1 +*I _886_:CK I *D DFF_X1 +*I _887_:CK I *D DFF_X1 +*I _888_:CK I *D DFF_X1 +*I _889_:CK I *D DFF_X1 +*I _890_:CK I *D DFF_X1 +*I _891_:CK I *D DFF_X1 +*I _892_:CK I *D DFF_X1 *CAP 1 clk:1 6.3 2 clk:2 3.21 @@ -316,48 +316,48 @@ resp_val O 101 clk:101 clk:102 0.003 102 clk:102 clk:103 0.003 103 clk:103 clk:104 0.0063 -104 _858_/CK clk:53 2.925 -105 _859_/CK clk:2 4.445 -106 _860_/CK clk:56 5.165 -107 _861_/CK clk:4 4.685 -108 _862_/CK clk:5 4.245 -109 _863_/CK clk:69 2.565 -110 _864_/CK clk:95 6.445 -111 _865_/CK clk:14 3.005 -112 _866_/CK clk:3 5.045 -113 _867_/CK clk:20 5.805 -114 _868_/CK clk:84 4.485 -115 _869_/CK clk:40 2.885 -116 _870_/CK clk:71 3.685 -117 _871_/CK clk:75 1.445 -118 _872_/CK clk:16 2.885 -119 _873_/CK clk:23 8.605 -120 _874_/CK clk:46 1.805 -121 _875_/CK clk:26 6.005 -122 _876_/CK clk:28 3.445 -123 _877_/CK clk:22 4.525 -124 _878_/CK clk:59 5.525 -125 _879_/CK clk:63 2.365 -126 _880_/CK clk:12 5.685 -127 _881_/CK clk:15 1.565 -128 _882_/CK clk:88 1.965 -129 _883_/CK clk:32 2.845 -130 _884_/CK clk:89 3.005 -131 _885_/CK clk:39 2.165 -132 _886_/CK clk:70 4.485 -133 _887_/CK clk:94 3.005 -134 _888_/CK clk:42 5.285 -135 _889_/CK clk:43 6.005 -136 _890_/CK clk:49 2.565 -137 _891_/CK clk:80 3.085 -138 _892_/CK clk:50 3.325 +104 _858_:CK clk:53 2.925 +105 _859_:CK clk:2 4.445 +106 _860_:CK clk:56 5.165 +107 _861_:CK clk:4 4.685 +108 _862_:CK clk:5 4.245 +109 _863_:CK clk:69 2.565 +110 _864_:CK clk:95 6.445 +111 _865_:CK clk:14 3.005 +112 _866_:CK clk:3 5.045 +113 _867_:CK clk:20 5.805 +114 _868_:CK clk:84 4.485 +115 _869_:CK clk:40 2.885 +116 _870_:CK clk:71 3.685 +117 _871_:CK clk:75 1.445 +118 _872_:CK clk:16 2.885 +119 _873_:CK clk:23 8.605 +120 _874_:CK clk:46 1.805 +121 _875_:CK clk:26 6.005 +122 _876_:CK clk:28 3.445 +123 _877_:CK clk:22 4.525 +124 _878_:CK clk:59 5.525 +125 _879_:CK clk:63 2.365 +126 _880_:CK clk:12 5.685 +127 _881_:CK clk:15 1.565 +128 _882_:CK clk:88 1.965 +129 _883_:CK clk:32 2.845 +130 _884_:CK clk:89 3.005 +131 _885_:CK clk:39 2.165 +132 _886_:CK clk:70 4.485 +133 _887_:CK clk:94 3.005 +134 _888_:CK clk:42 5.285 +135 _889_:CK clk:43 6.005 +136 _890_:CK clk:49 2.565 +137 _891_:CK clk:80 3.085 +138 _892_:CK clk:50 3.325 139 clk clk:104 0.0019275 *END *D_NET req_msg[31] 35.4314 *CONN *P req_msg[31] I -*I buffer1/A I *D BUF_X4 +*I buffer1:A I *D BUF_X4 *CAP 1 req_msg[31]:1 4.965 2 req_msg[31]:2 4.2 @@ -381,14 +381,14 @@ resp_val O 8 req_msg[31]:8 req_msg[31]:9 0.003 9 req_msg[31]:9 req_msg[31]:10 0.003 10 req_msg[31]:10 req_msg[31]:11 0.0063 -11 buffer1/A req_msg[31]:1 3.065 +11 buffer1:A req_msg[31]:1 3.065 12 req_msg[31] req_msg[31]:11 0.0029025 *END *D_NET req_msg[30] 14.0457 *CONN *P req_msg[30] I -*I buffer2/A I *D BUF_X4 +*I buffer2:A I *D BUF_X4 *CAP 1 req_msg[30]:1 6.895 2 req_msg[30]:2 6.3 @@ -404,14 +404,14 @@ resp_val O 4 req_msg[30]:4 req_msg[30]:5 0.003 5 req_msg[30]:5 req_msg[30]:6 0.003 6 req_msg[30]:6 req_msg[30]:7 0.0063 -7 buffer2/A req_msg[30]:1 2.385 +7 buffer2:A req_msg[30]:1 2.385 8 req_msg[30] req_msg[30]:7 0.0015075 *END *D_NET req_msg[29] 15.2414 *CONN *P req_msg[29] I -*I buffer3/A I *D BUF_X4 +*I buffer3:A I *D BUF_X4 *CAP 1 req_msg[29]:1 6.3 2 req_msg[29]:2 7.47 @@ -427,14 +427,14 @@ resp_val O 4 req_msg[29]:4 req_msg[29]:5 0.003 5 req_msg[29]:5 req_msg[29]:5 0.003 6 req_msg[29]:6 req_msg[29]:7 0.0063 -7 buffer3/A req_msg[29]:2 4.685 +7 buffer3:A req_msg[29]:2 4.685 8 req_msg[29] req_msg[29]:6 0.0029025 *END *D_NET req_msg[28] 16.4811 *CONN *P req_msg[28] I -*I buffer4/A I *D BUF_X4 +*I buffer4:A I *D BUF_X4 *CAP 1 req_msg[28]:1 4.2 2 req_msg[28]:2 4.2 @@ -450,14 +450,14 @@ resp_val O 4 req_msg[28]:1 req_msg[28]:5 0.005 5 req_msg[28]:5 req_msg[28]:5 0.003 6 req_msg[28]:6 req_msg[28]:7 0.0063 -7 buffer4/A req_msg[28]:4 7.685 +7 buffer4:A req_msg[28]:4 7.685 8 req_msg[28] req_msg[28]:6 0.00294 *END *D_NET req_msg[27] 14.1301 *CONN *P req_msg[27] I -*I buffer5/A I *D BUF_X4 +*I buffer5:A I *D BUF_X4 *CAP 1 req_msg[27]:1 6.935 2 req_msg[27]:2 6.3 @@ -473,14 +473,14 @@ resp_val O 4 req_msg[27]:4 req_msg[27]:5 0.003 5 req_msg[27]:5 req_msg[27]:6 0.003 6 req_msg[27]:6 req_msg[27]:7 0.0063 -7 buffer5/A req_msg[27]:1 2.545 +7 buffer5:A req_msg[27]:1 2.545 8 req_msg[27] req_msg[27]:7 0.0016425 *END *D_NET req_msg[26] 15.0945 *CONN *P req_msg[26] I -*I buffer6/A I *D BUF_X4 +*I buffer6:A I *D BUF_X4 *CAP 1 req_msg[26]:1 6.3 2 req_msg[26]:2 7.4 @@ -496,14 +496,14 @@ resp_val O 4 req_msg[26]:4 req_msg[26]:5 0.003 5 req_msg[26]:5 req_msg[26]:5 0.003 6 req_msg[26]:6 req_msg[26]:7 0.0063 -7 buffer6/A req_msg[26]:2 4.405 +7 buffer6:A req_msg[26]:2 4.405 8 req_msg[26] req_msg[26]:6 0.0026925 *END *D_NET req_msg[25] 14.6239 *CONN *P req_msg[25] I -*I buffer7/A I *D BUF_X4 +*I buffer7:A I *D BUF_X4 *CAP 1 req_msg[25]:1 7.175 2 req_msg[25]:2 6.3 @@ -519,14 +519,14 @@ resp_val O 4 req_msg[25]:4 req_msg[25]:5 0.003 5 req_msg[25]:5 req_msg[25]:6 0.003 6 req_msg[25]:6 req_msg[25]:7 0.0063 -7 buffer7/A req_msg[25]:1 3.505 +7 buffer7:A req_msg[25]:1 3.505 8 req_msg[25] req_msg[25]:7 0.0020625 *END *D_NET req_msg[24] 19.9497 *CONN *P req_msg[24] I -*I buffer8/A I *D BUF_X4 +*I buffer8:A I *D BUF_X4 *CAP 1 req_msg[24]:1 3.65 2 req_msg[24]:2 2.1 @@ -542,14 +542,14 @@ resp_val O 4 req_msg[24]:4 req_msg[24]:5 0.005 5 req_msg[24]:5 req_msg[24]:6 0.003 6 req_msg[24]:6 req_msg[24]:7 0.0063 -7 buffer8/A req_msg[24]:1 6.205 +7 buffer8:A req_msg[24]:1 6.205 8 req_msg[24] req_msg[24]:7 0.004875 *END *D_NET req_msg[23] 15.1508 *CONN *P req_msg[23] I -*I buffer9/A I *D BUF_X4 +*I buffer9:A I *D BUF_X4 *CAP 1 req_msg[23]:1 7.435 2 req_msg[23]:2 6.3 @@ -565,14 +565,14 @@ resp_val O 4 req_msg[23]:4 req_msg[23]:5 0.003 5 req_msg[23]:5 req_msg[23]:6 0.003 6 req_msg[23]:6 req_msg[23]:7 0.0063 -7 buffer9/A req_msg[23]:1 4.545 +7 buffer9:A req_msg[23]:1 4.545 8 req_msg[23] req_msg[23]:7 0.0022725 *END *D_NET req_msg[22] 34.6087 *CONN *P req_msg[22] I -*I buffer10/A I *D BUF_X4 +*I buffer10:A I *D BUF_X4 *CAP 1 req_msg[22]:1 8.4 2 req_msg[22]:2 8.88 @@ -588,14 +588,14 @@ resp_val O 4 req_msg[22]:4 req_msg[22]:5 0.005 5 req_msg[22]:5 req_msg[22]:6 0.003 6 req_msg[22]:6 req_msg[22]:7 0.0063 -7 buffer10/A req_msg[22]:2 1.925 +7 buffer10:A req_msg[22]:2 1.925 8 req_msg[22] req_msg[22]:7 0.004665 *END *D_NET req_msg[21] 14.6987 *CONN *P req_msg[21] I -*I buffer11/A I *D BUF_X4 +*I buffer11:A I *D BUF_X4 *CAP 1 req_msg[21]:1 1.025 2 req_msg[21]:2 6.3 @@ -609,14 +609,14 @@ resp_val O 3 req_msg[21]:3 req_msg[21]:4 0.005 4 req_msg[21]:4 req_msg[21]:5 0.003 5 req_msg[21]:5 req_msg[21]:6 0.0063 -6 buffer11/A req_msg[21]:1 4.105 +6 buffer11:A req_msg[21]:1 4.105 7 req_msg[21] req_msg[21]:6 0.004665 *END *D_NET req_msg[20] 18.7839 *CONN *P req_msg[20] I -*I buffer12/A I *D BUF_X4 +*I buffer12:A I *D BUF_X4 *CAP 1 req_msg[20]:1 2.1 2 req_msg[20]:2 2.1 @@ -640,14 +640,14 @@ resp_val O 8 req_msg[20]:8 req_msg[20]:9 0.003 9 req_msg[20]:9 req_msg[20]:9 0.003 10 req_msg[20]:10 req_msg[20]:11 0.0063 -11 buffer12/A req_msg[20]:6 3.365 +11 buffer12:A req_msg[20]:6 3.365 12 req_msg[20] req_msg[20]:10 0.0029775 *END *D_NET req_msg[19] 14.657 *CONN *P req_msg[19] I -*I buffer13/A I *D BUF_X4 +*I buffer13:A I *D BUF_X4 *CAP 1 req_msg[19]:1 7.195 2 req_msg[19]:2 6.3 @@ -663,14 +663,14 @@ resp_val O 4 req_msg[19]:4 req_msg[19]:5 0.003 5 req_msg[19]:5 req_msg[19]:6 0.003 6 req_msg[19]:6 req_msg[19]:7 0.0063 -7 buffer13/A req_msg[19]:1 3.585 +7 buffer13:A req_msg[19]:1 3.585 8 req_msg[19] req_msg[19]:7 0.0018525 *END *D_NET req_msg[18] 15.0664 *CONN *P req_msg[18] I -*I buffer14/A I *D BUF_X4 +*I buffer14:A I *D BUF_X4 *CAP 1 req_msg[18]:1 7.395 2 req_msg[18]:2 6.3 @@ -686,14 +686,14 @@ resp_val O 4 req_msg[18]:4 req_msg[18]:5 0.003 5 req_msg[18]:5 req_msg[18]:6 0.003 6 req_msg[18]:6 req_msg[18]:7 0.0063 -7 buffer14/A req_msg[18]:1 4.385 +7 buffer14:A req_msg[18]:1 4.385 8 req_msg[18] req_msg[18]:7 0.0021375 *END *D_NET req_msg[17] 13.9941 *CONN *P req_msg[17] I -*I buffer15/A I *D BUF_X4 +*I buffer15:A I *D BUF_X4 *CAP 1 req_msg[17]:1 0.675 2 req_msg[17]:2 6.3 @@ -707,14 +707,14 @@ resp_val O 3 req_msg[17]:3 req_msg[17]:4 0.005 4 req_msg[17]:4 req_msg[17]:5 0.003 5 req_msg[17]:5 req_msg[17]:6 0.0063 -6 buffer15/A req_msg[17]:1 2.705 +6 buffer15:A req_msg[17]:1 2.705 7 req_msg[17] req_msg[17]:6 0.003615 *END *D_NET req_msg[16] 15.5245 *CONN *P req_msg[16] I -*I buffer16/A I *D BUF_X4 +*I buffer16:A I *D BUF_X4 *CAP 1 req_msg[16]:1 7.615 2 req_msg[16]:2 6.3 @@ -730,14 +730,14 @@ resp_val O 4 req_msg[16]:4 req_msg[16]:5 0.003 5 req_msg[16]:5 req_msg[16]:6 0.003 6 req_msg[16]:6 req_msg[16]:7 0.0063 -7 buffer16/A req_msg[16]:1 5.265 +7 buffer16:A req_msg[16]:1 5.265 8 req_msg[16] req_msg[16]:7 0.0026925 *END *D_NET req_msg[15] 36.6326 *CONN *P req_msg[15] I -*I buffer17/A I *D BUF_X4 +*I buffer17:A I *D BUF_X4 *CAP 1 req_msg[15]:1 6.3 2 req_msg[15]:2 6.3 @@ -759,14 +759,14 @@ resp_val O 7 req_msg[15]:7 req_msg[15]:8 0.003 8 req_msg[15]:8 req_msg[15]:9 0.003 9 req_msg[15]:9 req_msg[15]:10 0.0063 -10 buffer17/A req_msg[15]:5 5.545 +10 buffer17:A req_msg[15]:5 5.545 11 req_msg[15] req_msg[15]:10 0.0017175 *END *D_NET req_msg[14] 13.847 *CONN *P req_msg[14] I -*I buffer18/A I *D BUF_X4 +*I buffer18:A I *D BUF_X4 *CAP 1 req_msg[14]:1 6.3 2 req_msg[14]:2 6.79 @@ -782,14 +782,14 @@ resp_val O 4 req_msg[14]:4 req_msg[14]:5 0.003 5 req_msg[14]:5 req_msg[14]:5 0.003 6 req_msg[14]:6 req_msg[14]:7 0.0063 -7 buffer18/A req_msg[14]:2 1.965 +7 buffer18:A req_msg[14]:2 1.965 8 req_msg[14] req_msg[14]:6 0.0018525 *END *D_NET req_msg[13] 14.7477 *CONN *P req_msg[13] I -*I buffer19/A I *D BUF_X4 +*I buffer19:A I *D BUF_X4 *CAP 1 req_msg[13]:1 6.3 2 req_msg[13]:2 7.23 @@ -805,14 +805,14 @@ resp_val O 4 req_msg[13]:4 req_msg[13]:5 0.003 5 req_msg[13]:5 req_msg[13]:5 0.003 6 req_msg[13]:6 req_msg[13]:7 0.0063 -7 buffer19/A req_msg[13]:2 3.725 +7 buffer19:A req_msg[13]:2 3.725 8 req_msg[13] req_msg[13]:6 0.0024825 *END *D_NET req_msg[12] 15.3978 *CONN *P req_msg[12] I -*I buffer20/A I *D BUF_X4 +*I buffer20:A I *D BUF_X4 *CAP 1 req_msg[12]:1 1.375 2 req_msg[12]:2 6.3 @@ -826,14 +826,14 @@ resp_val O 3 req_msg[12]:3 req_msg[12]:4 0.005 4 req_msg[12]:4 req_msg[12]:5 0.003 5 req_msg[12]:5 req_msg[12]:6 0.0063 -6 buffer20/A req_msg[12]:1 5.505 +6 buffer20:A req_msg[12]:1 5.505 7 req_msg[12] req_msg[12]:6 0.004455 *END *D_NET req_msg[11] 14.9301 *CONN *P req_msg[11] I -*I buffer21/A I *D BUF_X4 +*I buffer21:A I *D BUF_X4 *CAP 1 req_msg[11]:1 6.3 2 req_msg[11]:2 7.32 @@ -849,14 +849,14 @@ resp_val O 4 req_msg[11]:4 req_msg[11]:5 0.003 5 req_msg[11]:5 req_msg[11]:5 0.003 6 req_msg[11]:6 req_msg[11]:7 0.0063 -7 buffer21/A req_msg[11]:2 4.085 +7 buffer21:A req_msg[11]:2 4.085 8 req_msg[11] req_msg[11]:6 0.0025575 *END *D_NET req_msg[10] 15.5601 *CONN *P req_msg[10] I -*I buffer22/A I *D BUF_X4 +*I buffer22:A I *D BUF_X4 *CAP 1 req_msg[10]:1 7.635 2 req_msg[10]:2 6.3 @@ -872,14 +872,14 @@ resp_val O 4 req_msg[10]:4 req_msg[10]:5 0.003 5 req_msg[10]:5 req_msg[10]:6 0.003 6 req_msg[10]:6 req_msg[10]:7 0.0063 -7 buffer22/A req_msg[10]:1 5.345 +7 buffer22:A req_msg[10]:1 5.345 8 req_msg[10] req_msg[10]:7 0.0025575 *END *D_NET req_msg[9] 10.8764 *CONN *P req_msg[9] I -*I buffer23/A I *D BUF_X4 +*I buffer23:A I *D BUF_X4 *CAP 1 req_msg[9]:1 4.2 2 req_msg[9]:2 4.2 @@ -893,14 +893,14 @@ resp_val O 3 req_msg[9]:1 req_msg[9]:4 0.005 4 req_msg[9]:4 req_msg[9]:4 0.003 5 req_msg[9]:5 req_msg[9]:6 0.0063 -6 buffer23/A req_msg[9]:3 4.885 +6 buffer23:A req_msg[9]:3 4.885 7 req_msg[9] req_msg[9]:5 0.00189 *END *D_NET req_msg[8] 23.3245 *CONN *P req_msg[8] I -*I buffer24/A I *D BUF_X4 +*I buffer24:A I *D BUF_X4 *CAP 1 req_msg[8]:1 6.3 2 req_msg[8]:2 6.3 @@ -922,14 +922,14 @@ resp_val O 7 req_msg[8]:7 req_msg[8]:8 0.003 8 req_msg[8]:8 req_msg[8]:9 0.003 9 req_msg[8]:9 req_msg[8]:10 0.0063 -10 buffer24/A req_msg[8]:5 4.065 +10 buffer24:A req_msg[8]:5 4.065 11 req_msg[8] req_msg[8]:10 0.0026925 *END *D_NET req_msg[7] 14.3459 *CONN *P req_msg[7] I -*I buffer25/A I *D BUF_X4 +*I buffer25:A I *D BUF_X4 *CAP 1 req_msg[7]:1 0.85 2 req_msg[7]:2 6.3 @@ -943,14 +943,14 @@ resp_val O 3 req_msg[7]:3 req_msg[7]:4 0.005 4 req_msg[7]:4 req_msg[7]:5 0.003 5 req_msg[7]:5 req_msg[7]:6 0.0063 -6 buffer25/A req_msg[7]:1 3.405 +6 buffer25:A req_msg[7]:1 3.405 7 req_msg[7] req_msg[7]:6 0.004035 *END *D_NET req_msg[6] 11.2301 *CONN *P req_msg[6] I -*I buffer26/A I *D BUF_X4 +*I buffer26:A I *D BUF_X4 *CAP 1 req_msg[6]:1 4.2 2 req_msg[6]:2 4.2 @@ -964,14 +964,14 @@ resp_val O 3 req_msg[6]:1 req_msg[6]:4 0.005 4 req_msg[6]:4 req_msg[6]:4 0.003 5 req_msg[6]:5 req_msg[6]:6 0.0063 -6 buffer26/A req_msg[6]:3 5.585 +6 buffer26:A req_msg[6]:3 5.585 7 req_msg[6] req_msg[6]:5 0.00273 *END *D_NET req_msg[5] 28.567 *CONN *P req_msg[5] I -*I buffer27/A I *D BUF_X4 +*I buffer27:A I *D BUF_X4 *CAP 1 req_msg[5]:1 8.4 2 req_msg[5]:2 9.95 @@ -995,14 +995,14 @@ resp_val O 8 req_msg[5]:8 req_msg[5]:9 0.003 9 req_msg[5]:9 req_msg[5]:9 0.003 10 req_msg[5]:10 req_msg[5]:11 0.0063 -11 buffer27/A req_msg[5]:2 6.205 +11 buffer27:A req_msg[5]:2 6.205 12 req_msg[5] req_msg[5]:10 0.0018525 *END *D_NET req_msg[4] 19.9459 *CONN *P req_msg[4] I -*I buffer28/A I *D BUF_X4 +*I buffer28:A I *D BUF_X4 *CAP 1 req_msg[4]:1 3.65 2 req_msg[4]:2 2.1 @@ -1018,14 +1018,14 @@ resp_val O 4 req_msg[4]:4 req_msg[4]:5 0.005 5 req_msg[4]:5 req_msg[4]:6 0.003 6 req_msg[4]:6 req_msg[4]:7 0.0063 -7 buffer28/A req_msg[4]:1 6.205 +7 buffer28:A req_msg[4]:1 6.205 8 req_msg[4] req_msg[4]:7 0.004035 *END *D_NET req_msg[3] 15.0764 *CONN *P req_msg[3] I -*I buffer29/A I *D BUF_X4 +*I buffer29:A I *D BUF_X4 *CAP 1 req_msg[3]:1 2.1 2 req_msg[3]:2 2.1 @@ -1045,14 +1045,14 @@ resp_val O 6 req_msg[3]:6 req_msg[3]:7 0.005 7 req_msg[3]:7 req_msg[3]:7 0.003 8 req_msg[3]:8 req_msg[3]:9 0.0063 -9 buffer29/A req_msg[3]:5 4.885 +9 buffer29:A req_msg[3]:5 4.885 10 req_msg[3] req_msg[3]:8 0.00189 *END *D_NET req_msg[2] 36.7857 *CONN *P req_msg[2] I -*I buffer30/A I *D BUF_X4 +*I buffer30:A I *D BUF_X4 *CAP 1 req_msg[2]:1 5.665 2 req_msg[2]:2 4.2 @@ -1076,14 +1076,14 @@ resp_val O 8 req_msg[2]:8 req_msg[2]:9 0.003 9 req_msg[2]:9 req_msg[2]:10 0.003 10 req_msg[2]:10 req_msg[2]:11 0.0063 -11 buffer30/A req_msg[2]:1 5.865 +11 buffer30:A req_msg[2]:1 5.865 12 req_msg[2] req_msg[2]:11 0.0015075 *END *D_NET req_msg[1] 14.2895 *CONN *P req_msg[1] I -*I buffer31/A I *D BUF_X4 +*I buffer31:A I *D BUF_X4 *CAP 1 req_msg[1]:1 6.3 2 req_msg[1]:2 7.01 @@ -1099,14 +1099,14 @@ resp_val O 4 req_msg[1]:4 req_msg[1]:5 0.003 5 req_msg[1]:5 req_msg[1]:5 0.003 6 req_msg[1]:6 req_msg[1]:7 0.0063 -7 buffer31/A req_msg[1]:2 2.845 +7 buffer31:A req_msg[1]:2 2.845 8 req_msg[1] req_msg[1]:6 0.0019275 *END *D_NET req_msg[0] 14.345 *CONN *P req_msg[0] I -*I buffer32/A I *D BUF_X4 +*I buffer32:A I *D BUF_X4 *CAP 1 req_msg[0]:1 0.85 2 req_msg[0]:2 6.3 @@ -1120,14 +1120,14 @@ resp_val O 3 req_msg[0]:3 req_msg[0]:4 0.005 4 req_msg[0]:4 req_msg[0]:5 0.003 5 req_msg[0]:5 req_msg[0]:6 0.0063 -6 buffer32/A req_msg[0]:1 3.405 +6 buffer32:A req_msg[0]:1 3.405 7 req_msg[0] req_msg[0]:6 0.003825 *END *D_NET req_rdy 35.6583 *CONN *P req_rdy O -*I buffer36/Z O *D BUF_X4 +*I buffer36:Z O *D BUF_X4 *CAP 1 req_rdy:1 6.3 2 req_rdy:2 6.3 @@ -1149,14 +1149,14 @@ resp_val O 7 req_rdy:7 req_rdy:8 0.003 8 req_rdy:8 req_rdy:8 0.003 9 req_rdy:9 req_rdy:10 0.0063 -10 buffer36/Z req_rdy:5 3.505 +10 buffer36:Z req_rdy:5 3.505 11 req_rdy req_rdy:9 0.0031125 *END *D_NET req_val 26.5569 *CONN *P req_val I -*I buffer33/A I *D BUF_X4 +*I buffer33:A I *D BUF_X4 *CAP 1 req_val:1 4.855 2 req_val:2 4.2 @@ -1172,14 +1172,14 @@ resp_val O 4 req_val:4 req_val:5 0.005 5 req_val:5 req_val:6 0.003 6 req_val:6 req_val:7 0.0063 -7 buffer33/A req_val:1 2.625 +7 buffer33:A req_val:1 2.625 8 req_val req_val:7 0.004245 *END *D_NET reset 11.9292 *CONN *P reset I -*I buffer34/A I *D BUF_X4 +*I buffer34:A I *D BUF_X4 *CAP 1 reset:1 4.2 2 reset:2 4.2 @@ -1193,14 +1193,14 @@ resp_val O 3 reset:1 reset:4 0.005 4 reset:4 reset:4 0.003 5 reset:5 reset:6 0.0063 -6 buffer34/A reset:3 6.985 +6 buffer34:A reset:3 6.985 7 reset reset:5 0.00252 *END *D_NET resp_msg[15] 28.6101 *CONN *P resp_msg[15] O -*I buffer37/Z O *D BUF_X4 +*I buffer37:Z O *D BUF_X4 *CAP 1 resp_msg[15]:1 6.3 2 resp_msg[15]:2 6.3 @@ -1224,14 +1224,14 @@ resp_val O 8 resp_msg[15]:8 resp_msg[15]:9 0.003 9 resp_msg[15]:9 resp_msg[15]:9 0.003 10 resp_msg[15]:10 resp_msg[15]:11 0.0063 -11 buffer37/Z resp_msg[15]:6 6.305 +11 buffer37:Z resp_msg[15]:6 6.305 12 resp_msg[15] resp_msg[15]:10 0.0016425 *END *D_NET resp_msg[14] 19.3732 *CONN *P resp_msg[14] O -*I buffer38/Z O *D BUF_X4 +*I buffer38:Z O *D BUF_X4 *CAP 1 resp_msg[14]:1 2.1 2 resp_msg[14]:2 2.1 @@ -1255,14 +1255,14 @@ resp_val O 8 resp_msg[14]:8 resp_msg[14]:9 0.003 9 resp_msg[14]:9 resp_msg[14]:9 0.003 10 resp_msg[14]:10 resp_msg[14]:11 0.0063 -11 buffer38/Z resp_msg[14]:6 4.585 +11 buffer38:Z resp_msg[14]:6 4.585 12 resp_msg[14] resp_msg[14]:10 0.0023475 *END *D_NET resp_msg[13] 10.9359 *CONN *P resp_msg[13] O -*I buffer39/Z O *D BUF_X4 +*I buffer39:Z O *D BUF_X4 *CAP 1 resp_msg[13]:1 1.245 2 resp_msg[13]:2 4.2 @@ -1276,14 +1276,14 @@ resp_val O 3 resp_msg[13]:3 resp_msg[13]:4 0.005 4 resp_msg[13]:4 resp_msg[13]:5 0.003 5 resp_msg[13]:5 resp_msg[13]:6 0.0063 -6 buffer39/Z resp_msg[13]:1 4.985 +6 buffer39:Z resp_msg[13]:1 4.985 7 resp_msg[13] resp_msg[13]:6 0.004035 *END *D_NET resp_msg[12] 33.587 *CONN *P resp_msg[12] O -*I buffer40/Z O *D BUF_X4 +*I buffer40:Z O *D BUF_X4 *CAP 1 resp_msg[12]:1 6.3 2 resp_msg[12]:2 8.245 @@ -1307,14 +1307,14 @@ resp_val O 8 resp_msg[12]:8 resp_msg[12]:9 0.003 9 resp_msg[12]:9 resp_msg[12]:9 0.003 10 resp_msg[12]:10 resp_msg[12]:11 0.0063 -11 buffer40/Z resp_msg[12]:2 7.785 +11 buffer40:Z resp_msg[12]:2 7.785 12 resp_msg[12] resp_msg[12]:10 0.0027675 *END *D_NET resp_msg[11] 12.3406 *CONN *P resp_msg[11] O -*I buffer41/Z O *D BUF_X4 +*I buffer41:Z O *D BUF_X4 *CAP 1 resp_msg[11]:1 1.945 2 resp_msg[11]:2 4.2 @@ -1328,14 +1328,14 @@ resp_val O 3 resp_msg[11]:3 resp_msg[11]:4 0.005 4 resp_msg[11]:4 resp_msg[11]:5 0.003 5 resp_msg[11]:5 resp_msg[11]:6 0.0063 -6 buffer41/Z resp_msg[11]:1 7.785 +6 buffer41:Z resp_msg[11]:1 7.785 7 resp_msg[11] resp_msg[11]:6 0.005085 *END *D_NET resp_msg[10] 14.3911 *CONN *P resp_msg[10] O -*I buffer42/Z O *D BUF_X4 +*I buffer42:Z O *D BUF_X4 *CAP 1 resp_msg[10]:1 6.3 2 resp_msg[10]:2 6.3 @@ -1349,14 +1349,14 @@ resp_val O 3 resp_msg[10]:1 resp_msg[10]:4 0.005 4 resp_msg[10]:4 resp_msg[10]:4 0.003 5 resp_msg[10]:5 resp_msg[10]:6 0.0063 -6 buffer42/Z resp_msg[10]:3 3.505 +6 buffer42:Z resp_msg[10]:3 3.505 7 resp_msg[10] resp_msg[10]:5 0.00294 *END *D_NET resp_msg[9] 13.3708 *CONN *P resp_msg[9] O -*I buffer43/Z O *D BUF_X4 +*I buffer43:Z O *D BUF_X4 *CAP 1 resp_msg[9]:1 6.3 2 resp_msg[9]:2 6.545 @@ -1372,14 +1372,14 @@ resp_val O 4 resp_msg[9]:4 resp_msg[9]:5 0.003 5 resp_msg[9]:5 resp_msg[9]:5 0.003 6 resp_msg[9]:6 resp_msg[9]:7 0.0063 -7 buffer43/Z resp_msg[9]:2 0.985 +7 buffer43:Z resp_msg[9]:2 0.985 8 resp_msg[9] resp_msg[9]:6 0.0022725 *END *D_NET resp_msg[8] 15.7883 *CONN *P resp_msg[8] O -*I buffer44/Z O *D BUF_X4 +*I buffer44:Z O *D BUF_X4 *CAP 1 resp_msg[8]:1 6.3 2 resp_msg[8]:2 6.3 @@ -1393,14 +1393,14 @@ resp_val O 3 resp_msg[8]:1 resp_msg[8]:4 0.005 4 resp_msg[8]:4 resp_msg[8]:4 0.003 5 resp_msg[8]:5 resp_msg[8]:6 0.0063 -6 buffer44/Z resp_msg[8]:3 6.305 +6 buffer44:Z resp_msg[8]:3 6.305 7 resp_msg[8] resp_msg[8]:5 0.00231 *END *D_NET resp_msg[7] 33.642 *CONN *P resp_msg[7] O -*I buffer45/Z O *D BUF_X4 +*I buffer45:Z O *D BUF_X4 *CAP 1 resp_msg[7]:1 6.145 2 resp_msg[7]:2 4.2 @@ -1424,14 +1424,14 @@ resp_val O 8 resp_msg[7]:8 resp_msg[7]:9 0.003 9 resp_msg[7]:9 resp_msg[7]:10 0.003 10 resp_msg[7]:10 resp_msg[7]:11 0.0063 -11 buffer45/Z resp_msg[7]:1 7.785 +11 buffer45:Z resp_msg[7]:1 7.785 12 resp_msg[7] resp_msg[7]:11 0.0044475 *END *D_NET resp_msg[6] 21.3864 *CONN *P resp_msg[6] O -*I buffer46/Z O *D BUF_X4 +*I buffer46:Z O *D BUF_X4 *CAP 1 resp_msg[6]:1 6.3 2 resp_msg[6]:2 6.3 @@ -1447,14 +1447,14 @@ resp_val O 4 resp_msg[6]:1 resp_msg[6]:5 0.005 5 resp_msg[6]:5 resp_msg[6]:5 0.003 6 resp_msg[6]:6 resp_msg[6]:7 0.0063 -7 buffer46/Z resp_msg[6]:4 9.105 +7 buffer46:Z resp_msg[6]:4 9.105 8 resp_msg[6] resp_msg[6]:6 0.00189 *END *D_NET resp_msg[5] 17.9378 *CONN *P resp_msg[5] O -*I buffer47/Z O *D BUF_X4 +*I buffer47:Z O *D BUF_X4 *CAP 1 resp_msg[5]:1 4.745 2 resp_msg[5]:2 2.1 @@ -1470,14 +1470,14 @@ resp_val O 4 resp_msg[5]:4 resp_msg[5]:5 0.005 5 resp_msg[5]:5 resp_msg[5]:6 0.003 6 resp_msg[5]:6 resp_msg[5]:7 0.0063 -7 buffer47/Z resp_msg[5]:1 10.585 +7 buffer47:Z resp_msg[5]:1 10.585 8 resp_msg[5] resp_msg[5]:7 0.004455 *END *D_NET resp_msg[4] 26.2455 *CONN *P resp_msg[4] O -*I buffer48/Z O *D BUF_X4 +*I buffer48:Z O *D BUF_X4 *CAP 1 resp_msg[4]:1 8.4 2 resp_msg[4]:2 8.4 @@ -1493,14 +1493,14 @@ resp_val O 4 resp_msg[4]:1 resp_msg[4]:5 0.005 5 resp_msg[4]:5 resp_msg[4]:5 0.003 6 resp_msg[4]:6 resp_msg[4]:7 0.0063 -7 buffer48/Z resp_msg[4]:4 2.025 +7 buffer48:Z resp_msg[4]:4 2.025 8 resp_msg[4] resp_msg[4]:6 0.00168 *END *D_NET resp_msg[3] 18.7739 *CONN *P resp_msg[3] O -*I buffer49/Z O *D BUF_X4 +*I buffer49:Z O *D BUF_X4 *CAP 1 resp_msg[3]:1 2.1 2 resp_msg[3]:2 2.1 @@ -1524,14 +1524,14 @@ resp_val O 8 resp_msg[3]:8 resp_msg[3]:9 0.003 9 resp_msg[3]:9 resp_msg[3]:9 0.003 10 resp_msg[3]:10 resp_msg[3]:11 0.0063 -11 buffer49/Z resp_msg[3]:6 3.345 +11 buffer49:Z resp_msg[3]:6 3.345 12 resp_msg[3] resp_msg[3]:10 0.0029775 *END *D_NET resp_msg[2] 19.9883 *CONN *P resp_msg[2] O -*I buffer50/Z O *D BUF_X4 +*I buffer50:Z O *D BUF_X4 *CAP 1 resp_msg[2]:1 6.3 2 resp_msg[2]:2 6.3 @@ -1547,14 +1547,14 @@ resp_val O 4 resp_msg[2]:1 resp_msg[2]:5 0.005 5 resp_msg[2]:5 resp_msg[2]:5 0.003 6 resp_msg[2]:6 resp_msg[2]:7 0.0063 -7 buffer50/Z resp_msg[2]:4 6.305 +7 buffer50:Z resp_msg[2]:4 6.305 8 resp_msg[2] resp_msg[2]:6 0.00231 *END *D_NET resp_msg[1] 14.3892 *CONN *P resp_msg[1] O -*I buffer51/Z O *D BUF_X4 +*I buffer51:Z O *D BUF_X4 *CAP 1 resp_msg[1]:1 6.3 2 resp_msg[1]:2 6.3 @@ -1568,14 +1568,14 @@ resp_val O 3 resp_msg[1]:1 resp_msg[1]:4 0.005 4 resp_msg[1]:4 resp_msg[1]:4 0.003 5 resp_msg[1]:5 resp_msg[1]:6 0.0063 -6 buffer51/Z resp_msg[1]:3 3.505 +6 buffer51:Z resp_msg[1]:3 3.505 7 resp_msg[1] resp_msg[1]:5 0.00252 *END *D_NET resp_msg[0] 21.3911 *CONN *P resp_msg[0] O -*I buffer52/Z O *D BUF_X4 +*I buffer52:Z O *D BUF_X4 *CAP 1 resp_msg[0]:1 6.3 2 resp_msg[0]:2 6.3 @@ -1591,14 +1591,14 @@ resp_val O 4 resp_msg[0]:1 resp_msg[0]:5 0.005 5 resp_msg[0]:5 resp_msg[0]:5 0.003 6 resp_msg[0]:6 resp_msg[0]:7 0.0063 -7 buffer52/Z resp_msg[0]:4 9.105 +7 buffer52:Z resp_msg[0]:4 9.105 8 resp_msg[0] resp_msg[0]:6 0.00294 *END *D_NET resp_rdy 23.8301 *CONN *P resp_rdy I -*I buffer35/A I *D BUF_X4 +*I buffer35:A I *D BUF_X4 *CAP 1 resp_rdy:1 6.3 2 resp_rdy:2 6.3 @@ -1618,14 +1618,14 @@ resp_val O 6 resp_rdy:6 resp_rdy:7 0.005 7 resp_rdy:7 resp_rdy:7 0.003 8 resp_rdy:8 resp_rdy:9 0.0063 -9 buffer35/A resp_rdy:5 5.585 +9 buffer35:A resp_rdy:5 5.585 10 resp_rdy resp_rdy:8 0.00273 *END *D_NET resp_val 17.9341 *CONN *P resp_val O -*I buffer53/Z O *D BUF_X4 +*I buffer53:Z O *D BUF_X4 *CAP 1 resp_val:1 4.745 2 resp_val:2 2.1 @@ -1641,14 +1641,14 @@ resp_val O 4 resp_val:4 resp_val:5 0.005 5 resp_val:5 resp_val:6 0.003 6 resp_val:6 resp_val:7 0.0063 -7 buffer53/Z resp_val:1 10.585 +7 buffer53:Z resp_val:1 10.585 8 resp_val resp_val:7 0.003615 *END *D_NET _000_ 12.04 *CONN -*I _762_/Z O *D CLKBUF_X1 -*I _858_/D I *D DFF_X1 +*I _762_:Z O *D CLKBUF_X1 +*I _858_:D I *D DFF_X1 *CAP 1 _000_:1 2.82 2 _000_:2 2.1 @@ -1660,14 +1660,14 @@ resp_val O 2 _000_:2 _000_:3 0.005 3 _000_:3 _000_:4 8.4 4 _000_:4 _000_:5 0.005 -5 _762_/Z _000_:5 4.405 -6 _858_/D _000_:1 2.885 +5 _762_:Z _000_:5 4.405 +6 _858_:D _000_:1 2.885 *END *D_NET _001_ 7.8 *CONN -*I _758_/Z O *D CLKBUF_X1 -*I _859_/D I *D DFF_X1 +*I _758_:Z O *D CLKBUF_X1 +*I _859_:D I *D DFF_X1 *CAP 1 _001_:1 0.36 2 _001_:2 2.1 @@ -1677,51 +1677,51 @@ resp_val O 1 _001_:1 _001_:2 0.005 2 _001_:2 _001_:3 8.4 3 _001_:3 _001_:4 0.005 -4 _758_/Z _001_:4 5.765 -5 _859_/D _001_:1 1.445 +4 _758_:Z _001_:4 5.765 +5 _859_:D _001_:1 1.445 *END *D_NET _002_ 12.02 *CONN -*I _761_/Z O *D CLKBUF_X1 -*I _860_/D I *D DFF_X1 +*I _761_:Z O *D CLKBUF_X1 +*I _860_:D I *D DFF_X1 *CAP 1 _002_:1 3.97 2 _002_:2 4.14 *RES 1 _002_:2 _002_:1 8.4 -2 _761_/Z _002_:1 7.485 -3 _860_/D _002_:2 8.165 +2 _761_:Z _002_:1 7.485 +3 _860_:D _002_:2 8.165 *END *D_NET _003_ 3.76 *CONN -*I _757_/A I *D CLKBUF_X1 -*I _859_/QN O *D DFF_X1 +*I _757_:A I *D CLKBUF_X1 +*I _859_:QN O *D DFF_X1 *CAP 1 _003_:1 1.88 *RES 1 _003_:1 _003_:1 0.005 -2 _757_/A _003_:1 5.065 -3 _859_/QN _003_:1 2.465 +2 _757_:A _003_:1 5.065 +3 _859_:QN _003_:1 2.465 *END *D_NET _004_ 5.54 *CONN -*I _756_/A I *D CLKBUF_X1 -*I _860_/QN O *D DFF_X1 +*I _756_:A I *D CLKBUF_X1 +*I _860_:QN O *D DFF_X1 *CAP 1 _004_:1 2.77 *RES 1 _004_:1 _004_:1 0.005 -2 _756_/A _004_:1 2.865 -3 _860_/QN _004_:1 8.225 +2 _756_:A _004_:1 2.865 +3 _860_:QN _004_:1 8.225 *END *D_NET _005_ 8.07 *CONN -*I _720_/A I *D BUF_X1 -*I _858_/QN O *D DFF_X1 +*I _720_:A I *D BUF_X1 +*I _858_:QN O *D DFF_X1 *CAP 1 _005_:1 0.825 2 _005_:2 2.1 @@ -1731,26 +1731,26 @@ resp_val O 1 _005_:1 _005_:2 0.005 2 _005_:2 _005_:3 8.4 3 _005_:3 _005_:4 0.005 -4 _720_/A _005_:4 4.445 -5 _858_/QN _005_:1 3.305 +4 _720_:A _005_:4 4.445 +5 _858_:QN _005_:1 3.305 *END *D_NET _006_ 3.46 *CONN -*I _763_/A I *D CLKBUF_X1 -*I _877_/QN O *D DFF_X1 +*I _763_:A I *D CLKBUF_X1 +*I _877_:QN O *D DFF_X1 *CAP 1 _006_:1 1.73 *RES 1 _006_:1 _006_:1 0.005 -2 _763_/A _006_:1 6.525 -3 _877_/QN _006_:1 0.405 +2 _763_:A _006_:1 6.525 +3 _877_:QN _006_:1 0.405 *END *D_NET _007_ 11.9 *CONN -*I _766_/A I *D CLKBUF_X1 -*I _878_/QN O *D DFF_X1 +*I _766_:A I *D CLKBUF_X1 +*I _878_:QN O *D DFF_X1 *CAP 1 _007_:1 2.495 2 _007_:2 2.1 @@ -1762,14 +1762,14 @@ resp_val O 2 _007_:2 _007_:3 0.005 3 _007_:3 _007_:4 8.4 4 _007_:4 _007_:5 0.005 -5 _766_/A _007_:5 5.425 -6 _878_/QN _007_:1 1.585 +5 _766_:A _007_:5 5.425 +6 _878_:QN _007_:1 1.585 *END *D_NET _008_ 13.76 *CONN -*I _769_/A I *D CLKBUF_X1 -*I _879_/QN O *D DFF_X1 +*I _769_:A I *D CLKBUF_X1 +*I _879_:QN O *D DFF_X1 *CAP 1 _008_:1 3.12 2 _008_:2 2.1 @@ -1781,14 +1781,14 @@ resp_val O 2 _008_:2 _008_:3 0.005 3 _008_:3 _008_:4 8.4 4 _008_:4 _008_:5 0.005 -5 _769_/A _008_:1 4.085 -6 _879_/QN _008_:5 6.645 +5 _769_:A _008_:1 4.085 +6 _879_:QN _008_:5 6.645 *END *D_NET _009_ 8.04 *CONN -*I _772_/A I *D CLKBUF_X1 -*I _880_/QN O *D DFF_X1 +*I _772_:A I *D CLKBUF_X1 +*I _880_:QN O *D DFF_X1 *CAP 1 _009_:1 1.23 2 _009_:2 2.1 @@ -1798,14 +1798,14 @@ resp_val O 1 _009_:1 _009_:2 0.005 2 _009_:2 _009_:3 8.4 3 _009_:3 _009_:4 0.005 -4 _772_/A _009_:4 2.765 -5 _880_/QN _009_:1 4.925 +4 _772_:A _009_:4 2.765 +5 _880_:QN _009_:1 4.925 *END *D_NET _010_ 16.14 *CONN -*I _775_/A I *D CLKBUF_X1 -*I _881_/QN O *D DFF_X1 +*I _775_:A I *D CLKBUF_X1 +*I _881_:QN O *D DFF_X1 *CAP 1 _010_:1 0.355 2 _010_:2 4.2 @@ -1817,14 +1817,14 @@ resp_val O 2 _010_:2 _010_:3 16.8 3 _010_:3 _010_:4 0.005 4 _010_:4 _010_:5 8.4 -5 _775_/A _010_:1 1.425 -6 _881_/QN _010_:5 5.665 +5 _775_:A _010_:1 1.425 +6 _881_:QN _010_:5 5.665 *END *D_NET _011_ 17.26 *CONN -*I _778_/A I *D CLKBUF_X1 -*I _882_/QN O *D DFF_X1 +*I _778_:A I *D CLKBUF_X1 +*I _882_:QN O *D DFF_X1 *CAP 1 _011_:1 3.365 2 _011_:2 2.1 @@ -1836,27 +1836,27 @@ resp_val O 2 _011_:2 _011_:3 0.005 3 _011_:3 _011_:4 16.8 4 _011_:4 _011_:5 0.005 -5 _778_/A _011_:1 5.065 -6 _882_/QN _011_:5 4.265 +5 _778_:A _011_:1 5.065 +6 _882_:QN _011_:5 4.265 *END *D_NET _012_ 8.24 *CONN -*I _781_/A I *D CLKBUF_X1 -*I _883_/QN O *D DFF_X1 +*I _781_:A I *D CLKBUF_X1 +*I _883_:QN O *D DFF_X1 *CAP 1 _012_:1 3.335 2 _012_:2 2.885 *RES 1 _012_:2 _012_:1 8.4 -2 _781_/A _012_:2 3.145 -3 _883_/QN _012_:1 4.945 +2 _781_:A _012_:2 3.145 +3 _883_:QN _012_:1 4.945 *END *D_NET _013_ 15.04 *CONN -*I _784_/A I *D CLKBUF_X1 -*I _884_/QN O *D DFF_X1 +*I _784_:A I *D CLKBUF_X1 +*I _884_:QN O *D DFF_X1 *CAP 1 _013_:1 2.86 2 _013_:2 2.1 @@ -1868,27 +1868,27 @@ resp_val O 2 _013_:2 _013_:3 0.005 3 _013_:3 _013_:4 16.8 4 _013_:4 _013_:5 0.005 -5 _784_/A _013_:1 3.045 -6 _884_/QN _013_:5 1.845 +5 _784_:A _013_:1 3.045 +6 _884_:QN _013_:5 1.845 *END *D_NET _014_ 6.6 *CONN -*I _787_/A I *D CLKBUF_X1 -*I _885_/QN O *D DFF_X1 +*I _787_:A I *D CLKBUF_X1 +*I _885_:QN O *D DFF_X1 *CAP 1 _014_:1 2.77 2 _014_:2 2.63 *RES 1 _014_:1 _014_:2 8.4 -2 _787_/A _014_:2 2.125 -3 _885_/QN _014_:1 2.685 +2 _787_:A _014_:2 2.125 +3 _885_:QN _014_:1 2.685 *END *D_NET _015_ 7.9 *CONN -*I _790_/A I *D CLKBUF_X1 -*I _886_/QN O *D DFF_X1 +*I _790_:A I *D CLKBUF_X1 +*I _886_:QN O *D DFF_X1 *CAP 1 _015_:1 0.605 2 _015_:2 2.1 @@ -1898,14 +1898,14 @@ resp_val O 1 _015_:1 _015_:2 0.005 2 _015_:2 _015_:3 8.4 3 _015_:3 _015_:4 0.005 -4 _790_/A _015_:4 4.985 -5 _886_/QN _015_:1 2.425 +4 _790_:A _015_:4 4.985 +5 _886_:QN _015_:1 2.425 *END *D_NET _016_ 14.3 *CONN -*I _793_/A I *D CLKBUF_X1 -*I _887_/QN O *D DFF_X1 +*I _793_:A I *D CLKBUF_X1 +*I _887_:QN O *D DFF_X1 *CAP 1 _016_:1 1.23 2 _016_:2 2.1 @@ -1917,27 +1917,27 @@ resp_val O 2 _016_:2 _016_:3 8.4 3 _016_:3 _016_:4 0.005 4 _016_:5 _016_:4 8.4 -5 _793_/A _016_:1 4.925 -6 _887_/QN _016_:5 6.885 +5 _793_:A _016_:1 4.925 +6 _887_:QN _016_:5 6.885 *END *D_NET _017_ 12.19 *CONN -*I _796_/A I *D CLKBUF_X1 -*I _888_/QN O *D DFF_X1 +*I _796_:A I *D CLKBUF_X1 +*I _888_:QN O *D DFF_X1 *CAP 1 _017_:1 5.31 2 _017_:2 4.985 *RES 1 _017_:1 _017_:2 16.8 -2 _796_/A _017_:2 3.145 -3 _888_/QN _017_:1 4.445 +2 _796_:A _017_:2 3.145 +3 _888_:QN _017_:1 4.445 *END *D_NET _018_ 7.76 *CONN -*I _799_/A I *D CLKBUF_X1 -*I _889_/QN O *D DFF_X1 +*I _799_:A I *D CLKBUF_X1 +*I _889_:QN O *D DFF_X1 *CAP 1 _018_:1 0.85 2 _018_:2 2.1 @@ -1947,14 +1947,14 @@ resp_val O 1 _018_:1 _018_:2 0.005 2 _018_:2 _018_:3 8.4 3 _018_:3 _018_:4 0.005 -4 _799_/A _018_:1 3.405 -5 _889_/QN _018_:4 3.725 +4 _799_:A _018_:1 3.405 +5 _889_:QN _018_:4 3.725 *END *D_NET _019_ 12.32 *CONN -*I _802_/A I *D CLKBUF_X1 -*I _890_/QN O *D DFF_X1 +*I _802_:A I *D CLKBUF_X1 +*I _890_:QN O *D DFF_X1 *CAP 1 _019_:1 1.39 2 _019_:2 2.1 @@ -1966,14 +1966,14 @@ resp_val O 2 _019_:2 _019_:3 8.4 3 _019_:3 _019_:4 0.005 4 _019_:5 _019_:4 8.4 -5 _802_/A _019_:1 5.565 -6 _890_/QN _019_:5 2.285 +5 _802_:A _019_:1 5.565 +6 _890_:QN _019_:5 2.285 *END *D_NET _020_ 12.6 *CONN -*I _805_/A I *D CLKBUF_X1 -*I _891_/QN O *D DFF_X1 +*I _805_:A I *D CLKBUF_X1 +*I _891_:QN O *D DFF_X1 *CAP 1 _020_:1 3.025 2 _020_:2 2.1 @@ -1985,14 +1985,14 @@ resp_val O 2 _020_:2 _020_:3 0.005 3 _020_:3 _020_:4 8.4 4 _020_:4 _020_:5 0.005 -5 _805_/A _020_:1 3.705 -6 _891_/QN _020_:5 4.705 +5 _805_:A _020_:1 3.705 +6 _891_:QN _020_:5 4.705 *END *D_NET _021_ 14.38 *CONN -*I _808_/A I *D CLKBUF_X1 -*I _892_/QN O *D DFF_X1 +*I _808_:A I *D CLKBUF_X1 +*I _892_:QN O *D DFF_X1 *CAP 1 _021_:1 3.74 2 _021_:2 2.1 @@ -2004,77 +2004,77 @@ resp_val O 2 _021_:2 _021_:3 0.005 3 _021_:3 _021_:4 8.4 4 _021_:4 _021_:5 0.005 -5 _808_/A _021_:5 5.405 -6 _892_/QN _021_:1 6.565 +5 _808_:A _021_:5 5.405 +6 _892_:QN _021_:1 6.565 *END *D_NET _022_ 6.14 *CONN -*I _765_/Z O *D CLKBUF_X1 -*I _861_/D I *D DFF_X1 +*I _765_:Z O *D CLKBUF_X1 +*I _861_:D I *D DFF_X1 *CAP 1 _022_:1 3.07 *RES 1 _022_:1 _022_:1 0.005 -2 _765_/Z _022_:1 10.125 -3 _861_/D _022_:1 2.165 +2 _765_:Z _022_:1 10.125 +3 _861_:D _022_:1 2.165 *END *D_NET _023_ 5.84 *CONN -*I _795_/Z O *D CLKBUF_X1 -*I _871_/D I *D DFF_X1 +*I _795_:Z O *D CLKBUF_X1 +*I _871_:D I *D DFF_X1 *CAP 1 _023_:1 2.92 *RES 1 _023_:1 _023_:1 0.005 -2 _795_/Z _023_:1 8.685 -3 _871_/D _023_:1 3.005 +2 _795_:Z _023_:1 8.685 +3 _871_:D _023_:1 3.005 *END *D_NET _024_ 9.6 *CONN -*I _798_/Z O *D CLKBUF_X1 -*I _872_/D I *D DFF_X1 +*I _798_:Z O *D CLKBUF_X1 +*I _872_:D I *D DFF_X1 *CAP 1 _024_:1 3.81 2 _024_:2 3.09 *RES 1 _024_:2 _024_:1 8.4 -2 _798_/Z _024_:1 6.845 -3 _872_/D _024_:2 3.965 +2 _798_:Z _024_:1 6.845 +3 _872_:D _024_:2 3.965 *END *D_NET _025_ 8.84 *CONN -*I _801_/Z O *D CLKBUF_X1 -*I _873_/D I *D DFF_X1 +*I _801_:Z O *D CLKBUF_X1 +*I _873_:D I *D DFF_X1 *CAP 1 _025_:1 3.12 2 _025_:2 3.4 *RES 1 _025_:1 _025_:2 8.4 -2 _801_/Z _025_:1 4.085 -3 _873_/D _025_:2 5.205 +2 _801_:Z _025_:1 4.085 +3 _873_:D _025_:2 5.205 *END *D_NET _026_ 9.64 *CONN -*I _804_/Z O *D CLKBUF_X1 -*I _874_/D I *D DFF_X1 +*I _804_:Z O *D CLKBUF_X1 +*I _874_:D I *D DFF_X1 *CAP 1 _026_:1 3.62 2 _026_:2 3.3 *RES 1 _026_:2 _026_:1 8.4 -2 _804_/Z _026_:1 6.085 -3 _874_/D _026_:2 4.805 +2 _804_:Z _026_:1 6.085 +3 _874_:D _026_:2 4.805 *END *D_NET _027_ 12.02 *CONN -*I _807_/Z O *D CLKBUF_X1 -*I _875_/D I *D DFF_X1 +*I _807_:Z O *D CLKBUF_X1 +*I _875_:D I *D DFF_X1 *CAP 1 _027_:1 0.2 2 _027_:2 2.1 @@ -2086,27 +2086,27 @@ resp_val O 2 _027_:2 _027_:3 8.4 3 _027_:3 _027_:4 0.005 4 _027_:5 _027_:4 8.4 -5 _807_/Z _027_:1 0.805 -6 _875_/D _027_:5 6.445 +5 _807_:Z _027_:1 0.805 +6 _875_:D _027_:5 6.445 *END *D_NET _028_ 7.76 *CONN -*I _810_/Z O *D CLKBUF_X1 -*I _876_/D I *D DFF_X1 +*I _810_:Z O *D CLKBUF_X1 +*I _876_:D I *D DFF_X1 *CAP 1 _028_:1 2.69 2 _028_:2 3.29 *RES 1 _028_:1 _028_:2 8.4 -2 _810_/Z _028_:1 2.365 -3 _876_/D _028_:2 4.765 +2 _810_:Z _028_:1 2.365 +3 _876_:D _028_:2 4.765 *END *D_NET _029_ 11.44 *CONN -*I _768_/Z O *D CLKBUF_X1 -*I _862_/D I *D DFF_X1 +*I _768_:Z O *D CLKBUF_X1 +*I _862_:D I *D DFF_X1 *CAP 1 _029_:1 2.41 2 _029_:2 2.1 @@ -2118,26 +2118,26 @@ resp_val O 2 _029_:2 _029_:3 0.005 3 _029_:3 _029_:4 8.4 4 _029_:4 _029_:5 0.005 -5 _768_/Z _029_:5 4.845 -6 _862_/D _029_:1 1.245 +5 _768_:Z _029_:5 4.845 +6 _862_:D _029_:1 1.245 *END *D_NET _030_ 5.44 *CONN -*I _771_/Z O *D CLKBUF_X1 -*I _863_/D I *D DFF_X1 +*I _771_:Z O *D CLKBUF_X1 +*I _863_:D I *D DFF_X1 *CAP 1 _030_:1 2.72 *RES 1 _030_:1 _030_:1 0.005 -2 _771_/Z _030_:1 9.005 -3 _863_/D _030_:1 1.885 +2 _771_:Z _030_:1 9.005 +3 _863_:D _030_:1 1.885 *END *D_NET _031_ 17.74 *CONN -*I _774_/Z O *D CLKBUF_X1 -*I _864_/D I *D DFF_X1 +*I _774_:Z O *D CLKBUF_X1 +*I _864_:D I *D DFF_X1 *CAP 1 _031_:1 4.2 2 _031_:2 6.04 @@ -2149,14 +2149,14 @@ resp_val O 2 _031_:1 _031_:3 0.005 3 _031_:3 _031_:4 8.4 4 _031_:4 _031_:5 0.005 -5 _774_/Z _031_:5 2.925 -6 _864_/D _031_:2 7.365 +5 _774_:Z _031_:5 2.925 +6 _864_:D _031_:2 7.365 *END *D_NET _032_ 12.9 *CONN -*I _777_/Z O *D CLKBUF_X1 -*I _865_/D I *D DFF_X1 +*I _777_:Z O *D CLKBUF_X1 +*I _865_:D I *D DFF_X1 *CAP 1 _032_:1 2.85 2 _032_:2 2.1 @@ -2168,52 +2168,52 @@ resp_val O 2 _032_:2 _032_:3 0.005 3 _032_:3 _032_:4 8.4 4 _032_:4 _032_:5 0.005 -5 _777_/Z _032_:1 3.005 -6 _865_/D _032_:5 6.005 +5 _777_:Z _032_:1 3.005 +6 _865_:D _032_:5 6.005 *END *D_NET _033_ 5.96 *CONN -*I _780_/Z O *D CLKBUF_X1 -*I _866_/D I *D DFF_X1 +*I _780_:Z O *D CLKBUF_X1 +*I _866_:D I *D DFF_X1 *CAP 1 _033_:1 2.47 2 _033_:2 2.61 *RES 1 _033_:1 _033_:2 8.4 -2 _780_/Z _033_:1 1.485 -3 _866_/D _033_:2 2.045 +2 _780_:Z _033_:1 1.485 +3 _866_:D _033_:2 2.045 *END *D_NET _034_ 6.3 *CONN -*I _783_/Z O *D CLKBUF_X1 -*I _867_/D I *D DFF_X1 +*I _783_:Z O *D CLKBUF_X1 +*I _867_:D I *D DFF_X1 *CAP 1 _034_:1 3.15 *RES 1 _034_:1 _034_:1 0.005 -2 _783_/Z _034_:1 5.965 -3 _867_/D _034_:1 6.645 +2 _783_:Z _034_:1 5.965 +3 _867_:D _034_:1 6.645 *END *D_NET _035_ 6.76 *CONN -*I _786_/Z O *D CLKBUF_X1 -*I _868_/D I *D DFF_X1 +*I _786_:Z O *D CLKBUF_X1 +*I _868_:D I *D DFF_X1 *CAP 1 _035_:1 3.01 2 _035_:2 2.47 *RES 1 _035_:1 _035_:2 8.4 -2 _786_/Z _035_:1 3.645 -3 _868_/D _035_:2 1.485 +2 _786_:Z _035_:1 3.645 +3 _868_:D _035_:2 1.485 *END *D_NET _036_ 14.06 *CONN -*I _789_/Z O *D CLKBUF_X1 -*I _869_/D I *D DFF_X1 +*I _789_:Z O *D CLKBUF_X1 +*I _869_:D I *D DFF_X1 *CAP 1 _036_:1 3.17 2 _036_:2 2.1 @@ -2225,14 +2225,14 @@ resp_val O 2 _036_:2 _036_:3 0.005 3 _036_:3 _036_:4 8.4 4 _036_:4 _036_:5 0.005 -5 _789_/Z _036_:5 7.045 -6 _869_/D _036_:1 4.285 +5 _789_:Z _036_:5 7.045 +6 _869_:D _036_:1 4.285 *END *D_NET _037_ 11.58 *CONN -*I _792_/Z O *D CLKBUF_X1 -*I _870_/D I *D DFF_X1 +*I _792_:Z O *D CLKBUF_X1 +*I _870_:D I *D DFF_X1 *CAP 1 _037_:1 0.53 2 _037_:2 2.1 @@ -2244,27 +2244,27 @@ resp_val O 2 _037_:2 _037_:3 8.4 3 _037_:3 _037_:4 0.005 4 _037_:5 _037_:4 8.4 -5 _792_/Z _037_:5 4.245 -6 _870_/D _037_:1 2.125 +5 _792_:Z _037_:5 4.245 +6 _870_:D _037_:1 2.125 *END *D_NET _038_ 7.16 *CONN -*I _812_/Z O *D CLKBUF_X1 -*I _877_/D I *D DFF_X1 +*I _812_:Z O *D CLKBUF_X1 +*I _877_:D I *D DFF_X1 *CAP 1 _038_:1 3.2 2 _038_:2 2.48 *RES 1 _038_:2 _038_:1 8.4 -2 _812_/Z _038_:1 4.405 -3 _877_/D _038_:2 1.525 +2 _812_:Z _038_:1 4.405 +3 _877_:D _038_:2 1.525 *END *D_NET _039_ 14.64 *CONN -*I _832_/Z O *D CLKBUF_X1 -*I _887_/D I *D DFF_X1 +*I _832_:Z O *D CLKBUF_X1 +*I _887_:D I *D DFF_X1 *CAP 1 _039_:1 3.6 2 _039_:2 2.1 @@ -2276,39 +2276,39 @@ resp_val O 2 _039_:2 _039_:3 0.005 3 _039_:3 _039_:4 8.4 4 _039_:4 _039_:5 0.005 -5 _832_/Z _039_:5 6.485 -6 _887_/D _039_:1 6.005 +5 _832_:Z _039_:5 6.485 +6 _887_:D _039_:1 6.005 *END *D_NET _040_ 5.46 *CONN -*I _834_/Z O *D CLKBUF_X1 -*I _888_/D I *D DFF_X1 +*I _834_:Z O *D CLKBUF_X1 +*I _888_:D I *D DFF_X1 *CAP 1 _040_:1 2.73 *RES 1 _040_:1 _040_:1 0.005 -2 _834_/Z _040_:1 6.165 -3 _888_/D _040_:1 4.765 +2 _834_:Z _040_:1 6.165 +3 _888_:D _040_:1 4.765 *END *D_NET _041_ 7.12 *CONN -*I _836_/Z O *D CLKBUF_X1 -*I _889_/D I *D DFF_X1 +*I _836_:Z O *D CLKBUF_X1 +*I _889_:D I *D DFF_X1 *CAP 1 _041_:1 2.55 2 _041_:2 3.11 *RES 1 _041_:2 _041_:1 8.4 -2 _836_/Z _041_:1 1.805 -3 _889_/D _041_:2 4.045 +2 _836_:Z _041_:1 1.805 +3 _889_:D _041_:2 4.045 *END *D_NET _042_ 16.3 *CONN -*I _838_/Z O *D CLKBUF_X1 -*I _890_/D I *D DFF_X1 +*I _838_:Z O *D CLKBUF_X1 +*I _890_:D I *D DFF_X1 *CAP 1 _042_:1 0.47 2 _042_:2 4.2 @@ -2320,14 +2320,14 @@ resp_val O 2 _042_:2 _042_:3 16.8 3 _042_:3 _042_:4 0.005 4 _042_:4 _042_:5 8.4 -5 _838_/Z _042_:5 5.525 -6 _890_/D _042_:1 1.885 +5 _838_:Z _042_:5 5.525 +6 _890_:D _042_:1 1.885 *END *D_NET _043_ 16.38 *CONN -*I _840_/Z O *D CLKBUF_X1 -*I _891_/D I *D DFF_X1 +*I _840_:Z O *D CLKBUF_X1 +*I _891_:D I *D DFF_X1 *CAP 1 _043_:1 3.38 2 _043_:2 2.1 @@ -2339,27 +2339,27 @@ resp_val O 2 _043_:2 _043_:3 0.005 3 _043_:3 _043_:4 16.8 4 _043_:4 _043_:5 0.005 -5 _840_/Z _043_:5 2.445 -6 _891_/D _043_:1 5.125 +5 _840_:Z _043_:5 2.445 +6 _891_:D _043_:1 5.125 *END *D_NET _044_ 11.12 *CONN -*I _842_/Z O *D CLKBUF_X1 -*I _892_/D I *D DFF_X1 +*I _842_:Z O *D CLKBUF_X1 +*I _892_:D I *D DFF_X1 *CAP 1 _044_:1 3.98 2 _044_:2 3.68 *RES 1 _044_:2 _044_:1 8.4 -2 _842_/Z _044_:1 7.525 -3 _892_/D _044_:2 6.325 +2 _842_:Z _044_:1 7.525 +3 _892_:D _044_:2 6.325 *END *D_NET _045_ 12.76 *CONN -*I _814_/Z O *D CLKBUF_X1 -*I _878_/D I *D DFF_X1 +*I _814_:Z O *D CLKBUF_X1 +*I _878_:D I *D DFF_X1 *CAP 1 _045_:1 0.67 2 _045_:2 2.1 @@ -2371,14 +2371,14 @@ resp_val O 2 _045_:2 _045_:3 8.4 3 _045_:3 _045_:4 0.005 4 _045_:5 _045_:4 8.4 -5 _814_/Z _045_:5 6.045 -6 _878_/D _045_:1 2.685 +5 _814_:Z _045_:5 6.045 +6 _878_:D _045_:1 2.685 *END *D_NET _046_ 14.96 *CONN -*I _816_/Z O *D CLKBUF_X1 -*I _879_/D I *D DFF_X1 +*I _816_:Z O *D CLKBUF_X1 +*I _879_:D I *D DFF_X1 *CAP 1 _046_:1 3.3 2 _046_:2 2.1 @@ -2390,14 +2390,14 @@ resp_val O 2 _046_:2 _046_:3 0.005 3 _046_:3 _046_:4 8.4 4 _046_:4 _046_:5 0.005 -5 _816_/Z _046_:5 8.325 -6 _879_/D _046_:1 4.805 +5 _816_:Z _046_:5 8.325 +6 _879_:D _046_:1 4.805 *END *D_NET _047_ 18.06 *CONN -*I _818_/Z O *D CLKBUF_X1 -*I _880_/D I *D DFF_X1 +*I _818_:Z O *D CLKBUF_X1 +*I _880_:D I *D DFF_X1 *CAP 1 _047_:1 3.79 2 _047_:2 2.1 @@ -2411,39 +2411,39 @@ resp_val O 3 _047_:3 _047_:4 8.4 4 _047_:4 _047_:5 0.005 5 _047_:5 _047_:6 8.4 -6 _818_/Z _047_:6 4.165 -7 _880_/D _047_:1 6.765 +6 _818_:Z _047_:6 4.165 +7 _880_:D _047_:1 6.765 *END *D_NET _048_ 4.76 *CONN -*I _820_/Z O *D CLKBUF_X1 -*I _881_/D I *D DFF_X1 +*I _820_:Z O *D CLKBUF_X1 +*I _881_:D I *D DFF_X1 *CAP 1 _048_:1 2.38 *RES 1 _048_:1 _048_:1 0.005 -2 _820_/Z _048_:1 4.965 -3 _881_/D _048_:1 4.565 +2 _820_:Z _048_:1 4.965 +3 _881_:D _048_:1 4.565 *END *D_NET _049_ 7.18 *CONN -*I _822_/Z O *D CLKBUF_X1 -*I _882_/D I *D DFF_X1 +*I _822_:Z O *D CLKBUF_X1 +*I _882_:D I *D DFF_X1 *CAP 1 _049_:1 2.63 2 _049_:2 3.06 *RES 1 _049_:1 _049_:2 8.4 -2 _822_/Z _049_:1 2.125 -3 _882_/D _049_:2 3.845 +2 _822_:Z _049_:1 2.125 +3 _882_:D _049_:2 3.845 *END *D_NET _050_ 12.58 *CONN -*I _824_/Z O *D CLKBUF_X1 -*I _883_/D I *D DFF_X1 +*I _824_:Z O *D CLKBUF_X1 +*I _883_:D I *D DFF_X1 *CAP 1 _050_:1 2.73 2 _050_:2 2.1 @@ -2455,14 +2455,14 @@ resp_val O 2 _050_:2 _050_:3 0.005 3 _050_:3 _050_:4 8.4 4 _050_:4 _050_:5 0.005 -5 _824_/Z _050_:1 2.525 -6 _883_/D _050_:5 5.845 +5 _824_:Z _050_:1 2.525 +6 _883_:D _050_:5 5.845 *END *D_NET _051_ 8.46 *CONN -*I _826_/Z O *D CLKBUF_X1 -*I _884_/D I *D DFF_X1 +*I _826_:Z O *D CLKBUF_X1 +*I _884_:D I *D DFF_X1 *CAP 1 _051_:1 0.36 2 _051_:2 2.1 @@ -2472,27 +2472,27 @@ resp_val O 1 _051_:1 _051_:2 0.005 2 _051_:2 _051_:3 8.4 3 _051_:3 _051_:4 0.005 -4 _826_/Z _051_:4 7.085 -5 _884_/D _051_:1 1.445 +4 _826_:Z _051_:4 7.085 +5 _884_:D _051_:1 1.445 *END *D_NET _052_ 8.64 *CONN -*I _828_/Z O *D CLKBUF_X1 -*I _885_/D I *D DFF_X1 +*I _828_:Z O *D CLKBUF_X1 +*I _885_:D I *D DFF_X1 *CAP 1 _052_:1 3.75 2 _052_:2 2.67 *RES 1 _052_:2 _052_:1 8.4 -2 _828_/Z _052_:1 6.605 -3 _885_/D _052_:2 2.285 +2 _828_:Z _052_:1 6.605 +3 _885_:D _052_:2 2.285 *END *D_NET _053_ 11.4 *CONN -*I _830_/Z O *D CLKBUF_X1 -*I _886_/D I *D DFF_X1 +*I _830_:Z O *D CLKBUF_X1 +*I _886_:D I *D DFF_X1 *CAP 1 _053_:1 0.37 2 _053_:2 2.1 @@ -2504,14 +2504,14 @@ resp_val O 2 _053_:2 _053_:3 8.4 3 _053_:3 _053_:4 0.005 4 _053_:5 _053_:4 8.4 -5 _830_/Z _053_:5 4.525 -6 _886_/D _053_:1 1.485 +5 _830_:Z _053_:5 4.525 +6 _886_:D _053_:1 1.485 *END *D_NET _054_ 19.15 *CONN -*I _465_/ZN O *D OR3_X1 -*I _762_/A I *D CLKBUF_X1 +*I _465_:ZN O *D OR3_X1 +*I _762_:A I *D CLKBUF_X1 *CAP 1 _054_:1 0.705 2 _054_:2 4.2 @@ -2523,14 +2523,14 @@ resp_val O 2 _054_:2 _054_:3 16.8 3 _054_:3 _054_:4 0.005 4 _054_:4 _054_:5 8.4 -5 _465_/ZN _054_:5 10.285 -6 _762_/A _054_:1 2.825 +5 _465_:ZN _054_:5 10.285 +6 _762_:A _054_:1 2.825 *END *D_NET _055_ 18.07 *CONN -*I _455_/ZN O *D NAND2_X1 -*I _758_/A I *D CLKBUF_X1 +*I _455_:ZN O *D NAND2_X1 +*I _758_:A I *D CLKBUF_X1 *CAP 1 _055_:1 1.655 2 _055_:2 6.3 @@ -2540,14 +2540,14 @@ resp_val O 1 _055_:1 _055_:2 0.005 2 _055_:2 _055_:3 25.2 3 _055_:3 _055_:4 0.005 -4 _455_/ZN _055_:4 4.325 -5 _758_/A _055_:1 6.625 +4 _455_:ZN _055_:4 4.325 +5 _758_:A _055_:1 6.625 *END *D_NET _056_ 9.26 *CONN -*I _461_/ZN O *D NAND2_X1 -*I _761_/A I *D CLKBUF_X1 +*I _461_:ZN O *D NAND2_X1 +*I _761_:A I *D CLKBUF_X1 *CAP 1 _056_:1 1.09 2 _056_:2 2.1 @@ -2557,15 +2557,15 @@ resp_val O 1 _056_:1 _056_:2 0.005 2 _056_:2 _056_:3 8.4 3 _056_:3 _056_:4 0.005 -4 _461_/ZN _056_:4 5.765 -5 _761_/A _056_:1 4.365 +4 _461_:ZN _056_:4 5.765 +5 _761_:A _056_:1 4.365 *END *D_NET _057_ 11.09 *CONN -*I _454_/A3 I *D OR3_X1 -*I _463_/A2 I *D NOR2_X1 -*I _757_/Z O *D CLKBUF_X1 +*I _454_:A3 I *D OR3_X1 +*I _463_:A2 I *D NOR2_X1 +*I _757_:Z O *D CLKBUF_X1 *CAP 1 _057_:1 1.27 2 _057_:2 2.1 @@ -2575,15 +2575,15 @@ resp_val O 1 _057_:1 _057_:2 0.005 2 _057_:2 _057_:3 8.4 3 _057_:3 _057_:4 0.005 -4 _454_/A3 _057_:4 5.785 -5 _463_/A2 _057_:4 2.925 -6 _757_/Z _057_:1 5.085 +4 _454_:A3 _057_:4 5.785 +5 _463_:A2 _057_:4 2.925 +6 _757_:Z _057_:1 5.085 *END *D_NET _058_ 11.42 *CONN -*I _451_/A I *D INV_X1 -*I _756_/Z O *D CLKBUF_X1 +*I _451_:A I *D INV_X1 +*I _756_:Z O *D CLKBUF_X1 *CAP 1 _058_:1 3.22 2 _058_:2 2.1 @@ -2595,18 +2595,18 @@ resp_val O 2 _058_:2 _058_:3 0.005 3 _058_:3 _058_:4 8.4 4 _058_:4 _058_:5 0.005 -5 _451_/A _058_:5 1.565 -6 _756_/Z _058_:1 4.485 +5 _451_:A _058_:5 1.565 +6 _756_:Z _058_:1 4.485 *END *D_NET _059_ 52.84 *CONN -*I _439_/A3 I *D AND3_X1 -*I _457_/A I *D INV_X2 -*I _464_/B I *D AOI211_X1 -*I _531_/A2 I *D AND2_X1 -*I _684_/A2 I *D NAND2_X2 -*I _720_/Z O *D BUF_X1 +*I _439_:A3 I *D AND3_X1 +*I _457_:A I *D INV_X2 +*I _464_:B I *D AOI211_X1 +*I _531_:A2 I *D AND2_X1 +*I _684_:A2 I *D NAND2_X2 +*I _720_:Z O *D BUF_X1 *CAP 1 _059_:1 5.685 2 _059_:2 4.035 @@ -2630,31 +2630,31 @@ resp_val O 8 _059_:9 _059_:10 0.005 9 _059_:10 _059_:11 33.6 10 _059_:11 _059_:4 0.005 -11 _439_/A3 _059_:1 5.945 -12 _457_/A _059_:9 4.985 -13 _464_/B _059_:2 7.745 -14 _531_/A2 _059_:4 4.825 -15 _684_/A2 _059_:3 4.245 -16 _720_/Z _059_:5 2.365 +11 _439_:A3 _059_:1 5.945 +12 _457_:A _059_:9 4.985 +13 _464_:B _059_:2 7.745 +14 _531_:A2 _059_:4 4.825 +15 _684_:A2 _059_:3 4.245 +16 _720_:Z _059_:5 2.365 *END *D_NET _060_ 11.13 *CONN -*I _547_/C2 I *D OAI211_X1 -*I _763_/Z O *D CLKBUF_X1 +*I _547_:C2 I *D OAI211_X1 +*I _763_:Z O *D CLKBUF_X1 *CAP 1 _060_:1 4.65 2 _060_:2 3.015 *RES 1 _060_:2 _060_:1 8.4 -2 _547_/C2 _060_:2 3.665 -3 _763_/Z _060_:1 10.205 +2 _547_:C2 _060_:2 3.665 +3 _763_:Z _060_:1 10.205 *END *D_NET _061_ 14.23 *CONN -*I _559_/C2 I *D OAI211_X1 -*I _766_/Z O *D CLKBUF_X1 +*I _559_:C2 I *D OAI211_X1 +*I _766_:Z O *D CLKBUF_X1 *CAP 1 _061_:1 1.35 2 _061_:2 4.2 @@ -2664,14 +2664,14 @@ resp_val O 1 _061_:1 _061_:2 0.005 2 _061_:2 _061_:3 16.8 3 _061_:3 _061_:4 0.005 -4 _559_/C2 _061_:4 6.265 -5 _766_/Z _061_:1 5.405 +4 _559_:C2 _061_:4 6.265 +5 _766_:Z _061_:1 5.405 *END *D_NET _062_ 13.19 *CONN -*I _565_/C2 I *D OAI211_X1 -*I _769_/Z O *D CLKBUF_X1 +*I _565_:C2 I *D OAI211_X1 +*I _769_:Z O *D CLKBUF_X1 *CAP 1 _062_:1 4.015 2 _062_:2 2.1 @@ -2683,14 +2683,14 @@ resp_val O 2 _062_:2 _062_:3 0.005 3 _062_:3 _062_:4 8.4 4 _062_:4 _062_:5 0.005 -5 _565_/C2 _062_:1 7.665 -6 _769_/Z _062_:5 1.925 +5 _565_:C2 _062_:1 7.665 +6 _769_:Z _062_:5 1.925 *END *D_NET _063_ 8.22 *CONN -*I _574_/C2 I *D OAI211_X1 -*I _772_/Z O *D CLKBUF_X1 +*I _574_:C2 I *D OAI211_X1 +*I _772_:Z O *D CLKBUF_X1 *CAP 1 _063_:1 0.93 2 _063_:2 2.1 @@ -2700,14 +2700,14 @@ resp_val O 1 _063_:1 _063_:2 0.005 2 _063_:2 _063_:3 8.4 3 _063_:3 _063_:4 0.005 -4 _574_/C2 _063_:4 4.325 -5 _772_/Z _063_:1 3.725 +4 _574_:C2 _063_:4 4.325 +5 _772_:Z _063_:1 3.725 *END *D_NET _064_ 7.21 *CONN -*I _583_/C2 I *D OAI211_X1 -*I _775_/Z O *D CLKBUF_X1 +*I _583_:C2 I *D OAI211_X1 +*I _775_:Z O *D CLKBUF_X1 *CAP 1 _064_:1 0.745 2 _064_:2 2.1 @@ -2717,14 +2717,14 @@ resp_val O 1 _064_:1 _064_:2 0.005 2 _064_:2 _064_:3 8.4 3 _064_:3 _064_:4 0.005 -4 _583_/C2 _064_:1 2.985 -5 _775_/Z _064_:4 3.045 +4 _583_:C2 _064_:1 2.985 +5 _775_:Z _064_:4 3.045 *END *D_NET _065_ 20 *CONN -*I _591_/C2 I *D OAI211_X1 -*I _778_/Z O *D CLKBUF_X1 +*I _591_:C2 I *D OAI211_X1 +*I _778_:Z O *D CLKBUF_X1 *CAP 1 _065_:1 3.92 2 _065_:2 2.1 @@ -2736,14 +2736,14 @@ resp_val O 2 _065_:2 _065_:3 0.005 3 _065_:3 _065_:4 16.8 4 _065_:4 _065_:5 0.005 -5 _591_/C2 _065_:1 7.285 -6 _778_/Z _065_:5 7.525 +5 _591_:C2 _065_:1 7.285 +6 _778_:Z _065_:5 7.525 *END *D_NET _066_ 9.88 *CONN -*I _599_/C2 I *D OAI211_X1 -*I _781_/Z O *D CLKBUF_X1 +*I _599_:C2 I *D OAI211_X1 +*I _781_:Z O *D CLKBUF_X1 *CAP 1 _066_:1 1.19 2 _066_:2 2.1 @@ -2753,14 +2753,14 @@ resp_val O 1 _066_:1 _066_:2 0.005 2 _066_:2 _066_:3 8.4 3 _066_:3 _066_:4 0.005 -4 _599_/C2 _066_:4 6.605 -5 _781_/Z _066_:1 4.765 +4 _599_:C2 _066_:4 6.605 +5 _781_:Z _066_:1 4.765 *END *D_NET _067_ 12.79 *CONN -*I _608_/C2 I *D OAI211_X1 -*I _784_/Z O *D CLKBUF_X1 +*I _608_:C2 I *D OAI211_X1 +*I _784_:Z O *D CLKBUF_X1 *CAP 1 _067_:1 2.615 2 _067_:2 2.1 @@ -2772,14 +2772,14 @@ resp_val O 2 _067_:2 _067_:3 0.005 3 _067_:3 _067_:4 8.4 4 _067_:4 _067_:5 0.005 -5 _608_/C2 _067_:1 2.065 -6 _784_/Z _067_:5 6.725 +5 _608_:C2 _067_:1 2.065 +6 _784_:Z _067_:5 6.725 *END *D_NET _068_ 14.96 *CONN -*I _617_/C2 I *D OAI211_X1 -*I _787_/Z O *D CLKBUF_X1 +*I _617_:C2 I *D OAI211_X1 +*I _787_:Z O *D CLKBUF_X1 *CAP 1 _068_:1 1.45 2 _068_:2 2.1 @@ -2791,14 +2791,14 @@ resp_val O 2 _068_:2 _068_:3 8.4 3 _068_:3 _068_:4 0.005 4 _068_:5 _068_:4 8.4 -5 _617_/C2 _068_:5 7.325 -6 _787_/Z _068_:1 5.805 +5 _617_:C2 _068_:5 7.325 +6 _787_:Z _068_:1 5.805 *END *D_NET _069_ 6.3 *CONN -*I _626_/C2 I *D OAI211_X1 -*I _790_/Z O *D CLKBUF_X1 +*I _626_:C2 I *D OAI211_X1 +*I _790_:Z O *D CLKBUF_X1 *CAP 1 _069_:1 0.51 2 _069_:2 2.1 @@ -2808,14 +2808,14 @@ resp_val O 1 _069_:1 _069_:2 0.005 2 _069_:2 _069_:3 8.4 3 _069_:3 _069_:4 0.005 -4 _626_/C2 _069_:4 2.165 -5 _790_/Z _069_:1 2.045 +4 _626_:C2 _069_:4 2.165 +5 _790_:Z _069_:1 2.045 *END *D_NET _070_ 14.51 *CONN -*I _635_/C2 I *D OAI211_X1 -*I _793_/Z O *D CLKBUF_X1 +*I _635_:C2 I *D OAI211_X1 +*I _793_:Z O *D CLKBUF_X1 *CAP 1 _070_:1 3.005 2 _070_:2 2.1 @@ -2827,27 +2827,27 @@ resp_val O 2 _070_:2 _070_:3 0.005 3 _070_:3 _070_:4 8.4 4 _070_:4 _070_:5 0.005 -5 _635_/C2 _070_:1 3.625 -6 _793_/Z _070_:5 8.605 +5 _635_:C2 _070_:1 3.625 +6 _793_:Z _070_:5 8.605 *END *D_NET _071_ 10.66 *CONN -*I _638_/B2 I *D OAI21_X1 -*I _796_/Z O *D CLKBUF_X1 +*I _638_:B2 I *D OAI21_X1 +*I _796_:Z O *D CLKBUF_X1 *CAP 1 _071_:1 3.64 2 _071_:2 3.79 *RES 1 _071_:1 _071_:2 8.4 -2 _638_/B2 _071_:2 6.765 -3 _796_/Z _071_:1 6.165 +2 _638_:B2 _071_:2 6.765 +3 _796_:Z _071_:1 6.165 *END *D_NET _072_ 21.59 *CONN -*I _655_/C2 I *D OAI211_X1 -*I _799_/Z O *D CLKBUF_X1 +*I _655_:C2 I *D OAI211_X1 +*I _799_:Z O *D CLKBUF_X1 *CAP 1 _072_:1 5.585 2 _072_:2 4.2 @@ -2859,15 +2859,15 @@ resp_val O 2 _072_:2 _072_:3 0.005 3 _072_:3 _072_:4 16.8 4 _072_:4 _072_:5 0.005 -5 _655_/C2 _072_:1 5.545 -6 _799_/Z _072_:5 4.045 +5 _655_:C2 _072_:1 5.545 +6 _799_:Z _072_:5 4.045 *END *D_NET _073_ 27.41 *CONN -*I _663_/C1 I *D OAI211_X1 -*I _667_/B2 I *D AOI22_X1 -*I _802_/Z O *D CLKBUF_X1 +*I _663_:C1 I *D OAI211_X1 +*I _667_:B2 I *D AOI22_X1 +*I _802_:Z O *D CLKBUF_X1 *CAP 1 _073_:1 0.82 2 _073_:2 2.1 @@ -2885,15 +2885,15 @@ resp_val O 5 _073_:3 _073_:6 16.8 6 _073_:6 _073_:7 0.005 7 _073_:8 _073_:7 8.4 -8 _663_/C1 _073_:1 3.285 -9 _667_/B2 _073_:5 3.345 -10 _802_/Z _073_:8 6.205 +8 _663_:C1 _073_:1 3.285 +9 _667_:B2 _073_:5 3.345 +10 _802_:Z _073_:8 6.205 *END *D_NET _074_ 10.06 *CONN -*I _673_/C1 I *D OAI211_X1 -*I _805_/Z O *D CLKBUF_X1 +*I _673_:C1 I *D OAI211_X1 +*I _805_:Z O *D CLKBUF_X1 *CAP 1 _074_:1 1.76 2 _074_:2 2.1 @@ -2903,40 +2903,40 @@ resp_val O 1 _074_:1 _074_:2 0.005 2 _074_:2 _074_:3 8.4 3 _074_:3 _074_:4 0.005 -4 _673_/C1 _074_:1 7.045 -5 _805_/Z _074_:4 4.685 +4 _673_:C1 _074_:1 7.045 +5 _805_:Z _074_:4 4.685 *END *D_NET _075_ 8.46 *CONN -*I _680_/B2 I *D OAI21_X1 -*I _808_/Z O *D CLKBUF_X1 +*I _680_:B2 I *D OAI21_X1 +*I _808_:Z O *D CLKBUF_X1 *CAP 1 _075_:1 3.77 2 _075_:2 2.56 *RES 1 _075_:1 _075_:2 8.4 -2 _680_/B2 _075_:2 1.845 -3 _808_/Z _075_:1 6.685 +2 _680_:B2 _075_:2 1.845 +3 _808_:Z _075_:1 6.685 *END *D_NET _076_ 10.04 *CONN -*I _551_/Z O *D MUX2_X1 -*I _765_/A I *D CLKBUF_X1 +*I _551_:Z O *D MUX2_X1 +*I _765_:A I *D CLKBUF_X1 *CAP 1 _076_:1 3.41 2 _076_:2 3.71 *RES 1 _076_:1 _076_:2 8.4 -2 _551_/Z _076_:1 5.245 -3 _765_/A _076_:2 6.445 +2 _551_:Z _076_:1 5.245 +3 _765_:A _076_:2 6.445 *END *D_NET _077_ 13.8 *CONN -*I _636_/Z O *D MUX2_X1 -*I _795_/A I *D CLKBUF_X1 +*I _636_:Z O *D MUX2_X1 +*I _795_:A I *D CLKBUF_X1 *CAP 1 _077_:1 1.25 2 _077_:2 2.1 @@ -2948,27 +2948,27 @@ resp_val O 2 _077_:2 _077_:3 8.4 3 _077_:3 _077_:4 0.005 4 _077_:5 _077_:4 8.4 -5 _636_/Z _077_:5 5.805 -6 _795_/A _077_:1 5.005 +5 _636_:Z _077_:5 5.805 +6 _795_:A _077_:1 5.005 *END *D_NET _078_ 6.47 *CONN -*I _646_/ZN O *D OAI21_X1 -*I _798_/A I *D CLKBUF_X1 +*I _646_:ZN O *D OAI21_X1 +*I _798_:A I *D CLKBUF_X1 *CAP 1 _078_:1 2.445 2 _078_:2 2.89 *RES 1 _078_:2 _078_:1 8.4 -2 _646_/ZN _078_:1 1.385 -3 _798_/A _078_:2 3.165 +2 _646_:ZN _078_:1 1.385 +3 _798_:A _078_:2 3.165 *END *D_NET _079_ 7.79 *CONN -*I _656_/Z O *D MUX2_X1 -*I _801_/A I *D CLKBUF_X1 +*I _656_:Z O *D MUX2_X1 +*I _801_:A I *D CLKBUF_X1 *CAP 1 _079_:1 0.77 2 _079_:2 2.1 @@ -2978,27 +2978,27 @@ resp_val O 1 _079_:1 _079_:2 0.005 2 _079_:2 _079_:3 8.4 3 _079_:3 _079_:4 0.005 -4 _656_/Z _079_:1 3.085 -5 _801_/A _079_:4 4.105 +4 _656_:Z _079_:1 3.085 +5 _801_:A _079_:4 4.105 *END *D_NET _080_ 10.26 *CONN -*I _664_/Z O *D MUX2_X1 -*I _804_/A I *D CLKBUF_X1 +*I _664_:Z O *D MUX2_X1 +*I _804_:A I *D CLKBUF_X1 *CAP 1 _080_:1 3.77 2 _080_:2 3.46 *RES 1 _080_:2 _080_:1 8.4 -2 _664_/Z _080_:1 6.685 -3 _804_/A _080_:2 5.445 +2 _664_:Z _080_:1 6.685 +3 _804_:A _080_:2 5.445 *END *D_NET _081_ 12.44 *CONN -*I _674_/Z O *D MUX2_X1 -*I _807_/A I *D CLKBUF_X1 +*I _674_:Z O *D MUX2_X1 +*I _807_:A I *D CLKBUF_X1 *CAP 1 _081_:1 2.84 2 _081_:2 2.1 @@ -3010,14 +3010,14 @@ resp_val O 2 _081_:2 _081_:3 0.005 3 _081_:3 _081_:4 8.4 4 _081_:4 _081_:5 0.005 -5 _674_/Z _081_:5 5.125 -6 _807_/A _081_:1 2.965 +5 _674_:Z _081_:5 5.125 +6 _807_:A _081_:1 2.965 *END *D_NET _082_ 9.22 *CONN -*I _682_/ZN O *D OAI21_X1 -*I _810_/A I *D CLKBUF_X1 +*I _682_:ZN O *D OAI21_X1 +*I _810_:A I *D CLKBUF_X1 *CAP 1 _082_:1 1.345 2 _082_:2 2.1 @@ -3027,14 +3027,14 @@ resp_val O 1 _082_:1 _082_:2 0.005 2 _082_:2 _082_:3 8.4 3 _082_:3 _082_:4 0.005 -4 _682_/ZN _082_:1 5.385 -5 _810_/A _082_:4 4.665 +4 _682_:ZN _082_:1 5.385 +5 _810_:A _082_:4 4.665 *END *D_NET _083_ 14.7 *CONN -*I _560_/Z O *D MUX2_X1 -*I _768_/A I *D CLKBUF_X1 +*I _560_:Z O *D MUX2_X1 +*I _768_:A I *D CLKBUF_X1 *CAP 1 _083_:1 2.51 2 _083_:2 2.1 @@ -3046,52 +3046,52 @@ resp_val O 2 _083_:2 _083_:3 0.005 3 _083_:3 _083_:4 16.8 4 _083_:4 _083_:5 0.005 -5 _560_/Z _083_:5 2.565 -6 _768_/A _083_:1 1.645 +5 _560_:Z _083_:5 2.565 +6 _768_:A _083_:1 1.645 *END *D_NET _084_ 13.1 *CONN -*I _566_/Z O *D MUX2_X1 -*I _771_/A I *D CLKBUF_X1 +*I _566_:Z O *D MUX2_X1 +*I _771_:A I *D CLKBUF_X1 *CAP 1 _084_:1 4.46 2 _084_:2 6.29 *RES 1 _084_:1 _084_:2 16.8 -2 _566_/Z _084_:1 1.045 -3 _771_/A _084_:2 8.365 +2 _566_:Z _084_:1 1.045 +3 _771_:A _084_:2 8.365 *END *D_NET _085_ 6.4 *CONN -*I _575_/Z O *D MUX2_X1 -*I _774_/A I *D CLKBUF_X1 +*I _575_:Z O *D MUX2_X1 +*I _774_:A I *D CLKBUF_X1 *CAP 1 _085_:1 3.2 *RES 1 _085_:1 _085_:1 0.005 -2 _575_/Z _085_:1 7.725 -3 _774_/A _085_:1 5.085 +2 _575_:Z _085_:1 7.725 +3 _774_:A _085_:1 5.085 *END *D_NET _086_ 7.12 *CONN -*I _584_/Z O *D MUX2_X1 -*I _777_/A I *D CLKBUF_X1 +*I _584_:Z O *D MUX2_X1 +*I _777_:A I *D CLKBUF_X1 *CAP 1 _086_:1 3.03 2 _086_:2 2.63 *RES 1 _086_:2 _086_:1 8.4 -2 _584_/Z _086_:1 3.725 -3 _777_/A _086_:2 2.125 +2 _584_:Z _086_:1 3.725 +3 _777_:A _086_:2 2.125 *END *D_NET _087_ 6.37 *CONN -*I _592_/Z O *D MUX2_X1 -*I _780_/A I *D CLKBUF_X1 +*I _592_:Z O *D MUX2_X1 +*I _780_:A I *D CLKBUF_X1 *CAP 1 _087_:1 0.7 2 _087_:2 2.1 @@ -3101,39 +3101,39 @@ resp_val O 1 _087_:1 _087_:2 0.005 2 _087_:2 _087_:3 8.4 3 _087_:3 _087_:4 0.005 -4 _592_/Z _087_:1 2.805 -5 _780_/A _087_:4 1.545 +4 _592_:Z _087_:1 2.805 +5 _780_:A _087_:4 1.545 *END *D_NET _088_ 5.72 *CONN -*I _600_/Z O *D MUX2_X1 -*I _783_/A I *D CLKBUF_X1 +*I _600_:Z O *D MUX2_X1 +*I _783_:A I *D CLKBUF_X1 *CAP 1 _088_:1 2.29 2 _088_:2 2.67 *RES 1 _088_:2 _088_:1 8.4 -2 _600_/Z _088_:1 0.765 -3 _783_/A _088_:2 2.285 +2 _600_:Z _088_:1 0.765 +3 _783_:A _088_:2 2.285 *END *D_NET _089_ 5.45 *CONN -*I _609_/Z O *D MUX2_X1 -*I _786_/A I *D CLKBUF_X1 +*I _609_:Z O *D MUX2_X1 +*I _786_:A I *D CLKBUF_X1 *CAP 1 _089_:1 2.725 *RES 1 _089_:1 _089_:1 0.005 -2 _609_/Z _089_:1 7.285 -3 _786_/A _089_:1 3.625 +2 _609_:Z _089_:1 7.285 +3 _786_:A _089_:1 3.625 *END *D_NET _090_ 17.94 *CONN -*I _618_/Z O *D MUX2_X1 -*I _789_/A I *D CLKBUF_X1 +*I _618_:Z O *D MUX2_X1 +*I _789_:A I *D CLKBUF_X1 *CAP 1 _090_:1 3.7 2 _090_:2 2.1 @@ -3145,14 +3145,14 @@ resp_val O 2 _090_:2 _090_:3 0.005 3 _090_:3 _090_:4 16.8 4 _090_:4 _090_:5 0.005 -5 _618_/Z _090_:5 4.285 -6 _789_/A _090_:1 6.405 +5 _618_:Z _090_:5 4.285 +6 _789_:A _090_:1 6.405 *END *D_NET _091_ 19.89 *CONN -*I _627_/Z O *D MUX2_X1 -*I _792_/A I *D CLKBUF_X1 +*I _627_:Z O *D MUX2_X1 +*I _792_:A I *D CLKBUF_X1 *CAP 1 _091_:1 3.915 2 _091_:2 2.1 @@ -3166,14 +3166,14 @@ resp_val O 3 _091_:3 _091_:4 8.4 4 _091_:4 _091_:5 0.005 5 _091_:5 _091_:6 8.4 -6 _627_/Z _091_:6 7.325 -7 _792_/A _091_:1 7.265 +6 _627_:Z _091_:6 7.325 +7 _792_:A _091_:1 7.265 *END *D_NET _092_ 18.7 *CONN -*I _686_/Z O *D MUX2_X1 -*I _812_/A I *D CLKBUF_X1 +*I _686_:Z O *D MUX2_X1 +*I _812_:A I *D CLKBUF_X1 *CAP 1 _092_:1 0.52 2 _092_:2 4.2 @@ -3185,14 +3185,14 @@ resp_val O 2 _092_:2 _092_:3 16.8 3 _092_:3 _092_:4 0.005 4 _092_:4 _092_:5 8.4 -5 _686_/Z _092_:5 10.125 -6 _812_/A _092_:1 2.085 +5 _686_:Z _092_:5 10.125 +6 _812_:A _092_:1 2.085 *END *D_NET _093_ 13.38 *CONN -*I _706_/Z O *D MUX2_X1 -*I _832_/A I *D CLKBUF_X1 +*I _706_:Z O *D MUX2_X1 +*I _832_:A I *D CLKBUF_X1 *CAP 1 _093_:1 1.46 2 _093_:2 2.1 @@ -3204,52 +3204,52 @@ resp_val O 2 _093_:2 _093_:3 8.4 3 _093_:3 _093_:4 0.005 4 _093_:5 _093_:4 8.4 -5 _706_/Z _093_:5 4.125 -6 _832_/A _093_:1 5.845 +5 _706_:Z _093_:5 4.125 +6 _832_:A _093_:1 5.845 *END *D_NET _094_ 5.16 *CONN -*I _708_/Z O *D MUX2_X1 -*I _834_/A I *D CLKBUF_X1 +*I _708_:Z O *D MUX2_X1 +*I _834_:A I *D CLKBUF_X1 *CAP 1 _094_:1 2.58 *RES 1 _094_:1 _094_:1 0.005 -2 _708_/Z _094_:1 7.845 -3 _834_/A _094_:1 2.485 +2 _708_:Z _094_:1 7.845 +3 _834_:A _094_:1 2.485 *END *D_NET _095_ 8.28 *CONN -*I _710_/Z O *D MUX2_X1 -*I _836_/A I *D CLKBUF_X1 +*I _710_:Z O *D MUX2_X1 +*I _836_:A I *D CLKBUF_X1 *CAP 1 _095_:1 3.67 2 _095_:2 2.57 *RES 1 _095_:2 _095_:1 8.4 -2 _710_/Z _095_:1 6.285 -3 _836_/A _095_:2 1.885 +2 _710_:Z _095_:1 6.285 +3 _836_:A _095_:2 1.885 *END *D_NET _096_ 9.16 *CONN -*I _712_/Z O *D MUX2_X1 -*I _838_/A I *D CLKBUF_X1 +*I _712_:Z O *D MUX2_X1 +*I _838_:A I *D CLKBUF_X1 *CAP 1 _096_:1 3.36 2 _096_:2 3.32 *RES 1 _096_:2 _096_:1 8.4 -2 _712_/Z _096_:1 5.045 -3 _838_/A _096_:2 4.885 +2 _712_:Z _096_:1 5.045 +3 _838_:A _096_:2 4.885 *END *D_NET _097_ 13.39 *CONN -*I _714_/Z O *D MUX2_X1 -*I _840_/A I *D CLKBUF_X1 +*I _714_:Z O *D MUX2_X1 +*I _840_:A I *D CLKBUF_X1 *CAP 1 _097_:1 0.965 2 _097_:2 2.1 @@ -3261,14 +3261,14 @@ resp_val O 2 _097_:2 _097_:3 8.4 3 _097_:3 _097_:4 0.005 4 _097_:5 _097_:4 8.4 -5 _714_/Z _097_:5 6.125 -6 _840_/A _097_:1 3.865 +5 _714_:Z _097_:5 6.125 +6 _840_:A _097_:1 3.865 *END *D_NET _098_ 13.04 *CONN -*I _716_/Z O *D MUX2_X1 -*I _842_/A I *D CLKBUF_X1 +*I _716_:Z O *D MUX2_X1 +*I _842_:A I *D CLKBUF_X1 *CAP 1 _098_:1 2.7 2 _098_:2 2.1 @@ -3280,14 +3280,14 @@ resp_val O 2 _098_:2 _098_:3 0.005 3 _098_:3 _098_:4 8.4 4 _098_:4 _098_:5 0.005 -5 _716_/Z _098_:1 2.405 -6 _842_/A _098_:5 6.885 +5 _716_:Z _098_:1 2.405 +6 _842_:A _098_:5 6.885 *END *D_NET _099_ 9.29 *CONN -*I _688_/Z O *D MUX2_X1 -*I _814_/A I *D CLKBUF_X1 +*I _688_:Z O *D MUX2_X1 +*I _814_:A I *D CLKBUF_X1 *CAP 1 _099_:1 1.585 2 _099_:2 2.1 @@ -3297,14 +3297,14 @@ resp_val O 1 _099_:1 _099_:2 0.005 2 _099_:2 _099_:3 8.4 3 _099_:3 _099_:4 0.005 -4 _688_/Z _099_:4 3.845 -5 _814_/A _099_:1 6.345 +4 _688_:Z _099_:4 3.845 +5 _814_:A _099_:1 6.345 *END *D_NET _100_ 14.24 *CONN -*I _690_/Z O *D MUX2_X1 -*I _816_/A I *D CLKBUF_X1 +*I _690_:Z O *D MUX2_X1 +*I _816_:A I *D CLKBUF_X1 *CAP 1 _100_:1 1.92 2 _100_:2 2.1 @@ -3316,27 +3316,27 @@ resp_val O 2 _100_:2 _100_:3 8.4 3 _100_:3 _100_:4 0.005 4 _100_:5 _100_:4 8.4 -5 _690_/Z _100_:5 4.005 -6 _816_/A _100_:1 7.685 +5 _690_:Z _100_:5 4.005 +6 _816_:A _100_:1 7.685 *END *D_NET _101_ 7.73 *CONN -*I _692_/Z O *D MUX2_X1 -*I _818_/A I *D CLKBUF_X1 +*I _692_:Z O *D MUX2_X1 +*I _818_:A I *D CLKBUF_X1 *CAP 1 _101_:1 2.82 2 _101_:2 3.145 *RES 1 _101_:1 _101_:2 8.4 -2 _692_/Z _101_:1 2.885 -3 _818_/A _101_:2 4.185 +2 _692_:Z _101_:1 2.885 +3 _818_:A _101_:2 4.185 *END *D_NET _102_ 18.79 *CONN -*I _694_/Z O *D MUX2_X1 -*I _820_/A I *D CLKBUF_X1 +*I _694_:Z O *D MUX2_X1 +*I _820_:A I *D CLKBUF_X1 *CAP 1 _102_:1 3.335 2 _102_:2 2.1 @@ -3350,65 +3350,65 @@ resp_val O 3 _102_:3 _102_:4 8.4 4 _102_:4 _102_:5 0.005 5 _102_:5 _102_:6 8.4 -6 _694_/Z _102_:6 7.445 -7 _820_/A _102_:1 4.945 +6 _694_:Z _102_:6 7.445 +7 _820_:A _102_:1 4.945 *END *D_NET _103_ 5.19 *CONN -*I _696_/Z O *D MUX2_X1 -*I _822_/A I *D CLKBUF_X1 +*I _696_:Z O *D MUX2_X1 +*I _822_:A I *D CLKBUF_X1 *CAP 1 _103_:1 2.595 *RES 1 _103_:1 _103_:1 0.005 -2 _696_/Z _103_:1 5.245 -3 _822_/A _103_:1 5.145 +2 _696_:Z _103_:1 5.245 +3 _822_:A _103_:1 5.145 *END *D_NET _104_ 12.29 *CONN -*I _698_/Z O *D MUX2_X1 -*I _824_/A I *D CLKBUF_X1 +*I _698_:Z O *D MUX2_X1 +*I _824_:A I *D CLKBUF_X1 *CAP 1 _104_:1 4.425 2 _104_:2 5.92 *RES 1 _104_:1 _104_:2 16.8 -2 _698_/Z _104_:2 6.885 -3 _824_/A _104_:1 0.905 +2 _698_:Z _104_:2 6.885 +3 _824_:A _104_:1 0.905 *END *D_NET _105_ 11.06 *CONN -*I _700_/Z O *D MUX2_X1 -*I _826_/A I *D CLKBUF_X1 +*I _700_:Z O *D MUX2_X1 +*I _826_:A I *D CLKBUF_X1 *CAP 1 _105_:1 3.92 2 _105_:2 3.71 *RES 1 _105_:2 _105_:1 8.4 -2 _700_/Z _105_:1 7.285 -3 _826_/A _105_:2 6.445 +2 _700_:Z _105_:1 7.285 +3 _826_:A _105_:2 6.445 *END *D_NET _106_ 7.92 *CONN -*I _702_/Z O *D MUX2_X1 -*I _828_/A I *D CLKBUF_X1 +*I _702_:Z O *D MUX2_X1 +*I _828_:A I *D CLKBUF_X1 *CAP 1 _106_:1 2.65 2 _106_:2 3.41 *RES 1 _106_:1 _106_:2 8.4 -2 _702_/Z _106_:1 2.205 -3 _828_/A _106_:2 5.245 +2 _702_:Z _106_:1 2.205 +3 _828_:A _106_:2 5.245 *END *D_NET _107_ 17.41 *CONN -*I _704_/Z O *D MUX2_X1 -*I _830_/A I *D CLKBUF_X1 +*I _704_:Z O *D MUX2_X1 +*I _830_:A I *D CLKBUF_X1 *CAP 1 _107_:1 0.965 2 _107_:2 4.2 @@ -3420,30 +3420,30 @@ resp_val O 2 _107_:2 _107_:3 16.8 3 _107_:3 _107_:4 0.005 4 _107_:4 _107_:5 8.4 -5 _704_/Z _107_:5 5.765 -6 _830_/A _107_:1 3.865 +5 _704_:Z _107_:5 5.765 +6 _830_:A _107_:1 3.865 *END *D_NET _108_ 12.23 *CONN -*I _439_/A2 I *D AND3_X1 -*I _719_/Z O *D CLKBUF_X1 +*I _439_:A2 I *D AND3_X1 +*I _719_:Z O *D CLKBUF_X1 *CAP 1 _108_:1 4.64 2 _108_:2 3.575 *RES 1 _108_:2 _108_:1 8.4 -2 _439_/A2 _108_:2 5.905 -3 _719_/Z _108_:1 10.165 +2 _439_:A2 _108_:2 5.905 +3 _719_:Z _108_:1 10.165 *END *D_NET _109_ 23.52 *CONN -*I _438_/A I *D INV_X2 -*I _531_/A1 I *D AND2_X1 -*I _544_/A2 I *D NAND2_X1 -*I _548_/A1 I *D OR2_X1 -*I _718_/Z O *D CLKBUF_X1 +*I _438_:A I *D INV_X2 +*I _531_:A1 I *D AND2_X1 +*I _544_:A2 I *D NAND2_X1 +*I _548_:A1 I *D OR2_X1 +*I _718_:Z O *D CLKBUF_X1 *CAP 1 _109_:1 3.395 2 _109_:2 2.1 @@ -3457,20 +3457,20 @@ resp_val O 3 _109_:3 _109_:4 0.005 4 _109_:6 _109_:5 8.4 5 _109_:1 _109_:6 8.4 -6 _438_/A _109_:6 2.325 -7 _531_/A1 _109_:4 4.065 -8 _544_/A2 _109_:4 5.005 -9 _548_/A1 _109_:1 5.185 -10 _718_/Z _109_:5 5.285 +6 _438_:A _109_:6 2.325 +7 _531_:A1 _109_:4 4.065 +8 _544_:A2 _109_:4 5.005 +9 _548_:A1 _109_:1 5.185 +10 _718_:Z _109_:5 5.285 *END *D_NET _110_ 70.01 *CONN -*I _440_/A I *D XOR2_X1 -*I _483_/A I *D INV_X1 -*I _551_/A I *D MUX2_X1 -*I _683_/A I *D MUX2_X1 -*I _753_/Z O *D CLKBUF_X1 +*I _440_:A I *D XOR2_X1 +*I _483_:A I *D INV_X1 +*I _551_:A I *D MUX2_X1 +*I _683_:A I *D MUX2_X1 +*I _753_:Z O *D CLKBUF_X1 *CAP 1 _110_:1 4.815 2 _110_:2 5.585 @@ -3492,20 +3492,20 @@ resp_val O 7 _110_:8 _110_:9 8.4 8 _110_:9 _110_:10 0.005 9 _110_:6 _110_:8 8.4 -10 _440_/A _110_:2 5.545 -11 _483_/A _110_:1 2.465 -12 _551_/A _110_:3 5.725 -13 _683_/A _110_:7 3.545 -14 _753_/Z _110_:10 5.165 +10 _440_:A _110_:2 5.545 +11 _483_:A _110_:1 2.465 +12 _551_:A _110_:3 5.725 +13 _683_:A _110_:7 3.545 +14 _753_:Z _110_:10 5.165 *END *D_NET _111_ 37.2 *CONN -*I _501_/A I *D XNOR2_X1 -*I _524_/A I *D INV_X1 -*I _636_/A I *D MUX2_X1 -*I _705_/A I *D MUX2_X1 -*I _733_/Z O *D CLKBUF_X1 +*I _501_:A I *D XNOR2_X1 +*I _524_:A I *D INV_X1 +*I _636_:A I *D MUX2_X1 +*I _705_:A I *D MUX2_X1 +*I _733_:Z O *D CLKBUF_X1 *CAP 1 _111_:1 1.05 2 _111_:2 2.1 @@ -3529,19 +3529,19 @@ resp_val O 8 _111_:9 _111_:10 0.005 9 _111_:9 _111_:11 8.4 10 _111_:11 _111_:6 0.005 -11 _501_/A _111_:10 6.545 -12 _524_/A _111_:6 5.045 -13 _636_/A _111_:1 4.205 -14 _705_/A _111_:5 4.345 -15 _733_/Z _111_:4 3.885 +11 _501_:A _111_:10 6.545 +12 _524_:A _111_:6 5.045 +13 _636_:A _111_:1 4.205 +14 _705_:A _111_:5 4.345 +15 _733_:Z _111_:4 3.885 *END *D_NET _112_ 40.65 *CONN -*I _502_/A I *D XNOR2_X1 -*I _522_/A I *D INV_X1 -*I _707_/A I *D MUX2_X1 -*I _731_/Z O *D CLKBUF_X1 +*I _502_:A I *D XNOR2_X1 +*I _522_:A I *D INV_X1 +*I _707_:A I *D MUX2_X1 +*I _731_:Z O *D CLKBUF_X1 *CAP 1 _112_:1 3.035 2 _112_:2 2.1 @@ -3563,19 +3563,19 @@ resp_val O 7 _112_:8 _112_:9 8.4 8 _112_:9 _112_:10 0.005 9 _112_:4 _112_:8 25.2 -10 _502_/A _112_:1 3.745 -11 _522_/A _112_:6 5.725 -12 _707_/A _112_:5 5.365 -13 _731_/Z _112_:10 7.685 +10 _502_:A _112_:1 3.745 +11 _522_:A _112_:6 5.725 +12 _707_:A _112_:5 5.365 +13 _731_:Z _112_:10 7.685 *END *D_NET _113_ 50.47 *CONN -*I _512_/A I *D XNOR2_X1 -*I _534_/A I *D INV_X1 -*I _656_/A I *D MUX2_X1 -*I _709_/A I *D MUX2_X1 -*I _729_/Z O *D CLKBUF_X1 +*I _512_:A I *D XNOR2_X1 +*I _534_:A I *D INV_X1 +*I _656_:A I *D MUX2_X1 +*I _709_:A I *D MUX2_X1 +*I _729_:Z O *D CLKBUF_X1 *CAP 1 _113_:1 5.155 2 _113_:2 2.73 @@ -3599,21 +3599,21 @@ resp_val O 8 _113_:9 _113_:10 8.4 9 _113_:10 _113_:11 0.005 10 _113_:10 _113_:5 8.4 -11 _512_/A _113_:1 3.825 -12 _534_/A _113_:2 2.525 -13 _656_/A _113_:11 6.925 -14 _709_/A _113_:4 7.725 -15 _729_/Z _113_:7 4.365 +11 _512_:A _113_:1 3.825 +12 _534_:A _113_:2 2.525 +13 _656_:A _113_:11 6.925 +14 _709_:A _113_:4 7.725 +15 _729_:Z _113_:7 4.365 *END *D_NET _114_ 60.77 *CONN -*I _510_/A I *D XNOR2_X2 -*I _532_/A I *D INV_X1 -*I _664_/A I *D MUX2_X1 -*I _667_/B1 I *D AOI22_X1 -*I _711_/A I *D MUX2_X1 -*I _727_/Z O *D BUF_X1 +*I _510_:A I *D XNOR2_X2 +*I _532_:A I *D INV_X1 +*I _664_:A I *D MUX2_X1 +*I _667_:B1 I *D AOI22_X1 +*I _711_:A I *D MUX2_X1 +*I _727_:Z O *D BUF_X1 *CAP 1 _114_:1 5.37 2 _114_:2 6.3 @@ -3637,21 +3637,21 @@ resp_val O 8 _114_:8 _114_:9 0.005 9 _114_:10 _114_:11 25.2 10 _114_:4 _114_:10 8.4 -11 _510_/A _114_:10 1.765 -12 _532_/A _114_:11 4.845 -13 _664_/A _114_:5 6.785 -14 _667_/B1 _114_:7 4.105 -15 _711_/A _114_:9 6.985 -16 _727_/Z _114_:1 4.685 +11 _510_:A _114_:10 1.765 +12 _532_:A _114_:11 4.845 +13 _664_:A _114_:5 6.785 +14 _667_:B1 _114_:7 4.105 +15 _711_:A _114_:9 6.985 +16 _727_:Z _114_:1 4.685 *END *D_NET _115_ 43.42 *CONN -*I _507_/A I *D XNOR2_X1 -*I _528_/A I *D INV_X1 -*I _674_/A I *D MUX2_X1 -*I _713_/A I *D MUX2_X1 -*I _725_/Z O *D CLKBUF_X1 +*I _507_:A I *D XNOR2_X1 +*I _528_:A I *D INV_X1 +*I _674_:A I *D MUX2_X1 +*I _713_:A I *D MUX2_X1 +*I _725_:Z O *D CLKBUF_X1 *CAP 1 _115_:1 9.225 2 _115_:2 2.98 @@ -3671,19 +3671,19 @@ resp_val O 6 _115_:8 _115_:1 25.2 7 _115_:6 _115_:9 16.8 8 _115_:9 _115_:8 0.005 -9 _507_/A _115_:1 3.305 -10 _528_/A _115_:2 3.525 -11 _674_/A _115_:3 5.105 -12 _713_/A _115_:7 3.765 -13 _725_/Z _115_:8 3.965 +9 _507_:A _115_:1 3.305 +10 _528_:A _115_:2 3.525 +11 _674_:A _115_:3 5.105 +12 _713_:A _115_:7 3.765 +13 _725_:Z _115_:8 3.965 *END *D_NET _116_ 41.38 *CONN -*I _468_/A I *D INV_X1 -*I _508_/A I *D XNOR2_X2 -*I _715_/A I *D MUX2_X1 -*I _723_/Z O *D CLKBUF_X1 +*I _468_:A I *D INV_X1 +*I _508_:A I *D XNOR2_X2 +*I _715_:A I *D MUX2_X1 +*I _723_:Z O *D CLKBUF_X1 *CAP 1 _116_:1 9.63 2 _116_:2 9.06 @@ -3699,20 +3699,20 @@ resp_val O 4 _116_:5 _116_:6 0.005 5 _116_:2 _116_:7 0.005 6 _116_:7 _116_:4 16.8 -7 _468_/A _116_:3 4.805 -8 _508_/A _116_:1 4.925 -9 _715_/A _116_:2 2.645 -10 _723_/Z _116_:6 3.205 +7 _468_:A _116_:3 4.805 +8 _508_:A _116_:1 4.925 +9 _715_:A _116_:2 2.645 +10 _723_:Z _116_:6 3.205 *END *D_NET _117_ 50.26 *CONN -*I _481_/A2 I *D AND2_X1 -*I _482_/A2 I *D NOR2_X1 -*I _540_/A I *D XNOR2_X2 -*I _560_/A I *D MUX2_X1 -*I _687_/A I *D MUX2_X1 -*I _751_/Z O *D BUF_X1 +*I _481_:A2 I *D AND2_X1 +*I _482_:A2 I *D NOR2_X1 +*I _540_:A I *D XNOR2_X2 +*I _560_:A I *D MUX2_X1 +*I _687_:A I *D MUX2_X1 +*I _751_:Z O *D BUF_X1 *CAP 1 _117_:1 2.1 2 _117_:2 8.4 @@ -3738,22 +3738,22 @@ resp_val O 9 _117_:11 _117_:5 0.005 10 _117_:12 _117_:5 16.8 11 _117_:1 _117_:12 8.4 -12 _481_/A2 _117_:4 4.105 -13 _482_/A2 _117_:4 4.145 -14 _540_/A _117_:12 4.925 -15 _560_/A _117_:6 3.465 -16 _687_/A _117_:7 4.305 -17 _751_/Z _117_:9 4.005 +12 _481_:A2 _117_:4 4.105 +13 _482_:A2 _117_:4 4.145 +14 _540_:A _117_:12 4.925 +15 _560_:A _117_:6 3.465 +16 _687_:A _117_:7 4.305 +17 _751_:Z _117_:9 4.005 *END *D_NET _118_ 71.42 *CONN -*I _474_/A I *D XNOR2_X1 -*I _498_/A I *D AOI211_X1 -*I _566_/A I *D MUX2_X1 -*I _570_/A2 I *D AND2_X1 -*I _689_/A I *D MUX2_X1 -*I _749_/Z O *D CLKBUF_X1 +*I _474_:A I *D XNOR2_X1 +*I _498_:A I *D AOI211_X1 +*I _566_:A I *D MUX2_X1 +*I _570_:A2 I *D AND2_X1 +*I _689_:A I *D MUX2_X1 +*I _749_:Z O *D CLKBUF_X1 *CAP 1 _118_:1 3.055 2 _118_:2 2.1 @@ -3787,23 +3787,23 @@ resp_val O 13 _118_:15 _118_:2 0.005 14 _118_:15 _118_:16 8.4 15 _118_:16 _118_:12 0.005 -16 _474_/A _118_:1 3.825 -17 _498_/A _118_:3 4.505 -18 _566_/A _118_:5 4.805 -19 _570_/A2 _118_:11 7.765 -20 _689_/A _118_:13 4.485 -21 _749_/Z _118_:14 8.285 +16 _474_:A _118_:1 3.825 +17 _498_:A _118_:3 4.505 +18 _566_:A _118_:5 4.805 +19 _570_:A2 _118_:11 7.765 +20 _689_:A _118_:13 4.485 +21 _749_:Z _118_:14 8.285 *END *D_NET _119_ 75.98 *CONN -*I _473_/A I *D XNOR2_X1 -*I _497_/A2 I *D NOR2_X1 -*I _498_/C1 I *D AOI211_X1 -*I _575_/A I *D MUX2_X1 -*I _578_/B1 I *D AOI21_X1 -*I _691_/A I *D MUX2_X1 -*I _747_/Z O *D BUF_X1 +*I _473_:A I *D XNOR2_X1 +*I _497_:A2 I *D NOR2_X1 +*I _498_:C1 I *D AOI211_X1 +*I _575_:A I *D MUX2_X1 +*I _578_:B1 I *D AOI21_X1 +*I _691_:A I *D MUX2_X1 +*I _747_:Z O *D BUF_X1 *CAP 1 _119_:1 10.5 2 _119_:2 5.425 @@ -3839,22 +3839,22 @@ resp_val O 14 _119_:8 _119_:1 25.2 15 _119_:17 _119_:12 8.4 16 _119_:3 _119_:8 8.4 -17 _473_/A _119_:9 7.505 -18 _497_/A2 _119_:4 4.265 -19 _498_/C1 _119_:5 3.085 -20 _575_/A _119_:11 6.705 -21 _578_/B1 _119_:3 3.005 -22 _691_/A _119_:2 4.905 -23 _747_/Z _119_:15 4.925 +17 _473_:A _119_:9 7.505 +18 _497_:A2 _119_:4 4.265 +19 _498_:C1 _119_:5 3.085 +20 _575_:A _119_:11 6.705 +21 _578_:B1 _119_:3 3.005 +22 _691_:A _119_:2 4.905 +23 _747_:Z _119_:15 4.925 *END *D_NET _120_ 57.84 *CONN -*I _477_/A I *D XNOR2_X1 -*I _486_/A I *D INV_X1 -*I _584_/A I *D MUX2_X1 -*I _693_/A I *D MUX2_X1 -*I _745_/Z O *D CLKBUF_X1 +*I _477_:A I *D XNOR2_X1 +*I _486_:A I *D INV_X1 +*I _584_:A I *D MUX2_X1 +*I _693_:A I *D MUX2_X1 +*I _745_:Z O *D CLKBUF_X1 *CAP 1 _120_:1 8.87 2 _120_:2 8.4 @@ -3876,20 +3876,20 @@ resp_val O 7 _120_:8 _120_:9 0.005 8 _120_:8 _120_:10 16.8 9 _120_:10 _120_:2 0.005 -10 _477_/A _120_:3 3.225 -11 _486_/A _120_:9 3.585 -12 _584_/A _120_:4 7.245 -13 _693_/A _120_:5 7.365 -14 _745_/Z _120_:1 10.285 +10 _477_:A _120_:3 3.225 +11 _486_:A _120_:9 3.585 +12 _584_:A _120_:4 7.245 +13 _693_:A _120_:5 7.365 +14 _745_:Z _120_:1 10.285 *END *D_NET _121_ 46.05 *CONN -*I _476_/A I *D XNOR2_X2 -*I _488_/A I *D INV_X1 -*I _592_/A I *D MUX2_X1 -*I _695_/A I *D MUX2_X1 -*I _743_/Z O *D CLKBUF_X1 +*I _476_:A I *D XNOR2_X2 +*I _488_:A I *D INV_X1 +*I _592_:A I *D MUX2_X1 +*I _695_:A I *D MUX2_X1 +*I _743_:Z O *D CLKBUF_X1 *CAP 1 _121_:1 5.32 2 _121_:2 3.535 @@ -3909,20 +3909,20 @@ resp_val O 6 _121_:4 _121_:8 0.005 7 _121_:8 _121_:9 16.8 8 _121_:9 _121_:6 0.005 -9 _476_/A _121_:2 5.745 -10 _488_/A _121_:1 4.485 -11 _592_/A _121_:3 2.265 -12 _695_/A _121_:5 3.105 -13 _743_/Z _121_:7 0.925 +9 _476_:A _121_:2 5.745 +10 _488_:A _121_:1 4.485 +11 _592_:A _121_:3 2.265 +12 _695_:A _121_:5 3.105 +13 _743_:Z _121_:7 0.925 *END *D_NET _122_ 46.36 *CONN -*I _471_/A I *D XNOR2_X1 -*I _494_/A I *D INV_X1 -*I _600_/A I *D MUX2_X1 -*I _697_/A I *D MUX2_X1 -*I _741_/Z O *D CLKBUF_X1 +*I _471_:A I *D XNOR2_X1 +*I _494_:A I *D INV_X1 +*I _600_:A I *D MUX2_X1 +*I _697_:A I *D MUX2_X1 +*I _741_:Z O *D CLKBUF_X1 *CAP 1 _122_:1 2.77 2 _122_:2 2.945 @@ -3942,21 +3942,21 @@ resp_val O 6 _122_:1 _122_:8 0.005 7 _122_:8 _122_:9 25.2 8 _122_:9 _122_:4 0.005 -9 _471_/A _122_:4 4.385 -10 _494_/A _122_:2 3.385 -11 _600_/A _122_:3 5.085 -12 _697_/A _122_:1 2.685 -13 _741_/Z _122_:7 1.605 +9 _471_:A _122_:4 4.385 +10 _494_:A _122_:2 3.385 +11 _600_:A _122_:3 5.085 +12 _697_:A _122_:1 2.685 +13 _741_:Z _122_:7 1.605 *END *D_NET _123_ 53.78 *CONN -*I _470_/A I *D XNOR2_X2 -*I _492_/A2 I *D NOR2_X1 -*I _609_/A I *D MUX2_X1 -*I _613_/B1 I *D AOI221_X1 -*I _699_/A I *D MUX2_X1 -*I _739_/Z O *D BUF_X1 +*I _470_:A I *D XNOR2_X2 +*I _492_:A2 I *D NOR2_X1 +*I _609_:A I *D MUX2_X1 +*I _613_:B1 I *D AOI221_X1 +*I _699_:A I *D MUX2_X1 +*I _739_:Z O *D BUF_X1 *CAP 1 _123_:1 2.1 2 _123_:2 4.2 @@ -3982,21 +3982,21 @@ resp_val O 9 _123_:10 _123_:11 8.4 10 _123_:6 _123_:12 0.005 11 _123_:12 _123_:2 8.4 -12 _470_/A _123_:4 5.125 -13 _492_/A2 _123_:6 1.565 -14 _609_/A _123_:7 2.325 -15 _613_/B1 _123_:5 7.185 -16 _699_/A _123_:10 5.825 -17 _739_/Z _123_:11 1.565 +12 _470_:A _123_:4 5.125 +13 _492_:A2 _123_:6 1.565 +14 _609_:A _123_:7 2.325 +15 _613_:B1 _123_:5 7.185 +16 _699_:A _123_:10 5.825 +17 _739_:Z _123_:11 1.565 *END *D_NET _124_ 37.06 *CONN -*I _505_/A I *D XNOR2_X1 -*I _517_/A I *D INV_X1 -*I _618_/A I *D MUX2_X1 -*I _701_/A I *D MUX2_X1 -*I _737_/Z O *D CLKBUF_X1 +*I _505_:A I *D XNOR2_X1 +*I _517_:A I *D INV_X1 +*I _618_:A I *D MUX2_X1 +*I _701_:A I *D MUX2_X1 +*I _737_:Z O *D CLKBUF_X1 *CAP 1 _124_:1 3.22 2 _124_:2 3.255 @@ -4014,20 +4014,20 @@ resp_val O 5 _124_:6 _124_:7 0.005 6 _124_:6 _124_:8 16.8 7 _124_:8 _124_:2 0.005 -8 _505_/A _124_:2 4.625 -9 _517_/A _124_:1 4.485 -10 _618_/A _124_:7 5.945 -11 _701_/A _124_:4 2.085 -12 _737_/Z _124_:7 6.605 +8 _505_:A _124_:2 4.625 +9 _517_:A _124_:1 4.485 +10 _618_:A _124_:7 5.945 +11 _701_:A _124_:4 2.085 +12 _737_:Z _124_:7 6.605 *END *D_NET _125_ 31.84 *CONN -*I _504_/A I *D XNOR2_X2 -*I _519_/A I *D INV_X1 -*I _627_/A I *D MUX2_X1 -*I _703_/A I *D MUX2_X1 -*I _735_/Z O *D CLKBUF_X1 +*I _504_:A I *D XNOR2_X2 +*I _519_:A I *D INV_X1 +*I _627_:A I *D MUX2_X1 +*I _703_:A I *D MUX2_X1 +*I _735_:Z O *D CLKBUF_X1 *CAP 1 _125_:1 2.825 2 _125_:2 2.1 @@ -4047,21 +4047,21 @@ resp_val O 6 _125_:8 _125_:3 8.4 7 _125_:7 _125_:9 8.4 8 _125_:9 _125_:4 0.005 -9 _504_/A _125_:4 4.965 -10 _519_/A _125_:3 5.145 -11 _627_/A _125_:1 2.905 -12 _703_/A _125_:5 6.405 -13 _735_/Z _125_:8 2.285 +9 _504_:A _125_:4 4.965 +10 _519_:A _125_:3 5.145 +11 _627_:A _125_:1 2.905 +12 _703_:A _125_:5 6.405 +13 _735_:Z _125_:8 2.285 *END *D_NET _126_ 63.27 *CONN -*I _440_/B I *D XOR2_X1 -*I _444_/A2 I *D NOR2_X1 -*I _484_/A3 I *D NOR3_X1 -*I _556_/A2 I *D NAND2_X1 -*I _686_/A I *D MUX2_X1 -*I _754_/Z O *D BUF_X1 +*I _440_:B I *D XOR2_X1 +*I _444_:A2 I *D NOR2_X1 +*I _484_:A3 I *D NOR3_X1 +*I _556_:A2 I *D NAND2_X1 +*I _686_:A I *D MUX2_X1 +*I _754_:Z O *D BUF_X1 *CAP 1 _126_:1 9.61 2 _126_:2 4.275 @@ -4075,22 +4075,22 @@ resp_val O 3 _126_:4 _126_:5 67.2 4 _126_:5 _126_:6 0.005 5 _126_:1 _126_:3 25.2 -6 _440_/B _126_:3 3.545 -7 _444_/A2 _126_:2 6.145 -8 _484_/A3 _126_:2 2.565 -9 _556_/A2 _126_:1 4.845 -10 _686_/A _126_:6 4.305 -11 _754_/Z _126_:6 4.365 +6 _440_:B _126_:3 3.545 +7 _444_:A2 _126_:2 6.145 +8 _484_:A3 _126_:2 2.565 +9 _556_:A2 _126_:1 4.845 +10 _686_:A _126_:6 4.305 +11 _754_:Z _126_:6 4.365 *END *D_NET _127_ 33.99 *CONN -*I _446_/A2 I *D NOR4_X1 -*I _501_/B I *D XNOR2_X1 -*I _525_/B2 I *D AOI22_X1 -*I _640_/A2 I *D NOR2_X1 -*I _706_/A I *D MUX2_X1 -*I _734_/Z O *D BUF_X1 +*I _446_:A2 I *D NOR4_X1 +*I _501_:B I *D XNOR2_X1 +*I _525_:B2 I *D AOI22_X1 +*I _640_:A2 I *D NOR2_X1 +*I _706_:A I *D MUX2_X1 +*I _734_:Z O *D BUF_X1 *CAP 1 _127_:1 2.4 2 _127_:2 2.1 @@ -4110,22 +4110,22 @@ resp_val O 6 _127_:6 _127_:7 8.4 7 _127_:9 _127_:8 8.4 8 _127_:1 _127_:9 8.4 -9 _446_/A2 _127_:8 1.525 -10 _501_/B _127_:9 7.565 -11 _525_/B2 _127_:7 7.105 -12 _640_/A2 _127_:7 2.725 -13 _706_/A _127_:4 5.885 -14 _734_/Z _127_:1 1.205 +9 _446_:A2 _127_:8 1.525 +10 _501_:B _127_:9 7.565 +11 _525_:B2 _127_:7 7.105 +12 _640_:A2 _127_:7 2.725 +13 _706_:A _127_:4 5.885 +14 _734_:Z _127_:1 1.205 *END *D_NET _128_ 55.76 *CONN -*I _446_/A1 I *D NOR4_X1 -*I _502_/B I *D XNOR2_X1 -*I _523_/A2 I *D NOR2_X1 -*I _525_/A2 I *D AOI22_X1 -*I _708_/A I *D MUX2_X1 -*I _732_/Z O *D BUF_X1 +*I _446_:A1 I *D NOR4_X1 +*I _502_:B I *D XNOR2_X1 +*I _523_:A2 I *D NOR2_X1 +*I _525_:A2 I *D AOI22_X1 +*I _708_:A I *D MUX2_X1 +*I _732_:Z O *D BUF_X1 *CAP 1 _128_:1 1.265 2 _128_:2 8.4 @@ -4157,22 +4157,22 @@ resp_val O 12 _128_:13 _128_:14 0.005 13 _128_:14 _128_:15 8.4 14 _128_:3 _128_:7 16.8 -15 _446_/A1 _128_:10 2.585 -16 _502_/B _128_:6 4.765 -17 _523_/A2 _128_:5 2.445 -18 _525_/A2 _128_:1 5.065 -19 _708_/A _128_:9 1.765 -20 _732_/Z _128_:15 2.525 +15 _446_:A1 _128_:10 2.585 +16 _502_:B _128_:6 4.765 +17 _523_:A2 _128_:5 2.445 +18 _525_:A2 _128_:1 5.065 +19 _708_:A _128_:9 1.765 +20 _732_:Z _128_:15 2.525 *END *D_NET _129_ 54.66 *CONN -*I _447_/A4 I *D NOR4_X1 -*I _512_/B I *D XNOR2_X1 -*I _535_/B2 I *D AOI22_X1 -*I _658_/A2 I *D NOR2_X1 -*I _710_/A I *D MUX2_X1 -*I _730_/Z O *D BUF_X1 +*I _447_:A4 I *D NOR4_X1 +*I _512_:B I *D XNOR2_X1 +*I _535_:B2 I *D AOI22_X1 +*I _658_:A2 I *D NOR2_X1 +*I _710_:A I *D MUX2_X1 +*I _730_:Z O *D BUF_X1 *CAP 1 _129_:1 4.2 2 _129_:2 5.94 @@ -4200,22 +4200,22 @@ resp_val O 10 _129_:11 _129_:7 0.005 11 _129_:11 _129_:12 16.8 12 _129_:12 _129_:13 0.005 -13 _447_/A4 _129_:2 6.965 -14 _512_/B _129_:10 5.165 -15 _535_/B2 _129_:5 1.765 -16 _658_/A2 _129_:6 6.145 -17 _710_/A _129_:8 3.945 -18 _730_/Z _129_:13 1.365 +13 _447_:A4 _129_:2 6.965 +14 _512_:B _129_:10 5.165 +15 _535_:B2 _129_:5 1.765 +16 _658_:A2 _129_:6 6.145 +17 _710_:A _129_:8 3.945 +18 _730_:Z _129_:13 1.365 *END *D_NET _130_ 64.74 *CONN -*I _447_/A3 I *D NOR4_X1 -*I _510_/B I *D XNOR2_X2 -*I _533_/A2 I *D NOR2_X1 -*I _535_/A2 I *D AOI22_X1 -*I _712_/A I *D MUX2_X1 -*I _728_/Z O *D CLKBUF_X2 +*I _447_:A3 I *D NOR4_X1 +*I _510_:B I *D XNOR2_X2 +*I _533_:A2 I *D NOR2_X1 +*I _535_:A2 I *D AOI22_X1 +*I _712_:A I *D MUX2_X1 +*I _728_:Z O *D CLKBUF_X2 *CAP 1 _130_:1 4.2 2 _130_:2 6.13 @@ -4243,22 +4243,22 @@ resp_val O 10 _130_:11 _130_:12 0.005 11 _130_:9 _130_:5 33.6 12 _130_:13 _130_:12 8.4 -13 _447_/A3 _130_:2 7.725 -14 _510_/B _130_:9 4.065 -15 _533_/A2 _130_:8 6.305 -16 _535_/A2 _130_:5 4.025 -17 _712_/A _130_:12 1.765 -18 _728_/Z _130_:13 4.825 +13 _447_:A3 _130_:2 7.725 +14 _510_:B _130_:9 4.065 +15 _533_:A2 _130_:8 6.305 +16 _535_:A2 _130_:5 4.025 +17 _712_:A _130_:12 1.765 +18 _728_:Z _130_:13 4.825 *END *D_NET _131_ 54.17 *CONN -*I _447_/A2 I *D NOR4_X1 -*I _507_/B I *D XNOR2_X1 -*I _529_/A3 I *D NAND3_X1 -*I _675_/A2 I *D NOR2_X1 -*I _714_/A I *D MUX2_X1 -*I _726_/Z O *D BUF_X1 +*I _447_:A2 I *D NOR4_X1 +*I _507_:B I *D XNOR2_X1 +*I _529_:A3 I *D NAND3_X1 +*I _675_:A2 I *D NOR2_X1 +*I _714_:A I *D MUX2_X1 +*I _726_:Z O *D BUF_X1 *CAP 1 _131_:1 3.66 2 _131_:2 4.2 @@ -4292,21 +4292,21 @@ resp_val O 13 _131_:10 _131_:15 8.4 14 _131_:15 _131_:16 0.005 15 _131_:16 _131_:12 8.4 -16 _447_/A2 _131_:4 8.325 -17 _507_/B _131_:10 4.645 -18 _529_/A3 _131_:1 6.245 -19 _675_/A2 _131_:11 2.305 -20 _714_/A _131_:5 4.845 -21 _726_/Z _131_:6 6.405 +16 _447_:A2 _131_:4 8.325 +17 _507_:B _131_:10 4.645 +18 _529_:A3 _131_:1 6.245 +19 _675_:A2 _131_:11 2.305 +20 _714_:A _131_:5 4.845 +21 _726_:Z _131_:6 6.405 *END *D_NET _132_ 45.55 *CONN -*I _447_/A1 I *D NOR4_X1 -*I _469_/A2 I *D NAND2_X1 -*I _508_/B I *D XNOR2_X2 -*I _716_/A I *D MUX2_X1 -*I _724_/Z O *D BUF_X1 +*I _447_:A1 I *D NOR4_X1 +*I _469_:A2 I *D NAND2_X1 +*I _508_:B I *D XNOR2_X2 +*I _716_:A I *D MUX2_X1 +*I _724_:Z O *D BUF_X1 *CAP 1 _132_:1 6.205 2 _132_:2 3.855 @@ -4328,20 +4328,20 @@ resp_val O 7 _132_:9 _132_:10 0.005 8 _132_:10 _132_:6 8.4 9 _132_:5 _132_:3 16.8 -10 _447_/A1 _132_:2 7.025 -11 _469_/A2 _132_:4 7.665 -12 _508_/B _132_:1 8.025 -13 _716_/A _132_:3 7.605 -14 _724_/Z _132_:8 2.005 +10 _447_:A1 _132_:2 7.025 +11 _469_:A2 _132_:4 7.665 +12 _508_:B _132_:1 8.025 +13 _716_:A _132_:3 7.605 +14 _724_:Z _132_:8 2.005 *END *D_NET _133_ 43.51 *CONN -*I _444_/A1 I *D NOR2_X1 -*I _480_/A I *D INV_X1 -*I _540_/B I *D XNOR2_X2 -*I _688_/A I *D MUX2_X1 -*I _752_/Z O *D BUF_X1 +*I _444_:A1 I *D NOR2_X1 +*I _480_:A I *D INV_X1 +*I _540_:B I *D XNOR2_X2 +*I _688_:A I *D MUX2_X1 +*I _752_:Z O *D BUF_X1 *CAP 1 _133_:1 2.005 2 _133_:2 6.3 @@ -4363,19 +4363,19 @@ resp_val O 7 _133_:9 _133_:8 8.4 8 _133_:9 _133_:10 0.005 9 _133_:10 _133_:7 8.4 -10 _444_/A1 _133_:4 7.445 -11 _480_/A _133_:5 6.005 -12 _540_/B _133_:1 8.025 -13 _688_/A _133_:9 5.445 -14 _752_/Z _133_:8 9.725 +10 _444_:A1 _133_:4 7.445 +11 _480_:A _133_:5 6.005 +12 _540_:B _133_:1 8.025 +13 _688_:A _133_:9 5.445 +14 _752_:Z _133_:8 9.725 *END *D_NET _134_ 30.02 *CONN -*I _443_/A I *D INV_X1 -*I _474_/B I *D XNOR2_X1 -*I _690_/A I *D MUX2_X1 -*I _750_/Z O *D CLKBUF_X1 +*I _443_:A I *D INV_X1 +*I _474_:B I *D XNOR2_X1 +*I _690_:A I *D MUX2_X1 +*I _750_:Z O *D CLKBUF_X1 *CAP 1 _134_:1 5.445 2 _134_:2 6.3 @@ -4391,18 +4391,18 @@ resp_val O 4 _134_:5 _134_:2 0.005 5 _134_:6 _134_:3 8.4 6 _134_:2 _134_:7 8.4 -7 _443_/A _134_:1 4.985 -8 _474_/B _134_:6 4.845 -9 _690_/A _134_:7 6.385 -10 _750_/Z _134_:3 1.845 +7 _443_:A _134_:1 4.985 +8 _474_:B _134_:6 4.845 +9 _690_:A _134_:7 6.385 +10 _750_:Z _134_:3 1.845 *END *D_NET _135_ 36.86 *CONN -*I _442_/A I *D INV_X1 -*I _473_/B I *D XNOR2_X1 -*I _692_/A I *D MUX2_X1 -*I _748_/Z O *D CLKBUF_X1 +*I _442_:A I *D INV_X1 +*I _473_:B I *D XNOR2_X1 +*I _692_:A I *D MUX2_X1 +*I _748_:Z O *D CLKBUF_X1 *CAP 1 _135_:1 4.2 2 _135_:2 4.2 @@ -4422,20 +4422,20 @@ resp_val O 6 _135_:6 _135_:8 0.005 7 _135_:8 _135_:2 8.4 8 _135_:1 _135_:9 8.4 -9 _442_/A _135_:4 7.845 -10 _473_/B _135_:5 6.285 -11 _692_/A _135_:7 3.925 -12 _748_/Z _135_:9 5.285 +9 _442_:A _135_:4 7.845 +10 _473_:B _135_:5 6.285 +11 _692_:A _135_:7 3.925 +12 _748_:Z _135_:9 5.285 *END *D_NET _136_ 59.01 *CONN -*I _441_/A4 I *D NOR4_X1 -*I _477_/B I *D XNOR2_X1 -*I _487_/A3 I *D AND3_X1 -*I _587_/A2 I *D NOR2_X1 -*I _694_/A I *D MUX2_X1 -*I _746_/Z O *D CLKBUF_X1 +*I _441_:A4 I *D NOR4_X1 +*I _477_:B I *D XNOR2_X1 +*I _487_:A3 I *D AND3_X1 +*I _587_:A2 I *D NOR2_X1 +*I _694_:A I *D MUX2_X1 +*I _746_:Z O *D CLKBUF_X1 *CAP 1 _136_:1 2.195 2 _136_:2 4.2 @@ -4467,22 +4467,22 @@ resp_val O 12 _136_:13 _136_:14 8.4 13 _136_:14 _136_:15 0.005 14 _136_:11 _136_:2 8.4 -15 _441_/A4 _136_:8 6.625 -16 _477_/B _136_:6 4.045 -17 _487_/A3 _136_:1 3.025 -18 _587_/A2 _136_:1 5.765 -19 _694_/A _136_:5 2.785 -20 _746_/Z _136_:15 3.405 +15 _441_:A4 _136_:8 6.625 +16 _477_:B _136_:6 4.045 +17 _487_:A3 _136_:1 3.025 +18 _587_:A2 _136_:1 5.765 +19 _694_:A _136_:5 2.785 +20 _746_:Z _136_:15 3.405 *END *D_NET _137_ 51.73 *CONN -*I _441_/A3 I *D NOR4_X1 -*I _476_/B I *D XNOR2_X2 -*I _489_/A2 I *D AND2_X1 -*I _595_/B2 I *D OAI21_X1 -*I _696_/A I *D MUX2_X1 -*I _744_/Z O *D BUF_X1 +*I _441_:A3 I *D NOR4_X1 +*I _476_:B I *D XNOR2_X2 +*I _489_:A2 I *D AND2_X1 +*I _595_:B2 I *D OAI21_X1 +*I _696_:A I *D MUX2_X1 +*I _744_:Z O *D BUF_X1 *CAP 1 _137_:1 1.845 2 _137_:2 4.2 @@ -4508,23 +4508,23 @@ resp_val O 9 _137_:10 _137_:11 0.005 10 _137_:11 _137_:12 16.8 11 _137_:3 _137_:6 8.4 -12 _441_/A3 _137_:1 7.385 -13 _476_/B _137_:9 4.985 -14 _489_/A2 _137_:4 7.305 -15 _595_/B2 _137_:4 5.205 -16 _696_/A _137_:8 4.365 -17 _744_/Z _137_:12 7.045 +12 _441_:A3 _137_:1 7.385 +13 _476_:B _137_:9 4.985 +14 _489_:A2 _137_:4 7.305 +15 _595_:B2 _137_:4 5.205 +16 _696_:A _137_:8 4.365 +17 _744_:Z _137_:12 7.045 *END *D_NET _138_ 68.81 *CONN -*I _441_/A2 I *D NOR4_X1 -*I _471_/B I *D XNOR2_X1 -*I _495_/A3 I *D NAND3_X1 -*I _602_/A2 I *D AND2_X1 -*I _603_/A2 I *D NOR2_X1 -*I _698_/A I *D MUX2_X1 -*I _742_/Z O *D BUF_X1 +*I _441_:A2 I *D NOR4_X1 +*I _471_:B I *D XNOR2_X1 +*I _495_:A3 I *D NAND3_X1 +*I _602_:A2 I *D AND2_X1 +*I _603_:A2 I *D NOR2_X1 +*I _698_:A I *D MUX2_X1 +*I _742_:Z O *D BUF_X1 *CAP 1 _138_:1 6.3 2 _138_:2 8.4 @@ -4550,22 +4550,22 @@ resp_val O 9 _138_:11 _138_:12 0.005 10 _138_:12 _138_:2 16.8 11 _138_:9 _138_:11 8.4 -12 _441_/A2 _138_:4 7.265 -13 _471_/B _138_:5 2.045 -14 _495_/A3 _138_:11 2.725 -15 _602_/A2 _138_:9 6.685 -16 _603_/A2 _138_:6 3.985 -17 _698_/A _138_:10 7.865 -18 _742_/Z _138_:5 6.285 +12 _441_:A2 _138_:4 7.265 +13 _471_:B _138_:5 2.045 +14 _495_:A3 _138_:11 2.725 +15 _602_:A2 _138_:9 6.685 +16 _603_:A2 _138_:6 3.985 +17 _698_:A _138_:10 7.865 +18 _742_:Z _138_:5 6.285 *END *D_NET _139_ 45.46 *CONN -*I _441_/A1 I *D NOR4_X1 -*I _470_/B I *D XNOR2_X2 -*I _491_/A I *D INV_X1 -*I _700_/A I *D MUX2_X1 -*I _740_/Z O *D BUF_X1 +*I _441_:A1 I *D NOR4_X1 +*I _470_:B I *D XNOR2_X2 +*I _491_:A I *D INV_X1 +*I _700_:A I *D MUX2_X1 +*I _740_:Z O *D BUF_X1 *CAP 1 _139_:1 5.69 2 _139_:2 8.4 @@ -4589,21 +4589,21 @@ resp_val O 8 _139_:9 _139_:10 8.4 9 _139_:10 _139_:11 0.005 10 _139_:7 _139_:9 8.4 -11 _441_/A1 _139_:1 5.965 -12 _470_/B _139_:3 7.425 -13 _491_/A _139_:5 4.505 -14 _700_/A _139_:8 1.445 -15 _740_/Z _139_:11 4.405 +11 _441_:A1 _139_:1 5.965 +12 _470_:B _139_:3 7.425 +13 _491_:A _139_:5 4.505 +14 _700_:A _139_:8 1.445 +15 _740_:Z _139_:11 4.405 *END *D_NET _140_ 70.3 *CONN -*I _446_/A4 I *D NOR4_X1 -*I _505_/B I *D XNOR2_X1 -*I _518_/A3 I *D AND3_X1 -*I _622_/A2 I *D NOR2_X1 -*I _702_/A I *D MUX2_X1 -*I _738_/Z O *D CLKBUF_X1 +*I _446_:A4 I *D NOR4_X1 +*I _505_:B I *D XNOR2_X1 +*I _518_:A3 I *D AND3_X1 +*I _622_:A2 I *D NOR2_X1 +*I _702_:A I *D MUX2_X1 +*I _738_:Z O *D CLKBUF_X1 *CAP 1 _140_:1 7.24 2 _140_:2 4.2 @@ -4631,22 +4631,22 @@ resp_val O 10 _140_:11 _140_:12 25.2 11 _140_:12 _140_:13 0.005 12 _140_:6 _140_:13 16.8 -13 _446_/A4 _140_:5 3.045 -14 _505_/B _140_:13 3.485 -15 _518_/A3 _140_:1 3.765 -16 _622_/A2 _140_:6 5.745 -17 _702_/A _140_:9 3.825 -18 _738_/Z _140_:8 3.165 +13 _446_:A4 _140_:5 3.045 +14 _505_:B _140_:13 3.485 +15 _518_:A3 _140_:1 3.765 +16 _622_:A2 _140_:6 5.745 +17 _702_:A _140_:9 3.825 +18 _738_:Z _140_:8 3.165 *END *D_NET _141_ 50.26 *CONN -*I _446_/A3 I *D NOR4_X1 -*I _504_/B I *D XNOR2_X2 -*I _520_/A2 I *D AND2_X1 -*I _629_/A2 I *D NOR2_X1 -*I _704_/A I *D MUX2_X1 -*I _736_/Z O *D BUF_X1 +*I _446_:A3 I *D NOR4_X1 +*I _504_:B I *D XNOR2_X2 +*I _520_:A2 I *D AND2_X1 +*I _629_:A2 I *D NOR2_X1 +*I _704_:A I *D MUX2_X1 +*I _736_:Z O *D BUF_X1 *CAP 1 _141_:1 1.45 2 _141_:2 4.2 @@ -4678,25 +4678,25 @@ resp_val O 12 _141_:13 _141_:14 8.4 13 _141_:14 _141_:15 0.005 14 _141_:14 _141_:8 8.4 -15 _446_/A3 _141_:5 2.285 -16 _504_/B _141_:15 5.185 -17 _520_/A2 _141_:1 5.805 -18 _629_/A2 _141_:6 4.345 -19 _704_/A _141_:10 2.885 -20 _736_/Z _141_:11 4.445 +15 _446_:A3 _141_:5 2.285 +16 _504_:B _141_:15 5.185 +17 _520_:A2 _141_:1 5.805 +18 _629_:A2 _141_:6 4.345 +19 _704_:A _141_:10 2.885 +20 _736_:Z _141_:11 4.445 *END *D_NET _142_ 145.6 *CONN -*I _438_/ZN O *D INV_X2 -*I _439_/A1 I *D AND3_X1 -*I _466_/A I *D BUF_X2 -*I _610_/B1 I *D OAI21_X1 -*I _619_/B1 I *D OAI21_X1 -*I _628_/B1 I *D OAI21_X1 -*I _654_/B1 I *D OAI21_X1 -*I _662_/B1 I *D OAI21_X1 -*I _672_/B1 I *D OAI21_X1 +*I _438_:ZN O *D INV_X2 +*I _439_:A1 I *D AND3_X1 +*I _466_:A I *D BUF_X2 +*I _610_:B1 I *D OAI21_X1 +*I _619_:B1 I *D OAI21_X1 +*I _628_:B1 I *D OAI21_X1 +*I _654_:B1 I *D OAI21_X1 +*I _662_:B1 I *D OAI21_X1 +*I _672_:B1 I *D OAI21_X1 *CAP 1 _142_:1 12.6 2 _142_:2 3.385 @@ -4728,21 +4728,21 @@ resp_val O 12 _142_:13 _142_:14 42 13 _142_:14 _142_:15 0.005 14 _142_:8 _142_:15 16.8 -15 _438_/ZN _142_:3 0.965 -16 _439_/A1 _142_:2 5.145 -17 _466_/A _142_:6 3.925 -18 _610_/B1 _142_:7 5.345 -19 _619_/B1 _142_:11 5.245 -20 _628_/B1 _142_:12 5.565 -21 _654_/B1 _142_:8 5.565 -22 _662_/B1 _142_:9 3.265 -23 _672_/B1 _142_:12 4.225 +15 _438_:ZN _142_:3 0.965 +16 _439_:A1 _142_:2 5.145 +17 _466_:A _142_:6 3.925 +18 _610_:B1 _142_:7 5.345 +19 _619_:B1 _142_:11 5.245 +20 _628_:B1 _142_:12 5.565 +21 _654_:B1 _142_:8 5.565 +22 _662_:B1 _142_:9 3.265 +23 _672_:B1 _142_:12 4.225 *END *D_NET _143_ 46.72 *CONN -*I _441_/ZN O *D NOR4_X1 -*I _445_/A1 I *D NAND4_X1 +*I _441_:ZN O *D NOR4_X1 +*I _445_:A1 I *D NAND4_X1 *CAP 1 _143_:1 0.715 2 _143_:2 12.6 @@ -4754,17 +4754,17 @@ resp_val O 2 _143_:2 _143_:3 50.4 3 _143_:3 _143_:4 0.005 4 _143_:5 _143_:4 33.6 -5 _441_/ZN _143_:5 6.585 -6 _445_/A1 _143_:1 2.865 +5 _441_:ZN _143_:5 6.585 +6 _445_:A1 _143_:1 2.865 *END *D_NET _144_ 43.42 *CONN -*I _442_/ZN O *D INV_X1 -*I _445_/A2 I *D NAND4_X1 -*I _497_/A1 I *D NOR2_X1 -*I _498_/C2 I *D AOI211_X1 -*I _578_/B2 I *D AOI21_X1 +*I _442_:ZN O *D INV_X1 +*I _445_:A2 I *D NAND4_X1 +*I _497_:A1 I *D NOR2_X1 +*I _498_:C2 I *D AOI211_X1 +*I _578_:B2 I *D AOI21_X1 *CAP 1 _144_:1 2.84 2 _144_:2 2.51 @@ -4784,19 +4784,19 @@ resp_val O 6 _144_:6 _144_:7 0.005 7 _144_:7 _144_:8 25.2 8 _144_:3 _144_:9 8.4 -9 _442_/ZN _144_:8 9.365 -10 _445_/A2 _144_:3 4.005 -11 _497_/A1 _144_:1 2.965 -12 _498_/C2 _144_:9 1.685 -13 _578_/B2 _144_:2 1.645 +9 _442_:ZN _144_:8 9.365 +10 _445_:A2 _144_:3 4.005 +11 _497_:A1 _144_:1 2.965 +12 _498_:C2 _144_:9 1.685 +13 _578_:B2 _144_:2 1.645 *END *D_NET _145_ 27.51 *CONN -*I _443_/ZN O *D INV_X1 -*I _445_/A3 I *D NAND4_X1 -*I _498_/B I *D AOI211_X1 -*I _570_/A1 I *D AND2_X1 +*I _443_:ZN O *D INV_X1 +*I _445_:A3 I *D NAND4_X1 +*I _498_:B I *D AOI211_X1 +*I _570_:A1 I *D AND2_X1 *CAP 1 _145_:1 7.235 2 _145_:2 3.29 @@ -4810,16 +4810,16 @@ resp_val O 3 _145_:4 _145_:5 8.4 4 _145_:5 _145_:6 0.005 5 _145_:1 _145_:3 16.8 -6 _443_/ZN _145_:3 4.405 -7 _445_/A3 _145_:2 4.765 -8 _498_/B _145_:1 3.745 -9 _570_/A1 _145_:6 8.525 +6 _443_:ZN _145_:3 4.405 +7 _445_:A3 _145_:2 4.765 +8 _498_:B _145_:1 3.745 +9 _570_:A1 _145_:6 8.525 *END *D_NET _146_ 16.86 *CONN -*I _444_/ZN O *D NOR2_X1 -*I _445_/A4 I *D NAND4_X1 +*I _444_:ZN O *D NOR2_X1 +*I _445_:A4 I *D NAND4_X1 *CAP 1 _146_:1 2.85 2 _146_:2 2.1 @@ -4831,15 +4831,15 @@ resp_val O 2 _146_:2 _146_:3 8.4 3 _146_:3 _146_:4 0.005 4 _146_:5 _146_:4 8.4 -5 _444_/ZN _146_:1 11.405 -6 _445_/A4 _146_:5 5.525 +5 _444_:ZN _146_:1 11.405 +6 _445_:A4 _146_:5 5.525 *END *D_NET _147_ 47.6 *CONN -*I _445_/ZN O *D NAND4_X1 -*I _449_/A1 I *D NOR2_X1 -*I _456_/C1 I *D OAI211_X1 +*I _445_:ZN O *D NAND4_X1 +*I _449_:A1 I *D NOR2_X1 +*I _456_:C1 I *D OAI211_X1 *CAP 1 _147_:1 1.565 2 _147_:2 2.1 @@ -4853,15 +4853,15 @@ resp_val O 3 _147_:3 _147_:4 0.005 4 _147_:3 _147_:5 67.2 5 _147_:5 _147_:6 0.005 -6 _445_/ZN _147_:6 7.185 -7 _449_/A1 _147_:4 6.165 -8 _456_/C1 _147_:1 6.265 +6 _445_:ZN _147_:6 7.185 +7 _449_:A1 _147_:4 6.165 +8 _456_:C1 _147_:1 6.265 *END *D_NET _148_ 12.44 *CONN -*I _446_/ZN O *D NOR4_X1 -*I _448_/A1 I *D NAND2_X1 +*I _446_:ZN O *D NOR4_X1 +*I _448_:A1 I *D NAND2_X1 *CAP 1 _148_:1 0.86 2 _148_:2 2.1 @@ -4873,14 +4873,14 @@ resp_val O 2 _148_:2 _148_:3 8.4 3 _148_:3 _148_:4 0.005 4 _148_:5 _148_:4 8.4 -5 _446_/ZN _148_:1 3.445 -6 _448_/A1 _148_:5 4.645 +5 _446_:ZN _148_:1 3.445 +6 _448_:A1 _148_:5 4.645 *END *D_NET _149_ 27.99 *CONN -*I _447_/ZN O *D NOR4_X1 -*I _448_/A2 I *D NAND2_X1 +*I _447_:ZN O *D NOR4_X1 +*I _448_:A2 I *D NAND2_X1 *CAP 1 _149_:1 3.585 2 _149_:2 2.1 @@ -4892,15 +4892,15 @@ resp_val O 2 _149_:2 _149_:3 0.005 3 _149_:3 _149_:4 33.6 4 _149_:4 _149_:5 0.005 -5 _447_/ZN _149_:5 8.045 -6 _448_/A2 _149_:1 5.945 +5 _447_:ZN _149_:5 8.045 +6 _448_:A2 _149_:1 5.945 *END *D_NET _150_ 61.73 *CONN -*I _448_/ZN O *D NAND2_X1 -*I _449_/A2 I *D NOR2_X1 -*I _456_/C2 I *D OAI211_X1 +*I _448_:ZN O *D NAND2_X1 +*I _449_:A2 I *D NOR2_X1 +*I _456_:C2 I *D OAI211_X1 *CAP 1 _150_:1 1.225 2 _150_:2 2.1 @@ -4912,15 +4912,15 @@ resp_val O 2 _150_:2 _150_:3 8.4 3 _150_:3 _150_:4 0.005 4 _150_:5 _150_:4 100.8 -5 _448_/ZN _150_:5 4.505 -6 _449_/A2 _150_:4 4.865 -7 _456_/C2 _150_:1 4.905 +5 _448_:ZN _150_:5 4.505 +6 _449_:A2 _150_:4 4.865 +7 _456_:C2 _150_:1 4.905 *END *D_NET _151_ 20.47 *CONN -*I _449_/ZN O *D NOR2_X1 -*I _452_/A1 I *D NAND3_X1 +*I _449_:ZN O *D NOR2_X1 +*I _452_:A1 I *D NAND3_X1 *CAP 1 _151_:1 1.805 2 _151_:2 4.2 @@ -4932,17 +4932,17 @@ resp_val O 2 _151_:2 _151_:3 16.8 3 _151_:3 _151_:4 0.005 4 _151_:4 _151_:5 8.4 -5 _449_/ZN _151_:5 8.525 -6 _452_/A1 _151_:1 7.225 +5 _449_:ZN _151_:5 8.525 +6 _452_:A1 _151_:1 7.225 *END *D_NET _152_ 33.71 *CONN -*I _450_/ZN O *D INV_X1 -*I _452_/A2 I *D NAND3_X1 -*I _456_/A I *D OAI211_X1 -*I _460_/A1 I *D NAND4_X1 -*I _462_/A2 I *D NAND3_X1 +*I _450_:ZN O *D INV_X1 +*I _452_:A2 I *D NAND3_X1 +*I _456_:A I *D OAI211_X1 +*I _460_:A1 I *D NAND4_X1 +*I _462_:A2 I *D NAND3_X1 *CAP 1 _152_:1 1.74 2 _152_:2 4.2 @@ -4964,18 +4964,18 @@ resp_val O 7 _152_:8 _152_:9 0.005 8 _152_:8 _152_:2 8.4 9 _152_:10 _152_:6 8.4 -10 _450_/ZN _152_:10 2.965 -11 _452_/A2 _152_:9 6.465 -12 _456_/A _152_:1 6.965 -13 _460_/A1 _152_:5 4.065 -14 _462_/A2 _152_:6 4.985 +10 _450_:ZN _152_:10 2.965 +11 _452_:A2 _152_:9 6.465 +12 _456_:A _152_:1 6.965 +13 _460_:A1 _152_:5 4.065 +14 _462_:A2 _152_:6 4.985 *END *D_NET _153_ 17.1 *CONN -*I _451_/ZN O *D INV_X1 -*I _452_/A3 I *D NAND3_X1 -*I _456_/B I *D OAI211_X1 +*I _451_:ZN O *D INV_X1 +*I _452_:A3 I *D NAND3_X1 +*I _456_:B I *D OAI211_X1 *CAP 1 _153_:1 1.425 2 _153_:2 4.2 @@ -4985,15 +4985,15 @@ resp_val O 1 _153_:1 _153_:2 0.005 2 _153_:2 _153_:3 16.8 3 _153_:3 _153_:4 0.005 -4 _451_/ZN _153_:4 4.125 -5 _452_/A3 _153_:1 5.705 -6 _456_/B _153_:4 7.585 +4 _451_:ZN _153_:4 4.125 +5 _452_:A3 _153_:1 5.705 +6 _456_:B _153_:4 7.585 *END *D_NET _154_ 13.08 *CONN -*I _452_/ZN O *D NAND3_X1 -*I _455_/A1 I *D NAND2_X1 +*I _452_:ZN O *D NAND3_X1 +*I _455_:A1 I *D NAND2_X1 *CAP 1 _154_:1 2.765 2 _154_:2 2.1 @@ -5005,27 +5005,27 @@ resp_val O 2 _154_:2 _154_:3 0.005 3 _154_:3 _154_:4 8.4 4 _154_:4 _154_:5 0.005 -5 _452_/ZN _154_:5 6.705 -6 _455_/A1 _154_:1 2.665 +5 _452_:ZN _154_:5 6.705 +6 _455_:A1 _154_:1 2.665 *END *D_NET _155_ 8.59 *CONN -*I _453_/ZN O *D AND2_X1 -*I _454_/A1 I *D OR3_X1 +*I _453_:ZN O *D AND2_X1 +*I _454_:A1 I *D OR3_X1 *CAP 1 _155_:1 3.23 2 _155_:2 3.165 *RES 1 _155_:2 _155_:1 8.4 -2 _453_/ZN _155_:1 4.525 -3 _454_/A1 _155_:2 4.265 +2 _453_:ZN _155_:1 4.525 +3 _454_:A1 _155_:2 4.265 *END *D_NET _156_ 7.78 *CONN -*I _454_/ZN O *D OR3_X1 -*I _455_/A2 I *D NAND2_X1 +*I _454_:ZN O *D OR3_X1 +*I _455_:A2 I *D NAND2_X1 *CAP 1 _156_:1 1.43 2 _156_:2 2.1 @@ -5035,35 +5035,35 @@ resp_val O 1 _156_:1 _156_:2 0.005 2 _156_:2 _156_:3 8.4 3 _156_:3 _156_:4 0.005 -4 _454_/ZN _156_:1 5.725 -5 _455_/A2 _156_:4 1.445 +4 _454_:ZN _156_:1 5.725 +5 _455_:A2 _156_:4 1.445 *END *D_NET _157_ 10.26 *CONN -*I _456_/ZN O *D OAI211_X1 -*I _461_/A1 I *D NAND2_X1 +*I _456_:ZN O *D OAI211_X1 +*I _461_:A1 I *D NAND2_X1 *CAP 1 _157_:1 4.105 2 _157_:2 3.125 *RES 1 _157_:2 _157_:1 8.4 -2 _456_/ZN _157_:1 8.025 -3 _461_/A1 _157_:2 4.105 +2 _456_:ZN _157_:1 8.025 +3 _461_:A1 _157_:2 4.105 *END *D_NET _158_ 161.71 *CONN -*I _457_/ZN O *D INV_X2 -*I _458_/A I *D BUF_X2 -*I _545_/A2 I *D OR2_X2 -*I _601_/B2 I *D OAI21_X1 -*I _610_/B2 I *D OAI21_X1 -*I _619_/B2 I *D OAI21_X1 -*I _628_/B2 I *D OAI21_X1 -*I _654_/B2 I *D OAI21_X1 -*I _662_/B2 I *D OAI21_X1 -*I _672_/B2 I *D OAI21_X1 +*I _457_:ZN O *D INV_X2 +*I _458_:A I *D BUF_X2 +*I _545_:A2 I *D OR2_X2 +*I _601_:B2 I *D OAI21_X1 +*I _610_:B2 I *D OAI21_X1 +*I _619_:B2 I *D OAI21_X1 +*I _628_:B2 I *D OAI21_X1 +*I _654_:B2 I *D OAI21_X1 +*I _662_:B2 I *D OAI21_X1 +*I _672_:B2 I *D OAI21_X1 *CAP 1 _158_:1 4.2 2 _158_:2 6.36 @@ -5111,31 +5111,31 @@ resp_val O 20 _158_:22 _158_:21 16.8 21 _158_:22 _158_:23 0.005 22 _158_:23 _158_:9 33.6 -23 _457_/ZN _158_:2 8.645 -24 _458_/A _158_:3 5.345 -25 _545_/A2 _158_:13 7.805 -26 _601_/B2 _158_:7 4.785 -27 _610_/B2 _158_:14 6.645 -28 _619_/B2 _158_:18 6.545 -29 _628_/B2 _158_:21 4.265 -30 _654_/B2 _158_:8 5.745 -31 _662_/B2 _158_:12 1.965 -32 _672_/B2 _158_:21 2.925 +23 _457_:ZN _158_:2 8.645 +24 _458_:A _158_:3 5.345 +25 _545_:A2 _158_:13 7.805 +26 _601_:B2 _158_:7 4.785 +27 _610_:B2 _158_:14 6.645 +28 _619_:B2 _158_:18 6.545 +29 _628_:B2 _158_:21 4.265 +30 _654_:B2 _158_:8 5.745 +31 _662_:B2 _158_:12 1.965 +32 _672_:B2 _158_:21 2.925 *END *D_NET _159_ 223.95 *CONN -*I _458_/Z O *D BUF_X2 -*I _460_/A2 I *D NAND4_X1 -*I _467_/B2 I *D OAI21_X1 -*I _552_/B2 I *D OAI21_X1 -*I _561_/B2 I *D OAI21_X1 -*I _567_/B2 I *D OAI21_X1 -*I _576_/B2 I *D OAI21_X1 -*I _585_/B2 I *D OAI21_X1 -*I _593_/B2 I *D OAI21_X1 -*I _637_/B2 I *D OAI21_X1 -*I _679_/B2 I *D OAI21_X1 +*I _458_:Z O *D BUF_X2 +*I _460_:A2 I *D NAND4_X1 +*I _467_:B2 I *D OAI21_X1 +*I _552_:B2 I *D OAI21_X1 +*I _561_:B2 I *D OAI21_X1 +*I _567_:B2 I *D OAI21_X1 +*I _576_:B2 I *D OAI21_X1 +*I _585_:B2 I *D OAI21_X1 +*I _593_:B2 I *D OAI21_X1 +*I _637_:B2 I *D OAI21_X1 +*I _679_:B2 I *D OAI21_X1 *CAP 1 _159_:1 1.305 2 _159_:2 2.1 @@ -5199,32 +5199,32 @@ resp_val O 28 _159_:25 _159_:30 33.6 29 _159_:22 _159_:31 0.005 30 _159_:31 _159_:24 50.4 -31 _458_/Z _159_:1 5.225 -32 _460_/A2 _159_:5 5.525 -33 _467_/B2 _159_:9 2.165 -34 _552_/B2 _159_:21 4.805 -35 _561_/B2 _159_:22 5.545 -36 _567_/B2 _159_:16 5.705 -37 _576_/B2 _159_:15 5.685 -38 _585_/B2 _159_:13 7.345 -39 _593_/B2 _159_:14 4.345 -40 _637_/B2 _159_:25 2.645 -41 _679_/B2 _159_:23 4.165 +31 _458_:Z _159_:1 5.225 +32 _460_:A2 _159_:5 5.525 +33 _467_:B2 _159_:9 2.165 +34 _552_:B2 _159_:21 4.805 +35 _561_:B2 _159_:22 5.545 +36 _567_:B2 _159_:16 5.705 +37 _576_:B2 _159_:15 5.685 +38 _585_:B2 _159_:13 7.345 +39 _593_:B2 _159_:14 4.345 +40 _637_:B2 _159_:25 2.645 +41 _679_:B2 _159_:23 4.165 *END *D_NET _160_ 262.05 *CONN -*I _459_/Z O *D BUF_X2 -*I _460_/A3 I *D NAND4_X1 -*I _464_/C1 I *D AOI211_X1 -*I _683_/S I *D MUX2_X1 -*I _687_/S I *D MUX2_X1 -*I _689_/S I *D MUX2_X1 -*I _691_/S I *D MUX2_X1 -*I _693_/S I *D MUX2_X1 -*I _695_/S I *D MUX2_X1 -*I _697_/S I *D MUX2_X1 -*I _699_/S I *D MUX2_X1 +*I _459_:Z O *D BUF_X2 +*I _460_:A3 I *D NAND4_X1 +*I _464_:C1 I *D AOI211_X1 +*I _683_:S I *D MUX2_X1 +*I _687_:S I *D MUX2_X1 +*I _689_:S I *D MUX2_X1 +*I _691_:S I *D MUX2_X1 +*I _693_:S I *D MUX2_X1 +*I _695_:S I *D MUX2_X1 +*I _697_:S I *D MUX2_X1 +*I _699_:S I *D MUX2_X1 *CAP 1 _160_:1 1.31 2 _160_:2 4.2 @@ -5280,23 +5280,23 @@ resp_val O 24 _160_:23 _160_:18 92.4 25 _160_:27 _160_:27 0.005 26 _160_:27 _160_:9 42 -27 _459_/Z _160_:19 10.585 -28 _460_/A3 _160_:1 5.245 -29 _464_/C1 _160_:6 7.085 -30 _683_/S _160_:13 4.305 -31 _687_/S _160_:5 3.545 -32 _689_/S _160_:14 5.225 -33 _691_/S _160_:18 5.665 -34 _693_/S _160_:22 8.665 -35 _695_/S _160_:22 3.865 -36 _697_/S _160_:24 2.905 -37 _699_/S _160_:9 5.065 +27 _459_:Z _160_:19 10.585 +28 _460_:A3 _160_:1 5.245 +29 _464_:C1 _160_:6 7.085 +30 _683_:S _160_:13 4.305 +31 _687_:S _160_:5 3.545 +32 _689_:S _160_:14 5.225 +33 _691_:S _160_:18 5.665 +34 _693_:S _160_:22 8.665 +35 _695_:S _160_:22 3.865 +36 _697_:S _160_:24 2.905 +37 _699_:S _160_:9 5.065 *END *D_NET _161_ 12.59 *CONN -*I _460_/ZN O *D NAND4_X1 -*I _461_/A2 I *D NAND2_X1 +*I _460_:ZN O *D NAND4_X1 +*I _461_:A2 I *D NAND2_X1 *CAP 1 _161_:1 2.8 2 _161_:2 2.1 @@ -5308,14 +5308,14 @@ resp_val O 2 _161_:2 _161_:3 0.005 3 _161_:3 _161_:4 8.4 4 _161_:4 _161_:5 0.005 -5 _460_/ZN _161_:5 5.585 -6 _461_/A2 _161_:1 2.805 +5 _460_:ZN _161_:5 5.585 +6 _461_:A2 _161_:1 2.805 *END *D_NET _162_ 13.12 *CONN -*I _462_/ZN O *D NAND3_X1 -*I _463_/A1 I *D NOR2_X1 +*I _462_:ZN O *D NAND3_X1 +*I _463_:A1 I *D NOR2_X1 *CAP 1 _162_:1 3.155 2 _162_:2 2.1 @@ -5327,27 +5327,27 @@ resp_val O 2 _162_:2 _162_:3 0.005 3 _162_:3 _162_:4 8.4 4 _162_:4 _162_:5 0.005 -5 _462_/ZN _162_:5 5.225 -6 _463_/A1 _162_:1 4.225 +5 _462_:ZN _162_:5 5.225 +6 _463_:A1 _162_:1 4.225 *END *D_NET _163_ 9.59 *CONN -*I _463_/ZN O *D NOR2_X1 -*I _465_/A1 I *D OR3_X1 +*I _463_:ZN O *D NOR2_X1 +*I _465_:A1 I *D OR3_X1 *CAP 1 _163_:1 3.365 2 _163_:2 3.53 *RES 1 _163_:2 _163_:1 8.4 -2 _463_/ZN _163_:1 5.065 -3 _465_/A1 _163_:2 5.725 +2 _463_:ZN _163_:1 5.065 +3 _465_:A1 _163_:2 5.725 *END *D_NET _164_ 11.92 *CONN -*I _464_/ZN O *D AOI211_X1 -*I _465_/A3 I *D OR3_X1 +*I _464_:ZN O *D AOI211_X1 +*I _465_:A3 I *D OR3_X1 *CAP 1 _164_:1 1.81 2 _164_:2 2.1 @@ -5357,23 +5357,23 @@ resp_val O 1 _164_:1 _164_:2 0.005 2 _164_:2 _164_:3 8.4 3 _164_:3 _164_:4 0.005 -4 _464_/ZN _164_:4 8.205 -5 _465_/A3 _164_:1 7.245 +4 _464_:ZN _164_:4 8.205 +5 _465_:A3 _164_:1 7.245 *END *D_NET _165_ 206.18 *CONN -*I _466_/Z O *D BUF_X2 -*I _467_/B1 I *D OAI21_X1 -*I _552_/B1 I *D OAI21_X1 -*I _561_/B1 I *D OAI21_X1 -*I _567_/B1 I *D OAI21_X1 -*I _576_/B1 I *D OAI21_X1 -*I _585_/B1 I *D OAI21_X1 -*I _593_/B1 I *D OAI21_X1 -*I _601_/B1 I *D OAI21_X1 -*I _637_/B1 I *D OAI21_X1 -*I _679_/B1 I *D OAI21_X1 +*I _466_:Z O *D BUF_X2 +*I _467_:B1 I *D OAI21_X1 +*I _552_:B1 I *D OAI21_X1 +*I _561_:B1 I *D OAI21_X1 +*I _567_:B1 I *D OAI21_X1 +*I _576_:B1 I *D OAI21_X1 +*I _585_:B1 I *D OAI21_X1 +*I _593_:B1 I *D OAI21_X1 +*I _601_:B1 I *D OAI21_X1 +*I _637_:B1 I *D OAI21_X1 +*I _679_:B1 I *D OAI21_X1 *CAP 1 _165_:1 0.425 2 _165_:2 2.1 @@ -5433,23 +5433,23 @@ resp_val O 26 _165_:28 _165_:29 0.005 27 _165_:29 _165_:25 8.4 28 _165_:7 _165_:23 42 -29 _466_/Z _165_:1 1.705 -30 _467_/B1 _165_:9 3.465 -31 _552_/B1 _165_:20 5.105 -32 _561_/B1 _165_:5 6.845 -33 _567_/B1 _165_:16 4.405 -34 _576_/B1 _165_:14 4.385 -35 _585_/B1 _165_:13 6.045 -36 _593_/B1 _165_:15 3.045 -37 _601_/B1 _165_:21 3.485 -38 _637_/B1 _165_:24 1.465 -39 _679_/B1 _165_:22 2.865 +29 _466_:Z _165_:1 1.705 +30 _467_:B1 _165_:9 3.465 +31 _552_:B1 _165_:20 5.105 +32 _561_:B1 _165_:5 6.845 +33 _567_:B1 _165_:16 4.405 +34 _576_:B1 _165_:14 4.385 +35 _585_:B1 _165_:13 6.045 +36 _593_:B1 _165_:15 3.045 +37 _601_:B1 _165_:21 3.485 +38 _637_:B1 _165_:24 1.465 +39 _679_:B1 _165_:22 2.865 *END *D_NET _166_ 17.19 *CONN -*I _467_/ZN O *D OAI21_X1 -*I _547_/A I *D OAI211_X1 +*I _467_:ZN O *D OAI21_X1 +*I _547_:A I *D OAI211_X1 *CAP 1 _166_:1 3.53 2 _166_:2 2.1 @@ -5463,15 +5463,15 @@ resp_val O 3 _166_:3 _166_:4 8.4 4 _166_:4 _166_:5 0.005 5 _166_:5 _166_:6 8.4 -6 _467_/ZN _166_:6 3.465 -7 _547_/A _166_:1 5.725 +6 _467_:ZN _166_:6 3.465 +7 _547_:A _166_:1 5.725 *END *D_NET _167_ 13.45 *CONN -*I _468_/ZN O *D INV_X1 -*I _469_/A1 I *D NAND2_X1 -*I _682_/B1 I *D OAI21_X1 +*I _468_:ZN O *D INV_X1 +*I _469_:A1 I *D NAND2_X1 +*I _682_:B1 I *D OAI21_X1 *CAP 1 _167_:1 3.17 2 _167_:2 2.1 @@ -5481,15 +5481,15 @@ resp_val O 1 _167_:1 _167_:2 0.005 2 _167_:2 _167_:3 8.4 3 _167_:3 _167_:4 0.005 -4 _468_/ZN _167_:1 6.325 -5 _469_/A1 _167_:1 6.365 -6 _682_/B1 _167_:4 5.825 +4 _468_:ZN _167_:1 6.325 +5 _469_:A1 _167_:1 6.365 +6 _682_:B1 _167_:4 5.825 *END *D_NET _168_ 17.03 *CONN -*I _469_/ZN O *D NAND2_X1 -*I _530_/A1 I *D AND4_X1 +*I _469_:ZN O *D NAND2_X1 +*I _530_:A1 I *D AND4_X1 *CAP 1 _168_:1 2.76 2 _168_:2 2.1 @@ -5501,17 +5501,17 @@ resp_val O 2 _168_:2 _168_:3 0.005 3 _168_:3 _168_:4 16.8 4 _168_:4 _168_:5 0.005 -5 _469_/ZN _168_:5 6.225 -6 _530_/A1 _168_:1 2.645 +5 _469_:ZN _168_:5 6.225 +6 _530_:A1 _168_:1 2.645 *END *D_NET _169_ 34.86 *CONN -*I _470_/ZN O *D XNOR2_X2 -*I _472_/A1 I *D AND2_X1 -*I _495_/A1 I *D NAND3_X1 -*I _606_/B I *D XNOR2_X1 -*I _612_/A1 I *D AND2_X1 +*I _470_:ZN O *D XNOR2_X2 +*I _472_:A1 I *D AND2_X1 +*I _495_:A1 I *D NAND3_X1 +*I _606_:B I *D XNOR2_X1 +*I _612_:A1 I *D AND2_X1 *CAP 1 _169_:1 2.305 2 _169_:2 2.1 @@ -5535,18 +5535,18 @@ resp_val O 8 _169_:5 _169_:9 8.4 9 _169_:9 _169_:10 0.005 10 _169_:10 _169_:11 8.4 -11 _470_/ZN _169_:11 3.185 -12 _472_/A1 _169_:1 0.825 -13 _495_/A1 _169_:7 1.605 -14 _606_/B _169_:6 3.325 -15 _612_/A1 _169_:3 2.005 +11 _470_:ZN _169_:11 3.185 +12 _472_:A1 _169_:1 0.825 +13 _495_:A1 _169_:7 1.605 +14 _606_:B _169_:6 3.325 +15 _612_:A1 _169_:3 2.005 *END *D_NET _170_ 11.59 *CONN -*I _471_/ZN O *D XNOR2_X1 -*I _472_/A2 I *D AND2_X1 -*I _597_/B I *D XNOR2_X1 +*I _471_:ZN O *D XNOR2_X1 +*I _472_:A2 I *D AND2_X1 +*I _597_:B I *D XNOR2_X1 *CAP 1 _170_:1 5.04 2 _170_:2 2.495 @@ -5554,19 +5554,19 @@ resp_val O *RES 1 _170_:1 _170_:2 8.4 2 _170_:3 _170_:1 8.4 -3 _471_/ZN _170_:3 1.445 -4 _472_/A2 _170_:2 1.585 -5 _597_/B _170_:1 3.365 +3 _471_:ZN _170_:3 1.445 +4 _472_:A2 _170_:2 1.585 +5 _597_:B _170_:1 3.365 *END *D_NET _171_ 51.47 *CONN -*I _472_/ZN O *D AND2_X1 -*I _479_/A1 I *D NAND3_X1 -*I _490_/A I *D OAI21_X1 -*I _499_/A I *D OAI211_X1 -*I _538_/A1 I *D AND2_X1 -*I _613_/C2 I *D AOI221_X1 +*I _472_:ZN O *D AND2_X1 +*I _479_:A1 I *D NAND3_X1 +*I _490_:A I *D OAI21_X1 +*I _499_:A I *D OAI211_X1 +*I _538_:A1 I *D AND2_X1 +*I _613_:C2 I *D AOI221_X1 *CAP 1 _171_:1 3.515 2 _171_:2 12.6 @@ -5584,20 +5584,20 @@ resp_val O 5 _171_:5 _171_:7 0.005 6 _171_:7 _171_:2 33.6 7 _171_:8 _171_:1 8.4 -8 _472_/ZN _171_:8 2.965 -9 _479_/A1 _171_:5 7.785 -10 _490_/A _171_:4 2.345 -11 _499_/A _171_:6 5.965 -12 _538_/A1 _171_:5 2.645 -13 _613_/C2 _171_:1 5.665 +8 _472_:ZN _171_:8 2.965 +9 _479_:A1 _171_:5 7.785 +10 _490_:A _171_:4 2.345 +11 _499_:A _171_:6 5.965 +12 _538_:A1 _171_:5 2.645 +13 _613_:C2 _171_:1 5.665 *END *D_NET _172_ 23.95 *CONN -*I _473_/ZN O *D XNOR2_X1 -*I _475_/A1 I *D AND2_X1 -*I _572_/B I *D XNOR2_X1 -*I _577_/A1 I *D AND2_X1 +*I _473_:ZN O *D XNOR2_X1 +*I _475_:A1 I *D AND2_X1 +*I _572_:B I *D XNOR2_X1 +*I _577_:A1 I *D AND2_X1 *CAP 1 _172_:1 0.79 2 _172_:2 4.2 @@ -5615,18 +5615,18 @@ resp_val O 5 _172_:7 _172_:6 8.4 6 _172_:7 _172_:8 0.005 7 _172_:8 _172_:2 8.4 -8 _473_/ZN _172_:5 4.085 -9 _475_/A1 _172_:6 4.105 -10 _572_/B _172_:5 2.965 -11 _577_/A1 _172_:1 3.165 +8 _473_:ZN _172_:5 4.085 +9 _475_:A1 _172_:6 4.105 +10 _572_:B _172_:5 2.965 +11 _577_:A1 _172_:1 3.165 *END *D_NET _173_ 30.85 *CONN -*I _474_/ZN O *D XNOR2_X1 -*I _475_/A2 I *D AND2_X1 -*I _563_/B I *D XNOR2_X1 -*I _569_/A2 I *D AND2_X1 +*I _474_:ZN O *D XNOR2_X1 +*I _475_:A2 I *D AND2_X1 +*I _563_:B I *D XNOR2_X1 +*I _569_:A2 I *D AND2_X1 *CAP 1 _173_:1 3.84 2 _173_:2 2.935 @@ -5644,18 +5644,18 @@ resp_val O 5 _173_:5 _173_:7 8.4 6 _173_:7 _173_:2 0.005 7 _173_:6 _173_:8 16.8 -8 _474_/ZN _173_:8 4.805 -9 _475_/A2 _173_:2 3.345 -10 _563_/B _173_:3 4.605 -11 _569_/A2 _173_:1 6.965 +8 _474_:ZN _173_:8 4.805 +9 _475_:A2 _173_:2 3.345 +10 _563_:B _173_:3 4.605 +11 _569_:A2 _173_:1 6.965 *END *D_NET _174_ 47.88 *CONN -*I _475_/ZN O *D AND2_X1 -*I _479_/A2 I *D NAND3_X1 -*I _539_/A4 I *D NAND4_X1 -*I _579_/A2 I *D NAND2_X1 +*I _475_:ZN O *D AND2_X1 +*I _479_:A2 I *D NAND3_X1 +*I _539_:A4 I *D NAND4_X1 +*I _579_:A2 I *D NAND2_X1 *CAP 1 _174_:1 1.17 2 _174_:2 4.2 @@ -5673,20 +5673,20 @@ resp_val O 5 _174_:5 _174_:6 0.005 6 _174_:6 _174_:7 25.2 7 _174_:7 _174_:8 25.2 -8 _475_/ZN _174_:8 3.645 -9 _479_/A2 _174_:4 6.865 -10 _539_/A4 _174_:1 4.685 -11 _579_/A2 _174_:7 4.985 +8 _475_:ZN _174_:8 3.645 +9 _479_:A2 _174_:4 6.865 +10 _539_:A4 _174_:1 4.685 +11 _579_:A2 _174_:7 4.985 *END *D_NET _175_ 40.82 *CONN -*I _476_/ZN O *D XNOR2_X2 -*I _478_/A1 I *D AND2_X1 -*I _487_/A1 I *D AND3_X1 -*I _588_/A2 I *D NOR3_X1 -*I _589_/B1 I *D AOI221_X4 -*I _594_/A1 I *D NAND2_X1 +*I _476_:ZN O *D XNOR2_X2 +*I _478_:A1 I *D AND2_X1 +*I _487_:A1 I *D AND3_X1 +*I _588_:A2 I *D NOR3_X1 +*I _589_:B1 I *D AOI221_X4 +*I _594_:A1 I *D NAND2_X1 *CAP 1 _175_:1 3.375 2 _175_:2 4.09 @@ -5710,20 +5710,20 @@ resp_val O 8 _175_:10 _175_:11 8.4 9 _175_:11 _175_:4 0.005 10 _175_:11 _175_:6 8.4 -11 _476_/ZN _175_:9 5.305 -12 _478_/A1 _175_:1 5.105 -13 _487_/A1 _175_:5 4.545 -14 _588_/A2 _175_:3 5.145 -15 _589_/B1 _175_:2 7.965 -16 _594_/A1 _175_:4 3.205 +11 _476_:ZN _175_:9 5.305 +12 _478_:A1 _175_:1 5.105 +13 _487_:A1 _175_:5 4.545 +14 _588_:A2 _175_:3 5.145 +15 _589_:B1 _175_:2 7.965 +16 _594_:A1 _175_:4 3.205 *END *D_NET _176_ 16.78 *CONN -*I _477_/ZN O *D XNOR2_X1 -*I _478_/A2 I *D AND2_X1 -*I _581_/B I *D XOR2_X1 -*I _586_/A2 I *D AND2_X1 +*I _477_:ZN O *D XNOR2_X1 +*I _478_:A2 I *D AND2_X1 +*I _581_:B I *D XOR2_X1 +*I _586_:A2 I *D AND2_X1 *CAP 1 _176_:1 4.055 2 _176_:2 3.185 @@ -5735,20 +5735,20 @@ resp_val O 2 _176_:1 _176_:3 0.005 3 _176_:3 _176_:4 8.4 4 _176_:4 _176_:5 0.005 -5 _477_/ZN _176_:5 4.605 -6 _478_/A2 _176_:2 4.345 -7 _581_/B _176_:1 5.625 -8 _586_/A2 _176_:1 2.205 +5 _477_:ZN _176_:5 4.605 +6 _478_:A2 _176_:2 4.345 +7 _581_:B _176_:1 5.625 +8 _586_:A2 _176_:1 2.205 *END *D_NET _177_ 58.39 *CONN -*I _478_/ZN O *D AND2_X1 -*I _479_/A3 I *D NAND3_X1 -*I _499_/B I *D OAI211_X1 -*I _538_/A2 I *D AND2_X1 -*I _589_/C1 I *D AOI221_X4 -*I _596_/B2 I *D AOI21_X1 +*I _478_:ZN O *D AND2_X1 +*I _479_:A3 I *D NAND3_X1 +*I _499_:B I *D OAI211_X1 +*I _538_:A2 I *D AND2_X1 +*I _589_:C1 I *D AOI221_X4 +*I _596_:B2 I *D AOI21_X1 *CAP 1 _177_:1 0.47 2 _177_:2 4.2 @@ -5778,18 +5778,18 @@ resp_val O 11 _177_:3 _177_:13 33.6 12 _177_:13 _177_:14 0.005 13 _177_:10 _177_:14 8.4 -14 _478_/ZN _177_:8 4.245 -15 _479_/A3 _177_:6 6.105 -16 _499_/B _177_:5 5.785 -17 _538_/A2 _177_:1 1.885 -18 _589_/C1 _177_:9 5.005 -19 _596_/B2 _177_:10 1.385 +14 _478_:ZN _177_:8 4.245 +15 _479_:A3 _177_:6 6.105 +16 _499_:B _177_:5 5.785 +17 _538_:A2 _177_:1 1.885 +18 _589_:C1 _177_:9 5.005 +19 _596_:B2 _177_:10 1.385 *END *D_NET _178_ 19.19 *CONN -*I _479_/ZN O *D NAND3_X1 -*I _485_/A1 I *D OR3_X1 +*I _479_:ZN O *D NAND3_X1 +*I _485_:A1 I *D OR3_X1 *CAP 1 _178_:1 4.2 2 _178_:2 5.72 @@ -5801,15 +5801,15 @@ resp_val O 2 _178_:1 _178_:3 0.005 3 _178_:3 _178_:4 8.4 4 _178_:4 _178_:5 0.005 -5 _479_/ZN _178_:5 7.105 -6 _485_/A1 _178_:2 6.085 +5 _479_:ZN _178_:5 7.105 +6 _485_:A1 _178_:2 6.085 *END *D_NET _179_ 20.97 *CONN -*I _480_/ZN O *D INV_X1 -*I _481_/A1 I *D AND2_X1 -*I _482_/A1 I *D NOR2_X1 +*I _480_:ZN O *D INV_X1 +*I _481_:A1 I *D AND2_X1 +*I _482_:A1 I *D NOR2_X1 *CAP 1 _179_:1 1.215 2 _179_:2 6.3 @@ -5823,16 +5823,16 @@ resp_val O 3 _179_:3 _179_:4 0.005 4 _179_:5 _179_:6 0.005 5 _179_:6 _179_:2 16.8 -6 _480_/ZN _179_:5 7.525 -7 _481_/A1 _179_:1 4.865 -8 _482_/A1 _179_:4 4.365 +6 _480_:ZN _179_:5 7.525 +7 _481_:A1 _179_:1 4.865 +8 _482_:A1 _179_:4 4.365 *END *D_NET _180_ 15.16 *CONN -*I _481_/ZN O *D AND2_X1 -*I _485_/A2 I *D OR3_X1 -*I _562_/A I *D AOI21_X1 +*I _481_:ZN O *D AND2_X1 +*I _485_:A2 I *D OR3_X1 +*I _562_:A I *D AOI21_X1 *CAP 1 _180_:1 2.75 2 _180_:2 2.1 @@ -5844,29 +5844,29 @@ resp_val O 2 _180_:2 _180_:3 8.4 3 _180_:3 _180_:4 0.005 4 _180_:1 _180_:5 8.4 -5 _481_/ZN _180_:1 2.605 -6 _485_/A2 _180_:4 6.845 -7 _562_/A _180_:5 4.085 +5 _481_:ZN _180_:1 2.605 +6 _485_:A2 _180_:4 6.845 +7 _562_:A _180_:5 4.085 *END *D_NET _181_ 7.58 *CONN -*I _482_/ZN O *D NOR2_X1 -*I _484_/A1 I *D NOR3_X1 +*I _482_:ZN O *D NOR2_X1 +*I _484_:A1 I *D NOR3_X1 *CAP 1 _181_:1 3.35 2 _181_:2 2.54 *RES 1 _181_:1 _181_:2 8.4 -2 _482_/ZN _181_:1 5.005 -3 _484_/A1 _181_:2 1.765 +2 _482_:ZN _181_:1 5.005 +3 _484_:A1 _181_:2 1.765 *END *D_NET _182_ 13.39 *CONN -*I _483_/ZN O *D INV_X1 -*I _484_/A2 I *D NOR3_X1 -*I _556_/A1 I *D NAND2_X1 +*I _483_:ZN O *D INV_X1 +*I _484_:A2 I *D NOR3_X1 +*I _556_:A1 I *D NAND2_X1 *CAP 1 _182_:1 5.085 2 _182_:2 2.55 @@ -5874,28 +5874,28 @@ resp_val O *RES 1 _182_:2 _182_:1 8.4 2 _182_:1 _182_:3 8.4 -3 _483_/ZN _182_:3 4.645 -4 _484_/A2 _182_:2 1.805 -5 _556_/A1 _182_:1 3.545 +3 _483_:ZN _182_:3 4.645 +4 _484_:A2 _182_:2 1.805 +5 _556_:A1 _182_:1 3.545 *END *D_NET _183_ 8.38 *CONN -*I _484_/ZN O *D NOR3_X1 -*I _485_/A3 I *D OR3_X1 +*I _484_:ZN O *D NOR3_X1 +*I _485_:A3 I *D OR3_X1 *CAP 1 _183_:1 2.29 2 _183_:2 4 *RES 1 _183_:2 _183_:1 8.4 -2 _484_/ZN _183_:1 0.765 -3 _485_/A3 _183_:2 7.605 +2 _484_:ZN _183_:1 0.765 +3 _485_:A3 _183_:2 7.605 *END *D_NET _184_ 19.64 *CONN -*I _485_/ZN O *D OR3_X1 -*I _500_/A1 I *D NAND3_X1 +*I _485_:ZN O *D OR3_X1 +*I _500_:A1 I *D NAND3_X1 *CAP 1 _184_:1 4.2 2 _184_:2 6.68 @@ -5907,29 +5907,29 @@ resp_val O 2 _184_:1 _184_:3 0.005 3 _184_:3 _184_:4 8.4 4 _184_:4 _184_:5 0.005 -5 _485_/ZN _184_:2 9.925 -6 _500_/A1 _184_:5 4.165 +5 _485_:ZN _184_:2 9.925 +6 _500_:A1 _184_:5 4.165 *END *D_NET _185_ 11.2 *CONN -*I _486_/ZN O *D INV_X1 -*I _487_/A2 I *D AND3_X1 -*I _587_/A1 I *D NOR2_X1 +*I _486_:ZN O *D INV_X1 +*I _487_:A2 I *D AND3_X1 +*I _587_:A1 I *D NOR2_X1 *CAP 1 _185_:1 3.54 2 _185_:2 4.16 *RES 1 _185_:1 _185_:2 8.4 -2 _486_/ZN _185_:1 5.765 -3 _487_/A2 _185_:2 3.785 -4 _587_/A1 _185_:2 4.465 +2 _486_:ZN _185_:1 5.765 +3 _487_:A2 _185_:2 3.785 +4 _587_:A1 _185_:2 4.465 *END *D_NET _186_ 14.99 *CONN -*I _487_/ZN O *D AND3_X1 -*I _490_/B1 I *D OAI21_X1 +*I _487_:ZN O *D AND3_X1 +*I _490_:B1 I *D OAI21_X1 *CAP 1 _186_:1 2.875 2 _186_:2 2.1 @@ -5941,15 +5941,15 @@ resp_val O 2 _186_:2 _186_:3 0.005 3 _186_:3 _186_:4 16.8 4 _186_:4 _186_:5 0.005 -5 _487_/ZN _186_:5 1.685 -6 _490_/B1 _186_:1 3.105 +5 _487_:ZN _186_:5 1.685 +6 _490_:B1 _186_:1 3.105 *END *D_NET _187_ 19.82 *CONN -*I _488_/ZN O *D INV_X1 -*I _489_/A1 I *D AND2_X1 -*I _595_/B1 I *D OAI21_X1 +*I _488_:ZN O *D INV_X1 +*I _489_:A1 I *D AND2_X1 +*I _595_:B1 I *D OAI21_X1 *CAP 1 _187_:1 1.835 2 _187_:2 2.1 @@ -5965,15 +5965,15 @@ resp_val O 4 _187_:3 _187_:5 8.4 5 _187_:5 _187_:6 0.005 6 _187_:6 _187_:7 8.4 -7 _488_/ZN _187_:7 3.205 -8 _489_/A1 _187_:1 7.345 -9 _595_/B1 _187_:4 3.905 +7 _488_:ZN _187_:7 3.205 +8 _489_:A1 _187_:1 7.345 +9 _595_:B1 _187_:4 3.905 *END *D_NET _188_ 14.9 *CONN -*I _489_/ZN O *D AND2_X1 -*I _490_/B2 I *D OAI21_X1 +*I _489_:ZN O *D AND2_X1 +*I _490_:B2 I *D OAI21_X1 *CAP 1 _188_:1 3.2 2 _188_:2 2.1 @@ -5985,14 +5985,14 @@ resp_val O 2 _188_:2 _188_:3 0.005 3 _188_:3 _188_:4 8.4 4 _188_:4 _188_:5 0.005 -5 _489_/ZN _188_:5 8.605 -6 _490_/B2 _188_:1 4.405 +5 _489_:ZN _188_:5 8.605 +6 _490_:B2 _188_:1 4.405 *END *D_NET _189_ 25.59 *CONN -*I _490_/ZN O *D OAI21_X1 -*I _496_/A1 I *D AND3_X1 +*I _490_:ZN O *D OAI21_X1 +*I _496_:A1 I *D AND3_X1 *CAP 1 _189_:1 3.35 2 _189_:2 2.1 @@ -6004,15 +6004,15 @@ resp_val O 2 _189_:2 _189_:3 0.005 3 _189_:3 _189_:4 33.6 4 _189_:4 _189_:5 0.005 -5 _490_/ZN _189_:5 4.185 -6 _496_/A1 _189_:1 5.005 +5 _490_:ZN _189_:5 4.185 +6 _496_:A1 _189_:1 5.005 *END *D_NET _190_ 21.34 *CONN -*I _491_/ZN O *D INV_X1 -*I _492_/A1 I *D NOR2_X1 -*I _613_/B2 I *D AOI221_X1 +*I _491_:ZN O *D INV_X1 +*I _492_:A1 I *D NOR2_X1 +*I _613_:B2 I *D AOI221_X1 *CAP 1 _190_:1 4.2 2 _190_:2 3.77 @@ -6026,15 +6026,15 @@ resp_val O 3 _190_:4 _190_:5 8.4 4 _190_:5 _190_:1 0.005 5 _190_:6 _190_:1 8.4 -6 _491_/ZN _190_:2 6.685 -7 _492_/A1 _190_:3 2.865 -8 _613_/B2 _190_:6 7.945 +6 _491_:ZN _190_:2 6.685 +7 _492_:A1 _190_:3 2.865 +8 _613_:B2 _190_:6 7.945 *END *D_NET _191_ 10.58 *CONN -*I _492_/ZN O *D NOR2_X1 -*I _493_/A I *D INV_X1 +*I _492_:ZN O *D NOR2_X1 +*I _493_:A I *D INV_X1 *CAP 1 _191_:1 0.855 2 _191_:2 2.1 @@ -6046,29 +6046,29 @@ resp_val O 2 _191_:2 _191_:3 8.4 3 _191_:3 _191_:4 0.005 4 _191_:5 _191_:4 8.4 -5 _492_/ZN _191_:5 0.945 -6 _493_/A _191_:1 3.425 +5 _492_:ZN _191_:5 0.945 +6 _493_:A _191_:1 3.425 *END *D_NET _192_ 8.44 *CONN -*I _493_/ZN O *D INV_X1 -*I _496_/A2 I *D AND3_X1 +*I _493_:ZN O *D INV_X1 +*I _496_:A2 I *D AND3_X1 *CAP 1 _192_:1 3.16 2 _192_:2 3.16 *RES 1 _192_:2 _192_:1 8.4 -2 _493_/ZN _192_:1 4.245 -3 _496_/A2 _192_:2 4.245 +2 _493_:ZN _192_:1 4.245 +3 _496_:A2 _192_:2 4.245 *END *D_NET _193_ 20.9 *CONN -*I _494_/ZN O *D INV_X1 -*I _495_/A2 I *D NAND3_X1 -*I _602_/A1 I *D AND2_X1 -*I _603_/A1 I *D NOR2_X1 +*I _494_:ZN O *D INV_X1 +*I _495_:A2 I *D NAND3_X1 +*I _602_:A1 I *D AND2_X1 +*I _603_:A1 I *D NOR2_X1 *CAP 1 _193_:1 4.71 2 _193_:2 2.59 @@ -6082,29 +6082,29 @@ resp_val O 3 _193_:4 _193_:5 0.005 4 _193_:5 _193_:6 8.4 5 _193_:6 _193_:1 0.005 -6 _494_/ZN _193_:3 4.205 -7 _495_/A2 _193_:2 1.965 -8 _602_/A1 _193_:1 5.925 -9 _603_/A1 _193_:1 4.525 +6 _494_:ZN _193_:3 4.205 +7 _495_:A2 _193_:2 1.965 +8 _602_:A1 _193_:1 5.925 +9 _603_:A1 _193_:1 4.525 *END *D_NET _194_ 8.05 *CONN -*I _495_/ZN O *D NAND3_X1 -*I _496_/A3 I *D AND3_X1 +*I _495_:ZN O *D NAND3_X1 +*I _496_:A3 I *D AND3_X1 *CAP 1 _194_:1 3.155 2 _194_:2 2.97 *RES 1 _194_:1 _194_:2 8.4 -2 _495_/ZN _194_:1 4.225 -3 _496_/A3 _194_:2 3.485 +2 _495_:ZN _194_:1 4.225 +3 _496_:A3 _194_:2 3.485 *END *D_NET _195_ 12.43 *CONN -*I _496_/ZN O *D AND3_X1 -*I _500_/A2 I *D NAND3_X1 +*I _496_:ZN O *D AND3_X1 +*I _500_:A2 I *D NAND3_X1 *CAP 1 _195_:1 1.23 2 _195_:2 4.2 @@ -6114,14 +6114,14 @@ resp_val O 1 _195_:1 _195_:2 0.005 2 _195_:2 _195_:3 16.8 3 _195_:3 _195_:4 0.005 -4 _496_/ZN _195_:4 3.145 -5 _500_/A2 _195_:1 4.925 +4 _496_:ZN _195_:4 3.145 +5 _500_:A2 _195_:1 4.925 *END *D_NET _196_ 12.83 *CONN -*I _497_/ZN O *D NOR2_X1 -*I _499_/C1 I *D OAI211_X1 +*I _497_:ZN O *D NOR2_X1 +*I _499_:C1 I *D OAI211_X1 *CAP 1 _196_:1 3.415 2 _196_:2 2.1 @@ -6133,40 +6133,40 @@ resp_val O 2 _196_:2 _196_:3 0.005 3 _196_:3 _196_:4 8.4 4 _196_:4 _196_:5 0.005 -5 _497_/ZN _196_:5 3.605 -6 _499_/C1 _196_:1 5.265 +5 _497_:ZN _196_:5 3.605 +6 _499_:C1 _196_:1 5.265 *END *D_NET _197_ 15.25 *CONN -*I _498_/ZN O *D AOI211_X1 -*I _499_/C2 I *D OAI211_X1 +*I _498_:ZN O *D AOI211_X1 +*I _499_:C2 I *D OAI211_X1 *CAP 1 _197_:1 7.275 2 _197_:2 6.65 *RES 1 _197_:1 _197_:2 25.2 -2 _498_/ZN _197_:2 1.405 -3 _499_/C2 _197_:1 3.905 +2 _498_:ZN _197_:2 1.405 +3 _499_:C2 _197_:1 3.905 *END *D_NET _198_ 9.85 *CONN -*I _499_/ZN O *D OAI211_X1 -*I _500_/A3 I *D NAND3_X1 +*I _499_:ZN O *D OAI211_X1 +*I _500_:A3 I *D NAND3_X1 *CAP 1 _198_:1 3.505 2 _198_:2 3.52 *RES 1 _198_:2 _198_:1 8.4 -2 _499_/ZN _198_:1 5.625 -3 _500_/A3 _198_:2 5.685 +2 _499_:ZN _198_:1 5.625 +3 _500_:A3 _198_:2 5.685 *END *D_NET _199_ 21.55 *CONN -*I _500_/ZN O *D NAND3_X1 -*I _516_/A1 I *D NAND2_X1 +*I _500_:ZN O *D NAND3_X1 +*I _516_:A1 I *D NAND2_X1 *CAP 1 _199_:1 5.48 2 _199_:2 4.2 @@ -6178,16 +6178,16 @@ resp_val O 2 _199_:2 _199_:3 0.005 3 _199_:3 _199_:4 16.8 4 _199_:4 _199_:5 0.005 -5 _500_/ZN _199_:5 4.385 -6 _516_/A1 _199_:1 5.125 +5 _500_:ZN _199_:5 4.385 +6 _516_:A1 _199_:1 5.125 *END *D_NET _200_ 30.72 *CONN -*I _501_/ZN O *D XNOR2_X1 -*I _503_/A1 I *D AND2_X1 -*I _633_/B I *D XNOR2_X1 -*I _639_/A I *D OAI21_X1 +*I _501_:ZN O *D XNOR2_X1 +*I _503_:A1 I *D AND2_X1 +*I _633_:B I *D XNOR2_X1 +*I _639_:A I *D OAI21_X1 *CAP 1 _200_:1 4.07 2 _200_:2 2.1 @@ -6207,18 +6207,18 @@ resp_val O 6 _200_:4 _200_:8 8.4 7 _200_:8 _200_:9 0.005 8 _200_:9 _200_:6 8.4 -9 _501_/ZN _200_:5 7.525 -10 _503_/A1 _200_:6 1.565 -11 _633_/B _200_:1 7.885 -12 _639_/A _200_:7 2.485 +9 _501_:ZN _200_:5 7.525 +10 _503_:A1 _200_:6 1.565 +11 _633_:B _200_:1 7.885 +12 _639_:A _200_:7 2.485 *END *D_NET _201_ 33.14 *CONN -*I _502_/ZN O *D XNOR2_X1 -*I _503_/A2 I *D AND2_X1 -*I _643_/B I *D XNOR2_X1 -*I _650_/B1 I *D AOI21_X1 +*I _502_:ZN O *D XNOR2_X1 +*I _503_:A2 I *D AND2_X1 +*I _643_:B I *D XNOR2_X1 +*I _650_:B1 I *D AOI21_X1 *CAP 1 _201_:1 0.5 2 _201_:2 4.2 @@ -6234,18 +6234,18 @@ resp_val O 4 _201_:5 _201_:6 8.4 5 _201_:3 _201_:7 25.2 6 _201_:7 _201_:6 0.005 -7 _502_/ZN _201_:5 4.725 -8 _503_/A2 _201_:1 2.005 -9 _643_/B _201_:6 6.645 -10 _650_/B1 _201_:4 2.525 +7 _502_:ZN _201_:5 4.725 +8 _503_:A2 _201_:1 2.005 +9 _643_:B _201_:6 6.645 +10 _650_:B1 _201_:4 2.525 *END *D_NET _202_ 27.42 *CONN -*I _503_/ZN O *D AND2_X1 -*I _506_/A1 I *D AND3_X1 -*I _521_/A I *D OAI21_X1 -*I _649_/A2 I *D NAND2_X1 +*I _503_:ZN O *D AND2_X1 +*I _506_:A1 I *D AND3_X1 +*I _521_:A I *D OAI21_X1 +*I _649_:A2 I *D NAND2_X1 *CAP 1 _202_:1 8.07 2 _202_:2 3.015 @@ -6259,21 +6259,21 @@ resp_val O 3 _202_:4 _202_:5 8.4 4 _202_:5 _202_:1 0.005 5 _202_:6 _202_:1 16.8 -6 _503_/ZN _202_:6 2.845 -7 _506_/A1 _202_:2 3.665 -8 _521_/A _202_:3 7.665 -9 _649_/A2 _202_:1 7.085 +6 _503_:ZN _202_:6 2.845 +7 _506_:A1 _202_:2 3.665 +8 _521_:A _202_:3 7.665 +9 _649_:A2 _202_:1 7.085 *END *D_NET _203_ 36.11 *CONN -*I _504_/ZN O *D XNOR2_X2 -*I _506_/A2 I *D AND3_X1 -*I _518_/A1 I *D AND3_X1 -*I _620_/A2 I *D AND3_X1 -*I _623_/A2 I *D NOR3_X1 -*I _624_/C1 I *D AOI211_X1 -*I _630_/B1 I *D AOI21_X1 +*I _504_:ZN O *D XNOR2_X2 +*I _506_:A2 I *D AND3_X1 +*I _518_:A1 I *D AND3_X1 +*I _620_:A2 I *D AND3_X1 +*I _623_:A2 I *D NOR3_X1 +*I _624_:C1 I *D AOI211_X1 +*I _630_:B1 I *D AOI21_X1 *CAP 1 _203_:1 1.635 2 _203_:2 4.2 @@ -6295,22 +6295,22 @@ resp_val O 7 _203_:8 _203_:9 0.005 8 _203_:9 _203_:10 16.8 9 _203_:10 _203_:5 0.005 -10 _504_/ZN _203_:8 6.905 -11 _506_/A2 _203_:4 4.105 -12 _518_/A1 _203_:6 5.285 -13 _620_/A2 _203_:1 4.145 -14 _623_/A2 _203_:6 4.945 -15 _624_/C1 _203_:1 2.405 -16 _630_/B1 _203_:5 2.465 +10 _504_:ZN _203_:8 6.905 +11 _506_:A2 _203_:4 4.105 +12 _518_:A1 _203_:6 5.285 +13 _620_:A2 _203_:1 4.145 +14 _623_:A2 _203_:6 4.945 +15 _624_:C1 _203_:1 2.405 +16 _630_:B1 _203_:5 2.465 *END *D_NET _204_ 26.83 *CONN -*I _505_/ZN O *D XNOR2_X1 -*I _506_/A3 I *D AND3_X1 -*I _615_/B I *D XOR2_X1 -*I _620_/A3 I *D AND3_X1 -*I _621_/A2 I *D AND2_X1 +*I _505_:ZN O *D XNOR2_X1 +*I _506_:A3 I *D AND3_X1 +*I _615_:B I *D XOR2_X1 +*I _620_:A3 I *D AND3_X1 +*I _621_:A2 I *D AND2_X1 *CAP 1 _204_:1 3.325 2 _204_:2 2.1 @@ -6330,19 +6330,19 @@ resp_val O 6 _204_:7 _204_:8 0.005 7 _204_:1 _204_:9 8.4 8 _204_:9 _204_:8 8.4 -9 _505_/ZN _204_:5 4.925 -10 _506_/A3 _204_:4 4.865 -11 _615_/B _204_:8 3.345 -12 _620_/A3 _204_:1 4.905 -13 _621_/A2 _204_:9 2.045 +9 _505_:ZN _204_:5 4.925 +10 _506_:A3 _204_:4 4.865 +11 _615_:B _204_:8 3.345 +12 _620_:A3 _204_:1 4.905 +13 _621_:A2 _204_:9 2.045 *END *D_NET _205_ 49.57 *CONN -*I _506_/ZN O *D AND3_X1 -*I _515_/A1 I *D AND2_X1 -*I _539_/A1 I *D NAND4_X1 -*I _647_/A2 I *D AND2_X1 +*I _506_:ZN O *D AND3_X1 +*I _515_:A1 I *D AND2_X1 +*I _539_:A1 I *D NAND4_X1 +*I _647_:A2 I *D AND2_X1 *CAP 1 _205_:1 1.91 2 _205_:2 8.4 @@ -6366,17 +6366,17 @@ resp_val O 8 _205_:9 _205_:10 0.005 9 _205_:10 _205_:11 16.8 10 _205_:11 _205_:6 0.005 -11 _506_/ZN _205_:9 9.205 -12 _515_/A1 _205_:1 7.645 -13 _539_/A1 _205_:5 3.545 -14 _647_/A2 _205_:6 3.165 +11 _506_:ZN _205_:9 9.205 +12 _515_:A1 _205_:1 7.645 +13 _539_:A1 _205_:5 3.545 +14 _647_:A2 _205_:6 3.165 *END *D_NET _206_ 22.85 *CONN -*I _507_/ZN O *D XNOR2_X1 -*I _509_/A1 I *D NAND2_X1 -*I _666_/A I *D INV_X1 +*I _507_:ZN O *D XNOR2_X1 +*I _509_:A1 I *D NAND2_X1 +*I _666_:A I *D INV_X1 *CAP 1 _206_:1 1.3 2 _206_:2 2.1 @@ -6392,17 +6392,17 @@ resp_val O 4 _206_:3 _206_:5 16.8 5 _206_:5 _206_:6 0.005 6 _206_:7 _206_:4 8.4 -7 _507_/ZN _206_:1 5.205 -8 _509_/A1 _206_:6 4.185 -9 _666_/A _206_:7 2.725 +7 _507_:ZN _206_:1 5.205 +8 _509_:A1 _206_:6 4.185 +9 _666_:A _206_:7 2.725 *END *D_NET _207_ 33.41 *CONN -*I _508_/ZN O *D XNOR2_X2 -*I _509_/A2 I *D NAND2_X1 -*I _529_/A1 I *D NAND3_X1 -*I _677_/B I *D XNOR2_X1 +*I _508_:ZN O *D XNOR2_X2 +*I _509_:A2 I *D NAND2_X1 +*I _529_:A1 I *D NAND3_X1 +*I _677_:B I *D XNOR2_X1 *CAP 1 _207_:1 5.57 2 _207_:2 4.2 @@ -6422,17 +6422,17 @@ resp_val O 6 _207_:5 _207_:7 8.4 7 _207_:7 _207_:8 0.005 8 _207_:8 _207_:9 8.4 -9 _508_/ZN _207_:9 2.185 -10 _509_/A2 _207_:1 5.485 -11 _529_/A1 _207_:3 7.765 -12 _677_/B _207_:6 1.005 +9 _508_:ZN _207_:9 2.185 +10 _509_:A2 _207_:1 5.485 +11 _529_:A1 _207_:3 7.765 +12 _677_:B _207_:6 1.005 *END *D_NET _208_ 19.79 *CONN -*I _509_/ZN O *D NAND2_X1 -*I _514_/A1 I *D NOR3_X1 -*I _536_/A1 I *D OR3_X1 +*I _509_:ZN O *D NAND2_X1 +*I _514_:A1 I *D NOR3_X1 +*I _536_:A1 I *D OR3_X1 *CAP 1 _208_:1 1 2 _208_:2 4.2 @@ -6448,17 +6448,17 @@ resp_val O 4 _208_:4 _208_:5 8.4 5 _208_:6 _208_:7 0.005 6 _208_:7 _208_:2 8.4 -7 _509_/ZN _208_:6 4.125 -8 _514_/A1 _208_:1 4.005 -9 _536_/A1 _208_:5 6.265 +7 _509_:ZN _208_:6 4.125 +8 _514_:A1 _208_:1 4.005 +9 _536_:A1 _208_:5 6.265 *END *D_NET _209_ 28.44 *CONN -*I _510_/ZN O *D XNOR2_X2 -*I _511_/A I *D INV_X1 -*I _660_/B I *D XNOR2_X1 -*I _667_/A1 I *D AOI22_X1 +*I _510_:ZN O *D XNOR2_X2 +*I _511_:A I *D INV_X1 +*I _660_:B I *D XNOR2_X1 +*I _667_:A1 I *D AOI22_X1 *CAP 1 _209_:1 4.2 2 _209_:2 3.99 @@ -6478,17 +6478,17 @@ resp_val O 6 _209_:7 _209_:8 8.4 7 _209_:8 _209_:9 0.005 8 _209_:6 _209_:1 8.4 -9 _510_/ZN _209_:9 5.145 -10 _511_/A _209_:2 7.565 -11 _660_/B _209_:6 4.765 -12 _667_/A1 _209_:3 5.825 +9 _510_:ZN _209_:9 5.145 +10 _511_:A _209_:2 7.565 +11 _660_:B _209_:6 4.765 +12 _667_:A1 _209_:3 5.825 *END *D_NET _210_ 20.36 *CONN -*I _511_/ZN O *D INV_X1 -*I _514_/A2 I *D NOR3_X1 -*I _665_/A2 I *D OR3_X1 +*I _511_:ZN O *D INV_X1 +*I _514_:A2 I *D NOR3_X1 +*I _665_:A2 I *D OR3_X1 *CAP 1 _210_:1 4.37 2 _210_:2 4.2 @@ -6502,16 +6502,16 @@ resp_val O 3 _210_:4 _210_:5 0.005 4 _210_:5 _210_:6 8.4 5 _210_:6 _210_:2 0.005 -6 _511_/ZN _210_:1 9.085 -7 _514_/A2 _210_:3 4.765 -8 _665_/A2 _210_:4 1.685 +6 _511_:ZN _210_:1 9.085 +7 _514_:A2 _210_:3 4.765 +8 _665_:A2 _210_:4 1.685 *END *D_NET _211_ 20.36 *CONN -*I _512_/ZN O *D XNOR2_X1 -*I _513_/A I *D INV_X1 -*I _652_/B I *D XNOR2_X1 +*I _512_:ZN O *D XNOR2_X1 +*I _513_:A I *D INV_X1 +*I _652_:B I *D XNOR2_X1 *CAP 1 _211_:1 4.2 2 _211_:2 3.53 @@ -6525,17 +6525,17 @@ resp_val O 3 _211_:4 _211_:5 8.4 4 _211_:5 _211_:1 0.005 5 _211_:6 _211_:1 8.4 -6 _512_/ZN _211_:2 5.725 -7 _513_/A _211_:3 4.045 -8 _652_/B _211_:6 5.765 +6 _512_:ZN _211_:2 5.725 +7 _513_:A _211_:3 4.045 +8 _652_:B _211_:6 5.765 *END *D_NET _212_ 25.31 *CONN -*I _513_/ZN O *D INV_X1 -*I _514_/A3 I *D NOR3_X1 -*I _657_/A2 I *D NOR2_X1 -*I _665_/A3 I *D OR3_X1 +*I _513_:ZN O *D INV_X1 +*I _514_:A3 I *D NOR3_X1 +*I _657_:A2 I *D NOR2_X1 +*I _665_:A3 I *D OR3_X1 *CAP 1 _212_:1 4.2 2 _212_:2 4.2 @@ -6553,18 +6553,18 @@ resp_val O 5 _212_:6 _212_:7 0.005 6 _212_:7 _212_:2 8.4 7 _212_:8 _212_:1 8.4 -8 _513_/ZN _212_:4 5.565 -9 _514_/A3 _212_:5 5.525 -10 _657_/A2 _212_:8 4.065 -11 _665_/A3 _212_:6 1.885 +8 _513_:ZN _212_:4 5.565 +9 _514_:A3 _212_:5 5.525 +10 _657_:A2 _212_:8 4.065 +11 _665_:A3 _212_:6 1.885 *END *D_NET _213_ 70.57 *CONN -*I _514_/ZN O *D NOR3_X1 -*I _515_/A2 I *D AND2_X1 -*I _527_/A2 I *D NAND2_X1 -*I _539_/A3 I *D NAND4_X1 +*I _514_:ZN O *D NOR3_X1 +*I _515_:A2 I *D AND2_X1 +*I _527_:A2 I *D NAND2_X1 +*I _539_:A3 I *D NAND4_X1 *CAP 1 _213_:1 0.945 2 _213_:2 2.1 @@ -6584,16 +6584,16 @@ resp_val O 6 _213_:7 _213_:8 0.005 7 _213_:8 _213_:5 25.2 8 _213_:9 _213_:4 58.8 -9 _514_/ZN _213_:9 5.925 -10 _515_/A2 _213_:5 8.405 -11 _527_/A2 _213_:1 3.785 -12 _539_/A3 _213_:6 5.445 +9 _514_:ZN _213_:9 5.925 +10 _515_:A2 _213_:5 8.405 +11 _527_:A2 _213_:1 3.785 +12 _539_:A3 _213_:6 5.445 *END *D_NET _214_ 12.47 *CONN -*I _515_/ZN O *D AND2_X1 -*I _516_/A2 I *D NAND2_X1 +*I _515_:ZN O *D AND2_X1 +*I _516_:A2 I *D NAND2_X1 *CAP 1 _214_:1 0.845 2 _214_:2 2.1 @@ -6605,14 +6605,14 @@ resp_val O 2 _214_:2 _214_:3 8.4 3 _214_:3 _214_:4 0.005 4 _214_:5 _214_:4 8.4 -5 _515_/ZN _214_:5 4.765 -6 _516_/A2 _214_:1 3.385 +5 _515_:ZN _214_:5 4.765 +6 _516_:A2 _214_:1 3.385 *END *D_NET _215_ 20.23 *CONN -*I _516_/ZN O *D NAND2_X1 -*I _530_/A2 I *D AND4_X1 +*I _516_:ZN O *D NAND2_X1 +*I _530_:A2 I *D AND4_X1 *CAP 1 _215_:1 5.05 2 _215_:2 4.2 @@ -6624,15 +6624,15 @@ resp_val O 2 _215_:2 _215_:3 0.005 3 _215_:3 _215_:4 16.8 4 _215_:4 _215_:5 0.005 -5 _516_/ZN _215_:5 3.465 -6 _530_/A2 _215_:1 3.405 +5 _516_:ZN _215_:5 3.465 +6 _530_:A2 _215_:1 3.405 *END *D_NET _216_ 15.78 *CONN -*I _517_/ZN O *D INV_X1 -*I _518_/A2 I *D AND3_X1 -*I _622_/A1 I *D NOR2_X1 +*I _517_:ZN O *D INV_X1 +*I _518_:A2 I *D AND3_X1 +*I _622_:A1 I *D NOR2_X1 *CAP 1 _216_:1 3.86 2 _216_:2 2.1 @@ -6644,15 +6644,15 @@ resp_val O 2 _216_:2 _216_:3 8.4 3 _216_:3 _216_:4 0.005 4 _216_:1 _216_:5 8.4 -5 _517_/ZN _216_:5 3.205 -6 _518_/A2 _216_:4 4.525 -7 _622_/A1 _216_:1 7.045 +5 _517_:ZN _216_:5 3.205 +6 _518_:A2 _216_:4 4.525 +7 _622_:A1 _216_:1 7.045 *END *D_NET _217_ 12.46 *CONN -*I _518_/ZN O *D AND3_X1 -*I _521_/B1 I *D OAI21_X1 +*I _518_:ZN O *D AND3_X1 +*I _521_:B1 I *D OAI21_X1 *CAP 1 _217_:1 0.305 2 _217_:2 2.1 @@ -6664,15 +6664,15 @@ resp_val O 2 _217_:2 _217_:3 8.4 3 _217_:3 _217_:4 0.005 4 _217_:5 _217_:4 8.4 -5 _518_/ZN _217_:1 1.225 -6 _521_/B1 _217_:5 6.905 +5 _518_:ZN _217_:1 1.225 +6 _521_:B1 _217_:5 6.905 *END *D_NET _218_ 22.36 *CONN -*I _519_/ZN O *D INV_X1 -*I _520_/A1 I *D AND2_X1 -*I _629_/A1 I *D NOR2_X1 +*I _519_:ZN O *D INV_X1 +*I _520_:A1 I *D AND2_X1 +*I _629_:A1 I *D NOR2_X1 *CAP 1 _218_:1 1.41 2 _218_:2 4.2 @@ -6688,15 +6688,15 @@ resp_val O 4 _218_:4 _218_:5 8.4 5 _218_:6 _218_:7 0.005 6 _218_:7 _218_:2 8.4 -7 _519_/ZN _218_:6 7.325 -8 _520_/A1 _218_:5 6.565 -9 _629_/A1 _218_:1 5.645 +7 _519_:ZN _218_:6 7.325 +8 _520_:A1 _218_:5 6.565 +9 _629_:A1 _218_:1 5.645 *END *D_NET _219_ 12.28 *CONN -*I _520_/ZN O *D AND2_X1 -*I _521_/B2 I *D OAI21_X1 +*I _520_:ZN O *D AND2_X1 +*I _521_:B2 I *D OAI21_X1 *CAP 1 _219_:1 2.64 2 _219_:2 2.1 @@ -6708,14 +6708,14 @@ resp_val O 2 _219_:2 _219_:3 0.005 3 _219_:3 _219_:4 8.4 4 _219_:4 _219_:5 0.005 -5 _520_/ZN _219_:1 2.165 -6 _521_/B2 _219_:5 5.605 +5 _520_:ZN _219_:1 2.165 +6 _521_:B2 _219_:5 5.605 *END *D_NET _220_ 26.26 *CONN -*I _521_/ZN O *D OAI21_X1 -*I _526_/A I *D OAI21_X1 +*I _521_:ZN O *D OAI21_X1 +*I _526_:A I *D OAI21_X1 *CAP 1 _220_:1 1.455 2 _220_:2 8.4 @@ -6727,16 +6727,16 @@ resp_val O 2 _220_:2 _220_:3 33.6 3 _220_:3 _220_:4 0.005 4 _220_:4 _220_:5 8.4 -5 _521_/ZN _220_:1 5.825 -6 _526_/A _220_:5 4.705 +5 _521_:ZN _220_:1 5.825 +6 _526_:A _220_:5 4.705 *END *D_NET _221_ 45.87 *CONN -*I _522_/ZN O *D INV_X1 -*I _523_/A1 I *D NOR2_X1 -*I _525_/A1 I *D AOI22_X1 -*I _646_/B1 I *D OAI21_X1 +*I _522_:ZN O *D INV_X1 +*I _523_:A1 I *D NOR2_X1 +*I _525_:A1 I *D AOI22_X1 +*I _646_:B1 I *D OAI21_X1 *CAP 1 _221_:1 3.555 2 _221_:2 2.1 @@ -6754,17 +6754,17 @@ resp_val O 5 _221_:4 _221_:6 50.4 6 _221_:6 _221_:7 0.005 7 _221_:8 _221_:7 8.4 -8 _522_/ZN _221_:8 7.245 -9 _523_/A1 _221_:5 1.665 -10 _525_/A1 _221_:1 5.825 -11 _646_/B1 _221_:7 1.425 +8 _522_:ZN _221_:8 7.245 +9 _523_:A1 _221_:5 1.665 +10 _525_:A1 _221_:1 5.825 +11 _646_:B1 _221_:7 1.425 *END *D_NET _222_ 17.09 *CONN -*I _523_/ZN O *D NOR2_X1 -*I _526_/B1 I *D OAI21_X1 -*I _650_/A I *D AOI21_X1 +*I _523_:ZN O *D NOR2_X1 +*I _526_:B1 I *D OAI21_X1 +*I _650_:A I *D AOI21_X1 *CAP 1 _222_:1 4.275 2 _222_:2 5.565 @@ -6776,16 +6776,16 @@ resp_val O 2 _222_:3 _222_:4 0.005 3 _222_:4 _222_:5 8.4 4 _222_:5 _222_:1 0.005 -5 _523_/ZN _222_:1 0.305 -6 _526_/B1 _222_:2 5.465 -7 _650_/A _222_:3 3.225 +5 _523_:ZN _222_:1 0.305 +6 _526_:B1 _222_:2 5.465 +7 _650_:A _222_:3 3.225 *END *D_NET _223_ 13.82 *CONN -*I _524_/ZN O *D INV_X1 -*I _525_/B1 I *D AOI22_X1 -*I _640_/A1 I *D NOR2_X1 +*I _524_:ZN O *D INV_X1 +*I _525_:B1 I *D AOI22_X1 +*I _640_:A1 I *D NOR2_X1 *CAP 1 _223_:1 2.925 2 _223_:2 2.1 @@ -6795,15 +6795,15 @@ resp_val O 1 _223_:1 _223_:2 0.005 2 _223_:2 _223_:3 8.4 3 _223_:3 _223_:4 0.005 -4 _524_/ZN _223_:1 7.685 -5 _525_/B1 _223_:4 7.545 -6 _640_/A1 _223_:1 4.025 +4 _524_:ZN _223_:1 7.685 +5 _525_:B1 _223_:4 7.545 +6 _640_:A1 _223_:1 4.025 *END *D_NET _224_ 20.82 *CONN -*I _525_/ZN O *D AOI22_X1 -*I _526_/B2 I *D OAI21_X1 +*I _525_:ZN O *D AOI22_X1 +*I _526_:B2 I *D OAI21_X1 *CAP 1 _224_:1 4.52 2 _224_:2 2.1 @@ -6817,41 +6817,41 @@ resp_val O 3 _224_:3 _224_:4 8.4 4 _224_:4 _224_:5 0.005 5 _224_:5 _224_:6 8.4 -6 _525_/ZN _224_:1 9.685 -7 _526_/B2 _224_:6 6.765 +6 _525_:ZN _224_:1 9.685 +7 _526_:B2 _224_:6 6.765 *END *D_NET _225_ 13.39 *CONN -*I _526_/ZN O *D OAI21_X1 -*I _527_/A1 I *D NAND2_X1 +*I _526_:ZN O *D OAI21_X1 +*I _527_:A1 I *D NAND2_X1 *CAP 1 _225_:1 5.565 2 _225_:2 5.33 *RES 1 _225_:1 _225_:2 16.8 -2 _526_/ZN _225_:1 5.465 -3 _527_/A1 _225_:2 4.525 +2 _526_:ZN _225_:1 5.465 +3 _527_:A1 _225_:2 4.525 *END *D_NET _226_ 7.93 *CONN -*I _527_/ZN O *D NAND2_X1 -*I _530_/A3 I *D AND4_X1 +*I _527_:ZN O *D NAND2_X1 +*I _530_:A3 I *D AND4_X1 *CAP 1 _226_:1 2.925 2 _226_:2 3.14 *RES 1 _226_:1 _226_:2 8.4 -2 _527_/ZN _226_:1 3.305 -3 _530_/A3 _226_:2 4.165 +2 _527_:ZN _226_:1 3.305 +3 _530_:A3 _226_:2 4.165 *END *D_NET _227_ 23.7 *CONN -*I _528_/ZN O *D INV_X1 -*I _529_/A2 I *D NAND3_X1 -*I _675_/A1 I *D NOR2_X1 +*I _528_:ZN O *D INV_X1 +*I _529_:A2 I *D NAND3_X1 +*I _675_:A1 I *D NOR2_X1 *CAP 1 _227_:1 0.8 2 _227_:2 4.2 @@ -6869,15 +6869,15 @@ resp_val O 5 _227_:6 _227_:7 8.4 6 _227_:7 _227_:8 0.005 7 _227_:8 _227_:2 8.4 -8 _528_/ZN _227_:6 3.605 -9 _529_/A2 _227_:5 7.005 -10 _675_/A1 _227_:1 3.205 +8 _528_:ZN _227_:6 3.605 +9 _529_:A2 _227_:5 7.005 +10 _675_:A1 _227_:1 3.205 *END *D_NET _228_ 38.43 *CONN -*I _529_/ZN O *D NAND3_X1 -*I _530_/A4 I *D AND4_X1 +*I _529_:ZN O *D NAND3_X1 +*I _530_:A4 I *D AND4_X1 *CAP 1 _228_:1 7.485 2 _228_:2 6.3 @@ -6891,15 +6891,15 @@ resp_val O 3 _228_:3 _228_:4 8.4 4 _228_:4 _228_:5 0.005 5 _228_:5 _228_:6 33.6 -6 _529_/ZN _228_:1 4.745 -7 _530_/A4 _228_:6 4.925 +6 _529_:ZN _228_:1 4.745 +7 _530_:A4 _228_:6 4.925 *END *D_NET _229_ 32.12 *CONN -*I _530_/ZN O *D AND4_X1 -*I _537_/A1 I *D NAND4_X1 -*I _543_/B1 I *D AOI21_X1 +*I _530_:ZN O *D AND4_X1 +*I _537_:A1 I *D NAND4_X1 +*I _543_:B1 I *D AOI21_X1 *CAP 1 _229_:1 6.3 2 _229_:2 4.2 @@ -6917,16 +6917,16 @@ resp_val O 5 _229_:6 _229_:7 0.005 6 _229_:7 _229_:2 8.4 7 _229_:8 _229_:1 25.2 -8 _530_/ZN _229_:8 4.245 -9 _537_/A1 _229_:5 2.745 -10 _543_/B1 _229_:6 6.865 +8 _530_:ZN _229_:8 4.245 +9 _537_:A1 _229_:5 2.745 +10 _543_:B1 _229_:6 6.865 *END *D_NET _230_ 29.58 *CONN -*I _531_/ZN O *D AND2_X1 -*I _537_/A3 I *D NAND4_X1 -*I _553_/A I *D INV_X1 +*I _531_:ZN O *D AND2_X1 +*I _537_:A3 I *D NAND4_X1 +*I _553_:A I *D INV_X1 *CAP 1 _230_:1 2.1 2 _230_:2 8.4 @@ -6942,16 +6942,16 @@ resp_val O 4 _230_:5 _230_:1 8.4 5 _230_:6 _230_:7 0.005 6 _230_:7 _230_:2 16.8 -7 _531_/ZN _230_:6 9.005 -8 _537_/A3 _230_:4 4.965 -9 _553_/A _230_:5 3.205 +7 _531_:ZN _230_:6 9.005 +8 _537_:A3 _230_:4 4.965 +9 _553_:A _230_:5 3.205 *END *D_NET _231_ 20.67 *CONN -*I _532_/ZN O *D INV_X1 -*I _533_/A1 I *D NOR2_X1 -*I _535_/A1 I *D AOI22_X1 +*I _532_:ZN O *D INV_X1 +*I _533_:A1 I *D NOR2_X1 +*I _535_:A1 I *D AOI22_X1 *CAP 1 _231_:1 4.07 2 _231_:2 4.2 @@ -6965,15 +6965,15 @@ resp_val O 3 _231_:4 _231_:5 0.005 4 _231_:5 _231_:6 8.4 5 _231_:6 _231_:2 0.005 -6 _532_/ZN _231_:1 7.885 -7 _533_/A1 _231_:3 5.005 -8 _535_/A1 _231_:4 3.265 +6 _532_:ZN _231_:1 7.885 +7 _533_:A1 _231_:3 5.005 +8 _535_:A1 _231_:4 3.265 *END *D_NET _232_ 10.47 *CONN -*I _533_/ZN O *D NOR2_X1 -*I _536_/A2 I *D OR3_X1 +*I _533_:ZN O *D NOR2_X1 +*I _536_:A2 I *D OR3_X1 *CAP 1 _232_:1 1.375 2 _232_:2 2.1 @@ -6983,15 +6983,15 @@ resp_val O 1 _232_:1 _232_:2 0.005 2 _232_:2 _232_:3 8.4 3 _232_:3 _232_:4 0.005 -4 _533_/ZN _232_:4 7.045 -5 _536_/A2 _232_:1 5.505 +4 _533_:ZN _232_:4 7.045 +5 _536_:A2 _232_:1 5.505 *END *D_NET _233_ 13.02 *CONN -*I _534_/ZN O *D INV_X1 -*I _535_/B1 I *D AOI22_X1 -*I _658_/A1 I *D NOR2_X1 +*I _534_:ZN O *D INV_X1 +*I _535_:B1 I *D AOI22_X1 +*I _658_:A1 I *D NOR2_X1 *CAP 1 _233_:1 3.31 2 _233_:2 2.55 @@ -7003,29 +7003,29 @@ resp_val O 2 _233_:2 _233_:3 0.005 3 _233_:3 _233_:4 8.4 4 _233_:4 _233_:5 0.005 -5 _534_/ZN _233_:5 2.605 -6 _535_/B1 _233_:2 1.805 -7 _658_/A1 _233_:1 4.845 +5 _534_:ZN _233_:5 2.605 +6 _535_:B1 _233_:2 1.805 +7 _658_:A1 _233_:1 4.845 *END *D_NET _234_ 7.66 *CONN -*I _535_/ZN O *D AOI22_X1 -*I _536_/A3 I *D OR3_X1 +*I _535_:ZN O *D AOI22_X1 +*I _536_:A3 I *D OR3_X1 *CAP 1 _234_:1 2.645 2 _234_:2 3.285 *RES 1 _234_:1 _234_:2 8.4 -2 _535_/ZN _234_:1 2.185 -3 _536_/A3 _234_:2 4.745 +2 _535_:ZN _234_:1 2.185 +3 _536_:A3 _234_:2 4.745 *END *D_NET _235_ 62.61 *CONN -*I _536_/ZN O *D OR3_X1 -*I _537_/A4 I *D NAND4_X1 -*I _543_/B2 I *D AOI21_X1 +*I _536_:ZN O *D OR3_X1 +*I _537_:A4 I *D NAND4_X1 +*I _543_:B2 I *D AOI21_X1 *CAP 1 _235_:1 23.1 2 _235_:2 3.53 @@ -7039,15 +7039,15 @@ resp_val O 3 _235_:4 _235_:5 16.8 4 _235_:5 _235_:1 0.005 5 _235_:6 _235_:1 84 -6 _536_/ZN _235_:6 4.805 -7 _537_/A4 _235_:2 5.725 -8 _543_/B2 _235_:3 5.505 +6 _536_:ZN _235_:6 4.805 +7 _537_:A4 _235_:2 5.725 +8 _543_:B2 _235_:3 5.505 *END *D_NET _236_ 68.14 *CONN -*I _537_/ZN O *D NAND4_X1 -*I _547_/B I *D OAI211_X1 +*I _537_:ZN O *D NAND4_X1 +*I _547_:B I *D OAI211_X1 *CAP 1 _236_:1 11.565 2 _236_:2 10.5 @@ -7059,15 +7059,15 @@ resp_val O 2 _236_:2 _236_:3 0.005 3 _236_:3 _236_:4 84 4 _236_:4 _236_:5 0.005 -5 _537_/ZN _236_:1 4.265 -6 _547_/B _236_:5 6.025 +5 _537_:ZN _236_:1 4.265 +6 _547_:B _236_:5 6.025 *END *D_NET _237_ 23.93 *CONN -*I _538_/ZN O *D AND2_X1 -*I _539_/A2 I *D NAND4_X1 -*I _611_/A2 I *D NAND2_X1 +*I _538_:ZN O *D AND2_X1 +*I _539_:A2 I *D NAND4_X1 +*I _611_:A2 I *D NAND2_X1 *CAP 1 _237_:1 1.17 2 _237_:2 4.2 @@ -7083,15 +7083,15 @@ resp_val O 4 _237_:3 _237_:5 8.4 5 _237_:5 _237_:6 0.005 6 _237_:7 _237_:6 8.4 -7 _538_/ZN _237_:4 4.565 -8 _539_/A2 _237_:1 4.685 -9 _611_/A2 _237_:7 5.025 +7 _538_:ZN _237_:4 4.565 +8 _539_:A2 _237_:1 4.685 +9 _611_:A2 _237_:7 5.025 *END *D_NET _238_ 11.2 *CONN -*I _539_/ZN O *D NAND4_X1 -*I _542_/A1 I *D NOR3_X1 +*I _539_:ZN O *D NAND4_X1 +*I _542_:A1 I *D NOR3_X1 *CAP 1 _238_:1 1.535 2 _238_:2 2.1 @@ -7101,16 +7101,16 @@ resp_val O 1 _238_:1 _238_:2 0.005 2 _238_:2 _238_:3 8.4 3 _238_:3 _238_:4 0.005 -4 _539_/ZN _238_:4 7.865 -5 _542_/A1 _238_:1 6.145 +4 _539_:ZN _238_:4 7.865 +5 _542_:A1 _238_:1 6.145 *END *D_NET _239_ 23.88 *CONN -*I _540_/ZN O *D XNOR2_X2 -*I _541_/A I *D INV_X1 -*I _557_/A I *D XOR2_X1 -*I _562_/B1 I *D AOI21_X1 +*I _540_:ZN O *D XNOR2_X2 +*I _541_:A I *D INV_X1 +*I _557_:A I *D XOR2_X1 +*I _562_:B1 I *D AOI21_X1 *CAP 1 _239_:1 4.825 2 _239_:2 7.495 @@ -7124,29 +7124,29 @@ resp_val O 3 _239_:4 _239_:5 0.005 4 _239_:5 _239_:6 8.4 5 _239_:6 _239_:2 0.005 -6 _540_/ZN _239_:4 2.185 -7 _541_/A _239_:1 2.505 -8 _557_/A _239_:3 4.705 -9 _562_/B1 _239_:2 4.785 +6 _540_:ZN _239_:4 2.185 +7 _541_:A _239_:1 2.505 +8 _557_:A _239_:3 4.705 +9 _562_:B1 _239_:2 4.785 *END *D_NET _240_ 14.57 *CONN -*I _541_/ZN O *D INV_X1 -*I _542_/A3 I *D NOR3_X1 +*I _541_:ZN O *D INV_X1 +*I _542_:A3 I *D NOR3_X1 *CAP 1 _240_:1 6.115 2 _240_:2 5.37 *RES 1 _240_:1 _240_:2 16.8 -2 _541_/ZN _240_:2 4.685 -3 _542_/A3 _240_:1 7.665 +2 _541_:ZN _240_:2 4.685 +3 _542_:A3 _240_:1 7.665 *END *D_NET _241_ 10.85 *CONN -*I _542_/ZN O *D NOR3_X1 -*I _543_/A I *D AOI21_X1 +*I _542_:ZN O *D NOR3_X1 +*I _543_:A I *D AOI21_X1 *CAP 1 _241_:1 1.96 2 _241_:2 2.1 @@ -7156,15 +7156,15 @@ resp_val O 1 _241_:1 _241_:2 0.005 2 _241_:2 _241_:3 8.4 3 _241_:3 _241_:4 0.005 -4 _542_/ZN _241_:4 5.465 -5 _543_/A _241_:1 7.845 +4 _542_:ZN _241_:4 5.465 +5 _543_:A _241_:1 7.845 *END *D_NET _242_ 14.33 *CONN -*I _543_/ZN O *D AOI21_X1 -*I _544_/A1 I *D NAND2_X1 -*I _554_/A1 I *D NOR2_X2 +*I _543_:ZN O *D AOI21_X1 +*I _544_:A1 I *D NAND2_X1 +*I _554_:A1 I *D NOR2_X2 *CAP 1 _242_:1 1.225 2 _242_:2 2.1 @@ -7176,16 +7176,16 @@ resp_val O 2 _242_:2 _242_:3 8.4 3 _242_:3 _242_:4 0.005 4 _242_:5 _242_:4 8.4 -5 _543_/ZN _242_:4 5.645 -6 _544_/A1 _242_:1 4.905 -7 _554_/A1 _242_:5 1.325 +5 _543_:ZN _242_:4 5.645 +6 _544_:A1 _242_:1 4.905 +7 _554_:A1 _242_:5 1.325 *END *D_NET _243_ 17.33 *CONN -*I _544_/ZN O *D NAND2_X1 -*I _545_/A1 I *D OR2_X2 -*I _684_/A1 I *D NAND2_X2 +*I _544_:ZN O *D NAND2_X1 +*I _545_:A1 I *D OR2_X2 +*I _684_:A1 I *D NAND2_X2 *CAP 1 _243_:1 4.655 2 _243_:2 2.1 @@ -7197,21 +7197,21 @@ resp_val O 2 _243_:2 _243_:3 0.005 3 _243_:3 _243_:4 8.4 4 _243_:4 _243_:5 0.005 -5 _544_/ZN _243_:5 7.645 -6 _545_/A1 _243_:1 7.045 -7 _684_/A1 _243_:1 3.185 +5 _544_:ZN _243_:5 7.645 +6 _545_:A1 _243_:1 7.045 +7 _684_:A1 _243_:1 3.185 *END *D_NET _244_ 164.97 *CONN -*I _545_/ZN O *D OR2_X2 -*I _546_/A I *D BUF_X2 -*I _617_/C1 I *D OAI211_X1 -*I _626_/C1 I *D OAI211_X1 -*I _635_/C1 I *D OAI211_X1 -*I _655_/C1 I *D OAI211_X1 -*I _663_/C2 I *D OAI211_X1 -*I _673_/C2 I *D OAI211_X1 +*I _545_:ZN O *D OR2_X2 +*I _546_:A I *D BUF_X2 +*I _617_:C1 I *D OAI211_X1 +*I _626_:C1 I *D OAI211_X1 +*I _635_:C1 I *D OAI211_X1 +*I _655_:C1 I *D OAI211_X1 +*I _663_:C2 I *D OAI211_X1 +*I _673_:C2 I *D OAI211_X1 *CAP 1 _244_:1 2.435 2 _244_:2 14.7 @@ -7253,29 +7253,29 @@ resp_val O 17 _244_:19 _244_:16 25.2 18 _244_:19 _244_:20 0.005 19 _244_:20 _244_:18 8.4 -20 _545_/ZN _244_:1 9.745 -21 _546_/A _244_:4 8.365 -22 _617_/C1 _244_:11 5.965 -23 _626_/C1 _244_:13 3.525 -24 _635_/C1 _244_:16 4.985 -25 _655_/C1 _244_:9 4.185 -26 _663_/C2 _244_:10 1.925 -27 _673_/C2 _244_:17 5.685 +20 _545_:ZN _244_:1 9.745 +21 _546_:A _244_:4 8.365 +22 _617_:C1 _244_:11 5.965 +23 _626_:C1 _244_:13 3.525 +24 _635_:C1 _244_:16 4.985 +25 _655_:C1 _244_:9 4.185 +26 _663_:C2 _244_:10 1.925 +27 _673_:C2 _244_:17 5.685 *END *D_NET _245_ 203.72 *CONN -*I _546_/Z O *D BUF_X2 -*I _547_/C1 I *D OAI211_X1 -*I _559_/C1 I *D OAI211_X1 -*I _565_/C1 I *D OAI211_X1 -*I _574_/C1 I *D OAI211_X1 -*I _583_/C1 I *D OAI211_X1 -*I _591_/C1 I *D OAI211_X1 -*I _599_/C1 I *D OAI211_X1 -*I _608_/C1 I *D OAI211_X1 -*I _638_/B1 I *D OAI21_X1 -*I _680_/B1 I *D OAI21_X1 +*I _546_:Z O *D BUF_X2 +*I _547_:C1 I *D OAI211_X1 +*I _559_:C1 I *D OAI211_X1 +*I _565_:C1 I *D OAI211_X1 +*I _574_:C1 I *D OAI211_X1 +*I _583_:C1 I *D OAI211_X1 +*I _591_:C1 I *D OAI211_X1 +*I _599_:C1 I *D OAI211_X1 +*I _608_:C1 I *D OAI211_X1 +*I _638_:B1 I *D OAI21_X1 +*I _680_:B1 I *D OAI21_X1 *CAP 1 _245_:1 6.3 2 _245_:2 7.555 @@ -7331,23 +7331,23 @@ resp_val O 24 _245_:26 _245_:27 16.8 25 _245_:27 _245_:22 0.005 26 _245_:25 _245_:14 33.6 -27 _546_/Z _245_:25 8.945 -28 _547_/C1 _245_:2 5.025 -29 _559_/C1 _245_:7 4.905 -30 _565_/C1 _245_:8 6.305 -31 _574_/C1 _245_:13 2.965 -32 _583_/C1 _245_:12 1.625 -33 _591_/C1 _245_:17 5.925 -34 _599_/C1 _245_:9 7.965 -35 _608_/C1 _245_:3 0.705 -36 _638_/B1 _245_:18 8.065 -37 _680_/B1 _245_:22 2.265 +27 _546_:Z _245_:25 8.945 +28 _547_:C1 _245_:2 5.025 +29 _559_:C1 _245_:7 4.905 +30 _565_:C1 _245_:8 6.305 +31 _574_:C1 _245_:13 2.965 +32 _583_:C1 _245_:12 1.625 +33 _591_:C1 _245_:17 5.925 +34 _599_:C1 _245_:9 7.965 +35 _608_:C1 _245_:3 0.705 +36 _638_:B1 _245_:18 8.065 +37 _680_:B1 _245_:22 2.265 *END *D_NET _246_ 15.09 *CONN -*I _547_/ZN O *D OAI211_X1 -*I _551_/B I *D MUX2_X1 +*I _547_:ZN O *D OAI211_X1 +*I _551_:B I *D MUX2_X1 *CAP 1 _246_:1 3.445 2 _246_:2 2.1 @@ -7359,14 +7359,14 @@ resp_val O 2 _246_:2 _246_:3 0.005 3 _246_:3 _246_:4 8.4 4 _246_:4 _246_:5 0.005 -5 _547_/ZN _246_:1 5.385 -6 _551_/B _246_:5 8.005 +5 _547_:ZN _246_:1 5.385 +6 _551_:B _246_:5 8.005 *END *D_NET _247_ 7.65 *CONN -*I _548_/ZN O *D OR2_X1 -*I _549_/A I *D BUF_X2 +*I _548_:ZN O *D OR2_X1 +*I _549_:A I *D BUF_X2 *CAP 1 _247_:1 1.095 2 _247_:2 2.1 @@ -7376,22 +7376,22 @@ resp_val O 1 _247_:1 _247_:2 0.005 2 _247_:2 _247_:3 8.4 3 _247_:3 _247_:4 0.005 -4 _548_/ZN _247_:4 2.525 -5 _549_/A _247_:1 4.385 +4 _548_:ZN _247_:4 2.525 +5 _549_:A _247_:1 4.385 *END *D_NET _248_ 275.06 *CONN -*I _549_/Z O *D BUF_X2 -*I _550_/A I *D BUF_X2 -*I _600_/S I *D MUX2_X1 -*I _609_/S I *D MUX2_X1 -*I _618_/S I *D MUX2_X1 -*I _627_/S I *D MUX2_X1 -*I _636_/S I *D MUX2_X1 -*I _656_/S I *D MUX2_X1 -*I _664_/S I *D MUX2_X1 -*I _674_/S I *D MUX2_X1 +*I _549_:Z O *D BUF_X2 +*I _550_:A I *D BUF_X2 +*I _600_:S I *D MUX2_X1 +*I _609_:S I *D MUX2_X1 +*I _618_:S I *D MUX2_X1 +*I _627_:S I *D MUX2_X1 +*I _636_:S I *D MUX2_X1 +*I _656_:S I *D MUX2_X1 +*I _664_:S I *D MUX2_X1 +*I _674_:S I *D MUX2_X1 *CAP 1 _248_:1 0.765 2 _248_:2 4.2 @@ -7457,31 +7457,31 @@ resp_val O 29 _248_:30 _248_:31 8.4 30 _248_:31 _248_:32 0.005 31 _248_:26 _248_:32 42 -32 _549_/Z _248_:14 2.745 -33 _550_/A _248_:1 3.065 -34 _600_/S _248_:5 5.305 -35 _609_/S _248_:13 2.105 -36 _618_/S _248_:17 5.185 -37 _627_/S _248_:21 2.145 -38 _636_/S _248_:25 5.505 -39 _656_/S _248_:10 8.225 -40 _664_/S _248_:6 7.545 -41 _674_/S _248_:26 4.345 +32 _549_:Z _248_:14 2.745 +33 _550_:A _248_:1 3.065 +34 _600_:S _248_:5 5.305 +35 _609_:S _248_:13 2.105 +36 _618_:S _248_:17 5.185 +37 _627_:S _248_:21 2.145 +38 _636_:S _248_:25 5.505 +39 _656_:S _248_:10 8.225 +40 _664_:S _248_:6 7.545 +41 _674_:S _248_:26 4.345 *END *D_NET _249_ 205.07 *CONN -*I _550_/Z O *D BUF_X2 -*I _551_/S I *D MUX2_X1 -*I _560_/S I *D MUX2_X1 -*I _566_/S I *D MUX2_X1 -*I _575_/S I *D MUX2_X1 -*I _584_/S I *D MUX2_X1 -*I _592_/S I *D MUX2_X1 -*I _645_/A I *D OAI21_X1 -*I _646_/B2 I *D OAI21_X1 -*I _681_/A I *D OAI21_X1 -*I _682_/B2 I *D OAI21_X1 +*I _550_:Z O *D BUF_X2 +*I _551_:S I *D MUX2_X1 +*I _560_:S I *D MUX2_X1 +*I _566_:S I *D MUX2_X1 +*I _575_:S I *D MUX2_X1 +*I _584_:S I *D MUX2_X1 +*I _592_:S I *D MUX2_X1 +*I _645_:A I *D OAI21_X1 +*I _646_:B2 I *D OAI21_X1 +*I _681_:A I *D OAI21_X1 +*I _682_:B2 I *D OAI21_X1 *CAP 1 _249_:1 4.875 2 _249_:2 4.2 @@ -7539,23 +7539,23 @@ resp_val O 25 _249_:15 _249_:27 25.2 26 _249_:27 _249_:28 0.005 27 _249_:11 _249_:28 8.4 -28 _550_/Z _249_:22 6.185 -29 _551_/S _249_:17 5.505 -30 _560_/S _249_:1 2.705 -31 _566_/S _249_:5 5.025 -32 _575_/S _249_:19 7.345 -33 _584_/S _249_:25 5.945 -34 _592_/S _249_:9 3.025 -35 _645_/A _249_:11 5.165 -36 _646_/B2 _249_:10 2.685 -37 _681_/A _249_:16 1.325 -38 _682_/B2 _249_:12 4.085 +28 _550_:Z _249_:22 6.185 +29 _551_:S _249_:17 5.505 +30 _560_:S _249_:1 2.705 +31 _566_:S _249_:5 5.025 +32 _575_:S _249_:19 7.345 +33 _584_:S _249_:25 5.945 +34 _592_:S _249_:9 3.025 +35 _645_:A _249_:11 5.165 +36 _646_:B2 _249_:10 2.685 +37 _681_:A _249_:16 1.325 +38 _682_:B2 _249_:12 4.085 *END *D_NET _250_ 38.79 *CONN -*I _552_/ZN O *D OAI21_X1 -*I _559_/A I *D OAI211_X1 +*I _552_:ZN O *D OAI21_X1 +*I _559_:A I *D OAI211_X1 *CAP 1 _250_:1 12.6 2 _250_:2 13.65 @@ -7567,32 +7567,32 @@ resp_val O 2 _250_:1 _250_:3 0.005 3 _250_:3 _250_:4 16.8 4 _250_:4 _250_:5 0.005 -5 _552_/ZN _250_:5 6.185 -6 _559_/A _250_:2 4.205 +5 _552_:ZN _250_:5 6.185 +6 _559_:A _250_:2 4.205 *END *D_NET _251_ 7.92 *CONN -*I _553_/ZN O *D INV_X1 -*I _554_/A2 I *D NOR2_X2 +*I _553_:ZN O *D INV_X1 +*I _554_:A2 I *D NOR2_X2 *CAP 1 _251_:1 3.28 2 _251_:2 2.78 *RES 1 _251_:2 _251_:1 8.4 -2 _553_/ZN _251_:1 4.725 -3 _554_/A2 _251_:2 2.725 +2 _553_:ZN _251_:1 4.725 +3 _554_:A2 _251_:2 2.725 *END *D_NET _252_ 132.81 *CONN -*I _554_/ZN O *D NOR2_X2 -*I _555_/A I *D CLKBUF_X2 -*I _625_/A2 I *D NAND2_X1 -*I _634_/A1 I *D NAND2_X1 -*I _653_/A2 I *D NAND2_X1 -*I _661_/A2 I *D NAND2_X1 -*I _671_/A2 I *D NAND2_X1 +*I _554_:ZN O *D NOR2_X2 +*I _555_:A I *D CLKBUF_X2 +*I _625_:A2 I *D NAND2_X1 +*I _634_:A1 I *D NAND2_X1 +*I _653_:A2 I *D NAND2_X1 +*I _661_:A2 I *D NAND2_X1 +*I _671_:A2 I *D NAND2_X1 *CAP 1 _252_:1 1.045 2 _252_:2 4.2 @@ -7634,28 +7634,28 @@ resp_val O 17 _252_:20 _252_:6 33.6 18 _252_:19 _252_:4 50.4 19 _252_:4 _252_:16 25.2 -20 _554_/ZN _252_:15 2.925 -21 _555_/A _252_:11 2.265 -22 _625_/A2 _252_:16 4.625 -23 _634_/A1 _252_:1 4.185 -24 _653_/A2 _252_:9 7.645 -25 _661_/A2 _252_:10 5.305 -26 _671_/A2 _252_:19 3.505 +20 _554_:ZN _252_:15 2.925 +21 _555_:A _252_:11 2.265 +22 _625_:A2 _252_:16 4.625 +23 _634_:A1 _252_:1 4.185 +24 _653_:A2 _252_:9 7.645 +25 _661_:A2 _252_:10 5.305 +26 _671_:A2 _252_:19 3.505 *END *D_NET _253_ 226.88 *CONN -*I _555_/Z O *D CLKBUF_X2 -*I _558_/A1 I *D NAND2_X1 -*I _564_/A1 I *D NAND2_X1 -*I _573_/A1 I *D NAND2_X1 -*I _582_/A1 I *D NAND2_X1 -*I _590_/A1 I *D NAND2_X1 -*I _598_/A1 I *D NAND2_X1 -*I _607_/A1 I *D NAND2_X1 -*I _616_/A1 I *D NAND2_X1 -*I _644_/A2 I *D AND2_X1 -*I _678_/A2 I *D AND2_X1 +*I _555_:Z O *D CLKBUF_X2 +*I _558_:A1 I *D NAND2_X1 +*I _564_:A1 I *D NAND2_X1 +*I _573_:A1 I *D NAND2_X1 +*I _582_:A1 I *D NAND2_X1 +*I _590_:A1 I *D NAND2_X1 +*I _598_:A1 I *D NAND2_X1 +*I _607_:A1 I *D NAND2_X1 +*I _616_:A1 I *D NAND2_X1 +*I _644_:A2 I *D AND2_X1 +*I _678_:A2 I *D AND2_X1 *CAP 1 _253_:1 0.72 2 _253_:2 10.5 @@ -7717,24 +7717,24 @@ resp_val O 27 _253_:29 _253_:30 0.005 28 _253_:30 _253_:24 8.4 29 _253_:27 _253_:17 33.6 -30 _555_/Z _253_:14 4.905 -31 _558_/A1 _253_:18 6.265 -32 _564_/A1 _253_:21 3.565 -33 _573_/A1 _253_:23 5.065 -34 _582_/A1 _253_:4 1.285 -35 _590_/A1 _253_:9 6.165 -36 _598_/A1 _253_:1 2.885 -37 _607_/A1 _253_:5 6.485 -38 _616_/A1 _253_:10 1.805 -39 _644_/A2 _253_:24 6.725 -40 _678_/A2 _253_:27 5.465 +30 _555_:Z _253_:14 4.905 +31 _558_:A1 _253_:18 6.265 +32 _564_:A1 _253_:21 3.565 +33 _573_:A1 _253_:23 5.065 +34 _582_:A1 _253_:4 1.285 +35 _590_:A1 _253_:9 6.165 +36 _598_:A1 _253_:1 2.885 +37 _607_:A1 _253_:5 6.485 +38 _616_:A1 _253_:10 1.805 +39 _644_:A2 _253_:24 6.725 +40 _678_:A2 _253_:27 5.465 *END *D_NET _254_ 13.98 *CONN -*I _556_/ZN O *D NAND2_X1 -*I _557_/B I *D XOR2_X1 -*I _562_/B2 I *D AOI21_X1 +*I _556_:ZN O *D NAND2_X1 +*I _557_:B I *D XOR2_X1 +*I _562_:B2 I *D AOI21_X1 *CAP 1 _254_:1 3.635 2 _254_:2 2.485 @@ -7746,15 +7746,15 @@ resp_val O 2 _254_:2 _254_:3 0.005 3 _254_:3 _254_:4 8.4 4 _254_:4 _254_:5 0.005 -5 _556_/ZN _254_:5 3.485 -6 _557_/B _254_:2 1.545 -7 _562_/B2 _254_:1 6.145 +5 _556_:ZN _254_:5 3.485 +6 _557_:B _254_:2 1.545 +7 _562_:B2 _254_:1 6.145 *END *D_NET _255_ 14.57 *CONN -*I _558_/ZN O *D NAND2_X1 -*I _559_/B I *D OAI211_X1 +*I _558_:ZN O *D NAND2_X1 +*I _559_:B I *D OAI211_X1 *CAP 1 _255_:1 2.25 2 _255_:2 2.1 @@ -7766,14 +7766,14 @@ resp_val O 2 _255_:2 _255_:3 8.4 3 _255_:3 _255_:4 0.005 4 _255_:5 _255_:4 8.4 -5 _558_/ZN _255_:1 9.005 -6 _559_/B _255_:5 3.345 +5 _558_:ZN _255_:1 9.005 +6 _559_:B _255_:5 3.345 *END *D_NET _256_ 13.66 *CONN -*I _559_/ZN O *D OAI211_X1 -*I _560_/B I *D MUX2_X1 +*I _559_:ZN O *D OAI211_X1 +*I _560_:B I *D MUX2_X1 *CAP 1 _256_:1 1.015 2 _256_:2 2.1 @@ -7785,14 +7785,14 @@ resp_val O 2 _256_:2 _256_:3 8.4 3 _256_:3 _256_:4 0.005 4 _256_:5 _256_:4 8.4 -5 _559_/ZN _256_:5 6.465 -6 _560_/B _256_:1 4.065 +5 _559_:ZN _256_:5 6.465 +6 _560_:B _256_:1 4.065 *END *D_NET _257_ 23.93 *CONN -*I _561_/ZN O *D OAI21_X1 -*I _565_/A I *D OAI211_X1 +*I _561_:ZN O *D OAI21_X1 +*I _565_:A I *D OAI211_X1 *CAP 1 _257_:1 4.265 2 _257_:2 2.1 @@ -7804,15 +7804,15 @@ resp_val O 2 _257_:2 _257_:3 0.005 3 _257_:3 _257_:4 25.2 4 _257_:4 _257_:5 0.005 -5 _561_/ZN _257_:1 8.665 -6 _565_/A _257_:5 5.605 +5 _561_:ZN _257_:1 8.665 +6 _565_:A _257_:5 5.605 *END *D_NET _258_ 28.67 *CONN -*I _562_/ZN O *D AOI21_X1 -*I _563_/A I *D XNOR2_X1 -*I _568_/A I *D INV_X1 +*I _562_:ZN O *D AOI21_X1 +*I _563_:A I *D XNOR2_X1 +*I _568_:A I *D INV_X1 *CAP 1 _258_:1 4.2 2 _258_:2 5.655 @@ -7830,40 +7830,40 @@ resp_val O 5 _258_:6 _258_:7 8.4 6 _258_:7 _258_:8 0.005 7 _258_:8 _258_:3 8.4 -8 _562_/ZN _258_:6 4.645 -9 _563_/A _258_:2 5.825 -10 _568_/A _258_:5 4.885 +8 _562_:ZN _258_:6 4.645 +9 _563_:A _258_:2 5.825 +10 _568_:A _258_:5 4.885 *END *D_NET _259_ 8.28 *CONN -*I _564_/ZN O *D NAND2_X1 -*I _565_/B I *D OAI211_X1 +*I _564_:ZN O *D NAND2_X1 +*I _565_:B I *D OAI211_X1 *CAP 1 _259_:1 2.955 2 _259_:2 3.285 *RES 1 _259_:1 _259_:2 8.4 -2 _564_/ZN _259_:1 3.425 -3 _565_/B _259_:2 4.745 +2 _564_:ZN _259_:1 3.425 +3 _565_:B _259_:2 4.745 *END *D_NET _260_ 5.89 *CONN -*I _565_/ZN O *D OAI211_X1 -*I _566_/B I *D MUX2_X1 +*I _565_:ZN O *D OAI211_X1 +*I _566_:B I *D MUX2_X1 *CAP 1 _260_:1 2.945 *RES 1 _260_:1 _260_:1 0.005 -2 _565_/ZN _260_:1 9.265 -3 _566_/B _260_:1 2.525 +2 _565_:ZN _260_:1 9.265 +3 _566_:B _260_:1 2.525 *END *D_NET _261_ 13.18 *CONN -*I _567_/ZN O *D OAI21_X1 -*I _574_/A I *D OAI211_X1 +*I _567_:ZN O *D OAI21_X1 +*I _574_:A I *D OAI211_X1 *CAP 1 _261_:1 2.665 2 _261_:2 2.1 @@ -7875,15 +7875,15 @@ resp_val O 2 _261_:2 _261_:3 0.005 3 _261_:3 _261_:4 8.4 4 _261_:4 _261_:5 0.005 -5 _567_/ZN _261_:5 7.305 -6 _574_/A _261_:1 2.265 +5 _567_:ZN _261_:5 7.305 +6 _574_:A _261_:1 2.265 *END *D_NET _262_ 28.5 *CONN -*I _568_/ZN O *D INV_X1 -*I _569_/A1 I *D AND2_X1 -*I _579_/A1 I *D NAND2_X1 +*I _568_:ZN O *D INV_X1 +*I _569_:A1 I *D AND2_X1 +*I _579_:A1 I *D NAND2_X1 *CAP 1 _262_:1 0.9 2 _262_:2 2.1 @@ -7897,15 +7897,15 @@ resp_val O 3 _262_:3 _262_:4 0.005 4 _262_:4 _262_:5 16.8 5 _262_:6 _262_:4 16.8 -6 _568_/ZN _262_:1 3.605 -7 _569_/A1 _262_:5 7.725 -8 _579_/A1 _262_:6 3.685 +6 _568_:ZN _262_:1 3.605 +7 _569_:A1 _262_:5 7.725 +8 _579_:A1 _262_:6 3.685 *END *D_NET _263_ 8.44 *CONN -*I _569_/ZN O *D AND2_X1 -*I _571_/A1 I *D NOR2_X1 +*I _569_:ZN O *D AND2_X1 +*I _571_:A1 I *D NOR2_X1 *CAP 1 _263_:1 0.83 2 _263_:2 2.1 @@ -7915,29 +7915,29 @@ resp_val O 1 _263_:1 _263_:2 0.005 2 _263_:2 _263_:3 8.4 3 _263_:3 _263_:4 0.005 -4 _569_/ZN _263_:1 3.325 -5 _571_/A1 _263_:4 5.165 +4 _569_:ZN _263_:1 3.325 +5 _571_:A1 _263_:4 5.165 *END *D_NET _264_ 10.15 *CONN -*I _570_/ZN O *D AND2_X1 -*I _571_/A2 I *D NOR2_X1 -*I _577_/A2 I *D AND2_X1 +*I _570_:ZN O *D AND2_X1 +*I _571_:A2 I *D NOR2_X1 +*I _577_:A2 I *D AND2_X1 *CAP 1 _264_:1 4.095 2 _264_:2 3.08 *RES 1 _264_:2 _264_:1 8.4 -2 _570_/ZN _264_:1 4.125 -3 _571_/A2 _264_:1 3.865 -4 _577_/A2 _264_:2 3.925 +2 _570_:ZN _264_:1 4.125 +3 _571_:A2 _264_:1 3.865 +4 _577_:A2 _264_:2 3.925 *END *D_NET _265_ 9.31 *CONN -*I _571_/ZN O *D NOR2_X1 -*I _572_/A I *D XNOR2_X1 +*I _571_:ZN O *D NOR2_X1 +*I _572_:A I *D XNOR2_X1 *CAP 1 _265_:1 1.53 2 _265_:2 2.1 @@ -7947,39 +7947,39 @@ resp_val O 1 _265_:1 _265_:2 0.005 2 _265_:2 _265_:3 8.4 3 _265_:3 _265_:4 0.005 -4 _571_/ZN _265_:1 6.125 -5 _572_/A _265_:4 4.105 +4 _571_:ZN _265_:1 6.125 +5 _572_:A _265_:4 4.105 *END *D_NET _266_ 8.8 *CONN -*I _573_/ZN O *D NAND2_X1 -*I _574_/B I *D OAI211_X1 +*I _573_:ZN O *D NAND2_X1 +*I _574_:B I *D OAI211_X1 *CAP 1 _266_:1 4.05 2 _266_:2 2.45 *RES 1 _266_:1 _266_:2 8.4 -2 _573_/ZN _266_:1 7.805 -3 _574_/B _266_:2 1.405 +2 _573_:ZN _266_:1 7.805 +3 _574_:B _266_:2 1.405 *END *D_NET _267_ 5.3 *CONN -*I _574_/ZN O *D OAI211_X1 -*I _575_/B I *D MUX2_X1 +*I _574_:ZN O *D OAI211_X1 +*I _575_:B I *D MUX2_X1 *CAP 1 _267_:1 2.65 *RES 1 _267_:1 _267_:1 0.005 -2 _574_/ZN _267_:1 4.185 -3 _575_/B _267_:1 6.425 +2 _574_:ZN _267_:1 4.185 +3 _575_:B _267_:1 6.425 *END *D_NET _268_ 11.05 *CONN -*I _576_/ZN O *D OAI21_X1 -*I _583_/A I *D OAI211_X1 +*I _576_:ZN O *D OAI21_X1 +*I _583_:A I *D OAI211_X1 *CAP 1 _268_:1 3.195 2 _268_:2 2.1 @@ -7991,40 +7991,40 @@ resp_val O 2 _268_:2 _268_:3 0.005 3 _268_:3 _268_:4 8.4 4 _268_:4 _268_:5 0.005 -5 _576_/ZN _268_:1 4.385 -6 _583_/A _268_:5 0.925 +5 _576_:ZN _268_:1 4.385 +6 _583_:A _268_:5 0.925 *END *D_NET _269_ 8.43 *CONN -*I _577_/ZN O *D AND2_X1 -*I _578_/A I *D AOI21_X1 +*I _577_:ZN O *D AND2_X1 +*I _578_:A I *D AOI21_X1 *CAP 1 _269_:1 3.29 2 _269_:2 3.025 *RES 1 _269_:2 _269_:1 8.4 -2 _577_/ZN _269_:1 4.765 -3 _578_/A _269_:2 3.705 +2 _577_:ZN _269_:1 4.765 +3 _578_:A _269_:2 3.705 *END *D_NET _270_ 9.87 *CONN -*I _578_/ZN O *D AOI21_X1 -*I _580_/A1 I *D NAND2_X1 +*I _578_:ZN O *D AOI21_X1 +*I _580_:A1 I *D NAND2_X1 *CAP 1 _270_:1 3.13 2 _270_:2 3.905 *RES 1 _270_:2 _270_:1 8.4 -2 _578_/ZN _270_:1 4.125 -3 _580_/A1 _270_:2 7.225 +2 _578_:ZN _270_:1 4.125 +3 _580_:A1 _270_:2 7.225 *END *D_NET _271_ 10.23 *CONN -*I _579_/ZN O *D NAND2_X1 -*I _580_/A2 I *D NAND2_X1 +*I _579_:ZN O *D NAND2_X1 +*I _580_:A2 I *D NAND2_X1 *CAP 1 _271_:1 0.885 2 _271_:2 2.1 @@ -8034,18 +8034,18 @@ resp_val O 1 _271_:1 _271_:2 0.005 2 _271_:2 _271_:3 8.4 3 _271_:3 _271_:4 0.005 -4 _579_/ZN _271_:1 3.545 -5 _580_/A2 _271_:4 8.525 +4 _579_:ZN _271_:1 3.545 +5 _580_:A2 _271_:4 8.525 *END *D_NET _272_ 65.55 *CONN -*I _580_/ZN O *D NAND2_X1 -*I _581_/A I *D XOR2_X1 -*I _586_/A1 I *D AND2_X1 -*I _589_/C2 I *D AOI221_X4 -*I _596_/B1 I *D AOI21_X1 -*I _611_/A1 I *D NAND2_X1 +*I _580_:ZN O *D NAND2_X1 +*I _581_:A I *D XOR2_X1 +*I _586_:A1 I *D AND2_X1 +*I _589_:C2 I *D AOI221_X4 +*I _596_:B1 I *D AOI21_X1 +*I _611_:A1 I *D NAND2_X1 *CAP 1 _272_:1 6.66 2 _272_:2 3.94 @@ -8065,18 +8065,18 @@ resp_val O 6 _272_:7 _272_:8 0.005 7 _272_:8 _272_:5 33.6 8 _272_:7 _272_:9 33.6 -9 _580_/ZN _272_:9 9.965 -10 _581_/A _272_:2 7.365 -11 _586_/A1 _272_:1 1.445 -12 _589_/C2 _272_:3 6.445 -13 _596_/B1 _272_:4 1.385 -14 _611_/A1 _272_:7 3.725 +9 _580_:ZN _272_:9 9.965 +10 _581_:A _272_:2 7.365 +11 _586_:A1 _272_:1 1.445 +12 _589_:C2 _272_:3 6.445 +13 _596_:B1 _272_:4 1.385 +14 _611_:A1 _272_:7 3.725 *END *D_NET _273_ 4.9 *CONN -*I _582_/ZN O *D NAND2_X1 -*I _583_/B I *D OAI211_X1 +*I _582_:ZN O *D NAND2_X1 +*I _583_:B I *D OAI211_X1 *CAP 1 _273_:1 0.015 2 _273_:2 2.1 @@ -8086,14 +8086,14 @@ resp_val O 1 _273_:1 _273_:2 0.005 2 _273_:2 _273_:3 8.4 3 _273_:3 _273_:4 0.005 -4 _582_/ZN _273_:1 0.065 -5 _583_/B _273_:4 1.345 +4 _582_:ZN _273_:1 0.065 +5 _583_:B _273_:4 1.345 *END *D_NET _274_ 8.73 *CONN -*I _583_/ZN O *D OAI211_X1 -*I _584_/B I *D MUX2_X1 +*I _583_:ZN O *D OAI211_X1 +*I _584_:B I *D MUX2_X1 *CAP 1 _274_:1 0.445 2 _274_:2 2.1 @@ -8103,27 +8103,27 @@ resp_val O 1 _274_:1 _274_:2 0.005 2 _274_:2 _274_:3 8.4 3 _274_:3 _274_:4 0.005 -4 _583_/ZN _274_:1 1.785 -5 _584_/B _274_:4 7.285 +4 _583_:ZN _274_:1 1.785 +5 _584_:B _274_:4 7.285 *END *D_NET _275_ 15.48 *CONN -*I _585_/ZN O *D OAI21_X1 -*I _591_/A I *D OAI211_X1 +*I _585_:ZN O *D OAI21_X1 +*I _591_:A I *D OAI211_X1 *CAP 1 _275_:1 5.505 2 _275_:2 6.435 *RES 1 _275_:1 _275_:2 16.8 -2 _585_/ZN _275_:2 8.945 -3 _591_/A _275_:1 5.225 +2 _585_:ZN _275_:2 8.945 +3 _591_:A _275_:1 5.225 *END *D_NET _276_ 12.11 *CONN -*I _586_/ZN O *D AND2_X1 -*I _588_/A1 I *D NOR3_X1 +*I _586_:ZN O *D AND2_X1 +*I _588_:A1 I *D NOR3_X1 *CAP 1 _276_:1 2.86 2 _276_:2 2.1 @@ -8135,16 +8135,16 @@ resp_val O 2 _276_:2 _276_:3 0.005 3 _276_:3 _276_:4 8.4 4 _276_:4 _276_:5 0.005 -5 _586_/ZN _276_:1 3.045 -6 _588_/A1 _276_:5 4.385 +5 _586_:ZN _276_:1 3.045 +6 _588_:A1 _276_:5 4.385 *END *D_NET _277_ 19.41 *CONN -*I _587_/ZN O *D NOR2_X1 -*I _588_/A3 I *D NOR3_X1 -*I _589_/B2 I *D AOI221_X4 -*I _594_/A2 I *D NAND2_X1 +*I _587_:ZN O *D NOR2_X1 +*I _588_:A3 I *D NOR3_X1 +*I _589_:B2 I *D AOI221_X4 +*I _594_:A2 I *D NAND2_X1 *CAP 1 _277_:1 3.575 2 _277_:2 5.225 @@ -8156,16 +8156,16 @@ resp_val O 2 _277_:1 _277_:3 0.005 3 _277_:3 _277_:4 8.4 4 _277_:4 _277_:5 0.005 -5 _587_/ZN _277_:5 3.625 -6 _588_/A3 _277_:1 5.905 -7 _589_/B2 _277_:2 8.005 -8 _594_/A2 _277_:2 4.505 +5 _587_:ZN _277_:5 3.625 +6 _588_:A3 _277_:1 5.905 +7 _589_:B2 _277_:2 8.005 +8 _594_:A2 _277_:2 4.505 *END *D_NET _278_ 15.35 *CONN -*I _588_/ZN O *D NOR3_X1 -*I _589_/A I *D AOI221_X4 +*I _588_:ZN O *D NOR3_X1 +*I _589_:A I *D AOI221_X4 *CAP 1 _278_:1 1.8 2 _278_:2 2.1 @@ -8177,40 +8177,40 @@ resp_val O 2 _278_:2 _278_:3 8.4 3 _278_:3 _278_:4 0.005 4 _278_:5 _278_:4 8.4 -5 _588_/ZN _278_:5 6.705 -6 _589_/A _278_:1 7.205 +5 _588_:ZN _278_:5 6.705 +6 _589_:A _278_:1 7.205 *END *D_NET _279_ 10.07 *CONN -*I _590_/ZN O *D NAND2_X1 -*I _591_/B I *D OAI211_X1 +*I _590_:ZN O *D NAND2_X1 +*I _591_:B I *D OAI211_X1 *CAP 1 _279_:1 3.945 2 _279_:2 3.19 *RES 1 _279_:1 _279_:2 8.4 -2 _590_/ZN _279_:1 7.385 -3 _591_/B _279_:2 4.365 +2 _590_:ZN _279_:1 7.385 +3 _591_:B _279_:2 4.365 *END *D_NET _280_ 7.86 *CONN -*I _591_/ZN O *D OAI211_X1 -*I _592_/B I *D MUX2_X1 +*I _591_:ZN O *D OAI211_X1 +*I _592_:B I *D MUX2_X1 *CAP 1 _280_:1 3.575 2 _280_:2 2.455 *RES 1 _280_:1 _280_:2 8.4 -2 _591_/ZN _280_:1 5.905 -3 _592_/B _280_:2 1.425 +2 _591_:ZN _280_:1 5.905 +3 _592_:B _280_:2 1.425 *END *D_NET _281_ 14.74 *CONN -*I _593_/ZN O *D OAI21_X1 -*I _599_/A I *D OAI211_X1 +*I _593_:ZN O *D OAI21_X1 +*I _599_:A I *D OAI211_X1 *CAP 1 _281_:1 2.035 2 _281_:2 2.1 @@ -8222,28 +8222,28 @@ resp_val O 2 _281_:2 _281_:3 8.4 3 _281_:3 _281_:4 0.005 4 _281_:5 _281_:4 8.4 -5 _593_/ZN _281_:5 4.545 -6 _599_/A _281_:1 8.145 +5 _593_:ZN _281_:5 4.545 +6 _599_:A _281_:1 8.145 *END *D_NET _282_ 7.3 *CONN -*I _594_/ZN O *D NAND2_X1 -*I _595_/A I *D OAI21_X1 +*I _594_:ZN O *D NAND2_X1 +*I _595_:A I *D OAI21_X1 *CAP 1 _282_:1 2.865 2 _282_:2 2.885 *RES 1 _282_:1 _282_:2 8.4 -2 _594_/ZN _282_:1 3.065 -3 _595_/A _282_:2 3.145 +2 _594_:ZN _282_:1 3.065 +3 _595_:A _282_:2 3.145 *END *D_NET _283_ 22.51 *CONN -*I _595_/ZN O *D OAI21_X1 -*I _596_/A I *D AOI21_X1 -*I _613_/C1 I *D AOI221_X1 +*I _595_:ZN O *D OAI21_X1 +*I _596_:A I *D AOI21_X1 +*I _613_:C1 I *D AOI221_X1 *CAP 1 _283_:1 2.62 2 _283_:2 2.1 @@ -8259,16 +8259,16 @@ resp_val O 4 _283_:5 _283_:2 0.005 5 _283_:5 _283_:6 16.8 6 _283_:6 _283_:7 0.005 -7 _595_/ZN _283_:7 4.985 -8 _596_/A _283_:1 2.085 -9 _613_/C1 _283_:3 4.365 +7 _595_:ZN _283_:7 4.985 +8 _596_:A _283_:1 2.085 +9 _613_:C1 _283_:3 4.365 *END *D_NET _284_ 16.62 *CONN -*I _596_/ZN O *D AOI21_X1 -*I _597_/A I *D XNOR2_X1 -*I _604_/A1 I *D NOR3_X1 +*I _596_:ZN O *D AOI21_X1 +*I _597_:A I *D XNOR2_X1 +*I _604_:A1 I *D NOR3_X1 *CAP 1 _284_:1 2.1 2 _284_:2 4.2 @@ -8284,15 +8284,15 @@ resp_val O 4 _284_:5 _284_:1 8.4 5 _284_:6 _284_:7 0.005 6 _284_:7 _284_:2 8.4 -7 _596_/ZN _284_:4 0.165 -8 _597_/A _284_:5 5.825 -9 _604_/A1 _284_:6 2.065 +7 _596_:ZN _284_:4 0.165 +8 _597_:A _284_:5 5.825 +9 _604_:A1 _284_:6 2.065 *END *D_NET _285_ 8.67 *CONN -*I _598_/ZN O *D NAND2_X1 -*I _599_/B I *D OAI211_X1 +*I _598_:ZN O *D NAND2_X1 +*I _599_:B I *D OAI211_X1 *CAP 1 _285_:1 0.415 2 _285_:2 2.1 @@ -8302,14 +8302,14 @@ resp_val O 1 _285_:1 _285_:2 0.005 2 _285_:2 _285_:3 8.4 3 _285_:3 _285_:4 0.005 -4 _598_/ZN _285_:1 1.665 -5 _599_/B _285_:4 7.285 +4 _598_:ZN _285_:1 1.665 +5 _599_:B _285_:4 7.285 *END *D_NET _286_ 14.21 *CONN -*I _599_/ZN O *D OAI211_X1 -*I _600_/B I *D MUX2_X1 +*I _599_:ZN O *D OAI211_X1 +*I _600_:B I *D MUX2_X1 *CAP 1 _286_:1 2.8 2 _286_:2 2.1 @@ -8321,14 +8321,14 @@ resp_val O 2 _286_:2 _286_:3 0.005 3 _286_:3 _286_:4 8.4 4 _286_:4 _286_:5 0.005 -5 _599_/ZN _286_:5 8.825 -6 _600_/B _286_:1 2.805 +5 _599_:ZN _286_:5 8.825 +6 _600_:B _286_:1 2.805 *END *D_NET _287_ 36.09 *CONN -*I _601_/ZN O *D OAI21_X1 -*I _608_/A I *D OAI211_X1 +*I _601_:ZN O *D OAI21_X1 +*I _608_:A I *D OAI211_X1 *CAP 1 _287_:1 0.895 2 _287_:2 16.8 @@ -8338,14 +8338,14 @@ resp_val O 1 _287_:1 _287_:2 0.005 2 _287_:2 _287_:3 67.2 3 _287_:3 _287_:4 0.005 -4 _601_/ZN _287_:1 3.585 -5 _608_/A _287_:4 1.405 +4 _601_:ZN _287_:1 3.585 +5 _608_:A _287_:4 1.405 *END *D_NET _288_ 12.77 *CONN -*I _602_/ZN O *D AND2_X1 -*I _604_/A2 I *D NOR3_X1 +*I _602_:ZN O *D AND2_X1 +*I _604_:A2 I *D NOR3_X1 *CAP 1 _288_:1 3.58 2 _288_:2 2.1 @@ -8357,16 +8357,16 @@ resp_val O 2 _288_:2 _288_:3 0.005 3 _288_:3 _288_:4 8.4 4 _288_:4 _288_:5 0.005 -5 _602_/ZN _288_:1 5.925 -6 _604_/A2 _288_:5 2.825 +5 _602_:ZN _288_:1 5.925 +6 _604_:A2 _288_:5 2.825 *END *D_NET _289_ 17.5 *CONN -*I _603_/ZN O *D NOR2_X1 -*I _604_/A3 I *D NOR3_X1 -*I _605_/A2 I *D NOR2_X1 -*I _612_/A2 I *D AND2_X1 +*I _603_:ZN O *D NOR2_X1 +*I _604_:A3 I *D NOR3_X1 +*I _605_:A2 I *D NOR2_X1 +*I _612_:A2 I *D AND2_X1 *CAP 1 _289_:1 2.995 2 _289_:2 4.465 @@ -8378,68 +8378,68 @@ resp_val O 2 _289_:3 _289_:4 0.005 3 _289_:4 _289_:5 8.4 4 _289_:5 _289_:1 0.005 -5 _603_/ZN _289_:3 5.165 -6 _604_/A3 _289_:1 3.585 -7 _605_/A2 _289_:2 7.905 -8 _612_/A2 _289_:2 1.565 +5 _603_:ZN _289_:3 5.165 +6 _604_:A3 _289_:1 3.585 +7 _605_:A2 _289_:2 7.905 +8 _612_:A2 _289_:2 1.565 *END *D_NET _290_ 8.99 *CONN -*I _604_/ZN O *D NOR3_X1 -*I _605_/A1 I *D NOR2_X1 +*I _604_:ZN O *D NOR3_X1 +*I _605_:A1 I *D NOR2_X1 *CAP 1 _290_:1 2.845 2 _290_:2 3.75 *RES 1 _290_:1 _290_:2 8.4 -2 _604_/ZN _290_:1 2.985 -3 _605_/A1 _290_:2 6.605 +2 _604_:ZN _290_:1 2.985 +3 _605_:A1 _290_:2 6.605 *END *D_NET _291_ 12.11 *CONN -*I _605_/ZN O *D NOR2_X1 -*I _606_/A I *D XNOR2_X1 +*I _605_:ZN O *D NOR2_X1 +*I _606_:A I *D XNOR2_X1 *CAP 1 _291_:1 4.61 2 _291_:2 3.545 *RES 1 _291_:1 _291_:2 8.4 -2 _605_/ZN _291_:1 10.045 -3 _606_/A _291_:2 5.785 +2 _605_:ZN _291_:1 10.045 +3 _606_:A _291_:2 5.785 *END *D_NET _292_ 7.96 *CONN -*I _607_/ZN O *D NAND2_X1 -*I _608_/B I *D OAI211_X1 +*I _607_:ZN O *D NAND2_X1 +*I _608_:B I *D OAI211_X1 *CAP 1 _292_:1 3.415 2 _292_:2 2.665 *RES 1 _292_:2 _292_:1 8.4 -2 _607_/ZN _292_:1 5.265 -3 _608_/B _292_:2 2.265 +2 _607_:ZN _292_:1 5.265 +3 _608_:B _292_:2 2.265 *END *D_NET _293_ 6.93 *CONN -*I _608_/ZN O *D OAI211_X1 -*I _609_/B I *D MUX2_X1 +*I _608_:ZN O *D OAI211_X1 +*I _609_:B I *D MUX2_X1 *CAP 1 _293_:1 2.315 2 _293_:2 3.25 *RES 1 _293_:1 _293_:2 8.4 -2 _608_/ZN _293_:1 0.865 -3 _609_/B _293_:2 4.605 +2 _608_:ZN _293_:1 0.865 +3 _609_:B _293_:2 4.605 *END *D_NET _294_ 17.9 *CONN -*I _610_/ZN O *D OAI21_X1 -*I _617_/A I *D OAI211_X1 +*I _610_:ZN O *D OAI21_X1 +*I _617_:A I *D OAI211_X1 *CAP 1 _294_:1 3.415 2 _294_:2 2.1 @@ -8451,14 +8451,14 @@ resp_val O 2 _294_:2 _294_:3 0.005 3 _294_:3 _294_:4 16.8 4 _294_:4 _294_:5 0.005 -5 _610_/ZN _294_:5 5.345 -6 _617_/A _294_:1 5.265 +5 _610_:ZN _294_:5 5.345 +6 _617_:A _294_:1 5.265 *END *D_NET _295_ 7.07 *CONN -*I _611_/ZN O *D NAND2_X1 -*I _614_/A1 I *D NAND2_X1 +*I _611_:ZN O *D NAND2_X1 +*I _614_:A1 I *D NAND2_X1 *CAP 1 _295_:1 0.54 2 _295_:2 2.1 @@ -8468,14 +8468,14 @@ resp_val O 1 _295_:1 _295_:2 0.005 2 _295_:2 _295_:3 8.4 3 _295_:3 _295_:4 0.005 -4 _611_/ZN _295_:4 3.585 -5 _614_/A1 _295_:1 2.165 +4 _611_:ZN _295_:4 3.585 +5 _614_:A1 _295_:1 2.165 *END *D_NET _296_ 10.01 *CONN -*I _612_/ZN O *D AND2_X1 -*I _613_/A I *D AOI221_X1 +*I _612_:ZN O *D AND2_X1 +*I _613_:A I *D AOI221_X1 *CAP 1 _296_:1 1.3 2 _296_:2 2.1 @@ -8485,14 +8485,14 @@ resp_val O 1 _296_:1 _296_:2 0.005 2 _296_:2 _296_:3 8.4 3 _296_:3 _296_:4 0.005 -4 _612_/ZN _296_:1 5.205 -5 _613_/A _296_:4 6.425 +4 _612_:ZN _296_:1 5.205 +5 _613_:A _296_:4 6.425 *END *D_NET _297_ 25.22 *CONN -*I _613_/ZN O *D AOI221_X1 -*I _614_/A2 I *D NAND2_X1 +*I _613_:ZN O *D AOI221_X1 +*I _614_:A2 I *D NAND2_X1 *CAP 1 _297_:1 0.865 2 _297_:2 8.4 @@ -8504,17 +8504,17 @@ resp_val O 2 _297_:2 _297_:3 33.6 3 _297_:3 _297_:4 0.005 4 _297_:4 _297_:5 8.4 -5 _613_/ZN _297_:5 4.985 -6 _614_/A2 _297_:1 3.465 +5 _613_:ZN _297_:5 4.985 +6 _614_:A2 _297_:1 3.465 *END *D_NET _298_ 67.99 *CONN -*I _614_/ZN O *D NAND2_X1 -*I _615_/A I *D XOR2_X1 -*I _620_/A1 I *D AND3_X1 -*I _621_/A1 I *D AND2_X1 -*I _647_/A1 I *D AND2_X1 +*I _614_:ZN O *D NAND2_X1 +*I _615_:A I *D XOR2_X1 +*I _620_:A1 I *D AND3_X1 +*I _621_:A1 I *D AND2_X1 +*I _647_:A1 I *D AND2_X1 *CAP 1 _298_:1 6.68 2 _298_:2 6.025 @@ -8534,17 +8534,17 @@ resp_val O 6 _298_:5 _298_:7 50.4 7 _298_:7 _298_:8 0.005 8 _298_:8 _298_:9 16.8 -9 _614_/ZN _298_:9 2.025 -10 _615_/A _298_:2 7.305 -11 _620_/A1 _298_:3 3.625 -12 _621_/A1 _298_:1 1.525 -13 _647_/A1 _298_:6 3.925 +9 _614_:ZN _298_:9 2.025 +10 _615_:A _298_:2 7.305 +11 _620_:A1 _298_:3 3.625 +12 _621_:A1 _298_:1 1.525 +13 _647_:A1 _298_:6 3.925 *END *D_NET _299_ 7.23 *CONN -*I _616_/ZN O *D NAND2_X1 -*I _617_/B I *D OAI211_X1 +*I _616_:ZN O *D NAND2_X1 +*I _617_:B I *D OAI211_X1 *CAP 1 _299_:1 1.1 2 _299_:2 2.1 @@ -8554,14 +8554,14 @@ resp_val O 1 _299_:1 _299_:2 0.005 2 _299_:2 _299_:3 8.4 3 _299_:3 _299_:4 0.005 -4 _616_/ZN _299_:4 1.665 -5 _617_/B _299_:1 4.405 +4 _616_:ZN _299_:4 1.665 +5 _617_:B _299_:1 4.405 *END *D_NET _300_ 13.56 *CONN -*I _617_/ZN O *D OAI211_X1 -*I _618_/B I *D MUX2_X1 +*I _617_:ZN O *D OAI211_X1 +*I _618_:B I *D MUX2_X1 *CAP 1 _300_:1 1.095 2 _300_:2 4.2 @@ -8571,29 +8571,29 @@ resp_val O 1 _300_:1 _300_:2 0.005 2 _300_:2 _300_:3 16.8 3 _300_:3 _300_:4 0.005 -4 _617_/ZN _300_:4 5.945 -5 _618_/B _300_:1 4.385 +4 _617_:ZN _300_:4 5.945 +5 _618_:B _300_:1 4.385 *END *D_NET _301_ 10.38 *CONN -*I _619_/ZN O *D OAI21_X1 -*I _626_/A I *D OAI211_X1 +*I _619_:ZN O *D OAI21_X1 +*I _626_:A I *D OAI211_X1 *CAP 1 _301_:1 4.135 2 _301_:2 3.155 *RES 1 _301_:2 _301_:1 8.4 -2 _619_/ZN _301_:1 8.145 -3 _626_/A _301_:2 4.225 +2 _619_:ZN _301_:1 8.145 +3 _626_:A _301_:2 4.225 *END *D_NET _302_ 33.66 *CONN -*I _620_/ZN O *D AND3_X1 -*I _624_/A I *D AOI211_X1 -*I _632_/A1 I *D NOR2_X1 -*I _639_/B1 I *D OAI21_X1 +*I _620_:ZN O *D AND3_X1 +*I _624_:A I *D AOI211_X1 +*I _632_:A1 I *D NOR2_X1 +*I _639_:B1 I *D OAI21_X1 *CAP 1 _302_:1 2.755 2 _302_:2 2.1 @@ -8613,16 +8613,16 @@ resp_val O 6 _302_:6 _302_:7 0.005 7 _302_:9 _302_:8 8.4 8 _302_:5 _302_:9 16.8 -9 _620_/ZN _302_:8 9.245 -10 _624_/A _302_:9 1.825 -11 _632_/A1 _302_:1 2.625 -12 _639_/B1 _302_:7 3.245 +9 _620_:ZN _302_:8 9.245 +10 _624_:A _302_:9 1.825 +11 _632_:A1 _302_:1 2.625 +12 _639_:B1 _302_:7 3.245 *END *D_NET _303_ 12.69 *CONN -*I _621_/ZN O *D AND2_X1 -*I _623_/A1 I *D NOR3_X1 +*I _621_:ZN O *D AND2_X1 +*I _623_:A1 I *D NOR3_X1 *CAP 1 _303_:1 3.525 2 _303_:2 2.1 @@ -8634,16 +8634,16 @@ resp_val O 2 _303_:2 _303_:3 0.005 3 _303_:3 _303_:4 8.4 4 _303_:4 _303_:5 0.005 -5 _621_/ZN _303_:5 2.885 -6 _623_/A1 _303_:1 5.705 +5 _621_:ZN _303_:5 2.885 +6 _623_:A1 _303_:1 5.705 *END *D_NET _304_ 31.6 *CONN -*I _622_/ZN O *D NOR2_X1 -*I _623_/A3 I *D NOR3_X1 -*I _624_/C2 I *D AOI211_X1 -*I _630_/B2 I *D AOI21_X1 +*I _622_:ZN O *D NOR2_X1 +*I _623_:A3 I *D NOR3_X1 +*I _624_:C2 I *D AOI211_X1 +*I _630_:B2 I *D AOI21_X1 *CAP 1 _304_:1 2.1 2 _304_:2 4.2 @@ -8663,16 +8663,16 @@ resp_val O 6 _304_:7 _304_:2 8.4 7 _304_:8 _304_:9 8.4 8 _304_:9 _304_:1 8.4 -9 _622_/ZN _304_:6 9.405 -10 _623_/A3 _304_:9 4.185 -11 _624_/C2 _304_:5 3.805 -12 _630_/B2 _304_:8 3.825 +9 _622_:ZN _304_:6 9.405 +10 _623_:A3 _304_:9 4.185 +11 _624_:C2 _304_:5 3.805 +12 _630_:B2 _304_:8 3.825 *END *D_NET _305_ 6.76 *CONN -*I _623_/ZN O *D NOR3_X1 -*I _624_/B I *D AOI211_X1 +*I _623_:ZN O *D NOR3_X1 +*I _624_:B I *D AOI211_X1 *CAP 1 _305_:1 0.845 2 _305_:2 2.1 @@ -8682,14 +8682,14 @@ resp_val O 1 _305_:1 _305_:2 0.005 2 _305_:2 _305_:3 8.4 3 _305_:3 _305_:4 0.005 -4 _623_/ZN _305_:1 3.385 -5 _624_/B _305_:4 1.745 +4 _623_:ZN _305_:1 3.385 +5 _624_:B _305_:4 1.745 *END *D_NET _306_ 20.93 *CONN -*I _625_/ZN O *D NAND2_X1 -*I _626_/B I *D OAI211_X1 +*I _625_:ZN O *D NAND2_X1 +*I _626_:B I *D OAI211_X1 *CAP 1 _306_:1 3.37 2 _306_:2 2.1 @@ -8701,14 +8701,14 @@ resp_val O 2 _306_:2 _306_:3 0.005 3 _306_:3 _306_:4 25.2 4 _306_:4 _306_:5 0.005 -5 _625_/ZN _306_:5 3.185 -6 _626_/B _306_:1 5.085 +5 _625_:ZN _306_:5 3.185 +6 _626_:B _306_:1 5.085 *END *D_NET _307_ 16.96 *CONN -*I _626_/ZN O *D OAI211_X1 -*I _627_/B I *D MUX2_X1 +*I _626_:ZN O *D OAI211_X1 +*I _627_:B I *D MUX2_X1 *CAP 1 _307_:1 3.395 2 _307_:2 2.1 @@ -8722,27 +8722,27 @@ resp_val O 3 _307_:3 _307_:4 8.4 4 _307_:4 _307_:5 0.005 5 _307_:5 _307_:6 8.4 -6 _626_/ZN _307_:6 3.545 -7 _627_/B _307_:1 5.185 +6 _626_:ZN _307_:6 3.545 +7 _627_:B _307_:1 5.185 *END *D_NET _308_ 10.73 *CONN -*I _628_/ZN O *D OAI21_X1 -*I _635_/A I *D OAI211_X1 +*I _628_:ZN O *D OAI21_X1 +*I _635_:A I *D OAI211_X1 *CAP 1 _308_:1 3.945 2 _308_:2 3.52 *RES 1 _308_:1 _308_:2 8.4 -2 _628_/ZN _308_:1 7.385 -3 _635_/A _308_:2 5.685 +2 _628_:ZN _308_:1 7.385 +3 _635_:A _308_:2 5.685 *END *D_NET _309_ 12.58 *CONN -*I _629_/ZN O *D NOR2_X1 -*I _630_/A I *D AOI21_X1 +*I _629_:ZN O *D NOR2_X1 +*I _630_:A I *D AOI21_X1 *CAP 1 _309_:1 3.75 2 _309_:2 2.1 @@ -8754,29 +8754,29 @@ resp_val O 2 _309_:2 _309_:3 0.005 3 _309_:3 _309_:4 8.4 4 _309_:4 _309_:5 0.005 -5 _629_/ZN _309_:1 6.605 -6 _630_/A _309_:5 1.765 +5 _629_:ZN _309_:1 6.605 +6 _630_:A _309_:5 1.765 *END *D_NET _310_ 7.13 *CONN -*I _630_/ZN O *D AOI21_X1 -*I _631_/A I *D INV_X1 +*I _630_:ZN O *D AOI21_X1 +*I _631_:A I *D INV_X1 *CAP 1 _310_:1 2.68 2 _310_:2 2.985 *RES 1 _310_:2 _310_:1 8.4 -2 _630_/ZN _310_:1 2.325 -3 _631_/A _310_:2 3.545 +2 _630_:ZN _310_:1 2.325 +3 _631_:A _310_:2 3.545 *END *D_NET _311_ 31.08 *CONN -*I _631_/ZN O *D INV_X1 -*I _632_/A2 I *D NOR2_X1 -*I _639_/B2 I *D OAI21_X1 -*I _649_/A1 I *D NAND2_X1 +*I _631_:ZN O *D INV_X1 +*I _632_:A2 I *D NOR2_X1 +*I _639_:B2 I *D OAI21_X1 +*I _649_:A1 I *D NAND2_X1 *CAP 1 _311_:1 2.47 2 _311_:2 3.53 @@ -8794,55 +8794,55 @@ resp_val O 5 _311_:6 _311_:7 8.4 6 _311_:2 _311_:8 0.005 7 _311_:8 _311_:4 16.8 -8 _631_/ZN _311_:2 5.725 -9 _632_/A2 _311_:1 1.485 -10 _639_/B2 _311_:3 4.545 -11 _649_/A1 _311_:7 8.425 +8 _631_:ZN _311_:2 5.725 +9 _632_:A2 _311_:1 1.485 +10 _639_:B2 _311_:3 4.545 +11 _649_:A1 _311_:7 8.425 *END *D_NET _312_ 8.48 *CONN -*I _632_/ZN O *D NOR2_X1 -*I _633_/A I *D XNOR2_X1 +*I _632_:ZN O *D NOR2_X1 +*I _633_:A I *D XNOR2_X1 *CAP 1 _312_:1 2.275 2 _312_:2 4.065 *RES 1 _312_:2 _312_:1 8.4 -2 _632_/ZN _312_:1 0.705 -3 _633_/A _312_:2 7.865 +2 _632_:ZN _312_:1 0.705 +3 _633_:A _312_:2 7.865 *END *D_NET _313_ 14.35 *CONN -*I _634_/ZN O *D NAND2_X1 -*I _635_/B I *D OAI211_X1 +*I _634_:ZN O *D NAND2_X1 +*I _635_:B I *D OAI211_X1 *CAP 1 _313_:1 5.715 2 _313_:2 5.66 *RES 1 _313_:1 _313_:2 16.8 -2 _634_/ZN _313_:2 5.845 -3 _635_/B _313_:1 6.065 +2 _634_:ZN _313_:2 5.845 +3 _635_:B _313_:1 6.065 *END *D_NET _314_ 10.11 *CONN -*I _635_/ZN O *D OAI211_X1 -*I _636_/B I *D MUX2_X1 +*I _635_:ZN O *D OAI211_X1 +*I _636_:B I *D MUX2_X1 *CAP 1 _314_:1 3.435 2 _314_:2 3.72 *RES 1 _314_:1 _314_:2 8.4 -2 _635_/ZN _314_:1 5.345 -3 _636_/B _314_:2 6.485 +2 _635_:ZN _314_:1 5.345 +3 _636_:B _314_:2 6.485 *END *D_NET _315_ 13.6 *CONN -*I _637_/ZN O *D OAI21_X1 -*I _638_/A I *D OAI21_X1 +*I _637_:ZN O *D OAI21_X1 +*I _638_:A I *D OAI21_X1 *CAP 1 _315_:1 0.605 2 _315_:2 2.1 @@ -8854,26 +8854,26 @@ resp_val O 2 _315_:2 _315_:3 8.4 3 _315_:3 _315_:4 0.005 4 _315_:5 _315_:4 8.4 -5 _637_/ZN _315_:1 2.425 -6 _638_/A _315_:5 7.985 +5 _637_:ZN _315_:1 2.425 +6 _638_:A _315_:5 7.985 *END *D_NET _316_ 6.57 *CONN -*I _638_/ZN O *D OAI21_X1 -*I _645_/B1 I *D OAI21_X1 +*I _638_:ZN O *D OAI21_X1 +*I _645_:B1 I *D OAI21_X1 *CAP 1 _316_:1 3.285 *RES 1 _316_:1 _316_:1 0.005 -2 _638_/ZN _316_:1 8.745 -3 _645_/B1 _316_:1 4.405 +2 _638_:ZN _316_:1 8.745 +3 _645_:B1 _316_:1 4.405 *END *D_NET _317_ 26.78 *CONN -*I _639_/ZN O *D OAI21_X1 -*I _642_/A1 I *D AND2_X1 +*I _639_:ZN O *D OAI21_X1 +*I _642_:A1 I *D AND2_X1 *CAP 1 _317_:1 3.285 2 _317_:2 2.1 @@ -8887,15 +8887,15 @@ resp_val O 3 _317_:3 _317_:4 25.2 4 _317_:4 _317_:5 0.005 5 _317_:6 _317_:5 8.4 -6 _639_/ZN _317_:1 4.745 -7 _642_/A1 _317_:6 6.825 +6 _639_:ZN _317_:1 4.745 +7 _642_:A1 _317_:6 6.825 *END *D_NET _318_ 23.86 *CONN -*I _640_/ZN O *D NOR2_X1 -*I _641_/A I *D INV_X1 -*I _650_/B2 I *D AOI21_X1 +*I _640_:ZN O *D NOR2_X1 +*I _641_:A I *D INV_X1 +*I _650_:B2 I *D AOI21_X1 *CAP 1 _318_:1 1.215 2 _318_:2 2.1 @@ -8911,15 +8911,15 @@ resp_val O 4 _318_:3 _318_:5 16.8 5 _318_:5 _318_:6 0.005 6 _318_:4 _318_:7 8.4 -7 _640_/ZN _318_:1 4.865 -8 _641_/A _318_:6 7.625 -9 _650_/B2 _318_:7 1.645 +7 _640_:ZN _318_:1 4.865 +8 _641_:A _318_:6 7.625 +9 _650_:B2 _318_:7 1.645 *END *D_NET _319_ 16.35 *CONN -*I _641_/ZN O *D INV_X1 -*I _642_/A2 I *D AND2_X1 +*I _641_:ZN O *D INV_X1 +*I _642_:A2 I *D AND2_X1 *CAP 1 _319_:1 3.615 2 _319_:2 2.1 @@ -8931,14 +8931,14 @@ resp_val O 2 _319_:2 _319_:3 0.005 3 _319_:3 _319_:4 8.4 4 _319_:4 _319_:5 0.005 -5 _641_/ZN _319_:5 9.845 -6 _642_/A2 _319_:1 6.065 +5 _641_:ZN _319_:5 9.845 +6 _642_:A2 _319_:1 6.065 *END *D_NET _320_ 19.59 *CONN -*I _642_/ZN O *D AND2_X1 -*I _643_/A I *D XNOR2_X1 +*I _642_:ZN O *D AND2_X1 +*I _643_:A I *D XNOR2_X1 *CAP 1 _320_:1 3.94 2 _320_:2 2.1 @@ -8950,65 +8950,65 @@ resp_val O 2 _320_:2 _320_:3 0.005 3 _320_:3 _320_:4 16.8 4 _320_:4 _320_:5 0.005 -5 _642_/ZN _320_:1 7.365 -6 _643_/A _320_:5 6.625 +5 _642_:ZN _320_:1 7.365 +6 _643_:A _320_:5 6.625 *END *D_NET _321_ 4.53 *CONN -*I _644_/ZN O *D AND2_X1 -*I _645_/B2 I *D OAI21_X1 +*I _644_:ZN O *D AND2_X1 +*I _645_:B2 I *D OAI21_X1 *CAP 1 _321_:1 2.265 *RES 1 _321_:1 _321_:1 0.005 -2 _644_/ZN _321_:1 5.965 -3 _645_/B2 _321_:1 3.105 +2 _644_:ZN _321_:1 5.965 +3 _645_:B2 _321_:1 3.105 *END *D_NET _322_ 7.7 *CONN -*I _645_/ZN O *D OAI21_X1 -*I _646_/A I *D OAI21_X1 +*I _645_:ZN O *D OAI21_X1 +*I _646_:A I *D OAI21_X1 *CAP 1 _322_:1 3.305 2 _322_:2 2.645 *RES 1 _322_:2 _322_:1 8.4 -2 _645_/ZN _322_:1 4.825 -3 _646_/A _322_:2 2.185 +2 _645_:ZN _322_:1 4.825 +3 _646_:A _322_:2 2.185 *END *D_NET _323_ 5.96 *CONN -*I _647_/ZN O *D AND2_X1 -*I _648_/A I *D INV_X1 +*I _647_:ZN O *D AND2_X1 +*I _648_:A I *D INV_X1 *CAP 1 _323_:1 2.38 2 _323_:2 2.7 *RES 1 _323_:2 _323_:1 8.4 -2 _647_/ZN _323_:1 1.125 -3 _648_/A _323_:2 2.405 +2 _647_:ZN _323_:1 1.125 +3 _648_:A _323_:2 2.405 *END *D_NET _324_ 9.52 *CONN -*I _648_/ZN O *D INV_X1 -*I _651_/A1 I *D AND3_X1 +*I _648_:ZN O *D INV_X1 +*I _651_:A1 I *D AND3_X1 *CAP 1 _324_:1 3.08 2 _324_:2 3.78 *RES 1 _324_:2 _324_:1 8.4 -2 _648_/ZN _324_:1 3.925 -3 _651_/A1 _324_:2 6.725 +2 _648_:ZN _324_:1 3.925 +3 _651_:A1 _324_:2 6.725 *END *D_NET _325_ 16.4 *CONN -*I _649_/ZN O *D NAND2_X1 -*I _651_/A2 I *D AND3_X1 +*I _649_:ZN O *D NAND2_X1 +*I _651_:A2 I *D AND3_X1 *CAP 1 _325_:1 2.51 2 _325_:2 4.2 @@ -9018,29 +9018,29 @@ resp_val O 1 _325_:1 _325_:2 0.005 2 _325_:2 _325_:3 16.8 3 _325_:3 _325_:4 0.005 -4 _649_/ZN _325_:1 10.045 -5 _651_/A2 _325_:4 5.965 +4 _649_:ZN _325_:1 10.045 +5 _651_:A2 _325_:4 5.965 *END *D_NET _326_ 11.42 *CONN -*I _650_/ZN O *D AOI21_X1 -*I _651_/A3 I *D AND3_X1 +*I _650_:ZN O *D AOI21_X1 +*I _651_:A3 I *D AND3_X1 *CAP 1 _326_:1 4.41 2 _326_:2 5.5 *RES 1 _326_:1 _326_:2 16.8 -2 _650_/ZN _326_:1 0.845 -3 _651_/A3 _326_:2 5.205 +2 _650_:ZN _326_:1 0.845 +3 _651_:A3 _326_:2 5.205 *END *D_NET _327_ 61.28 *CONN -*I _651_/ZN O *D AND3_X1 -*I _652_/A I *D XNOR2_X1 -*I _657_/A1 I *D NOR2_X1 -*I _665_/A1 I *D OR3_X1 +*I _651_:ZN O *D AND3_X1 +*I _652_:A I *D XNOR2_X1 +*I _657_:A1 I *D NOR2_X1 +*I _665_:A1 I *D OR3_X1 *CAP 1 _327_:1 2.1 2 _327_:2 6.3 @@ -9064,29 +9064,29 @@ resp_val O 8 _327_:9 _327_:10 58.8 9 _327_:9 _327_:11 0.005 10 _327_:11 _327_:8 8.4 -11 _651_/ZN _327_:10 3.545 -12 _652_/A _327_:5 4.625 -13 _657_/A1 _327_:6 2.765 -14 _665_/A1 _327_:7 2.445 +11 _651_:ZN _327_:10 3.545 +12 _652_:A _327_:5 4.625 +13 _657_:A1 _327_:6 2.765 +14 _665_:A1 _327_:7 2.445 *END *D_NET _328_ 11.24 *CONN -*I _653_/ZN O *D NAND2_X1 -*I _655_/A I *D OAI211_X1 +*I _653_:ZN O *D NAND2_X1 +*I _655_:A I *D OAI211_X1 *CAP 1 _328_:1 4.75 2 _328_:2 2.97 *RES 1 _328_:2 _328_:1 8.4 -2 _653_/ZN _328_:1 10.605 -3 _655_/A _328_:2 3.485 +2 _653_:ZN _328_:1 10.605 +3 _655_:A _328_:2 3.485 *END *D_NET _329_ 25.84 *CONN -*I _654_/ZN O *D OAI21_X1 -*I _655_/B I *D OAI211_X1 +*I _654_:ZN O *D OAI21_X1 +*I _655_:B I *D OAI211_X1 *CAP 1 _329_:1 1.765 2 _329_:2 10.5 @@ -9096,14 +9096,14 @@ resp_val O 1 _329_:1 _329_:2 0.005 2 _329_:2 _329_:3 42 3 _329_:3 _329_:4 0.005 -4 _654_/ZN _329_:1 7.065 -5 _655_/B _329_:4 2.625 +4 _654_:ZN _329_:1 7.065 +5 _655_:B _329_:4 2.625 *END *D_NET _330_ 13.59 *CONN -*I _655_/ZN O *D OAI211_X1 -*I _656_/B I *D MUX2_X1 +*I _655_:ZN O *D OAI211_X1 +*I _656_:B I *D MUX2_X1 *CAP 1 _330_:1 3.535 2 _330_:2 2.1 @@ -9115,14 +9115,14 @@ resp_val O 2 _330_:2 _330_:3 0.005 3 _330_:3 _330_:4 8.4 4 _330_:4 _330_:5 0.005 -5 _655_/ZN _330_:1 5.745 -6 _656_/B _330_:5 4.645 +5 _655_:ZN _330_:1 5.745 +6 _656_:B _330_:5 4.645 *END *D_NET _331_ 9.43 *CONN -*I _657_/ZN O *D NOR2_X1 -*I _659_/A1 I *D NOR2_X1 +*I _657_:ZN O *D NOR2_X1 +*I _659_:A1 I *D NOR2_X1 *CAP 1 _331_:1 0.85 2 _331_:2 2.1 @@ -9132,15 +9132,15 @@ resp_val O 1 _331_:1 _331_:2 0.005 2 _331_:2 _331_:3 8.4 3 _331_:3 _331_:4 0.005 -4 _657_/ZN _331_:1 3.405 -5 _659_/A1 _331_:4 7.065 +4 _657_:ZN _331_:1 3.405 +5 _659_:A1 _331_:4 7.065 *END *D_NET _332_ 28.55 *CONN -*I _658_/ZN O *D NOR2_X1 -*I _659_/A2 I *D NOR2_X1 -*I _667_/A2 I *D AOI22_X1 +*I _658_:ZN O *D NOR2_X1 +*I _659_:A2 I *D NOR2_X1 +*I _667_:A2 I *D AOI22_X1 *CAP 1 _332_:1 3.815 2 _332_:2 2.1 @@ -9154,15 +9154,15 @@ resp_val O 3 _332_:3 _332_:4 8.4 4 _332_:4 _332_:5 0.005 5 _332_:5 _332_:6 16.8 -6 _658_/ZN _332_:6 8.285 -7 _659_/A2 _332_:5 8.365 -8 _667_/A2 _332_:1 6.865 +6 _658_:ZN _332_:6 8.285 +7 _659_:A2 _332_:5 8.365 +8 _667_:A2 _332_:1 6.865 *END *D_NET _333_ 15.06 *CONN -*I _659_/ZN O *D NOR2_X1 -*I _660_/A I *D XNOR2_X1 +*I _659_:ZN O *D NOR2_X1 +*I _660_:A I *D XNOR2_X1 *CAP 1 _333_:1 3.875 2 _333_:2 2.1 @@ -9174,14 +9174,14 @@ resp_val O 2 _333_:2 _333_:3 0.005 3 _333_:3 _333_:4 8.4 4 _333_:4 _333_:5 0.005 -5 _659_/ZN _333_:5 6.225 -6 _660_/A _333_:1 7.105 +5 _659_:ZN _333_:5 6.225 +6 _660_:A _333_:1 7.105 *END *D_NET _334_ 12.32 *CONN -*I _661_/ZN O *D NAND2_X1 -*I _663_/A I *D OAI211_X1 +*I _661_:ZN O *D NAND2_X1 +*I _663_:A I *D OAI211_X1 *CAP 1 _334_:1 0.995 2 _334_:2 2.1 @@ -9193,14 +9193,14 @@ resp_val O 2 _334_:2 _334_:3 8.4 3 _334_:3 _334_:4 0.005 4 _334_:5 _334_:4 8.4 -5 _661_/ZN _334_:5 3.865 -6 _663_/A _334_:1 3.985 +5 _661_:ZN _334_:5 3.865 +6 _663_:A _334_:1 3.985 *END *D_NET _335_ 7.71 *CONN -*I _662_/ZN O *D OAI21_X1 -*I _663_/B I *D OAI211_X1 +*I _662_:ZN O *D OAI21_X1 +*I _663_:B I *D OAI211_X1 *CAP 1 _335_:1 0.545 2 _335_:2 2.1 @@ -9210,28 +9210,28 @@ resp_val O 1 _335_:1 _335_:2 0.005 2 _335_:2 _335_:3 8.4 3 _335_:3 _335_:4 0.005 -4 _662_/ZN _335_:1 2.185 -5 _663_/B _335_:4 4.845 +4 _662_:ZN _335_:1 2.185 +5 _663_:B _335_:4 4.845 *END *D_NET _336_ 7.48 *CONN -*I _663_/ZN O *D OAI211_X1 -*I _664_/B I *D MUX2_X1 +*I _663_:ZN O *D OAI211_X1 +*I _664_:B I *D MUX2_X1 *CAP 1 _336_:1 2.615 2 _336_:2 3.225 *RES 1 _336_:2 _336_:1 8.4 -2 _663_/ZN _336_:1 2.065 -3 _664_/B _336_:2 4.505 +2 _663_:ZN _336_:1 2.065 +3 _664_:B _336_:2 4.505 *END *D_NET _337_ 19 *CONN -*I _665_/ZN O *D OR3_X1 -*I _668_/A1 I *D AND3_X1 -*I _669_/B1 I *D AOI21_X1 +*I _665_:ZN O *D OR3_X1 +*I _668_:A1 I *D AND3_X1 +*I _669_:B1 I *D AOI21_X1 *CAP 1 _337_:1 0.645 2 _337_:2 2.1 @@ -9247,16 +9247,16 @@ resp_val O 4 _337_:3 _337_:5 8.4 5 _337_:5 _337_:6 0.005 6 _337_:6 _337_:7 8.4 -7 _665_/ZN _337_:7 5.485 -8 _668_/A1 _337_:4 4.745 -9 _669_/B1 _337_:1 2.585 +7 _665_:ZN _337_:7 5.485 +8 _668_:A1 _337_:4 4.745 +9 _669_:B1 _337_:1 2.585 *END *D_NET _338_ 14.13 *CONN -*I _666_/ZN O *D INV_X1 -*I _668_/A2 I *D AND3_X1 -*I _669_/A I *D AOI21_X1 +*I _666_:ZN O *D INV_X1 +*I _668_:A2 I *D AND3_X1 +*I _669_:A I *D AOI21_X1 *CAP 1 _338_:1 2.57 2 _338_:2 2.1 @@ -9268,16 +9268,16 @@ resp_val O 2 _338_:2 _338_:3 8.4 3 _338_:3 _338_:4 0.005 4 _338_:1 _338_:5 8.4 -5 _666_/ZN _338_:5 5.605 -6 _668_/A2 _338_:4 3.985 -7 _669_/A _338_:1 1.885 +5 _666_:ZN _338_:5 5.605 +6 _668_:A2 _338_:4 3.985 +7 _669_:A _338_:1 1.885 *END *D_NET _339_ 19.36 *CONN -*I _667_/ZN O *D AOI22_X1 -*I _668_/A3 I *D AND3_X1 -*I _669_/B2 I *D AOI21_X1 +*I _667_:ZN O *D AOI22_X1 +*I _668_:A3 I *D AND3_X1 +*I _669_:B2 I *D AOI21_X1 *CAP 1 _339_:1 0.985 2 _339_:2 2.1 @@ -9293,15 +9293,15 @@ resp_val O 4 _339_:3 _339_:5 8.4 5 _339_:5 _339_:6 0.005 6 _339_:7 _339_:6 8.4 -7 _667_/ZN _339_:7 6.365 -8 _668_/A3 _339_:4 3.225 -9 _669_/B2 _339_:1 3.945 +7 _667_:ZN _339_:7 6.365 +8 _668_:A3 _339_:4 3.225 +9 _669_:B2 _339_:1 3.945 *END *D_NET _340_ 8.93 *CONN -*I _668_/ZN O *D AND3_X1 -*I _670_/A1 I *D NOR2_X1 +*I _668_:ZN O *D AND3_X1 +*I _670_:A1 I *D NOR2_X1 *CAP 1 _340_:1 1.895 2 _340_:2 2.1 @@ -9311,29 +9311,29 @@ resp_val O 1 _340_:1 _340_:2 0.005 2 _340_:2 _340_:3 8.4 3 _340_:3 _340_:4 0.005 -4 _668_/ZN _340_:4 1.885 -5 _670_/A1 _340_:1 7.585 +4 _668_:ZN _340_:4 1.885 +5 _670_:A1 _340_:1 7.585 *END *D_NET _341_ 14.77 *CONN -*I _669_/ZN O *D AOI21_X1 -*I _670_/A2 I *D NOR2_X1 -*I _676_/A1 I *D NOR2_X1 +*I _669_:ZN O *D AOI21_X1 +*I _670_:A2 I *D NOR2_X1 +*I _676_:A1 I *D NOR2_X1 *CAP 1 _341_:1 6.38 2 _341_:2 5.205 *RES 1 _341_:1 _341_:2 16.8 -2 _669_/ZN _341_:1 2.445 -3 _670_/A2 _341_:1 6.285 -4 _676_/A1 _341_:2 4.025 +2 _669_:ZN _341_:1 2.445 +3 _670_:A2 _341_:1 6.285 +4 _676_:A1 _341_:2 4.025 *END *D_NET _342_ 18.94 *CONN -*I _671_/ZN O *D NAND2_X1 -*I _673_/A I *D OAI211_X1 +*I _671_:ZN O *D NAND2_X1 +*I _673_:A I *D OAI211_X1 *CAP 1 _342_:1 4.035 2 _342_:2 2.1 @@ -9345,14 +9345,14 @@ resp_val O 2 _342_:2 _342_:3 0.005 3 _342_:3 _342_:4 16.8 4 _342_:4 _342_:5 0.005 -5 _671_/ZN _342_:5 4.945 -6 _673_/A _342_:1 7.745 +5 _671_:ZN _342_:5 4.945 +6 _673_:A _342_:1 7.745 *END *D_NET _343_ 18.81 *CONN -*I _672_/ZN O *D OAI21_X1 -*I _673_/B I *D OAI211_X1 +*I _672_:ZN O *D OAI21_X1 +*I _673_:B I *D OAI211_X1 *CAP 1 _343_:1 3.155 2 _343_:2 2.1 @@ -9364,14 +9364,14 @@ resp_val O 2 _343_:2 _343_:3 0.005 3 _343_:3 _343_:4 16.8 4 _343_:4 _343_:5 0.005 -5 _672_/ZN _343_:1 4.225 -6 _673_/B _343_:5 8.205 +5 _672_:ZN _343_:1 4.225 +6 _673_:B _343_:5 8.205 *END *D_NET _344_ 9.72 *CONN -*I _673_/ZN O *D OAI211_X1 -*I _674_/B I *D MUX2_X1 +*I _673_:ZN O *D OAI211_X1 +*I _674_:B I *D MUX2_X1 *CAP 1 _344_:1 1.455 2 _344_:2 2.1 @@ -9381,27 +9381,27 @@ resp_val O 1 _344_:1 _344_:2 0.005 2 _344_:2 _344_:3 8.4 3 _344_:3 _344_:4 0.005 -4 _673_/ZN _344_:1 5.825 -5 _674_/B _344_:4 5.225 +4 _673_:ZN _344_:1 5.825 +5 _674_:B _344_:4 5.225 *END *D_NET _345_ 7.64 *CONN -*I _675_/ZN O *D NOR2_X1 -*I _676_/A2 I *D NOR2_X1 +*I _675_:ZN O *D NOR2_X1 +*I _676_:A2 I *D NOR2_X1 *CAP 1 _345_:1 3.14 2 _345_:2 2.78 *RES 1 _345_:2 _345_:1 8.4 -2 _675_/ZN _345_:1 4.165 -3 _676_/A2 _345_:2 2.725 +2 _675_:ZN _345_:1 4.165 +3 _676_:A2 _345_:2 2.725 *END *D_NET _346_ 11.02 *CONN -*I _676_/ZN O *D NOR2_X1 -*I _677_/A I *D XNOR2_X1 +*I _676_:ZN O *D NOR2_X1 +*I _677_:A I *D XNOR2_X1 *CAP 1 _346_:1 2.625 2 _346_:2 2.1 @@ -9413,14 +9413,14 @@ resp_val O 2 _346_:2 _346_:3 0.005 3 _346_:3 _346_:4 8.4 4 _346_:4 _346_:5 0.005 -5 _676_/ZN _346_:1 2.105 -6 _677_/A _346_:5 3.145 +5 _676_:ZN _346_:1 2.105 +6 _677_:A _346_:5 3.145 *END *D_NET _347_ 16.32 *CONN -*I _678_/ZN O *D AND2_X1 -*I _681_/B1 I *D OAI21_X1 +*I _678_:ZN O *D AND2_X1 +*I _681_:B1 I *D OAI21_X1 *CAP 1 _347_:1 1.34 2 _347_:2 4.2 @@ -9432,14 +9432,14 @@ resp_val O 2 _347_:2 _347_:3 16.8 3 _347_:3 _347_:4 0.005 4 _347_:4 _347_:5 8.4 -5 _678_/ZN _347_:1 5.365 -6 _681_/B1 _347_:5 2.085 +5 _678_:ZN _347_:1 5.365 +6 _681_:B1 _347_:5 2.085 *END *D_NET _348_ 58.08 *CONN -*I _679_/ZN O *D OAI21_X1 -*I _680_/A I *D OAI21_X1 +*I _679_:ZN O *D OAI21_X1 +*I _680_:A I *D OAI21_X1 *CAP 1 _348_:1 25.955 2 _348_:2 25.2 @@ -9451,14 +9451,14 @@ resp_val O 2 _348_:2 _348_:3 0.005 3 _348_:3 _348_:4 8.4 4 _348_:4 _348_:5 0.005 -5 _679_/ZN _348_:5 3.945 -6 _680_/A _348_:1 3.025 +5 _679_:ZN _348_:5 3.945 +6 _680_:A _348_:1 3.025 *END *D_NET _349_ 11.22 *CONN -*I _680_/ZN O *D OAI21_X1 -*I _681_/B2 I *D OAI21_X1 +*I _680_:ZN O *D OAI21_X1 +*I _681_:B2 I *D OAI21_X1 *CAP 1 _349_:1 2.945 2 _349_:2 2.1 @@ -9470,27 +9470,27 @@ resp_val O 2 _349_:2 _349_:3 0.005 3 _349_:3 _349_:4 8.4 4 _349_:4 _349_:5 0.005 -5 _680_/ZN _349_:5 2.265 -6 _681_/B2 _349_:1 3.385 +5 _680_:ZN _349_:5 2.265 +6 _681_:B2 _349_:1 3.385 *END *D_NET _350_ 7.82 *CONN -*I _681_/ZN O *D OAI21_X1 -*I _682_/A I *D OAI21_X1 +*I _681_:ZN O *D OAI21_X1 +*I _682_:A I *D OAI21_X1 *CAP 1 _350_:1 2.645 2 _350_:2 3.365 *RES 1 _350_:1 _350_:2 8.4 -2 _681_/ZN _350_:1 2.185 -3 _682_/A _350_:2 5.065 +2 _681_:ZN _350_:1 2.185 +3 _682_:A _350_:2 5.065 *END *D_NET _351_ 20.85 *CONN -*I _683_/Z O *D MUX2_X1 -*I _686_/B I *D MUX2_X1 +*I _683_:Z O *D MUX2_X1 +*I _686_:B I *D MUX2_X1 *CAP 1 _351_:1 1.645 2 _351_:2 4.2 @@ -9502,20 +9502,20 @@ resp_val O 2 _351_:2 _351_:3 16.8 3 _351_:3 _351_:4 0.005 4 _351_:4 _351_:5 8.4 -5 _683_/Z _351_:5 9.925 -6 _686_/B _351_:1 6.585 +5 _683_:Z _351_:5 9.925 +6 _686_:B _351_:1 6.585 *END *D_NET _352_ 152.45 *CONN -*I _684_/ZN O *D NAND2_X2 -*I _685_/A I *D BUF_X2 -*I _706_/S I *D MUX2_X1 -*I _708_/S I *D MUX2_X1 -*I _710_/S I *D MUX2_X1 -*I _712_/S I *D MUX2_X1 -*I _714_/S I *D MUX2_X1 -*I _716_/S I *D MUX2_X1 +*I _684_:ZN O *D NAND2_X2 +*I _685_:A I *D BUF_X2 +*I _706_:S I *D MUX2_X1 +*I _708_:S I *D MUX2_X1 +*I _710_:S I *D MUX2_X1 +*I _712_:S I *D MUX2_X1 +*I _714_:S I *D MUX2_X1 +*I _716_:S I *D MUX2_X1 *CAP 1 _352_:1 12.915 2 _352_:2 14.7 @@ -9561,29 +9561,29 @@ resp_val O 19 _352_:14 _352_:21 25.2 20 _352_:21 _352_:22 0.005 21 _352_:20 _352_:22 25.2 -22 _684_/ZN _352_:11 4.245 -23 _685_/A _352_:15 4.145 -24 _706_/S _352_:3 7.185 -25 _708_/S _352_:19 2.345 -26 _710_/S _352_:10 3.185 -27 _712_/S _352_:1 1.265 -28 _714_/S _352_:16 4.865 -29 _716_/S _352_:20 8.905 +22 _684_:ZN _352_:11 4.245 +23 _685_:A _352_:15 4.145 +24 _706_:S _352_:3 7.185 +25 _708_:S _352_:19 2.345 +26 _710_:S _352_:10 3.185 +27 _712_:S _352_:1 1.265 +28 _714_:S _352_:16 4.865 +29 _716_:S _352_:20 8.905 *END *D_NET _353_ 291.37 *CONN -*I _685_/Z O *D BUF_X2 -*I _686_/S I *D MUX2_X1 -*I _688_/S I *D MUX2_X1 -*I _690_/S I *D MUX2_X1 -*I _692_/S I *D MUX2_X1 -*I _694_/S I *D MUX2_X1 -*I _696_/S I *D MUX2_X1 -*I _698_/S I *D MUX2_X1 -*I _700_/S I *D MUX2_X1 -*I _702_/S I *D MUX2_X1 -*I _704_/S I *D MUX2_X1 +*I _685_:Z O *D BUF_X2 +*I _686_:S I *D MUX2_X1 +*I _688_:S I *D MUX2_X1 +*I _690_:S I *D MUX2_X1 +*I _692_:S I *D MUX2_X1 +*I _694_:S I *D MUX2_X1 +*I _696_:S I *D MUX2_X1 +*I _698_:S I *D MUX2_X1 +*I _700_:S I *D MUX2_X1 +*I _702_:S I *D MUX2_X1 +*I _704_:S I *D MUX2_X1 *CAP 1 _353_:1 9.065 2 _353_:2 9.285 @@ -9649,48 +9649,48 @@ resp_val O 29 _353_:30 _353_:31 58.8 30 _353_:31 _353_:32 0.005 31 _353_:32 _353_:13 16.8 -32 _685_/Z _353_:13 7.265 -33 _686_/S _353_:2 3.545 -34 _688_/S _353_:14 6.745 -35 _690_/S _353_:3 7.145 -36 _692_/S _353_:7 2.625 -37 _694_/S _353_:22 2.185 -38 _696_/S _353_:23 4.145 -39 _698_/S _353_:18 10.025 -40 _700_/S _353_:1 2.665 -41 _702_/S _353_:8 3.065 -42 _704_/S _353_:12 4.185 +32 _685_:Z _353_:13 7.265 +33 _686_:S _353_:2 3.545 +34 _688_:S _353_:14 6.745 +35 _690_:S _353_:3 7.145 +36 _692_:S _353_:7 2.625 +37 _694_:S _353_:22 2.185 +38 _696_:S _353_:23 4.145 +39 _698_:S _353_:18 10.025 +40 _700_:S _353_:1 2.665 +41 _702_:S _353_:8 3.065 +42 _704_:S _353_:12 4.185 *END *D_NET _354_ 6.64 *CONN -*I _687_/Z O *D MUX2_X1 -*I _688_/B I *D MUX2_X1 +*I _687_:Z O *D MUX2_X1 +*I _688_:B I *D MUX2_X1 *CAP 1 _354_:1 2.53 2 _354_:2 2.89 *RES 1 _354_:1 _354_:2 8.4 -2 _687_/Z _354_:1 1.725 -3 _688_/B _354_:2 3.165 +2 _687_:Z _354_:1 1.725 +3 _688_:B _354_:2 3.165 *END *D_NET _355_ 5.09 *CONN -*I _689_/Z O *D MUX2_X1 -*I _690_/B I *D MUX2_X1 +*I _689_:Z O *D MUX2_X1 +*I _690_:B I *D MUX2_X1 *CAP 1 _355_:1 2.545 *RES 1 _355_:1 _355_:1 0.005 -2 _689_/Z _355_:1 6.085 -3 _690_/B _355_:1 4.105 +2 _689_:Z _355_:1 6.085 +3 _690_:B _355_:1 4.105 *END *D_NET _356_ 13.08 *CONN -*I _691_/Z O *D MUX2_X1 -*I _692_/B I *D MUX2_X1 +*I _691_:Z O *D MUX2_X1 +*I _692_:B I *D MUX2_X1 *CAP 1 _356_:1 1.09 2 _356_:2 2.1 @@ -9702,14 +9702,14 @@ resp_val O 2 _356_:2 _356_:3 8.4 3 _356_:3 _356_:4 0.005 4 _356_:5 _356_:4 8.4 -5 _691_/Z _356_:1 4.365 -6 _692_/B _356_:5 5.005 +5 _691_:Z _356_:1 4.365 +6 _692_:B _356_:5 5.005 *END *D_NET _357_ 8.05 *CONN -*I _693_/Z O *D MUX2_X1 -*I _694_/B I *D MUX2_X1 +*I _693_:Z O *D MUX2_X1 +*I _694_:B I *D MUX2_X1 *CAP 1 _357_:1 1.265 2 _357_:2 2.1 @@ -9719,27 +9719,27 @@ resp_val O 1 _357_:1 _357_:2 0.005 2 _357_:2 _357_:3 8.4 3 _357_:3 _357_:4 0.005 -4 _693_/Z _357_:4 2.645 -5 _694_/B _357_:1 5.065 +4 _693_:Z _357_:4 2.645 +5 _694_:B _357_:1 5.065 *END *D_NET _358_ 7.46 *CONN -*I _695_/Z O *D MUX2_X1 -*I _696_/B I *D MUX2_X1 +*I _695_:Z O *D MUX2_X1 +*I _696_:B I *D MUX2_X1 *CAP 1 _358_:1 2.59 2 _358_:2 3.24 *RES 1 _358_:1 _358_:2 8.4 -2 _695_/Z _358_:1 1.965 -3 _696_/B _358_:2 4.565 +2 _695_:Z _358_:1 1.965 +3 _696_:B _358_:2 4.565 *END *D_NET _359_ 12.77 *CONN -*I _697_/Z O *D MUX2_X1 -*I _698_/B I *D MUX2_X1 +*I _697_:Z O *D MUX2_X1 +*I _698_:B I *D MUX2_X1 *CAP 1 _359_:1 0.79 2 _359_:2 2.1 @@ -9751,14 +9751,14 @@ resp_val O 2 _359_:2 _359_:3 8.4 3 _359_:3 _359_:4 0.005 4 _359_:5 _359_:4 8.4 -5 _697_/Z _359_:1 3.165 -6 _698_/B _359_:5 5.585 +5 _697_:Z _359_:1 3.165 +6 _698_:B _359_:5 5.585 *END *D_NET _360_ 14.56 *CONN -*I _699_/Z O *D MUX2_X1 -*I _700_/B I *D MUX2_X1 +*I _699_:Z O *D MUX2_X1 +*I _700_:B I *D MUX2_X1 *CAP 1 _360_:1 3.03 2 _360_:2 2.1 @@ -9770,14 +9770,14 @@ resp_val O 2 _360_:2 _360_:3 0.005 3 _360_:3 _360_:4 8.4 4 _360_:4 _360_:5 0.005 -5 _699_/Z _360_:5 8.605 -6 _700_/B _360_:1 3.725 +5 _699_:Z _360_:5 8.605 +6 _700_:B _360_:1 3.725 *END *D_NET _361_ 13.53 *CONN -*I _701_/Z O *D MUX2_X1 -*I _702_/B I *D MUX2_X1 +*I _701_:Z O *D MUX2_X1 +*I _702_:B I *D MUX2_X1 *CAP 1 _361_:1 1.64 2 _361_:2 2.1 @@ -9789,14 +9789,14 @@ resp_val O 2 _361_:2 _361_:3 8.4 3 _361_:3 _361_:4 0.005 4 _361_:5 _361_:4 8.4 -5 _701_/Z _361_:1 6.565 -6 _702_/B _361_:5 3.705 +5 _701_:Z _361_:1 6.565 +6 _702_:B _361_:5 3.705 *END *D_NET _362_ 15.5 *CONN -*I _703_/Z O *D MUX2_X1 -*I _704_/B I *D MUX2_X1 +*I _703_:Z O *D MUX2_X1 +*I _704_:B I *D MUX2_X1 *CAP 1 _362_:1 3 2 _362_:2 2.1 @@ -9810,14 +9810,14 @@ resp_val O 3 _362_:3 _362_:4 8.4 4 _362_:4 _362_:5 0.005 5 _362_:5 _362_:6 8.4 -6 _703_/Z _362_:1 3.605 -7 _704_/B _362_:6 2.205 +6 _703_:Z _362_:1 3.605 +7 _704_:B _362_:6 2.205 *END *D_NET _363_ 7.44 *CONN -*I _705_/Z O *D MUX2_X1 -*I _706_/B I *D MUX2_X1 +*I _705_:Z O *D MUX2_X1 +*I _706_:B I *D MUX2_X1 *CAP 1 _363_:1 1.2 2 _363_:2 2.1 @@ -9827,39 +9827,39 @@ resp_val O 1 _363_:1 _363_:2 0.005 2 _363_:2 _363_:3 8.4 3 _363_:3 _363_:4 0.005 -4 _705_/Z _363_:4 1.685 -5 _706_/B _363_:1 4.805 +4 _705_:Z _363_:4 1.685 +5 _706_:B _363_:1 4.805 *END *D_NET _364_ 12.74 *CONN -*I _707_/Z O *D MUX2_X1 -*I _708_/B I *D MUX2_X1 +*I _707_:Z O *D MUX2_X1 +*I _708_:B I *D MUX2_X1 *CAP 1 _364_:1 5.36 2 _364_:2 5.21 *RES 1 _364_:1 _364_:2 16.8 -2 _707_/Z _364_:1 4.645 -3 _708_/B _364_:2 4.045 +2 _707_:Z _364_:1 4.645 +3 _708_:B _364_:2 4.045 *END *D_NET _365_ 4.33 *CONN -*I _709_/Z O *D MUX2_X1 -*I _710_/B I *D MUX2_X1 +*I _709_:Z O *D MUX2_X1 +*I _710_:B I *D MUX2_X1 *CAP 1 _365_:1 2.165 *RES 1 _365_:1 _365_:1 0.005 -2 _709_/Z _365_:1 2.285 -3 _710_/B _365_:1 6.385 +2 _709_:Z _365_:1 2.285 +3 _710_:B _365_:1 6.385 *END *D_NET _366_ 9.46 *CONN -*I _711_/Z O *D MUX2_X1 -*I _712_/B I *D MUX2_X1 +*I _711_:Z O *D MUX2_X1 +*I _712_:B I *D MUX2_X1 *CAP 1 _366_:1 1.01 2 _366_:2 2.1 @@ -9869,14 +9869,14 @@ resp_val O 1 _366_:1 _366_:2 0.005 2 _366_:2 _366_:3 8.4 3 _366_:3 _366_:4 0.005 -4 _711_/Z _366_:4 6.485 -5 _712_/B _366_:1 4.045 +4 _711_:Z _366_:4 6.485 +5 _712_:B _366_:1 4.045 *END *D_NET _367_ 17.2 *CONN -*I _713_/Z O *D MUX2_X1 -*I _714_/B I *D MUX2_X1 +*I _713_:Z O *D MUX2_X1 +*I _714_:B I *D MUX2_X1 *CAP 1 _367_:1 2.62 2 _367_:2 2.1 @@ -9890,14 +9890,14 @@ resp_val O 3 _367_:3 _367_:4 8.4 4 _367_:4 _367_:5 0.005 5 _367_:5 _367_:6 8.4 -6 _713_/Z _367_:1 2.085 -7 _714_/B _367_:6 7.125 +6 _713_:Z _367_:1 2.085 +7 _714_:B _367_:6 7.125 *END *D_NET _368_ 14.54 *CONN -*I _715_/Z O *D MUX2_X1 -*I _716_/B I *D MUX2_X1 +*I _715_:Z O *D MUX2_X1 +*I _716_:B I *D MUX2_X1 *CAP 1 _368_:1 1.74 2 _368_:2 2.1 @@ -9909,14 +9909,14 @@ resp_val O 2 _368_:2 _368_:3 8.4 3 _368_:3 _368_:4 0.005 4 _368_:5 _368_:4 8.4 -5 _715_/Z _368_:1 6.965 -6 _716_/B _368_:5 5.325 +5 _715_:Z _368_:1 6.965 +6 _716_:B _368_:5 5.325 *END *D_NET _369_ 13.47 *CONN -*I _683_/B I *D MUX2_X1 -*I _811_/Z O *D CLKBUF_X1 +*I _683_:B I *D MUX2_X1 +*I _811_:Z O *D CLKBUF_X1 *CAP 1 _369_:1 1.435 2 _369_:2 4.2 @@ -9926,14 +9926,14 @@ resp_val O 1 _369_:1 _369_:2 0.005 2 _369_:2 _369_:3 16.8 3 _369_:3 _369_:4 0.005 -4 _683_/B _369_:1 5.745 -5 _811_/Z _369_:4 4.405 +4 _683_:B _369_:1 5.745 +5 _811_:Z _369_:4 4.405 *END *D_NET _370_ 146.79 *CONN -*I _705_/B I *D MUX2_X1 -*I _831_/Z O *D CLKBUF_X1 +*I _705_:B I *D MUX2_X1 +*I _831_:Z O *D CLKBUF_X1 *CAP 1 _370_:1 55.395 2 _370_:2 54.6 @@ -9945,27 +9945,27 @@ resp_val O 2 _370_:2 _370_:3 0.005 3 _370_:3 _370_:4 67.2 4 _370_:4 _370_:5 0.005 -5 _705_/B _370_:1 3.185 -6 _831_/Z _370_:5 4.805 +5 _705_:B _370_:1 3.185 +6 _831_:Z _370_:5 4.805 *END *D_NET _371_ 42.84 *CONN -*I _707_/B I *D MUX2_X1 -*I _833_/Z O *D CLKBUF_X1 +*I _707_:B I *D MUX2_X1 +*I _833_:Z O *D CLKBUF_X1 *CAP 1 _371_:1 20.09 2 _371_:2 20.23 *RES 1 _371_:1 _371_:2 75.6 -2 _707_/B _371_:2 5.325 -3 _833_/Z _371_:1 4.765 +2 _707_:B _371_:2 5.325 +3 _833_:Z _371_:1 4.765 *END *D_NET _372_ 108.62 *CONN -*I _709_/B I *D MUX2_X1 -*I _835_/Z O *D CLKBUF_X1 +*I _709_:B I *D MUX2_X1 +*I _835_:Z O *D CLKBUF_X1 *CAP 1 _372_:1 51.76 2 _372_:2 50.4 @@ -9977,14 +9977,14 @@ resp_val O 2 _372_:2 _372_:3 0.005 3 _372_:3 _372_:4 8.4 4 _372_:4 _372_:5 0.005 -5 _709_/B _372_:1 5.445 -6 _835_/Z _372_:5 1.805 +5 _709_:B _372_:1 5.445 +6 _835_:Z _372_:5 1.805 *END *D_NET _373_ 8.47 *CONN -*I _711_/B I *D MUX2_X1 -*I _837_/Z O *D CLKBUF_X1 +*I _711_:B I *D MUX2_X1 +*I _837_:Z O *D CLKBUF_X1 *CAP 1 _373_:1 1.175 2 _373_:2 2.1 @@ -9994,14 +9994,14 @@ resp_val O 1 _373_:1 _373_:2 0.005 2 _373_:2 _373_:3 8.4 3 _373_:3 _373_:4 0.005 -4 _711_/B _373_:1 4.705 -5 _837_/Z _373_:4 3.845 +4 _711_:B _373_:1 4.705 +5 _837_:Z _373_:4 3.845 *END *D_NET _374_ 17.02 *CONN -*I _713_/B I *D MUX2_X1 -*I _839_/Z O *D CLKBUF_X1 +*I _713_:B I *D MUX2_X1 +*I _839_:Z O *D CLKBUF_X1 *CAP 1 _374_:1 1.84 2 _374_:2 4.2 @@ -10013,14 +10013,14 @@ resp_val O 2 _374_:2 _374_:3 16.8 3 _374_:3 _374_:4 0.005 4 _374_:4 _374_:5 8.4 -5 _713_/B _374_:5 1.485 -6 _839_/Z _374_:1 7.365 +5 _713_:B _374_:5 1.485 +6 _839_:Z _374_:1 7.365 *END *D_NET _375_ 75.04 *CONN -*I _715_/B I *D MUX2_X1 -*I _841_/Z O *D CLKBUF_X1 +*I _715_:B I *D MUX2_X1 +*I _841_:Z O *D CLKBUF_X1 *CAP 1 _375_:1 0.59 2 _375_:2 35.7 @@ -10030,14 +10030,14 @@ resp_val O 1 _375_:1 _375_:2 0.005 2 _375_:2 _375_:3 142.8 3 _375_:3 _375_:4 0.005 -4 _715_/B _375_:4 4.925 -5 _841_/Z _375_:1 2.365 +4 _715_:B _375_:4 4.925 +5 _841_:Z _375_:1 2.365 *END *D_NET _376_ 50.63 *CONN -*I _467_/A I *D OAI21_X1 -*I _764_/Z O *D CLKBUF_X1 +*I _467_:A I *D OAI21_X1 +*I _764_:Z O *D CLKBUF_X1 *CAP 1 _376_:1 19.955 2 _376_:2 18.9 @@ -10049,14 +10049,14 @@ resp_val O 2 _376_:2 _376_:3 0.005 3 _376_:3 _376_:4 16.8 4 _376_:4 _376_:5 0.005 -5 _467_/A _376_:1 4.225 -6 _764_/Z _376_:5 4.645 +5 _467_:A _376_:1 4.225 +6 _764_:Z _376_:5 4.645 *END *D_NET _377_ 75.99 *CONN -*I _552_/A I *D OAI21_X1 -*I _767_/Z O *D CLKBUF_X1 +*I _552_:A I *D OAI21_X1 +*I _767_:Z O *D CLKBUF_X1 *CAP 1 _377_:1 4.2 2 _377_:2 5.285 @@ -10068,14 +10068,14 @@ resp_val O 2 _377_:1 _377_:3 0.005 3 _377_:3 _377_:4 126 4 _377_:4 _377_:5 0.005 -5 _552_/A _377_:2 4.345 -6 _767_/Z _377_:5 4.845 +5 _552_:A _377_:2 4.345 +6 _767_:Z _377_:5 4.845 *END *D_NET _378_ 36.2 *CONN -*I _561_/A I *D OAI21_X1 -*I _770_/Z O *D CLKBUF_X1 +*I _561_:A I *D OAI21_X1 +*I _770_:Z O *D CLKBUF_X1 *CAP 1 _378_:1 3.55 2 _378_:2 2.1 @@ -10089,14 +10089,14 @@ resp_val O 3 _378_:3 _378_:4 42 4 _378_:4 _378_:5 0.005 5 _378_:6 _378_:5 8.4 -6 _561_/A _378_:6 7.805 -7 _770_/Z _378_:1 5.805 +6 _561_:A _378_:6 7.805 +7 _770_:Z _378_:1 5.805 *END *D_NET _379_ 23.68 *CONN -*I _567_/A I *D OAI21_X1 -*I _773_/Z O *D CLKBUF_X1 +*I _567_:A I *D OAI21_X1 +*I _773_:Z O *D CLKBUF_X1 *CAP 1 _379_:1 7.21 2 _379_:2 6.3 @@ -10108,14 +10108,14 @@ resp_val O 2 _379_:2 _379_:3 0.005 3 _379_:3 _379_:4 8.4 4 _379_:4 _379_:5 0.005 -5 _567_/A _379_:1 3.645 -6 _773_/Z _379_:5 10.125 +5 _567_:A _379_:1 3.645 +6 _773_:Z _379_:5 10.125 *END *D_NET _380_ 100.31 *CONN -*I _687_/B I *D MUX2_X1 -*I _813_/Z O *D CLKBUF_X1 +*I _687_:B I *D MUX2_X1 +*I _813_:Z O *D CLKBUF_X1 *CAP 1 _380_:1 45.15 2 _380_:2 44.1 @@ -10127,14 +10127,14 @@ resp_val O 2 _380_:2 _380_:3 0.005 3 _380_:3 _380_:4 16.8 4 _380_:4 _380_:5 0.005 -5 _687_/B _380_:5 3.225 -6 _813_/Z _380_:1 4.205 +5 _687_:B _380_:5 3.225 +6 _813_:Z _380_:1 4.205 *END *D_NET _381_ 117.45 *CONN -*I _576_/A I *D OAI21_X1 -*I _776_/Z O *D CLKBUF_X1 +*I _576_:A I *D OAI21_X1 +*I _776_:Z O *D CLKBUF_X1 *CAP 1 _381_:1 5.03 2 _381_:2 4.2 @@ -10146,14 +10146,14 @@ resp_val O 2 _381_:2 _381_:3 0.005 3 _381_:3 _381_:4 210 4 _381_:4 _381_:5 0.005 -5 _576_/A _381_:5 4.785 -6 _776_/Z _381_:1 3.325 +5 _576_:A _381_:5 4.785 +6 _776_:Z _381_:1 3.325 *END *D_NET _382_ 34.18 *CONN -*I _585_/A I *D OAI21_X1 -*I _779_/Z O *D CLKBUF_X1 +*I _585_:A I *D OAI21_X1 +*I _779_:Z O *D CLKBUF_X1 *CAP 1 _382_:1 1.32 2 _382_:2 12.6 @@ -10165,14 +10165,14 @@ resp_val O 2 _382_:2 _382_:3 50.4 3 _382_:3 _382_:4 0.005 4 _382_:4 _382_:5 8.4 -5 _585_/A _382_:1 5.285 -6 _779_/Z _382_:5 4.285 +5 _585_:A _382_:1 5.285 +6 _779_:Z _382_:5 4.285 *END *D_NET _383_ 15.12 *CONN -*I _593_/A I *D OAI21_X1 -*I _782_/Z O *D CLKBUF_X1 +*I _593_:A I *D OAI21_X1 +*I _782_:Z O *D CLKBUF_X1 *CAP 1 _383_:1 4.2 2 _383_:2 4.77 @@ -10184,14 +10184,14 @@ resp_val O 2 _383_:1 _383_:3 0.005 3 _383_:3 _383_:4 8.4 4 _383_:4 _383_:5 0.005 -5 _593_/A _383_:2 2.285 -6 _782_/Z _383_:5 2.765 +5 _593_:A _383_:2 2.285 +6 _782_:Z _383_:5 2.765 *END *D_NET _384_ 69.22 *CONN -*I _601_/A I *D OAI21_X1 -*I _785_/Z O *D CLKBUF_X1 +*I _601_:A I *D OAI21_X1 +*I _785_:Z O *D CLKBUF_X1 *CAP 1 _384_:1 29.4 2 _384_:2 29.73 @@ -10203,14 +10203,14 @@ resp_val O 2 _384_:1 _384_:3 0.005 3 _384_:3 _384_:4 16.8 4 _384_:4 _384_:5 0.005 -5 _601_/A _384_:5 2.725 -6 _785_/Z _384_:2 1.325 +5 _601_:A _384_:5 2.725 +6 _785_:Z _384_:2 1.325 *END *D_NET _385_ 95.23 *CONN -*I _610_/A I *D OAI21_X1 -*I _788_/Z O *D CLKBUF_X1 +*I _610_:A I *D OAI21_X1 +*I _788_:Z O *D CLKBUF_X1 *CAP 1 _385_:1 1.145 2 _385_:2 46.2 @@ -10220,14 +10220,14 @@ resp_val O 1 _385_:1 _385_:2 0.005 2 _385_:2 _385_:3 184.8 3 _385_:3 _385_:4 0.005 -4 _610_/A _385_:1 4.585 -5 _788_/Z _385_:4 1.085 +4 _610_:A _385_:1 4.585 +5 _788_:Z _385_:4 1.085 *END *D_NET _386_ 43.56 *CONN -*I _619_/A I *D OAI21_X1 -*I _791_/Z O *D CLKBUF_X1 +*I _619_:A I *D OAI21_X1 +*I _791_:Z O *D CLKBUF_X1 *CAP 1 _386_:1 12.6 2 _386_:2 14.36 @@ -10241,14 +10241,14 @@ resp_val O 3 _386_:3 _386_:4 16.8 4 _386_:4 _386_:5 0.005 5 _386_:6 _386_:5 8.4 -6 _619_/A _386_:6 4.485 -7 _791_/Z _386_:2 7.045 +6 _619_:A _386_:6 4.485 +7 _791_:Z _386_:2 7.045 *END *D_NET _387_ 13.5 *CONN -*I _628_/A I *D OAI21_X1 -*I _794_/Z O *D CLKBUF_X1 +*I _628_:A I *D OAI21_X1 +*I _794_:Z O *D CLKBUF_X1 *CAP 1 _387_:1 3.07 2 _387_:2 2.1 @@ -10260,27 +10260,27 @@ resp_val O 2 _387_:2 _387_:3 0.005 3 _387_:3 _387_:4 8.4 4 _387_:4 _387_:5 0.005 -5 _628_/A _387_:5 6.325 -6 _794_/Z _387_:1 3.885 +5 _628_:A _387_:5 6.325 +6 _794_:Z _387_:1 3.885 *END *D_NET _388_ 91.83 *CONN -*I _637_/A I *D OAI21_X1 -*I _797_/Z O *D CLKBUF_X1 +*I _637_:A I *D OAI21_X1 +*I _797_:Z O *D CLKBUF_X1 *CAP 1 _388_:1 44.655 2 _388_:2 45.36 *RES 1 _388_:1 _388_:2 176.4 -2 _637_/A _388_:1 2.225 -3 _797_/Z _388_:2 5.045 +2 _637_:A _388_:1 2.225 +3 _797_:Z _388_:2 5.045 *END *D_NET _389_ 75.76 *CONN -*I _654_/A I *D OAI21_X1 -*I _800_/Z O *D CLKBUF_X1 +*I _654_:A I *D OAI21_X1 +*I _800_:Z O *D CLKBUF_X1 *CAP 1 _389_:1 5.18 2 _389_:2 4.2 @@ -10292,27 +10292,27 @@ resp_val O 2 _389_:2 _389_:3 0.005 3 _389_:3 _389_:4 126 4 _389_:4 _389_:5 0.005 -5 _654_/A _389_:5 4.805 -6 _800_/Z _389_:1 3.925 +5 _654_:A _389_:5 4.805 +6 _800_:Z _389_:1 3.925 *END *D_NET _390_ 15.39 *CONN -*I _662_/A I *D OAI21_X1 -*I _803_/Z O *D CLKBUF_X1 +*I _662_:A I *D OAI21_X1 +*I _803_:Z O *D CLKBUF_X1 *CAP 1 _390_:1 6.69 2 _390_:2 5.205 *RES 1 _390_:1 _390_:2 16.8 -2 _662_/A _390_:2 4.025 -3 _803_/Z _390_:1 9.965 +2 _662_:A _390_:2 4.025 +3 _803_:Z _390_:1 9.965 *END *D_NET _391_ 60.04 *CONN -*I _689_/B I *D MUX2_X1 -*I _815_/Z O *D CLKBUF_X1 +*I _689_:B I *D MUX2_X1 +*I _815_:Z O *D CLKBUF_X1 *CAP 1 _391_:1 3.79 2 _391_:2 2.1 @@ -10324,14 +10324,14 @@ resp_val O 2 _391_:2 _391_:3 0.005 3 _391_:3 _391_:4 100.8 4 _391_:4 _391_:5 0.005 -5 _689_/B _391_:1 6.765 -6 _815_/Z _391_:5 4.125 +5 _689_:B _391_:1 6.765 +6 _815_:Z _391_:5 4.125 *END *D_NET _392_ 146.71 *CONN -*I _672_/A I *D OAI21_X1 -*I _806_/Z O *D CLKBUF_X1 +*I _672_:A I *D OAI21_X1 +*I _806_:Z O *D CLKBUF_X1 *CAP 1 _392_:1 60.9 2 _392_:2 61.61 @@ -10343,14 +10343,14 @@ resp_val O 2 _392_:1 _392_:3 0.005 3 _392_:3 _392_:4 42 4 _392_:4 _392_:5 0.005 -5 _672_/A _392_:5 4.985 -6 _806_/Z _392_:2 2.845 +5 _672_:A _392_:5 4.985 +6 _806_:Z _392_:2 2.845 *END *D_NET _393_ 44.83 *CONN -*I _679_/A I *D OAI21_X1 -*I _809_/Z O *D CLKBUF_X1 +*I _679_:A I *D OAI21_X1 +*I _809_:Z O *D CLKBUF_X1 *CAP 1 _393_:1 0.525 2 _393_:2 2.1 @@ -10362,14 +10362,14 @@ resp_val O 2 _393_:2 _393_:3 8.4 3 _393_:3 _393_:4 0.005 4 _393_:4 _393_:5 75.6 -5 _679_/A _393_:1 2.105 -6 _809_/Z _393_:5 3.565 +5 _679_:A _393_:1 2.105 +6 _809_:Z _393_:5 3.565 *END *D_NET _394_ 124.29 *CONN -*I _691_/B I *D MUX2_X1 -*I _817_/Z O *D CLKBUF_X1 +*I _691_:B I *D MUX2_X1 +*I _817_:Z O *D CLKBUF_X1 *CAP 1 _394_:1 12.6 2 _394_:2 13.19 @@ -10381,14 +10381,14 @@ resp_val O 2 _394_:1 _394_:3 0.005 3 _394_:3 _394_:4 193.2 4 _394_:4 _394_:5 0.005 -5 _691_/B _394_:5 2.625 -6 _817_/Z _394_:2 2.365 +5 _691_:B _394_:5 2.625 +6 _817_:Z _394_:2 2.365 *END *D_NET _395_ 17.4 *CONN -*I _693_/B I *D MUX2_X1 -*I _819_/Z O *D CLKBUF_X1 +*I _693_:B I *D MUX2_X1 +*I _819_:Z O *D CLKBUF_X1 *CAP 1 _395_:1 1.27 2 _395_:2 4.2 @@ -10400,14 +10400,14 @@ resp_val O 2 _395_:2 _395_:3 16.8 3 _395_:3 _395_:4 0.005 4 _395_:4 _395_:5 8.4 -5 _693_/B _395_:1 5.085 -6 _819_/Z _395_:5 4.525 +5 _693_:B _395_:1 5.085 +6 _819_:Z _395_:5 4.525 *END *D_NET _396_ 82.49 *CONN -*I _695_/B I *D MUX2_X1 -*I _821_/Z O *D CLKBUF_X1 +*I _695_:B I *D MUX2_X1 +*I _821_:Z O *D CLKBUF_X1 *CAP 1 _396_:1 35.7 2 _396_:2 35.905 @@ -10419,14 +10419,14 @@ resp_val O 2 _396_:1 _396_:3 0.005 3 _396_:3 _396_:4 16.8 4 _396_:4 _396_:5 0.005 -5 _695_/B _396_:2 0.825 -6 _821_/Z _396_:5 4.565 +5 _695_:B _396_:2 0.825 +6 _821_:Z _396_:5 4.565 *END *D_NET _397_ 127.14 *CONN -*I _697_/B I *D MUX2_X1 -*I _823_/Z O *D CLKBUF_X1 +*I _697_:B I *D MUX2_X1 +*I _823_:Z O *D CLKBUF_X1 *CAP 1 _397_:1 14.67 2 _397_:2 12.6 @@ -10438,14 +10438,14 @@ resp_val O 2 _397_:2 _397_:3 0.005 3 _397_:3 _397_:4 193.2 4 _397_:4 _397_:5 0.005 -5 _697_/B _397_:5 2.405 -6 _823_/Z _397_:1 8.285 +5 _697_:B _397_:5 2.405 +6 _823_:Z _397_:1 8.285 *END *D_NET _398_ 50.59 *CONN -*I _699_/B I *D MUX2_X1 -*I _825_/Z O *D CLKBUF_X1 +*I _699_:B I *D MUX2_X1 +*I _825_:Z O *D CLKBUF_X1 *CAP 1 _398_:1 1.825 2 _398_:2 14.7 @@ -10457,14 +10457,14 @@ resp_val O 2 _398_:2 _398_:3 58.8 3 _398_:3 _398_:4 0.005 4 _398_:4 _398_:5 25.2 -5 _699_/B _398_:1 7.305 -6 _825_/Z _398_:5 9.885 +5 _699_:B _398_:1 7.305 +6 _825_:Z _398_:5 9.885 *END *D_NET _399_ 8.16 *CONN -*I _701_/B I *D MUX2_X1 -*I _827_/Z O *D CLKBUF_X1 +*I _701_:B I *D MUX2_X1 +*I _827_:Z O *D CLKBUF_X1 *CAP 1 _399_:1 1.23 2 _399_:2 2.1 @@ -10474,14 +10474,14 @@ resp_val O 1 _399_:1 _399_:2 0.005 2 _399_:2 _399_:3 8.4 3 _399_:3 _399_:4 0.005 -4 _701_/B _399_:4 3.005 -5 _827_/Z _399_:1 4.925 +4 _701_:B _399_:4 3.005 +5 _827_:Z _399_:1 4.925 *END *D_NET _400_ 41.92 *CONN -*I _703_/B I *D MUX2_X1 -*I _829_/Z O *D CLKBUF_X1 +*I _703_:B I *D MUX2_X1 +*I _829_:Z O *D CLKBUF_X1 *CAP 1 _400_:1 0.99 2 _400_:2 16.8 @@ -10493,23 +10493,23 @@ resp_val O 2 _400_:2 _400_:3 67.2 3 _400_:3 _400_:4 0.005 4 _400_:4 _400_:5 8.4 -5 _703_/B _400_:5 4.285 -6 _829_/Z _400_:1 3.965 +5 _703_:B _400_:5 4.285 +6 _829_:Z _400_:1 3.965 *END *D_NET _401_ 265.34 *CONN -*I _459_/A I *D BUF_X2 -*I _548_/A2 I *D OR2_X1 -*I _701_/S I *D MUX2_X1 -*I _703_/S I *D MUX2_X1 -*I _705_/S I *D MUX2_X1 -*I _707_/S I *D MUX2_X1 -*I _709_/S I *D MUX2_X1 -*I _711_/S I *D MUX2_X1 -*I _713_/S I *D MUX2_X1 -*I _715_/S I *D MUX2_X1 -*I _759_/Z O *D BUF_X2 +*I _459_:A I *D BUF_X2 +*I _548_:A2 I *D OR2_X1 +*I _701_:S I *D MUX2_X1 +*I _703_:S I *D MUX2_X1 +*I _705_:S I *D MUX2_X1 +*I _707_:S I *D MUX2_X1 +*I _709_:S I *D MUX2_X1 +*I _711_:S I *D MUX2_X1 +*I _713_:S I *D MUX2_X1 +*I _715_:S I *D MUX2_X1 +*I _759_:Z O *D BUF_X2 *CAP 1 _401_:1 20.005 2 _401_:2 27.3 @@ -10559,24 +10559,24 @@ resp_val O 21 _401_:18 _401_:1 75.6 22 _401_:18 _401_:24 0.005 23 _401_:24 _401_:9 50.4 -24 _459_/A _401_:5 6.805 -25 _548_/A2 _401_:1 4.425 -26 _701_/S _401_:7 3.385 -27 _703_/S _401_:6 7.705 -28 _705_/S _401_:18 3.585 -29 _707_/S _401_:8 6.665 -30 _709_/S _401_:11 9.025 -31 _711_/S _401_:13 7.745 -32 _713_/S _401_:14 3.985 -33 _715_/S _401_:20 2.425 -34 _759_/Z _401_:22 4.585 +24 _459_:A _401_:5 6.805 +25 _548_:A2 _401_:1 4.425 +26 _701_:S _401_:7 3.385 +27 _703_:S _401_:6 7.705 +28 _705_:S _401_:18 3.585 +29 _707_:S _401_:8 6.665 +30 _709_:S _401_:11 9.025 +31 _711_:S _401_:13 7.745 +32 _713_:S _401_:14 3.985 +33 _715_:S _401_:20 2.425 +34 _759_:Z _401_:22 4.585 *END *D_NET _402_ 38.12 *CONN -*I _460_/A4 I *D NAND4_X1 -*I _464_/C2 I *D AOI211_X1 -*I _760_/Z O *D CLKBUF_X1 +*I _460_:A4 I *D NAND4_X1 +*I _464_:C2 I *D AOI211_X1 +*I _760_:Z O *D CLKBUF_X1 *CAP 1 _402_:1 5.62 2 _402_:2 4.2 @@ -10594,18 +10594,18 @@ resp_val O 5 _402_:4 _402_:6 8.4 6 _402_:6 _402_:7 0.005 7 _402_:7 _402_:8 16.8 -8 _460_/A4 _402_:5 4.485 -9 _464_/C2 _402_:1 5.685 -10 _760_/Z _402_:8 7.285 +8 _460_:A4 _402_:5 4.485 +9 _464_:C2 _402_:1 5.685 +10 _760_:Z _402_:8 7.285 *END *D_NET _403_ 38.41 *CONN -*I _450_/A I *D INV_X1 -*I _454_/A2 I *D OR3_X1 -*I _464_/A I *D AOI211_X1 -*I _465_/A2 I *D OR3_X1 -*I _717_/Z O *D CLKBUF_X1 +*I _450_:A I *D INV_X1 +*I _454_:A2 I *D OR3_X1 +*I _464_:A I *D AOI211_X1 +*I _465_:A2 I *D OR3_X1 +*I _717_:Z O *D CLKBUF_X1 *CAP 1 _403_:1 3.72 2 _403_:2 3.355 @@ -10627,19 +10627,19 @@ resp_val O 7 _403_:8 _403_:9 8.4 8 _403_:9 _403_:10 0.005 9 _403_:10 _403_:7 16.8 -10 _450_/A _403_:3 2.185 -11 _454_/A2 _403_:2 5.025 -12 _464_/A _403_:6 8.305 -13 _465_/A2 _403_:1 6.485 -14 _717_/Z _403_:8 4.445 +10 _450_:A _403_:3 2.185 +11 _454_:A2 _403_:2 5.025 +12 _464_:A _403_:6 8.305 +13 _465_:A2 _403_:1 6.485 +14 _717_:Z _403_:8 4.445 *END *D_NET _404_ 55.24 *CONN -*I _440_/Z O *D XOR2_X1 -*I _537_/A2 I *D NAND4_X1 -*I _542_/A2 I *D NOR3_X1 -*I _755_/A I *D CLKBUF_X1 +*I _440_:Z O *D XOR2_X1 +*I _537_:A2 I *D NAND4_X1 +*I _542_:A2 I *D NOR3_X1 +*I _755_:A I *D CLKBUF_X1 *CAP 1 _404_:1 14.7 2 _404_:2 6.3 @@ -10657,17 +10657,17 @@ resp_val O 5 _404_:7 _404_:8 0.005 6 _404_:8 _404_:2 16.8 7 _404_:5 _404_:1 58.8 -8 _440_/Z _404_:4 2.245 -9 _537_/A2 _404_:5 4.205 -10 _542_/A2 _404_:6 6.905 -11 _755_/A _404_:7 4.745 +8 _440_:Z _404_:4 2.245 +9 _537_:A2 _404_:5 4.205 +10 _542_:A2 _404_:6 6.905 +11 _755_:A _404_:7 4.745 *END *D_NET _405_ 40.41 *CONN -*I _633_/ZN O *D XNOR2_X1 -*I _634_/A2 I *D NAND2_X1 -*I _852_/A I *D CLKBUF_X1 +*I _633_:ZN O *D XNOR2_X1 +*I _634_:A2 I *D NAND2_X1 +*I _852_:A I *D CLKBUF_X1 *CAP 1 _405_:1 2.1 2 _405_:2 12.6 @@ -10685,16 +10685,16 @@ resp_val O 5 _405_:7 _405_:6 8.4 6 _405_:7 _405_:8 0.005 7 _405_:8 _405_:2 42 -8 _633_/ZN _405_:4 6.205 -9 _634_/A2 _405_:5 2.885 -10 _852_/A _405_:6 4.545 +8 _633_:ZN _405_:4 6.205 +9 _634_:A2 _405_:5 2.885 +10 _852_:A _405_:6 4.545 *END *D_NET _406_ 44.04 *CONN -*I _643_/ZN O *D XNOR2_X1 -*I _644_/A1 I *D AND2_X1 -*I _853_/A I *D CLKBUF_X1 +*I _643_:ZN O *D XNOR2_X1 +*I _644_:A1 I *D AND2_X1 +*I _853_:A I *D CLKBUF_X1 *CAP 1 _406_:1 4.2 2 _406_:2 5.69 @@ -10712,16 +10712,16 @@ resp_val O 5 _406_:6 _406_:5 8.4 6 _406_:7 _406_:8 0.005 7 _406_:8 _406_:3 33.6 -8 _643_/ZN _406_:7 4.965 -9 _644_/A1 _406_:2 5.965 -10 _853_/A _406_:6 1.565 +8 _643_:ZN _406_:7 4.965 +9 _644_:A1 _406_:2 5.965 +10 _853_:A _406_:6 1.565 *END *D_NET _407_ 30.66 *CONN -*I _652_/ZN O *D XNOR2_X1 -*I _653_/A1 I *D NAND2_X1 -*I _854_/A I *D CLKBUF_X1 +*I _652_:ZN O *D XNOR2_X1 +*I _653_:A1 I *D NAND2_X1 +*I _854_:A I *D CLKBUF_X1 *CAP 1 _407_:1 5.365 2 _407_:2 2.1 @@ -10735,16 +10735,16 @@ resp_val O 3 _407_:3 _407_:4 16.8 4 _407_:4 _407_:5 0.005 5 _407_:6 _407_:5 16.8 -6 _652_/ZN _407_:1 5.205 -7 _653_/A1 _407_:1 7.865 -8 _854_/A _407_:6 6.265 +6 _652_:ZN _407_:1 5.205 +7 _653_:A1 _407_:1 7.865 +8 _854_:A _407_:6 6.265 *END *D_NET _408_ 32.41 *CONN -*I _660_/ZN O *D XNOR2_X1 -*I _661_/A1 I *D NAND2_X1 -*I _855_/A I *D CLKBUF_X1 +*I _660_:ZN O *D XNOR2_X1 +*I _661_:A1 I *D NAND2_X1 +*I _855_:A I *D CLKBUF_X1 *CAP 1 _408_:1 3.1 2 _408_:2 2.1 @@ -10762,16 +10762,16 @@ resp_val O 5 _408_:4 _408_:6 8.4 6 _408_:6 _408_:7 0.005 7 _408_:8 _408_:7 25.2 -8 _660_/ZN _408_:5 4.165 -9 _661_/A1 _408_:1 4.005 -10 _855_/A _408_:8 6.265 +8 _660_:ZN _408_:5 4.165 +9 _661_:A1 _408_:1 4.005 +10 _855_:A _408_:8 6.265 *END *D_NET _409_ 62.73 *CONN -*I _670_/ZN O *D NOR2_X1 -*I _671_/A1 I *D NAND2_X1 -*I _856_/A I *D CLKBUF_X1 +*I _670_:ZN O *D NOR2_X1 +*I _671_:A1 I *D NAND2_X1 +*I _856_:A I *D CLKBUF_X1 *CAP 1 _409_:1 1.2 2 _409_:2 4.2 @@ -10787,16 +10787,16 @@ resp_val O 4 _409_:3 _409_:5 84 5 _409_:5 _409_:6 0.005 6 _409_:7 _409_:6 8.4 -7 _670_/ZN _409_:4 5.665 -8 _671_/A1 _409_:1 4.805 -9 _856_/A _409_:7 5.805 +7 _670_:ZN _409_:4 5.665 +8 _671_:A1 _409_:1 4.805 +9 _856_:A _409_:7 5.805 *END *D_NET _410_ 69.36 *CONN -*I _677_/ZN O *D XNOR2_X1 -*I _678_/A1 I *D AND2_X1 -*I _857_/A I *D CLKBUF_X1 +*I _677_:ZN O *D XNOR2_X1 +*I _678_:A1 I *D AND2_X1 +*I _857_:A I *D CLKBUF_X1 *CAP 1 _410_:1 17.19 2 _410_:2 4.2 @@ -10816,16 +10816,16 @@ resp_val O 6 _410_:7 _410_:8 8.4 7 _410_:8 _410_:9 0.005 8 _410_:9 _410_:1 67.2 -9 _677_/ZN _410_:1 1.565 -10 _678_/A1 _410_:5 6.225 -11 _857_/A _410_:6 4.945 +9 _677_:ZN _410_:1 1.565 +10 _678_:A1 _410_:5 6.225 +11 _857_:A _410_:6 4.945 *END *D_NET _411_ 37.88 *CONN -*I _557_/Z O *D XOR2_X1 -*I _558_/A2 I *D NAND2_X1 -*I _843_/A I *D CLKBUF_X1 +*I _557_:Z O *D XOR2_X1 +*I _558_:A2 I *D NAND2_X1 +*I _843_:A I *D CLKBUF_X1 *CAP 1 _411_:1 4.2 2 _411_:2 5.44 @@ -10843,16 +10843,16 @@ resp_val O 5 _411_:4 _411_:6 8.4 6 _411_:6 _411_:7 0.005 7 _411_:8 _411_:7 16.8 -8 _557_/Z _411_:8 4.445 -9 _558_/A2 _411_:5 7.565 -10 _843_/A _411_:2 4.965 +8 _557_:Z _411_:8 4.445 +9 _558_:A2 _411_:5 7.565 +10 _843_:A _411_:2 4.965 *END *D_NET _412_ 34.6 *CONN -*I _563_/ZN O *D XNOR2_X1 -*I _564_/A2 I *D NAND2_X1 -*I _844_/A I *D CLKBUF_X1 +*I _563_:ZN O *D XNOR2_X1 +*I _564_:A2 I *D NAND2_X1 +*I _844_:A I *D CLKBUF_X1 *CAP 1 _412_:1 0.785 2 _412_:2 10.5 @@ -10868,16 +10868,16 @@ resp_val O 4 _412_:3 _412_:5 8.4 5 _412_:5 _412_:6 0.005 6 _412_:7 _412_:6 8.4 -7 _563_/ZN _412_:7 2.405 -8 _564_/A2 _412_:4 4.865 -9 _844_/A _412_:1 3.145 +7 _563_:ZN _412_:7 2.405 +8 _564_:A2 _412_:4 4.865 +9 _844_:A _412_:1 3.145 *END *D_NET _413_ 45.38 *CONN -*I _572_/ZN O *D XNOR2_X1 -*I _573_/A2 I *D NAND2_X1 -*I _845_/A I *D CLKBUF_X1 +*I _572_:ZN O *D XNOR2_X1 +*I _573_:A2 I *D NAND2_X1 +*I _845_:A I *D CLKBUF_X1 *CAP 1 _413_:1 2.1 2 _413_:2 3.69 @@ -10895,16 +10895,16 @@ resp_val O 5 _413_:6 _413_:5 8.4 6 _413_:7 _413_:8 0.005 7 _413_:8 _413_:3 16.8 -8 _572_/ZN _413_:7 3.525 -9 _573_/A2 _413_:2 6.365 -10 _845_/A _413_:6 5.285 +8 _572_:ZN _413_:7 3.525 +9 _573_:A2 _413_:2 6.365 +10 _845_:A _413_:6 5.285 *END *D_NET _414_ 36.89 *CONN -*I _581_/Z O *D XOR2_X1 -*I _582_/A2 I *D NAND2_X1 -*I _846_/A I *D CLKBUF_X1 +*I _581_:Z O *D XOR2_X1 +*I _582_:A2 I *D NAND2_X1 +*I _846_:A I *D CLKBUF_X1 *CAP 1 _414_:1 7.71 2 _414_:2 6.3 @@ -10920,16 +10920,16 @@ resp_val O 4 _414_:4 _414_:5 0.005 5 _414_:5 _414_:6 8.4 6 _414_:6 _414_:7 16.8 -7 _581_/Z _414_:7 7.925 -8 _582_/A2 _414_:6 1.425 -9 _846_/A _414_:1 5.645 +7 _581_:Z _414_:7 7.925 +8 _582_:A2 _414_:6 1.425 +9 _846_:A _414_:1 5.645 *END *D_NET _415_ 42.73 *CONN -*I _589_/ZN O *D AOI221_X4 -*I _590_/A2 I *D NAND2_X1 -*I _847_/A I *D CLKBUF_X1 +*I _589_:ZN O *D AOI221_X4 +*I _590_:A2 I *D NAND2_X1 +*I _847_:A I *D CLKBUF_X1 *CAP 1 _415_:1 8.065 2 _415_:2 7.585 @@ -10943,16 +10943,16 @@ resp_val O 3 _415_:3 _415_:4 33.6 4 _415_:4 _415_:5 0.005 5 _415_:6 _415_:5 8.4 -6 _589_/ZN _415_:1 7.065 -7 _590_/A2 _415_:2 5.145 -8 _847_/A _415_:6 6.065 +6 _589_:ZN _415_:1 7.065 +7 _590_:A2 _415_:2 5.145 +8 _847_:A _415_:6 6.065 *END *D_NET _416_ 28.97 *CONN -*I _597_/ZN O *D XNOR2_X1 -*I _598_/A2 I *D NAND2_X1 -*I _848_/A I *D CLKBUF_X1 +*I _597_:ZN O *D XNOR2_X1 +*I _598_:A2 I *D NAND2_X1 +*I _848_:A I *D CLKBUF_X1 *CAP 1 _416_:1 3.17 2 _416_:2 2.1 @@ -10968,16 +10968,16 @@ resp_val O 4 _416_:4 _416_:5 0.005 5 _416_:5 _416_:6 8.4 6 _416_:6 _416_:7 25.2 -7 _597_/ZN _416_:7 1.685 -8 _598_/A2 _416_:6 1.585 -9 _848_/A _416_:1 4.285 +7 _597_:ZN _416_:7 1.685 +8 _598_:A2 _416_:6 1.585 +9 _848_:A _416_:1 4.285 *END *D_NET _417_ 46.17 *CONN -*I _606_/ZN O *D XNOR2_X1 -*I _607_/A2 I *D NAND2_X1 -*I _849_/A I *D CLKBUF_X1 +*I _606_:ZN O *D XNOR2_X1 +*I _607_:A2 I *D NAND2_X1 +*I _849_:A I *D CLKBUF_X1 *CAP 1 _417_:1 7.595 2 _417_:2 2.1 @@ -10991,16 +10991,16 @@ resp_val O 3 _417_:3 _417_:4 58.8 4 _417_:4 _417_:5 0.005 5 _417_:6 _417_:1 16.8 -6 _606_/ZN _417_:6 1.645 -7 _607_/A2 _417_:1 5.185 -8 _849_/A _417_:5 1.525 +6 _606_:ZN _417_:6 1.645 +7 _607_:A2 _417_:1 5.185 +8 _849_:A _417_:5 1.525 *END *D_NET _418_ 28.25 *CONN -*I _615_/Z O *D XOR2_X1 -*I _616_/A2 I *D NAND2_X1 -*I _850_/A I *D CLKBUF_X1 +*I _615_:Z O *D XOR2_X1 +*I _616_:A2 I *D NAND2_X1 +*I _850_:A I *D CLKBUF_X1 *CAP 1 _418_:1 3.39 2 _418_:2 2.1 @@ -11016,16 +11016,16 @@ resp_val O 4 _418_:4 _418_:5 0.005 5 _418_:6 _418_:5 8.4 6 _418_:7 _418_:6 8.4 -7 _615_/Z _418_:7 6.245 -8 _616_/A2 _418_:6 3.105 -9 _850_/A _418_:1 5.165 +7 _615_:Z _418_:7 6.245 +8 _616_:A2 _418_:6 3.105 +9 _850_:A _418_:1 5.165 *END *D_NET _419_ 18.91 *CONN -*I _624_/ZN O *D AOI211_X1 -*I _625_/A1 I *D NAND2_X1 -*I _851_/A I *D CLKBUF_X1 +*I _624_:ZN O *D AOI211_X1 +*I _625_:A1 I *D NAND2_X1 +*I _851_:A I *D CLKBUF_X1 *CAP 1 _419_:1 2.93 2 _419_:2 4.2 @@ -11037,16 +11037,16 @@ resp_val O 2 _419_:2 _419_:3 16.8 3 _419_:3 _419_:4 0.005 4 _419_:1 _419_:5 8.4 -5 _624_/ZN _419_:5 4.605 -6 _625_/A1 _419_:1 3.325 -7 _851_/A _419_:4 4.705 +5 _624_:ZN _419_:5 4.605 +6 _625_:A1 _419_:1 3.325 +7 _851_:A _419_:4 4.705 *END *D_NET _420_ 28.91 *CONN -*I _453_/A2 I *D AND2_X1 -*I _462_/A3 I *D NAND3_X1 -*I _722_/Z O *D CLKBUF_X1 +*I _453_:A2 I *D AND2_X1 +*I _462_:A3 I *D NAND3_X1 +*I _722_:Z O *D CLKBUF_X1 *CAP 1 _420_:1 0.92 2 _420_:2 4.2 @@ -11064,17 +11064,17 @@ resp_val O 5 _420_:6 _420_:7 16.8 6 _420_:6 _420_:8 0.005 7 _420_:8 _420_:2 8.4 -8 _453_/A2 _420_:1 3.685 -9 _462_/A3 _420_:5 4.225 -10 _722_/Z _420_:7 7.925 +8 _453_:A2 _420_:1 3.685 +9 _462_:A3 _420_:5 4.225 +10 _722_:Z _420_:7 7.925 *END *D_NET _421_ 85.11 *CONN -*I _439_/ZN O *D AND3_X1 -*I _453_/A1 I *D AND2_X1 -*I _462_/A1 I *D NAND3_X1 -*I _721_/A I *D CLKBUF_X1 +*I _439_:ZN O *D AND3_X1 +*I _453_:A1 I *D AND2_X1 +*I _462_:A1 I *D NAND3_X1 +*I _721_:A I *D CLKBUF_X1 *CAP 1 _421_:1 0.73 2 _421_:2 2.1 @@ -11098,79 +11098,79 @@ resp_val O 8 _421_:9 _421_:10 0.005 9 _421_:11 _421_:10 8.4 10 _421_:7 _421_:5 16.8 -11 _439_/ZN _421_:7 6.005 -12 _453_/A1 _421_:1 2.925 -13 _462_/A1 _421_:5 5.745 -14 _721_/A _421_:11 4.365 +11 _439_:ZN _421_:7 6.005 +12 _453_:A1 _421_:1 2.925 +13 _462_:A1 _421_:5 5.745 +14 _721_:A _421_:11 4.365 *END *D_NET ctrl.state.out\[1\] 9.8 *CONN -*I _719_/A I *D CLKBUF_X1 -*I _859_/Q O *D DFF_X1 +*I _719_:A I *D CLKBUF_X1 +*I _859_:Q O *D DFF_X1 *CAP 1 ctrl.state.out\[1\]:1 3.08 2 ctrl.state.out\[1\]:2 3.92 *RES 1 ctrl.state.out\[1\]:2 ctrl.state.out\[1\]:1 8.4 -2 _719_/A ctrl.state.out\[1\]:2 7.285 -3 _859_/Q ctrl.state.out\[1\]:1 3.925 +2 _719_:A ctrl.state.out\[1\]:2 7.285 +3 _859_:Q ctrl.state.out\[1\]:1 3.925 *END *D_NET ctrl.state.out\[2\] 11.41 *CONN -*I _718_/A I *D CLKBUF_X1 -*I _860_/Q O *D DFF_X1 +*I _718_:A I *D CLKBUF_X1 +*I _860_:Q O *D DFF_X1 *CAP 1 ctrl.state.out\[2\]:1 4.38 2 ctrl.state.out\[2\]:2 3.425 *RES 1 ctrl.state.out\[2\]:2 ctrl.state.out\[2\]:1 8.4 -2 _718_/A ctrl.state.out\[2\]:2 5.305 -3 _860_/Q ctrl.state.out\[2\]:1 9.125 +2 _718_:A ctrl.state.out\[2\]:2 5.305 +3 _860_:Q ctrl.state.out\[2\]:1 9.125 *END *D_NET dpath.a_lt_b\$in0\[0\] 7.74 *CONN -*I _753_/A I *D CLKBUF_X1 -*I _861_/Q O *D DFF_X1 +*I _753_:A I *D CLKBUF_X1 +*I _861_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[0\]:1 2.74 2 dpath.a_lt_b\$in0\[0\]:2 3.23 *RES 1 dpath.a_lt_b\$in0\[0\]:1 dpath.a_lt_b\$in0\[0\]:2 8.4 -2 _753_/A dpath.a_lt_b\$in0\[0\]:2 4.525 -3 _861_/Q dpath.a_lt_b\$in0\[0\]:1 2.565 +2 _753_:A dpath.a_lt_b\$in0\[0\]:2 4.525 +3 _861_:Q dpath.a_lt_b\$in0\[0\]:1 2.565 *END *D_NET dpath.a_lt_b\$in0\[10\] 3.19 *CONN -*I _733_/A I *D CLKBUF_X1 -*I _871_/Q O *D DFF_X1 +*I _733_:A I *D CLKBUF_X1 +*I _871_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[10\]:1 1.595 *RES 1 dpath.a_lt_b\$in0\[10\]:1 dpath.a_lt_b\$in0\[10\]:1 0.005 -2 _733_/A dpath.a_lt_b\$in0\[10\]:1 4.505 -3 _871_/Q dpath.a_lt_b\$in0\[10\]:1 1.885 +2 _733_:A dpath.a_lt_b\$in0\[10\]:1 4.505 +3 _871_:Q dpath.a_lt_b\$in0\[10\]:1 1.885 *END *D_NET dpath.a_lt_b\$in0\[11\] 5.7 *CONN -*I _731_/A I *D CLKBUF_X1 -*I _872_/Q O *D DFF_X1 +*I _731_:A I *D CLKBUF_X1 +*I _872_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[11\]:1 2.85 *RES 1 dpath.a_lt_b\$in0\[11\]:1 dpath.a_lt_b\$in0\[11\]:1 0.005 -2 _731_/A dpath.a_lt_b\$in0\[11\]:1 7.045 -3 _872_/Q dpath.a_lt_b\$in0\[11\]:1 4.365 +2 _731_:A dpath.a_lt_b\$in0\[11\]:1 7.045 +3 _872_:Q dpath.a_lt_b\$in0\[11\]:1 4.365 *END *D_NET dpath.a_lt_b\$in0\[12\] 10.05 *CONN -*I _729_/A I *D CLKBUF_X1 -*I _873_/Q O *D DFF_X1 +*I _729_:A I *D CLKBUF_X1 +*I _873_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[12\]:1 1.005 2 dpath.a_lt_b\$in0\[12\]:2 2.1 @@ -11180,40 +11180,40 @@ resp_val O 1 dpath.a_lt_b\$in0\[12\]:1 dpath.a_lt_b\$in0\[12\]:2 0.005 2 dpath.a_lt_b\$in0\[12\]:2 dpath.a_lt_b\$in0\[12\]:3 8.4 3 dpath.a_lt_b\$in0\[12\]:3 dpath.a_lt_b\$in0\[12\]:4 0.005 -4 _729_/A dpath.a_lt_b\$in0\[12\]:1 4.025 -5 _873_/Q dpath.a_lt_b\$in0\[12\]:4 7.685 +4 _729_:A dpath.a_lt_b\$in0\[12\]:1 4.025 +5 _873_:Q dpath.a_lt_b\$in0\[12\]:4 7.685 *END *D_NET dpath.a_lt_b\$in0\[13\] 8.02 *CONN -*I _727_/A I *D BUF_X1 -*I _874_/Q O *D DFF_X1 +*I _727_:A I *D BUF_X1 +*I _874_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[13\]:1 3.02 2 dpath.a_lt_b\$in0\[13\]:2 3.09 *RES 1 dpath.a_lt_b\$in0\[13\]:1 dpath.a_lt_b\$in0\[13\]:2 8.4 -2 _727_/A dpath.a_lt_b\$in0\[13\]:2 3.965 -3 _874_/Q dpath.a_lt_b\$in0\[13\]:1 3.685 +2 _727_:A dpath.a_lt_b\$in0\[13\]:2 3.965 +3 _874_:Q dpath.a_lt_b\$in0\[13\]:1 3.685 *END *D_NET dpath.a_lt_b\$in0\[14\] 9.8 *CONN -*I _725_/A I *D CLKBUF_X1 -*I _875_/Q O *D DFF_X1 +*I _725_:A I *D CLKBUF_X1 +*I _875_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[14\]:1 3.63 2 dpath.a_lt_b\$in0\[14\]:2 3.37 *RES 1 dpath.a_lt_b\$in0\[14\]:1 dpath.a_lt_b\$in0\[14\]:2 8.4 -2 _725_/A dpath.a_lt_b\$in0\[14\]:2 5.085 -3 _875_/Q dpath.a_lt_b\$in0\[14\]:1 6.125 +2 _725_:A dpath.a_lt_b\$in0\[14\]:2 5.085 +3 _875_:Q dpath.a_lt_b\$in0\[14\]:1 6.125 *END *D_NET dpath.a_lt_b\$in0\[15\] 13.81 *CONN -*I _723_/A I *D CLKBUF_X1 -*I _876_/Q O *D DFF_X1 +*I _723_:A I *D CLKBUF_X1 +*I _876_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[15\]:1 3.655 2 dpath.a_lt_b\$in0\[15\]:2 2.1 @@ -11225,51 +11225,51 @@ resp_val O 2 dpath.a_lt_b\$in0\[15\]:2 dpath.a_lt_b\$in0\[15\]:3 0.005 3 dpath.a_lt_b\$in0\[15\]:3 dpath.a_lt_b\$in0\[15\]:4 8.4 4 dpath.a_lt_b\$in0\[15\]:4 dpath.a_lt_b\$in0\[15\]:5 0.005 -5 _723_/A dpath.a_lt_b\$in0\[15\]:1 6.225 -6 _876_/Q dpath.a_lt_b\$in0\[15\]:5 4.605 +5 _723_:A dpath.a_lt_b\$in0\[15\]:1 6.225 +6 _876_:Q dpath.a_lt_b\$in0\[15\]:5 4.605 *END *D_NET dpath.a_lt_b\$in0\[1\] 3.18 *CONN -*I _751_/A I *D BUF_X1 -*I _862_/Q O *D DFF_X1 +*I _751_:A I *D BUF_X1 +*I _862_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[1\]:1 1.59 *RES 1 dpath.a_lt_b\$in0\[1\]:1 dpath.a_lt_b\$in0\[1\]:1 0.005 -2 _751_/A dpath.a_lt_b\$in0\[1\]:1 4.725 -3 _862_/Q dpath.a_lt_b\$in0\[1\]:1 1.645 +2 _751_:A dpath.a_lt_b\$in0\[1\]:1 4.725 +3 _862_:Q dpath.a_lt_b\$in0\[1\]:1 1.645 *END *D_NET dpath.a_lt_b\$in0\[2\] 4.2 *CONN -*I _749_/A I *D CLKBUF_X1 -*I _863_/Q O *D DFF_X1 +*I _749_:A I *D CLKBUF_X1 +*I _863_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[2\]:1 2.1 *RES 1 dpath.a_lt_b\$in0\[2\]:1 dpath.a_lt_b\$in0\[2\]:1 0.005 -2 _749_/A dpath.a_lt_b\$in0\[2\]:1 7.645 -3 _863_/Q dpath.a_lt_b\$in0\[2\]:1 0.765 +2 _749_:A dpath.a_lt_b\$in0\[2\]:1 7.645 +3 _863_:Q dpath.a_lt_b\$in0\[2\]:1 0.765 *END *D_NET dpath.a_lt_b\$in0\[3\] 11.63 *CONN -*I _747_/A I *D BUF_X1 -*I _864_/Q O *D DFF_X1 +*I _747_:A I *D BUF_X1 +*I _864_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[3\]:1 4.56 2 dpath.a_lt_b\$in0\[3\]:2 3.355 *RES 1 dpath.a_lt_b\$in0\[3\]:2 dpath.a_lt_b\$in0\[3\]:1 8.4 -2 _747_/A dpath.a_lt_b\$in0\[3\]:2 5.025 -3 _864_/Q dpath.a_lt_b\$in0\[3\]:1 9.845 +2 _747_:A dpath.a_lt_b\$in0\[3\]:2 5.025 +3 _864_:Q dpath.a_lt_b\$in0\[3\]:1 9.845 *END *D_NET dpath.a_lt_b\$in0\[4\] 15.14 *CONN -*I _745_/A I *D CLKBUF_X1 -*I _865_/Q O *D DFF_X1 +*I _745_:A I *D CLKBUF_X1 +*I _865_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[4\]:1 1.79 2 dpath.a_lt_b\$in0\[4\]:2 2.1 @@ -11281,40 +11281,40 @@ resp_val O 2 dpath.a_lt_b\$in0\[4\]:2 dpath.a_lt_b\$in0\[4\]:3 8.4 3 dpath.a_lt_b\$in0\[4\]:3 dpath.a_lt_b\$in0\[4\]:4 0.005 4 dpath.a_lt_b\$in0\[4\]:5 dpath.a_lt_b\$in0\[4\]:4 8.4 -5 _745_/A dpath.a_lt_b\$in0\[4\]:1 7.165 -6 _865_/Q dpath.a_lt_b\$in0\[4\]:5 6.325 +5 _745_:A dpath.a_lt_b\$in0\[4\]:1 7.165 +6 _865_:Q dpath.a_lt_b\$in0\[4\]:5 6.325 *END *D_NET dpath.a_lt_b\$in0\[5\] 7.63 *CONN -*I _743_/A I *D CLKBUF_X1 -*I _866_/Q O *D DFF_X1 +*I _743_:A I *D CLKBUF_X1 +*I _866_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[5\]:1 3.23 2 dpath.a_lt_b\$in0\[5\]:2 2.685 *RES 1 dpath.a_lt_b\$in0\[5\]:2 dpath.a_lt_b\$in0\[5\]:1 8.4 -2 _743_/A dpath.a_lt_b\$in0\[5\]:2 2.345 -3 _866_/Q dpath.a_lt_b\$in0\[5\]:1 4.525 +2 _743_:A dpath.a_lt_b\$in0\[5\]:2 2.345 +3 _866_:Q dpath.a_lt_b\$in0\[5\]:1 4.525 *END *D_NET dpath.a_lt_b\$in0\[6\] 8.4 *CONN -*I _741_/A I *D CLKBUF_X1 -*I _867_/Q O *D DFF_X1 +*I _741_:A I *D CLKBUF_X1 +*I _867_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[6\]:1 3.68 2 dpath.a_lt_b\$in0\[6\]:2 2.62 *RES 1 dpath.a_lt_b\$in0\[6\]:1 dpath.a_lt_b\$in0\[6\]:2 8.4 -2 _741_/A dpath.a_lt_b\$in0\[6\]:2 2.085 -3 _867_/Q dpath.a_lt_b\$in0\[6\]:1 6.325 +2 _741_:A dpath.a_lt_b\$in0\[6\]:2 2.085 +3 _867_:Q dpath.a_lt_b\$in0\[6\]:1 6.325 *END *D_NET dpath.a_lt_b\$in0\[7\] 6.6 *CONN -*I _739_/A I *D BUF_X1 -*I _868_/Q O *D DFF_X1 +*I _739_:A I *D BUF_X1 +*I _868_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[7\]:1 0.29 2 dpath.a_lt_b\$in0\[7\]:2 2.1 @@ -11324,26 +11324,26 @@ resp_val O 1 dpath.a_lt_b\$in0\[7\]:1 dpath.a_lt_b\$in0\[7\]:2 0.005 2 dpath.a_lt_b\$in0\[7\]:2 dpath.a_lt_b\$in0\[7\]:3 8.4 3 dpath.a_lt_b\$in0\[7\]:3 dpath.a_lt_b\$in0\[7\]:4 0.005 -4 _739_/A dpath.a_lt_b\$in0\[7\]:4 3.645 -5 _868_/Q dpath.a_lt_b\$in0\[7\]:1 1.165 +4 _739_:A dpath.a_lt_b\$in0\[7\]:4 3.645 +5 _868_:Q dpath.a_lt_b\$in0\[7\]:1 1.165 *END *D_NET dpath.a_lt_b\$in0\[8\] 5.29 *CONN -*I _737_/A I *D CLKBUF_X1 -*I _869_/Q O *D DFF_X1 +*I _737_:A I *D CLKBUF_X1 +*I _869_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[8\]:1 2.645 *RES 1 dpath.a_lt_b\$in0\[8\]:1 dpath.a_lt_b\$in0\[8\]:1 0.005 -2 _737_/A dpath.a_lt_b\$in0\[8\]:1 5.985 -3 _869_/Q dpath.a_lt_b\$in0\[8\]:1 4.605 +2 _737_:A dpath.a_lt_b\$in0\[8\]:1 5.985 +3 _869_:Q dpath.a_lt_b\$in0\[8\]:1 4.605 *END *D_NET dpath.a_lt_b\$in0\[9\] 6.6 *CONN -*I _735_/A I *D CLKBUF_X1 -*I _870_/Q O *D DFF_X1 +*I _735_:A I *D CLKBUF_X1 +*I _870_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in0\[9\]:1 0.09 2 dpath.a_lt_b\$in0\[9\]:2 2.1 @@ -11353,40 +11353,40 @@ resp_val O 1 dpath.a_lt_b\$in0\[9\]:1 dpath.a_lt_b\$in0\[9\]:2 0.005 2 dpath.a_lt_b\$in0\[9\]:2 dpath.a_lt_b\$in0\[9\]:3 8.4 3 dpath.a_lt_b\$in0\[9\]:3 dpath.a_lt_b\$in0\[9\]:4 0.005 -4 _735_/A dpath.a_lt_b\$in0\[9\]:4 4.445 -5 _870_/Q dpath.a_lt_b\$in0\[9\]:1 0.365 +4 _735_:A dpath.a_lt_b\$in0\[9\]:4 4.445 +5 _870_:Q dpath.a_lt_b\$in0\[9\]:1 0.365 *END *D_NET dpath.a_lt_b\$in1\[0\] 6.98 *CONN -*I _754_/A I *D BUF_X1 -*I _877_/Q O *D DFF_X1 +*I _754_:A I *D BUF_X1 +*I _877_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[0\]:1 2.58 2 dpath.a_lt_b\$in1\[0\]:2 3.01 *RES 1 dpath.a_lt_b\$in1\[0\]:1 dpath.a_lt_b\$in1\[0\]:2 8.4 -2 _754_/A dpath.a_lt_b\$in1\[0\]:2 3.645 -3 _877_/Q dpath.a_lt_b\$in1\[0\]:1 1.925 +2 _754_:A dpath.a_lt_b\$in1\[0\]:2 3.645 +3 _877_:Q dpath.a_lt_b\$in1\[0\]:1 1.925 *END *D_NET dpath.a_lt_b\$in1\[10\] 8.15 *CONN -*I _734_/A I *D BUF_X1 -*I _887_/Q O *D DFF_X1 +*I _734_:A I *D BUF_X1 +*I _887_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[10\]:1 3.68 2 dpath.a_lt_b\$in1\[10\]:2 2.495 *RES 1 dpath.a_lt_b\$in1\[10\]:1 dpath.a_lt_b\$in1\[10\]:2 8.4 -2 _734_/A dpath.a_lt_b\$in1\[10\]:2 1.585 -3 _887_/Q dpath.a_lt_b\$in1\[10\]:1 6.325 +2 _734_:A dpath.a_lt_b\$in1\[10\]:2 1.585 +3 _887_:Q dpath.a_lt_b\$in1\[10\]:1 6.325 *END *D_NET dpath.a_lt_b\$in1\[11\] 10.72 *CONN -*I _732_/A I *D BUF_X1 -*I _888_/Q O *D DFF_X1 +*I _732_:A I *D BUF_X1 +*I _888_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[11\]:1 0.43 2 dpath.a_lt_b\$in1\[11\]:2 2.1 @@ -11398,52 +11398,52 @@ resp_val O 2 dpath.a_lt_b\$in1\[11\]:2 dpath.a_lt_b\$in1\[11\]:3 8.4 3 dpath.a_lt_b\$in1\[11\]:3 dpath.a_lt_b\$in1\[11\]:4 0.005 4 dpath.a_lt_b\$in1\[11\]:5 dpath.a_lt_b\$in1\[11\]:4 8.4 -5 _732_/A dpath.a_lt_b\$in1\[11\]:1 1.725 -6 _888_/Q dpath.a_lt_b\$in1\[11\]:5 2.925 +5 _732_:A dpath.a_lt_b\$in1\[11\]:1 1.725 +6 _888_:Q dpath.a_lt_b\$in1\[11\]:5 2.925 *END *D_NET dpath.a_lt_b\$in1\[12\] 7.26 *CONN -*I _730_/A I *D BUF_X1 -*I _889_/Q O *D DFF_X1 +*I _730_:A I *D BUF_X1 +*I _889_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[12\]:1 2.77 2 dpath.a_lt_b\$in1\[12\]:2 2.96 *RES 1 dpath.a_lt_b\$in1\[12\]:1 dpath.a_lt_b\$in1\[12\]:2 8.4 -2 _730_/A dpath.a_lt_b\$in1\[12\]:2 3.445 -3 _889_/Q dpath.a_lt_b\$in1\[12\]:1 2.685 +2 _730_:A dpath.a_lt_b\$in1\[12\]:2 3.445 +3 _889_:Q dpath.a_lt_b\$in1\[12\]:1 2.685 *END *D_NET dpath.a_lt_b\$in1\[13\] 6.62 *CONN -*I _728_/A I *D CLKBUF_X2 -*I _890_/Q O *D DFF_X1 +*I _728_:A I *D CLKBUF_X2 +*I _890_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[13\]:1 2.29 2 dpath.a_lt_b\$in1\[13\]:2 3.12 *RES 1 dpath.a_lt_b\$in1\[13\]:1 dpath.a_lt_b\$in1\[13\]:2 8.4 -2 _728_/A dpath.a_lt_b\$in1\[13\]:2 4.085 -3 _890_/Q dpath.a_lt_b\$in1\[13\]:1 0.765 +2 _728_:A dpath.a_lt_b\$in1\[13\]:2 4.085 +3 _890_:Q dpath.a_lt_b\$in1\[13\]:1 0.765 *END *D_NET dpath.a_lt_b\$in1\[14\] 4.92 *CONN -*I _726_/A I *D BUF_X1 -*I _891_/Q O *D DFF_X1 +*I _726_:A I *D BUF_X1 +*I _891_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[14\]:1 2.46 *RES 1 dpath.a_lt_b\$in1\[14\]:1 dpath.a_lt_b\$in1\[14\]:1 0.005 -2 _726_/A dpath.a_lt_b\$in1\[14\]:1 2.805 -3 _891_/Q dpath.a_lt_b\$in1\[14\]:1 7.045 +2 _726_:A dpath.a_lt_b\$in1\[14\]:1 2.805 +3 _891_:Q dpath.a_lt_b\$in1\[14\]:1 7.045 *END *D_NET dpath.a_lt_b\$in1\[15\] 13.76 *CONN -*I _724_/A I *D BUF_X1 -*I _892_/Q O *D DFF_X1 +*I _724_:A I *D BUF_X1 +*I _892_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[15\]:1 3.12 2 dpath.a_lt_b\$in1\[15\]:2 2.1 @@ -11455,64 +11455,64 @@ resp_val O 2 dpath.a_lt_b\$in1\[15\]:2 dpath.a_lt_b\$in1\[15\]:3 0.005 3 dpath.a_lt_b\$in1\[15\]:3 dpath.a_lt_b\$in1\[15\]:4 8.4 4 dpath.a_lt_b\$in1\[15\]:4 dpath.a_lt_b\$in1\[15\]:5 0.005 -5 _724_/A dpath.a_lt_b\$in1\[15\]:1 4.085 -6 _892_/Q dpath.a_lt_b\$in1\[15\]:5 6.645 +5 _724_:A dpath.a_lt_b\$in1\[15\]:1 4.085 +6 _892_:Q dpath.a_lt_b\$in1\[15\]:5 6.645 *END *D_NET dpath.a_lt_b\$in1\[1\] 8.15 *CONN -*I _752_/A I *D BUF_X1 -*I _878_/Q O *D DFF_X1 +*I _752_:A I *D BUF_X1 +*I _878_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[1\]:1 2.69 2 dpath.a_lt_b\$in1\[1\]:2 3.485 *RES 1 dpath.a_lt_b\$in1\[1\]:2 dpath.a_lt_b\$in1\[1\]:1 8.4 -2 _752_/A dpath.a_lt_b\$in1\[1\]:2 5.545 -3 _878_/Q dpath.a_lt_b\$in1\[1\]:1 2.365 +2 _752_:A dpath.a_lt_b\$in1\[1\]:2 5.545 +3 _878_:Q dpath.a_lt_b\$in1\[1\]:1 2.365 *END *D_NET dpath.a_lt_b\$in1\[2\] 7.68 *CONN -*I _750_/A I *D CLKBUF_X1 -*I _879_/Q O *D DFF_X1 +*I _750_:A I *D CLKBUF_X1 +*I _879_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[2\]:1 3.38 2 dpath.a_lt_b\$in1\[2\]:2 2.56 *RES 1 dpath.a_lt_b\$in1\[2\]:2 dpath.a_lt_b\$in1\[2\]:1 8.4 -2 _750_/A dpath.a_lt_b\$in1\[2\]:2 1.845 -3 _879_/Q dpath.a_lt_b\$in1\[2\]:1 5.125 +2 _750_:A dpath.a_lt_b\$in1\[2\]:2 1.845 +3 _879_:Q dpath.a_lt_b\$in1\[2\]:1 5.125 *END *D_NET dpath.a_lt_b\$in1\[3\] 4.02 *CONN -*I _748_/A I *D CLKBUF_X1 -*I _880_/Q O *D DFF_X1 +*I _748_:A I *D CLKBUF_X1 +*I _880_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[3\]:1 2.01 *RES 1 dpath.a_lt_b\$in1\[3\]:1 dpath.a_lt_b\$in1\[3\]:1 0.005 -2 _748_/A dpath.a_lt_b\$in1\[3\]:1 1.605 -3 _880_/Q dpath.a_lt_b\$in1\[3\]:1 6.445 +2 _748_:A dpath.a_lt_b\$in1\[3\]:1 1.605 +3 _880_:Q dpath.a_lt_b\$in1\[3\]:1 6.445 *END *D_NET dpath.a_lt_b\$in1\[4\] 4.57 *CONN -*I _746_/A I *D CLKBUF_X1 -*I _881_/Q O *D DFF_X1 +*I _746_:A I *D CLKBUF_X1 +*I _881_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[4\]:1 2.285 *RES 1 dpath.a_lt_b\$in1\[4\]:1 dpath.a_lt_b\$in1\[4\]:1 0.005 -2 _746_/A dpath.a_lt_b\$in1\[4\]:1 3.625 -3 _881_/Q dpath.a_lt_b\$in1\[4\]:1 5.525 +2 _746_:A dpath.a_lt_b\$in1\[4\]:1 3.625 +3 _881_:Q dpath.a_lt_b\$in1\[4\]:1 5.525 *END *D_NET dpath.a_lt_b\$in1\[5\] 11.53 *CONN -*I _744_/A I *D BUF_X1 -*I _882_/Q O *D DFF_X1 +*I _744_:A I *D BUF_X1 +*I _882_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[5\]:1 1.065 2 dpath.a_lt_b\$in1\[5\]:2 2.1 @@ -11524,26 +11524,26 @@ resp_val O 2 dpath.a_lt_b\$in1\[5\]:2 dpath.a_lt_b\$in1\[5\]:3 8.4 3 dpath.a_lt_b\$in1\[5\]:3 dpath.a_lt_b\$in1\[5\]:4 0.005 4 dpath.a_lt_b\$in1\[5\]:5 dpath.a_lt_b\$in1\[5\]:4 8.4 -5 _744_/A dpath.a_lt_b\$in1\[5\]:1 4.265 -6 _882_/Q dpath.a_lt_b\$in1\[5\]:5 2.005 +5 _744_:A dpath.a_lt_b\$in1\[5\]:1 4.265 +6 _882_:Q dpath.a_lt_b\$in1\[5\]:5 2.005 *END *D_NET dpath.a_lt_b\$in1\[6\] 5.85 *CONN -*I _742_/A I *D BUF_X1 -*I _883_/Q O *D DFF_X1 +*I _742_:A I *D BUF_X1 +*I _883_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[6\]:1 2.925 *RES 1 dpath.a_lt_b\$in1\[6\]:1 dpath.a_lt_b\$in1\[6\]:1 0.005 -2 _742_/A dpath.a_lt_b\$in1\[6\]:1 4.905 -3 _883_/Q dpath.a_lt_b\$in1\[6\]:1 6.805 +2 _742_:A dpath.a_lt_b\$in1\[6\]:1 4.905 +3 _883_:Q dpath.a_lt_b\$in1\[6\]:1 6.805 *END *D_NET dpath.a_lt_b\$in1\[7\] 8.4 *CONN -*I _740_/A I *D BUF_X1 -*I _884_/Q O *D DFF_X1 +*I _740_:A I *D BUF_X1 +*I _884_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[7\]:1 0.1 2 dpath.a_lt_b\$in1\[7\]:2 2.1 @@ -11553,14 +11553,14 @@ resp_val O 1 dpath.a_lt_b\$in1\[7\]:1 dpath.a_lt_b\$in1\[7\]:2 0.005 2 dpath.a_lt_b\$in1\[7\]:2 dpath.a_lt_b\$in1\[7\]:3 8.4 3 dpath.a_lt_b\$in1\[7\]:3 dpath.a_lt_b\$in1\[7\]:4 0.005 -4 _740_/A dpath.a_lt_b\$in1\[7\]:4 8.005 -5 _884_/Q dpath.a_lt_b\$in1\[7\]:1 0.405 +4 _740_:A dpath.a_lt_b\$in1\[7\]:4 8.005 +5 _884_:Q dpath.a_lt_b\$in1\[7\]:1 0.405 *END *D_NET dpath.a_lt_b\$in1\[8\] 7.07 *CONN -*I _738_/A I *D CLKBUF_X1 -*I _885_/Q O *D DFF_X1 +*I _738_:A I *D CLKBUF_X1 +*I _885_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[8\]:1 0.29 2 dpath.a_lt_b\$in1\[8\]:2 2.1 @@ -11570,27 +11570,27 @@ resp_val O 1 dpath.a_lt_b\$in1\[8\]:1 dpath.a_lt_b\$in1\[8\]:2 0.005 2 dpath.a_lt_b\$in1\[8\]:2 dpath.a_lt_b\$in1\[8\]:3 8.4 3 dpath.a_lt_b\$in1\[8\]:3 dpath.a_lt_b\$in1\[8\]:4 0.005 -4 _738_/A dpath.a_lt_b\$in1\[8\]:4 4.585 -5 _885_/Q dpath.a_lt_b\$in1\[8\]:1 1.165 +4 _738_:A dpath.a_lt_b\$in1\[8\]:4 4.585 +5 _885_:Q dpath.a_lt_b\$in1\[8\]:1 1.165 *END *D_NET dpath.a_lt_b\$in1\[9\] 7.71 *CONN -*I _736_/A I *D BUF_X1 -*I _886_/Q O *D DFF_X1 +*I _736_:A I *D BUF_X1 +*I _886_:Q O *D DFF_X1 *CAP 1 dpath.a_lt_b\$in1\[9\]:1 3.09 2 dpath.a_lt_b\$in1\[9\]:2 2.865 *RES 1 dpath.a_lt_b\$in1\[9\]:2 dpath.a_lt_b\$in1\[9\]:1 8.4 -2 _736_/A dpath.a_lt_b\$in1\[9\]:2 3.065 -3 _886_/Q dpath.a_lt_b\$in1\[9\]:1 3.965 +2 _736_:A dpath.a_lt_b\$in1\[9\]:2 3.065 +3 _886_:Q dpath.a_lt_b\$in1\[9\]:1 3.965 *END *D_NET net1 55.69 *CONN -*I _809_/A I *D CLKBUF_X1 -*I buffer1/Z O *D BUF_X4 +*I _809_:A I *D CLKBUF_X1 +*I buffer1:Z O *D BUF_X4 *CAP 1 net1:1 3.53 2 net1:2 2.1 @@ -11602,14 +11602,14 @@ resp_val O 2 net1:2 net1:3 0.005 3 net1:3 net1:4 92.4 4 net1:4 net1:5 0.005 -5 _809_/A net1:1 5.725 -6 buffer1/Z net1:5 4.865 +5 _809_:A net1:1 5.725 +6 buffer1:Z net1:5 4.865 *END *D_NET net10 75.3 *CONN -*I _782_/A I *D CLKBUF_X1 -*I buffer10/Z O *D BUF_X4 +*I _782_:A I *D CLKBUF_X1 +*I buffer10:Z O *D BUF_X4 *CAP 1 net10:1 23.1 2 net10:2 24.165 @@ -11621,14 +11621,14 @@ resp_val O 2 net10:1 net10:3 0.005 3 net10:3 net10:4 50.4 4 net10:4 net10:5 0.005 -5 _782_/A net10:2 4.265 -6 buffer10/Z net10:5 3.545 +5 _782_:A net10:2 4.265 +6 buffer10:Z net10:5 3.545 *END *D_NET net11 13.99 *CONN -*I _779_/A I *D CLKBUF_X1 -*I buffer11/Z O *D BUF_X4 +*I _779_:A I *D CLKBUF_X1 +*I buffer11:Z O *D BUF_X4 *CAP 1 net11:1 2.95 2 net11:2 2.1 @@ -11640,14 +11640,14 @@ resp_val O 2 net11:2 net11:3 0.005 3 net11:3 net11:4 8.4 4 net11:4 net11:5 0.005 -5 _779_/A net11:1 3.405 -6 buffer11/Z net11:5 7.785 +5 _779_:A net11:1 3.405 +6 buffer11:Z net11:5 7.785 *END *D_NET net12 56.35 *CONN -*I _776_/A I *D CLKBUF_X1 -*I buffer12/Z O *D BUF_X4 +*I _776_:A I *D CLKBUF_X1 +*I buffer12:Z O *D BUF_X4 *CAP 1 net12:1 25.465 2 net12:2 25.2 @@ -11659,14 +11659,14 @@ resp_val O 2 net12:2 net12:3 0.005 3 net12:3 net12:4 8.4 4 net12:4 net12:5 0.005 -5 _776_/A net12:5 2.445 -6 buffer12/Z net12:1 1.065 +5 _776_:A net12:5 2.445 +6 buffer12:Z net12:1 1.065 *END *D_NET net13 39.43 *CONN -*I _773_/A I *D CLKBUF_X1 -*I buffer13/Z O *D BUF_X4 +*I _773_:A I *D CLKBUF_X1 +*I buffer13:Z O *D BUF_X4 *CAP 1 net13:1 8.13 2 net13:2 6.3 @@ -11680,14 +11680,14 @@ resp_val O 3 net13:3 net13:4 8.4 4 net13:4 net13:5 0.005 5 net13:5 net13:6 33.6 -6 _773_/A net13:1 7.325 -7 buffer13/Z net13:6 4.345 +6 _773_:A net13:1 7.325 +7 buffer13:Z net13:6 4.345 *END *D_NET net14 42.94 *CONN -*I _770_/A I *D CLKBUF_X1 -*I buffer14/Z O *D BUF_X4 +*I _770_:A I *D CLKBUF_X1 +*I buffer14:Z O *D BUF_X4 *CAP 1 net14:1 8.4 2 net14:2 10.275 @@ -11701,14 +11701,14 @@ resp_val O 3 net14:3 net14:4 8.4 4 net14:4 net14:5 0.005 5 net14:6 net14:5 33.6 -6 _770_/A net14:6 2.785 -7 buffer14/Z net14:2 7.505 +6 _770_:A net14:6 2.785 +7 buffer14:Z net14:2 7.505 *END *D_NET net15 20.48 *CONN -*I _767_/A I *D CLKBUF_X1 -*I buffer15/Z O *D BUF_X4 +*I _767_:A I *D CLKBUF_X1 +*I buffer15:Z O *D BUF_X4 *CAP 1 net15:1 4.2 2 net15:2 4.795 @@ -11722,14 +11722,14 @@ resp_val O 3 net15:3 net15:4 8.4 4 net15:4 net15:5 0.005 5 net15:6 net15:5 8.4 -6 _767_/A net15:2 2.385 -7 buffer15/Z net15:6 4.985 +6 _767_:A net15:2 2.385 +7 buffer15:Z net15:6 4.985 *END *D_NET net16 17.07 *CONN -*I _764_/A I *D CLKBUF_X1 -*I buffer16/Z O *D BUF_X4 +*I _764_:A I *D CLKBUF_X1 +*I buffer16:Z O *D BUF_X4 *CAP 1 net16:1 1.1 2 net16:2 4.2 @@ -11741,14 +11741,14 @@ resp_val O 2 net16:2 net16:3 16.8 3 net16:3 net16:4 0.005 4 net16:4 net16:5 8.4 -5 _764_/A net16:1 4.405 -6 buffer16/Z net16:5 4.545 +5 _764_:A net16:1 4.405 +6 buffer16:Z net16:5 4.545 *END *D_NET net17 101.7 *CONN -*I _841_/A I *D CLKBUF_X1 -*I buffer17/Z O *D BUF_X4 +*I _841_:A I *D CLKBUF_X1 +*I buffer17:Z O *D BUF_X4 *CAP 1 net17:1 47.545 2 net17:2 46.2 @@ -11760,14 +11760,14 @@ resp_val O 2 net17:2 net17:3 0.005 3 net17:3 net17:4 8.4 4 net17:4 net17:5 0.005 -5 _841_/A net17:1 5.385 -6 buffer17/Z net17:5 4.825 +5 _841_:A net17:1 5.385 +6 buffer17:Z net17:5 4.825 *END *D_NET net18 36.67 *CONN -*I _839_/A I *D CLKBUF_X1 -*I buffer18/Z O *D BUF_X4 +*I _839_:A I *D CLKBUF_X1 +*I buffer18:Z O *D BUF_X4 *CAP 1 net18:1 0.615 2 net18:2 10.5 @@ -11779,14 +11779,14 @@ resp_val O 2 net18:2 net18:3 42 3 net18:3 net18:4 0.005 4 net18:4 net18:5 25.2 -5 _839_/A net18:5 3.685 -6 buffer18/Z net18:1 2.465 +5 _839_:A net18:5 3.685 +6 buffer18:Z net18:1 2.465 *END *D_NET net19 47.97 *CONN -*I _837_/A I *D CLKBUF_X1 -*I buffer19/Z O *D BUF_X4 +*I _837_:A I *D CLKBUF_X1 +*I buffer19:Z O *D BUF_X4 *CAP 1 net19:1 6.3 2 net19:2 6.96 @@ -11798,14 +11798,14 @@ resp_val O 2 net19:1 net19:3 0.005 3 net19:3 net19:4 67.2 4 net19:4 net19:5 0.005 -5 _837_/A net19:2 2.645 -6 buffer19/Z net19:5 0.905 +5 _837_:A net19:2 2.645 +6 buffer19:Z net19:5 0.905 *END *D_NET net2 18.15 *CONN -*I _806_/A I *D CLKBUF_X1 -*I buffer2/Z O *D BUF_X4 +*I _806_:A I *D CLKBUF_X1 +*I buffer2:Z O *D BUF_X4 *CAP 1 net2:1 3.625 2 net2:2 2.1 @@ -11817,14 +11817,14 @@ resp_val O 2 net2:2 net2:3 0.005 3 net2:3 net2:4 16.8 4 net2:4 net2:5 0.005 -5 _806_/A net2:5 5.005 -6 buffer2/Z net2:1 6.105 +5 _806_:A net2:5 5.005 +6 buffer2:Z net2:1 6.105 *END *D_NET net20 73.1 *CONN -*I _835_/A I *D CLKBUF_X1 -*I buffer20/Z O *D BUF_X4 +*I _835_:A I *D CLKBUF_X1 +*I buffer20:Z O *D BUF_X4 *CAP 1 net20:1 4.505 2 net20:2 4.2 @@ -11836,27 +11836,27 @@ resp_val O 2 net20:2 net20:3 0.005 3 net20:3 net20:4 117.6 4 net20:4 net20:5 0.005 -5 _835_/A net20:1 1.225 -6 buffer20/Z net20:5 10.585 +5 _835_:A net20:1 1.225 +6 buffer20:Z net20:5 10.585 *END *D_NET net21 8.74 *CONN -*I _833_/A I *D CLKBUF_X1 -*I buffer21/Z O *D BUF_X4 +*I _833_:A I *D CLKBUF_X1 +*I buffer21:Z O *D BUF_X4 *CAP 1 net21:1 3.175 2 net21:2 3.295 *RES 1 net21:1 net21:2 8.4 -2 _833_/A net21:2 4.785 -3 buffer21/Z net21:1 4.305 +2 _833_:A net21:2 4.785 +3 buffer21:Z net21:1 4.305 *END *D_NET net22 17.83 *CONN -*I _831_/A I *D CLKBUF_X1 -*I buffer22/Z O *D BUF_X4 +*I _831_:A I *D CLKBUF_X1 +*I buffer22:Z O *D BUF_X4 *CAP 1 net22:1 0.98 2 net22:2 4.2 @@ -11868,27 +11868,27 @@ resp_val O 2 net22:2 net22:3 16.8 3 net22:3 net22:4 0.005 4 net22:4 net22:5 8.4 -5 _831_/A net22:1 3.925 -6 buffer22/Z net22:5 6.545 +5 _831_:A net22:1 3.925 +6 buffer22:Z net22:5 6.545 *END *D_NET net23 7.94 *CONN -*I _829_/A I *D CLKBUF_X1 -*I buffer23/Z O *D BUF_X4 +*I _829_:A I *D CLKBUF_X1 +*I buffer23:Z O *D BUF_X4 *CAP 1 net23:1 2.975 2 net23:2 3.095 *RES 1 net23:1 net23:2 8.4 -2 _829_/A net23:2 3.985 -3 buffer23/Z net23:1 3.505 +2 _829_:A net23:2 3.985 +3 buffer23:Z net23:1 3.505 *END *D_NET net24 102.5 *CONN -*I _827_/A I *D CLKBUF_X1 -*I buffer24/Z O *D BUF_X4 +*I _827_:A I *D CLKBUF_X1 +*I buffer24:Z O *D BUF_X4 *CAP 1 net24:1 37.8 2 net24:2 38.765 @@ -11900,14 +11900,14 @@ resp_val O 2 net24:1 net24:3 0.005 3 net24:3 net24:4 42 4 net24:4 net24:5 0.005 -5 _827_/A net24:5 7.945 -6 buffer24/Z net24:2 3.865 +5 _827_:A net24:5 7.945 +6 buffer24:Z net24:2 3.865 *END *D_NET net25 34.99 *CONN -*I _825_/A I *D CLKBUF_X1 -*I buffer25/Z O *D BUF_X4 +*I _825_:A I *D CLKBUF_X1 +*I buffer25:Z O *D BUF_X4 *CAP 1 net25:1 7.85 2 net25:2 6.3 @@ -11921,27 +11921,27 @@ resp_val O 3 net25:3 net25:4 8.4 4 net25:4 net25:5 0.005 5 net25:5 net25:6 25.2 -6 _825_/A net25:1 6.205 -7 buffer25/Z net25:6 4.985 +6 _825_:A net25:1 6.205 +7 buffer25:Z net25:6 4.985 *END *D_NET net26 9.65 *CONN -*I _823_/A I *D CLKBUF_X1 -*I buffer26/Z O *D BUF_X4 +*I _823_:A I *D CLKBUF_X1 +*I buffer26:Z O *D BUF_X4 *CAP 1 net26:1 3.675 2 net26:2 3.25 *RES 1 net26:1 net26:2 8.4 -2 _823_/A net26:2 4.605 -3 buffer26/Z net26:1 6.305 +2 _823_:A net26:2 4.605 +3 buffer26:Z net26:1 6.305 *END *D_NET net27 24.38 *CONN -*I _821_/A I *D CLKBUF_X1 -*I buffer27/Z O *D BUF_X4 +*I _821_:A I *D CLKBUF_X1 +*I buffer27:Z O *D BUF_X4 *CAP 1 net27:1 3.245 2 net27:2 2.1 @@ -11953,14 +11953,14 @@ resp_val O 2 net27:2 net27:3 0.005 3 net27:3 net27:4 25.2 4 net27:4 net27:5 0.005 -5 _821_/A net27:1 4.585 -6 buffer27/Z net27:5 10.585 +5 _821_:A net27:1 4.585 +6 buffer27:Z net27:5 10.585 *END *D_NET net28 32.43 *CONN -*I _819_/A I *D CLKBUF_X1 -*I buffer28/Z O *D BUF_X4 +*I _819_:A I *D CLKBUF_X1 +*I buffer28:Z O *D BUF_X4 *CAP 1 net28:1 3.07 2 net28:2 2.1 @@ -11974,27 +11974,27 @@ resp_val O 3 net28:3 net28:4 25.2 4 net28:4 net28:5 0.005 5 net28:5 net28:6 16.8 -6 _819_/A net28:1 3.885 -7 buffer28/Z net28:6 10.585 +6 _819_:A net28:1 3.885 +7 buffer28:Z net28:6 10.585 *END *D_NET net29 8.64 *CONN -*I _817_/A I *D CLKBUF_X1 -*I buffer29/Z O *D BUF_X4 +*I _817_:A I *D CLKBUF_X1 +*I buffer29:Z O *D BUF_X4 *CAP 1 net29:1 2.975 2 net29:2 3.445 *RES 1 net29:2 net29:1 8.4 -2 _817_/A net29:2 5.385 -3 buffer29/Z net29:1 3.505 +2 _817_:A net29:2 5.385 +3 buffer29:Z net29:1 3.505 *END *D_NET net3 16.67 *CONN -*I _803_/A I *D CLKBUF_X1 -*I buffer3/Z O *D BUF_X4 +*I _803_:A I *D CLKBUF_X1 +*I buffer3:Z O *D BUF_X4 *CAP 1 net3:1 4.2 2 net3:2 5.77 @@ -12006,14 +12006,14 @@ resp_val O 2 net3:1 net3:3 0.005 3 net3:3 net3:4 8.4 4 net3:4 net3:5 0.005 -5 _803_/A net3:2 6.285 -6 buffer3/Z net3:5 1.865 +5 _803_:A net3:2 6.285 +6 buffer3:Z net3:5 1.865 *END *D_NET net30 41.99 *CONN -*I _815_/A I *D CLKBUF_X1 -*I buffer30/Z O *D BUF_X4 +*I _815_:A I *D CLKBUF_X1 +*I buffer30:Z O *D BUF_X4 *CAP 1 net30:1 12.6 2 net30:2 14.105 @@ -12025,14 +12025,14 @@ resp_val O 2 net30:1 net30:3 0.005 3 net30:3 net30:4 25.2 4 net30:4 net30:5 0.005 -5 _815_/A net30:5 2.365 -6 buffer30/Z net30:2 6.025 +5 _815_:A net30:5 2.365 +6 buffer30:Z net30:2 6.025 *END *D_NET net31 12.68 *CONN -*I _813_/A I *D CLKBUF_X1 -*I buffer31/Z O *D BUF_X4 +*I _813_:A I *D CLKBUF_X1 +*I buffer31:Z O *D BUF_X4 *CAP 1 net31:1 3.485 2 net31:2 2.1 @@ -12044,14 +12044,14 @@ resp_val O 2 net31:2 net31:3 0.005 3 net31:3 net31:4 8.4 4 net31:4 net31:5 0.005 -5 _813_/A net31:5 3.025 -6 buffer31/Z net31:1 5.545 +5 _813_:A net31:5 3.025 +6 buffer31:Z net31:1 5.545 *END *D_NET net32 31.4 *CONN -*I _811_/A I *D CLKBUF_X1 -*I buffer32/Z O *D BUF_X4 +*I _811_:A I *D CLKBUF_X1 +*I buffer32:Z O *D BUF_X4 *CAP 1 net32:1 1.855 2 net32:2 10.5 @@ -12063,14 +12063,14 @@ resp_val O 2 net32:2 net32:3 42 3 net32:3 net32:4 0.005 4 net32:4 net32:5 8.4 -5 _811_/A net32:1 7.425 -6 buffer32/Z net32:5 4.985 +5 _811_:A net32:1 7.425 +6 buffer32:Z net32:5 4.985 *END *D_NET net33 140.89 *CONN -*I _760_/A I *D CLKBUF_X1 -*I buffer33/Z O *D BUF_X4 +*I _760_:A I *D CLKBUF_X1 +*I buffer33:Z O *D BUF_X4 *CAP 1 net33:1 24.76 2 net33:2 23.1 @@ -12082,14 +12082,14 @@ resp_val O 2 net33:2 net33:3 0.005 3 net33:3 net33:4 176.4 4 net33:4 net33:5 0.005 -5 _760_/A net33:1 6.645 -6 buffer33/Z net33:5 6.345 +5 _760_:A net33:1 6.645 +6 buffer33:Z net33:5 6.345 *END *D_NET net34 43.74 *CONN -*I _717_/A I *D CLKBUF_X1 -*I buffer34/Z O *D BUF_X4 +*I _717_:A I *D CLKBUF_X1 +*I buffer34:Z O *D BUF_X4 *CAP 1 net34:1 2.275 2 net34:2 16.8 @@ -12101,14 +12101,14 @@ resp_val O 2 net34:2 net34:3 67.2 3 net34:3 net34:4 0.005 4 net34:4 net34:5 8.4 -5 _717_/A net34:5 2.785 -6 buffer34/Z net34:1 9.105 +5 _717_:A net34:5 2.785 +6 buffer34:Z net34:1 9.105 *END *D_NET net35 89.27 *CONN -*I _722_/A I *D CLKBUF_X1 -*I buffer35/Z O *D BUF_X4 +*I _722_:A I *D CLKBUF_X1 +*I buffer35:Z O *D BUF_X4 *CAP 1 net35:1 23.1 2 net35:2 24.675 @@ -12120,15 +12120,15 @@ resp_val O 2 net35:1 net35:3 0.005 3 net35:3 net35:4 75.6 4 net35:4 net35:5 0.005 -5 _722_/A net35:5 4.245 -6 buffer35/Z net35:2 6.305 +5 _722_:A net35:5 4.245 +6 buffer35:Z net35:2 6.305 *END *D_NET net36 129.98 *CONN -*I _759_/A I *D BUF_X2 -*I _858_/Q O *D DFF_X1 -*I buffer36/A I *D BUF_X4 +*I _759_:A I *D BUF_X2 +*I _858_:Q O *D DFF_X1 +*I buffer36:A I *D BUF_X4 *CAP 1 net36:1 1.22 2 net36:2 16.8 @@ -12148,15 +12148,15 @@ resp_val O 6 net36:6 net36:7 16.8 7 net36:7 net36:8 0.005 8 net36:8 net36:9 8.4 -9 _759_/A net36:5 2.045 -10 _858_/Q net36:9 1.045 -11 buffer36/A net36:1 4.885 +9 _759_:A net36:5 2.045 +10 _858_:Q net36:9 1.045 +11 buffer36:A net36:1 4.885 *END *D_NET net37 78.01 *CONN -*I _857_/Z O *D CLKBUF_X1 -*I buffer37/A I *D BUF_X4 +*I _857_:Z O *D CLKBUF_X1 +*I buffer37:A I *D BUF_X4 *CAP 1 net37:1 1.395 2 net37:2 35.7 @@ -12166,14 +12166,14 @@ resp_val O 1 net37:1 net37:2 0.005 2 net37:2 net37:3 142.8 3 net37:3 net37:4 0.005 -4 _857_/Z net37:4 7.645 -5 buffer37/A net37:1 5.585 +4 _857_:Z net37:4 7.645 +5 buffer37:A net37:1 5.585 *END *D_NET net38 24.72 *CONN -*I _856_/Z O *D CLKBUF_X1 -*I buffer38/A I *D BUF_X4 +*I _856_:Z O *D CLKBUF_X1 +*I buffer38:A I *D BUF_X4 *CAP 1 net38:1 8.4 2 net38:2 9.31 @@ -12185,14 +12185,14 @@ resp_val O 2 net38:1 net38:3 0.005 3 net38:3 net38:4 8.4 4 net38:4 net38:5 0.005 -5 _856_/Z net38:2 3.645 -6 buffer38/A net38:5 3.805 +5 _856_:Z net38:2 3.645 +6 buffer38:A net38:5 3.805 *END *D_NET net39 80.42 *CONN -*I _855_/Z O *D CLKBUF_X1 -*I buffer39/A I *D BUF_X4 +*I _855_:Z O *D CLKBUF_X1 +*I buffer39:A I *D BUF_X4 *CAP 1 net39:1 3.66 2 net39:2 2.1 @@ -12204,27 +12204,27 @@ resp_val O 2 net39:2 net39:3 0.005 3 net39:3 net39:4 142.8 4 net39:4 net39:5 0.005 -5 _855_/Z net39:1 6.245 -6 buffer39/A net39:5 3.405 +5 _855_:Z net39:1 6.245 +6 buffer39:A net39:5 3.405 *END *D_NET net4 10.39 *CONN -*I _800_/A I *D CLKBUF_X1 -*I buffer4/Z O *D BUF_X4 +*I _800_:A I *D CLKBUF_X1 +*I buffer4:Z O *D BUF_X4 *CAP 1 net4:1 4.375 2 net4:2 2.92 *RES 1 net4:1 net4:2 8.4 -2 _800_/A net4:2 3.285 -3 buffer4/Z net4:1 9.105 +2 _800_:A net4:2 3.285 +3 buffer4:Z net4:1 9.105 *END *D_NET net40 70.87 *CONN -*I _854_/Z O *D CLKBUF_X1 -*I buffer40/A I *D BUF_X4 +*I _854_:Z O *D CLKBUF_X1 +*I buffer40:A I *D BUF_X4 *CAP 1 net40:1 4.2 2 net40:2 5.01 @@ -12236,14 +12236,14 @@ resp_val O 2 net40:1 net40:3 0.005 3 net40:3 net40:4 117.6 4 net40:4 net40:5 0.005 -5 _854_/Z net40:2 3.245 -6 buffer40/A net40:5 4.105 +5 _854_:Z net40:2 3.245 +6 buffer40:A net40:5 4.105 *END *D_NET net41 50.52 *CONN -*I _853_/Z O *D CLKBUF_X1 -*I buffer41/A I *D BUF_X4 +*I _853_:Z O *D CLKBUF_X1 +*I buffer41:A I *D BUF_X4 *CAP 1 net41:1 1.31 2 net41:2 23.1 @@ -12253,14 +12253,14 @@ resp_val O 1 net41:1 net41:2 0.005 2 net41:2 net41:3 92.4 3 net41:3 net41:4 0.005 -4 _853_/Z net41:1 5.245 -5 buffer41/A net41:4 3.405 +4 _853_:Z net41:1 5.245 +5 buffer41:A net41:4 3.405 *END *D_NET net42 48.22 *CONN -*I _852_/Z O *D CLKBUF_X1 -*I buffer42/A I *D BUF_X4 +*I _852_:Z O *D CLKBUF_X1 +*I buffer42:A I *D BUF_X4 *CAP 1 net42:1 1.22 2 net42:2 14.7 @@ -12272,14 +12272,14 @@ resp_val O 2 net42:2 net42:3 58.8 3 net42:3 net42:4 0.005 4 net42:5 net42:4 25.2 -5 _852_/Z net42:5 7.565 -6 buffer42/A net42:1 4.885 +5 _852_:Z net42:5 7.565 +6 buffer42:A net42:1 4.885 *END *D_NET net43 95.76 *CONN -*I _851_/Z O *D CLKBUF_X1 -*I buffer43/A I *D BUF_X4 +*I _851_:Z O *D CLKBUF_X1 +*I buffer43:A I *D BUF_X4 *CAP 1 net43:1 29.4 2 net43:2 30.22 @@ -12291,14 +12291,14 @@ resp_val O 2 net43:1 net43:3 0.005 3 net43:3 net43:4 67.2 4 net43:4 net43:5 0.005 -5 _851_/Z net43:2 3.285 -6 buffer43/A net43:5 3.445 +5 _851_:Z net43:2 3.285 +6 buffer43:A net43:5 3.445 *END *D_NET net44 71.58 *CONN -*I _850_/Z O *D CLKBUF_X1 -*I buffer44/A I *D BUF_X4 +*I _850_:Z O *D CLKBUF_X1 +*I buffer44:A I *D BUF_X4 *CAP 1 net44:1 6.3 2 net44:2 7.52 @@ -12310,14 +12310,14 @@ resp_val O 2 net44:1 net44:3 0.005 3 net44:3 net44:4 109.2 4 net44:4 net44:5 0.005 -5 _850_/Z net44:5 3.885 -6 buffer44/A net44:2 4.885 +5 _850_:Z net44:5 3.885 +6 buffer44:A net44:2 4.885 *END *D_NET net45 74.53 *CONN -*I _849_/Z O *D CLKBUF_X1 -*I buffer45/A I *D BUF_X4 +*I _849_:Z O *D CLKBUF_X1 +*I buffer45:A I *D BUF_X4 *CAP 1 net45:1 27.84 2 net45:2 27.3 @@ -12329,14 +12329,14 @@ resp_val O 2 net45:2 net45:3 0.005 3 net45:3 net45:4 33.6 4 net45:4 net45:5 0.005 -5 _849_/Z net45:1 2.165 -6 buffer45/A net45:5 4.105 +5 _849_:Z net45:1 2.165 +6 buffer45:A net45:5 4.105 *END *D_NET net46 139.3 *CONN -*I _848_/Z O *D CLKBUF_X1 -*I buffer46/A I *D BUF_X4 +*I _848_:Z O *D CLKBUF_X1 +*I buffer46:A I *D BUF_X4 *CAP 1 net46:1 14.52 2 net46:2 12.6 @@ -12348,14 +12348,14 @@ resp_val O 2 net46:2 net46:3 0.005 3 net46:3 net46:4 218.4 4 net46:4 net46:5 0.005 -5 _848_/Z net46:5 2.125 -6 buffer46/A net46:1 7.685 +5 _848_:Z net46:5 2.125 +6 buffer46:A net46:1 7.685 *END *D_NET net47 77.17 *CONN -*I _847_/Z O *D CLKBUF_X1 -*I buffer47/A I *D BUF_X4 +*I _847_:Z O *D CLKBUF_X1 +*I buffer47:A I *D BUF_X4 *CAP 1 net47:1 29.4 2 net47:2 30.91 @@ -12367,14 +12367,14 @@ resp_val O 2 net47:1 net47:3 0.005 3 net47:3 net47:4 25.2 4 net47:4 net47:5 0.005 -5 _847_/Z net47:2 6.045 -6 buffer47/A net47:5 5.505 +5 _847_:Z net47:2 6.045 +6 buffer47:A net47:5 5.505 *END *D_NET net48 156.84 *CONN -*I _846_/Z O *D CLKBUF_X1 -*I buffer48/A I *D BUF_X4 +*I _846_:Z O *D CLKBUF_X1 +*I buffer48:A I *D BUF_X4 *CAP 1 net48:1 22.21 2 net48:2 21 @@ -12386,14 +12386,14 @@ resp_val O 2 net48:2 net48:3 0.005 3 net48:3 net48:4 218.4 4 net48:4 net48:5 0.005 -5 _846_/Z net48:5 6.445 -6 buffer48/A net48:1 4.845 +5 _846_:Z net48:5 6.445 +6 buffer48:A net48:1 4.845 *END *D_NET net49 113.28 *CONN -*I _845_/Z O *D CLKBUF_X1 -*I buffer49/A I *D BUF_X4 +*I _845_:Z O *D CLKBUF_X1 +*I buffer49:A I *D BUF_X4 *CAP 1 net49:1 50.4 2 net49:2 51.18 @@ -12405,27 +12405,27 @@ resp_val O 2 net49:1 net49:3 0.005 3 net49:3 net49:4 16.8 4 net49:4 net49:5 0.005 -5 _845_/Z net49:2 3.125 -6 buffer49/A net49:5 5.045 +5 _845_:Z net49:2 3.125 +6 buffer49:A net49:5 5.045 *END *D_NET net5 8.89 *CONN -*I _797_/A I *D CLKBUF_X1 -*I buffer5/Z O *D BUF_X4 +*I _797_:A I *D CLKBUF_X1 +*I buffer5:Z O *D BUF_X4 *CAP 1 net5:1 3.445 2 net5:2 3.1 *RES 1 net5:2 net5:1 8.4 -2 _797_/A net5:2 4.005 -3 buffer5/Z net5:1 5.385 +2 _797_:A net5:2 4.005 +3 buffer5:Z net5:1 5.385 *END *D_NET net50 70.5 *CONN -*I _844_/Z O *D CLKBUF_X1 -*I buffer50/A I *D BUF_X4 +*I _844_:Z O *D CLKBUF_X1 +*I buffer50:A I *D BUF_X4 *CAP 1 net50:1 3.32 2 net50:2 2.1 @@ -12437,14 +12437,14 @@ resp_val O 2 net50:2 net50:3 0.005 3 net50:3 net50:4 126 4 net50:4 net50:5 0.005 -5 _844_/Z net50:5 1.725 -6 buffer50/A net50:1 4.885 +5 _844_:Z net50:5 1.725 +6 buffer50:A net50:1 4.885 *END *D_NET net51 88.13 *CONN -*I _843_/Z O *D CLKBUF_X1 -*I buffer51/A I *D BUF_X4 +*I _843_:Z O *D CLKBUF_X1 +*I buffer51:A I *D BUF_X4 *CAP 1 net51:1 4.2 2 net51:2 5.245 @@ -12456,14 +12456,14 @@ resp_val O 2 net51:1 net51:3 0.005 3 net51:3 net51:4 151.2 4 net51:4 net51:5 0.005 -5 _843_/Z net51:5 4.085 -6 buffer51/A net51:2 4.185 +5 _843_:Z net51:5 4.085 +6 buffer51:A net51:2 4.185 *END *D_NET net52 111.22 *CONN -*I _755_/Z O *D CLKBUF_X1 -*I buffer52/A I *D BUF_X4 +*I _755_:Z O *D CLKBUF_X1 +*I buffer52:A I *D BUF_X4 *CAP 1 net52:1 14.7 2 net52:2 16.62 @@ -12475,14 +12475,14 @@ resp_val O 2 net52:1 net52:3 0.005 3 net52:3 net52:4 151.2 4 net52:4 net52:5 0.005 -5 _755_/Z net52:5 4.765 -6 buffer52/A net52:2 7.685 +5 _755_:Z net52:5 4.765 +6 buffer52:A net52:2 7.685 *END *D_NET net53 105.89 *CONN -*I _721_/Z O *D CLKBUF_X1 -*I buffer53/A I *D BUF_X4 +*I _721_:Z O *D CLKBUF_X1 +*I buffer53:A I *D BUF_X4 *CAP 1 net53:1 3.27 2 net53:2 2.1 @@ -12494,27 +12494,27 @@ resp_val O 2 net53:2 net53:3 0.005 3 net53:3 net53:4 193.2 4 net53:4 net53:5 0.005 -5 _721_/Z net53:1 4.685 -6 buffer53/A net53:5 5.505 +5 _721_:Z net53:1 4.685 +6 buffer53:A net53:5 5.505 *END *D_NET net6 27.12 *CONN -*I _794_/A I *D CLKBUF_X1 -*I buffer6/Z O *D BUF_X4 +*I _794_:A I *D CLKBUF_X1 +*I buffer6:Z O *D BUF_X4 *CAP 1 net6:1 12.995 2 net6:2 13.165 *RES 1 net6:1 net6:2 50.4 -2 _794_/A net6:2 2.265 -3 buffer6/Z net6:1 1.585 +2 _794_:A net6:2 2.265 +3 buffer6:Z net6:1 1.585 *END *D_NET net7 72.61 *CONN -*I _791_/A I *D CLKBUF_X1 -*I buffer7/Z O *D BUF_X4 +*I _791_:A I *D CLKBUF_X1 +*I buffer7:Z O *D BUF_X4 *CAP 1 net7:1 31.5 2 net7:2 32.605 @@ -12526,14 +12526,14 @@ resp_val O 2 net7:1 net7:3 0.005 3 net7:3 net7:4 8.4 4 net7:4 net7:5 0.005 -5 _791_/A net7:5 6.405 -6 buffer7/Z net7:2 4.425 +5 _791_:A net7:5 6.405 +6 buffer7:Z net7:2 4.425 *END *D_NET net8 10.74 *CONN -*I _788_/A I *D CLKBUF_X1 -*I buffer8/Z O *D BUF_X4 +*I _788_:A I *D CLKBUF_X1 +*I buffer8:Z O *D BUF_X4 *CAP 1 net8:1 0.625 2 net8:2 2.1 @@ -12543,14 +12543,14 @@ resp_val O 1 net8:1 net8:2 0.005 2 net8:2 net8:3 8.4 3 net8:3 net8:4 0.005 -4 _788_/A net8:1 2.505 -5 buffer8/Z net8:4 10.585 +4 _788_:A net8:1 2.505 +5 buffer8:Z net8:4 10.585 *END *D_NET net9 11.49 *CONN -*I _785_/A I *D CLKBUF_X1 -*I buffer9/Z O *D BUF_X4 +*I _785_:A I *D CLKBUF_X1 +*I buffer9:Z O *D BUF_X4 *CAP 1 net9:1 0.955 2 net9:2 2.1 @@ -12562,7 +12562,7 @@ resp_val O 2 net9:2 net9:3 8.4 3 net9:3 net9:4 0.005 4 net9:5 net9:4 8.4 -5 _785_/A net9:5 2.365 -6 buffer9/Z net9:1 3.825 +5 _785_:A net9:5 2.365 +6 buffer9:Z net9:1 3.825 *END From ced2b70f4910379c028b0f54048de921e0946e9c Mon Sep 17 00:00:00 2001 From: Christian Costa Date: Fri, 13 Dec 2024 14:41:54 +0100 Subject: [PATCH 49/98] etc: Update spdlog also when installed version does not match. Signed-off-by: Christian Costa --- etc/DependencyInstaller.sh | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/etc/DependencyInstaller.sh b/etc/DependencyInstaller.sh index 0c9b693f7dc..1a102428382 100755 --- a/etc/DependencyInstaller.sh +++ b/etc/DependencyInstaller.sh @@ -192,14 +192,19 @@ _installCommonDev() { # spdlog spdlogPrefix=${PREFIX:-"/usr/local"} - if [[ ! -d ${spdlogPrefix}/include/spdlog ]]; then + installed_version="none" + if [ -d ${spdlogPrefix}/include/spdlog ]; then + installed_version=`grep "#define SPDLOG_VER_" ${spdlogPrefix}/include/spdlog/version.h | sed 's/.*\s//' | tr '\n' '.' | sed 's/\.$//'` + fi + if [ ${installed_version} != ${spdlogVersion} ]; then cd "${baseDir}" git clone --depth=1 -b "v${spdlogVersion}" https://github.com/gabime/spdlog.git cd spdlog ${cmakePrefix}/bin/cmake -DCMAKE_INSTALL_PREFIX="${spdlogPrefix}" -DCMAKE_POSITION_INDEPENDENT_CODE=ON -DSPDLOG_BUILD_EXAMPLE=OFF -B build . ${cmakePrefix}/bin/cmake --build build -j $(nproc) --target install + echo "spdlog ${spdlogVersion} installed (from ${installed_version})." else - echo "spdlog already installed." + echo "spdlog ${spdlogVersion} already installed." fi CMAKE_PACKAGE_ROOT_ARGS+=" -D spdlog_ROOT=$(realpath $spdlogPrefix) " From e091dbb7e478a8a73f601ebbcfa27e22058fced4 Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Fri, 13 Dec 2024 13:35:00 -0300 Subject: [PATCH 50/98] rsz: fix pin delimiter only for iterms Signed-off-by: Eder Monteiro --- src/rsz/src/SpefWriter.cc | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/src/rsz/src/SpefWriter.cc b/src/rsz/src/SpefWriter.cc index 51e6b304198..01d421efd2d 100644 --- a/src/rsz/src/SpefWriter.cc +++ b/src/rsz/src/SpefWriter.cc @@ -264,9 +264,32 @@ void SpefWriter::writeNet(Corner* corner, const Net* net, Parasitic* parasitic) stream << count++ << " "; auto n1 = parasitics_->node1(res); - stream << fixPinDelimiter(escapeDollarSign(parasitics_->name(n1))) << " "; auto n2 = parasitics_->node2(res); - stream << fixPinDelimiter(escapeDollarSign(parasitics_->name(n2))) << " "; + + odb::dbITerm* iterm = nullptr; + odb::dbBTerm* bterm = nullptr; + odb::dbModITerm* moditerm = nullptr; + odb::dbModBTerm* modbterm = nullptr; + + std::string node1_name = escapeDollarSign(parasitics_->name(n1)); + auto pin1 = parasitics_->pin(n1); + if (pin1 != nullptr) { + network_->staToDb(pin1, iterm, bterm, moditerm, modbterm); + if (iterm != nullptr) { + node1_name = fixPinDelimiter(node1_name); + } + } + std::string node2_name = escapeDollarSign(parasitics_->name(n2)); + auto pin2 = parasitics_->pin(n2); + if (pin2 != nullptr) { + network_->staToDb(pin2, iterm, bterm, moditerm, modbterm); + if (iterm != nullptr) { + node2_name = fixPinDelimiter(node2_name); + } + } + + stream << node1_name << " "; + stream << node2_name << " "; stream << parasitics_->value(res) / res_scale << '\n'; } From abc8b1db42c62ef6b353a0499b410411670abf68 Mon Sep 17 00:00:00 2001 From: bernardo Date: Sat, 14 Dec 2024 22:40:26 +0000 Subject: [PATCH 51/98] creation of new files Signed-off-by: bernardo --- src/drt/CMakeLists.txt | 477 +++++++++++++------------- src/drt/src/pa/FlexPA_acc_pattern.cpp | 52 +++ src/drt/src/pa/FlexPA_acc_point.cpp | 51 +++ src/drt/src/pa/FlexPA_row_pattern.cpp | 52 +++ 4 files changed, 398 insertions(+), 234 deletions(-) create mode 100644 src/drt/src/pa/FlexPA_acc_pattern.cpp create mode 100644 src/drt/src/pa/FlexPA_acc_point.cpp create mode 100644 src/drt/src/pa/FlexPA_row_pattern.cpp diff --git a/src/drt/CMakeLists.txt b/src/drt/CMakeLists.txt index 6afd7152593..d7e3a60c515 100644 --- a/src/drt/CMakeLists.txt +++ b/src/drt/CMakeLists.txt @@ -1,264 +1,273 @@ -############################################################################### -## -## BSD 3-Clause License -## -## Copyright (c) 2021, The Regents of the University of California -## All rights reserved. -## -## Redistribution and use in source and binary forms, with or without -## modification, are permitted provided that the following conditions are met: -## -## * Redistributions of source code must retain the above copyright notice, this -## list of conditions and the following disclaimer. -## -## * Redistributions in binary form must reproduce the above copyright notice, -## this list of conditions and the following disclaimer in the documentation -## and#or other materials provided with the distribution. -## -## * Neither the name of the copyright holder nor the names of its -## contributors may be used to endorse or promote products derived from -## this software without specific prior written permission. -## -## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -## POSSIBILITY OF SUCH DAMAGE. -## -############################################################################### +############################################################################## # ####BSD 3 + - Clause License####Copyright(c) 2021, + The Regents of the University of California + ##All rights reserved.####Redistribution and use in source and binary forms, + with or without##modification, + are permitted provided that the following conditions are met + :####*Redistributions of source code must retain the above copyright notice, + this##list of conditions and the following disclaimer.####*Redistributions + in binary form must reproduce the above copyright notice, + ##this list of conditions and the following disclaimer in the documentation + ##and# + or other materials provided with the distribution.####*Neither the name + of the copyright holder nor the names of its + ##contributors may be used to endorse + or promote products derived from + ##this software without specific prior written permission.####THIS + SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS"##AND ANY EXPRESS OR IMPLIED WARRANTIES, + INCLUDING, + BUT NOT LIMITED TO, + THE##IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + PARTICULAR PURPOSE + ##ARE DISCLAIMED.IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + ##LIABLE FOR ANY DIRECT, + INDIRECT, + INCIDENTAL, + SPECIAL, + EXEMPLARY, + OR##CONSEQUENTIAL DAMAGES(INCLUDING, + BUT NOT LIMITED TO, + PROCUREMENT OF##SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; + OR BUSINESS##INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + WHETHER IN##CONTRACT, + STRICT LIABILITY, + OR TORT(INCLUDING NEGLIGENCE OR + OTHERWISE)##ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + EVEN IF ADVISED OF THE##POSSIBILITY OF SUCH DAMAGE + .################################################################################ # -include("openroad") + include("openroad") -option(DEBUG_DRT_UNDERFLOW "Check for underflow in drt cost calculations" OFF) + option(DEBUG_DRT_UNDERFLOW + "Check for underflow in drt cost calculations" OFF) -project(drt - LANGUAGES CXX -) + project(drt LANGUAGES CXX) -set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${PROJECT_SOURCE_DIR}/cmake) + set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${ + PROJECT_SOURCE_DIR} + / cmake) -include(CheckIPOSupported) -check_ipo_supported(RESULT ipo_supported OUTPUT error) + include(CheckIPOSupported) check_ipo_supported( + RESULT ipo_supported OUTPUT error) -find_package(Boost REQUIRED COMPONENTS serialization) -find_package(OpenMP REQUIRED) -find_package(VTune) + find_package(Boost REQUIRED COMPONENTS serialization) find_package( + OpenMP REQUIRED) find_package(VTune) -swig_lib(NAME drt - NAMESPACE drt - I_FILE src/TritonRoute.i - SCRIPTS src/TritonRoute.tcl -) + swig_lib( + NAME drt NAMESPACE drt I_FILE src + / TritonRoute.i SCRIPTS src / TritonRoute.tcl) -set(FLEXROUTE_HOME ${PROJECT_SOURCE_DIR}) + set(FLEXROUTE_HOME ${PROJECT_SOURCE_DIR}) -target_sources(drt - PRIVATE - src/gr/FlexGRCMap.cpp - src/gr/FlexGR.cpp - src/gr/FlexGR_end.cpp - src/gr/FlexGRGridGraph.cpp - src/gr/FlexGRGridGraph_maze.cpp - src/gr/FlexGR_init.cpp - src/gr/FlexGR_maze.cpp - src/gr/FlexGR_rq.cpp - src/gr/FlexGR_topo.cpp - src/dr/FlexDR_conn.cpp - src/dr/FlexDR_init.cpp - src/dr/FlexDR.cpp - src/db/drObj/drNet.cpp - src/dr/FlexDR_maze.cpp - src/dr/FlexGridGraph_maze.cpp - src/dr/FlexGridGraph.cpp - src/dr/FlexDR_rq.cpp - src/dr/FlexDR_end.cpp - src/dr/FlexDR_graphics.cpp - src/ta/FlexTA_end.cpp - src/ta/FlexTA_init.cpp - src/ta/FlexTA_rq.cpp - src/ta/FlexTA_assign.cpp - src/ta/FlexTA.cpp - src/ta/FlexTA_graphics.cpp - src/global.cpp - src/gc/FlexGC_end.cpp - src/gc/FlexGC_rq.cpp - src/gc/FlexGC.cpp - src/gc/FlexGC_init.cpp - src/gc/FlexGC_main.cpp - src/gc/FlexGC_eol.cpp - src/gc/FlexGC_inf.cpp - src/gc/FlexGC_cut.cpp - src/gc/FlexGC_metspc.cpp - src/db/drObj/drAccessPattern.cpp - src/db/drObj/drPin.cpp - src/db/drObj/drShape.cpp - src/db/drObj/drVia.cpp - src/db/infra/frTime_helper.cpp - src/db/infra/frTime.cpp - src/db/infra/KDTree.cpp - src/db/taObj/taShape.cpp - src/db/obj/frShape.cpp - src/db/obj/frInst.cpp - src/db/obj/frVia.cpp - src/db/obj/frAccess.cpp - src/db/obj/frRPin.cpp - src/db/obj/frNode.cpp - src/db/obj/frInstTerm.cpp - src/db/obj/frNet.cpp - src/db/tech/frConstraint.cc - src/db/obj/frMarker.cpp - src/db/tech/frLayer.cc - src/frRegionQuery.cpp - src/io/io_pin.cpp - src/io/io.cpp - src/io/GuideProcessor.cpp - src/io/io_parser_helper.cpp - src/pa/FlexPA_init.cpp - src/pa/FlexPA.cpp - src/pa/FlexPA_prep.cpp - src/pa/FlexPA_unique.cpp - src/pa/FlexPA_graphics.cpp - src/rp/FlexRP_init.cpp - src/rp/FlexRP.cpp - src/rp/FlexRP_prep.cpp - src/distributed/frArchive.cpp - src/distributed/drUpdate.cpp - src/distributed/paUpdate.cpp - src/TritonRoute.cpp - src/MakeTritonRoute.cpp - src/frBaseTypes.cpp - src/DesignCallBack.cpp -) + target_sources(drt PRIVATE src / gr + / FlexGRCMap.cpp src / gr + / FlexGR.cpp src / gr + / FlexGR_end.cpp src / gr + / FlexGRGridGraph.cpp + src + / gr + / FlexGRGridGraph_maze.cpp + src + / gr + / FlexGR_init.cpp + src + / gr + / FlexGR_maze.cpp + src + / gr / FlexGR_rq.cpp src + / gr + / FlexGR_topo.cpp + src + / dr + / FlexDR_conn.cpp + src + / dr + / FlexDR_init.cpp + src + / dr + / FlexDR.cpp src + / db / drObj / drNet.cpp src + / dr + / FlexDR_maze.cpp + src + / dr + / FlexGridGraph_maze.cpp src + / dr / FlexGridGraph.cpp src + / dr / FlexDR_rq.cpp src + / dr / FlexDR_end.cpp src + / dr + / FlexDR_graphics.cpp src + / ta / FlexTA_end.cpp src + / ta / FlexTA_init.cpp src + / ta / FlexTA_rq.cpp src + / ta / FlexTA_assign.cpp src + / ta + / FlexTA.cpp src / ta + / FlexTA_graphics.cpp src + / global.cpp src / gc + / FlexGC_end.cpp src / gc + / FlexGC_rq.cpp src / gc + / FlexGC.cpp src + / gc / FlexGC_init.cpp src + / gc / FlexGC_main.cpp src + / gc / FlexGC_eol.cpp src + / gc / FlexGC_inf.cpp src + / gc / FlexGC_cut.cpp src + / gc / FlexGC_metspc.cpp src + / db / drObj + / drAccessPattern.cpp src + / db / drObj / drPin.cpp src + / db / drObj + / drShape.cpp + src + / db / drObj / drVia.cpp src + / db / infra + / frTime_helper.cpp src / db + / infra + / frTime.cpp src / db + / infra + / KDTree.cpp src / db + / taObj + / taShape.cpp + src + / db / obj / frShape.cpp src + / db / obj / frInst.cpp src + / db / obj / frVia.cpp src + / db + / obj / frAccess.cpp src + / db / obj / frRPin.cpp src + / db / obj / frNode.cpp src + / db / obj + / frInstTerm.cpp src + / db / obj / frNet.cpp src + / db + / tech / frConstraint.cc src + / db + / obj / frMarker.cpp src + / db / tech / frLayer.cc src + / frRegionQuery.cpp src / io + / io_pin.cpp src / io + / io.cpp src / io + / GuideProcessor.cpp src + / io + / io_parser_helper.cpp src + / pa / FlexPA_init.cpp src + / pa + / FlexPA.cpp src + / pa / FlexPA_prep.cpp src + / pa + / FlexPA_acc_point.cpp src + / pa + / FlexPA_acc_pattern.cpp src + / pa + / FlexPA_row_pattern.cpp src + / pa / FlexPA_unique.cpp src + / pa + / FlexPA_graphics.cpp src + / rp / FlexRP_init.cpp src + / rp + / FlexRP.cpp src + / rp / FlexRP_prep.cpp src + / distributed + / frArchive.cpp src + / distributed / drUpdate.cpp src + / distributed / paUpdate.cpp src + / TritonRoute.cpp + src + / MakeTritonRoute.cpp src + / frBaseTypes.cpp + src + / DesignCallBack.cpp) -target_include_directories(drt - PUBLIC - include + target_include_directories( + drt PUBLIC include - PRIVATE - src -) + PRIVATE + src) -target_link_libraries(drt - PUBLIC - gui - odb - stt - OpenSTA - utl - dst - dbSta - Threads::Threads - OpenMP::OpenMP_CXX - ${Boost_LIBRARIES} - ZLIB::ZLIB -) + target_link_libraries( + drt PUBLIC gui odb stt OpenSTA utl dst + dbSta Threads::Threads OpenMP:: + OpenMP_CXX ${ + Boost_LIBRARIES} ZLIB:: + ZLIB) -messages( - TARGET drt -) + messages(TARGET drt) -############################################################ -# Compiler flags -############################################################ -# Todo: add -Wextra and cleanup warnings -target_compile_options(drt - PRIVATE - $<$:-Wall -pedantic -Wcast-qual -Wredundant-decls -Wformat-security> - $<$:-Wall -pedantic -Wcast-qual -Wredundant-decls -Wformat-security -Wno-gnu-zero-variadic-macro-arguments> - $<$:-Wall -pedantic -Wcast-qual -Wredundant-decls -Wformat-security -Wno-gnu-zero-variadic-macro-arguments> - ) + ############################################################ +#Compiler flags + ############################################################ +#Todo : add - Wextra and cleanup warnings + target_compile_options( + drt PRIVATE $<$ : -Wall - pedantic - Wcast + - qual - Wredundant - decls - Wformat - security> + $<$ : -Wall - pedantic - Wcast - qual + - Wredundant - decls - Wformat - security - Wno - gnu - zero + - variadic - macro - arguments> + $<$ : -Wall - pedantic - Wcast - qual + - Wredundant - decls - Wformat - security - Wno - gnu - zero + - variadic - macro - arguments>) -############################################################ -# Unit testing -############################################################ -if(ENABLE_TESTS) - enable_testing() + ############################################################ +#Unit testing + ############################################################if ( + ENABLE_TESTS) enable_testing() - add_executable(trTest - ${FLEXROUTE_HOME}/test/gcTest.cpp - ${FLEXROUTE_HOME}/test/fixture.cpp - ${FLEXROUTE_HOME}/test/stubs.cpp - ${OPENROAD_HOME}/src/gui/src/stub.cpp - ) + add_executable(trTest ${FLEXROUTE_HOME} / test + / gcTest.cpp ${FLEXROUTE_HOME} / test + / fixture.cpp ${FLEXROUTE_HOME} / test + / stubs.cpp ${OPENROAD_HOME} / src / gui / src + / stub.cpp) - target_include_directories(trTest - PRIVATE - ${FLEXROUTE_HOME}/src - ${OPENROAD_HOME}/include - ) + target_include_directories(trTest PRIVATE ${FLEXROUTE_HOME} + / src ${OPENROAD_HOME} / include) - target_link_libraries(trTest - drt - odb - ) + target_link_libraries(trTest drt odb) - # Use the shared library if found. We need to pass this info to - # the code to select the corresponding include. Using the shared - # library speeds up compilation. - if (Boost_unit_test_framework_FOUND) - message(STATUS "Boost unit_test_framework library found") - target_link_libraries(trTest - Boost::unit_test_framework - ) - target_compile_definitions(trTest - PRIVATE - HAS_BOOST_UNIT_TEST_LIBRARY - ) - endif() +#Use the shared library if found.We need to pass this info to +#the code to select the corresponding include.Using the shared +#library speeds up compilation. + if (Boost_unit_test_framework_FOUND) message( + STATUS "Boost unit_test_framework library found") + target_link_libraries( + trTest Boost::unit_test_framework) + target_compile_definitions( + trTest PRIVATE + HAS_BOOST_UNIT_TEST_LIBRARY) endif() - add_test(NAME trTest COMMAND trTest) - add_dependencies(build_and_test trTest) + add_test(NAME trTest COMMAND + trTest) add_dependencies(build_and_test + trTest) - if(DEBUG_DRT_UNDERFLOW) - target_compile_definitions(drt - PRIVATE - DEBUG_DRT_UNDERFLOW=1 - ) - endif() -endif() + if (DEBUG_DRT_UNDERFLOW) target_compile_definitions( + drt PRIVATE + DEBUG_DRT_UNDERFLOW + = 1) endif() endif() -############################################################ -# VTune ITT API -############################################################ + ############################################################ +#VTune ITT API + ############################################################ -if (VTune_FOUND) - target_compile_definitions(drt - PUBLIC - HAS_VTUNE=1 - ) + if (VTune_FOUND) target_compile_definitions(drt PUBLIC HAS_VTUNE = 1) - target_link_libraries(drt - PUBLIC - VTune::VTune - ) + target_link_libraries(drt PUBLIC VTune::VTune) -endif(VTune_FOUND) + endif(VTune_FOUND) -if (Python3_FOUND AND BUILD_PYTHON) - swig_lib(NAME drt_py - NAMESPACE drt - LANGUAGE python - I_FILE src/TritonRoute-py.i - SWIG_INCLUDES ${PROJECT_SOURCE_DIR}/include/drt - SCRIPTS ${CMAKE_CURRENT_BINARY_DIR}/drt_py.py - ) + if (Python3_FOUND AND BUILD_PYTHON) swig_lib( + NAME drt_py NAMESPACE drt LANGUAGE python I_FILE src + / TritonRoute + - py.i SWIG_INCLUDES ${PROJECT_SOURCE_DIR} / include + / drt SCRIPTS ${CMAKE_CURRENT_BINARY_DIR} + / drt_py.py) - target_include_directories(drt_py - PUBLIC - include - ) + target_include_directories(drt_py PUBLIC include) - target_link_libraries(drt_py - PUBLIC - drt - ) + target_link_libraries(drt_py PUBLIC drt) -endif() + endif() -add_subdirectory(test) \ No newline at end of file + add_subdirectory(test) \ No newline at end of file diff --git a/src/drt/src/pa/FlexPA_acc_pattern.cpp b/src/drt/src/pa/FlexPA_acc_pattern.cpp new file mode 100644 index 00000000000..d88fc8cf26c --- /dev/null +++ b/src/drt/src/pa/FlexPA_acc_pattern.cpp @@ -0,0 +1,52 @@ +/* Authors: Lutong Wang and Bangqi Xu */ +/* + * Copyright (c) 2019, The Regents of the University of California + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the University nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include +#include +#include + +#include "FlexPA.h" +#include "FlexPA_graphics.h" +#include "db/infra/frTime.h" +#include "distributed/PinAccessJobDescription.h" +#include "distributed/frArchive.h" +#include "dst/Distributed.h" +#include "dst/JobMessage.h" +#include "frProfileTask.h" +#include "gc/FlexGC.h" +#include "serialization.h" +#include "utl/exception.h" + +namespace drt { + +using utl::ThreadException; + +} \ No newline at end of file diff --git a/src/drt/src/pa/FlexPA_acc_point.cpp b/src/drt/src/pa/FlexPA_acc_point.cpp new file mode 100644 index 00000000000..b822826978d --- /dev/null +++ b/src/drt/src/pa/FlexPA_acc_point.cpp @@ -0,0 +1,51 @@ +/* Authors: Lutong Wang and Bangqi Xu */ +/* + * Copyright (c) 2019, The Regents of the University of California + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the University nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +// #include +// #include +// #include +// #include + +#include "FlexPA.h" +#include "FlexPA_graphics.h" +// #include "db/infra/frTime.h" +// #include "distributed/PinAccessJobDescription.h" +// #include "distributed/frArchive.h" +// #include "dst/Distributed.h" +// #include "dst/JobMessage.h" +#include "frProfileTask.h" +#include "gc/FlexGC.h" +// #include "serialization.h" +#include "utl/exception.h" + +namespace drt { + +using utl::ThreadException; + +} \ No newline at end of file diff --git a/src/drt/src/pa/FlexPA_row_pattern.cpp b/src/drt/src/pa/FlexPA_row_pattern.cpp new file mode 100644 index 00000000000..d88fc8cf26c --- /dev/null +++ b/src/drt/src/pa/FlexPA_row_pattern.cpp @@ -0,0 +1,52 @@ +/* Authors: Lutong Wang and Bangqi Xu */ +/* + * Copyright (c) 2019, The Regents of the University of California + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the University nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include +#include +#include + +#include "FlexPA.h" +#include "FlexPA_graphics.h" +#include "db/infra/frTime.h" +#include "distributed/PinAccessJobDescription.h" +#include "distributed/frArchive.h" +#include "dst/Distributed.h" +#include "dst/JobMessage.h" +#include "frProfileTask.h" +#include "gc/FlexGC.h" +#include "serialization.h" +#include "utl/exception.h" + +namespace drt { + +using utl::ThreadException; + +} \ No newline at end of file From 804080d6d789caf0e74a39848087bb45c64b85b2 Mon Sep 17 00:00:00 2001 From: bernardo Date: Sat, 14 Dec 2024 22:48:00 +0000 Subject: [PATCH 52/98] move serializeInstRows Signed-off-by: bernardo move prepPatternInstRows Signed-off-by: bernardo move genInstRowPattern Signed-off-by: bernardo move genInstRowPatternInit Signed-off-by: bernardo move genInstRowPatternPerform Signed-off-by: bernardo move genInstRowPattern_commit Signed-off-by: bernardo move genInstRowPattern_print Signed-off-by: bernardo move getEdgeCost Signed-off-by: bernardo move addAccessPatternObj Signed-off-by: bernardo --- src/drt/src/pa/FlexPA_prep.cpp | 403 ------------------------- src/drt/src/pa/FlexPA_row_pattern.cpp | 406 +++++++++++++++++++++++++- 2 files changed, 405 insertions(+), 404 deletions(-) diff --git a/src/drt/src/pa/FlexPA_prep.cpp b/src/drt/src/pa/FlexPA_prep.cpp index c6117dcb4f4..83c9ba08415 100644 --- a/src/drt/src/pa/FlexPA_prep.cpp +++ b/src/drt/src/pa/FlexPA_prep.cpp @@ -1462,14 +1462,6 @@ static inline void serializePatterns( ar << patterns; file.close(); } -static inline void serializeInstRows( - const std::vector>& inst_rows, - const std::string& file_name) -{ - paUpdate update; - update.setInstRows(inst_rows); - paUpdate::serialize(update, file_name); -} void FlexPA::initInstAccessPoints(frInst* inst) { @@ -1567,109 +1559,6 @@ void FlexPA::initAllAccessPoints() } } -void FlexPA::prepPatternInstRows(std::vector> inst_rows) -{ - ThreadException exception; - int cnt = 0; - if (isDistributed()) { - omp_set_num_threads(cloud_sz_); - const int batch_size = inst_rows.size() / cloud_sz_; - paUpdate all_updates; -#pragma omp parallel for schedule(dynamic) - for (int i = 0; i < cloud_sz_; i++) { - try { - std::vector>::const_iterator start - = inst_rows.begin() + (i * batch_size); - std::vector>::const_iterator end - = (i == cloud_sz_ - 1) ? inst_rows.end() : start + batch_size; - std::vector> batch(start, end); - std::string path = fmt::format("{}/batch_{}.bin", shared_vol_, i); - serializeInstRows(batch, path); - dst::JobMessage msg(dst::JobMessage::PIN_ACCESS, - dst::JobMessage::UNICAST), - result; - std::unique_ptr uDesc - = std::make_unique(); - uDesc->setPath(path); - uDesc->setType(PinAccessJobDescription::INST_ROWS); - msg.setJobDescription(std::move(uDesc)); - const bool ok - = dist_->sendJob(msg, remote_host_.c_str(), remote_port_, result); - if (!ok) { - logger_->error(utl::DRT, 329, "Error sending INST_ROWS Job to cloud"); - } - auto desc - = static_cast(result.getJobDescription()); - paUpdate update; - paUpdate::deserialize(design_, update, desc->getPath()); - for (const auto& [term, aps] : update.getGroupResults()) { - term->setAccessPoints(aps); - } -#pragma omp critical - { - for (const auto& res : update.getGroupResults()) { - all_updates.addGroupResult(res); - } - for (i = 0; i < batch.size(); i++) { - cnt++; - if (router_cfg_->VERBOSE > 0) { - if (cnt % (cnt > 100000 ? 100000 : 10000) == 0) { - logger_->info(DRT, 110, " Complete {} groups.", cnt); - } - } - } - } - } catch (...) { - exception.capture(); - } - } - // send updates back to workers - dst::JobMessage msg(dst::JobMessage::PIN_ACCESS, - dst::JobMessage::BROADCAST), - result; - const std::string updates_path - = fmt::format("{}/final_updates.bin", shared_vol_); - paUpdate::serialize(all_updates, updates_path); - std::unique_ptr uDesc - = std::make_unique(); - uDesc->setPath(updates_path); - uDesc->setType(PinAccessJobDescription::UPDATE_PA); - msg.setJobDescription(std::move(uDesc)); - const bool ok - = dist_->sendJob(msg, remote_host_.c_str(), remote_port_, result); - if (!ok) { - logger_->error(utl::DRT, 332, "Error sending UPDATE_PA Job to cloud"); - } - } else { - omp_set_num_threads(router_cfg_->MAX_THREADS); - // choose access pattern of a row of insts - int rowIdx = 0; -#pragma omp parallel for schedule(dynamic) - for (int i = 0; i < (int) inst_rows.size(); i++) { // NOLINT - try { - auto& instRow = inst_rows[i]; - genInstRowPattern(instRow); -#pragma omp critical - { - rowIdx++; - cnt++; - if (router_cfg_->VERBOSE > 0) { - if (cnt % (cnt > 100000 ? 100000 : 10000) == 0) { - logger_->info(DRT, 82, " Complete {} groups.", cnt); - } - } - } - } catch (...) { - exception.capture(); - } - } - } - exception.rethrow(); - if (router_cfg_->VERBOSE > 0) { - logger_->info(DRT, 84, " Complete {} groups.", cnt); - } -} - void FlexPA::prepPattern() { ProfileTask profile("PA:pattern"); @@ -1823,298 +1712,6 @@ void FlexPA::revertAccessPoints() } } -// calculate which pattern to be used for each inst -// the insts must be in the same row and sorted from left to right -void FlexPA::genInstRowPattern(std::vector& insts) -{ - if (insts.empty()) { - return; - } - - std::vector>> nodes(insts.size() + 2); - - genInstRowPatternInit(nodes, insts); - genInstRowPatternPerform(nodes, insts); - genInstRowPattern_commit(nodes, insts); -} - -// init dp node array for valid access patterns -void FlexPA::genInstRowPatternInit( - std::vector>>& nodes, - const std::vector& insts) -{ - // init virtual nodes - const int source_node_idx = insts.size() + 1; - nodes[source_node_idx] = std::vector>(1); - nodes[source_node_idx][0] = std::make_unique(); - nodes[source_node_idx][0]->setNodeCost(0); - nodes[source_node_idx][0]->setPathCost(0); - nodes[source_node_idx][0]->setIdx({insts.size() + 1, 0}); - nodes[source_node_idx][0]->setAsSource(); - - const int sink_node_idx = insts.size(); - nodes[sink_node_idx] = std::vector>(1); - nodes[sink_node_idx][0] = std::make_unique(); - nodes[sink_node_idx][0]->setNodeCost(0); - nodes[sink_node_idx][0]->setIdx({insts.size(), 0}); - nodes[sink_node_idx][0]->setAsSink(); - - // init inst nodes - for (int inst_idx = 0; inst_idx < (int) insts.size(); inst_idx++) { - auto& inst = insts[inst_idx]; - const int unique_inst_idx = unique_insts_.getIndex(inst); - auto& inst_patterns = unique_inst_patterns_[unique_inst_idx]; - nodes[inst_idx] - = std::vector>(inst_patterns.size()); - for (int acc_pattern_idx = 0; acc_pattern_idx < (int) inst_patterns.size(); - acc_pattern_idx++) { - nodes[inst_idx][acc_pattern_idx] = std::make_unique(); - auto access_pattern = inst_patterns[acc_pattern_idx].get(); - nodes[inst_idx][acc_pattern_idx]->setNodeCost(access_pattern->getCost()); - nodes[inst_idx][acc_pattern_idx]->setIdx({inst_idx, acc_pattern_idx}); - } - } -} - -void FlexPA::genInstRowPatternPerform( - std::vector>>& nodes, - const std::vector& insts) -{ - const int source_node_idx = insts.size() + 1; - for (int curr_inst_idx = 0; curr_inst_idx <= (int) insts.size(); - curr_inst_idx++) { - for (int curr_acc_pattern_idx = 0; - curr_acc_pattern_idx < nodes[curr_inst_idx].size(); - curr_acc_pattern_idx++) { - FlexDPNode* curr_node = nodes[curr_inst_idx][curr_acc_pattern_idx].get(); - if (curr_node->getNodeCost() == std::numeric_limits::max()) { - continue; - } - const int prev_inst_idx - = curr_inst_idx > 0 ? curr_inst_idx - 1 : source_node_idx; - for (int prev_acc_pattern_idx = 0; - prev_acc_pattern_idx < nodes[prev_inst_idx].size(); - prev_acc_pattern_idx++) { - FlexDPNode* prev_node - = nodes[prev_inst_idx][prev_acc_pattern_idx].get(); - if (prev_node->getPathCost() == std::numeric_limits::max()) { - continue; - } - - const int edge_cost = getEdgeCost(prev_node, curr_node, insts); - if (curr_node->getPathCost() == std::numeric_limits::max() - || curr_node->getPathCost() - > prev_node->getPathCost() + edge_cost) { - curr_node->setPathCost(prev_node->getPathCost() + edge_cost); - curr_node->setPrevNode(prev_node); - } - } - } - } -} - -void FlexPA::genInstRowPattern_commit( - std::vector>>& nodes, - const std::vector& insts) -{ - const bool is_debug_mode = false; - FlexDPNode* curr_node = nodes[insts.size()][0].get(); - int inst_cnt = insts.size(); - std::vector inst_access_pattern_idx(insts.size(), -1); - while (curr_node->hasPrevNode()) { - // non-virtual node - if (inst_cnt != (int) insts.size()) { - auto [curr_inst_idx, curr_acc_patterns_idx] = curr_node->getIdx(); - inst_access_pattern_idx[curr_inst_idx] = curr_acc_patterns_idx; - - auto& inst = insts[curr_inst_idx]; - int access_point_idx = 0; - const int unique_inst_idx = unique_insts_.getIndex(inst); - auto access_pattern - = unique_inst_patterns_[unique_inst_idx][curr_acc_patterns_idx].get(); - auto& access_points = access_pattern->getPattern(); - - // update inst_term ap - for (auto& inst_term : inst->getInstTerms()) { - if (isSkipInstTerm(inst_term.get())) { - continue; - } - - int pin_idx = 0; - // to avoid unused variable warning in GCC - for (int i = 0; i < (int) (inst_term->getTerm()->getPins().size()); - i++) { - auto& access_point = access_points[access_point_idx]; - inst_term->setAccessPoint(pin_idx, access_point); - pin_idx++; - access_point_idx++; - } - } - } - curr_node = curr_node->getPrevNode(); - inst_cnt--; - } - - if (inst_cnt != -1) { - std::string inst_names; - for (frInst* inst : insts) { - inst_names += '\n' + inst->getName(); - } - logger_->error(DRT, - 85, - "Valid access pattern combination not found for {}", - inst_names); - } - - if (is_debug_mode) { - genInstRowPattern_print(nodes, insts); - } -} - -void FlexPA::genInstRowPattern_print( - std::vector>>& nodes, - const std::vector& insts) -{ - FlexDPNode* curr_node = nodes[insts.size()][0].get(); - int inst_cnt = insts.size(); - std::vector inst_access_pattern_idx(insts.size(), -1); - - while (curr_node->hasPrevNode()) { - // non-virtual node - if (inst_cnt != (int) insts.size()) { - auto [curr_inst_idx, curr_acc_pattern_idx] = curr_node->getIdx(); - inst_access_pattern_idx[curr_inst_idx] = curr_acc_pattern_idx; - - // print debug information - auto& inst = insts[curr_inst_idx]; - int access_point_idx = 0; - const int unique_inst_idx = unique_insts_.getIndex(inst); - auto access_pattern - = unique_inst_patterns_[unique_inst_idx][curr_acc_pattern_idx].get(); - auto& access_points = access_pattern->getPattern(); - - for (auto& inst_term : inst->getInstTerms()) { - if (isSkipInstTerm(inst_term.get())) { - continue; - } - - // for (auto &pin: inst_term->getTerm()->getPins()) { - // to avoid unused variable warning in GCC - for (int i = 0; i < (int) (inst_term->getTerm()->getPins().size()); - i++) { - auto& access_point = access_points[access_point_idx]; - if (access_point) { - const Point& pt(access_point->getPoint()); - if (inst_term->hasNet()) { - std::cout << " gcclean2via " << inst->getName() << " " - << inst_term->getTerm()->getName() << " " - << access_point->getViaDef()->getName() << " " << pt.x() - << " " << pt.y() << " " << inst->getOrient().getString() - << "\n"; - inst_term_valid_via_ap_cnt_++; - } - } - access_point_idx++; - } - } - } - curr_node = curr_node->getPrevNode(); - inst_cnt--; - } - - std::cout << std::flush; - - if (inst_cnt != -1) { - logger_->error(DRT, 276, "Valid access pattern combination not found."); - } -} - -int FlexPA::getEdgeCost(FlexDPNode* prev_node, - FlexDPNode* curr_node, - const std::vector& insts) -{ - int edge_cost = 0; - auto [prev_inst_idx, prev_acc_pattern_idx] = prev_node->getIdx(); - auto [curr_inst_idx, curr_acc_pattern_idx] = curr_node->getIdx(); - if (prev_node->isSource() || curr_node->isSink()) { - return edge_cost; - } - - // check DRC - std::vector> temp_vias; - std::vector> objs; - // push the vias from prev inst access pattern and curr inst access pattern - const auto prev_inst = insts[prev_inst_idx]; - const auto prev_unique_inst_idx = unique_insts_.getIndex(prev_inst); - const auto curr_inst = insts[curr_inst_idx]; - const auto curr_unique_inst_idx = unique_insts_.getIndex(curr_inst); - const auto prev_pin_access_pattern - = unique_inst_patterns_[prev_unique_inst_idx][prev_acc_pattern_idx].get(); - const auto curr_pin_access_pattern - = unique_inst_patterns_[curr_unique_inst_idx][curr_acc_pattern_idx].get(); - addAccessPatternObj( - prev_inst, prev_pin_access_pattern, objs, temp_vias, true); - addAccessPatternObj( - curr_inst, curr_pin_access_pattern, objs, temp_vias, false); - - const bool has_vio = !genPatterns_gc({prev_inst, curr_inst}, objs, Edge); - if (!has_vio) { - const int prev_node_cost = prev_node->getNodeCost(); - const int curr_node_cost = curr_node->getNodeCost(); - edge_cost = (prev_node_cost + curr_node_cost) / 2; - } else { - edge_cost = 1000; - } - - return edge_cost; -} - -void FlexPA::addAccessPatternObj( - frInst* inst, - FlexPinAccessPattern* access_pattern, - std::vector>& objs, - std::vector>& vias, - const bool isPrev) -{ - const dbTransform xform = inst->getNoRotationTransform(); - int access_point_idx = 0; - auto& access_points = access_pattern->getPattern(); - - for (auto& inst_term : inst->getInstTerms()) { - if (isSkipInstTerm(inst_term.get())) { - continue; - } - - // to avoid unused variable warning in GCC - for (int i = 0; i < (int) (inst_term->getTerm()->getPins().size()); i++) { - auto& access_point = access_points[access_point_idx]; - if (!access_point - || (isPrev && access_point != access_pattern->getBoundaryAP(false))) { - access_point_idx++; - continue; - } - if ((!isPrev) && access_point != access_pattern->getBoundaryAP(true)) { - access_point_idx++; - continue; - } - if (access_point->hasAccess(frDirEnum::U)) { - auto via = std::make_unique(access_point->getViaDef()); - Point pt(access_point->getPoint()); - xform.apply(pt); - via->setOrigin(pt); - auto rvia = via.get(); - if (inst_term->hasNet()) { - objs.emplace_back(rvia, inst_term->getNet()); - } else { - objs.emplace_back(rvia, inst_term.get()); - } - vias.push_back(std::move(via)); - } - access_point_idx++; - } - } -} - void FlexPA::getInsts(std::vector& insts) { std::set target_frinsts; diff --git a/src/drt/src/pa/FlexPA_row_pattern.cpp b/src/drt/src/pa/FlexPA_row_pattern.cpp index d88fc8cf26c..1ca2b6c136e 100644 --- a/src/drt/src/pa/FlexPA_row_pattern.cpp +++ b/src/drt/src/pa/FlexPA_row_pattern.cpp @@ -49,4 +49,408 @@ namespace drt { using utl::ThreadException; -} \ No newline at end of file +static inline void serializeInstRows( + const std::vector>& inst_rows, + const std::string& file_name) +{ + paUpdate update; + update.setInstRows(inst_rows); + paUpdate::serialize(update, file_name); +} + +void FlexPA::prepPatternInstRows(std::vector> inst_rows) +{ + ThreadException exception; + int cnt = 0; + if (isDistributed()) { + omp_set_num_threads(cloud_sz_); + const int batch_size = inst_rows.size() / cloud_sz_; + paUpdate all_updates; +#pragma omp parallel for schedule(dynamic) + for (int i = 0; i < cloud_sz_; i++) { + try { + std::vector>::const_iterator start + = inst_rows.begin() + (i * batch_size); + std::vector>::const_iterator end + = (i == cloud_sz_ - 1) ? inst_rows.end() : start + batch_size; + std::vector> batch(start, end); + std::string path = fmt::format("{}/batch_{}.bin", shared_vol_, i); + serializeInstRows(batch, path); + dst::JobMessage msg(dst::JobMessage::PIN_ACCESS, + dst::JobMessage::UNICAST), + result; + std::unique_ptr uDesc + = std::make_unique(); + uDesc->setPath(path); + uDesc->setType(PinAccessJobDescription::INST_ROWS); + msg.setJobDescription(std::move(uDesc)); + const bool ok + = dist_->sendJob(msg, remote_host_.c_str(), remote_port_, result); + if (!ok) { + logger_->error(utl::DRT, 329, "Error sending INST_ROWS Job to cloud"); + } + auto desc + = static_cast(result.getJobDescription()); + paUpdate update; + paUpdate::deserialize(design_, update, desc->getPath()); + for (const auto& [term, aps] : update.getGroupResults()) { + term->setAccessPoints(aps); + } +#pragma omp critical + { + for (const auto& res : update.getGroupResults()) { + all_updates.addGroupResult(res); + } + for (i = 0; i < batch.size(); i++) { + cnt++; + if (router_cfg_->VERBOSE > 0) { + if (cnt % (cnt > 100000 ? 100000 : 10000) == 0) { + logger_->info(DRT, 110, " Complete {} groups.", cnt); + } + } + } + } + } catch (...) { + exception.capture(); + } + } + // send updates back to workers + dst::JobMessage msg(dst::JobMessage::PIN_ACCESS, + dst::JobMessage::BROADCAST), + result; + const std::string updates_path + = fmt::format("{}/final_updates.bin", shared_vol_); + paUpdate::serialize(all_updates, updates_path); + std::unique_ptr uDesc + = std::make_unique(); + uDesc->setPath(updates_path); + uDesc->setType(PinAccessJobDescription::UPDATE_PA); + msg.setJobDescription(std::move(uDesc)); + const bool ok + = dist_->sendJob(msg, remote_host_.c_str(), remote_port_, result); + if (!ok) { + logger_->error(utl::DRT, 332, "Error sending UPDATE_PA Job to cloud"); + } + } else { + omp_set_num_threads(router_cfg_->MAX_THREADS); + // choose access pattern of a row of insts + int rowIdx = 0; +#pragma omp parallel for schedule(dynamic) + for (int i = 0; i < (int) inst_rows.size(); i++) { // NOLINT + try { + auto& instRow = inst_rows[i]; + genInstRowPattern(instRow); +#pragma omp critical + { + rowIdx++; + cnt++; + if (router_cfg_->VERBOSE > 0) { + if (cnt % (cnt > 100000 ? 100000 : 10000) == 0) { + logger_->info(DRT, 82, " Complete {} groups.", cnt); + } + } + } + } catch (...) { + exception.capture(); + } + } + } + exception.rethrow(); + if (router_cfg_->VERBOSE > 0) { + logger_->info(DRT, 84, " Complete {} groups.", cnt); + } +} + +// calculate which pattern to be used for each inst +// the insts must be in the same row and sorted from left to right +void FlexPA::genInstRowPattern(std::vector& insts) +{ + if (insts.empty()) { + return; + } + + std::vector>> nodes(insts.size() + 2); + + genInstRowPatternInit(nodes, insts); + genInstRowPatternPerform(nodes, insts); + genInstRowPattern_commit(nodes, insts); +} + +// init dp node array for valid access patterns +void FlexPA::genInstRowPatternInit( + std::vector>>& nodes, + const std::vector& insts) +{ + // init virtual nodes + const int source_node_idx = insts.size() + 1; + nodes[source_node_idx] = std::vector>(1); + nodes[source_node_idx][0] = std::make_unique(); + nodes[source_node_idx][0]->setNodeCost(0); + nodes[source_node_idx][0]->setPathCost(0); + nodes[source_node_idx][0]->setIdx({insts.size() + 1, 0}); + nodes[source_node_idx][0]->setAsSource(); + + const int sink_node_idx = insts.size(); + nodes[sink_node_idx] = std::vector>(1); + nodes[sink_node_idx][0] = std::make_unique(); + nodes[sink_node_idx][0]->setNodeCost(0); + nodes[sink_node_idx][0]->setIdx({insts.size(), 0}); + nodes[sink_node_idx][0]->setAsSink(); + + // init inst nodes + for (int inst_idx = 0; inst_idx < (int) insts.size(); inst_idx++) { + auto& inst = insts[inst_idx]; + const int unique_inst_idx = unique_insts_.getIndex(inst); + auto& inst_patterns = unique_inst_patterns_[unique_inst_idx]; + nodes[inst_idx] + = std::vector>(inst_patterns.size()); + for (int acc_pattern_idx = 0; acc_pattern_idx < (int) inst_patterns.size(); + acc_pattern_idx++) { + nodes[inst_idx][acc_pattern_idx] = std::make_unique(); + auto access_pattern = inst_patterns[acc_pattern_idx].get(); + nodes[inst_idx][acc_pattern_idx]->setNodeCost(access_pattern->getCost()); + nodes[inst_idx][acc_pattern_idx]->setIdx({inst_idx, acc_pattern_idx}); + } + } +} + +void FlexPA::genInstRowPatternPerform( + std::vector>>& nodes, + const std::vector& insts) +{ + const int source_node_idx = insts.size() + 1; + for (int curr_inst_idx = 0; curr_inst_idx <= (int) insts.size(); + curr_inst_idx++) { + for (int curr_acc_pattern_idx = 0; + curr_acc_pattern_idx < nodes[curr_inst_idx].size(); + curr_acc_pattern_idx++) { + FlexDPNode* curr_node = nodes[curr_inst_idx][curr_acc_pattern_idx].get(); + if (curr_node->getNodeCost() == std::numeric_limits::max()) { + continue; + } + const int prev_inst_idx + = curr_inst_idx > 0 ? curr_inst_idx - 1 : source_node_idx; + for (int prev_acc_pattern_idx = 0; + prev_acc_pattern_idx < nodes[prev_inst_idx].size(); + prev_acc_pattern_idx++) { + FlexDPNode* prev_node + = nodes[prev_inst_idx][prev_acc_pattern_idx].get(); + if (prev_node->getPathCost() == std::numeric_limits::max()) { + continue; + } + + const int edge_cost = getEdgeCost(prev_node, curr_node, insts); + if (curr_node->getPathCost() == std::numeric_limits::max() + || curr_node->getPathCost() + > prev_node->getPathCost() + edge_cost) { + curr_node->setPathCost(prev_node->getPathCost() + edge_cost); + curr_node->setPrevNode(prev_node); + } + } + } + } +} + +void FlexPA::genInstRowPattern_commit( + std::vector>>& nodes, + const std::vector& insts) +{ + const bool is_debug_mode = false; + FlexDPNode* curr_node = nodes[insts.size()][0].get(); + int inst_cnt = insts.size(); + std::vector inst_access_pattern_idx(insts.size(), -1); + while (curr_node->hasPrevNode()) { + // non-virtual node + if (inst_cnt != (int) insts.size()) { + auto [curr_inst_idx, curr_acc_patterns_idx] = curr_node->getIdx(); + inst_access_pattern_idx[curr_inst_idx] = curr_acc_patterns_idx; + + auto& inst = insts[curr_inst_idx]; + int access_point_idx = 0; + const int unique_inst_idx = unique_insts_.getIndex(inst); + auto access_pattern + = unique_inst_patterns_[unique_inst_idx][curr_acc_patterns_idx].get(); + auto& access_points = access_pattern->getPattern(); + + // update inst_term ap + for (auto& inst_term : inst->getInstTerms()) { + if (isSkipInstTerm(inst_term.get())) { + continue; + } + + int pin_idx = 0; + // to avoid unused variable warning in GCC + for (int i = 0; i < (int) (inst_term->getTerm()->getPins().size()); + i++) { + auto& access_point = access_points[access_point_idx]; + inst_term->setAccessPoint(pin_idx, access_point); + pin_idx++; + access_point_idx++; + } + } + } + curr_node = curr_node->getPrevNode(); + inst_cnt--; + } + + if (inst_cnt != -1) { + std::string inst_names; + for (frInst* inst : insts) { + inst_names += '\n' + inst->getName(); + } + logger_->error(DRT, + 85, + "Valid access pattern combination not found for {}", + inst_names); + } + + if (is_debug_mode) { + genInstRowPattern_print(nodes, insts); + } +} + +void FlexPA::genInstRowPattern_print( + std::vector>>& nodes, + const std::vector& insts) +{ + FlexDPNode* curr_node = nodes[insts.size()][0].get(); + int inst_cnt = insts.size(); + std::vector inst_access_pattern_idx(insts.size(), -1); + + while (curr_node->hasPrevNode()) { + // non-virtual node + if (inst_cnt != (int) insts.size()) { + auto [curr_inst_idx, curr_acc_pattern_idx] = curr_node->getIdx(); + inst_access_pattern_idx[curr_inst_idx] = curr_acc_pattern_idx; + + // print debug information + auto& inst = insts[curr_inst_idx]; + int access_point_idx = 0; + const int unique_inst_idx = unique_insts_.getIndex(inst); + auto access_pattern + = unique_inst_patterns_[unique_inst_idx][curr_acc_pattern_idx].get(); + auto& access_points = access_pattern->getPattern(); + + for (auto& inst_term : inst->getInstTerms()) { + if (isSkipInstTerm(inst_term.get())) { + continue; + } + + // for (auto &pin: inst_term->getTerm()->getPins()) { + // to avoid unused variable warning in GCC + for (int i = 0; i < (int) (inst_term->getTerm()->getPins().size()); + i++) { + auto& access_point = access_points[access_point_idx]; + if (access_point) { + const Point& pt(access_point->getPoint()); + if (inst_term->hasNet()) { + std::cout << " gcclean2via " << inst->getName() << " " + << inst_term->getTerm()->getName() << " " + << access_point->getViaDef()->getName() << " " << pt.x() + << " " << pt.y() << " " << inst->getOrient().getString() + << "\n"; + inst_term_valid_via_ap_cnt_++; + } + } + access_point_idx++; + } + } + } + curr_node = curr_node->getPrevNode(); + inst_cnt--; + } + + std::cout << std::flush; + + if (inst_cnt != -1) { + logger_->error(DRT, 276, "Valid access pattern combination not found."); + } +} + +int FlexPA::getEdgeCost(FlexDPNode* prev_node, + FlexDPNode* curr_node, + const std::vector& insts) +{ + int edge_cost = 0; + auto [prev_inst_idx, prev_acc_pattern_idx] = prev_node->getIdx(); + auto [curr_inst_idx, curr_acc_pattern_idx] = curr_node->getIdx(); + if (prev_node->isSource() || curr_node->isSink()) { + return edge_cost; + } + + // check DRC + std::vector> temp_vias; + std::vector> objs; + // push the vias from prev inst access pattern and curr inst access pattern + const auto prev_inst = insts[prev_inst_idx]; + const auto prev_unique_inst_idx = unique_insts_.getIndex(prev_inst); + const auto curr_inst = insts[curr_inst_idx]; + const auto curr_unique_inst_idx = unique_insts_.getIndex(curr_inst); + const auto prev_pin_access_pattern + = unique_inst_patterns_[prev_unique_inst_idx][prev_acc_pattern_idx].get(); + const auto curr_pin_access_pattern + = unique_inst_patterns_[curr_unique_inst_idx][curr_acc_pattern_idx].get(); + addAccessPatternObj( + prev_inst, prev_pin_access_pattern, objs, temp_vias, true); + addAccessPatternObj( + curr_inst, curr_pin_access_pattern, objs, temp_vias, false); + + const bool has_vio = !genPatterns_gc({prev_inst, curr_inst}, objs, Edge); + if (!has_vio) { + const int prev_node_cost = prev_node->getNodeCost(); + const int curr_node_cost = curr_node->getNodeCost(); + edge_cost = (prev_node_cost + curr_node_cost) / 2; + } else { + edge_cost = 1000; + } + + return edge_cost; +} + +void FlexPA::addAccessPatternObj( + frInst* inst, + FlexPinAccessPattern* access_pattern, + std::vector>& objs, + std::vector>& vias, + const bool isPrev) +{ + const dbTransform xform = inst->getNoRotationTransform(); + int access_point_idx = 0; + auto& access_points = access_pattern->getPattern(); + + for (auto& inst_term : inst->getInstTerms()) { + if (isSkipInstTerm(inst_term.get())) { + continue; + } + + // to avoid unused variable warning in GCC + for (int i = 0; i < (int) (inst_term->getTerm()->getPins().size()); i++) { + auto& access_point = access_points[access_point_idx]; + if (!access_point + || (isPrev && access_point != access_pattern->getBoundaryAP(false))) { + access_point_idx++; + continue; + } + if ((!isPrev) && access_point != access_pattern->getBoundaryAP(true)) { + access_point_idx++; + continue; + } + if (access_point->hasAccess(frDirEnum::U)) { + auto via = std::make_unique(access_point->getViaDef()); + Point pt(access_point->getPoint()); + xform.apply(pt); + via->setOrigin(pt); + auto rvia = via.get(); + if (inst_term->hasNet()) { + objs.emplace_back(rvia, inst_term->getNet()); + } else { + objs.emplace_back(rvia, inst_term.get()); + } + vias.push_back(std::move(via)); + } + access_point_idx++; + } + } +} + +} // namespace drt \ No newline at end of file From 90b0f89bd25c6ec05b899f8c5d22b77081aef713 Mon Sep 17 00:00:00 2001 From: bernardo Date: Sat, 14 Dec 2024 23:06:17 +0000 Subject: [PATCH 53/98] move genPatterns Signed-off-by: bernardo move genPatterns_helper Signed-off-by: bernardo move genPatternsInit Signed-off-by: bernardo move genPattern_reset Signed-off-by: bernardo move genPatterns_gc Signed-off-by: bernardo move genPatterns_perform Signed-off-by: bernardo move getEdgeCost Signed-off-by: bernardo move extractAccessPatternFromNodes Signed-off-by: bernardo move genPatterns_commit Signed-off-by: bernardo move genPatternsPrintDebug Signed-off-by: bernardo move genPatterns_print Signed-off-by: bernardo move getFlatEdgeIdx Signed-off-by: bernardo --- src/drt/src/pa/FlexPA_acc_pattern.cpp | 634 ++++++++++++++++++++++++++ src/drt/src/pa/FlexPA_prep.cpp | 634 -------------------------- 2 files changed, 634 insertions(+), 634 deletions(-) diff --git a/src/drt/src/pa/FlexPA_acc_pattern.cpp b/src/drt/src/pa/FlexPA_acc_pattern.cpp index d88fc8cf26c..207c8b028f0 100644 --- a/src/drt/src/pa/FlexPA_acc_pattern.cpp +++ b/src/drt/src/pa/FlexPA_acc_pattern.cpp @@ -49,4 +49,638 @@ namespace drt { using utl::ThreadException; +int FlexPA::genPatterns( + const std::vector>& pins, + int curr_unique_inst_idx) +{ + if (pins.empty()) { + return -1; + } + + int max_access_point_size = 0; + int pin_access_idx = unique_insts_.getPAIndex(pins[0].second->getInst()); + for (auto& [pin, inst_term] : pins) { + max_access_point_size + = std::max(max_access_point_size, + pin->getPinAccess(pin_access_idx)->getNumAccessPoints()); + } + if (max_access_point_size == 0) { + return 0; + } + + // moved for mt + std::set> inst_access_patterns; + std::set> used_access_points; + std::set> viol_access_points; + int num_valid_pattern = 0; + + num_valid_pattern += FlexPA::genPatterns_helper(pins, + inst_access_patterns, + used_access_points, + viol_access_points, + curr_unique_inst_idx, + max_access_point_size); + // try reverse order if no valid pattern + if (num_valid_pattern == 0) { + auto reversed_pins = pins; + reverse(reversed_pins.begin(), reversed_pins.end()); + + num_valid_pattern += FlexPA::genPatterns_helper(reversed_pins, + inst_access_patterns, + used_access_points, + viol_access_points, + curr_unique_inst_idx, + max_access_point_size); + } + + return num_valid_pattern; +} + +int FlexPA::genPatterns_helper( + const std::vector>& pins, + std::set>& inst_access_patterns, + std::set>& used_access_points, + std::set>& viol_access_points, + const int curr_unique_inst_idx, + const int max_access_point_size) +{ + int num_node = (pins.size() + 2) * max_access_point_size; + int num_edge = num_node * max_access_point_size; + int num_valid_pattern = 0; + + std::vector>> nodes(pins.size() + 2); + std::vector vio_edge(num_edge, -1); + + genPatternsInit(nodes, + pins, + inst_access_patterns, + used_access_points, + viol_access_points); + + for (int i = 0; i < router_cfg_->ACCESS_PATTERN_END_ITERATION_NUM; i++) { + genPatterns_reset(nodes, pins); + genPatterns_perform(nodes, + pins, + vio_edge, + used_access_points, + viol_access_points, + curr_unique_inst_idx, + max_access_point_size); + bool is_valid = false; + if (genPatterns_commit(nodes, + pins, + is_valid, + inst_access_patterns, + used_access_points, + viol_access_points, + curr_unique_inst_idx, + max_access_point_size)) { + if (is_valid) { + num_valid_pattern++; + } else { + } + } else { + break; + } + } + return num_valid_pattern; +} + +// init dp node array for valid access points +void FlexPA::genPatternsInit( + std::vector>>& nodes, + const std::vector>& pins, + std::set>& inst_access_patterns, + std::set>& used_access_points, + std::set>& viol_access_points) +{ + // clear temp storage and flag + inst_access_patterns.clear(); + used_access_points.clear(); + viol_access_points.clear(); + + // init virtual nodes + const int source_node_idx = pins.size() + 1; + nodes[source_node_idx] = std::vector>(1); + nodes[source_node_idx][0] = std::make_unique(); + FlexDPNode* source_node = nodes[source_node_idx][0].get(); + source_node->setNodeCost(0); + source_node->setIdx({pins.size() + 1, 0}); + source_node->setPathCost(0); + source_node->setAsSource(); + + const int sink_node_idx = pins.size(); + nodes[sink_node_idx] = std::vector>(1); + nodes[sink_node_idx][0] = std::make_unique(); + FlexDPNode* sink_node = nodes[sink_node_idx][0].get(); + sink_node->setNodeCost(0); + sink_node->setIdx({pins.size(), 0}); + sink_node->setAsSink(); + // init pin nodes + int pin_idx = 0; + int ap_idx = 0; + int pin_access_idx = unique_insts_.getPAIndex(pins[0].second->getInst()); + + for (auto& [pin, inst_term] : pins) { + ap_idx = 0; + auto size = pin->getPinAccess(pin_access_idx)->getAccessPoints().size(); + nodes[pin_idx] = std::vector>(size); + for (auto& ap : pin->getPinAccess(pin_access_idx)->getAccessPoints()) { + nodes[pin_idx][ap_idx] = std::make_unique(); + nodes[pin_idx][ap_idx]->setIdx({pin_idx, ap_idx}); + nodes[pin_idx][ap_idx]->setNodeCost(ap->getCost()); + ap_idx++; + } + pin_idx++; + } +} + +void FlexPA::genPatterns_reset( + std::vector>>& nodes, + const std::vector>& pins) +{ + for (auto& pin_nodes : nodes) { + for (auto& node : pin_nodes) { + node->setPathCost(std::numeric_limits::max()); + node->setPrevNode(nullptr); + } + } + + FlexDPNode* source_node = nodes[pins.size() + 1][0].get(); + source_node->setNodeCost(0); + source_node->setPathCost(0); + + FlexDPNode* sink_node = nodes[pins.size()][0].get(); + sink_node->setNodeCost(0); +} + +bool FlexPA::genPatterns_gc( + const std::set& target_objs, + const std::vector>& objs, + const PatternType pattern_type, + std::set* owners) +{ + if (objs.empty()) { + if (router_cfg_->VERBOSE > 1) { + logger_->warn(DRT, 89, "genPattern_gc objs empty."); + } + return true; + } + + FlexGCWorker design_rule_checker(getTech(), logger_, router_cfg_); + design_rule_checker.setIgnoreMinArea(); + design_rule_checker.setIgnoreLongSideEOL(); + design_rule_checker.setIgnoreCornerSpacing(); + + frCoord llx = std::numeric_limits::max(); + frCoord lly = std::numeric_limits::max(); + frCoord urx = std::numeric_limits::min(); + frCoord ury = std::numeric_limits::min(); + for (auto& [connFig, owner] : objs) { + Rect bbox = connFig->getBBox(); + llx = std::min(llx, bbox.xMin()); + lly = std::min(lly, bbox.yMin()); + urx = std::max(urx, bbox.xMax()); + ury = std::max(ury, bbox.yMax()); + } + const Rect ext_box(llx - 3000, lly - 3000, urx + 3000, ury + 3000); + design_rule_checker.setExtBox(ext_box); + design_rule_checker.setDrcBox(ext_box); + + design_rule_checker.setTargetObjs(target_objs); + if (target_objs.empty()) { + design_rule_checker.setIgnoreDB(); + } + design_rule_checker.initPA0(getDesign()); + for (auto& [connFig, owner] : objs) { + design_rule_checker.addPAObj(connFig, owner); + } + design_rule_checker.initPA1(); + design_rule_checker.main(); + design_rule_checker.end(); + + const bool no_drv = design_rule_checker.getMarkers().empty(); + if (owners) { + for (auto& marker : design_rule_checker.getMarkers()) { + for (auto& src : marker->getSrcs()) { + owners->insert(src); + } + } + } + if (graphics_) { + graphics_->setObjsAndMakers( + objs, design_rule_checker.getMarkers(), pattern_type); + } + return no_drv; +} + +void FlexPA::genPatterns_perform( + std::vector>>& nodes, + const std::vector>& pins, + std::vector& vio_edges, + const std::set>& used_access_points, + const std::set>& viol_access_points, + const int curr_unique_inst_idx, + const int max_access_point_size) +{ + const int source_node_idx = pins.size() + 1; + for (int curr_pin_idx = 0; curr_pin_idx <= (int) pins.size(); + curr_pin_idx++) { + for (int curr_acc_point_idx = 0; + curr_acc_point_idx < (int) nodes[curr_pin_idx].size(); + curr_acc_point_idx++) { + FlexDPNode* curr_node = nodes[curr_pin_idx][curr_acc_point_idx].get(); + if (curr_node->getNodeCost() == std::numeric_limits::max()) { + continue; + } + int prev_pin_idx = curr_pin_idx > 0 ? curr_pin_idx - 1 : source_node_idx; + for (int prev_acc_point_idx = 0; + prev_acc_point_idx < nodes[prev_pin_idx].size(); + prev_acc_point_idx++) { + FlexDPNode* prev_node = nodes[prev_pin_idx][prev_acc_point_idx].get(); + if (prev_node->getPathCost() == std::numeric_limits::max()) { + continue; + } + + const int edge_cost = getEdgeCost(prev_node, + curr_node, + pins, + vio_edges, + used_access_points, + viol_access_points, + curr_unique_inst_idx, + max_access_point_size); + if (curr_node->getPathCost() == std::numeric_limits::max() + || curr_node->getPathCost() + > prev_node->getPathCost() + edge_cost) { + curr_node->setPathCost(prev_node->getPathCost() + edge_cost); + curr_node->setPrevNode(prev_node); + } + } + } + } +} + +int FlexPA::getEdgeCost( + FlexDPNode* prev_node, + FlexDPNode* curr_node, + const std::vector>& pins, + std::vector& vio_edges, + const std::set>& used_access_points, + const std::set>& viol_access_points, + const int curr_unique_inst_idx, + const int max_access_point_size) +{ + int edge_cost = 0; + auto [prev_pin_idx, prev_acc_point_idx] = prev_node->getIdx(); + auto [curr_pin_idx, curr_acc_point_idx] = curr_node->getIdx(); + + if (prev_node->isSource() || curr_node->isSink()) { + return edge_cost; + } + + bool has_vio = false; + // check if the edge has been calculated + int edge_idx = getFlatEdgeIdx(prev_pin_idx, + prev_acc_point_idx, + curr_acc_point_idx, + max_access_point_size); + if (vio_edges[edge_idx] != -1) { + has_vio = (vio_edges[edge_idx] == 1); + } else { + auto curr_unique_inst = unique_insts_.getUnique(curr_unique_inst_idx); + dbTransform xform = curr_unique_inst->getNoRotationTransform(); + // check DRC + std::vector> objs; + const auto& [pin_1, inst_term_1] = pins[prev_pin_idx]; + const auto target_obj = inst_term_1->getInst(); + const int pin_access_idx = unique_insts_.getPAIndex(target_obj); + const auto pa_1 = pin_1->getPinAccess(pin_access_idx); + std::unique_ptr via1; + if (pa_1->getAccessPoint(prev_acc_point_idx)->hasAccess(frDirEnum::U)) { + via1 = std::make_unique( + pa_1->getAccessPoint(prev_acc_point_idx)->getViaDef()); + Point pt1(pa_1->getAccessPoint(prev_acc_point_idx)->getPoint()); + xform.apply(pt1); + via1->setOrigin(pt1); + if (inst_term_1->hasNet()) { + objs.emplace_back(via1.get(), inst_term_1->getNet()); + } else { + objs.emplace_back(via1.get(), inst_term_1); + } + } + + const auto& [pin_2, inst_term_2] = pins[curr_pin_idx]; + const auto pa_2 = pin_2->getPinAccess(pin_access_idx); + std::unique_ptr via2; + if (pa_2->getAccessPoint(curr_acc_point_idx)->hasAccess(frDirEnum::U)) { + via2 = std::make_unique( + pa_2->getAccessPoint(curr_acc_point_idx)->getViaDef()); + Point pt2(pa_2->getAccessPoint(curr_acc_point_idx)->getPoint()); + xform.apply(pt2); + via2->setOrigin(pt2); + if (inst_term_2->hasNet()) { + objs.emplace_back(via2.get(), inst_term_2->getNet()); + } else { + objs.emplace_back(via2.get(), inst_term_2); + } + } + + has_vio = !genPatterns_gc({target_obj}, objs, Edge); + vio_edges[edge_idx] = has_vio; + + // look back for GN14 + if (!has_vio) { + // check one more back + if (prev_node->hasPrevNode()) { + auto prev_prev_node = prev_node->getPrevNode(); + auto [prev_prev_pin_idx, prev_prev_acc_point_idx] + = prev_prev_node->getIdx(); + if (!prev_prev_node->isSource()) { + const auto& [pin_3, inst_term_3] = pins[prev_prev_pin_idx]; + auto pa_3 = pin_3->getPinAccess(pin_access_idx); + std::unique_ptr via3; + if (pa_3->getAccessPoint(prev_prev_acc_point_idx) + ->hasAccess(frDirEnum::U)) { + via3 = std::make_unique( + pa_3->getAccessPoint(prev_prev_acc_point_idx)->getViaDef()); + Point pt3( + pa_3->getAccessPoint(prev_prev_acc_point_idx)->getPoint()); + xform.apply(pt3); + via3->setOrigin(pt3); + if (inst_term_3->hasNet()) { + objs.emplace_back(via3.get(), inst_term_3->getNet()); + } else { + objs.emplace_back(via3.get(), inst_term_3); + } + } + + has_vio = !genPatterns_gc({target_obj}, objs, Edge); + } + } + } + } + + if (!has_vio) { + if ((prev_pin_idx == 0 + && used_access_points.find( + std::make_pair(prev_pin_idx, prev_acc_point_idx)) + != used_access_points.end()) + || (curr_pin_idx == (int) pins.size() - 1 + && used_access_points.find( + std::make_pair(curr_pin_idx, curr_acc_point_idx)) + != used_access_points.end())) { + edge_cost = 100; + } else if (viol_access_points.find( + std::make_pair(prev_pin_idx, prev_acc_point_idx)) + != viol_access_points.end() + || viol_access_points.find( + std::make_pair(curr_pin_idx, curr_acc_point_idx)) + != viol_access_points.end()) { + edge_cost = 1000; + } else { + const int prev_node_cost = prev_node->getNodeCost(); + const int curr_node_cost = curr_node->getNodeCost(); + edge_cost = (prev_node_cost + curr_node_cost) / 2; + } + } else { + edge_cost = 1000 /*violation cost*/; + } + + return edge_cost; +} + +std::vector FlexPA::extractAccessPatternFromNodes( + const std::vector>>& nodes, + const std::vector>& pins, + std::set>& used_access_points) +{ + std::vector access_pattern(pins.size(), -1); + + const FlexDPNode* source_node = nodes[pins.size() + 1][0].get(); + const FlexDPNode* sink_node = nodes[pins.size()][0].get(); + + FlexDPNode* curr_node = sink_node->getPrevNode(); + + while (curr_node != source_node) { + if (!curr_node) { + logger_->error(DRT, 90, "Valid access pattern not found."); + } + + auto [curr_pin_idx, curr_acc_point_idx] = curr_node->getIdx(); + access_pattern[curr_pin_idx] = curr_acc_point_idx; + used_access_points.insert({curr_pin_idx, curr_acc_point_idx}); + + curr_node = curr_node->getPrevNode(); + } + return access_pattern; +} + +bool FlexPA::genPatterns_commit( + const std::vector>>& nodes, + const std::vector>& pins, + bool& is_valid, + std::set>& inst_access_patterns, + std::set>& used_access_points, + std::set>& viol_access_points, + const int curr_unique_inst_idx, + const int max_access_point_size) +{ + std::vector access_pattern + = extractAccessPatternFromNodes(nodes, pins, used_access_points); + // not a new access pattern + if (inst_access_patterns.find(access_pattern) != inst_access_patterns.end()) { + return false; + } + + inst_access_patterns.insert(access_pattern); + // create new access pattern and push to uniqueInstances + auto pin_access_pattern = std::make_unique(); + std::map pin_to_access_point; + // check DRC for the whole pattern + std::vector> objs; + std::vector> temp_vias; + frInst* target_obj = nullptr; + for (int pin_idx = 0; pin_idx < (int) pins.size(); pin_idx++) { + auto acc_point_idx = access_pattern[pin_idx]; + auto& [pin, inst_term] = pins[pin_idx]; + auto inst = inst_term->getInst(); + target_obj = inst; + const int pin_access_idx = unique_insts_.getPAIndex(inst); + const auto pa = pin->getPinAccess(pin_access_idx); + const auto access_point = pa->getAccessPoint(acc_point_idx); + pin_to_access_point[pin] = access_point; + + // add objs + std::unique_ptr via; + if (access_point->hasAccess(frDirEnum::U)) { + via = std::make_unique(access_point->getViaDef()); + auto rvia = via.get(); + temp_vias.push_back(std::move(via)); + + dbTransform xform = inst->getNoRotationTransform(); + Point pt(access_point->getPoint()); + xform.apply(pt); + rvia->setOrigin(pt); + if (inst_term->hasNet()) { + objs.emplace_back(rvia, inst_term->getNet()); + } else { + objs.emplace_back(rvia, inst_term); + } + } + } + + frAccessPoint* left_access_point = nullptr; + frAccessPoint* right_access_point = nullptr; + frCoord left_pt = std::numeric_limits::max(); + frCoord right_pt = std::numeric_limits::min(); + + const auto& [pin, inst_term] = pins[0]; + const auto inst = inst_term->getInst(); + for (auto& inst_term : inst->getInstTerms()) { + if (isSkipInstTerm(inst_term.get())) { + continue; + } + uint64_t n_no_ap_pins = 0; + for (auto& pin : inst_term->getTerm()->getPins()) { + if (pin_to_access_point.find(pin.get()) == pin_to_access_point.end()) { + n_no_ap_pins++; + pin_access_pattern->addAccessPoint(nullptr); + } else { + const auto& ap = pin_to_access_point[pin.get()]; + const Point tmpPt = ap->getPoint(); + if (tmpPt.x() < left_pt) { + left_access_point = ap; + left_pt = tmpPt.x(); + } + if (tmpPt.x() > right_pt) { + right_access_point = ap; + right_pt = tmpPt.x(); + } + pin_access_pattern->addAccessPoint(ap); + } + } + if (n_no_ap_pins == inst_term->getTerm()->getPins().size()) { + logger_->error(DRT, + 91, + "{} does not have valid access points.", + inst_term->getName()); + } + } + pin_access_pattern->setBoundaryAP(true, left_access_point); + pin_access_pattern->setBoundaryAP(false, right_access_point); + + std::set owners; + if (target_obj != nullptr + && genPatterns_gc({target_obj}, objs, Commit, &owners)) { + pin_access_pattern->updateCost(); + unique_inst_patterns_[curr_unique_inst_idx].push_back( + std::move(pin_access_pattern)); + // genPatterns_print(nodes, pins); + is_valid = true; + } else { + for (int idx_1 = 0; idx_1 < (int) pins.size(); idx_1++) { + auto idx_2 = access_pattern[idx_1]; + auto& [pin, inst_term] = pins[idx_1]; + if (inst_term->hasNet()) { + if (owners.find(inst_term->getNet()) != owners.end()) { + viol_access_points.insert(std::make_pair(idx_1, idx_2)); // idx ; + } + } else { + if (owners.find(inst_term) != owners.end()) { + viol_access_points.insert(std::make_pair(idx_1, idx_2)); // idx ; + } + } + } + } + + // new access pattern + return true; +} + +void FlexPA::genPatternsPrintDebug( + std::vector>>& nodes, + const std::vector>& pins) +{ + FlexDPNode* sink_node = nodes[pins.size() + 1][0].get(); + FlexDPNode* curr_node = sink_node; + int pin_cnt = pins.size(); + + dbTransform xform; + auto& [pin, inst_term] = pins[0]; + if (inst_term) { + frInst* inst = inst_term->getInst(); + xform = inst->getNoRotationTransform(); + } + + std::cout << "failed pattern:"; + + double dbu = getDesign()->getTopBlock()->getDBUPerUU(); + while (curr_node->hasPrevNode()) { + // non-virtual node + if (pin_cnt != (int) pins.size()) { + auto& [pin, inst_term] = pins[pin_cnt]; + auto inst = inst_term->getInst(); + std::cout << " " << inst_term->getTerm()->getName(); + const int pin_access_idx = unique_insts_.getPAIndex(inst); + auto pa = pin->getPinAccess(pin_access_idx); + auto [curr_pin_idx, curr_acc_point_idx] = curr_node->getIdx(); + Point pt(pa->getAccessPoint(curr_acc_point_idx)->getPoint()); + xform.apply(pt); + std::cout << " (" << pt.x() / dbu << ", " << pt.y() / dbu << ")"; + } + + curr_node = curr_node->getPrevNode(); + pin_cnt--; + } + std::cout << std::endl; + if (pin_cnt != -1) { + logger_->error(DRT, 277, "Valid access pattern not found."); + } +} + +void FlexPA::genPatterns_print( + std::vector>>& nodes, + const std::vector>& pins) +{ + FlexDPNode* sink_node = nodes[pins.size() + 1][0].get(); + FlexDPNode* curr_node = sink_node; + int pin_cnt = pins.size(); + + std::cout << "new pattern\n"; + + while (curr_node->hasPrevNode()) { + // non-virtual node + if (pin_cnt != (int) pins.size()) { + auto& [pin, inst_term] = pins[pin_cnt]; + auto inst = inst_term->getInst(); + const int pin_access_idx = unique_insts_.getPAIndex(inst); + auto pa = pin->getPinAccess(pin_access_idx); + auto [curr_pin_idx, curr_acc_point_idx] = curr_node->getIdx(); + std::unique_ptr via = std::make_unique( + pa->getAccessPoint(curr_acc_point_idx)->getViaDef()); + Point pt(pa->getAccessPoint(curr_acc_point_idx)->getPoint()); + std::cout << " gccleanvia " << inst->getMaster()->getName() << " " + << inst_term->getTerm()->getName() << " " + << via->getViaDef()->getName() << " " << pt.x() << " " << pt.y() + << " " << inst->getOrient().getString() << "\n"; + } + + curr_node = curr_node->getPrevNode(); + pin_cnt--; + } + if (pin_cnt != -1) { + logger_->error(DRT, 278, "Valid access pattern not found."); + } +} + +// get flat edge index +int FlexPA::getFlatEdgeIdx(const int prev_idx_1, + const int prev_idx_2, + const int curr_idx_2, + const int idx_2_dim) +{ + return ((prev_idx_1 + 1) * idx_2_dim + prev_idx_2) * idx_2_dim + curr_idx_2; +} + } \ No newline at end of file diff --git a/src/drt/src/pa/FlexPA_prep.cpp b/src/drt/src/pa/FlexPA_prep.cpp index 83c9ba08415..f176c4d8ca4 100644 --- a/src/drt/src/pa/FlexPA_prep.cpp +++ b/src/drt/src/pa/FlexPA_prep.cpp @@ -1823,638 +1823,4 @@ int FlexPA::prepPatternInst(frInst* inst, return genPatterns(pin_inst_term_pairs, curr_unique_inst_idx); } -int FlexPA::genPatterns( - const std::vector>& pins, - int curr_unique_inst_idx) -{ - if (pins.empty()) { - return -1; - } - - int max_access_point_size = 0; - int pin_access_idx = unique_insts_.getPAIndex(pins[0].second->getInst()); - for (auto& [pin, inst_term] : pins) { - max_access_point_size - = std::max(max_access_point_size, - pin->getPinAccess(pin_access_idx)->getNumAccessPoints()); - } - if (max_access_point_size == 0) { - return 0; - } - - // moved for mt - std::set> inst_access_patterns; - std::set> used_access_points; - std::set> viol_access_points; - int num_valid_pattern = 0; - - num_valid_pattern += FlexPA::genPatterns_helper(pins, - inst_access_patterns, - used_access_points, - viol_access_points, - curr_unique_inst_idx, - max_access_point_size); - // try reverse order if no valid pattern - if (num_valid_pattern == 0) { - auto reversed_pins = pins; - reverse(reversed_pins.begin(), reversed_pins.end()); - - num_valid_pattern += FlexPA::genPatterns_helper(reversed_pins, - inst_access_patterns, - used_access_points, - viol_access_points, - curr_unique_inst_idx, - max_access_point_size); - } - - return num_valid_pattern; -} - -int FlexPA::genPatterns_helper( - const std::vector>& pins, - std::set>& inst_access_patterns, - std::set>& used_access_points, - std::set>& viol_access_points, - const int curr_unique_inst_idx, - const int max_access_point_size) -{ - int num_node = (pins.size() + 2) * max_access_point_size; - int num_edge = num_node * max_access_point_size; - int num_valid_pattern = 0; - - std::vector>> nodes(pins.size() + 2); - std::vector vio_edge(num_edge, -1); - - genPatternsInit(nodes, - pins, - inst_access_patterns, - used_access_points, - viol_access_points); - - for (int i = 0; i < router_cfg_->ACCESS_PATTERN_END_ITERATION_NUM; i++) { - genPatterns_reset(nodes, pins); - genPatterns_perform(nodes, - pins, - vio_edge, - used_access_points, - viol_access_points, - curr_unique_inst_idx, - max_access_point_size); - bool is_valid = false; - if (genPatterns_commit(nodes, - pins, - is_valid, - inst_access_patterns, - used_access_points, - viol_access_points, - curr_unique_inst_idx, - max_access_point_size)) { - if (is_valid) { - num_valid_pattern++; - } else { - } - } else { - break; - } - } - return num_valid_pattern; -} - -// init dp node array for valid access points -void FlexPA::genPatternsInit( - std::vector>>& nodes, - const std::vector>& pins, - std::set>& inst_access_patterns, - std::set>& used_access_points, - std::set>& viol_access_points) -{ - // clear temp storage and flag - inst_access_patterns.clear(); - used_access_points.clear(); - viol_access_points.clear(); - - // init virtual nodes - const int source_node_idx = pins.size() + 1; - nodes[source_node_idx] = std::vector>(1); - nodes[source_node_idx][0] = std::make_unique(); - FlexDPNode* source_node = nodes[source_node_idx][0].get(); - source_node->setNodeCost(0); - source_node->setIdx({pins.size() + 1, 0}); - source_node->setPathCost(0); - source_node->setAsSource(); - - const int sink_node_idx = pins.size(); - nodes[sink_node_idx] = std::vector>(1); - nodes[sink_node_idx][0] = std::make_unique(); - FlexDPNode* sink_node = nodes[sink_node_idx][0].get(); - sink_node->setNodeCost(0); - sink_node->setIdx({pins.size(), 0}); - sink_node->setAsSink(); - // init pin nodes - int pin_idx = 0; - int ap_idx = 0; - int pin_access_idx = unique_insts_.getPAIndex(pins[0].second->getInst()); - - for (auto& [pin, inst_term] : pins) { - ap_idx = 0; - auto size = pin->getPinAccess(pin_access_idx)->getAccessPoints().size(); - nodes[pin_idx] = std::vector>(size); - for (auto& ap : pin->getPinAccess(pin_access_idx)->getAccessPoints()) { - nodes[pin_idx][ap_idx] = std::make_unique(); - nodes[pin_idx][ap_idx]->setIdx({pin_idx, ap_idx}); - nodes[pin_idx][ap_idx]->setNodeCost(ap->getCost()); - ap_idx++; - } - pin_idx++; - } -} - -void FlexPA::genPatterns_reset( - std::vector>>& nodes, - const std::vector>& pins) -{ - for (auto& pin_nodes : nodes) { - for (auto& node : pin_nodes) { - node->setPathCost(std::numeric_limits::max()); - node->setPrevNode(nullptr); - } - } - - FlexDPNode* source_node = nodes[pins.size() + 1][0].get(); - source_node->setNodeCost(0); - source_node->setPathCost(0); - - FlexDPNode* sink_node = nodes[pins.size()][0].get(); - sink_node->setNodeCost(0); -} - -bool FlexPA::genPatterns_gc( - const std::set& target_objs, - const std::vector>& objs, - const PatternType pattern_type, - std::set* owners) -{ - if (objs.empty()) { - if (router_cfg_->VERBOSE > 1) { - logger_->warn(DRT, 89, "genPattern_gc objs empty."); - } - return true; - } - - FlexGCWorker design_rule_checker(getTech(), logger_, router_cfg_); - design_rule_checker.setIgnoreMinArea(); - design_rule_checker.setIgnoreLongSideEOL(); - design_rule_checker.setIgnoreCornerSpacing(); - - frCoord llx = std::numeric_limits::max(); - frCoord lly = std::numeric_limits::max(); - frCoord urx = std::numeric_limits::min(); - frCoord ury = std::numeric_limits::min(); - for (auto& [connFig, owner] : objs) { - Rect bbox = connFig->getBBox(); - llx = std::min(llx, bbox.xMin()); - lly = std::min(lly, bbox.yMin()); - urx = std::max(urx, bbox.xMax()); - ury = std::max(ury, bbox.yMax()); - } - const Rect ext_box(llx - 3000, lly - 3000, urx + 3000, ury + 3000); - design_rule_checker.setExtBox(ext_box); - design_rule_checker.setDrcBox(ext_box); - - design_rule_checker.setTargetObjs(target_objs); - if (target_objs.empty()) { - design_rule_checker.setIgnoreDB(); - } - design_rule_checker.initPA0(getDesign()); - for (auto& [connFig, owner] : objs) { - design_rule_checker.addPAObj(connFig, owner); - } - design_rule_checker.initPA1(); - design_rule_checker.main(); - design_rule_checker.end(); - - const bool no_drv = design_rule_checker.getMarkers().empty(); - if (owners) { - for (auto& marker : design_rule_checker.getMarkers()) { - for (auto& src : marker->getSrcs()) { - owners->insert(src); - } - } - } - if (graphics_) { - graphics_->setObjsAndMakers( - objs, design_rule_checker.getMarkers(), pattern_type); - } - return no_drv; -} - -void FlexPA::genPatterns_perform( - std::vector>>& nodes, - const std::vector>& pins, - std::vector& vio_edges, - const std::set>& used_access_points, - const std::set>& viol_access_points, - const int curr_unique_inst_idx, - const int max_access_point_size) -{ - const int source_node_idx = pins.size() + 1; - for (int curr_pin_idx = 0; curr_pin_idx <= (int) pins.size(); - curr_pin_idx++) { - for (int curr_acc_point_idx = 0; - curr_acc_point_idx < (int) nodes[curr_pin_idx].size(); - curr_acc_point_idx++) { - FlexDPNode* curr_node = nodes[curr_pin_idx][curr_acc_point_idx].get(); - if (curr_node->getNodeCost() == std::numeric_limits::max()) { - continue; - } - int prev_pin_idx = curr_pin_idx > 0 ? curr_pin_idx - 1 : source_node_idx; - for (int prev_acc_point_idx = 0; - prev_acc_point_idx < nodes[prev_pin_idx].size(); - prev_acc_point_idx++) { - FlexDPNode* prev_node = nodes[prev_pin_idx][prev_acc_point_idx].get(); - if (prev_node->getPathCost() == std::numeric_limits::max()) { - continue; - } - - const int edge_cost = getEdgeCost(prev_node, - curr_node, - pins, - vio_edges, - used_access_points, - viol_access_points, - curr_unique_inst_idx, - max_access_point_size); - if (curr_node->getPathCost() == std::numeric_limits::max() - || curr_node->getPathCost() - > prev_node->getPathCost() + edge_cost) { - curr_node->setPathCost(prev_node->getPathCost() + edge_cost); - curr_node->setPrevNode(prev_node); - } - } - } - } -} - -int FlexPA::getEdgeCost( - FlexDPNode* prev_node, - FlexDPNode* curr_node, - const std::vector>& pins, - std::vector& vio_edges, - const std::set>& used_access_points, - const std::set>& viol_access_points, - const int curr_unique_inst_idx, - const int max_access_point_size) -{ - int edge_cost = 0; - auto [prev_pin_idx, prev_acc_point_idx] = prev_node->getIdx(); - auto [curr_pin_idx, curr_acc_point_idx] = curr_node->getIdx(); - - if (prev_node->isSource() || curr_node->isSink()) { - return edge_cost; - } - - bool has_vio = false; - // check if the edge has been calculated - int edge_idx = getFlatEdgeIdx(prev_pin_idx, - prev_acc_point_idx, - curr_acc_point_idx, - max_access_point_size); - if (vio_edges[edge_idx] != -1) { - has_vio = (vio_edges[edge_idx] == 1); - } else { - auto curr_unique_inst = unique_insts_.getUnique(curr_unique_inst_idx); - dbTransform xform = curr_unique_inst->getNoRotationTransform(); - // check DRC - std::vector> objs; - const auto& [pin_1, inst_term_1] = pins[prev_pin_idx]; - const auto target_obj = inst_term_1->getInst(); - const int pin_access_idx = unique_insts_.getPAIndex(target_obj); - const auto pa_1 = pin_1->getPinAccess(pin_access_idx); - std::unique_ptr via1; - if (pa_1->getAccessPoint(prev_acc_point_idx)->hasAccess(frDirEnum::U)) { - via1 = std::make_unique( - pa_1->getAccessPoint(prev_acc_point_idx)->getViaDef()); - Point pt1(pa_1->getAccessPoint(prev_acc_point_idx)->getPoint()); - xform.apply(pt1); - via1->setOrigin(pt1); - if (inst_term_1->hasNet()) { - objs.emplace_back(via1.get(), inst_term_1->getNet()); - } else { - objs.emplace_back(via1.get(), inst_term_1); - } - } - - const auto& [pin_2, inst_term_2] = pins[curr_pin_idx]; - const auto pa_2 = pin_2->getPinAccess(pin_access_idx); - std::unique_ptr via2; - if (pa_2->getAccessPoint(curr_acc_point_idx)->hasAccess(frDirEnum::U)) { - via2 = std::make_unique( - pa_2->getAccessPoint(curr_acc_point_idx)->getViaDef()); - Point pt2(pa_2->getAccessPoint(curr_acc_point_idx)->getPoint()); - xform.apply(pt2); - via2->setOrigin(pt2); - if (inst_term_2->hasNet()) { - objs.emplace_back(via2.get(), inst_term_2->getNet()); - } else { - objs.emplace_back(via2.get(), inst_term_2); - } - } - - has_vio = !genPatterns_gc({target_obj}, objs, Edge); - vio_edges[edge_idx] = has_vio; - - // look back for GN14 - if (!has_vio) { - // check one more back - if (prev_node->hasPrevNode()) { - auto prev_prev_node = prev_node->getPrevNode(); - auto [prev_prev_pin_idx, prev_prev_acc_point_idx] - = prev_prev_node->getIdx(); - if (!prev_prev_node->isSource()) { - const auto& [pin_3, inst_term_3] = pins[prev_prev_pin_idx]; - auto pa_3 = pin_3->getPinAccess(pin_access_idx); - std::unique_ptr via3; - if (pa_3->getAccessPoint(prev_prev_acc_point_idx) - ->hasAccess(frDirEnum::U)) { - via3 = std::make_unique( - pa_3->getAccessPoint(prev_prev_acc_point_idx)->getViaDef()); - Point pt3( - pa_3->getAccessPoint(prev_prev_acc_point_idx)->getPoint()); - xform.apply(pt3); - via3->setOrigin(pt3); - if (inst_term_3->hasNet()) { - objs.emplace_back(via3.get(), inst_term_3->getNet()); - } else { - objs.emplace_back(via3.get(), inst_term_3); - } - } - - has_vio = !genPatterns_gc({target_obj}, objs, Edge); - } - } - } - } - - if (!has_vio) { - if ((prev_pin_idx == 0 - && used_access_points.find( - std::make_pair(prev_pin_idx, prev_acc_point_idx)) - != used_access_points.end()) - || (curr_pin_idx == (int) pins.size() - 1 - && used_access_points.find( - std::make_pair(curr_pin_idx, curr_acc_point_idx)) - != used_access_points.end())) { - edge_cost = 100; - } else if (viol_access_points.find( - std::make_pair(prev_pin_idx, prev_acc_point_idx)) - != viol_access_points.end() - || viol_access_points.find( - std::make_pair(curr_pin_idx, curr_acc_point_idx)) - != viol_access_points.end()) { - edge_cost = 1000; - } else { - const int prev_node_cost = prev_node->getNodeCost(); - const int curr_node_cost = curr_node->getNodeCost(); - edge_cost = (prev_node_cost + curr_node_cost) / 2; - } - } else { - edge_cost = 1000 /*violation cost*/; - } - - return edge_cost; -} - -std::vector FlexPA::extractAccessPatternFromNodes( - const std::vector>>& nodes, - const std::vector>& pins, - std::set>& used_access_points) -{ - std::vector access_pattern(pins.size(), -1); - - const FlexDPNode* source_node = nodes[pins.size() + 1][0].get(); - const FlexDPNode* sink_node = nodes[pins.size()][0].get(); - - FlexDPNode* curr_node = sink_node->getPrevNode(); - - while (curr_node != source_node) { - if (!curr_node) { - logger_->error(DRT, 90, "Valid access pattern not found."); - } - - auto [curr_pin_idx, curr_acc_point_idx] = curr_node->getIdx(); - access_pattern[curr_pin_idx] = curr_acc_point_idx; - used_access_points.insert({curr_pin_idx, curr_acc_point_idx}); - - curr_node = curr_node->getPrevNode(); - } - return access_pattern; -} - -bool FlexPA::genPatterns_commit( - const std::vector>>& nodes, - const std::vector>& pins, - bool& is_valid, - std::set>& inst_access_patterns, - std::set>& used_access_points, - std::set>& viol_access_points, - const int curr_unique_inst_idx, - const int max_access_point_size) -{ - std::vector access_pattern - = extractAccessPatternFromNodes(nodes, pins, used_access_points); - // not a new access pattern - if (inst_access_patterns.find(access_pattern) != inst_access_patterns.end()) { - return false; - } - - inst_access_patterns.insert(access_pattern); - // create new access pattern and push to uniqueInstances - auto pin_access_pattern = std::make_unique(); - std::map pin_to_access_point; - // check DRC for the whole pattern - std::vector> objs; - std::vector> temp_vias; - frInst* target_obj = nullptr; - for (int pin_idx = 0; pin_idx < (int) pins.size(); pin_idx++) { - auto acc_point_idx = access_pattern[pin_idx]; - auto& [pin, inst_term] = pins[pin_idx]; - auto inst = inst_term->getInst(); - target_obj = inst; - const int pin_access_idx = unique_insts_.getPAIndex(inst); - const auto pa = pin->getPinAccess(pin_access_idx); - const auto access_point = pa->getAccessPoint(acc_point_idx); - pin_to_access_point[pin] = access_point; - - // add objs - std::unique_ptr via; - if (access_point->hasAccess(frDirEnum::U)) { - via = std::make_unique(access_point->getViaDef()); - auto rvia = via.get(); - temp_vias.push_back(std::move(via)); - - dbTransform xform = inst->getNoRotationTransform(); - Point pt(access_point->getPoint()); - xform.apply(pt); - rvia->setOrigin(pt); - if (inst_term->hasNet()) { - objs.emplace_back(rvia, inst_term->getNet()); - } else { - objs.emplace_back(rvia, inst_term); - } - } - } - - frAccessPoint* left_access_point = nullptr; - frAccessPoint* right_access_point = nullptr; - frCoord left_pt = std::numeric_limits::max(); - frCoord right_pt = std::numeric_limits::min(); - - const auto& [pin, inst_term] = pins[0]; - const auto inst = inst_term->getInst(); - for (auto& inst_term : inst->getInstTerms()) { - if (isSkipInstTerm(inst_term.get())) { - continue; - } - uint64_t n_no_ap_pins = 0; - for (auto& pin : inst_term->getTerm()->getPins()) { - if (pin_to_access_point.find(pin.get()) == pin_to_access_point.end()) { - n_no_ap_pins++; - pin_access_pattern->addAccessPoint(nullptr); - } else { - const auto& ap = pin_to_access_point[pin.get()]; - const Point tmpPt = ap->getPoint(); - if (tmpPt.x() < left_pt) { - left_access_point = ap; - left_pt = tmpPt.x(); - } - if (tmpPt.x() > right_pt) { - right_access_point = ap; - right_pt = tmpPt.x(); - } - pin_access_pattern->addAccessPoint(ap); - } - } - if (n_no_ap_pins == inst_term->getTerm()->getPins().size()) { - logger_->error(DRT, - 91, - "{} does not have valid access points.", - inst_term->getName()); - } - } - pin_access_pattern->setBoundaryAP(true, left_access_point); - pin_access_pattern->setBoundaryAP(false, right_access_point); - - std::set owners; - if (target_obj != nullptr - && genPatterns_gc({target_obj}, objs, Commit, &owners)) { - pin_access_pattern->updateCost(); - unique_inst_patterns_[curr_unique_inst_idx].push_back( - std::move(pin_access_pattern)); - // genPatterns_print(nodes, pins); - is_valid = true; - } else { - for (int idx_1 = 0; idx_1 < (int) pins.size(); idx_1++) { - auto idx_2 = access_pattern[idx_1]; - auto& [pin, inst_term] = pins[idx_1]; - if (inst_term->hasNet()) { - if (owners.find(inst_term->getNet()) != owners.end()) { - viol_access_points.insert(std::make_pair(idx_1, idx_2)); // idx ; - } - } else { - if (owners.find(inst_term) != owners.end()) { - viol_access_points.insert(std::make_pair(idx_1, idx_2)); // idx ; - } - } - } - } - - // new access pattern - return true; -} - -void FlexPA::genPatternsPrintDebug( - std::vector>>& nodes, - const std::vector>& pins) -{ - FlexDPNode* sink_node = nodes[pins.size() + 1][0].get(); - FlexDPNode* curr_node = sink_node; - int pin_cnt = pins.size(); - - dbTransform xform; - auto& [pin, inst_term] = pins[0]; - if (inst_term) { - frInst* inst = inst_term->getInst(); - xform = inst->getNoRotationTransform(); - } - - std::cout << "failed pattern:"; - - double dbu = getDesign()->getTopBlock()->getDBUPerUU(); - while (curr_node->hasPrevNode()) { - // non-virtual node - if (pin_cnt != (int) pins.size()) { - auto& [pin, inst_term] = pins[pin_cnt]; - auto inst = inst_term->getInst(); - std::cout << " " << inst_term->getTerm()->getName(); - const int pin_access_idx = unique_insts_.getPAIndex(inst); - auto pa = pin->getPinAccess(pin_access_idx); - auto [curr_pin_idx, curr_acc_point_idx] = curr_node->getIdx(); - Point pt(pa->getAccessPoint(curr_acc_point_idx)->getPoint()); - xform.apply(pt); - std::cout << " (" << pt.x() / dbu << ", " << pt.y() / dbu << ")"; - } - - curr_node = curr_node->getPrevNode(); - pin_cnt--; - } - std::cout << std::endl; - if (pin_cnt != -1) { - logger_->error(DRT, 277, "Valid access pattern not found."); - } -} - -void FlexPA::genPatterns_print( - std::vector>>& nodes, - const std::vector>& pins) -{ - FlexDPNode* sink_node = nodes[pins.size() + 1][0].get(); - FlexDPNode* curr_node = sink_node; - int pin_cnt = pins.size(); - - std::cout << "new pattern\n"; - - while (curr_node->hasPrevNode()) { - // non-virtual node - if (pin_cnt != (int) pins.size()) { - auto& [pin, inst_term] = pins[pin_cnt]; - auto inst = inst_term->getInst(); - const int pin_access_idx = unique_insts_.getPAIndex(inst); - auto pa = pin->getPinAccess(pin_access_idx); - auto [curr_pin_idx, curr_acc_point_idx] = curr_node->getIdx(); - std::unique_ptr via = std::make_unique( - pa->getAccessPoint(curr_acc_point_idx)->getViaDef()); - Point pt(pa->getAccessPoint(curr_acc_point_idx)->getPoint()); - std::cout << " gccleanvia " << inst->getMaster()->getName() << " " - << inst_term->getTerm()->getName() << " " - << via->getViaDef()->getName() << " " << pt.x() << " " << pt.y() - << " " << inst->getOrient().getString() << "\n"; - } - - curr_node = curr_node->getPrevNode(); - pin_cnt--; - } - if (pin_cnt != -1) { - logger_->error(DRT, 278, "Valid access pattern not found."); - } -} - -// get flat edge index -int FlexPA::getFlatEdgeIdx(const int prev_idx_1, - const int prev_idx_2, - const int curr_idx_2, - const int idx_2_dim) -{ - return ((prev_idx_1 + 1) * idx_2_dim + prev_idx_2) * idx_2_dim + curr_idx_2; -} - } // namespace drt From fa7039c3ba816e8341ae53043863d62dcdc84c12 Mon Sep 17 00:00:00 2001 From: bernardo Date: Sat, 14 Dec 2024 23:36:56 +0000 Subject: [PATCH 54/98] move genAPOnTrack Signed-off-by: bernardo move genCentered Signed-off-by: bernardo move genEnclosed Signed-off-by: bernardo move genAPCosted Signed-off-by: bernardo --- src/drt/src/pa/FlexPA_acc_point.cpp | 168 ++++++++++++++++++++++++++++ src/drt/src/pa/FlexPA_prep.cpp | 168 ---------------------------- 2 files changed, 168 insertions(+), 168 deletions(-) diff --git a/src/drt/src/pa/FlexPA_acc_point.cpp b/src/drt/src/pa/FlexPA_acc_point.cpp index b822826978d..e652c58204d 100644 --- a/src/drt/src/pa/FlexPA_acc_point.cpp +++ b/src/drt/src/pa/FlexPA_acc_point.cpp @@ -48,4 +48,172 @@ namespace drt { using utl::ThreadException; +/** + * + * @details This follows the Tao of PAO paper cost structure. + * On track and half track are the preffered access points, + * this function is responsible for generating them. + * It iterates over every track coord in the range [low, high] + * and inserts one of its coordinates on the coords map. + * if use_nearby_grid is true it changes the access point cost to it. + * + * TODO: + * This function doesn't seem to be getting the best access point. + * it iterates through every track contained between low and high + * and takes the first one (closest to low) not the best one (lowest cost). + * note that std::map.insert() will not override and entry. + * it should prioritize OnGrid access points + */ +void FlexPA::genAPOnTrack( + std::map& coords, + const std::map& track_coords, + const frCoord low, + const frCoord high, + const bool use_nearby_grid) +{ + for (auto it = track_coords.lower_bound(low); it != track_coords.end(); + it++) { + auto& [coord, cost] = *it; + if (coord > high) { + break; + } + if (use_nearby_grid) { + coords.insert({coord, frAccessPointEnum::NearbyGrid}); + } else { + coords.insert(*it); + } + } +} + +// will not generate center for wider edge +/** + * @details This follows the Tao of PAO paper cost structure. + * First it iterates through the range [low, high] to check if there are + * at least 3 possible OnTrack access points as those take priority. + * If false it created and access points in the middle point between [low, high] + */ + +void FlexPA::genAPCentered(std::map& coords, + const frLayerNum layer_num, + const frCoord low, + const frCoord high) +{ + // if touching two tracks, then no center?? + int candidates_on_grid = 0; + for (auto it = coords.lower_bound(low); it != coords.end(); it++) { + auto& [coordinate, cost] = *it; + if (coordinate > high) { + break; + } + if (cost == frAccessPointEnum::OnGrid) { + candidates_on_grid++; + } + } + if (candidates_on_grid >= 3) { + return; + } + + // If there are less than 3 coords OnGrid will create a Centered Access Point + frCoord manu_grid = getDesign()->getTech()->getManufacturingGrid(); + frCoord coord = (low + high) / 2 / manu_grid * manu_grid; + + if (coords.find(coord) == coords.end()) { + coords.insert(std::make_pair(coord, frAccessPointEnum::Center)); + } else { + coords[coord] = std::min(coords[coord], frAccessPointEnum::Center); + } +} + +/** + * @details This follows the Tao of PAO paper cost structure. + * Enclosed Boundary APs satisfy via-in-pin requirement. + * This is the worst access point adressed in the paper + */ + +void FlexPA::genAPEnclosedBoundary(std::map& coords, + const gtl::rectangle_data& rect, + const frLayerNum layer_num, + const bool is_curr_layer_horz) +{ + const auto rect_width = gtl::delta(rect, gtl::HORIZONTAL); + const auto rect_height = gtl::delta(rect, gtl::VERTICAL); + const int max_num_via_trial = 2; + if (layer_num + 1 > getDesign()->getTech()->getTopLayerNum()) { + return; + } + // hardcode first two single vias + std::vector via_defs; + int cnt = 0; + for (auto& [tup, via] : layer_num_to_via_defs_[layer_num + 1][1]) { + via_defs.push_back(via); + cnt++; + if (cnt >= max_num_via_trial) { + break; + } + } + for (auto& via_def : via_defs) { + frVia via(via_def); + const Rect box = via.getLayer1BBox(); + const auto via_width = box.dx(); + const auto via_height = box.dy(); + if (via_width > rect_width || via_height > rect_height) { + continue; + } + const int coord_top = is_curr_layer_horz ? gtl::yh(rect) - box.yMax() + : gtl::xh(rect) - box.xMax(); + const int coord_low = is_curr_layer_horz ? gtl::yl(rect) - box.yMin() + : gtl::xl(rect) - box.xMin(); + for (const int coord : {coord_top, coord_low}) { + if (coords.find(coord) == coords.end()) { + coords.insert(std::make_pair(coord, frAccessPointEnum::EncOpt)); + } else { + coords[coord] = std::min(coords[coord], frAccessPointEnum::EncOpt); + } + } + } +} + +void FlexPA::genAPCosted( + const frAccessPointEnum cost, + std::map& coords, + const std::map& track_coords, + const frLayerNum base_layer_num, + const frLayerNum layer_num, + const gtl::rectangle_data& rect, + const bool is_curr_layer_horz, + const int offset) +{ + auto layer = getDesign()->getTech()->getLayer(layer_num); + const auto min_width_layer = layer->getMinWidth(); + const int rect_min = is_curr_layer_horz ? gtl::yl(rect) : gtl::xl(rect); + const int rect_max = is_curr_layer_horz ? gtl::yh(rect) : gtl::xh(rect); + + switch (cost) { + case (frAccessPointEnum::OnGrid): + genAPOnTrack(coords, track_coords, rect_min + offset, rect_max - offset); + break; + + // frAccessPointEnum::Halfgrid not defined + + case (frAccessPointEnum::Center): + genAPCentered( + coords, base_layer_num, rect_min + offset, rect_max - offset); + break; + + case (frAccessPointEnum::EncOpt): + genAPEnclosedBoundary(coords, rect, base_layer_num, is_curr_layer_horz); + break; + + case (frAccessPointEnum::NearbyGrid): + genAPOnTrack( + coords, track_coords, rect_min - min_width_layer, rect_min, true); + genAPOnTrack( + coords, track_coords, rect_max, rect_max + min_width_layer, true); + break; + + default: + logger_->error(DRT, 257, "Invalid frAccessPointEnum type"); + } +} + } \ No newline at end of file diff --git a/src/drt/src/pa/FlexPA_prep.cpp b/src/drt/src/pa/FlexPA_prep.cpp index f176c4d8ca4..e2de2fe3ec1 100644 --- a/src/drt/src/pa/FlexPA_prep.cpp +++ b/src/drt/src/pa/FlexPA_prep.cpp @@ -132,174 +132,6 @@ FlexPA::mergePinShapes(T* pin, frInstTerm* inst_term, const bool is_shrink) return pin_shapes; } -/** - * - * @details This follows the Tao of PAO paper cost structure. - * On track and half track are the preffered access points, - * this function is responsible for generating them. - * It iterates over every track coord in the range [low, high] - * and inserts one of its coordinates on the coords map. - * if use_nearby_grid is true it changes the access point cost to it. - * - * TODO: - * This function doesn't seem to be getting the best access point. - * it iterates through every track contained between low and high - * and takes the first one (closest to low) not the best one (lowest cost). - * note that std::map.insert() will not override and entry. - * it should prioritize OnGrid access points - */ -void FlexPA::genAPOnTrack( - std::map& coords, - const std::map& track_coords, - const frCoord low, - const frCoord high, - const bool use_nearby_grid) -{ - for (auto it = track_coords.lower_bound(low); it != track_coords.end(); - it++) { - auto& [coord, cost] = *it; - if (coord > high) { - break; - } - if (use_nearby_grid) { - coords.insert({coord, frAccessPointEnum::NearbyGrid}); - } else { - coords.insert(*it); - } - } -} - -// will not generate center for wider edge -/** - * @details This follows the Tao of PAO paper cost structure. - * First it iterates through the range [low, high] to check if there are - * at least 3 possible OnTrack access points as those take priority. - * If false it created and access points in the middle point between [low, high] - */ - -void FlexPA::genAPCentered(std::map& coords, - const frLayerNum layer_num, - const frCoord low, - const frCoord high) -{ - // if touching two tracks, then no center?? - int candidates_on_grid = 0; - for (auto it = coords.lower_bound(low); it != coords.end(); it++) { - auto& [coordinate, cost] = *it; - if (coordinate > high) { - break; - } - if (cost == frAccessPointEnum::OnGrid) { - candidates_on_grid++; - } - } - if (candidates_on_grid >= 3) { - return; - } - - // If there are less than 3 coords OnGrid will create a Centered Access Point - frCoord manu_grid = getDesign()->getTech()->getManufacturingGrid(); - frCoord coord = (low + high) / 2 / manu_grid * manu_grid; - - if (coords.find(coord) == coords.end()) { - coords.insert(std::make_pair(coord, frAccessPointEnum::Center)); - } else { - coords[coord] = std::min(coords[coord], frAccessPointEnum::Center); - } -} - -/** - * @details This follows the Tao of PAO paper cost structure. - * Enclosed Boundary APs satisfy via-in-pin requirement. - * This is the worst access point adressed in the paper - */ - -void FlexPA::genAPEnclosedBoundary(std::map& coords, - const gtl::rectangle_data& rect, - const frLayerNum layer_num, - const bool is_curr_layer_horz) -{ - const auto rect_width = gtl::delta(rect, gtl::HORIZONTAL); - const auto rect_height = gtl::delta(rect, gtl::VERTICAL); - const int max_num_via_trial = 2; - if (layer_num + 1 > getDesign()->getTech()->getTopLayerNum()) { - return; - } - // hardcode first two single vias - std::vector via_defs; - int cnt = 0; - for (auto& [tup, via] : layer_num_to_via_defs_[layer_num + 1][1]) { - via_defs.push_back(via); - cnt++; - if (cnt >= max_num_via_trial) { - break; - } - } - for (auto& via_def : via_defs) { - frVia via(via_def); - const Rect box = via.getLayer1BBox(); - const auto via_width = box.dx(); - const auto via_height = box.dy(); - if (via_width > rect_width || via_height > rect_height) { - continue; - } - const int coord_top = is_curr_layer_horz ? gtl::yh(rect) - box.yMax() - : gtl::xh(rect) - box.xMax(); - const int coord_low = is_curr_layer_horz ? gtl::yl(rect) - box.yMin() - : gtl::xl(rect) - box.xMin(); - for (const int coord : {coord_top, coord_low}) { - if (coords.find(coord) == coords.end()) { - coords.insert(std::make_pair(coord, frAccessPointEnum::EncOpt)); - } else { - coords[coord] = std::min(coords[coord], frAccessPointEnum::EncOpt); - } - } - } -} - -void FlexPA::genAPCosted( - const frAccessPointEnum cost, - std::map& coords, - const std::map& track_coords, - const frLayerNum base_layer_num, - const frLayerNum layer_num, - const gtl::rectangle_data& rect, - const bool is_curr_layer_horz, - const int offset) -{ - auto layer = getDesign()->getTech()->getLayer(layer_num); - const auto min_width_layer = layer->getMinWidth(); - const int rect_min = is_curr_layer_horz ? gtl::yl(rect) : gtl::xl(rect); - const int rect_max = is_curr_layer_horz ? gtl::yh(rect) : gtl::xh(rect); - - switch (cost) { - case (frAccessPointEnum::OnGrid): - genAPOnTrack(coords, track_coords, rect_min + offset, rect_max - offset); - break; - - // frAccessPointEnum::Halfgrid not defined - - case (frAccessPointEnum::Center): - genAPCentered( - coords, base_layer_num, rect_min + offset, rect_max - offset); - break; - - case (frAccessPointEnum::EncOpt): - genAPEnclosedBoundary(coords, rect, base_layer_num, is_curr_layer_horz); - break; - - case (frAccessPointEnum::NearbyGrid): - genAPOnTrack( - coords, track_coords, rect_min - min_width_layer, rect_min, true); - genAPOnTrack( - coords, track_coords, rect_max, rect_max + min_width_layer, true); - break; - - default: - logger_->error(DRT, 257, "Invalid frAccessPointEnum type"); - } -} - // Responsible for checking if an AP is valid and configuring it void FlexPA::gen_createAccessPoint( std::vector>& aps, From 9ae2588a6b0b90ef845f30b5f1bf0adcabff226d Mon Sep 17 00:00:00 2001 From: bernardo Date: Sat, 14 Dec 2024 23:40:19 +0000 Subject: [PATCH 55/98] move gen_createAccessPoint Signed-off-by: bernardo move gen_initializeAccessPoint Signed-off-by: bernardo move genAPsFromRect Signed-off-by: bernardo move genAPsFromLayerShapes Signed-off-by: bernardo move genAPsFromPinShapes Signed-off-by: bernardo move genEndPoint Signed-off-by: bernardo move isPointOutsideShapes Signed-off-by: bernardo move check_addPlanarAccess Signed-off-by: bernardo move isPlanarViolationFree Signed-off-by: bernardo move getViasFromMetalWidthMap Signed-off-by: bernardo move check_addViaAccess Signed-off-by: bernardo move checkViaAccess Signed-off-by: bernardo move checkDirectionalViaAccess Signed-off-by: bernardo move isViaViolationFree Signed-off-by: bernardo move check_addViaAccess Signed-off-by: bernardo --- src/drt/src/pa/FlexPA_acc_point.cpp | 860 ++++++++++++++++++++++++++++ src/drt/src/pa/FlexPA_prep.cpp | 860 ---------------------------- 2 files changed, 860 insertions(+), 860 deletions(-) diff --git a/src/drt/src/pa/FlexPA_acc_point.cpp b/src/drt/src/pa/FlexPA_acc_point.cpp index e652c58204d..cc12c86f72b 100644 --- a/src/drt/src/pa/FlexPA_acc_point.cpp +++ b/src/drt/src/pa/FlexPA_acc_point.cpp @@ -216,4 +216,864 @@ void FlexPA::genAPCosted( } } +// Responsible for checking if an AP is valid and configuring it +void FlexPA::gen_createAccessPoint( + std::vector>& aps, + std::set>& apset, + const gtl::rectangle_data& maxrect, + const frCoord x, + const frCoord y, + const frLayerNum layer_num, + const bool allow_planar, + const bool allow_via, + const frAccessPointEnum low_cost, + const frAccessPointEnum high_cost) +{ + gtl::point_data pt(x, y); + if (!gtl::contains(maxrect, pt) && low_cost != frAccessPointEnum::NearbyGrid + && high_cost != frAccessPointEnum::NearbyGrid) { + return; + } + Point fpt(x, y); + if (apset.find(std::make_pair(fpt, layer_num)) != apset.end()) { + return; + } + auto ap = std::make_unique(fpt, layer_num); + + ap->setMultipleAccesses(frDirEnumPlanar, allow_planar); + + if (allow_planar) { + const auto lower_layer = getDesign()->getTech()->getLayer(layer_num); + // rectonly forbid wrongway planar access + // rightway on grid only forbid off track rightway planar access + // horz layer + if (lower_layer->getDir() == dbTechLayerDir::HORIZONTAL) { + if (lower_layer->isUnidirectional()) { + ap->setMultipleAccesses(frDirEnumVert, false); + } + if (lower_layer->getLef58RightWayOnGridOnlyConstraint() + && low_cost != frAccessPointEnum::OnGrid) { + ap->setMultipleAccesses(frDirEnumHorz, false); + } + } + // vert layer + if (lower_layer->getDir() == dbTechLayerDir::VERTICAL) { + if (lower_layer->isUnidirectional()) { + ap->setMultipleAccesses(frDirEnumHorz, false); + } + if (lower_layer->getLef58RightWayOnGridOnlyConstraint() + && low_cost != frAccessPointEnum::OnGrid) { + ap->setMultipleAccesses(frDirEnumVert, false); + } + } + } + ap->setAccess(frDirEnum::D, false); + ap->setAccess(frDirEnum::U, allow_via); + + ap->setAllowVia(allow_via); + ap->setType((frAccessPointEnum) low_cost, true); + ap->setType((frAccessPointEnum) high_cost, false); + if ((low_cost == frAccessPointEnum::NearbyGrid + || high_cost == frAccessPointEnum::NearbyGrid)) { + Point end; + const int half_width + = design_->getTech()->getLayer(ap->getLayerNum())->getMinWidth() / 2; + if (fpt.x() < gtl::xl(maxrect) + half_width) { + end.setX(gtl::xl(maxrect) + half_width); + } else if (fpt.x() > gtl::xh(maxrect) - half_width) { + end.setX(gtl::xh(maxrect) - half_width); + } else { + end.setX(fpt.x()); + } + if (fpt.y() < gtl::yl(maxrect) + half_width) { + end.setY(gtl::yl(maxrect) + half_width); + } else if (fpt.y() > gtl::yh(maxrect) - half_width) { + end.setY(gtl::yh(maxrect) - half_width); + } else { + end.setY(fpt.y()); + } + + Point e = fpt; + if (fpt.x() != end.x()) { + e.setX(end.x()); + } else if (fpt.y() != end.y()) { + e.setY(end.y()); + } + if (!(e == fpt)) { + frPathSeg ps; + ps.setPoints_safe(fpt, e); + if (ps.getBeginPoint() == end) { + ps.setBeginStyle(frEndStyle(frcTruncateEndStyle)); + } else if (ps.getEndPoint() == end) { + ps.setEndStyle(frEndStyle(frcTruncateEndStyle)); + } + ap->addPathSeg(ps); + if (!(e == end)) { + fpt = e; + ps.setPoints_safe(fpt, end); + if (ps.getBeginPoint() == end) { + ps.setBeginStyle(frEndStyle(frcTruncateEndStyle)); + } else { + ps.setEndStyle(frEndStyle(frcTruncateEndStyle)); + } + ap->addPathSeg(ps); + } + } + } + aps.push_back(std::move(ap)); + apset.insert(std::make_pair(fpt, layer_num)); +} + +void FlexPA::gen_initializeAccessPoints( + std::vector>& aps, + std::set>& apset, + const gtl::rectangle_data& rect, + const frLayerNum layer_num, + const bool allow_planar, + const bool allow_via, + const bool is_layer1_horz, + const std::map& x_coords, + const std::map& y_coords, + const frAccessPointEnum lower_type, + const frAccessPointEnum upper_type) +{ + // build points; + for (auto& [x_coord, cost_x] : x_coords) { + for (auto& [y_coord, cost_y] : y_coords) { + // lower full/half/center + auto& low_cost = is_layer1_horz ? cost_y : cost_x; + auto& high_cost = (!is_layer1_horz) ? cost_y : cost_x; + if (low_cost == lower_type && high_cost == upper_type) { + gen_createAccessPoint(aps, + apset, + rect, + x_coord, + y_coord, + layer_num, + allow_planar, + allow_via, + low_cost, + high_cost); + } + } + } +} + +/** + * @details Generates all necessary access points from a rectangle shape + * In this case a rectangle is one of the pin shapes of the pin + */ +void FlexPA::genAPsFromRect(std::vector>& aps, + std::set>& apset, + const gtl::rectangle_data& rect, + const frLayerNum layer_num, + const bool allow_planar, + const bool allow_via, + frAccessPointEnum lower_type, + const frAccessPointEnum upper_type, + const bool is_macro_cell_pin) +{ + auto layer = getDesign()->getTech()->getLayer(layer_num); + const auto min_width_layer1 = layer->getMinWidth(); + if (std::min(gtl::delta(rect, gtl::HORIZONTAL), + gtl::delta(rect, gtl::VERTICAL)) + < min_width_layer1) { + return; + } + frLayerNum second_layer_num = 0; + if (layer_num + 2 <= getDesign()->getTech()->getTopLayerNum()) { + second_layer_num = layer_num + 2; + } else if (layer_num - 2 >= getDesign()->getTech()->getBottomLayerNum()) { + second_layer_num = layer_num - 2; + } else { + logger_->error(DRT, 68, "genAPsFromRect cannot find second_layer_num."); + } + auto& layer1_track_coords = track_coords_[layer_num]; + auto& layer2_track_coords = track_coords_[second_layer_num]; + const bool is_layer1_horz = (layer->getDir() == dbTechLayerDir::HORIZONTAL); + + std::map x_coords; + std::map y_coords; + int hwidth = layer->getWidth() / 2; + bool use_center_line = false; + if (is_macro_cell_pin && !layer->getLef58RightWayOnGridOnlyConstraint()) { + auto rect_dir = gtl::guess_orientation(rect); + if ((rect_dir == gtl::HORIZONTAL && is_layer1_horz) + || (rect_dir == gtl::VERTICAL && !is_layer1_horz)) { + auto layer_width = layer->getWidth(); + if ((rect_dir == gtl::HORIZONTAL + && gtl::delta(rect, gtl::VERTICAL) < 2 * layer_width) + || (rect_dir == gtl::VERTICAL + && gtl::delta(rect, gtl::HORIZONTAL) < 2 * layer_width)) { + use_center_line = true; + } + } + } + + // gen all full/half grid coords + /** offset used to only be used after an if (!is_macro_cell_pin || + * !use_center_line), so this logic was combined with offset is_macro_cell_pin + * ? hwidth : 0; + */ + const int offset = is_macro_cell_pin && !use_center_line ? hwidth : 0; + const int layer1_rect_min = is_layer1_horz ? gtl::yl(rect) : gtl::xl(rect); + const int layer1_rect_max = is_layer1_horz ? gtl::yh(rect) : gtl::xh(rect); + auto& layer1_coords = is_layer1_horz ? y_coords : x_coords; + auto& layer2_coords = is_layer1_horz ? x_coords : y_coords; + + const frAccessPointEnum frDirEnums[] = {frAccessPointEnum::OnGrid, + frAccessPointEnum::Center, + frAccessPointEnum::EncOpt, + frAccessPointEnum::NearbyGrid}; + + for (const auto cost : frDirEnums) { + if (upper_type >= cost) { + genAPCosted(cost, + layer2_coords, + layer2_track_coords, + layer_num, + second_layer_num, + rect, + !is_layer1_horz, + offset); + } + } + if (!(is_macro_cell_pin && use_center_line)) { + for (const auto cost : frDirEnums) { + if (lower_type >= cost) { + genAPCosted(cost, + layer1_coords, + layer1_track_coords, + layer_num, + layer_num, + rect, + is_layer1_horz); + } + } + } else { + genAPCentered(layer1_coords, layer_num, layer1_rect_min, layer1_rect_max); + for (auto& [layer1_coord, cost] : layer1_coords) { + layer1_coords[layer1_coord] = frAccessPointEnum::OnGrid; + } + } + + if (is_macro_cell_pin && use_center_line && is_layer1_horz) { + lower_type = frAccessPointEnum::OnGrid; + } + + gen_initializeAccessPoints(aps, + apset, + rect, + layer_num, + allow_planar, + allow_via, + is_layer1_horz, + x_coords, + y_coords, + lower_type, + upper_type); +} + +void FlexPA::genAPsFromLayerShapes( + std::vector>& aps, + std::set>& apset, + frInstTerm* inst_term, + const gtl::polygon_90_set_data& layer_shapes, + const frLayerNum layer_num, + bool allow_via, + const frAccessPointEnum lower_type, + const frAccessPointEnum upper_type) +{ + if (getDesign()->getTech()->getLayer(layer_num)->getType() + != dbTechLayerType::ROUTING) { + return; + } + bool allow_planar = true; + bool is_macro_cell_pin = false; + if (inst_term) { + if (isStdCell(inst_term->getInst())) { + if ((layer_num >= router_cfg_->VIAINPIN_BOTTOMLAYERNUM + && layer_num <= router_cfg_->VIAINPIN_TOPLAYERNUM) + || layer_num <= router_cfg_->VIA_ACCESS_LAYERNUM) { + allow_planar = false; + } + } + is_macro_cell_pin = isMacroCell(inst_term->getInst()); + } else { + // IO term is treated as the MacroCellPin as the top block + is_macro_cell_pin = true; + allow_planar = true; + allow_via = false; + } + // lower layer is current layer + // rightway on grid only forbid off track up via access on upper layer + const auto upper_layer + = (layer_num + 2 <= getDesign()->getTech()->getTopLayerNum()) + ? getDesign()->getTech()->getLayer(layer_num + 2) + : nullptr; + if (!is_macro_cell_pin && upper_layer + && upper_layer->getLef58RightWayOnGridOnlyConstraint() + && upper_type != frAccessPointEnum::OnGrid) { + return; + } + std::vector> maxrects; + gtl::get_max_rectangles(maxrects, layer_shapes); + for (auto& bbox_rect : maxrects) { + genAPsFromRect(aps, + apset, + bbox_rect, + layer_num, + allow_planar, + allow_via, + lower_type, + upper_type, + is_macro_cell_pin); + } +} + +// filter off-grid coordinate +// lower on-grid 0, upper on-grid 0 = 0 +// lower 1/2 1, upper on-grid 0 = 1 +// lower center 2, upper on-grid 0 = 2 +// lower center 2, upper center 2 = 4 + +template +void FlexPA::genAPsFromPinShapes( + std::vector>& aps, + std::set>& apset, + T* pin, + frInstTerm* inst_term, + const std::vector>& pin_shapes, + const frAccessPointEnum lower_type, + const frAccessPointEnum upper_type) +{ + // only VIA_ACCESS_LAYERNUM layer can have via access + const bool allow_via = true; + frLayerNum layer_num = (int) pin_shapes.size() - 1; + for (auto it = pin_shapes.rbegin(); it != pin_shapes.rend(); it++) { + if (!it->empty() + && getDesign()->getTech()->getLayer(layer_num)->getType() + == dbTechLayerType::ROUTING) { + genAPsFromLayerShapes(aps, + apset, + inst_term, + *it, + layer_num, + allow_via, + lower_type, + upper_type); + } + layer_num--; + } +} + +Point FlexPA::genEndPoint( + const std::vector>& layer_polys, + const Point& begin_point, + const frLayerNum layer_num, + const frDirEnum dir, + const bool is_block) +{ + const int step_size_multiplier = 3; + frCoord x = begin_point.x(); + frCoord y = begin_point.y(); + const frCoord width = getDesign()->getTech()->getLayer(layer_num)->getWidth(); + const frCoord step_size = step_size_multiplier * width; + const frCoord pitch = getDesign()->getTech()->getLayer(layer_num)->getPitch(); + gtl::rectangle_data rect; + if (is_block) { + gtl::extents(rect, layer_polys[0]); + if (layer_polys.size() > 1) { + logger_->warn(DRT, 6000, "Macro pin has more than 1 polygon"); + } + } + switch (dir) { + case (frDirEnum::W): + if (is_block) { + x = gtl::xl(rect) - pitch; + } else { + x -= step_size; + } + break; + case (frDirEnum::E): + if (is_block) { + x = gtl::xh(rect) + pitch; + } else { + x += step_size; + } + break; + case (frDirEnum::S): + if (is_block) { + y = gtl::yl(rect) - pitch; + } else { + y -= step_size; + } + break; + case (frDirEnum::N): + if (is_block) { + y = gtl::yh(rect) + pitch; + } else { + y += step_size; + } + break; + default: + logger_->error(DRT, 70, "Unexpected direction in getPlanarEP."); + } + return {x, y}; +} + +bool FlexPA::isPointOutsideShapes( + const Point& point, + const std::vector>& layer_polys) +{ + const gtl::point_data pt(point.getX(), point.getY()); + for (auto& layer_poly : layer_polys) { + if (gtl::contains(layer_poly, pt)) { + return false; + break; + } + } + return true; +} + +template +void FlexPA::check_addPlanarAccess( + frAccessPoint* ap, + const std::vector>& layer_polys, + frDirEnum dir, + T* pin, + frInstTerm* inst_term) +{ + const Point begin_point = ap->getPoint(); + // skip viaonly access + if (!ap->hasAccess(dir)) { + return; + } + const bool is_block + = inst_term + && inst_term->getInst()->getMaster()->getMasterType().isBlock(); + const Point end_point + = genEndPoint(layer_polys, begin_point, ap->getLayerNum(), dir, is_block); + const bool is_outside = isPointOutsideShapes(end_point, layer_polys); + // skip if two width within shape for standard cell + if (!is_outside) { + ap->setAccess(dir, false); + return; + } + // TODO: EDIT HERE Wrongdirection segments + frLayer* layer = getDesign()->getTech()->getLayer(ap->getLayerNum()); + auto ps = std::make_unique(); + auto style = layer->getDefaultSegStyle(); + const bool vert_dir = (dir == frDirEnum::S || dir == frDirEnum::N); + const bool wrong_dir + = (layer->getDir() == dbTechLayerDir::HORIZONTAL && vert_dir) + || (layer->getDir() == dbTechLayerDir::VERTICAL && !vert_dir); + if (dir == frDirEnum::W || dir == frDirEnum::S) { + ps->setPoints(end_point, begin_point); + style.setEndStyle(frcTruncateEndStyle, 0); + } else { + ps->setPoints(begin_point, end_point); + style.setBeginStyle(frcTruncateEndStyle, 0); + } + if (wrong_dir) { + style.setWidth(layer->getWrongDirWidth()); + } + ps->setLayerNum(ap->getLayerNum()); + ps->setStyle(style); + if (inst_term && inst_term->hasNet()) { + ps->addToNet(inst_term->getNet()); + } else { + ps->addToPin(pin); + } + + const bool no_drv + = isPlanarViolationFree(ap, pin, ps.get(), inst_term, begin_point, layer); + ap->setAccess(dir, no_drv); +} + +template +bool FlexPA::isPlanarViolationFree(frAccessPoint* ap, + T* pin, + frPathSeg* ps, + frInstTerm* inst_term, + const Point point, + frLayer* layer) +{ + // Runs the DRC Engine to check for any violations + FlexGCWorker design_rule_checker(getTech(), logger_, router_cfg_); + design_rule_checker.setIgnoreMinArea(); + design_rule_checker.setIgnoreCornerSpacing(); + const auto pitch = layer->getPitch(); + const auto extension = 5 * pitch; + Rect tmp_box(point, point); + Rect ext_box; + tmp_box.bloat(extension, ext_box); + design_rule_checker.setExtBox(ext_box); + design_rule_checker.setDrcBox(ext_box); + if (inst_term) { + design_rule_checker.addTargetObj(inst_term->getInst()); + } else { + design_rule_checker.addTargetObj(pin->getTerm()); + } + design_rule_checker.initPA0(getDesign()); + auto pin_term = pin->getTerm(); + frBlockObject* owner; + if (inst_term) { + if (inst_term->hasNet()) { + owner = inst_term->getNet(); + } else { + owner = inst_term; + } + } else { + if (pin_term->hasNet()) { + owner = pin_term->getNet(); + } else { + owner = pin_term; + } + } + design_rule_checker.addPAObj(ps, owner); + for (auto& apPs : ap->getPathSegs()) { + design_rule_checker.addPAObj(&apPs, owner); + } + design_rule_checker.initPA1(); + design_rule_checker.main(); + design_rule_checker.end(); + + if (graphics_) { + graphics_->setPlanarAP(ap, ps, design_rule_checker.getMarkers()); + } + + return design_rule_checker.getMarkers().empty(); +} + +void FlexPA::getViasFromMetalWidthMap( + const Point& pt, + const frLayerNum layer_num, + const gtl::polygon_90_set_data& polyset, + std::vector>& via_defs) +{ + const auto tech = getTech(); + if (layer_num == tech->getTopLayerNum()) { + return; + } + const auto cut_layer = tech->getLayer(layer_num + 1)->getDbLayer(); + // If the upper layer has an NDR special handling will be needed + // here. Assuming normal min-width routing for now. + const frCoord top_width = tech->getLayer(layer_num + 2)->getMinWidth(); + const auto width_orient + = tech->isHorizontalLayer(layer_num) ? gtl::VERTICAL : gtl::HORIZONTAL; + frCoord bottom_width = -1; + auto viaMap = cut_layer->getTech()->getMetalWidthViaMap(); + for (auto entry : viaMap) { + if (entry->getCutLayer() != cut_layer) { + continue; + } + + if (entry->isPgVia()) { + continue; + } + + if (entry->isViaCutClass()) { + logger_->warn( + DRT, + 519, + "Via cut classes in LEF58_METALWIDTHVIAMAP are not supported."); + continue; + } + + if (entry->getAboveLayerWidthLow() > top_width + || entry->getAboveLayerWidthHigh() < top_width) { + continue; + } + + if (bottom_width < 0) { // compute bottom_width once + std::vector> maxrects; + gtl::get_max_rectangles(maxrects, polyset); + for (auto& rect : maxrects) { + if (contains(rect, gtl::point_data(pt.x(), pt.y()))) { + const frCoord width = delta(rect, width_orient); + bottom_width = std::max(bottom_width, width); + } + } + } + + if (entry->getBelowLayerWidthLow() > bottom_width + || entry->getBelowLayerWidthHigh() < bottom_width) { + continue; + } + + via_defs.emplace_back(via_defs.size(), tech->getVia(entry->getViaName())); + } +} + +template +void FlexPA::check_addViaAccess( + frAccessPoint* ap, + const std::vector>& layer_polys, + const gtl::polygon_90_set_data& polyset, + const frDirEnum dir, + T* pin, + frInstTerm* inst_term, + bool deep_search) +{ + const Point begin_point = ap->getPoint(); + const auto layer_num = ap->getLayerNum(); + // skip planar only access + if (!ap->isViaAllowed()) { + return; + } + + bool via_in_pin = false; + const auto lower_type = ap->getType(true); + const auto upper_type = ap->getType(false); + if (layer_num >= router_cfg_->VIAINPIN_BOTTOMLAYERNUM + && layer_num <= router_cfg_->VIAINPIN_TOPLAYERNUM) { + via_in_pin = true; + } else if ((lower_type == frAccessPointEnum::EncOpt + && upper_type != frAccessPointEnum::NearbyGrid) + || (upper_type == frAccessPointEnum::EncOpt + && lower_type != frAccessPointEnum::NearbyGrid)) { + via_in_pin = true; + } + + // check if ap is on the left/right boundary of the cell + Rect boundary_bbox; + bool is_side_bound = false; + if (inst_term) { + boundary_bbox = inst_term->getInst()->getBoundaryBBox(); + frCoord width = getDesign()->getTech()->getLayer(layer_num)->getWidth(); + if (begin_point.x() <= boundary_bbox.xMin() + 3 * width + || begin_point.x() >= boundary_bbox.xMax() - 3 * width) { + is_side_bound = true; + } + } + const int max_num_via_trial = 2; + // use std:pair to ensure deterministic behavior + std::vector> via_defs; + getViasFromMetalWidthMap(begin_point, layer_num, polyset, via_defs); + + if (via_defs.empty()) { // no via map entry + // hardcode first two single vias + for (auto& [tup, via_def] : layer_num_to_via_defs_[layer_num + 1][1]) { + via_defs.emplace_back(via_defs.size(), via_def); + if (via_defs.size() >= max_num_via_trial && !deep_search) { + break; + } + } + } + + std::set> valid_via_defs; + for (auto& [idx, via_def] : via_defs) { + auto via = std::make_unique(via_def); + via->setOrigin(begin_point); + const Rect box = via->getLayer1BBox(); + if (inst_term) { + if (!boundary_bbox.contains(box)) { + continue; + } + Rect layer2_boundary_box = via->getLayer2BBox(); + if (!boundary_bbox.contains(layer2_boundary_box)) { + continue; + } + } + + frCoord max_ext = 0; + const gtl::rectangle_data viarect( + box.xMin(), box.yMin(), box.xMax(), box.yMax()); + using boost::polygon::operators::operator+=; + using boost::polygon::operators::operator&=; + gtl::polygon_90_set_data intersection; + intersection += viarect; + intersection &= polyset; + // via ranking criteria: max extension distance beyond pin shape + std::vector> int_rects; + intersection.get_rectangles(int_rects, + gtl::orientation_2d_enum::HORIZONTAL); + for (const auto& r : int_rects) { + max_ext = std::max(max_ext, box.xMax() - gtl::xh(r)); + max_ext = std::max(max_ext, gtl::xl(r) - box.xMin()); + } + if (!is_side_bound) { + if (int_rects.size() > 1) { + int_rects.clear(); + intersection.get_rectangles(int_rects, + gtl::orientation_2d_enum::VERTICAL); + } + for (const auto& r : int_rects) { + max_ext = std::max(max_ext, box.yMax() - gtl::yh(r)); + max_ext = std::max(max_ext, gtl::yl(r) - box.yMin()); + } + } + if (via_in_pin && max_ext) { + continue; + } + if (checkViaAccess(ap, via.get(), pin, inst_term, layer_polys)) { + valid_via_defs.insert({max_ext, idx, via_def}); + if (valid_via_defs.size() >= max_num_via_trial) { + break; + } + } + } + ap->setAccess(dir, !valid_via_defs.empty()); + for (auto& [ext, idx, via_def] : valid_via_defs) { + ap->addViaDef(via_def); + } +} + +template +bool FlexPA::checkViaAccess( + frAccessPoint* ap, + frVia* via, + T* pin, + frInstTerm* inst_term, + const std::vector>& layer_polys) +{ + for (const frDirEnum dir : frDirEnumPlanar) { + if (checkDirectionalViaAccess(ap, via, pin, inst_term, layer_polys, dir)) { + return true; + } + } + return false; +} + +template +bool FlexPA::checkDirectionalViaAccess( + frAccessPoint* ap, + frVia* via, + T* pin, + frInstTerm* inst_term, + const std::vector>& layer_polys, + frDirEnum dir) +{ + auto upper_layer = getTech()->getLayer(via->getViaDef()->getLayer2Num()); + const bool vert_dir = (dir == frDirEnum::S || dir == frDirEnum::N); + const bool wrong_dir = (upper_layer->isHorizontal() && vert_dir) + || (upper_layer->isVertical() && !vert_dir); + auto style = upper_layer->getDefaultSegStyle(); + + if (wrong_dir) { + if (!router_cfg_->USENONPREFTRACKS || upper_layer->isUnidirectional()) { + return false; + } + style.setWidth(upper_layer->getWrongDirWidth()); + } + + const Point begin_point = ap->getPoint(); + const bool is_block + = inst_term + && inst_term->getInst()->getMaster()->getMasterType().isBlock(); + const Point end_point = genEndPoint(layer_polys, + begin_point, + via->getViaDef()->getLayer2Num(), + dir, + is_block); + + if (inst_term && inst_term->hasNet()) { + via->addToNet(inst_term->getNet()); + } else { + via->addToPin(pin); + } + // PS + auto ps = std::make_unique(); + if (dir == frDirEnum::W || dir == frDirEnum::S) { + ps->setPoints(end_point, begin_point); + style.setEndStyle(frcTruncateEndStyle, 0); + } else { + ps->setPoints(begin_point, end_point); + style.setBeginStyle(frcTruncateEndStyle, 0); + } + ps->setLayerNum(upper_layer->getLayerNum()); + ps->setStyle(style); + if (inst_term && inst_term->hasNet()) { + ps->addToNet(inst_term->getNet()); + } else { + ps->addToPin(pin); + } + return isViaViolationFree(ap, via, pin, ps.get(), inst_term, begin_point); +} + +template +bool FlexPA::isViaViolationFree(frAccessPoint* ap, + frVia* via, + T* pin, + frPathSeg* ps, + frInstTerm* inst_term, + const Point point) +{ + // Runs the DRC Engine to check for any violations + FlexGCWorker design_rule_checker(getTech(), logger_, router_cfg_); + design_rule_checker.setIgnoreMinArea(); + design_rule_checker.setIgnoreLongSideEOL(); + design_rule_checker.setIgnoreCornerSpacing(); + const auto pitch = getTech()->getLayer(ap->getLayerNum())->getPitch(); + const auto extension = 5 * pitch; + Rect tmp_box(point, point); + Rect ext_box; + tmp_box.bloat(extension, ext_box); + auto pin_term = pin->getTerm(); + auto pin_net = pin_term->getNet(); + design_rule_checker.setExtBox(ext_box); + design_rule_checker.setDrcBox(ext_box); + if (inst_term) { + if (!inst_term->getNet() || !inst_term->getNet()->getNondefaultRule() + || router_cfg_->AUTO_TAPER_NDR_NETS) { + design_rule_checker.addTargetObj(inst_term->getInst()); + } + } else { + if (!pin_net || !pin_net->getNondefaultRule() + || router_cfg_->AUTO_TAPER_NDR_NETS) { + design_rule_checker.addTargetObj(pin_term); + } + } + + design_rule_checker.initPA0(getDesign()); + frBlockObject* owner; + if (inst_term) { + if (inst_term->hasNet()) { + owner = inst_term->getNet(); + } else { + owner = inst_term; + } + } else { + if (pin_term->hasNet()) { + owner = pin_net; + } else { + owner = pin_term; + } + } + design_rule_checker.addPAObj(ps, owner); + design_rule_checker.addPAObj(via, owner); + for (auto& apPs : ap->getPathSegs()) { + design_rule_checker.addPAObj(&apPs, owner); + } + design_rule_checker.initPA1(); + design_rule_checker.main(); + design_rule_checker.end(); + + const bool no_drv = design_rule_checker.getMarkers().empty(); + + if (graphics_) { + graphics_->setViaAP(ap, via, design_rule_checker.getMarkers()); + } + return no_drv; +} + +template +void FlexPA::check_addAccess( + frAccessPoint* ap, + const gtl::polygon_90_set_data& polyset, + const std::vector>& polys, + T* pin, + frInstTerm* inst_term, + bool deep_search) +{ + if (!deep_search) { + for (const frDirEnum dir : frDirEnumPlanar) { + check_addPlanarAccess(ap, polys, dir, pin, inst_term); + } + } + check_addViaAccess( + ap, polys, polyset, frDirEnum::U, pin, inst_term, deep_search); +} + } \ No newline at end of file diff --git a/src/drt/src/pa/FlexPA_prep.cpp b/src/drt/src/pa/FlexPA_prep.cpp index e2de2fe3ec1..d27cd789a37 100644 --- a/src/drt/src/pa/FlexPA_prep.cpp +++ b/src/drt/src/pa/FlexPA_prep.cpp @@ -132,149 +132,6 @@ FlexPA::mergePinShapes(T* pin, frInstTerm* inst_term, const bool is_shrink) return pin_shapes; } -// Responsible for checking if an AP is valid and configuring it -void FlexPA::gen_createAccessPoint( - std::vector>& aps, - std::set>& apset, - const gtl::rectangle_data& maxrect, - const frCoord x, - const frCoord y, - const frLayerNum layer_num, - const bool allow_planar, - const bool allow_via, - const frAccessPointEnum low_cost, - const frAccessPointEnum high_cost) -{ - gtl::point_data pt(x, y); - if (!gtl::contains(maxrect, pt) && low_cost != frAccessPointEnum::NearbyGrid - && high_cost != frAccessPointEnum::NearbyGrid) { - return; - } - Point fpt(x, y); - if (apset.find(std::make_pair(fpt, layer_num)) != apset.end()) { - return; - } - auto ap = std::make_unique(fpt, layer_num); - - ap->setMultipleAccesses(frDirEnumPlanar, allow_planar); - - if (allow_planar) { - const auto lower_layer = getDesign()->getTech()->getLayer(layer_num); - // rectonly forbid wrongway planar access - // rightway on grid only forbid off track rightway planar access - // horz layer - if (lower_layer->getDir() == dbTechLayerDir::HORIZONTAL) { - if (lower_layer->isUnidirectional()) { - ap->setMultipleAccesses(frDirEnumVert, false); - } - if (lower_layer->getLef58RightWayOnGridOnlyConstraint() - && low_cost != frAccessPointEnum::OnGrid) { - ap->setMultipleAccesses(frDirEnumHorz, false); - } - } - // vert layer - if (lower_layer->getDir() == dbTechLayerDir::VERTICAL) { - if (lower_layer->isUnidirectional()) { - ap->setMultipleAccesses(frDirEnumHorz, false); - } - if (lower_layer->getLef58RightWayOnGridOnlyConstraint() - && low_cost != frAccessPointEnum::OnGrid) { - ap->setMultipleAccesses(frDirEnumVert, false); - } - } - } - ap->setAccess(frDirEnum::D, false); - ap->setAccess(frDirEnum::U, allow_via); - - ap->setAllowVia(allow_via); - ap->setType((frAccessPointEnum) low_cost, true); - ap->setType((frAccessPointEnum) high_cost, false); - if ((low_cost == frAccessPointEnum::NearbyGrid - || high_cost == frAccessPointEnum::NearbyGrid)) { - Point end; - const int half_width - = design_->getTech()->getLayer(ap->getLayerNum())->getMinWidth() / 2; - if (fpt.x() < gtl::xl(maxrect) + half_width) { - end.setX(gtl::xl(maxrect) + half_width); - } else if (fpt.x() > gtl::xh(maxrect) - half_width) { - end.setX(gtl::xh(maxrect) - half_width); - } else { - end.setX(fpt.x()); - } - if (fpt.y() < gtl::yl(maxrect) + half_width) { - end.setY(gtl::yl(maxrect) + half_width); - } else if (fpt.y() > gtl::yh(maxrect) - half_width) { - end.setY(gtl::yh(maxrect) - half_width); - } else { - end.setY(fpt.y()); - } - - Point e = fpt; - if (fpt.x() != end.x()) { - e.setX(end.x()); - } else if (fpt.y() != end.y()) { - e.setY(end.y()); - } - if (!(e == fpt)) { - frPathSeg ps; - ps.setPoints_safe(fpt, e); - if (ps.getBeginPoint() == end) { - ps.setBeginStyle(frEndStyle(frcTruncateEndStyle)); - } else if (ps.getEndPoint() == end) { - ps.setEndStyle(frEndStyle(frcTruncateEndStyle)); - } - ap->addPathSeg(ps); - if (!(e == end)) { - fpt = e; - ps.setPoints_safe(fpt, end); - if (ps.getBeginPoint() == end) { - ps.setBeginStyle(frEndStyle(frcTruncateEndStyle)); - } else { - ps.setEndStyle(frEndStyle(frcTruncateEndStyle)); - } - ap->addPathSeg(ps); - } - } - } - aps.push_back(std::move(ap)); - apset.insert(std::make_pair(fpt, layer_num)); -} - -void FlexPA::gen_initializeAccessPoints( - std::vector>& aps, - std::set>& apset, - const gtl::rectangle_data& rect, - const frLayerNum layer_num, - const bool allow_planar, - const bool allow_via, - const bool is_layer1_horz, - const std::map& x_coords, - const std::map& y_coords, - const frAccessPointEnum lower_type, - const frAccessPointEnum upper_type) -{ - // build points; - for (auto& [x_coord, cost_x] : x_coords) { - for (auto& [y_coord, cost_y] : y_coords) { - // lower full/half/center - auto& low_cost = is_layer1_horz ? cost_y : cost_x; - auto& high_cost = (!is_layer1_horz) ? cost_y : cost_x; - if (low_cost == lower_type && high_cost == upper_type) { - gen_createAccessPoint(aps, - apset, - rect, - x_coord, - y_coord, - layer_num, - allow_planar, - allow_via, - low_cost, - high_cost); - } - } - } -} - bool FlexPA::enclosesOnTrackPlanarAccess( const gtl::rectangle_data& rect, frLayerNum layer_num) @@ -321,723 +178,6 @@ bool FlexPA::enclosesOnTrackPlanarAccess( return true; } -/** - * @details Generates all necessary access points from a rectangle shape - * In this case a rectangle is one of the pin shapes of the pin - */ -void FlexPA::genAPsFromRect(std::vector>& aps, - std::set>& apset, - const gtl::rectangle_data& rect, - const frLayerNum layer_num, - const bool allow_planar, - const bool allow_via, - frAccessPointEnum lower_type, - const frAccessPointEnum upper_type, - const bool is_macro_cell_pin) -{ - auto layer = getDesign()->getTech()->getLayer(layer_num); - const auto min_width_layer1 = layer->getMinWidth(); - if (std::min(gtl::delta(rect, gtl::HORIZONTAL), - gtl::delta(rect, gtl::VERTICAL)) - < min_width_layer1) { - return; - } - frLayerNum second_layer_num = 0; - if (layer_num + 2 <= getDesign()->getTech()->getTopLayerNum()) { - second_layer_num = layer_num + 2; - } else if (layer_num - 2 >= getDesign()->getTech()->getBottomLayerNum()) { - second_layer_num = layer_num - 2; - } else { - logger_->error(DRT, 68, "genAPsFromRect cannot find second_layer_num."); - } - auto& layer1_track_coords = track_coords_[layer_num]; - auto& layer2_track_coords = track_coords_[second_layer_num]; - const bool is_layer1_horz = (layer->getDir() == dbTechLayerDir::HORIZONTAL); - - std::map x_coords; - std::map y_coords; - int hwidth = layer->getWidth() / 2; - bool use_center_line = false; - if (is_macro_cell_pin && !layer->getLef58RightWayOnGridOnlyConstraint()) { - auto rect_dir = gtl::guess_orientation(rect); - if ((rect_dir == gtl::HORIZONTAL && is_layer1_horz) - || (rect_dir == gtl::VERTICAL && !is_layer1_horz)) { - auto layer_width = layer->getWidth(); - if ((rect_dir == gtl::HORIZONTAL - && gtl::delta(rect, gtl::VERTICAL) < 2 * layer_width) - || (rect_dir == gtl::VERTICAL - && gtl::delta(rect, gtl::HORIZONTAL) < 2 * layer_width)) { - use_center_line = true; - } - } - } - - // gen all full/half grid coords - /** offset used to only be used after an if (!is_macro_cell_pin || - * !use_center_line), so this logic was combined with offset is_macro_cell_pin - * ? hwidth : 0; - */ - const int offset = is_macro_cell_pin && !use_center_line ? hwidth : 0; - const int layer1_rect_min = is_layer1_horz ? gtl::yl(rect) : gtl::xl(rect); - const int layer1_rect_max = is_layer1_horz ? gtl::yh(rect) : gtl::xh(rect); - auto& layer1_coords = is_layer1_horz ? y_coords : x_coords; - auto& layer2_coords = is_layer1_horz ? x_coords : y_coords; - - const frAccessPointEnum frDirEnums[] = {frAccessPointEnum::OnGrid, - frAccessPointEnum::Center, - frAccessPointEnum::EncOpt, - frAccessPointEnum::NearbyGrid}; - - for (const auto cost : frDirEnums) { - if (upper_type >= cost) { - genAPCosted(cost, - layer2_coords, - layer2_track_coords, - layer_num, - second_layer_num, - rect, - !is_layer1_horz, - offset); - } - } - if (!(is_macro_cell_pin && use_center_line)) { - for (const auto cost : frDirEnums) { - if (lower_type >= cost) { - genAPCosted(cost, - layer1_coords, - layer1_track_coords, - layer_num, - layer_num, - rect, - is_layer1_horz); - } - } - } else { - genAPCentered(layer1_coords, layer_num, layer1_rect_min, layer1_rect_max); - for (auto& [layer1_coord, cost] : layer1_coords) { - layer1_coords[layer1_coord] = frAccessPointEnum::OnGrid; - } - } - - if (is_macro_cell_pin && use_center_line && is_layer1_horz) { - lower_type = frAccessPointEnum::OnGrid; - } - - gen_initializeAccessPoints(aps, - apset, - rect, - layer_num, - allow_planar, - allow_via, - is_layer1_horz, - x_coords, - y_coords, - lower_type, - upper_type); -} - -void FlexPA::genAPsFromLayerShapes( - std::vector>& aps, - std::set>& apset, - frInstTerm* inst_term, - const gtl::polygon_90_set_data& layer_shapes, - const frLayerNum layer_num, - bool allow_via, - const frAccessPointEnum lower_type, - const frAccessPointEnum upper_type) -{ - if (getDesign()->getTech()->getLayer(layer_num)->getType() - != dbTechLayerType::ROUTING) { - return; - } - bool allow_planar = true; - bool is_macro_cell_pin = false; - if (inst_term) { - if (isStdCell(inst_term->getInst())) { - if ((layer_num >= router_cfg_->VIAINPIN_BOTTOMLAYERNUM - && layer_num <= router_cfg_->VIAINPIN_TOPLAYERNUM) - || layer_num <= router_cfg_->VIA_ACCESS_LAYERNUM) { - allow_planar = false; - } - } - is_macro_cell_pin = isMacroCell(inst_term->getInst()); - } else { - // IO term is treated as the MacroCellPin as the top block - is_macro_cell_pin = true; - allow_planar = true; - allow_via = false; - } - // lower layer is current layer - // rightway on grid only forbid off track up via access on upper layer - const auto upper_layer - = (layer_num + 2 <= getDesign()->getTech()->getTopLayerNum()) - ? getDesign()->getTech()->getLayer(layer_num + 2) - : nullptr; - if (!is_macro_cell_pin && upper_layer - && upper_layer->getLef58RightWayOnGridOnlyConstraint() - && upper_type != frAccessPointEnum::OnGrid) { - return; - } - std::vector> maxrects; - gtl::get_max_rectangles(maxrects, layer_shapes); - for (auto& bbox_rect : maxrects) { - genAPsFromRect(aps, - apset, - bbox_rect, - layer_num, - allow_planar, - allow_via, - lower_type, - upper_type, - is_macro_cell_pin); - } -} - -// filter off-grid coordinate -// lower on-grid 0, upper on-grid 0 = 0 -// lower 1/2 1, upper on-grid 0 = 1 -// lower center 2, upper on-grid 0 = 2 -// lower center 2, upper center 2 = 4 - -template -void FlexPA::genAPsFromPinShapes( - std::vector>& aps, - std::set>& apset, - T* pin, - frInstTerm* inst_term, - const std::vector>& pin_shapes, - const frAccessPointEnum lower_type, - const frAccessPointEnum upper_type) -{ - // only VIA_ACCESS_LAYERNUM layer can have via access - const bool allow_via = true; - frLayerNum layer_num = (int) pin_shapes.size() - 1; - for (auto it = pin_shapes.rbegin(); it != pin_shapes.rend(); it++) { - if (!it->empty() - && getDesign()->getTech()->getLayer(layer_num)->getType() - == dbTechLayerType::ROUTING) { - genAPsFromLayerShapes(aps, - apset, - inst_term, - *it, - layer_num, - allow_via, - lower_type, - upper_type); - } - layer_num--; - } -} - -Point FlexPA::genEndPoint( - const std::vector>& layer_polys, - const Point& begin_point, - const frLayerNum layer_num, - const frDirEnum dir, - const bool is_block) -{ - const int step_size_multiplier = 3; - frCoord x = begin_point.x(); - frCoord y = begin_point.y(); - const frCoord width = getDesign()->getTech()->getLayer(layer_num)->getWidth(); - const frCoord step_size = step_size_multiplier * width; - const frCoord pitch = getDesign()->getTech()->getLayer(layer_num)->getPitch(); - gtl::rectangle_data rect; - if (is_block) { - gtl::extents(rect, layer_polys[0]); - if (layer_polys.size() > 1) { - logger_->warn(DRT, 6000, "Macro pin has more than 1 polygon"); - } - } - switch (dir) { - case (frDirEnum::W): - if (is_block) { - x = gtl::xl(rect) - pitch; - } else { - x -= step_size; - } - break; - case (frDirEnum::E): - if (is_block) { - x = gtl::xh(rect) + pitch; - } else { - x += step_size; - } - break; - case (frDirEnum::S): - if (is_block) { - y = gtl::yl(rect) - pitch; - } else { - y -= step_size; - } - break; - case (frDirEnum::N): - if (is_block) { - y = gtl::yh(rect) + pitch; - } else { - y += step_size; - } - break; - default: - logger_->error(DRT, 70, "Unexpected direction in getPlanarEP."); - } - return {x, y}; -} - -bool FlexPA::isPointOutsideShapes( - const Point& point, - const std::vector>& layer_polys) -{ - const gtl::point_data pt(point.getX(), point.getY()); - for (auto& layer_poly : layer_polys) { - if (gtl::contains(layer_poly, pt)) { - return false; - break; - } - } - return true; -} - -template -void FlexPA::check_addPlanarAccess( - frAccessPoint* ap, - const std::vector>& layer_polys, - frDirEnum dir, - T* pin, - frInstTerm* inst_term) -{ - const Point begin_point = ap->getPoint(); - // skip viaonly access - if (!ap->hasAccess(dir)) { - return; - } - const bool is_block - = inst_term - && inst_term->getInst()->getMaster()->getMasterType().isBlock(); - const Point end_point - = genEndPoint(layer_polys, begin_point, ap->getLayerNum(), dir, is_block); - const bool is_outside = isPointOutsideShapes(end_point, layer_polys); - // skip if two width within shape for standard cell - if (!is_outside) { - ap->setAccess(dir, false); - return; - } - // TODO: EDIT HERE Wrongdirection segments - frLayer* layer = getDesign()->getTech()->getLayer(ap->getLayerNum()); - auto ps = std::make_unique(); - auto style = layer->getDefaultSegStyle(); - const bool vert_dir = (dir == frDirEnum::S || dir == frDirEnum::N); - const bool wrong_dir - = (layer->getDir() == dbTechLayerDir::HORIZONTAL && vert_dir) - || (layer->getDir() == dbTechLayerDir::VERTICAL && !vert_dir); - if (dir == frDirEnum::W || dir == frDirEnum::S) { - ps->setPoints(end_point, begin_point); - style.setEndStyle(frcTruncateEndStyle, 0); - } else { - ps->setPoints(begin_point, end_point); - style.setBeginStyle(frcTruncateEndStyle, 0); - } - if (wrong_dir) { - style.setWidth(layer->getWrongDirWidth()); - } - ps->setLayerNum(ap->getLayerNum()); - ps->setStyle(style); - if (inst_term && inst_term->hasNet()) { - ps->addToNet(inst_term->getNet()); - } else { - ps->addToPin(pin); - } - - const bool no_drv - = isPlanarViolationFree(ap, pin, ps.get(), inst_term, begin_point, layer); - ap->setAccess(dir, no_drv); -} - -template -bool FlexPA::isPlanarViolationFree(frAccessPoint* ap, - T* pin, - frPathSeg* ps, - frInstTerm* inst_term, - const Point point, - frLayer* layer) -{ - // Runs the DRC Engine to check for any violations - FlexGCWorker design_rule_checker(getTech(), logger_, router_cfg_); - design_rule_checker.setIgnoreMinArea(); - design_rule_checker.setIgnoreCornerSpacing(); - const auto pitch = layer->getPitch(); - const auto extension = 5 * pitch; - Rect tmp_box(point, point); - Rect ext_box; - tmp_box.bloat(extension, ext_box); - design_rule_checker.setExtBox(ext_box); - design_rule_checker.setDrcBox(ext_box); - if (inst_term) { - design_rule_checker.addTargetObj(inst_term->getInst()); - } else { - design_rule_checker.addTargetObj(pin->getTerm()); - } - design_rule_checker.initPA0(getDesign()); - auto pin_term = pin->getTerm(); - frBlockObject* owner; - if (inst_term) { - if (inst_term->hasNet()) { - owner = inst_term->getNet(); - } else { - owner = inst_term; - } - } else { - if (pin_term->hasNet()) { - owner = pin_term->getNet(); - } else { - owner = pin_term; - } - } - design_rule_checker.addPAObj(ps, owner); - for (auto& apPs : ap->getPathSegs()) { - design_rule_checker.addPAObj(&apPs, owner); - } - design_rule_checker.initPA1(); - design_rule_checker.main(); - design_rule_checker.end(); - - if (graphics_) { - graphics_->setPlanarAP(ap, ps, design_rule_checker.getMarkers()); - } - - return design_rule_checker.getMarkers().empty(); -} - -void FlexPA::getViasFromMetalWidthMap( - const Point& pt, - const frLayerNum layer_num, - const gtl::polygon_90_set_data& polyset, - std::vector>& via_defs) -{ - const auto tech = getTech(); - if (layer_num == tech->getTopLayerNum()) { - return; - } - const auto cut_layer = tech->getLayer(layer_num + 1)->getDbLayer(); - // If the upper layer has an NDR special handling will be needed - // here. Assuming normal min-width routing for now. - const frCoord top_width = tech->getLayer(layer_num + 2)->getMinWidth(); - const auto width_orient - = tech->isHorizontalLayer(layer_num) ? gtl::VERTICAL : gtl::HORIZONTAL; - frCoord bottom_width = -1; - auto viaMap = cut_layer->getTech()->getMetalWidthViaMap(); - for (auto entry : viaMap) { - if (entry->getCutLayer() != cut_layer) { - continue; - } - - if (entry->isPgVia()) { - continue; - } - - if (entry->isViaCutClass()) { - logger_->warn( - DRT, - 519, - "Via cut classes in LEF58_METALWIDTHVIAMAP are not supported."); - continue; - } - - if (entry->getAboveLayerWidthLow() > top_width - || entry->getAboveLayerWidthHigh() < top_width) { - continue; - } - - if (bottom_width < 0) { // compute bottom_width once - std::vector> maxrects; - gtl::get_max_rectangles(maxrects, polyset); - for (auto& rect : maxrects) { - if (contains(rect, gtl::point_data(pt.x(), pt.y()))) { - const frCoord width = delta(rect, width_orient); - bottom_width = std::max(bottom_width, width); - } - } - } - - if (entry->getBelowLayerWidthLow() > bottom_width - || entry->getBelowLayerWidthHigh() < bottom_width) { - continue; - } - - via_defs.emplace_back(via_defs.size(), tech->getVia(entry->getViaName())); - } -} - -template -void FlexPA::check_addViaAccess( - frAccessPoint* ap, - const std::vector>& layer_polys, - const gtl::polygon_90_set_data& polyset, - const frDirEnum dir, - T* pin, - frInstTerm* inst_term, - bool deep_search) -{ - const Point begin_point = ap->getPoint(); - const auto layer_num = ap->getLayerNum(); - // skip planar only access - if (!ap->isViaAllowed()) { - return; - } - - bool via_in_pin = false; - const auto lower_type = ap->getType(true); - const auto upper_type = ap->getType(false); - if (layer_num >= router_cfg_->VIAINPIN_BOTTOMLAYERNUM - && layer_num <= router_cfg_->VIAINPIN_TOPLAYERNUM) { - via_in_pin = true; - } else if ((lower_type == frAccessPointEnum::EncOpt - && upper_type != frAccessPointEnum::NearbyGrid) - || (upper_type == frAccessPointEnum::EncOpt - && lower_type != frAccessPointEnum::NearbyGrid)) { - via_in_pin = true; - } - - // check if ap is on the left/right boundary of the cell - Rect boundary_bbox; - bool is_side_bound = false; - if (inst_term) { - boundary_bbox = inst_term->getInst()->getBoundaryBBox(); - frCoord width = getDesign()->getTech()->getLayer(layer_num)->getWidth(); - if (begin_point.x() <= boundary_bbox.xMin() + 3 * width - || begin_point.x() >= boundary_bbox.xMax() - 3 * width) { - is_side_bound = true; - } - } - const int max_num_via_trial = 2; - // use std:pair to ensure deterministic behavior - std::vector> via_defs; - getViasFromMetalWidthMap(begin_point, layer_num, polyset, via_defs); - - if (via_defs.empty()) { // no via map entry - // hardcode first two single vias - for (auto& [tup, via_def] : layer_num_to_via_defs_[layer_num + 1][1]) { - via_defs.emplace_back(via_defs.size(), via_def); - if (via_defs.size() >= max_num_via_trial && !deep_search) { - break; - } - } - } - - std::set> valid_via_defs; - for (auto& [idx, via_def] : via_defs) { - auto via = std::make_unique(via_def); - via->setOrigin(begin_point); - const Rect box = via->getLayer1BBox(); - if (inst_term) { - if (!boundary_bbox.contains(box)) { - continue; - } - Rect layer2_boundary_box = via->getLayer2BBox(); - if (!boundary_bbox.contains(layer2_boundary_box)) { - continue; - } - } - - frCoord max_ext = 0; - const gtl::rectangle_data viarect( - box.xMin(), box.yMin(), box.xMax(), box.yMax()); - using boost::polygon::operators::operator+=; - using boost::polygon::operators::operator&=; - gtl::polygon_90_set_data intersection; - intersection += viarect; - intersection &= polyset; - // via ranking criteria: max extension distance beyond pin shape - std::vector> int_rects; - intersection.get_rectangles(int_rects, - gtl::orientation_2d_enum::HORIZONTAL); - for (const auto& r : int_rects) { - max_ext = std::max(max_ext, box.xMax() - gtl::xh(r)); - max_ext = std::max(max_ext, gtl::xl(r) - box.xMin()); - } - if (!is_side_bound) { - if (int_rects.size() > 1) { - int_rects.clear(); - intersection.get_rectangles(int_rects, - gtl::orientation_2d_enum::VERTICAL); - } - for (const auto& r : int_rects) { - max_ext = std::max(max_ext, box.yMax() - gtl::yh(r)); - max_ext = std::max(max_ext, gtl::yl(r) - box.yMin()); - } - } - if (via_in_pin && max_ext) { - continue; - } - if (checkViaAccess(ap, via.get(), pin, inst_term, layer_polys)) { - valid_via_defs.insert({max_ext, idx, via_def}); - if (valid_via_defs.size() >= max_num_via_trial) { - break; - } - } - } - ap->setAccess(dir, !valid_via_defs.empty()); - for (auto& [ext, idx, via_def] : valid_via_defs) { - ap->addViaDef(via_def); - } -} - -template -bool FlexPA::checkViaAccess( - frAccessPoint* ap, - frVia* via, - T* pin, - frInstTerm* inst_term, - const std::vector>& layer_polys) -{ - for (const frDirEnum dir : frDirEnumPlanar) { - if (checkDirectionalViaAccess(ap, via, pin, inst_term, layer_polys, dir)) { - return true; - } - } - return false; -} - -template -bool FlexPA::checkDirectionalViaAccess( - frAccessPoint* ap, - frVia* via, - T* pin, - frInstTerm* inst_term, - const std::vector>& layer_polys, - frDirEnum dir) -{ - auto upper_layer = getTech()->getLayer(via->getViaDef()->getLayer2Num()); - const bool vert_dir = (dir == frDirEnum::S || dir == frDirEnum::N); - const bool wrong_dir = (upper_layer->isHorizontal() && vert_dir) - || (upper_layer->isVertical() && !vert_dir); - auto style = upper_layer->getDefaultSegStyle(); - - if (wrong_dir) { - if (!router_cfg_->USENONPREFTRACKS || upper_layer->isUnidirectional()) { - return false; - } - style.setWidth(upper_layer->getWrongDirWidth()); - } - - const Point begin_point = ap->getPoint(); - const bool is_block - = inst_term - && inst_term->getInst()->getMaster()->getMasterType().isBlock(); - const Point end_point = genEndPoint(layer_polys, - begin_point, - via->getViaDef()->getLayer2Num(), - dir, - is_block); - - if (inst_term && inst_term->hasNet()) { - via->addToNet(inst_term->getNet()); - } else { - via->addToPin(pin); - } - // PS - auto ps = std::make_unique(); - if (dir == frDirEnum::W || dir == frDirEnum::S) { - ps->setPoints(end_point, begin_point); - style.setEndStyle(frcTruncateEndStyle, 0); - } else { - ps->setPoints(begin_point, end_point); - style.setBeginStyle(frcTruncateEndStyle, 0); - } - ps->setLayerNum(upper_layer->getLayerNum()); - ps->setStyle(style); - if (inst_term && inst_term->hasNet()) { - ps->addToNet(inst_term->getNet()); - } else { - ps->addToPin(pin); - } - return isViaViolationFree(ap, via, pin, ps.get(), inst_term, begin_point); -} - -template -bool FlexPA::isViaViolationFree(frAccessPoint* ap, - frVia* via, - T* pin, - frPathSeg* ps, - frInstTerm* inst_term, - const Point point) -{ - // Runs the DRC Engine to check for any violations - FlexGCWorker design_rule_checker(getTech(), logger_, router_cfg_); - design_rule_checker.setIgnoreMinArea(); - design_rule_checker.setIgnoreLongSideEOL(); - design_rule_checker.setIgnoreCornerSpacing(); - const auto pitch = getTech()->getLayer(ap->getLayerNum())->getPitch(); - const auto extension = 5 * pitch; - Rect tmp_box(point, point); - Rect ext_box; - tmp_box.bloat(extension, ext_box); - auto pin_term = pin->getTerm(); - auto pin_net = pin_term->getNet(); - design_rule_checker.setExtBox(ext_box); - design_rule_checker.setDrcBox(ext_box); - if (inst_term) { - if (!inst_term->getNet() || !inst_term->getNet()->getNondefaultRule() - || router_cfg_->AUTO_TAPER_NDR_NETS) { - design_rule_checker.addTargetObj(inst_term->getInst()); - } - } else { - if (!pin_net || !pin_net->getNondefaultRule() - || router_cfg_->AUTO_TAPER_NDR_NETS) { - design_rule_checker.addTargetObj(pin_term); - } - } - - design_rule_checker.initPA0(getDesign()); - frBlockObject* owner; - if (inst_term) { - if (inst_term->hasNet()) { - owner = inst_term->getNet(); - } else { - owner = inst_term; - } - } else { - if (pin_term->hasNet()) { - owner = pin_net; - } else { - owner = pin_term; - } - } - design_rule_checker.addPAObj(ps, owner); - design_rule_checker.addPAObj(via, owner); - for (auto& apPs : ap->getPathSegs()) { - design_rule_checker.addPAObj(&apPs, owner); - } - design_rule_checker.initPA1(); - design_rule_checker.main(); - design_rule_checker.end(); - - const bool no_drv = design_rule_checker.getMarkers().empty(); - - if (graphics_) { - graphics_->setViaAP(ap, via, design_rule_checker.getMarkers()); - } - return no_drv; -} - -template -void FlexPA::check_addAccess( - frAccessPoint* ap, - const gtl::polygon_90_set_data& polyset, - const std::vector>& polys, - T* pin, - frInstTerm* inst_term, - bool deep_search) -{ - if (!deep_search) { - for (const frDirEnum dir : frDirEnumPlanar) { - check_addPlanarAccess(ap, polys, dir, pin, inst_term); - } - } - check_addViaAccess( - ap, polys, polyset, frDirEnum::U, pin, inst_term, deep_search); -} - template void FlexPA::check_setAPsAccesses( std::vector>& aps, From 58ab150f8ac80115e85ee93030a586e200f8452a Mon Sep 17 00:00:00 2001 From: bernardo Date: Sun, 15 Dec 2024 00:04:52 +0000 Subject: [PATCH 56/98] more rest of acc point Signed-off-by: bernardo move mergePinShapes Signed-off-by: bernardo move reverAccessPoint Signed-off-by: bernardo --- src/drt/CMakeLists.txt | 480 ++++++++++++++-------------- src/drt/src/pa/FlexPA_acc_point.cpp | 448 ++++++++++++++++++++++++++ src/drt/src/pa/FlexPA_prep.cpp | 448 -------------------------- 3 files changed, 685 insertions(+), 691 deletions(-) diff --git a/src/drt/CMakeLists.txt b/src/drt/CMakeLists.txt index d7e3a60c515..3ccba7f51cd 100644 --- a/src/drt/CMakeLists.txt +++ b/src/drt/CMakeLists.txt @@ -1,273 +1,267 @@ -############################################################################## # ####BSD 3 - - Clause License####Copyright(c) 2021, - The Regents of the University of California - ##All rights reserved.####Redistribution and use in source and binary forms, - with or without##modification, - are permitted provided that the following conditions are met - :####*Redistributions of source code must retain the above copyright notice, - this##list of conditions and the following disclaimer.####*Redistributions - in binary form must reproduce the above copyright notice, - ##this list of conditions and the following disclaimer in the documentation - ##and# - or other materials provided with the distribution.####*Neither the name - of the copyright holder nor the names of its - ##contributors may be used to endorse - or promote products derived from - ##this software without specific prior written permission.####THIS - SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - "AS IS"##AND ANY EXPRESS OR IMPLIED WARRANTIES, - INCLUDING, - BUT NOT LIMITED TO, - THE##IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - PARTICULAR PURPOSE - ##ARE DISCLAIMED.IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - ##LIABLE FOR ANY DIRECT, - INDIRECT, - INCIDENTAL, - SPECIAL, - EXEMPLARY, - OR##CONSEQUENTIAL DAMAGES(INCLUDING, - BUT NOT LIMITED TO, - PROCUREMENT OF##SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; - OR BUSINESS##INTERRUPTION) - HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - WHETHER IN##CONTRACT, - STRICT LIABILITY, - OR TORT(INCLUDING NEGLIGENCE OR - OTHERWISE)##ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - EVEN IF ADVISED OF THE##POSSIBILITY OF SUCH DAMAGE - .################################################################################ # +############################################################################### +## +## BSD 3-Clause License +## +## Copyright (c) 2021, The Regents of the University of California +## All rights reserved. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, this +## list of conditions and the following disclaimer. +## +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and#or other materials provided with the distribution. +## +## * Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from +## this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. +## +############################################################################### - include("openroad") +include("openroad") - option(DEBUG_DRT_UNDERFLOW - "Check for underflow in drt cost calculations" OFF) +option(DEBUG_DRT_UNDERFLOW "Check for underflow in drt cost calculations" OFF) - project(drt LANGUAGES CXX) +project(drt + LANGUAGES CXX +) - set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${ - PROJECT_SOURCE_DIR} - / cmake) +set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${PROJECT_SOURCE_DIR}/cmake) - include(CheckIPOSupported) check_ipo_supported( - RESULT ipo_supported OUTPUT error) +include(CheckIPOSupported) +check_ipo_supported(RESULT ipo_supported OUTPUT error) - find_package(Boost REQUIRED COMPONENTS serialization) find_package( - OpenMP REQUIRED) find_package(VTune) +find_package(Boost REQUIRED COMPONENTS serialization) +find_package(OpenMP REQUIRED) +find_package(VTune) - swig_lib( - NAME drt NAMESPACE drt I_FILE src - / TritonRoute.i SCRIPTS src / TritonRoute.tcl) +swig_lib(NAME drt + NAMESPACE drt + I_FILE src/TritonRoute.i + SCRIPTS src/TritonRoute.tcl +) - set(FLEXROUTE_HOME ${PROJECT_SOURCE_DIR}) +set(FLEXROUTE_HOME ${PROJECT_SOURCE_DIR}) - target_sources(drt PRIVATE src / gr - / FlexGRCMap.cpp src / gr - / FlexGR.cpp src / gr - / FlexGR_end.cpp src / gr - / FlexGRGridGraph.cpp - src - / gr - / FlexGRGridGraph_maze.cpp - src - / gr - / FlexGR_init.cpp - src - / gr - / FlexGR_maze.cpp - src - / gr / FlexGR_rq.cpp src - / gr - / FlexGR_topo.cpp - src - / dr - / FlexDR_conn.cpp - src - / dr - / FlexDR_init.cpp - src - / dr - / FlexDR.cpp src - / db / drObj / drNet.cpp src - / dr - / FlexDR_maze.cpp - src - / dr - / FlexGridGraph_maze.cpp src - / dr / FlexGridGraph.cpp src - / dr / FlexDR_rq.cpp src - / dr / FlexDR_end.cpp src - / dr - / FlexDR_graphics.cpp src - / ta / FlexTA_end.cpp src - / ta / FlexTA_init.cpp src - / ta / FlexTA_rq.cpp src - / ta / FlexTA_assign.cpp src - / ta - / FlexTA.cpp src / ta - / FlexTA_graphics.cpp src - / global.cpp src / gc - / FlexGC_end.cpp src / gc - / FlexGC_rq.cpp src / gc - / FlexGC.cpp src - / gc / FlexGC_init.cpp src - / gc / FlexGC_main.cpp src - / gc / FlexGC_eol.cpp src - / gc / FlexGC_inf.cpp src - / gc / FlexGC_cut.cpp src - / gc / FlexGC_metspc.cpp src - / db / drObj - / drAccessPattern.cpp src - / db / drObj / drPin.cpp src - / db / drObj - / drShape.cpp - src - / db / drObj / drVia.cpp src - / db / infra - / frTime_helper.cpp src / db - / infra - / frTime.cpp src / db - / infra - / KDTree.cpp src / db - / taObj - / taShape.cpp - src - / db / obj / frShape.cpp src - / db / obj / frInst.cpp src - / db / obj / frVia.cpp src - / db - / obj / frAccess.cpp src - / db / obj / frRPin.cpp src - / db / obj / frNode.cpp src - / db / obj - / frInstTerm.cpp src - / db / obj / frNet.cpp src - / db - / tech / frConstraint.cc src - / db - / obj / frMarker.cpp src - / db / tech / frLayer.cc src - / frRegionQuery.cpp src / io - / io_pin.cpp src / io - / io.cpp src / io - / GuideProcessor.cpp src - / io - / io_parser_helper.cpp src - / pa / FlexPA_init.cpp src - / pa - / FlexPA.cpp src - / pa / FlexPA_prep.cpp src - / pa - / FlexPA_acc_point.cpp src - / pa - / FlexPA_acc_pattern.cpp src - / pa - / FlexPA_row_pattern.cpp src - / pa / FlexPA_unique.cpp src - / pa - / FlexPA_graphics.cpp src - / rp / FlexRP_init.cpp src - / rp - / FlexRP.cpp src - / rp / FlexRP_prep.cpp src - / distributed - / frArchive.cpp src - / distributed / drUpdate.cpp src - / distributed / paUpdate.cpp src - / TritonRoute.cpp - src - / MakeTritonRoute.cpp src - / frBaseTypes.cpp - src - / DesignCallBack.cpp) +target_sources(drt + PRIVATE + src/gr/FlexGRCMap.cpp + src/gr/FlexGR.cpp + src/gr/FlexGR_end.cpp + src/gr/FlexGRGridGraph.cpp + src/gr/FlexGRGridGraph_maze.cpp + src/gr/FlexGR_init.cpp + src/gr/FlexGR_maze.cpp + src/gr/FlexGR_rq.cpp + src/gr/FlexGR_topo.cpp + src/dr/FlexDR_conn.cpp + src/dr/FlexDR_init.cpp + src/dr/FlexDR.cpp + src/db/drObj/drNet.cpp + src/dr/FlexDR_maze.cpp + src/dr/FlexGridGraph_maze.cpp + src/dr/FlexGridGraph.cpp + src/dr/FlexDR_rq.cpp + src/dr/FlexDR_end.cpp + src/dr/FlexDR_graphics.cpp + src/ta/FlexTA_end.cpp + src/ta/FlexTA_init.cpp + src/ta/FlexTA_rq.cpp + src/ta/FlexTA_assign.cpp + src/ta/FlexTA.cpp + src/ta/FlexTA_graphics.cpp + src/global.cpp + src/gc/FlexGC_end.cpp + src/gc/FlexGC_rq.cpp + src/gc/FlexGC.cpp + src/gc/FlexGC_init.cpp + src/gc/FlexGC_main.cpp + src/gc/FlexGC_eol.cpp + src/gc/FlexGC_inf.cpp + src/gc/FlexGC_cut.cpp + src/gc/FlexGC_metspc.cpp + src/db/drObj/drAccessPattern.cpp + src/db/drObj/drPin.cpp + src/db/drObj/drShape.cpp + src/db/drObj/drVia.cpp + src/db/infra/frTime_helper.cpp + src/db/infra/frTime.cpp + src/db/infra/KDTree.cpp + src/db/taObj/taShape.cpp + src/db/obj/frShape.cpp + src/db/obj/frInst.cpp + src/db/obj/frVia.cpp + src/db/obj/frAccess.cpp + src/db/obj/frRPin.cpp + src/db/obj/frNode.cpp + src/db/obj/frInstTerm.cpp + src/db/obj/frNet.cpp + src/db/tech/frConstraint.cc + src/db/obj/frMarker.cpp + src/db/tech/frLayer.cc + src/frRegionQuery.cpp + src/io/io_pin.cpp + src/io/io.cpp + src/io/GuideProcessor.cpp + src/io/io_parser_helper.cpp + src/pa/FlexPA_init.cpp + src/pa/FlexPA.cpp + src/pa/FlexPA_prep.cpp + src/pa/FlexPA_acc_point.cpp + src/pa/FlexPA_acc_pattern.cpp + src/pa/FlexPA_row_pattern.cpp + src/pa/FlexPA_unique.cpp + src/pa/FlexPA_graphics.cpp + src/rp/FlexRP_init.cpp + src/rp/FlexRP.cpp + src/rp/FlexRP_prep.cpp + src/distributed/frArchive.cpp + src/distributed/drUpdate.cpp + src/distributed/paUpdate.cpp + src/TritonRoute.cpp + src/MakeTritonRoute.cpp + src/frBaseTypes.cpp + src/DesignCallBack.cpp +) - target_include_directories( - drt PUBLIC include +target_include_directories(drt + PUBLIC + include - PRIVATE - src) + PRIVATE + src +) - target_link_libraries( - drt PUBLIC gui odb stt OpenSTA utl dst - dbSta Threads::Threads OpenMP:: - OpenMP_CXX ${ - Boost_LIBRARIES} ZLIB:: - ZLIB) +target_link_libraries(drt + PUBLIC + gui + odb + stt + OpenSTA + utl + dst + dbSta + Threads::Threads + OpenMP::OpenMP_CXX + ${Boost_LIBRARIES} + ZLIB::ZLIB +) - messages(TARGET drt) +messages( + TARGET drt +) - ############################################################ -#Compiler flags - ############################################################ -#Todo : add - Wextra and cleanup warnings - target_compile_options( - drt PRIVATE $<$ : -Wall - pedantic - Wcast - - qual - Wredundant - decls - Wformat - security> - $<$ : -Wall - pedantic - Wcast - qual - - Wredundant - decls - Wformat - security - Wno - gnu - zero - - variadic - macro - arguments> - $<$ : -Wall - pedantic - Wcast - qual - - Wredundant - decls - Wformat - security - Wno - gnu - zero - - variadic - macro - arguments>) +############################################################ +# Compiler flags +############################################################ +# Todo: add -Wextra and cleanup warnings +target_compile_options(drt + PRIVATE + $<$:-Wall -pedantic -Wcast-qual -Wredundant-decls -Wformat-security> + $<$:-Wall -pedantic -Wcast-qual -Wredundant-decls -Wformat-security -Wno-gnu-zero-variadic-macro-arguments> + $<$:-Wall -pedantic -Wcast-qual -Wredundant-decls -Wformat-security -Wno-gnu-zero-variadic-macro-arguments> + ) - ############################################################ -#Unit testing - ############################################################if ( - ENABLE_TESTS) enable_testing() +############################################################ +# Unit testing +############################################################ +if(ENABLE_TESTS) + enable_testing() - add_executable(trTest ${FLEXROUTE_HOME} / test - / gcTest.cpp ${FLEXROUTE_HOME} / test - / fixture.cpp ${FLEXROUTE_HOME} / test - / stubs.cpp ${OPENROAD_HOME} / src / gui / src - / stub.cpp) + add_executable(trTest + ${FLEXROUTE_HOME}/test/gcTest.cpp + ${FLEXROUTE_HOME}/test/fixture.cpp + ${FLEXROUTE_HOME}/test/stubs.cpp + ${OPENROAD_HOME}/src/gui/src/stub.cpp + ) - target_include_directories(trTest PRIVATE ${FLEXROUTE_HOME} - / src ${OPENROAD_HOME} / include) + target_include_directories(trTest + PRIVATE + ${FLEXROUTE_HOME}/src + ${OPENROAD_HOME}/include + ) - target_link_libraries(trTest drt odb) + target_link_libraries(trTest + drt + odb + ) -#Use the shared library if found.We need to pass this info to -#the code to select the corresponding include.Using the shared -#library speeds up compilation. - if (Boost_unit_test_framework_FOUND) message( - STATUS "Boost unit_test_framework library found") - target_link_libraries( - trTest Boost::unit_test_framework) - target_compile_definitions( - trTest PRIVATE - HAS_BOOST_UNIT_TEST_LIBRARY) endif() + # Use the shared library if found. We need to pass this info to + # the code to select the corresponding include. Using the shared + # library speeds up compilation. + if (Boost_unit_test_framework_FOUND) + message(STATUS "Boost unit_test_framework library found") + target_link_libraries(trTest + Boost::unit_test_framework + ) + target_compile_definitions(trTest + PRIVATE + HAS_BOOST_UNIT_TEST_LIBRARY + ) + endif() - add_test(NAME trTest COMMAND - trTest) add_dependencies(build_and_test - trTest) + add_test(NAME trTest COMMAND trTest) + add_dependencies(build_and_test trTest) - if (DEBUG_DRT_UNDERFLOW) target_compile_definitions( - drt PRIVATE - DEBUG_DRT_UNDERFLOW - = 1) endif() endif() + if(DEBUG_DRT_UNDERFLOW) + target_compile_definitions(drt + PRIVATE + DEBUG_DRT_UNDERFLOW=1 + ) + endif() +endif() - ############################################################ -#VTune ITT API - ############################################################ +############################################################ +# VTune ITT API +############################################################ - if (VTune_FOUND) target_compile_definitions(drt PUBLIC HAS_VTUNE = 1) +if (VTune_FOUND) + target_compile_definitions(drt + PUBLIC + HAS_VTUNE=1 + ) - target_link_libraries(drt PUBLIC VTune::VTune) + target_link_libraries(drt + PUBLIC + VTune::VTune + ) - endif(VTune_FOUND) +endif(VTune_FOUND) - if (Python3_FOUND AND BUILD_PYTHON) swig_lib( - NAME drt_py NAMESPACE drt LANGUAGE python I_FILE src - / TritonRoute - - py.i SWIG_INCLUDES ${PROJECT_SOURCE_DIR} / include - / drt SCRIPTS ${CMAKE_CURRENT_BINARY_DIR} - / drt_py.py) +if (Python3_FOUND AND BUILD_PYTHON) + swig_lib(NAME drt_py + NAMESPACE drt + LANGUAGE python + I_FILE src/TritonRoute-py.i + SWIG_INCLUDES ${PROJECT_SOURCE_DIR}/include/drt + SCRIPTS ${CMAKE_CURRENT_BINARY_DIR}/drt_py.py + ) - target_include_directories(drt_py PUBLIC include) + target_include_directories(drt_py + PUBLIC + include + ) - target_link_libraries(drt_py PUBLIC drt) + target_link_libraries(drt_py + PUBLIC + drt + ) - endif() +endif() - add_subdirectory(test) \ No newline at end of file +add_subdirectory(test) \ No newline at end of file diff --git a/src/drt/src/pa/FlexPA_acc_point.cpp b/src/drt/src/pa/FlexPA_acc_point.cpp index cc12c86f72b..291ff9d46cc 100644 --- a/src/drt/src/pa/FlexPA_acc_point.cpp +++ b/src/drt/src/pa/FlexPA_acc_point.cpp @@ -1076,4 +1076,452 @@ void FlexPA::check_addAccess( ap, polys, polyset, frDirEnum::U, pin, inst_term, deep_search); } +template +void FlexPA::check_setAPsAccesses( + std::vector>& aps, + const std::vector>& pin_shapes, + T* pin, + frInstTerm* inst_term, + const bool& is_std_cell_pin) +{ + std::vector>> layer_polys( + pin_shapes.size()); + for (int i = 0; i < (int) pin_shapes.size(); i++) { + pin_shapes[i].get_polygons(layer_polys[i]); + } + bool has_access = false; + for (auto& ap : aps) { + const auto layer_num = ap->getLayerNum(); + check_addAccess(ap.get(), + pin_shapes[layer_num], + layer_polys[layer_num], + pin, + inst_term); + if (is_std_cell_pin) { + has_access |= ((layer_num == router_cfg_->VIA_ACCESS_LAYERNUM + && ap->hasAccess(frDirEnum::U)) + || (layer_num != router_cfg_->VIA_ACCESS_LAYERNUM + && ap->hasAccess())); + } else { + has_access |= ap->hasAccess(); + } + } + if (!has_access) { + for (auto& ap : aps) { + const auto layer_num = ap->getLayerNum(); + check_addAccess(ap.get(), + pin_shapes[layer_num], + layer_polys[layer_num], + pin, + inst_term, + true); + } + } +} + +template +void FlexPA::updatePinStats( + const std::vector>& tmp_aps, + T* pin, + frInstTerm* inst_term) +{ + bool is_std_cell_pin = false; + bool is_macro_cell_pin = false; + if (inst_term) { + is_std_cell_pin = isStdCell(inst_term->getInst()); + is_macro_cell_pin = isMacroCell(inst_term->getInst()); + } + for (auto& ap : tmp_aps) { + if (ap->hasAccess(frDirEnum::W) || ap->hasAccess(frDirEnum::E) + || ap->hasAccess(frDirEnum::S) || ap->hasAccess(frDirEnum::N)) { + if (is_std_cell_pin) { +#pragma omp atomic + std_cell_pin_valid_planar_ap_cnt_++; + } + if (is_macro_cell_pin) { +#pragma omp atomic + macro_cell_pin_valid_planar_ap_cnt_++; + } + } + if (ap->hasAccess(frDirEnum::U)) { + if (is_std_cell_pin) { +#pragma omp atomic + std_cell_pin_valid_via_ap_cnt_++; + } + if (is_macro_cell_pin) { +#pragma omp atomic + macro_cell_pin_valid_via_ap_cnt_++; + } + } + } +} + +template +bool FlexPA::initPinAccessCostBounded( + std::vector>& aps, + std::set>& apset, + std::vector>& pin_shapes, + T* pin, + frInstTerm* inst_term, + const frAccessPointEnum lower_type, + const frAccessPointEnum upper_type) +{ + bool is_std_cell_pin = false; + bool is_macro_cell_pin = false; + if (inst_term) { + is_std_cell_pin = isStdCell(inst_term->getInst()); + is_macro_cell_pin = isMacroCell(inst_term->getInst()); + } + const bool is_io_pin = (inst_term == nullptr); + std::vector> tmp_aps; + genAPsFromPinShapes( + tmp_aps, apset, pin, inst_term, pin_shapes, lower_type, upper_type); + check_setAPsAccesses(tmp_aps, pin_shapes, pin, inst_term, is_std_cell_pin); + if (is_std_cell_pin) { +#pragma omp atomic + std_cell_pin_gen_ap_cnt_ += tmp_aps.size(); + } + if (is_macro_cell_pin) { +#pragma omp atomic + macro_cell_pin_gen_ap_cnt_ += tmp_aps.size(); + } + if (graphics_) { + graphics_->setAPs(tmp_aps, lower_type, upper_type); + } + for (auto& ap : tmp_aps) { + // for stdcell, add (i) planar access if layer_num != VIA_ACCESS_LAYERNUM, + // and (ii) access if exist access for macro, allow pure planar ap + if (is_std_cell_pin) { + const auto layer_num = ap->getLayerNum(); + if ((layer_num == router_cfg_->VIA_ACCESS_LAYERNUM + && ap->hasAccess(frDirEnum::U)) + || (layer_num != router_cfg_->VIA_ACCESS_LAYERNUM + && ap->hasAccess())) { + aps.push_back(std::move(ap)); + } + } else if ((is_macro_cell_pin || is_io_pin) && ap->hasAccess()) { + aps.push_back(std::move(ap)); + } + } + int n_sparse_access_points = (int) aps.size(); + Rect tbx; + for (int i = 0; i < (int) aps.size(); + i++) { // not perfect but will do the job + int r = design_->getTech()->getLayer(aps[i]->getLayerNum())->getWidth() / 2; + tbx.init( + aps[i]->x() - r, aps[i]->y() - r, aps[i]->x() + r, aps[i]->y() + r); + for (int j = i + 1; j < (int) aps.size(); j++) { + if (aps[i]->getLayerNum() == aps[j]->getLayerNum() + && tbx.intersects(aps[j]->getPoint())) { + n_sparse_access_points--; + break; + } + } + } + if (is_std_cell_pin + && n_sparse_access_points >= router_cfg_->MINNUMACCESSPOINT_STDCELLPIN) { + updatePinStats(aps, pin, inst_term); + // write to pa + const int pin_access_idx = unique_insts_.getPAIndex(inst_term->getInst()); + for (auto& ap : aps) { + pin->getPinAccess(pin_access_idx)->addAccessPoint(std::move(ap)); + } + return true; + } + if (is_macro_cell_pin + && n_sparse_access_points + >= router_cfg_->MINNUMACCESSPOINT_MACROCELLPIN) { + updatePinStats(aps, pin, inst_term); + // write to pa + const int pin_access_idx = unique_insts_.getPAIndex(inst_term->getInst()); + for (auto& ap : aps) { + pin->getPinAccess(pin_access_idx)->addAccessPoint(std::move(ap)); + } + return true; + } + if (is_io_pin && (int) aps.size() > 0) { + // IO term pin always only have one access + for (auto& ap : aps) { + pin->getPinAccess(0)->addAccessPoint(std::move(ap)); + } + return true; + } + return false; +} + +template +std::vector> +FlexPA::mergePinShapes(T* pin, frInstTerm* inst_term, const bool is_shrink) +{ + frInst* inst = nullptr; + if (inst_term) { + inst = inst_term->getInst(); + } + + dbTransform xform; + if (inst) { + xform = inst->getDBTransform(); + } + + frTechObject* tech = getDesign()->getTech(); + std::size_t num_layers = tech->getLayers().size(); + + std::vector layer_widths; + if (is_shrink) { + layer_widths.resize(num_layers, 0); + for (int i = 0; i < int(layer_widths.size()); i++) { + layer_widths[i] = tech->getLayer(i)->getWidth(); + } + } + + std::vector> pin_shapes(num_layers); + + for (auto& shape : pin->getFigs()) { + if (shape->typeId() == frcRect) { + auto obj = static_cast(shape.get()); + auto layer_num = obj->getLayerNum(); + auto layer = tech->getLayer(layer_num); + dbTechLayerDir dir = layer->getDir(); + if (layer->getType() != dbTechLayerType::ROUTING) { + continue; + } + Rect box = obj->getBBox(); + xform.apply(box); + gtl::rectangle_data rect( + box.xMin(), box.yMin(), box.xMax(), box.yMax()); + if (is_shrink) { + if (dir == dbTechLayerDir::HORIZONTAL) { + gtl::shrink(rect, gtl::VERTICAL, layer_widths[layer_num] / 2); + } else if (dir == dbTechLayerDir::VERTICAL) { + gtl::shrink(rect, gtl::HORIZONTAL, layer_widths[layer_num] / 2); + } + } + using boost::polygon::operators::operator+=; + pin_shapes[layer_num] += rect; + } else if (shape->typeId() == frcPolygon) { + auto obj = static_cast(shape.get()); + auto layer_num = obj->getLayerNum(); + std::vector> points; + // must be copied pts + for (Point pt : obj->getPoints()) { + xform.apply(pt); + points.emplace_back(pt.x(), pt.y()); + } + gtl::polygon_90_data poly; + poly.set(points.begin(), points.end()); + using boost::polygon::operators::operator+=; + pin_shapes[layer_num] += poly; + } else { + logger_->error(DRT, 67, "FlexPA mergePinShapes unsupported shape."); + } + } + return pin_shapes; +} + +// first create all access points with costs +template +int FlexPA::initPinAccess(T* pin, frInstTerm* inst_term) +{ + // aps are after xform + // before checkPoints, ap->hasAccess(dir) indicates whether to check drc + std::vector> aps; + std::set> apset; + bool is_std_cell_pin = false; + bool is_macro_cell_pin = false; + if (inst_term) { + is_std_cell_pin = isStdCell(inst_term->getInst()); + is_macro_cell_pin = isMacroCell(inst_term->getInst()); + } + + if (graphics_) { + std::set* inst_class = nullptr; + if (inst_term) { + inst_class = unique_insts_.getClass(inst_term->getInst()); + } + graphics_->startPin(pin, inst_term, inst_class); + } + + std::vector> pin_shapes + = mergePinShapes(pin, inst_term); + + for (auto upper : {frAccessPointEnum::OnGrid, + frAccessPointEnum::HalfGrid, + frAccessPointEnum::Center, + frAccessPointEnum::EncOpt, + frAccessPointEnum::NearbyGrid}) { + for (auto lower : {frAccessPointEnum::OnGrid, + frAccessPointEnum::HalfGrid, + frAccessPointEnum::Center, + frAccessPointEnum::EncOpt}) { + if (upper == frAccessPointEnum::NearbyGrid && !aps.empty()) { + // Only use NearbyGrid as a last resort (at least until + // nangate45/aes is resolved). + continue; + } + if (initPinAccessCostBounded( + aps, apset, pin_shapes, pin, inst_term, lower, upper)) { + return aps.size(); + } + } + } + + // inst_term aps are written back here if not early stopped + // IO term aps are are written back in initPinAccessCostBounded and always + // early stopped + updatePinStats(aps, pin, inst_term); + const int n_aps = aps.size(); + if (n_aps == 0) { + if (is_std_cell_pin) { + std_cell_pin_no_ap_cnt_++; + } + if (is_macro_cell_pin) { + macro_cell_pin_no_ap_cnt_++; + } + } else { + if (inst_term == nullptr) { + logger_->error(DRT, 254, "inst_term can not be nullptr"); + } + // write to pa + const int pin_access_idx = unique_insts_.getPAIndex(inst_term->getInst()); + for (auto& ap : aps) { + pin->getPinAccess(pin_access_idx)->addAccessPoint(std::move(ap)); + } + } + return n_aps; +} + +void FlexPA::initInstAccessPoints(frInst* inst) +{ + ProfileTask profile("PA:uniqueInstance"); + for (auto& inst_term : inst->getInstTerms()) { + // only do for normal and clock terms + if (isSkipInstTerm(inst_term.get())) { + continue; + } + int n_aps = 0; + for (auto& pin : inst_term->getTerm()->getPins()) { + n_aps += initPinAccess(pin.get(), inst_term.get()); + } + if (!n_aps) { + logger_->error(DRT, + 73, + "No access point for {}/{}.", + inst_term->getInst()->getName(), + inst_term->getTerm()->getName()); + } + } +} + +void FlexPA::initAllAccessPoints() +{ + ProfileTask profile("PA:point"); + int pin_count = 0; + + omp_set_num_threads(router_cfg_->MAX_THREADS); + ThreadException exception; + + const std::vector& unique = unique_insts_.getUnique(); +#pragma omp parallel for schedule(dynamic) + for (int i = 0; i < (int) unique.size(); i++) { // NOLINT + try { + frInst* inst = unique[i]; + + // only do for core and block cells + if (!isStdCell(inst) && !isMacroCell(inst)) { + continue; + } + + initInstAccessPoints(inst); + if (router_cfg_->VERBOSE <= 0) { + continue; + } + + int inst_terms_cnt = static_cast(inst->getInstTerms().size()); +#pragma omp critical + for (int i = 0; i < inst_terms_cnt; i++) { + pin_count++; + if (pin_count % (pin_count > 10000 ? 10000 : 1000) == 0) { + logger_->info(DRT, 76, " Complete {} pins.", pin_count); + } + } + } catch (...) { + exception.capture(); + } + } + exception.rethrow(); + + // PA for IO terms + if (target_insts_.empty()) { + omp_set_num_threads(router_cfg_->MAX_THREADS); +#pragma omp parallel for schedule(dynamic) + for (unsigned i = 0; // NOLINT + i < getDesign()->getTopBlock()->getTerms().size(); + i++) { + try { + auto& term = getDesign()->getTopBlock()->getTerms()[i]; + if (term->getType().isSupply()) { + continue; + } + auto net = term->getNet(); + if (!net || net->isSpecial()) { + continue; + } + int n_aps = 0; + for (auto& pin : term->getPins()) { + n_aps += initPinAccess(pin.get(), nullptr); + } + if (!n_aps) { + logger_->error( + DRT, 74, "No access point for PIN/{}.", term->getName()); + } + } catch (...) { + exception.capture(); + } + } + exception.rethrow(); + } + + if (router_cfg_->VERBOSE > 0) { + logger_->info(DRT, 78, " Complete {} pins.", pin_count); + } +} + +void FlexPA::revertAccessPoints() +{ + const auto& unique = unique_insts_.getUnique(); + for (auto& inst : unique) { + const dbTransform xform = inst->getTransform(); + const Point offset(xform.getOffset()); + dbTransform revertXform(Point(-offset.getX(), -offset.getY())); + + const auto pin_access_idx = unique_insts_.getPAIndex(inst); + for (auto& inst_term : inst->getInstTerms()) { + // if (isSkipInstTerm(inst_term.get())) { + // continue; + // } + + for (auto& pin : inst_term->getTerm()->getPins()) { + auto pin_access = pin->getPinAccess(pin_access_idx); + for (auto& access_point : pin_access->getAccessPoints()) { + Point unique_AP_point(access_point->getPoint()); + revertXform.apply(unique_AP_point); + access_point->setPoint(unique_AP_point); + for (auto& ps : access_point->getPathSegs()) { + Point begin = ps.getBeginPoint(); + Point end = ps.getEndPoint(); + revertXform.apply(begin); + revertXform.apply(end); + if (end < begin) { + Point tmp = begin; + begin = end; + end = tmp; + } + ps.setPoints(begin, end); + } + } + } + } + } +} + } \ No newline at end of file diff --git a/src/drt/src/pa/FlexPA_prep.cpp b/src/drt/src/pa/FlexPA_prep.cpp index d27cd789a37..659291a4916 100644 --- a/src/drt/src/pa/FlexPA_prep.cpp +++ b/src/drt/src/pa/FlexPA_prep.cpp @@ -63,75 +63,6 @@ bool FlexPA::isMacroCell(frInst* inst) || masterType == dbMasterType::RING); } -template -std::vector> -FlexPA::mergePinShapes(T* pin, frInstTerm* inst_term, const bool is_shrink) -{ - frInst* inst = nullptr; - if (inst_term) { - inst = inst_term->getInst(); - } - - dbTransform xform; - if (inst) { - xform = inst->getDBTransform(); - } - - frTechObject* tech = getDesign()->getTech(); - std::size_t num_layers = tech->getLayers().size(); - - std::vector layer_widths; - if (is_shrink) { - layer_widths.resize(num_layers, 0); - for (int i = 0; i < int(layer_widths.size()); i++) { - layer_widths[i] = tech->getLayer(i)->getWidth(); - } - } - - std::vector> pin_shapes(num_layers); - - for (auto& shape : pin->getFigs()) { - if (shape->typeId() == frcRect) { - auto obj = static_cast(shape.get()); - auto layer_num = obj->getLayerNum(); - auto layer = tech->getLayer(layer_num); - dbTechLayerDir dir = layer->getDir(); - if (layer->getType() != dbTechLayerType::ROUTING) { - continue; - } - Rect box = obj->getBBox(); - xform.apply(box); - gtl::rectangle_data rect( - box.xMin(), box.yMin(), box.xMax(), box.yMax()); - if (is_shrink) { - if (dir == dbTechLayerDir::HORIZONTAL) { - gtl::shrink(rect, gtl::VERTICAL, layer_widths[layer_num] / 2); - } else if (dir == dbTechLayerDir::VERTICAL) { - gtl::shrink(rect, gtl::HORIZONTAL, layer_widths[layer_num] / 2); - } - } - using boost::polygon::operators::operator+=; - pin_shapes[layer_num] += rect; - } else if (shape->typeId() == frcPolygon) { - auto obj = static_cast(shape.get()); - auto layer_num = obj->getLayerNum(); - std::vector> points; - // must be copied pts - for (Point pt : obj->getPoints()) { - xform.apply(pt); - points.emplace_back(pt.x(), pt.y()); - } - gtl::polygon_90_data poly; - poly.set(points.begin(), points.end()); - using boost::polygon::operators::operator+=; - pin_shapes[layer_num] += poly; - } else { - logger_->error(DRT, 67, "FlexPA mergePinShapes unsupported shape."); - } - } - return pin_shapes; -} - bool FlexPA::enclosesOnTrackPlanarAccess( const gtl::rectangle_data& rect, frLayerNum layer_num) @@ -178,251 +109,6 @@ bool FlexPA::enclosesOnTrackPlanarAccess( return true; } -template -void FlexPA::check_setAPsAccesses( - std::vector>& aps, - const std::vector>& pin_shapes, - T* pin, - frInstTerm* inst_term, - const bool& is_std_cell_pin) -{ - std::vector>> layer_polys( - pin_shapes.size()); - for (int i = 0; i < (int) pin_shapes.size(); i++) { - pin_shapes[i].get_polygons(layer_polys[i]); - } - bool has_access = false; - for (auto& ap : aps) { - const auto layer_num = ap->getLayerNum(); - check_addAccess(ap.get(), - pin_shapes[layer_num], - layer_polys[layer_num], - pin, - inst_term); - if (is_std_cell_pin) { - has_access |= ((layer_num == router_cfg_->VIA_ACCESS_LAYERNUM - && ap->hasAccess(frDirEnum::U)) - || (layer_num != router_cfg_->VIA_ACCESS_LAYERNUM - && ap->hasAccess())); - } else { - has_access |= ap->hasAccess(); - } - } - if (!has_access) { - for (auto& ap : aps) { - const auto layer_num = ap->getLayerNum(); - check_addAccess(ap.get(), - pin_shapes[layer_num], - layer_polys[layer_num], - pin, - inst_term, - true); - } - } -} - -template -void FlexPA::updatePinStats( - const std::vector>& tmp_aps, - T* pin, - frInstTerm* inst_term) -{ - bool is_std_cell_pin = false; - bool is_macro_cell_pin = false; - if (inst_term) { - is_std_cell_pin = isStdCell(inst_term->getInst()); - is_macro_cell_pin = isMacroCell(inst_term->getInst()); - } - for (auto& ap : tmp_aps) { - if (ap->hasAccess(frDirEnum::W) || ap->hasAccess(frDirEnum::E) - || ap->hasAccess(frDirEnum::S) || ap->hasAccess(frDirEnum::N)) { - if (is_std_cell_pin) { -#pragma omp atomic - std_cell_pin_valid_planar_ap_cnt_++; - } - if (is_macro_cell_pin) { -#pragma omp atomic - macro_cell_pin_valid_planar_ap_cnt_++; - } - } - if (ap->hasAccess(frDirEnum::U)) { - if (is_std_cell_pin) { -#pragma omp atomic - std_cell_pin_valid_via_ap_cnt_++; - } - if (is_macro_cell_pin) { -#pragma omp atomic - macro_cell_pin_valid_via_ap_cnt_++; - } - } - } -} - -template -bool FlexPA::initPinAccessCostBounded( - std::vector>& aps, - std::set>& apset, - std::vector>& pin_shapes, - T* pin, - frInstTerm* inst_term, - const frAccessPointEnum lower_type, - const frAccessPointEnum upper_type) -{ - bool is_std_cell_pin = false; - bool is_macro_cell_pin = false; - if (inst_term) { - is_std_cell_pin = isStdCell(inst_term->getInst()); - is_macro_cell_pin = isMacroCell(inst_term->getInst()); - } - const bool is_io_pin = (inst_term == nullptr); - std::vector> tmp_aps; - genAPsFromPinShapes( - tmp_aps, apset, pin, inst_term, pin_shapes, lower_type, upper_type); - check_setAPsAccesses(tmp_aps, pin_shapes, pin, inst_term, is_std_cell_pin); - if (is_std_cell_pin) { -#pragma omp atomic - std_cell_pin_gen_ap_cnt_ += tmp_aps.size(); - } - if (is_macro_cell_pin) { -#pragma omp atomic - macro_cell_pin_gen_ap_cnt_ += tmp_aps.size(); - } - if (graphics_) { - graphics_->setAPs(tmp_aps, lower_type, upper_type); - } - for (auto& ap : tmp_aps) { - // for stdcell, add (i) planar access if layer_num != VIA_ACCESS_LAYERNUM, - // and (ii) access if exist access for macro, allow pure planar ap - if (is_std_cell_pin) { - const auto layer_num = ap->getLayerNum(); - if ((layer_num == router_cfg_->VIA_ACCESS_LAYERNUM - && ap->hasAccess(frDirEnum::U)) - || (layer_num != router_cfg_->VIA_ACCESS_LAYERNUM - && ap->hasAccess())) { - aps.push_back(std::move(ap)); - } - } else if ((is_macro_cell_pin || is_io_pin) && ap->hasAccess()) { - aps.push_back(std::move(ap)); - } - } - int n_sparse_access_points = (int) aps.size(); - Rect tbx; - for (int i = 0; i < (int) aps.size(); - i++) { // not perfect but will do the job - int r = design_->getTech()->getLayer(aps[i]->getLayerNum())->getWidth() / 2; - tbx.init( - aps[i]->x() - r, aps[i]->y() - r, aps[i]->x() + r, aps[i]->y() + r); - for (int j = i + 1; j < (int) aps.size(); j++) { - if (aps[i]->getLayerNum() == aps[j]->getLayerNum() - && tbx.intersects(aps[j]->getPoint())) { - n_sparse_access_points--; - break; - } - } - } - if (is_std_cell_pin - && n_sparse_access_points >= router_cfg_->MINNUMACCESSPOINT_STDCELLPIN) { - updatePinStats(aps, pin, inst_term); - // write to pa - const int pin_access_idx = unique_insts_.getPAIndex(inst_term->getInst()); - for (auto& ap : aps) { - pin->getPinAccess(pin_access_idx)->addAccessPoint(std::move(ap)); - } - return true; - } - if (is_macro_cell_pin - && n_sparse_access_points - >= router_cfg_->MINNUMACCESSPOINT_MACROCELLPIN) { - updatePinStats(aps, pin, inst_term); - // write to pa - const int pin_access_idx = unique_insts_.getPAIndex(inst_term->getInst()); - for (auto& ap : aps) { - pin->getPinAccess(pin_access_idx)->addAccessPoint(std::move(ap)); - } - return true; - } - if (is_io_pin && (int) aps.size() > 0) { - // IO term pin always only have one access - for (auto& ap : aps) { - pin->getPinAccess(0)->addAccessPoint(std::move(ap)); - } - return true; - } - return false; -} - -// first create all access points with costs -template -int FlexPA::initPinAccess(T* pin, frInstTerm* inst_term) -{ - // aps are after xform - // before checkPoints, ap->hasAccess(dir) indicates whether to check drc - std::vector> aps; - std::set> apset; - bool is_std_cell_pin = false; - bool is_macro_cell_pin = false; - if (inst_term) { - is_std_cell_pin = isStdCell(inst_term->getInst()); - is_macro_cell_pin = isMacroCell(inst_term->getInst()); - } - - if (graphics_) { - std::set* inst_class = nullptr; - if (inst_term) { - inst_class = unique_insts_.getClass(inst_term->getInst()); - } - graphics_->startPin(pin, inst_term, inst_class); - } - - std::vector> pin_shapes - = mergePinShapes(pin, inst_term); - - for (auto upper : {frAccessPointEnum::OnGrid, - frAccessPointEnum::HalfGrid, - frAccessPointEnum::Center, - frAccessPointEnum::EncOpt, - frAccessPointEnum::NearbyGrid}) { - for (auto lower : {frAccessPointEnum::OnGrid, - frAccessPointEnum::HalfGrid, - frAccessPointEnum::Center, - frAccessPointEnum::EncOpt}) { - if (upper == frAccessPointEnum::NearbyGrid && !aps.empty()) { - // Only use NearbyGrid as a last resort (at least until - // nangate45/aes is resolved). - continue; - } - if (initPinAccessCostBounded( - aps, apset, pin_shapes, pin, inst_term, lower, upper)) { - return aps.size(); - } - } - } - - // inst_term aps are written back here if not early stopped - // IO term aps are are written back in initPinAccessCostBounded and always - // early stopped - updatePinStats(aps, pin, inst_term); - const int n_aps = aps.size(); - if (n_aps == 0) { - if (is_std_cell_pin) { - std_cell_pin_no_ap_cnt_++; - } - if (is_macro_cell_pin) { - macro_cell_pin_no_ap_cnt_++; - } - } else { - if (inst_term == nullptr) { - logger_->error(DRT, 254, "inst_term can not be nullptr"); - } - // write to pa - const int pin_access_idx = unique_insts_.getPAIndex(inst_term->getInst()); - for (auto& ap : aps) { - pin->getPinAccess(pin_access_idx)->addAccessPoint(std::move(ap)); - } - } - return n_aps; -} - static inline void serializePatterns( const std::vector>>& patterns, @@ -435,102 +121,6 @@ static inline void serializePatterns( file.close(); } -void FlexPA::initInstAccessPoints(frInst* inst) -{ - ProfileTask profile("PA:uniqueInstance"); - for (auto& inst_term : inst->getInstTerms()) { - // only do for normal and clock terms - if (isSkipInstTerm(inst_term.get())) { - continue; - } - int n_aps = 0; - for (auto& pin : inst_term->getTerm()->getPins()) { - n_aps += initPinAccess(pin.get(), inst_term.get()); - } - if (!n_aps) { - logger_->error(DRT, - 73, - "No access point for {}/{}.", - inst_term->getInst()->getName(), - inst_term->getTerm()->getName()); - } - } -} - -void FlexPA::initAllAccessPoints() -{ - ProfileTask profile("PA:point"); - int pin_count = 0; - - omp_set_num_threads(router_cfg_->MAX_THREADS); - ThreadException exception; - - const std::vector& unique = unique_insts_.getUnique(); -#pragma omp parallel for schedule(dynamic) - for (int i = 0; i < (int) unique.size(); i++) { // NOLINT - try { - frInst* inst = unique[i]; - - // only do for core and block cells - if (!isStdCell(inst) && !isMacroCell(inst)) { - continue; - } - - initInstAccessPoints(inst); - if (router_cfg_->VERBOSE <= 0) { - continue; - } - - int inst_terms_cnt = static_cast(inst->getInstTerms().size()); -#pragma omp critical - for (int i = 0; i < inst_terms_cnt; i++) { - pin_count++; - if (pin_count % (pin_count > 10000 ? 10000 : 1000) == 0) { - logger_->info(DRT, 76, " Complete {} pins.", pin_count); - } - } - } catch (...) { - exception.capture(); - } - } - exception.rethrow(); - - // PA for IO terms - if (target_insts_.empty()) { - omp_set_num_threads(router_cfg_->MAX_THREADS); -#pragma omp parallel for schedule(dynamic) - for (unsigned i = 0; // NOLINT - i < getDesign()->getTopBlock()->getTerms().size(); - i++) { - try { - auto& term = getDesign()->getTopBlock()->getTerms()[i]; - if (term->getType().isSupply()) { - continue; - } - auto net = term->getNet(); - if (!net || net->isSpecial()) { - continue; - } - int n_aps = 0; - for (auto& pin : term->getPins()) { - n_aps += initPinAccess(pin.get(), nullptr); - } - if (!n_aps) { - logger_->error( - DRT, 74, "No access point for PIN/{}.", term->getName()); - } - } catch (...) { - exception.capture(); - } - } - exception.rethrow(); - } - - if (router_cfg_->VERBOSE > 0) { - logger_->info(DRT, 78, " Complete {} pins.", pin_count); - } -} - void FlexPA::prepPattern() { ProfileTask profile("PA:pattern"); @@ -646,44 +236,6 @@ void FlexPA::prepPattern() prepPatternInstRows(std::move(inst_rows)); } -void FlexPA::revertAccessPoints() -{ - const auto& unique = unique_insts_.getUnique(); - for (auto& inst : unique) { - const dbTransform xform = inst->getTransform(); - const Point offset(xform.getOffset()); - dbTransform revertXform(Point(-offset.getX(), -offset.getY())); - - const auto pin_access_idx = unique_insts_.getPAIndex(inst); - for (auto& inst_term : inst->getInstTerms()) { - // if (isSkipInstTerm(inst_term.get())) { - // continue; - // } - - for (auto& pin : inst_term->getTerm()->getPins()) { - auto pin_access = pin->getPinAccess(pin_access_idx); - for (auto& access_point : pin_access->getAccessPoints()) { - Point unique_AP_point(access_point->getPoint()); - revertXform.apply(unique_AP_point); - access_point->setPoint(unique_AP_point); - for (auto& ps : access_point->getPathSegs()) { - Point begin = ps.getBeginPoint(); - Point end = ps.getEndPoint(); - revertXform.apply(begin); - revertXform.apply(end); - if (end < begin) { - Point tmp = begin; - begin = end; - end = tmp; - } - ps.setPoints(begin, end); - } - } - } - } - } -} - void FlexPA::getInsts(std::vector& insts) { std::set target_frinsts; From 8e1dbab883e048a68a688dcf6f70dbc8d7b2df07 Mon Sep 17 00:00:00 2001 From: bernardo Date: Sun, 15 Dec 2024 00:18:38 +0000 Subject: [PATCH 57/98] move prepPatternInst Signed-off-by: bernardo --- src/drt/src/pa/FlexPA_acc_pattern.cpp | 52 +++++++++++++++++++++++++++ src/drt/src/pa/FlexPA_prep.cpp | 52 --------------------------- 2 files changed, 52 insertions(+), 52 deletions(-) diff --git a/src/drt/src/pa/FlexPA_acc_pattern.cpp b/src/drt/src/pa/FlexPA_acc_pattern.cpp index 207c8b028f0..c917782935e 100644 --- a/src/drt/src/pa/FlexPA_acc_pattern.cpp +++ b/src/drt/src/pa/FlexPA_acc_pattern.cpp @@ -49,6 +49,58 @@ namespace drt { using utl::ThreadException; +// the input inst must be unique instance +int FlexPA::prepPatternInst(frInst* inst, + const int curr_unique_inst_idx, + const double x_weight) +{ + std::vector>> pins; + // TODO: add assert in case input inst is not unique inst + int pin_access_idx = unique_insts_.getPAIndex(inst); + for (auto& inst_term : inst->getInstTerms()) { + if (isSkipInstTerm(inst_term.get())) { + continue; + } + int n_aps = 0; + for (auto& pin : inst_term->getTerm()->getPins()) { + // container of access points + auto pin_access = pin->getPinAccess(pin_access_idx); + int sum_x_coord = 0; + int sum_y_coord = 0; + int cnt = 0; + // get avg x coord for sort + for (auto& access_point : pin_access->getAccessPoints()) { + sum_x_coord += access_point->getPoint().x(); + sum_y_coord += access_point->getPoint().y(); + cnt++; + } + n_aps += cnt; + if (cnt != 0) { + const double coord + = (x_weight * sum_x_coord + (1.0 - x_weight) * sum_y_coord) / cnt; + pins.push_back({(int) std::round(coord), {pin.get(), inst_term.get()}}); + } + } + if (n_aps == 0 && !inst_term->getTerm()->getPins().empty()) { + logger_->error(DRT, 86, "Pin does not have an access point."); + } + } + std::sort(pins.begin(), + pins.end(), + [](const std::pair>& lhs, + const std::pair>& rhs) { + return lhs.first < rhs.first; + }); + + std::vector> pin_inst_term_pairs; + pin_inst_term_pairs.reserve(pins.size()); + for (auto& [x, m] : pins) { + pin_inst_term_pairs.push_back(m); + } + + return genPatterns(pin_inst_term_pairs, curr_unique_inst_idx); +} + int FlexPA::genPatterns( const std::vector>& pins, int curr_unique_inst_idx) diff --git a/src/drt/src/pa/FlexPA_prep.cpp b/src/drt/src/pa/FlexPA_prep.cpp index 659291a4916..eb74ccd09fb 100644 --- a/src/drt/src/pa/FlexPA_prep.cpp +++ b/src/drt/src/pa/FlexPA_prep.cpp @@ -295,56 +295,4 @@ bool FlexPA::isSkipInstTerm(frInstTerm* in) return skip_unique_inst_term_.at({inst_class, in->getTerm()}); } -// the input inst must be unique instance -int FlexPA::prepPatternInst(frInst* inst, - const int curr_unique_inst_idx, - const double x_weight) -{ - std::vector>> pins; - // TODO: add assert in case input inst is not unique inst - int pin_access_idx = unique_insts_.getPAIndex(inst); - for (auto& inst_term : inst->getInstTerms()) { - if (isSkipInstTerm(inst_term.get())) { - continue; - } - int n_aps = 0; - for (auto& pin : inst_term->getTerm()->getPins()) { - // container of access points - auto pin_access = pin->getPinAccess(pin_access_idx); - int sum_x_coord = 0; - int sum_y_coord = 0; - int cnt = 0; - // get avg x coord for sort - for (auto& access_point : pin_access->getAccessPoints()) { - sum_x_coord += access_point->getPoint().x(); - sum_y_coord += access_point->getPoint().y(); - cnt++; - } - n_aps += cnt; - if (cnt != 0) { - const double coord - = (x_weight * sum_x_coord + (1.0 - x_weight) * sum_y_coord) / cnt; - pins.push_back({(int) std::round(coord), {pin.get(), inst_term.get()}}); - } - } - if (n_aps == 0 && !inst_term->getTerm()->getPins().empty()) { - logger_->error(DRT, 86, "Pin does not have an access point."); - } - } - std::sort(pins.begin(), - pins.end(), - [](const std::pair>& lhs, - const std::pair>& rhs) { - return lhs.first < rhs.first; - }); - - std::vector> pin_inst_term_pairs; - pin_inst_term_pairs.reserve(pins.size()); - for (auto& [x, m] : pins) { - pin_inst_term_pairs.push_back(m); - } - - return genPatterns(pin_inst_term_pairs, curr_unique_inst_idx); -} - } // namespace drt From 61d8e6a446cbeafab832f991e666ef5bda083f5a Mon Sep 17 00:00:00 2001 From: bernardo Date: Sun, 15 Dec 2024 00:20:14 +0000 Subject: [PATCH 58/98] move prepPattern Signed-off-by: bernardo --- src/drt/src/pa/FlexPA_acc_pattern.cpp | 127 ++++++++++++++++++++++++++ src/drt/src/pa/FlexPA_prep.cpp | 127 -------------------------- 2 files changed, 127 insertions(+), 127 deletions(-) diff --git a/src/drt/src/pa/FlexPA_acc_pattern.cpp b/src/drt/src/pa/FlexPA_acc_pattern.cpp index c917782935e..6d9f5b7cd66 100644 --- a/src/drt/src/pa/FlexPA_acc_pattern.cpp +++ b/src/drt/src/pa/FlexPA_acc_pattern.cpp @@ -49,6 +49,133 @@ namespace drt { using utl::ThreadException; +static inline void serializePatterns( + const std::vector>>& + patterns, + const std::string& file_name) +{ + std::ofstream file(file_name.c_str()); + frOArchive ar(file); + registerTypes(ar); + ar << patterns; + file.close(); +} + +void FlexPA::prepPattern() +{ + ProfileTask profile("PA:pattern"); + + const auto& unique = unique_insts_.getUnique(); + + // revert access points to origin + unique_inst_patterns_.resize(unique.size()); + + int cnt = 0; + + omp_set_num_threads(router_cfg_->MAX_THREADS); + ThreadException exception; +#pragma omp parallel for schedule(dynamic) + for (int curr_unique_inst_idx = 0; curr_unique_inst_idx < (int) unique.size(); + curr_unique_inst_idx++) { + try { + auto& inst = unique[curr_unique_inst_idx]; + // only do for core and block cells + // TODO the above comment says "block cells" but that's not what the code + // does? + if (!isStdCell(inst)) { + continue; + } + + int num_valid_pattern = prepPatternInst(inst, curr_unique_inst_idx, 1.0); + + if (num_valid_pattern == 0) { + // In FAx1_ASAP7_75t_R (in asap7) the pins are mostly horizontal + // and sorting in X works poorly. So we try again sorting in Y. + num_valid_pattern = prepPatternInst(inst, curr_unique_inst_idx, 0.0); + if (num_valid_pattern == 0) { + logger_->warn( + DRT, + 87, + "No valid pattern for unique instance {}, master is {}.", + inst->getName(), + inst->getMaster()->getName()); + } + } +#pragma omp critical + { + cnt++; + if (router_cfg_->VERBOSE > 0) { + if (cnt % (cnt > 1000 ? 1000 : 100) == 0) { + logger_->info(DRT, 79, " Complete {} unique inst patterns.", cnt); + } + } + } + } catch (...) { + exception.capture(); + } + } + exception.rethrow(); + if (router_cfg_->VERBOSE > 0) { + logger_->info(DRT, 81, " Complete {} unique inst patterns.", cnt); + } + if (isDistributed()) { + dst::JobMessage msg(dst::JobMessage::PIN_ACCESS, + dst::JobMessage::BROADCAST), + result; + std::unique_ptr uDesc + = std::make_unique(); + std::string patterns_file = fmt::format("{}/patterns.bin", shared_vol_); + serializePatterns(unique_inst_patterns_, patterns_file); + uDesc->setPath(patterns_file); + uDesc->setType(PinAccessJobDescription::UPDATE_PATTERNS); + msg.setJobDescription(std::move(uDesc)); + const bool ok + = dist_->sendJob(msg, remote_host_.c_str(), remote_port_, result); + if (!ok) { + logger_->error( + utl::DRT, 330, "Error sending UPDATE_PATTERNS Job to cloud"); + } + } + + // prep pattern for each row + std::vector insts; + std::vector> inst_rows; + std::vector row_insts; + + auto instLocComp = [](frInst* const& a, frInst* const& b) { + const Point originA = a->getOrigin(); + const Point originB = b->getOrigin(); + if (originA.y() == originB.y()) { + return (originA.x() < originB.x()); + } + return (originA.y() < originB.y()); + }; + + getInsts(insts); + std::sort(insts.begin(), insts.end(), instLocComp); + + // gen rows of insts + int prev_y_coord = INT_MIN; + int prev_x_end_coord = INT_MIN; + for (auto inst : insts) { + Point origin = inst->getOrigin(); + if (origin.y() != prev_y_coord || origin.x() > prev_x_end_coord) { + if (!row_insts.empty()) { + inst_rows.push_back(row_insts); + row_insts.clear(); + } + } + row_insts.push_back(inst); + prev_y_coord = origin.y(); + Rect inst_boundary_box = inst->getBoundaryBBox(); + prev_x_end_coord = inst_boundary_box.xMax(); + } + if (!row_insts.empty()) { + inst_rows.push_back(row_insts); + } + prepPatternInstRows(std::move(inst_rows)); +} + // the input inst must be unique instance int FlexPA::prepPatternInst(frInst* inst, const int curr_unique_inst_idx, diff --git a/src/drt/src/pa/FlexPA_prep.cpp b/src/drt/src/pa/FlexPA_prep.cpp index eb74ccd09fb..d3b5b7817ea 100644 --- a/src/drt/src/pa/FlexPA_prep.cpp +++ b/src/drt/src/pa/FlexPA_prep.cpp @@ -109,133 +109,6 @@ bool FlexPA::enclosesOnTrackPlanarAccess( return true; } -static inline void serializePatterns( - const std::vector>>& - patterns, - const std::string& file_name) -{ - std::ofstream file(file_name.c_str()); - frOArchive ar(file); - registerTypes(ar); - ar << patterns; - file.close(); -} - -void FlexPA::prepPattern() -{ - ProfileTask profile("PA:pattern"); - - const auto& unique = unique_insts_.getUnique(); - - // revert access points to origin - unique_inst_patterns_.resize(unique.size()); - - int cnt = 0; - - omp_set_num_threads(router_cfg_->MAX_THREADS); - ThreadException exception; -#pragma omp parallel for schedule(dynamic) - for (int curr_unique_inst_idx = 0; curr_unique_inst_idx < (int) unique.size(); - curr_unique_inst_idx++) { - try { - auto& inst = unique[curr_unique_inst_idx]; - // only do for core and block cells - // TODO the above comment says "block cells" but that's not what the code - // does? - if (!isStdCell(inst)) { - continue; - } - - int num_valid_pattern = prepPatternInst(inst, curr_unique_inst_idx, 1.0); - - if (num_valid_pattern == 0) { - // In FAx1_ASAP7_75t_R (in asap7) the pins are mostly horizontal - // and sorting in X works poorly. So we try again sorting in Y. - num_valid_pattern = prepPatternInst(inst, curr_unique_inst_idx, 0.0); - if (num_valid_pattern == 0) { - logger_->warn( - DRT, - 87, - "No valid pattern for unique instance {}, master is {}.", - inst->getName(), - inst->getMaster()->getName()); - } - } -#pragma omp critical - { - cnt++; - if (router_cfg_->VERBOSE > 0) { - if (cnt % (cnt > 1000 ? 1000 : 100) == 0) { - logger_->info(DRT, 79, " Complete {} unique inst patterns.", cnt); - } - } - } - } catch (...) { - exception.capture(); - } - } - exception.rethrow(); - if (router_cfg_->VERBOSE > 0) { - logger_->info(DRT, 81, " Complete {} unique inst patterns.", cnt); - } - if (isDistributed()) { - dst::JobMessage msg(dst::JobMessage::PIN_ACCESS, - dst::JobMessage::BROADCAST), - result; - std::unique_ptr uDesc - = std::make_unique(); - std::string patterns_file = fmt::format("{}/patterns.bin", shared_vol_); - serializePatterns(unique_inst_patterns_, patterns_file); - uDesc->setPath(patterns_file); - uDesc->setType(PinAccessJobDescription::UPDATE_PATTERNS); - msg.setJobDescription(std::move(uDesc)); - const bool ok - = dist_->sendJob(msg, remote_host_.c_str(), remote_port_, result); - if (!ok) { - logger_->error( - utl::DRT, 330, "Error sending UPDATE_PATTERNS Job to cloud"); - } - } - - // prep pattern for each row - std::vector insts; - std::vector> inst_rows; - std::vector row_insts; - - auto instLocComp = [](frInst* const& a, frInst* const& b) { - const Point originA = a->getOrigin(); - const Point originB = b->getOrigin(); - if (originA.y() == originB.y()) { - return (originA.x() < originB.x()); - } - return (originA.y() < originB.y()); - }; - - getInsts(insts); - std::sort(insts.begin(), insts.end(), instLocComp); - - // gen rows of insts - int prev_y_coord = INT_MIN; - int prev_x_end_coord = INT_MIN; - for (auto inst : insts) { - Point origin = inst->getOrigin(); - if (origin.y() != prev_y_coord || origin.x() > prev_x_end_coord) { - if (!row_insts.empty()) { - inst_rows.push_back(row_insts); - row_insts.clear(); - } - } - row_insts.push_back(inst); - prev_y_coord = origin.y(); - Rect inst_boundary_box = inst->getBoundaryBBox(); - prev_x_end_coord = inst_boundary_box.xMax(); - } - if (!row_insts.empty()) { - inst_rows.push_back(row_insts); - } - prepPatternInstRows(std::move(inst_rows)); -} - void FlexPA::getInsts(std::vector& insts) { std::set target_frinsts; From 3cedd47548896463ac310f5fc48637a0041cb6b0 Mon Sep 17 00:00:00 2001 From: bernardo Date: Sun, 15 Dec 2024 00:23:12 +0000 Subject: [PATCH 59/98] move serializePatterns Signed-off-by: bernardo move isSkipInstTerm Signed-off-by: bernardo move isStdCell and isMacroCell Signed-off-by: bernardo --- src/drt/src/pa/FlexPA.cpp | 43 ++++++++++++++++ src/drt/src/pa/FlexPA_acc_pattern.cpp | 30 +++++++++++ src/drt/src/pa/FlexPA_prep.cpp | 73 --------------------------- 3 files changed, 73 insertions(+), 73 deletions(-) diff --git a/src/drt/src/pa/FlexPA.cpp b/src/drt/src/pa/FlexPA.cpp index d56c830f915..d716652603e 100644 --- a/src/drt/src/pa/FlexPA.cpp +++ b/src/drt/src/pa/FlexPA.cpp @@ -176,6 +176,49 @@ void FlexPA::setDistributed(const std::string& rhost, cloud_sz_ = cloud_sz; } +// Skip power pins, pins connected to special nets, and dangling pins +// (since we won't route these). +// +// Checks only this inst_term and not an equivalent ones. This +// is a helper to isSkipInstTerm and initSkipInstTerm. +bool FlexPA::isSkipInstTermLocal(frInstTerm* in) +{ + auto term = in->getTerm(); + if (term->getType().isSupply()) { + return true; + } + auto in_net = in->getNet(); + if (in_net && !in_net->isSpecial()) { + return false; + } + return true; +} + +bool FlexPA::isSkipInstTerm(frInstTerm* in) +{ + auto inst_class = unique_insts_.getClass(in->getInst()); + if (inst_class == nullptr) { + return isSkipInstTermLocal(in); + } + + // This should be already computed in initSkipInstTerm() + return skip_unique_inst_term_.at({inst_class, in->getTerm()}); +} + +// TODO there should be a better way to get this info by getting the master +// terms from OpenDB +bool FlexPA::isStdCell(frInst* inst) +{ + return inst->getMaster()->getMasterType().isCore(); +} + +bool FlexPA::isMacroCell(frInst* inst) +{ + dbMasterType masterType = inst->getMaster()->getMasterType(); + return (masterType.isBlock() || masterType.isPad() + || masterType == dbMasterType::RING); +} + int FlexPA::main() { ProfileTask profile("PA:main"); diff --git a/src/drt/src/pa/FlexPA_acc_pattern.cpp b/src/drt/src/pa/FlexPA_acc_pattern.cpp index 6d9f5b7cd66..a0cc3b55ad8 100644 --- a/src/drt/src/pa/FlexPA_acc_pattern.cpp +++ b/src/drt/src/pa/FlexPA_acc_pattern.cpp @@ -61,6 +61,36 @@ static inline void serializePatterns( file.close(); } +void FlexPA::getInsts(std::vector& insts) +{ + std::set target_frinsts; + for (auto inst : target_insts_) { + target_frinsts.insert(design_->getTopBlock()->findInst(inst->getName())); + } + for (auto& inst : design_->getTopBlock()->getInsts()) { + if (!target_insts_.empty() + && target_frinsts.find(inst.get()) == target_frinsts.end()) { + continue; + } + if (!unique_insts_.hasUnique(inst.get())) { + continue; + } + if (!isStdCell(inst.get())) { + continue; + } + bool is_skip = true; + for (auto& inst_term : inst->getInstTerms()) { + if (!isSkipInstTerm(inst_term.get())) { + is_skip = false; + break; + } + } + if (!is_skip) { + insts.push_back(inst.get()); + } + } +} + void FlexPA::prepPattern() { ProfileTask profile("PA:pattern"); diff --git a/src/drt/src/pa/FlexPA_prep.cpp b/src/drt/src/pa/FlexPA_prep.cpp index d3b5b7817ea..5c2c59ac8bb 100644 --- a/src/drt/src/pa/FlexPA_prep.cpp +++ b/src/drt/src/pa/FlexPA_prep.cpp @@ -49,20 +49,6 @@ namespace drt { using utl::ThreadException; -// TODO there should be a better way to get this info by getting the master -// terms from OpenDB -bool FlexPA::isStdCell(frInst* inst) -{ - return inst->getMaster()->getMasterType().isCore(); -} - -bool FlexPA::isMacroCell(frInst* inst) -{ - dbMasterType masterType = inst->getMaster()->getMasterType(); - return (masterType.isBlock() || masterType.isPad() - || masterType == dbMasterType::RING); -} - bool FlexPA::enclosesOnTrackPlanarAccess( const gtl::rectangle_data& rect, frLayerNum layer_num) @@ -109,63 +95,4 @@ bool FlexPA::enclosesOnTrackPlanarAccess( return true; } -void FlexPA::getInsts(std::vector& insts) -{ - std::set target_frinsts; - for (auto inst : target_insts_) { - target_frinsts.insert(design_->getTopBlock()->findInst(inst->getName())); - } - for (auto& inst : design_->getTopBlock()->getInsts()) { - if (!target_insts_.empty() - && target_frinsts.find(inst.get()) == target_frinsts.end()) { - continue; - } - if (!unique_insts_.hasUnique(inst.get())) { - continue; - } - if (!isStdCell(inst.get())) { - continue; - } - bool is_skip = true; - for (auto& inst_term : inst->getInstTerms()) { - if (!isSkipInstTerm(inst_term.get())) { - is_skip = false; - break; - } - } - if (!is_skip) { - insts.push_back(inst.get()); - } - } -} - -// Skip power pins, pins connected to special nets, and dangling pins -// (since we won't route these). -// -// Checks only this inst_term and not an equivalent ones. This -// is a helper to isSkipInstTerm and initSkipInstTerm. -bool FlexPA::isSkipInstTermLocal(frInstTerm* in) -{ - auto term = in->getTerm(); - if (term->getType().isSupply()) { - return true; - } - auto in_net = in->getNet(); - if (in_net && !in_net->isSpecial()) { - return false; - } - return true; -} - -bool FlexPA::isSkipInstTerm(frInstTerm* in) -{ - auto inst_class = unique_insts_.getClass(in->getInst()); - if (inst_class == nullptr) { - return isSkipInstTermLocal(in); - } - - // This should be already computed in initSkipInstTerm() - return skip_unique_inst_term_.at({inst_class, in->getTerm()}); -} - } // namespace drt From a71b8de04c55e7ef2dfa7cf2b9ea76f25640b89a Mon Sep 17 00:00:00 2001 From: bernardo Date: Sun, 15 Dec 2024 00:32:49 +0000 Subject: [PATCH 60/98] delete FlexPA_prep.cpp Signed-off-by: bernardo clang-format Signed-off-by: bernardo --- src/drt/CMakeLists.txt | 1 - src/drt/src/pa/FlexPA_acc_pattern.cpp | 2 +- src/drt/src/pa/FlexPA_acc_point.cpp | 12 +--- src/drt/src/pa/FlexPA_prep.cpp | 98 --------------------------- 4 files changed, 2 insertions(+), 111 deletions(-) delete mode 100644 src/drt/src/pa/FlexPA_prep.cpp diff --git a/src/drt/CMakeLists.txt b/src/drt/CMakeLists.txt index 3ccba7f51cd..b9daea54785 100644 --- a/src/drt/CMakeLists.txt +++ b/src/drt/CMakeLists.txt @@ -121,7 +121,6 @@ target_sources(drt src/io/io_parser_helper.cpp src/pa/FlexPA_init.cpp src/pa/FlexPA.cpp - src/pa/FlexPA_prep.cpp src/pa/FlexPA_acc_point.cpp src/pa/FlexPA_acc_pattern.cpp src/pa/FlexPA_row_pattern.cpp diff --git a/src/drt/src/pa/FlexPA_acc_pattern.cpp b/src/drt/src/pa/FlexPA_acc_pattern.cpp index a0cc3b55ad8..f32b4380a51 100644 --- a/src/drt/src/pa/FlexPA_acc_pattern.cpp +++ b/src/drt/src/pa/FlexPA_acc_pattern.cpp @@ -892,4 +892,4 @@ int FlexPA::getFlatEdgeIdx(const int prev_idx_1, return ((prev_idx_1 + 1) * idx_2_dim + prev_idx_2) * idx_2_dim + curr_idx_2; } -} \ No newline at end of file +} // namespace drt \ No newline at end of file diff --git a/src/drt/src/pa/FlexPA_acc_point.cpp b/src/drt/src/pa/FlexPA_acc_point.cpp index 291ff9d46cc..1a8726d7b9c 100644 --- a/src/drt/src/pa/FlexPA_acc_point.cpp +++ b/src/drt/src/pa/FlexPA_acc_point.cpp @@ -27,21 +27,11 @@ */ #include -// #include -// #include -// #include -// #include #include "FlexPA.h" #include "FlexPA_graphics.h" -// #include "db/infra/frTime.h" -// #include "distributed/PinAccessJobDescription.h" -// #include "distributed/frArchive.h" -// #include "dst/Distributed.h" -// #include "dst/JobMessage.h" #include "frProfileTask.h" #include "gc/FlexGC.h" -// #include "serialization.h" #include "utl/exception.h" namespace drt { @@ -1524,4 +1514,4 @@ void FlexPA::revertAccessPoints() } } -} \ No newline at end of file +} // namespace drt \ No newline at end of file diff --git a/src/drt/src/pa/FlexPA_prep.cpp b/src/drt/src/pa/FlexPA_prep.cpp deleted file mode 100644 index 5c2c59ac8bb..00000000000 --- a/src/drt/src/pa/FlexPA_prep.cpp +++ /dev/null @@ -1,98 +0,0 @@ -/* Authors: Lutong Wang and Bangqi Xu */ -/* - * Copyright (c) 2019, The Regents of the University of California - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of the University nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include - -#include "FlexPA.h" -#include "FlexPA_graphics.h" -#include "db/infra/frTime.h" -#include "distributed/PinAccessJobDescription.h" -#include "distributed/frArchive.h" -#include "dst/Distributed.h" -#include "dst/JobMessage.h" -#include "frProfileTask.h" -#include "gc/FlexGC.h" -#include "serialization.h" -#include "utl/exception.h" - -namespace drt { - -using utl::ThreadException; - -bool FlexPA::enclosesOnTrackPlanarAccess( - const gtl::rectangle_data& rect, - frLayerNum layer_num) -{ - frCoord low, high; - frLayer* layer = getDesign()->getTech()->getLayer(layer_num); - if (layer->isHorizontal()) { - low = gtl::yl(rect); - high = gtl::yh(rect); - } else if (layer->isVertical()) { - low = gtl::xl(rect); - high = gtl::xh(rect); - } else { - logger_->error( - DRT, - 1003, - "enclosesPlanarAccess: layer is neither vertical or horizontal"); - } - const auto& tracks = track_coords_[layer_num]; - const auto low_track = tracks.lower_bound(low); - if (low_track == tracks.end()) { - logger_->error(DRT, 1004, "enclosesPlanarAccess: low track not found"); - } - if (low_track->first > high) { - return false; - } - auto high_track = tracks.lower_bound(high); - if (high_track != tracks.end()) { - if (high_track->first > high) { - high_track--; - } - } else { - logger_->error(DRT, 1005, "enclosesPlanarAccess: high track not found"); - } - if (high_track->first - low_track->first > (int) layer->getPitch()) { - return true; - } - if (low_track->first - (int) layer->getWidth() / 2 < low) { - return false; - } - if (high_track->first + (int) layer->getWidth() / 2 > high) { - return false; - } - return true; -} - -} // namespace drt From 081fab77866ec4cb473817579f78488c749b18bf Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Sun, 15 Dec 2024 15:31:48 +0000 Subject: [PATCH 61/98] mpl2: handle the track pattern more directly If you have multiple track patterns (eg m2 in asap7) the current code is wrong. This is a partial solution in that it just uses the first track pattern. Ideally it should consider snapping to any of the track patterns. The cost will be snapping further than needed. This "fixes" #6267. Signed-off-by: Matt Liberty --- src/mpl2/src/hier_rtlmp.cpp | 15 +++++++-------- src/mpl2/src/hier_rtlmp.h | 3 ++- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mpl2/src/hier_rtlmp.cpp b/src/mpl2/src/hier_rtlmp.cpp index 315f97b8e1f..335d41834b0 100644 --- a/src/mpl2/src/hier_rtlmp.cpp +++ b/src/mpl2/src/hier_rtlmp.cpp @@ -4547,11 +4547,7 @@ LayerParameters Snapper::computeLayerParameters( odb::dbTrackGrid* track_grid = block->findTrackGrid(layer); if (track_grid) { - std::vector coordinate_grid; - getTrackGrid(track_grid, coordinate_grid, target_direction); - - params.offset = coordinate_grid[0]; - params.pitch = coordinate_grid[1] - coordinate_grid[0]; + getTrackGrid(track_grid, params.offset, params.pitch, target_direction); } else { logger_->error( MPL, 39, "No track-grid found for layer {}", layer->getName()); @@ -4599,13 +4595,16 @@ int Snapper::getPinWidth(odb::dbITerm* pin, } void Snapper::getTrackGrid(odb::dbTrackGrid* track_grid, - std::vector& coordinate_grid, + int& origin, + int& step, const odb::dbTechLayerDir& target_direction) { + // TODO: handle multiple patterns + int count; if (target_direction == odb::dbTechLayerDir::VERTICAL) { - track_grid->getGridX(coordinate_grid); + track_grid->getGridPatternX(0, origin, count, step); } else { - track_grid->getGridY(coordinate_grid); + track_grid->getGridPatternY(0, origin, count, step); } } diff --git a/src/mpl2/src/hier_rtlmp.h b/src/mpl2/src/hier_rtlmp.h index 3e3a00c140c..f7a132d1ff9 100644 --- a/src/mpl2/src/hier_rtlmp.h +++ b/src/mpl2/src/hier_rtlmp.h @@ -418,7 +418,8 @@ class Snapper odb::dbITerm* pin, const odb::dbTechLayerDir& target_direction); void getTrackGrid(odb::dbTrackGrid* track_grid, - std::vector& coordinate_grid, + int& origin, + int& step, const odb::dbTechLayerDir& target_direction); int getPinWidth(odb::dbITerm* pin, const odb::dbTechLayerDir& target_direction); From 69a894860759d9869ec6e03d2bb82a05edb92e6f Mon Sep 17 00:00:00 2001 From: bernardo Date: Sun, 15 Dec 2024 15:53:24 +0000 Subject: [PATCH 62/98] drt: update copyright Signed-off-by: bernardo --- src/drt/src/pa/FlexPA_row_pattern.cpp | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/drt/src/pa/FlexPA_row_pattern.cpp b/src/drt/src/pa/FlexPA_row_pattern.cpp index 1ca2b6c136e..798d2a97834 100644 --- a/src/drt/src/pa/FlexPA_row_pattern.cpp +++ b/src/drt/src/pa/FlexPA_row_pattern.cpp @@ -1,6 +1,10 @@ -/* Authors: Lutong Wang and Bangqi Xu */ +/* Authors: Lutong Wang, Bangqi Xu and Precision Innovations*/ /* - * Copyright (c) 2019, The Regents of the University of California + * Copyright (c) 2024, + * The Regents of the University of California and Precision Innovations Inc. + * + * BSD 3-Clause License + * * All rights reserved. * * Redistribution and use in source and binary forms, with or without From e2c97ba81a31afed0ef83c066434f54f6935e20f Mon Sep 17 00:00:00 2001 From: bernardo Date: Sun, 15 Dec 2024 21:37:29 +0000 Subject: [PATCH 63/98] drt: adjust copyright Signed-off-by: bernardo --- src/drt/src/pa/FlexPA_acc_pattern.cpp | 1 + src/drt/src/pa/FlexPA_acc_point.cpp | 1 + src/drt/src/pa/FlexPA_row_pattern.cpp | 9 +++------ 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/src/drt/src/pa/FlexPA_acc_pattern.cpp b/src/drt/src/pa/FlexPA_acc_pattern.cpp index f32b4380a51..fe04cd0d832 100644 --- a/src/drt/src/pa/FlexPA_acc_pattern.cpp +++ b/src/drt/src/pa/FlexPA_acc_pattern.cpp @@ -1,6 +1,7 @@ /* Authors: Lutong Wang and Bangqi Xu */ /* * Copyright (c) 2019, The Regents of the University of California + * Copyright (c) 2024, Precision Innovations Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/drt/src/pa/FlexPA_acc_point.cpp b/src/drt/src/pa/FlexPA_acc_point.cpp index 1a8726d7b9c..73b356e7e8c 100644 --- a/src/drt/src/pa/FlexPA_acc_point.cpp +++ b/src/drt/src/pa/FlexPA_acc_point.cpp @@ -1,6 +1,7 @@ /* Authors: Lutong Wang and Bangqi Xu */ /* * Copyright (c) 2019, The Regents of the University of California + * Copyright (c) 2024, Precision Innovations Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/drt/src/pa/FlexPA_row_pattern.cpp b/src/drt/src/pa/FlexPA_row_pattern.cpp index 798d2a97834..112349c1d47 100644 --- a/src/drt/src/pa/FlexPA_row_pattern.cpp +++ b/src/drt/src/pa/FlexPA_row_pattern.cpp @@ -1,10 +1,7 @@ -/* Authors: Lutong Wang, Bangqi Xu and Precision Innovations*/ +/* Authors: Lutong Wang, Bangqi Xu*/ /* - * Copyright (c) 2024, - * The Regents of the University of California and Precision Innovations Inc. - * - * BSD 3-Clause License - * + * Copyright (c) 2019, The Regents of the University of California + * Copyright (c) 2024, Precision Innovations Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without From 8129fda54c86728166cfcce14d8139ad0c631c06 Mon Sep 17 00:00:00 2001 From: bernardo Date: Sun, 15 Dec 2024 18:35:14 +0000 Subject: [PATCH 64/98] drt: Transform slight refactoring Signed-off-by: bernardo --- src/drt/src/db/drObj/drVia.cpp | 4 +--- src/drt/src/db/drObj/drVia.h | 8 ++++---- src/drt/src/db/obj/frVia.h | 12 +++++------- src/drt/src/db/taObj/taVia.h | 10 ++++------ src/drt/src/dr/FlexDR_maze.cpp | 15 +++++---------- src/drt/src/dr/FlexDR_rq.cpp | 12 +++--------- src/drt/src/frRegionQuery.cpp | 4 +--- src/drt/src/gc/FlexGC_init.cpp | 6 ++---- src/drt/src/gr/FlexGR_rq.cpp | 12 +++--------- src/drt/src/io/io.cpp | 4 +--- src/drt/src/io/io_parser_helper.cpp | 3 +-- src/drt/src/ta/FlexTA_assign.cpp | 6 ++---- src/drt/test/fixture.cpp | 2 +- 13 files changed, 33 insertions(+), 65 deletions(-) diff --git a/src/drt/src/db/drObj/drVia.cpp b/src/drt/src/db/drObj/drVia.cpp index 103f95353c6..ef61f152115 100644 --- a/src/drt/src/db/drObj/drVia.cpp +++ b/src/drt/src/db/drObj/drVia.cpp @@ -100,9 +100,7 @@ Rect drVia::getBBox() const } } Rect box(xl, yl, xh, yh); - dbTransform xform; - xform.setOffset(origin_); - xform.apply(box); + getTransform().apply(box); return box; } diff --git a/src/drt/src/db/drObj/drVia.h b/src/drt/src/db/drObj/drVia.h index 37fa4d96940..0a12682ea4c 100644 --- a/src/drt/src/db/drObj/drVia.h +++ b/src/drt/src/db/drObj/drVia.h @@ -56,7 +56,7 @@ class drVia : public drRef for (auto& fig : viaDef_->getLayer1Figs()) { box.merge(fig->getBBox()); } - dbTransform(origin_).apply(box); + getTransform().apply(box); return box; } Rect getCutBBox() const @@ -66,7 +66,7 @@ class drVia : public drRef for (auto& fig : viaDef_->getCutFigs()) { box.merge(fig->getBBox()); } - dbTransform(origin_).apply(box); + getTransform().apply(box); return box; } Rect getLayer2BBox() const @@ -76,7 +76,7 @@ class drVia : public drRef for (auto& fig : viaDef_->getLayer2Figs()) { box.merge(fig->getBBox()); } - dbTransform(origin_).apply(box); + getTransform().apply(box); return box; } // setters @@ -97,7 +97,7 @@ class drVia : public drRef void setOrient(const dbOrientType& tmpOrient) override { ; } Point getOrigin() const override { return origin_; } void setOrigin(const Point& tmpPoint) override { origin_ = tmpPoint; } - dbTransform getTransform() const override { return origin_; } + dbTransform getTransform() const override { return dbTransform(origin_); } void setTransform(const dbTransform& xformIn) override {} /* from frPinFig diff --git a/src/drt/src/db/obj/frVia.h b/src/drt/src/db/obj/frVia.h index 498564a301c..ba9c7602a2e 100644 --- a/src/drt/src/db/obj/frVia.h +++ b/src/drt/src/db/obj/frVia.h @@ -64,7 +64,7 @@ class frVia : public frRef for (auto& fig : viaDef_->getLayer1Figs()) { box.merge(fig->getBBox()); } - dbTransform(origin_).apply(box); + getTransform().apply(box); return box; } Rect getCutBBox() const @@ -74,7 +74,7 @@ class frVia : public frRef for (auto& fig : viaDef_->getCutFigs()) { box.merge(fig->getBBox()); } - dbTransform(origin_).apply(box); + getTransform().apply(box); return box; } Rect getLayer2BBox() const @@ -84,7 +84,7 @@ class frVia : public frRef for (auto& fig : viaDef_->getLayer2Figs()) { box.merge(fig->getBBox()); } - dbTransform(origin_).apply(box); + getTransform().apply(box); return box; } // setters @@ -105,7 +105,7 @@ class frVia : public frRef void setOrient(const dbOrientType& tmpOrient) override { ; } Point getOrigin() const override { return origin_; } void setOrigin(const Point& tmpPoint) override { origin_ = tmpPoint; } - dbTransform getTransform() const override { return origin_; } + dbTransform getTransform() const override { return dbTransform(origin_); } void setTransform(const dbTransform& xformIn) override {} /* from frPinFig @@ -209,9 +209,7 @@ class frVia : public frRef } } Rect box(xl, yl, xh, yh); - dbTransform xform; - xform.setOffset(origin_); - xform.apply(box); + getTransform().apply(box); return box; } void move(const dbTransform& xform) override { ; } diff --git a/src/drt/src/db/taObj/taVia.h b/src/drt/src/db/taObj/taVia.h index e4dc5a58182..9f4d651c09e 100644 --- a/src/drt/src/db/taObj/taVia.h +++ b/src/drt/src/db/taObj/taVia.h @@ -65,7 +65,7 @@ class taVia : public taRef for (auto& fig : viaDef_->getLayer1Figs()) { box.merge(fig->getBBox()); } - dbTransform(origin_).apply(box); + getTransform().apply(box); return box; } Rect getCutBBox() const @@ -75,7 +75,7 @@ class taVia : public taRef for (auto& fig : viaDef_->getCutFigs()) { box.merge(fig->getBBox()); } - dbTransform(origin_).apply(box); + getTransform().apply(box); return box; } Rect getLayer2BBox() const @@ -85,7 +85,7 @@ class taVia : public taRef for (auto& fig : viaDef_->getLayer2Figs()) { box.merge(fig->getBBox()); } - dbTransform(origin_).apply(box); + getTransform().apply(box); return box; } // setters @@ -205,9 +205,7 @@ class taVia : public taRef } } Rect box(xl, yl, xh, yh); - dbTransform xform; - xform.setOffset(origin_); - xform.apply(box); + getTransform().apply(box); return box; } void move(const dbTransform& xform) override { ; } diff --git a/src/drt/src/dr/FlexDR_maze.cpp b/src/drt/src/dr/FlexDR_maze.cpp index 99290be5a2c..8729ac35436 100644 --- a/src/drt/src/dr/FlexDR_maze.cpp +++ b/src/drt/src/dr/FlexDR_maze.cpp @@ -556,7 +556,6 @@ void FlexDRWorker::modMinimumcutCostVia(const Rect& box, FlexMazeIdx mIdx1, mIdx2; Rect bx, tmpBx, sViaBox; - dbTransform xform; Point pt; frCoord dx, dy; frVia sVia; @@ -599,7 +598,7 @@ void FlexDRWorker::modMinimumcutCostVia(const Rect& box, for (int i = mIdx1.x(); i <= mIdx2.x(); i++) { for (int j = mIdx1.y(); j <= mIdx2.y(); j++) { gridGraph_.getPoint(pt, i, j); - xform.setOffset(pt); + dbTransform xform(pt); tmpBx = viaBox; if (gridGraph_.isSVia(i, j, zIdx)) { auto sViaDef = apSVia_[FlexMazeIdx(i, j, zIdx)]->getAccessViaDef(); @@ -797,13 +796,12 @@ void FlexDRWorker::modMinSpacingCostViaHelper(const Rect& box, Rect tmpBx; frSquaredDistance distSquare = 0; frCoord dx, dy; - dbTransform xform; frVia sVia; frMIdx zIdx = isUpperVia ? z : z - 1; for (int i = mIdx1.x(); i <= mIdx2.x(); i++) { for (int j = mIdx1.y(); j <= mIdx2.y(); j++) { gridGraph_.getPoint(pt, i, j); - xform.setOffset(pt); + dbTransform xform(pt); tmpBx = viaBox; if (gridGraph_.isSVia(i, j, zIdx)) { auto sViaDef = apSVia_[FlexMazeIdx(i, j, zIdx)]->getAccessViaDef(); @@ -1223,7 +1221,6 @@ void FlexDRWorker::modAdjCutSpacingCost_fixedObj(const frDesign* design, frSquaredDistance distSquare = 0; frSquaredDistance c2cSquare = 0; frCoord dx, dy, prl; - dbTransform xform; frSquaredDistance reqDistSquare = 0; Point boxCenter, tmpBxCenter; boxCenter = {(box.xMin() + box.xMax()) / 2, (box.yMin() + box.yMax()) / 2}; @@ -1237,7 +1234,7 @@ void FlexDRWorker::modAdjCutSpacingCost_fixedObj(const frDesign* design, for (auto& uFig : via.getViaDef()->getCutFigs()) { auto obj = static_cast(uFig.get()); gridGraph_.getPoint(pt, i, j); - xform.setOffset(pt); + dbTransform xform(pt); Rect tmpBx = obj->getBBox(); xform.apply(tmpBx); tmpBxCenter = {(tmpBx.xMin() + tmpBx.xMax()) / 2, @@ -1414,7 +1411,6 @@ void FlexDRWorker::modInterLayerCutSpacingCost(const Rect& box, frSquaredDistance distSquare = 0; frSquaredDistance c2cSquare = 0; frCoord prl, dx, dy; - dbTransform xform; frSquaredDistance reqDistSquare = 0; Point boxCenter, tmpBxCenter; boxCenter = {(box.xMin() + box.xMax()) / 2, (box.yMin() + box.yMax()) / 2}; @@ -1425,7 +1421,7 @@ void FlexDRWorker::modInterLayerCutSpacingCost(const Rect& box, for (auto& uFig : via.getViaDef()->getCutFigs()) { auto obj = static_cast(uFig.get()); gridGraph_.getPoint(pt, i, j); - xform.setOffset(pt); + dbTransform xform(pt); Rect tmpBx = obj->getBBox(); xform.apply(tmpBx); tmpBxCenter = {(tmpBx.xMin() + tmpBx.xMax()) / 2, @@ -1561,9 +1557,8 @@ void FlexDRWorker::modPathCost(drConnFig* connFig, modEolSpacingRulesCost(box, ei.z(), type, false, ndr); } - dbTransform xform; Point pt = obj->getOrigin(); - xform.setOffset(pt); + dbTransform xform(pt); for (auto& uFig : obj->getViaDef()->getCutFigs()) { auto rect = static_cast(uFig.get()); box = rect->getBBox(); diff --git a/src/drt/src/dr/FlexDR_rq.cpp b/src/drt/src/dr/FlexDR_rq.cpp index 7e7d67ec970..0487b4c5e17 100644 --- a/src/drt/src/dr/FlexDR_rq.cpp +++ b/src/drt/src/dr/FlexDR_rq.cpp @@ -72,9 +72,7 @@ void FlexDRWorkerRegionQuery::add(drConnFig* connFig) impl_->shapes_.at(obj->getLayerNum()).insert(std::make_pair(frb, obj)); } else if (connFig->typeId() == drcVia) { auto via = static_cast(connFig); - dbTransform xform; - Point origin = via->getOrigin(); - xform.setOffset(origin); + dbTransform xform = via->getTransform(); for (auto& uShape : via->getViaDef()->getLayer1Figs()) { auto shape = uShape.get(); if (shape->typeId() == frcRect) { @@ -124,9 +122,7 @@ void FlexDRWorkerRegionQuery::Impl::add( allShapes.at(obj->getLayerNum()).push_back(std::make_pair(frb, obj)); } else if (connFig->typeId() == drcVia) { auto via = static_cast(connFig); - dbTransform xform; - Point origin = via->getOrigin(); - xform.setOffset(origin); + dbTransform xform = via->getTransform(); for (auto& uShape : via->getViaDef()->getLayer1Figs()) { auto shape = uShape.get(); if (shape->typeId() == frcRect) { @@ -174,9 +170,7 @@ void FlexDRWorkerRegionQuery::remove(drConnFig* connFig) impl_->shapes_.at(obj->getLayerNum()).remove(std::make_pair(frb, obj)); } else if (connFig->typeId() == drcVia) { auto via = static_cast(connFig); - dbTransform xform; - Point origin = via->getOrigin(); - xform.setOffset(origin); + dbTransform xform = via->getTransform(); for (auto& uShape : via->getViaDef()->getLayer1Figs()) { auto shape = uShape.get(); if (shape->typeId() == frcRect) { diff --git a/src/drt/src/frRegionQuery.cpp b/src/drt/src/frRegionQuery.cpp index 2f720435e31..76ca45eb6f9 100644 --- a/src/drt/src/frRegionQuery.cpp +++ b/src/drt/src/frRegionQuery.cpp @@ -388,9 +388,7 @@ void frRegionQuery::removeMarker(frMarker* in) void frRegionQuery::Impl::add(frVia* via, ObjectsByLayer& allShapes) { - dbTransform xform; - Point origin = via->getOrigin(); - xform.setOffset(origin); + dbTransform xform = via->getTransform(); for (auto& uShape : via->getViaDef()->getLayer1Figs()) { auto shape = uShape.get(); if (shape->typeId() == frcRect) { diff --git a/src/drt/src/gc/FlexGC_init.cpp b/src/drt/src/gc/FlexGC_init.cpp index 4575e6a5962..b22a740d2f1 100644 --- a/src/drt/src/gc/FlexGC_init.cpp +++ b/src/drt/src/gc/FlexGC_init.cpp @@ -283,7 +283,6 @@ gcNet* FlexGCWorker::Impl::initDRObj(drConnFig* obj, gcNet* currNet) if (currNet == nullptr) { currNet = getNet(obj); } - dbTransform xform; frLayerNum layerNum; if (obj->typeId() == drcPathSeg) { auto pathSeg = static_cast(obj); @@ -299,7 +298,7 @@ gcNet* FlexGCWorker::Impl::initDRObj(drConnFig* obj, gcNet* currNet) } else if (obj->typeId() == drcVia) { auto via = static_cast(obj); layerNum = via->getViaDef()->getLayer1Num(); - xform = via->getTransform(); + dbTransform xform = via->getTransform(); for (auto& fig : via->getViaDef()->getLayer1Figs()) { Rect box = fig->getBBox(); xform.apply(box); @@ -343,7 +342,6 @@ gcNet* FlexGCWorker::Impl::initRouteObj(frBlockObject* obj, gcNet* currNet) if (currNet == nullptr) { currNet = getNet(obj); } - dbTransform xform; frLayerNum layerNum; if (obj->typeId() == frcPathSeg) { auto pathSeg = static_cast(obj); @@ -358,7 +356,7 @@ gcNet* FlexGCWorker::Impl::initRouteObj(frBlockObject* obj, gcNet* currNet) } else if (obj->typeId() == frcVia) { auto via = static_cast(obj); layerNum = via->getViaDef()->getLayer1Num(); - xform = via->getTransform(); + dbTransform xform = via->getTransform(); for (auto& fig : via->getViaDef()->getLayer1Figs()) { Rect box = fig->getBBox(); xform.apply(box); diff --git a/src/drt/src/gr/FlexGR_rq.cpp b/src/drt/src/gr/FlexGR_rq.cpp index e958277f4d6..ceb7dd2aaad 100644 --- a/src/drt/src/gr/FlexGR_rq.cpp +++ b/src/drt/src/gr/FlexGR_rq.cpp @@ -44,9 +44,7 @@ void FlexGRWorkerRegionQuery::add(grConnFig* connFig) shapes_.at(obj->getLayerNum()).insert(std::make_pair(boostr, obj)); } else if (connFig->typeId() == grcVia) { auto via = static_cast(connFig); - dbTransform xform; - Point origin = via->getOrigin(); - xform.setOffset(origin); + dbTransform xform = via->getTransform(); for (auto& uShape : via->getViaDef()->getLayer1Figs()) { auto shape = uShape.get(); if (shape->typeId() == frcRect) { @@ -95,9 +93,7 @@ void FlexGRWorkerRegionQuery::add( allShapes.at(obj->getLayerNum()).push_back(std::make_pair(frb, obj)); } else if (connFig->typeId() == grcVia) { auto via = static_cast(connFig); - dbTransform xform; - Point origin = via->getOrigin(); - xform.setOffset(origin); + dbTransform xform = via->getTransform(); for (auto& uShape : via->getViaDef()->getLayer1Figs()) { auto shape = uShape.get(); if (shape->typeId() == frcRect) { @@ -144,9 +140,7 @@ void FlexGRWorkerRegionQuery::remove(grConnFig* connFig) shapes_.at(obj->getLayerNum()).remove(std::make_pair(frb, obj)); } else if (connFig->typeId() == grcVia) { auto via = static_cast(connFig); - dbTransform xform; - Point origin = via->getOrigin(); - xform.setOffset(origin); + dbTransform xform = via->getTransform(); for (auto& uShape : via->getViaDef()->getLayer1Figs()) { auto shape = uShape.get(); if (shape->typeId() == frcRect) { diff --git a/src/drt/src/io/io.cpp b/src/drt/src/io/io.cpp index d2efa2d8d62..171a82d3e9c 100644 --- a/src/drt/src/io/io.cpp +++ b/src/drt/src/io/io.cpp @@ -1175,10 +1175,8 @@ odb::Rect io::Parser::getViaBoxForTermAboveMaxLayer(odb::dbBTerm* term, ->getLayerNum(); if (layerNum == router_cfg_->TOP_ROUTING_LAYER) { odb::Rect viaBox = vbox->getBox(); - odb::dbTransform xform; odb::Point path_origin = pshape.point; - xform.setOffset({path_origin.x(), path_origin.y()}); - xform.setOrient(odb::dbOrientType(odb::dbOrientType::R0)); + odb::dbTransform xform(path_origin); xform.apply(viaBox); if (bbox.intersects(viaBox)) { bbox = viaBox; diff --git a/src/drt/src/io/io_parser_helper.cpp b/src/drt/src/io/io_parser_helper.cpp index 4cd2ff0a7e8..6879c2be72f 100644 --- a/src/drt/src/io/io_parser_helper.cpp +++ b/src/drt/src/io/io_parser_helper.cpp @@ -852,12 +852,11 @@ void io::Parser::checkPins() foundTracks = false; foundCenterTracks = false; hasPolys = false; - dbTransform xform; for (auto& pin : bTerm->getPins()) { for (auto& uFig : pin->getFigs()) { checkFig(uFig.get(), bTerm->getName(), - xform, + dbTransform(), foundTracks, foundCenterTracks, hasPolys); diff --git a/src/drt/src/ta/FlexTA_assign.cpp b/src/drt/src/ta/FlexTA_assign.cpp index 8631f9d5747..dbe7b6b148a 100644 --- a/src/drt/src/ta/FlexTA_assign.cpp +++ b/src/drt/src/ta/FlexTA_assign.cpp @@ -89,13 +89,12 @@ void FlexTAWorker::modMinSpacingCostPlanar( idx2); Rect box2(-halfwidth2, -halfwidth2, halfwidth2, halfwidth2); - dbTransform xform; frCoord dx, dy; auto& trackLocs = getTrackLocs(lNum); auto& workerRegionQuery = getWorkerRegionQuery(); for (int i = idx1; i <= idx2; i++) { auto trackLoc = trackLocs[i]; - xform.setOffset(Point(boxLeft, trackLoc)); + dbTransform xform(Point(boxLeft, trackLoc)); xform.apply(box2); box2boxDistSquare(box1, box2, dx, dy); if (dy >= bloatDist) { @@ -562,9 +561,8 @@ void FlexTAWorker::modCost(taPinFig* fig, modMinSpacingCostVia(box, layerNum, obj, isAddCost, true, false, pinS); modMinSpacingCostVia(box, layerNum, obj, isAddCost, false, false, pinS); - dbTransform xform; Point pt = obj->getOrigin(); - xform.setOffset(pt); + dbTransform xform(pt); for (auto& uFig : obj->getViaDef()->getCutFigs()) { auto rect = static_cast(uFig.get()); box = rect->getBBox(); diff --git a/src/drt/test/fixture.cpp b/src/drt/test/fixture.cpp index dddb6f73bc6..10f26ea868b 100644 --- a/src/drt/test/fixture.cpp +++ b/src/drt/test/fixture.cpp @@ -194,7 +194,7 @@ frInst* Fixture::makeInst(const char* name, auto ptr_db_inst = std::make_unique(); odb::dbInst* db_inst = ptr_db_inst->create(db_->getChip()->getBlock(), db_master, "dummy"); - dbTransform trans = dbTransform(); + dbTransform trans; db_inst->setTransform(trans); auto uInst = std::make_unique(name, master, db_inst); auto tmpInst = uInst.get(); From 00b48d7b2bb1b8a80240ceb5f1b531685376b3cf Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Mon, 16 Dec 2024 11:17:49 -0300 Subject: [PATCH 65/98] grt: remove outdated argument and rename internal vars Signed-off-by: Eder Monteiro --- src/gpl/src/routeBase.cpp | 2 +- src/grt/README.md | 3 +-- src/grt/include/grt/GlobalRouter.h | 4 ++-- src/grt/src/GlobalRouter.cpp | 8 ++++---- src/grt/src/GlobalRouter.i | 4 ++-- src/grt/src/GlobalRouter.tcl | 14 +++----------- 6 files changed, 13 insertions(+), 22 deletions(-) diff --git a/src/gpl/src/routeBase.cpp b/src/gpl/src/routeBase.cpp index 706c48a0207..5ae00f39cca 100644 --- a/src/gpl/src/routeBase.cpp +++ b/src/gpl/src/routeBase.cpp @@ -331,7 +331,7 @@ void RouteBase::getGrtResult() // these two options must be on grouter_->setAllowCongestion(true); - grouter_->setOverflowIterations(0); + grouter_->setCongestionIterations(0); // this option must be off grouter_->setCriticalNetsPercentage(0); diff --git a/src/grt/README.md b/src/grt/README.md index 1fdaea67719..f22a4b109a4 100644 --- a/src/grt/README.md +++ b/src/grt/README.md @@ -25,7 +25,6 @@ global_route [-grid_origin {x y}] [-critical_nets_percentage percent] [-allow_congestion] - [-overflow_iterations] [-verbose] [-start_incremental] [-end_incremental] @@ -408,7 +407,7 @@ command. (See `GlobalRouter.h` for a complete list) ```python gr.setGridOrigin(x, y) # int, default 0,0 gr.setCongestionReportFile(file_name) # string -gr.setOverflowIterations(n) # int, default 50 +gr.setCongestionIterations(n) # int, default 50 gr.setAllowCongestion(allowCongestion) # boolean, default False gr.setCriticalNetsPercentage(percentage) # float gr.setMinRoutingLayer(minLayer) # int diff --git a/src/grt/include/grt/GlobalRouter.h b/src/grt/include/grt/GlobalRouter.h index bd9801eef45..5f2232c7397 100644 --- a/src/grt/include/grt/GlobalRouter.h +++ b/src/grt/include/grt/GlobalRouter.h @@ -179,7 +179,7 @@ class GlobalRouter : public ant::GlobalRouteSource int layer, float reduction_percentage); void setVerbose(bool v); - void setOverflowIterations(int iterations); + void setCongestionIterations(int iterations); void setCongestionReportIterStep(int congestion_report_iter_step); void setCongestionReportFile(const char* file_name); void setGridOrigin(int x, int y); @@ -486,7 +486,7 @@ class GlobalRouter : public ant::GlobalRouteSource // Flow variables float adjustment_; int layer_for_guide_dimension_; - int overflow_iterations_; + int congestion_iterations_; int congestion_report_iter_step_; bool allow_congestion_; std::vector vertical_capacities_; diff --git a/src/grt/src/GlobalRouter.cpp b/src/grt/src/GlobalRouter.cpp index 8051acdd0a8..7dad3108378 100644 --- a/src/grt/src/GlobalRouter.cpp +++ b/src/grt/src/GlobalRouter.cpp @@ -92,7 +92,7 @@ GlobalRouter::GlobalRouter() grid_(new Grid), adjustment_(0.0), layer_for_guide_dimension_(3), - overflow_iterations_(50), + congestion_iterations_(50), congestion_report_iter_step_(0), allow_congestion_(false), macro_extension_(0), @@ -1882,9 +1882,9 @@ void GlobalRouter::setVerbose(const bool v) verbose_ = v; } -void GlobalRouter::setOverflowIterations(int iterations) +void GlobalRouter::setCongestionIterations(int iterations) { - overflow_iterations_ = iterations; + congestion_iterations_ = iterations; } void GlobalRouter::setCongestionReportIterStep(int congestion_report_iter_step) @@ -2001,7 +2001,7 @@ void GlobalRouter::ensureLayerForGuideDimension(int max_routing_layer) void GlobalRouter::configFastRoute() { fastroute_->setVerbose(verbose_); - fastroute_->setOverflowIterations(overflow_iterations_); + fastroute_->setOverflowIterations(congestion_iterations_); fastroute_->setCongestionReportIterStep(congestion_report_iter_step_); if (congestion_file_name_ != nullptr) { diff --git a/src/grt/src/GlobalRouter.i b/src/grt/src/GlobalRouter.i index db6a1a35d96..9d72b47793e 100644 --- a/src/grt/src/GlobalRouter.i +++ b/src/grt/src/GlobalRouter.i @@ -108,9 +108,9 @@ set_verbose(bool v) } void -set_overflow_iterations(int iterations) +set_congestion_iterations(int iterations) { - getGlobalRouter()->setOverflowIterations(iterations); + getGlobalRouter()->setCongestionIterations(iterations); } void diff --git a/src/grt/src/GlobalRouter.tcl b/src/grt/src/GlobalRouter.tcl index 325ed219c18..18e2d7bd3ea 100644 --- a/src/grt/src/GlobalRouter.tcl +++ b/src/grt/src/GlobalRouter.tcl @@ -179,7 +179,6 @@ sta::define_cmd_args "global_route" {[-guide_file out_file] \ [-grid_origin origin] \ [-critical_nets_percentage percent] \ [-allow_congestion] \ - [-overflow_iterations iterations] \ [-verbose] \ [-start_incremental] \ [-end_incremental] @@ -188,7 +187,7 @@ sta::define_cmd_args "global_route" {[-guide_file out_file] \ proc global_route { args } { sta::parse_key_args "global_route" args \ keys {-guide_file -congestion_iterations -congestion_report_file \ - -overflow_iterations -grid_origin -critical_nets_percentage -congestion_report_iter_step + -grid_origin -critical_nets_percentage -congestion_report_iter_step } \ flags {-allow_congestion -verbose -start_incremental -end_incremental} @@ -219,9 +218,9 @@ proc global_route { args } { if { [info exists keys(-congestion_iterations)] } { set iterations $keys(-congestion_iterations) sta::check_positive_integer "-congestion_iterations" $iterations - grt::set_overflow_iterations $iterations + grt::set_congestion_iterations $iterations } else { - grt::set_overflow_iterations 50 + grt::set_congestion_iterations 50 } if { [info exists keys(-congestion_report_file)] } { @@ -236,13 +235,6 @@ proc global_route { args } { grt::set_congestion_report_iter_step 0 } - if { [info exists keys(-overflow_iterations)] } { - utl::war GRT 147 "Argument -overflow_iterations is deprecated. Use -congestion_iterations." - set iterations $keys(-overflow_iterations) - sta::check_positive_integer "-overflow_iterations" $iterations - grt::set_overflow_iterations $iterations - } - if { [info exists keys(-critical_nets_percentage)] } { set percentage $keys(-critical_nets_percentage) sta::check_percent "-critical_nets_percentage" $percentage From 24071edef155fc660c96c7b37039166c15bc5a74 Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Mon, 16 Dec 2024 11:48:53 -0300 Subject: [PATCH 66/98] grt: clang-tidy Signed-off-by: Eder Monteiro --- src/grt/include/grt/GlobalRouter.h | 2 +- src/grt/src/GlobalRouter.cpp | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/src/grt/include/grt/GlobalRouter.h b/src/grt/include/grt/GlobalRouter.h index 5f2232c7397..57d0ab4a058 100644 --- a/src/grt/include/grt/GlobalRouter.h +++ b/src/grt/include/grt/GlobalRouter.h @@ -486,7 +486,7 @@ class GlobalRouter : public ant::GlobalRouteSource // Flow variables float adjustment_; int layer_for_guide_dimension_; - int congestion_iterations_; + int congestion_iterations_{50}; int congestion_report_iter_step_; bool allow_congestion_; std::vector vertical_capacities_; diff --git a/src/grt/src/GlobalRouter.cpp b/src/grt/src/GlobalRouter.cpp index 7dad3108378..7cb3b33e576 100644 --- a/src/grt/src/GlobalRouter.cpp +++ b/src/grt/src/GlobalRouter.cpp @@ -92,7 +92,6 @@ GlobalRouter::GlobalRouter() grid_(new Grid), adjustment_(0.0), layer_for_guide_dimension_(3), - congestion_iterations_(50), congestion_report_iter_step_(0), allow_congestion_(false), macro_extension_(0), From f0b70f5db10610a56cbfcea9b001515d28043eb9 Mon Sep 17 00:00:00 2001 From: luis201420 Date: Mon, 16 Dec 2024 20:45:27 +0000 Subject: [PATCH 67/98] ant: removing unused variables Signed-off-by: luis201420 --- src/ant/include/ant/AntennaChecker.hh | 4 ---- src/ant/src/AntennaChecker.cc | 13 ------------- 2 files changed, 17 deletions(-) diff --git a/src/ant/include/ant/AntennaChecker.hh b/src/ant/include/ant/AntennaChecker.hh index e73c185a02b..d604255b705 100644 --- a/src/ant/include/ant/AntennaChecker.hh +++ b/src/ant/include/ant/AntennaChecker.hh @@ -180,8 +180,6 @@ class AntennaChecker void buildLayerMaps(odb::dbNet* net, LayerToGraphNodes& node_by_layer_map); void checkNet(odb::dbNet* net, bool verbose, - bool report_if_no_violation, - std::ofstream& report_file, odb::dbMTerm* diode_mterm, float ratio_margin, int& net_violation_count, @@ -205,8 +203,6 @@ class AntennaChecker void printReport(); int checkGates(odb::dbNet* db_net, bool verbose, - bool report_if_no_violation, - std::ofstream& report_file, odb::dbMTerm* diode_mterm, float ratio_margin, GateToLayerToNodeInfo& gate_info, diff --git a/src/ant/src/AntennaChecker.cc b/src/ant/src/AntennaChecker.cc index 339d1d4b58b..2c07901ac7a 100644 --- a/src/ant/src/AntennaChecker.cc +++ b/src/ant/src/AntennaChecker.cc @@ -775,8 +775,6 @@ void AntennaChecker::printReport() int AntennaChecker::checkGates(odb::dbNet* db_net, bool verbose, - bool report_if_no_violation, - std::ofstream& report_file, odb::dbMTerm* diode_mterm, float ratio_margin, GateToLayerToNodeInfo& gate_info, @@ -1020,8 +1018,6 @@ void AntennaChecker::buildLayerMaps(odb::dbNet* db_net, void AntennaChecker::checkNet(odb::dbNet* db_net, bool verbose, - bool report_if_no_violation, - std::ofstream& report_file, odb::dbMTerm* diode_mterm, float ratio_margin, int& net_violation_count, @@ -1041,8 +1037,6 @@ void AntennaChecker::checkNet(odb::dbNet* db_net, int pin_violations = checkGates(db_net, verbose, - report_if_no_violation, - report_file, diode_mterm, ratio_margin, gate_info, @@ -1075,11 +1069,8 @@ Violations AntennaChecker::getAntennaViolations(odb::dbNet* net, int net_violation_count, pin_violation_count; net_violation_count = 0; pin_violation_count = 0; - std::ofstream report_file; checkNet(net, false, - false, - report_file, diode_mterm, ratio_margin, net_violation_count, @@ -1132,8 +1123,6 @@ int AntennaChecker::checkAntennas(odb::dbNet* net, if (!net->isSpecial()) { checkNet(net, verbose, - true, - report_file, nullptr, 0, net_violation_count, @@ -1158,8 +1147,6 @@ int AntennaChecker::checkAntennas(odb::dbNet* net, Violations antenna_violations; checkNet(net, verbose, - false, - report_file, nullptr, 0, net_violation_count, From 22395d8ce2f2cd12aee12fe10aae812d85ea1f5e Mon Sep 17 00:00:00 2001 From: Jeff Ng Date: Mon, 16 Dec 2024 15:03:27 -0800 Subject: [PATCH 68/98] bumped up coverage timeout to 3h Signed-off-by: Jeff Ng --- jenkins/Jenkinsfile.coverage | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/jenkins/Jenkinsfile.coverage b/jenkins/Jenkinsfile.coverage index cad7c504b6e..4c2c16af309 100644 --- a/jenkins/Jenkinsfile.coverage +++ b/jenkins/Jenkinsfile.coverage @@ -21,7 +21,7 @@ node { stage('Dynamic Code Coverage') { catchError(buildResult: 'FAILURE', stageResult: 'FAILURE') { - timeout(time: 2, unit: 'HOURS') { + timeout(time: 3, unit: 'HOURS') { sh './etc/CodeCoverage.sh dynamic'; } } From 9db18f376a9f50307f7a8edb8b6f4d7d09f12270 Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Tue, 17 Dec 2024 00:39:38 +0000 Subject: [PATCH 69/98] gui: add pin density heat map Signed-off-by: Matt Liberty --- src/gui/CMakeLists.txt | 1 + src/gui/README.md | 1 + src/gui/include/gui/gui.h | 2 + src/gui/src/gui.cpp | 6 +- src/gui/src/heatMapPinDensity.cpp | 174 ++++++++++++++++++++++++++++++ src/gui/src/heatMapPinDensity.h | 76 +++++++++++++ src/gui/src/stub.cpp | 9 ++ 7 files changed, 268 insertions(+), 1 deletion(-) create mode 100644 src/gui/src/heatMapPinDensity.cpp create mode 100644 src/gui/src/heatMapPinDensity.h diff --git a/src/gui/CMakeLists.txt b/src/gui/CMakeLists.txt index 32533b2be2a..b7330dd1328 100755 --- a/src/gui/CMakeLists.txt +++ b/src/gui/CMakeLists.txt @@ -55,6 +55,7 @@ if (Qt5_FOUND AND BUILD_GUI) src/ruler.cpp src/heatMap.cpp src/heatMapSetup.cpp + src/heatMapPinDensity.cpp src/heatMapPlacementDensity.cpp src/browserWidget.cpp src/globalConnectDialog.cpp diff --git a/src/gui/README.md b/src/gui/README.md index 4c8fb352acf..0fab55bc788 100644 --- a/src/gui/README.md +++ b/src/gui/README.md @@ -628,6 +628,7 @@ gui::show_help To control the settings in the heat maps: The currently availble heat maps are: +- ``Pin`` - ``Power`` - ``Routing`` - ``Placement`` diff --git a/src/gui/include/gui/gui.h b/src/gui/include/gui/gui.h index 0eeb6c6c58a..dcdc9530ed1 100644 --- a/src/gui/include/gui/gui.h +++ b/src/gui/include/gui/gui.h @@ -57,6 +57,7 @@ class Logger; namespace gui { class HeatMapDataSource; +class PinDensityDataSource; class PlacementDensityDataSource; class Painter; class Selected; @@ -809,6 +810,7 @@ class Gui std::set renderers_; + std::unique_ptr pin_density_heat_map_; std::unique_ptr placement_density_heat_map_; static Gui* singleton_; diff --git a/src/gui/src/gui.cpp b/src/gui/src/gui.cpp index d1b9de94c2f..94af2a9e65e 100644 --- a/src/gui/src/gui.cpp +++ b/src/gui/src/gui.cpp @@ -41,6 +41,7 @@ #include "clockWidget.h" #include "displayControls.h" #include "drcWidget.h" +#include "heatMapPinDensity.h" #include "heatMapPlacementDensity.h" #include "helpWidget.h" #include "inspector.h" @@ -228,6 +229,7 @@ Gui::Gui() : continue_after_close_(false), logger_(nullptr), db_(nullptr), + pin_density_heat_map_(nullptr), placement_density_heat_map_(nullptr) { resetConversions(); @@ -1283,7 +1285,9 @@ void Gui::init(odb::dbDatabase* db, utl::Logger* logger) db_ = db; setLogger(logger); - // placement density heatmap + pin_density_heat_map_ = std::make_unique(logger); + pin_density_heat_map_->registerHeatMap(); + placement_density_heat_map_ = std::make_unique(logger); placement_density_heat_map_->registerHeatMap(); diff --git a/src/gui/src/heatMapPinDensity.cpp b/src/gui/src/heatMapPinDensity.cpp new file mode 100644 index 00000000000..14af39c64c4 --- /dev/null +++ b/src/gui/src/heatMapPinDensity.cpp @@ -0,0 +1,174 @@ +////////////////////////////////////////////////////////////////////////////// +// BSD 3-Clause License +// +// Copyright (c) 2024, Precision Innovations Inc. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#include "heatMapPinDensity.h" + +#include + +#include "db_sta/dbNetwork.hh" +#include "odb/db.h" +#include "odb/dbTransform.h" + +namespace gui { + +PinDensityDataSource::PinDensityDataSource(utl::Logger* logger) + : RealValueHeatMapDataSource(logger, + "pins", + "Pin Density", + "Pin", + "PinDensity") +{ +} + +bool PinDensityDataSource::populateMap() +{ + if (getBlock() == nullptr) { + return false; + } + + // Iterate through blocks hierarchically to gather the flattened data + // for this view. + std::vector> blocks + = {{getBlock(), odb::dbTransform()}}; + + while (!blocks.empty()) { + auto [current_block, current_transform] = blocks.back(); + blocks.pop_back(); + + const bool has_child_blocks = !current_block->getChildren().empty(); + + for (auto* inst : current_block->getInsts()) { + if (!inst->getPlacementStatus().isPlaced()) { + continue; + } + + odb::dbMaster* master = inst->getMaster(); + odb::dbBlock* child; + if (has_child_blocks + && (child = inst->getBlock()->findChild(master->getName().c_str()))) { + const odb::dbTransform child_transform = inst->getTransform(); + blocks.emplace_back(child, child_transform); + continue; + } + + for (odb::dbITerm* iterm : inst->getITerms()) { + if (iterm->getSigType().isSupply()) { + continue; + } + + // Get iterm bbox + odb::Rect bbox; + bbox.mergeInit(); + for (auto& [layer, geom_bbox] : iterm->getGeometries()) { + bbox.merge(geom_bbox); + } + if (bbox.isInverted()) { + continue; + } + + current_transform.apply(bbox); + addToMap(bbox, 1); + } + } + } + + return true; +} + +void PinDensityDataSource::combineMapData(bool base_has_value, + double& base, + const double new_data, + const double data_area, + const double intersection_area, + const double rect_area) +{ + base += (new_data / data_area) * intersection_area; +} + +void PinDensityDataSource::onShow() +{ + HeatMapDataSource::onShow(); + + addOwner(getBlock()); +} + +void PinDensityDataSource::onHide() +{ + HeatMapDataSource::onHide(); + + removeOwner(); +} + +void PinDensityDataSource::inDbInstCreate(odb::dbInst*) +{ + destroyMap(); +} + +void PinDensityDataSource::inDbInstCreate(odb::dbInst*, odb::dbRegion*) +{ + destroyMap(); +} + +void PinDensityDataSource::inDbInstDestroy(odb::dbInst*) +{ + destroyMap(); +} + +void PinDensityDataSource::inDbInstPlacementStatusBefore( + odb::dbInst*, + const odb::dbPlacementStatus&) +{ + destroyMap(); +} + +void PinDensityDataSource::inDbInstSwapMasterBefore(odb::dbInst*, + odb::dbMaster*) +{ + destroyMap(); +} + +void PinDensityDataSource::inDbInstSwapMasterAfter(odb::dbInst*) +{ + destroyMap(); +} + +void PinDensityDataSource::inDbPreMoveInst(odb::dbInst*) +{ + destroyMap(); +} + +void PinDensityDataSource::inDbPostMoveInst(odb::dbInst*) +{ + destroyMap(); +} + +} // namespace gui diff --git a/src/gui/src/heatMapPinDensity.h b/src/gui/src/heatMapPinDensity.h new file mode 100644 index 00000000000..87c9ede9bdd --- /dev/null +++ b/src/gui/src/heatMapPinDensity.h @@ -0,0 +1,76 @@ +/////////////////////////////////////////////////////////////////////////////// +// BSD 3-Clause License +// +// Copyright (c) 2021, The Regents of the University of California +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#pragma once + +#include "db_sta/dbSta.hh" +#include "gui/heatMap.h" +#include "odb/dbBlockCallBackObj.h" +#include "sta/Corner.hh" + +namespace gui { + +class PinDensityDataSource : public RealValueHeatMapDataSource, + public odb::dbBlockCallBackObj +{ + public: + PinDensityDataSource(utl::Logger* logger); + ~PinDensityDataSource() {} + + virtual void onShow() override; + virtual void onHide() override; + + // from dbBlockCallBackObj API + virtual void inDbInstCreate(odb::dbInst*) override; + virtual void inDbInstCreate(odb::dbInst*, odb::dbRegion*) override; + virtual void inDbInstDestroy(odb::dbInst*) override; + virtual void inDbInstPlacementStatusBefore( + odb::dbInst*, + const odb::dbPlacementStatus&) override; + virtual void inDbInstSwapMasterBefore(odb::dbInst*, odb::dbMaster*) override; + virtual void inDbInstSwapMasterAfter(odb::dbInst*) override; + virtual void inDbPreMoveInst(odb::dbInst*) override; + virtual void inDbPostMoveInst(odb::dbInst*) override; + + protected: + virtual bool populateMap() override; + virtual void combineMapData(bool base_has_value, + double& base, + const double new_data, + const double data_area, + const double intersection_area, + const double rect_area) override; + + virtual bool destroyMapOnNotVisible() const override { return true; } +}; + +} // namespace gui diff --git a/src/gui/src/stub.cpp b/src/gui/src/stub.cpp index 1b69c796302..98604fb9404 100644 --- a/src/gui/src/stub.cpp +++ b/src/gui/src/stub.cpp @@ -50,6 +50,14 @@ DBUToString Descriptor::Property::convert_dbu StringToDBU Descriptor::Property::convert_string = [](const std::string& value, bool*) { return 0; }; +// empty heat map class +class PinDensityDataSource +{ + public: + PinDensityDataSource() {} + ~PinDensityDataSource() {} +}; + // empty heat map class class PlacementDensityDataSource { @@ -64,6 +72,7 @@ Gui::Gui() : continue_after_close_(false), logger_(nullptr), db_(nullptr), + pin_density_heat_map_(nullptr), placement_density_heat_map_(nullptr) { } From 947262d0952d939b37ac972db64756047674774a Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Tue, 17 Dec 2024 00:54:21 +0000 Subject: [PATCH 70/98] gui: clang-tidy heatMapPinDensity.* Signed-off-by: Matt Liberty --- src/gui/src/heatMapPinDensity.cpp | 13 +++++----- src/gui/src/heatMapPinDensity.h | 40 +++++++++++++++---------------- src/gui/src/stub.cpp | 6 ----- 3 files changed, 26 insertions(+), 33 deletions(-) diff --git a/src/gui/src/heatMapPinDensity.cpp b/src/gui/src/heatMapPinDensity.cpp index 14af39c64c4..bdf1c84a1f1 100644 --- a/src/gui/src/heatMapPinDensity.cpp +++ b/src/gui/src/heatMapPinDensity.cpp @@ -72,12 +72,13 @@ bool PinDensityDataSource::populateMap() } odb::dbMaster* master = inst->getMaster(); - odb::dbBlock* child; - if (has_child_blocks - && (child = inst->getBlock()->findChild(master->getName().c_str()))) { - const odb::dbTransform child_transform = inst->getTransform(); - blocks.emplace_back(child, child_transform); - continue; + if (has_child_blocks) { + auto child = inst->getBlock()->findChild(master->getName().c_str()); + if (child) { + const odb::dbTransform child_transform = inst->getTransform(); + blocks.emplace_back(child, child_transform); + continue; + } } for (odb::dbITerm* iterm : inst->getITerms()) { diff --git a/src/gui/src/heatMapPinDensity.h b/src/gui/src/heatMapPinDensity.h index 87c9ede9bdd..0b2603c55d4 100644 --- a/src/gui/src/heatMapPinDensity.h +++ b/src/gui/src/heatMapPinDensity.h @@ -44,33 +44,31 @@ class PinDensityDataSource : public RealValueHeatMapDataSource, { public: PinDensityDataSource(utl::Logger* logger); - ~PinDensityDataSource() {} - virtual void onShow() override; - virtual void onHide() override; + void onShow() override; + void onHide() override; // from dbBlockCallBackObj API - virtual void inDbInstCreate(odb::dbInst*) override; - virtual void inDbInstCreate(odb::dbInst*, odb::dbRegion*) override; - virtual void inDbInstDestroy(odb::dbInst*) override; - virtual void inDbInstPlacementStatusBefore( - odb::dbInst*, - const odb::dbPlacementStatus&) override; - virtual void inDbInstSwapMasterBefore(odb::dbInst*, odb::dbMaster*) override; - virtual void inDbInstSwapMasterAfter(odb::dbInst*) override; - virtual void inDbPreMoveInst(odb::dbInst*) override; - virtual void inDbPostMoveInst(odb::dbInst*) override; + void inDbInstCreate(odb::dbInst*) override; + void inDbInstCreate(odb::dbInst*, odb::dbRegion*) override; + void inDbInstDestroy(odb::dbInst*) override; + void inDbInstPlacementStatusBefore(odb::dbInst*, + const odb::dbPlacementStatus&) override; + void inDbInstSwapMasterBefore(odb::dbInst*, odb::dbMaster*) override; + void inDbInstSwapMasterAfter(odb::dbInst*) override; + void inDbPreMoveInst(odb::dbInst*) override; + void inDbPostMoveInst(odb::dbInst*) override; protected: - virtual bool populateMap() override; - virtual void combineMapData(bool base_has_value, - double& base, - const double new_data, - const double data_area, - const double intersection_area, - const double rect_area) override; + bool populateMap() override; + void combineMapData(bool base_has_value, + double& base, + double new_data, + double data_area, + double intersection_area, + double rect_area) override; - virtual bool destroyMapOnNotVisible() const override { return true; } + bool destroyMapOnNotVisible() const override { return true; } }; } // namespace gui diff --git a/src/gui/src/stub.cpp b/src/gui/src/stub.cpp index 98604fb9404..4c900f0e380 100644 --- a/src/gui/src/stub.cpp +++ b/src/gui/src/stub.cpp @@ -53,17 +53,11 @@ StringToDBU Descriptor::Property::convert_string // empty heat map class class PinDensityDataSource { - public: - PinDensityDataSource() {} - ~PinDensityDataSource() {} }; // empty heat map class class PlacementDensityDataSource { - public: - PlacementDensityDataSource() {} - ~PlacementDensityDataSource() {} }; //// From b965c70d9210c975710866417a4dd1e7fca4bad8 Mon Sep 17 00:00:00 2001 From: luis201420 Date: Tue, 17 Dec 2024 03:01:14 +0000 Subject: [PATCH 71/98] ant: removing debug prints Signed-off-by: luis201420 --- src/ant/src/AntennaChecker.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/src/ant/src/AntennaChecker.cc b/src/ant/src/AntennaChecker.cc index 2c07901ac7a..9021cba5efb 100644 --- a/src/ant/src/AntennaChecker.cc +++ b/src/ant/src/AntennaChecker.cc @@ -1086,7 +1086,6 @@ int AntennaChecker::checkAntennas(odb::dbNet* net, const int num_threads, bool verbose) { - printf("Start to checkAntenna\n"); { std::lock_guard lock(mapMutex); net_to_report_.clear(); From f11eeeaa279be99340acfb9813d7728091a63cbc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 17 Dec 2024 11:29:22 +0100 Subject: [PATCH 72/98] gui: Adjust title passing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Martin Povišer --- src/gui/include/gui/gui.h | 2 +- src/gui/src/gui.cpp | 3 ++- src/gui/src/mainWindow.cpp | 25 +++++++++++++------------ 3 files changed, 16 insertions(+), 14 deletions(-) diff --git a/src/gui/include/gui/gui.h b/src/gui/include/gui/gui.h index f158588d5bd..2f391638e53 100644 --- a/src/gui/include/gui/gui.h +++ b/src/gui/include/gui/gui.h @@ -731,7 +731,7 @@ class Gui const std::string& option); void dumpHeatMap(const std::string& name, const std::string& file); - void setMainWindowTitle(std::string title); + void setMainWindowTitle(const std::string& title); std::string getMainWindowTitle(); void selectHelp(const std::string& item); diff --git a/src/gui/src/gui.cpp b/src/gui/src/gui.cpp index 5af79f7add9..23e089cec58 100644 --- a/src/gui/src/gui.cpp +++ b/src/gui/src/gui.cpp @@ -1002,7 +1002,7 @@ void Gui::dumpHeatMap(const std::string& name, const std::string& file) source->dumpToFile(file); } -void Gui::setMainWindowTitle(std::string title) +void Gui::setMainWindowTitle(const std::string& title) { main_window_title_ = title; if (main_window) { @@ -1381,6 +1381,7 @@ int startGui(int& argc, if (minimize) { main_window->showMinimized(); } + main_window->setTitle(gui->getMainWindowTitle()); open_road->addObserver(main_window); if (!interactive) { diff --git a/src/gui/src/mainWindow.cpp b/src/gui/src/mainWindow.cpp index db1a301e9f7..1a583f0b7f8 100644 --- a/src/gui/src/mainWindow.cpp +++ b/src/gui/src/mainWindow.cpp @@ -49,6 +49,7 @@ #include #include #include +#include #include #include "browserWidget.h" @@ -112,8 +113,7 @@ MainWindow::MainWindow(bool load_settings, QWidget* parent) charts_widget_(new ChartsWidget(this)), help_widget_(new HelpWidget(this)), find_dialog_(new FindObjectDialog(this)), - goto_dialog_(new GotoLocationDialog(this, viewers_)), - window_title_(Gui::get()->getMainWindowTitle()) + goto_dialog_(new GotoLocationDialog(this, viewers_)) { // Size and position the window QSize size = QDesktopWidget().availableGeometry(this).size(); @@ -418,10 +418,9 @@ MainWindow::MainWindow(bool load_settings, QWidget* parent) settings.endGroup(); } - // load resources and set window icon and title + // load resources and set window icon loadQTResources(); setWindowIcon(QIcon(":/icon.png")); - updateTitle(); Descriptor::Property::convert_dbu = [this](int value, bool add_units) -> std::string { @@ -452,19 +451,21 @@ void MainWindow::setDatabase(odb::dbDatabase* db) void MainWindow::setTitle(std::string title) { - window_title_ = title; + window_title_ = std::move(title); updateTitle(); } void MainWindow::updateTitle() { - odb::dbBlock* block = getBlock(); - if (block != nullptr) { - const std::string title - = fmt::format("{} - {}", window_title_, block->getName()); - setWindowTitle(QString::fromStdString(title)); - } else { - setWindowTitle(QString::fromStdString(window_title_)); + if (!window_title_.empty()) { + odb::dbBlock* block = getBlock(); + if (block != nullptr) { + const std::string title + = fmt::format("{} - {}", window_title_, block->getName()); + setWindowTitle(QString::fromStdString(title)); + } else { + setWindowTitle(QString::fromStdString(window_title_)); + } } } From 30955a09dc666c5966c787191d5f54e46b73a98d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 17 Dec 2024 11:35:19 +0100 Subject: [PATCH 73/98] gui: Document `set_title` MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Martin Povišer --- src/gui/README.md | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/gui/README.md b/src/gui/README.md index 4c8fb352acf..b15f8c7d8ff 100644 --- a/src/gui/README.md +++ b/src/gui/README.md @@ -253,6 +253,20 @@ gui::show | `script` | TCL script to evaluate in the GUI. | | `interactive` | Boolean if true, the GUI should open in an interactive session (default), or if false that the GUI would execute the script and return to the terminal.| +### Set GUI Title + +To set the title of the main GUI window: + +```tcl +gui::set_title title +``` + +#### Options + +| Switch Name | Description | +| ---- | ---- | +| `title` | window title to use for the main GUI window | + ### Hide GUI To close the GUI and return to the command-line: From 9a939868e9fe2fc1ed9b122876ba57c9833cac1c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 17 Dec 2024 12:01:33 +0100 Subject: [PATCH 74/98] gui: Appease tidy MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Martin Povišer --- src/gui/src/mainWindow.cpp | 5 ++--- src/gui/src/mainWindow.h | 2 +- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/src/gui/src/mainWindow.cpp b/src/gui/src/mainWindow.cpp index 1a583f0b7f8..bfec4295e6c 100644 --- a/src/gui/src/mainWindow.cpp +++ b/src/gui/src/mainWindow.cpp @@ -49,7 +49,6 @@ #include #include #include -#include #include #include "browserWidget.h" @@ -449,9 +448,9 @@ void MainWindow::setDatabase(odb::dbDatabase* db) db_ = db; } -void MainWindow::setTitle(std::string title) +void MainWindow::setTitle(const std::string& title) { - window_title_ = std::move(title); + window_title_ = title; updateTitle(); } diff --git a/src/gui/src/mainWindow.h b/src/gui/src/mainWindow.h index c68d5e41a0b..06d7a8ef5c2 100644 --- a/src/gui/src/mainWindow.h +++ b/src/gui/src/mainWindow.h @@ -113,7 +113,7 @@ class MainWindow : public QMainWindow, public ord::OpenRoadObserver std::vector getRestoreTclCommands(); - void setTitle(std::string title); + void setTitle(const std::string& title); signals: // Signaled when we get a postRead callback to tell the sub-widgets From 4840de522ea6babe032982f88b9cc5f6efd2fd30 Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Tue, 17 Dec 2024 15:40:39 +0000 Subject: [PATCH 75/98] gui: improvements for pin & placement density heatmaps Address feedback in #6365 and clang-tidy heatMapPlacementDensity.* Cleaner handing of hierarchy with correct hierarchical transforms. Signed-off-by: Matt Liberty --- src/gui/src/heatMapPinDensity.cpp | 21 +++++------ src/gui/src/heatMapPlacementDensity.cpp | 23 +++++-------- src/gui/src/heatMapPlacementDensity.h | 46 ++++++++++++------------- 3 files changed, 38 insertions(+), 52 deletions(-) diff --git a/src/gui/src/heatMapPinDensity.cpp b/src/gui/src/heatMapPinDensity.cpp index bdf1c84a1f1..830ee988879 100644 --- a/src/gui/src/heatMapPinDensity.cpp +++ b/src/gui/src/heatMapPinDensity.cpp @@ -61,24 +61,19 @@ bool PinDensityDataSource::populateMap() = {{getBlock(), odb::dbTransform()}}; while (!blocks.empty()) { - auto [current_block, current_transform] = blocks.back(); + auto [block, transform] = blocks.back(); blocks.pop_back(); - const bool has_child_blocks = !current_block->getChildren().empty(); - - for (auto* inst : current_block->getInsts()) { + for (auto* inst : block->getInsts()) { if (!inst->getPlacementStatus().isPlaced()) { continue; } - odb::dbMaster* master = inst->getMaster(); - if (has_child_blocks) { - auto child = inst->getBlock()->findChild(master->getName().c_str()); - if (child) { - const odb::dbTransform child_transform = inst->getTransform(); - blocks.emplace_back(child, child_transform); - continue; - } + if (inst->isHierarchical()) { + odb::dbTransform child_transform = inst->getTransform(); + child_transform.concat(transform); + blocks.emplace_back(inst->getChild(), child_transform); + continue; } for (odb::dbITerm* iterm : inst->getITerms()) { @@ -96,7 +91,7 @@ bool PinDensityDataSource::populateMap() continue; } - current_transform.apply(bbox); + transform.apply(bbox); addToMap(bbox, 1); } } diff --git a/src/gui/src/heatMapPlacementDensity.cpp b/src/gui/src/heatMapPlacementDensity.cpp index e1d705e1d07..e4dff57eabf 100644 --- a/src/gui/src/heatMapPlacementDensity.cpp +++ b/src/gui/src/heatMapPlacementDensity.cpp @@ -44,10 +44,7 @@ PlacementDensityDataSource::PlacementDensityDataSource(utl::Logger* logger) : HeatMapDataSource(logger, "Placement Density", "Placement", - "PlacementDensity"), - include_taps_(true), - include_filler_(false), - include_io_(false) + "PlacementDensity") { addBooleanSetting( "Taps", @@ -78,12 +75,10 @@ bool PlacementDensityDataSource::populateMap() = {{getBlock(), odb::dbTransform()}}; while (!blocks.empty()) { - auto [current_block, current_transform] = blocks.back(); + auto [block, transform] = blocks.back(); blocks.pop_back(); - const bool has_child_blocks = !current_block->getChildren().empty(); - - for (auto* inst : current_block->getInsts()) { + for (auto* inst : block->getInsts()) { if (!inst->getPlacementStatus().isPlaced()) { continue; } @@ -100,16 +95,14 @@ bool PlacementDensityDataSource::populateMap() continue; } - odb::dbMaster* master = inst->getMaster(); - odb::dbBlock* child; - if (has_child_blocks - && (child = inst->getBlock()->findChild(master->getName().c_str()))) { - const odb::dbTransform child_transform = inst->getTransform(); - blocks.emplace_back(child, child_transform); + if (inst->isHierarchical()) { + odb::dbTransform child_transform = inst->getTransform(); + child_transform.concat(transform); + blocks.emplace_back(inst->getChild(), child_transform); continue; } odb::Rect inst_box = inst->getBBox()->getBox(); - current_transform.apply(inst_box); + transform.apply(inst_box); addToMap(inst_box, 100.0); } diff --git a/src/gui/src/heatMapPlacementDensity.h b/src/gui/src/heatMapPlacementDensity.h index 9cdf3b1bc63..9d1d36da178 100644 --- a/src/gui/src/heatMapPlacementDensity.h +++ b/src/gui/src/heatMapPlacementDensity.h @@ -44,38 +44,36 @@ class PlacementDensityDataSource : public HeatMapDataSource, { public: PlacementDensityDataSource(utl::Logger* logger); - ~PlacementDensityDataSource() {} - virtual void onShow() override; - virtual void onHide() override; + void onShow() override; + void onHide() override; // from dbBlockCallBackObj API - virtual void inDbInstCreate(odb::dbInst*) override; - virtual void inDbInstCreate(odb::dbInst*, odb::dbRegion*) override; - virtual void inDbInstDestroy(odb::dbInst*) override; - virtual void inDbInstPlacementStatusBefore( - odb::dbInst*, - const odb::dbPlacementStatus&) override; - virtual void inDbInstSwapMasterBefore(odb::dbInst*, odb::dbMaster*) override; - virtual void inDbInstSwapMasterAfter(odb::dbInst*) override; - virtual void inDbPreMoveInst(odb::dbInst*) override; - virtual void inDbPostMoveInst(odb::dbInst*) override; + void inDbInstCreate(odb::dbInst*) override; + void inDbInstCreate(odb::dbInst*, odb::dbRegion*) override; + void inDbInstDestroy(odb::dbInst*) override; + void inDbInstPlacementStatusBefore(odb::dbInst*, + const odb::dbPlacementStatus&) override; + void inDbInstSwapMasterBefore(odb::dbInst*, odb::dbMaster*) override; + void inDbInstSwapMasterAfter(odb::dbInst*) override; + void inDbPreMoveInst(odb::dbInst*) override; + void inDbPostMoveInst(odb::dbInst*) override; protected: - virtual bool populateMap() override; - virtual void combineMapData(bool base_has_value, - double& base, - const double new_data, - const double data_area, - const double intersection_area, - const double rect_area) override; + bool populateMap() override; + void combineMapData(bool base_has_value, + double& base, + double new_data, + double data_area, + double intersection_area, + double rect_area) override; - virtual bool destroyMapOnNotVisible() const override { return true; } + bool destroyMapOnNotVisible() const override { return true; } private: - bool include_taps_; - bool include_filler_; - bool include_io_; + bool include_taps_{true}; + bool include_filler_{false}; + bool include_io_{false}; }; } // namespace gui From 27bafe21bcebb904c6e1ba1d1974bde87280ebad Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Tue, 17 Dec 2024 10:38:47 -0700 Subject: [PATCH 76/98] rsz: use isLinkCell for filtering Signed-off-by: Peter Gadfort --- src/rsz/include/rsz/Resizer.hh | 2 +- src/rsz/src/Resizer.cc | 13 +++++-------- src/rsz/test/report_dont_use.ok | 4 ++-- src/rsz/test/report_dont_use_corners.ok | 4 ++-- 4 files changed, 10 insertions(+), 13 deletions(-) diff --git a/src/rsz/include/rsz/Resizer.hh b/src/rsz/include/rsz/Resizer.hh index 15575af187e..820c73800c5 100644 --- a/src/rsz/include/rsz/Resizer.hh +++ b/src/rsz/include/rsz/Resizer.hh @@ -262,7 +262,7 @@ class Resizer : public dbStaState void setDontUse(LibertyCell* cell, bool dont_use); bool dontUse(LibertyCell* cell); - void reportDontUse() const; + void reportDontUse(); void setDontTouch(const Instance* inst, bool dont_touch); bool dontTouch(const Instance* inst); void setDontTouch(const Net* net, bool dont_touch); diff --git a/src/rsz/src/Resizer.cc b/src/rsz/src/Resizer.cc index 0141d3b79e0..d929c392bdc 100644 --- a/src/rsz/src/Resizer.cc +++ b/src/rsz/src/Resizer.cc @@ -1803,21 +1803,18 @@ bool Resizer::dontUse(LibertyCell* cell) return cell->dontUse() || dont_use_.hasKey(cell); } -void Resizer::reportDontUse() const +void Resizer::reportDontUse() { logger_->report("Don't Use Cells:"); if (dont_use_.empty()) { logger_->report(" none"); } else { - std::set cells; - for (auto* cell : dont_use_) { - cells.insert(db_network_->staToDb(cell)); - } - - for (auto* cell : cells) { - logger_->report(" {}", cell->getName()); + if (!isLinkCell(cell)) { + continue; + } + logger_->report(" {}", cell->name()); } } } diff --git a/src/rsz/test/report_dont_use.ok b/src/rsz/test/report_dont_use.ok index 7fcca46dc20..f6b907cee8d 100644 --- a/src/rsz/test/report_dont_use.ok +++ b/src/rsz/test/report_dont_use.ok @@ -11,8 +11,8 @@ Don't Use Cells: CLKBUF_X2 CLKBUF_X3 INV_X1 - INV_X16 INV_X2 - INV_X32 INV_X4 INV_X8 + INV_X16 + INV_X32 diff --git a/src/rsz/test/report_dont_use_corners.ok b/src/rsz/test/report_dont_use_corners.ok index 7fcca46dc20..f6b907cee8d 100644 --- a/src/rsz/test/report_dont_use_corners.ok +++ b/src/rsz/test/report_dont_use_corners.ok @@ -11,8 +11,8 @@ Don't Use Cells: CLKBUF_X2 CLKBUF_X3 INV_X1 - INV_X16 INV_X2 - INV_X32 INV_X4 INV_X8 + INV_X16 + INV_X32 From 337da210b704f17212b695a582dc6ea9ba15fbce Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Tue, 17 Dec 2024 14:36:11 -0700 Subject: [PATCH 77/98] rsz: make isLinkCell const Signed-off-by: Peter Gadfort --- src/rsz/include/rsz/Resizer.hh | 4 ++-- src/rsz/src/Resizer.cc | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/rsz/include/rsz/Resizer.hh b/src/rsz/include/rsz/Resizer.hh index 820c73800c5..3c0ad1e7f2e 100644 --- a/src/rsz/include/rsz/Resizer.hh +++ b/src/rsz/include/rsz/Resizer.hh @@ -262,7 +262,7 @@ class Resizer : public dbStaState void setDontUse(LibertyCell* cell, bool dont_use); bool dontUse(LibertyCell* cell); - void reportDontUse(); + void reportDontUse() const; void setDontTouch(const Instance* inst, bool dont_touch); bool dontTouch(const Instance* inst); void setDontTouch(const Net* net, bool dont_touch); @@ -441,7 +441,7 @@ class Resizer : public dbStaState bool isTristateDriver(const Pin* pin); void checkLibertyForAllCorners(); void findBuffers(); - bool isLinkCell(LibertyCell* cell); + bool isLinkCell(LibertyCell* cell) const; void findTargetLoads(); void balanceBin(const vector& bin, const std::set& base_sites); diff --git a/src/rsz/src/Resizer.cc b/src/rsz/src/Resizer.cc index d929c392bdc..4412159931d 100644 --- a/src/rsz/src/Resizer.cc +++ b/src/rsz/src/Resizer.cc @@ -558,7 +558,7 @@ void Resizer::findBuffers() } } -bool Resizer::isLinkCell(LibertyCell* cell) +bool Resizer::isLinkCell(LibertyCell* cell) const { return network_->findLibertyCell(cell->name()) == cell; } @@ -1803,7 +1803,7 @@ bool Resizer::dontUse(LibertyCell* cell) return cell->dontUse() || dont_use_.hasKey(cell); } -void Resizer::reportDontUse() +void Resizer::reportDontUse() const { logger_->report("Don't Use Cells:"); From 51bec7d929c3ae42587d722c91d9bf2d6b80189a Mon Sep 17 00:00:00 2001 From: luis201420 Date: Tue, 17 Dec 2024 21:51:04 +0000 Subject: [PATCH 78/98] ant: avoiding saving violation reports when calling from GRT repair antennas Signed-off-by: luis201420 --- src/ant/include/ant/AntennaChecker.hh | 2 ++ src/ant/src/AntennaChecker.cc | 18 +++++++----------- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/src/ant/include/ant/AntennaChecker.hh b/src/ant/include/ant/AntennaChecker.hh index d604255b705..9b752642b5a 100644 --- a/src/ant/include/ant/AntennaChecker.hh +++ b/src/ant/include/ant/AntennaChecker.hh @@ -180,6 +180,7 @@ class AntennaChecker void buildLayerMaps(odb::dbNet* net, LayerToGraphNodes& node_by_layer_map); void checkNet(odb::dbNet* net, bool verbose, + bool save_report, odb::dbMTerm* diode_mterm, float ratio_margin, int& net_violation_count, @@ -203,6 +204,7 @@ class AntennaChecker void printReport(); int checkGates(odb::dbNet* db_net, bool verbose, + bool save_report, odb::dbMTerm* diode_mterm, float ratio_margin, GateToLayerToNodeInfo& gate_info, diff --git a/src/ant/src/AntennaChecker.cc b/src/ant/src/AntennaChecker.cc index 9021cba5efb..1a8cd46bebf 100644 --- a/src/ant/src/AntennaChecker.cc +++ b/src/ant/src/AntennaChecker.cc @@ -775,6 +775,7 @@ void AntennaChecker::printReport() int AntennaChecker::checkGates(odb::dbNet* db_net, bool verbose, + bool save_report, odb::dbMTerm* diode_mterm, float ratio_margin, GateToLayerToNodeInfo& gate_info, @@ -821,7 +822,7 @@ int AntennaChecker::checkGates(odb::dbNet* db_net, net_report.report += "\n"; } // Write report on map - { + if (save_report) { std::lock_guard lock(mapMutex); net_to_report_.at(db_net) = net_report; } @@ -1018,6 +1019,7 @@ void AntennaChecker::buildLayerMaps(odb::dbNet* db_net, void AntennaChecker::checkNet(odb::dbNet* db_net, bool verbose, + bool save_report, odb::dbMTerm* diode_mterm, float ratio_margin, int& net_violation_count, @@ -1037,6 +1039,7 @@ void AntennaChecker::checkNet(odb::dbNet* db_net, int pin_violations = checkGates(db_net, verbose, + save_report, diode_mterm, ratio_margin, gate_info, @@ -1058,18 +1061,11 @@ Violations AntennaChecker::getAntennaViolations(odb::dbNet* net, return antenna_violations; } - // for the case where the check_net_violation api is called directly - { - std::lock_guard lock(mapMutex); - if (net_to_report_.find(net) == net_to_report_.end()) { - net_to_report_[net]; - } - } - int net_violation_count, pin_violation_count; net_violation_count = 0; pin_violation_count = 0; checkNet(net, + false, false, diode_mterm, ratio_margin, @@ -1077,8 +1073,6 @@ Violations AntennaChecker::getAntennaViolations(odb::dbNet* net, pin_violation_count, antenna_violations); - std::lock_guard lock(mapMutex); - net_to_report_.clear(); return antenna_violations; } @@ -1122,6 +1116,7 @@ int AntennaChecker::checkAntennas(odb::dbNet* net, if (!net->isSpecial()) { checkNet(net, verbose, + true, nullptr, 0, net_violation_count, @@ -1146,6 +1141,7 @@ int AntennaChecker::checkAntennas(odb::dbNet* net, Violations antenna_violations; checkNet(net, verbose, + true, nullptr, 0, net_violation_count, From c5a5033d3ab4eea061956fff67d8c3c0e9857286 Mon Sep 17 00:00:00 2001 From: luis201420 Date: Tue, 17 Dec 2024 21:58:12 +0000 Subject: [PATCH 79/98] ant: renaming mutex variable for name pattern Signed-off-by: luis201420 --- src/ant/include/ant/AntennaChecker.hh | 2 +- src/ant/src/AntennaChecker.cc | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/ant/include/ant/AntennaChecker.hh b/src/ant/include/ant/AntennaChecker.hh index 9b752642b5a..9a0ef13c521 100644 --- a/src/ant/include/ant/AntennaChecker.hh +++ b/src/ant/include/ant/AntennaChecker.hh @@ -247,7 +247,7 @@ class AntennaChecker std::string report_file_name_; std::vector nets_; std::map net_to_report_; - std::mutex mapMutex; + std::mutex map_mutex_; // consts static constexpr int max_diode_count_per_gate = 10; }; diff --git a/src/ant/src/AntennaChecker.cc b/src/ant/src/AntennaChecker.cc index 1a8cd46bebf..18a2c6b0a05 100644 --- a/src/ant/src/AntennaChecker.cc +++ b/src/ant/src/AntennaChecker.cc @@ -100,7 +100,7 @@ void AntennaChecker::initAntennaRules() odb::dbTech* tech = db_->getTech(); // initialize nets_to_report_ with all nets to avoid issues with // multithreading - std::lock_guard lock(mapMutex); + std::lock_guard lock(map_mutex_); if (net_to_report_.empty()) { for (odb::dbNet* net : block_->getNets()) { if (!net->isSpecial()) { @@ -755,7 +755,7 @@ bool AntennaChecker::checkRatioViolations(odb::dbNet* db_net, void AntennaChecker::writeReport(std::ofstream& report_file, bool verbose) { - std::lock_guard lock(mapMutex); + std::lock_guard lock(map_mutex_); for (const auto& [net, violation_report] : net_to_report_) { if (verbose || violation_report.violated) { report_file << violation_report.report; @@ -765,7 +765,7 @@ void AntennaChecker::writeReport(std::ofstream& report_file, bool verbose) void AntennaChecker::printReport() { - std::lock_guard lock(mapMutex); + std::lock_guard lock(map_mutex_); for (const auto& [net, violation_report] : net_to_report_) { if (violation_report.violated) { logger_->report("{}", violation_report.report); @@ -823,7 +823,7 @@ int AntennaChecker::checkGates(odb::dbNet* db_net, } // Write report on map if (save_report) { - std::lock_guard lock(mapMutex); + std::lock_guard lock(map_mutex_); net_to_report_.at(db_net) = net_report; } @@ -1081,7 +1081,7 @@ int AntennaChecker::checkAntennas(odb::dbNet* net, bool verbose) { { - std::lock_guard lock(mapMutex); + std::lock_guard lock(map_mutex_); net_to_report_.clear(); } initAntennaRules(); From 5ecb42d795d7fa783fbb7952c62ee1645df5e1a4 Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Wed, 18 Dec 2024 07:42:11 +0000 Subject: [PATCH 80/98] drt: make frViaDef const in frVia and general cleanup in rp/ Signed-off-by: Matt Liberty --- src/drt/src/TritonRoute.cpp | 2 +- src/drt/src/db/drObj/drAccessPattern.h | 9 +- src/drt/src/db/drObj/drVia.h | 8 +- src/drt/src/db/grObj/grVia.h | 6 +- src/drt/src/db/obj/frAccess.cpp | 4 +- src/drt/src/db/obj/frAccess.h | 12 +- src/drt/src/db/obj/frVia.h | 8 +- src/drt/src/db/taObj/taVia.h | 8 +- src/drt/src/db/tech/frLayer.h | 23 +- src/drt/src/distributed/drUpdate.h | 2 +- src/drt/src/dr/FlexDR.h | 2 +- src/drt/src/dr/FlexDR_init.cpp | 2 +- src/drt/src/dr/FlexDR_maze.cpp | 23 +- src/drt/src/dr/FlexGridGraph.cpp | 6 +- src/drt/src/gr/FlexGR_init.cpp | 4 +- src/drt/src/io/io.cpp | 4 +- src/drt/src/io/io.h | 4 +- src/drt/src/io/io_parser_helper.cpp | 16 +- src/drt/src/pa/FlexPA.h | 7 +- src/drt/src/pa/FlexPA_acc_point.cpp | 10 +- src/drt/src/pa/FlexPA_init.cpp | 4 +- src/drt/src/rp/FlexRP.cpp | 10 + src/drt/src/rp/FlexRP.h | 72 ++-- src/drt/src/rp/FlexRP_init.cpp | 4 +- src/drt/src/rp/FlexRP_prep.cpp | 555 ++++++++++++------------- src/drt/src/serialization.h | 2 +- src/drt/src/ta/FlexTA.h | 2 +- src/drt/src/ta/FlexTA_assign.cpp | 7 +- src/drt/src/ta/FlexTA_init.cpp | 4 +- 29 files changed, 399 insertions(+), 421 deletions(-) diff --git a/src/drt/src/TritonRoute.cpp b/src/drt/src/TritonRoute.cpp index 6c636a27fef..330d6a30764 100644 --- a/src/drt/src/TritonRoute.cpp +++ b/src/drt/src/TritonRoute.cpp @@ -610,7 +610,7 @@ void TritonRoute::initDesign() void TritonRoute::prep() { - FlexRP rp(getDesign(), getDesign()->getTech(), logger_, router_cfg_.get()); + FlexRP rp(getDesign(), logger_, router_cfg_.get()); rp.main(); } diff --git a/src/drt/src/db/drObj/drAccessPattern.h b/src/drt/src/db/drObj/drAccessPattern.h index f24b5be891e..576a08ac716 100644 --- a/src/drt/src/db/drObj/drAccessPattern.h +++ b/src/drt/src/db/drObj/drAccessPattern.h @@ -52,7 +52,7 @@ class drAccessPattern : public drBlockObject { return (dir == frDirEnum::U) ? vU_ : vD_; } - frViaDef* getAccessViaDef(const frDirEnum& dir = frDirEnum::U) + const frViaDef* getAccessViaDef(const frDirEnum& dir = frDirEnum::U) { return (dir == frDirEnum::U) ? (*vU_)[vUIdx_] : (*vD_)[vDIdx_]; } @@ -68,7 +68,8 @@ class drAccessPattern : public drBlockObject void setPin(drPin* in) { pin_ = in; } void setValidAccess(const std::vector& in) { validAccess_ = in; } - void setAccessViaDef(const frDirEnum dir, std::vector* viaDef) + void setAccessViaDef(const frDirEnum dir, + std::vector* viaDef) { if (dir == frDirEnum::U) { vU_ = viaDef; @@ -96,8 +97,8 @@ class drAccessPattern : public drBlockObject FlexMazeIdx mazeIdx_; drPin* pin_{nullptr}; std::vector validAccess_ = std::vector(6, true); - std::vector* vU_{nullptr}; - std::vector* vD_{nullptr}; + std::vector* vU_{nullptr}; + std::vector* vD_{nullptr}; int vUIdx_{0}; int vDIdx_{0}; bool onTrackX_{true}; // initialized in initMazeIdx_ap diff --git a/src/drt/src/db/drObj/drVia.h b/src/drt/src/db/drObj/drVia.h index 0a12682ea4c..f0c30270109 100644 --- a/src/drt/src/db/drObj/drVia.h +++ b/src/drt/src/db/drObj/drVia.h @@ -44,11 +44,11 @@ class drVia : public drRef public: // constructors drVia() = default; - drVia(frViaDef* in) : viaDef_(in) {} + drVia(const frViaDef* in) : viaDef_(in) {} drVia(const drVia& in) = default; drVia(const frVia& in); // getters - frViaDef* getViaDef() const { return viaDef_; } + const frViaDef* getViaDef() const { return viaDef_; } Rect getLayer1BBox() const { Rect box; @@ -80,7 +80,7 @@ class drVia : public drRef return box; } // setters - void setViaDef(frViaDef* in) { viaDef_ = in; } + void setViaDef(const frViaDef* in) { viaDef_ = in; } // others frBlockObjectEnum typeId() const override { return drcVia; } @@ -165,7 +165,7 @@ class drVia : public drRef protected: Point origin_; - frViaDef* viaDef_{nullptr}; + const frViaDef* viaDef_{nullptr}; drBlockObject* owner_{nullptr}; FlexMazeIdx beginMazeIdx_; FlexMazeIdx endMazeIdx_; diff --git a/src/drt/src/db/grObj/grVia.h b/src/drt/src/db/grObj/grVia.h index aec2462245c..266081d9d10 100644 --- a/src/drt/src/db/grObj/grVia.h +++ b/src/drt/src/db/grObj/grVia.h @@ -51,10 +51,10 @@ class grVia : public grRef } // getters - frViaDef* getViaDef() const { return viaDef; } + const frViaDef* getViaDef() const { return viaDef; } // setters - void setViaDef(frViaDef* in) { viaDef = in; } + void setViaDef(const frViaDef* in) { viaDef = in; } // others frBlockObjectEnum typeId() const override { return grcVia; } @@ -150,7 +150,7 @@ class grVia : public grRef protected: Point origin; - frViaDef* viaDef{nullptr}; + const frViaDef* viaDef{nullptr}; frBlockObject* child{nullptr}; frBlockObject* parent{nullptr}; frBlockObject* owner{nullptr}; diff --git a/src/drt/src/db/obj/frAccess.cpp b/src/drt/src/db/obj/frAccess.cpp index 3bf1ae7dd11..9d9e0b003a2 100644 --- a/src/drt/src/db/obj/frAccess.cpp +++ b/src/drt/src/db/obj/frAccess.cpp @@ -34,7 +34,7 @@ namespace drt { -void frAccessPoint::addViaDef(frViaDef* in) +void frAccessPoint::addViaDef(const frViaDef* in) { auto numCut = in->getNumCut(); int numCutIdx = numCut - 1; @@ -62,7 +62,7 @@ void frAccessPoint::serialize(Archive& ar, const unsigned int version) int inSz = 0; (ar) & inSz; while (inSz--) { - frViaDef* vd; + const frViaDef* vd; serializeViaDef(ar, vd); viaDefs_[i].push_back(vd); } diff --git a/src/drt/src/db/obj/frAccess.h b/src/drt/src/db/obj/frAccess.h index 3d6a376007e..49d36a03d9d 100644 --- a/src/drt/src/db/obj/frAccess.h +++ b/src/drt/src/db/obj/frAccess.h @@ -111,15 +111,15 @@ class frAccessPoint : public frBlockObject // e.g., getViaDefs() --> get all one-cut viadefs // e.g., getViaDefs(1) --> get all one-cut viadefs // e.g., getViaDefs(2) --> get all two-cut viadefs - const std::vector& getViaDefs(int numCut = 1) const + const std::vector& getViaDefs(int numCut = 1) const { return viaDefs_[numCut - 1]; } - std::vector& getViaDefs(int numCut = 1) + std::vector& getViaDefs(int numCut = 1) { return viaDefs_[numCut - 1]; } - const std::vector>& getAllViaDefs() const + const std::vector>& getAllViaDefs() const { return viaDefs_; } @@ -127,7 +127,7 @@ class frAccessPoint : public frBlockObject // e.g., getViaDef(1) --> get best one-cut viadef // e.g., getViaDef(2) --> get best two-cut viadef // e.g., getViaDef(1, 1) --> get 1st alternative one-cut viadef - frViaDef* getViaDef(int numCut = 1, int idx = 0) const + const frViaDef* getViaDef(int numCut = 1, int idx = 0) const { return viaDefs_[numCut - 1][idx]; } @@ -176,7 +176,7 @@ class frAccessPoint : public frBlockObject setAccess(dirArray[i], isValid); } } - void addViaDef(frViaDef* in); + void addViaDef(const frViaDef* in); void addToPinAccess(frPinAccess* in) { aps_ = in; } void setType(frAccessPointEnum in, bool isL = true) { @@ -201,7 +201,7 @@ class frAccessPoint : public frBlockObject // 0 = E, 1 = S, 2 = W, 3 = N, 4 = U, 5 = D std::vector accesses_ = std::vector(6, false); // cut number -> up-via access map - std::vector> viaDefs_; + std::vector> viaDefs_; frAccessPointEnum typeL_{frAccessPointEnum::OnGrid}; frAccessPointEnum typeH_{frAccessPointEnum::OnGrid}; frPinAccess* aps_{nullptr}; diff --git a/src/drt/src/db/obj/frVia.h b/src/drt/src/db/obj/frVia.h index ba9c7602a2e..5bd86f7ce60 100644 --- a/src/drt/src/db/obj/frVia.h +++ b/src/drt/src/db/obj/frVia.h @@ -42,7 +42,7 @@ class frVia : public frRef public: // constructors frVia() = default; - frVia(frViaDef* in) : viaDef_(in) {} + frVia(const frViaDef* in) : viaDef_(in) {} frVia(const frVia& in) : frRef(in), origin_(in.origin_), @@ -56,7 +56,7 @@ class frVia : public frRef } frVia(const drVia& in); // getters - frViaDef* getViaDef() const { return viaDef_; } + const frViaDef* getViaDef() const { return viaDef_; } Rect getLayer1BBox() const { Rect box; @@ -88,7 +88,7 @@ class frVia : public frRef return box; } // setters - void setViaDef(frViaDef* in) { viaDef_ = in; } + void setViaDef(const frViaDef* in) { viaDef_ = in; } // others frBlockObjectEnum typeId() const override { return frcVia; } @@ -232,7 +232,7 @@ class frVia : public frRef private: Point origin_; - frViaDef* viaDef_{nullptr}; + const frViaDef* viaDef_{nullptr}; frBlockObject* owner_{nullptr}; frListIter> iter_; int index_in_owner_{0}; diff --git a/src/drt/src/db/taObj/taVia.h b/src/drt/src/db/taObj/taVia.h index 9f4d651c09e..2377f622098 100644 --- a/src/drt/src/db/taObj/taVia.h +++ b/src/drt/src/db/taObj/taVia.h @@ -55,9 +55,9 @@ class taVia : public taRef public: // constructors taVia() = default; - taVia(frViaDef* in) : viaDef_(in) {} + taVia(const frViaDef* in) : viaDef_(in) {} // getters - frViaDef* getViaDef() const { return viaDef_; } + const frViaDef* getViaDef() const { return viaDef_; } Rect getLayer1BBox() const { Rect box; @@ -89,7 +89,7 @@ class taVia : public taRef return box; } // setters - void setViaDef(frViaDef* in) { viaDef_ = in; } + void setViaDef(const frViaDef* in) { viaDef_ = in; } // others frBlockObjectEnum typeId() const override { return tacVia; } @@ -213,7 +213,7 @@ class taVia : public taRef protected: Point origin_; - frViaDef* viaDef_{nullptr}; + const frViaDef* viaDef_{nullptr}; frBlockObject* owner_{nullptr}; }; } // namespace drt diff --git a/src/drt/src/db/tech/frLayer.h b/src/drt/src/db/tech/frLayer.h index e0631e4dd69..c02827ccb55 100644 --- a/src/drt/src/db/tech/frLayer.h +++ b/src/drt/src/db/tech/frLayer.h @@ -55,14 +55,17 @@ class frLayer void setLayerNum(frLayerNum layerNumIn) { layerNum_ = layerNumIn; } void setWidth(frUInt4 widthIn) { width_ = widthIn; } void setMinWidth(frUInt4 minWidthIn) { minWidth_ = minWidthIn; } - void setDefaultViaDef(frViaDef* in) { defaultViaDef_ = in; } - void addSecondaryViaDef(frViaDef* in) { secondaryViaDefs_.emplace_back(in); } - const std::vector& getSecondaryViaDefs() const + void setDefaultViaDef(const frViaDef* in) { defaultViaDef_ = in; } + void addSecondaryViaDef(const frViaDef* in) + { + secondaryViaDefs_.emplace_back(in); + } + const std::vector& getSecondaryViaDefs() const { return secondaryViaDefs_; } void addConstraint(frConstraint* consIn) { constraints_.push_back(consIn); } - void addViaDef(frViaDef* viaDefIn) { viaDefs_.insert(viaDefIn); } + void addViaDef(const frViaDef* viaDefIn) { viaDefs_.insert(viaDefIn); } void setHasVia2ViaMinStepViol(bool in) { hasMinStepViol_ = in; } void setUnidirectional(bool in) { unidirectional_ = in; } // getters @@ -128,13 +131,13 @@ class frLayer style.setEndStyle(frcExtendEndStyle, width_ / 2); return style; } - frViaDef* getDefaultViaDef() const { return defaultViaDef_; } - frViaDef* getSecondaryViaDef(int idx) const + const frViaDef* getDefaultViaDef() const { return defaultViaDef_; } + const frViaDef* getSecondaryViaDef(int idx) const { return secondaryViaDefs_.at(idx); } bool hasVia2ViaMinStepViol() { return hasMinStepViol_; } - std::set getViaDefs() const { return viaDefs_; } + std::set getViaDefs() const { return viaDefs_; } dbTechLayerType getType() const { if (fakeCut_) { @@ -853,11 +856,11 @@ class frLayer frUInt4 width_{0}; frUInt4 wrongDirWidth_{0}; frUInt4 minWidth_{0}; - frViaDef* defaultViaDef_{nullptr}; - std::vector secondaryViaDefs_; + const frViaDef* defaultViaDef_{nullptr}; + std::vector secondaryViaDefs_; bool hasMinStepViol_{false}; bool unidirectional_{false}; - std::set viaDefs_; + std::set viaDefs_; std::vector cutClasses_; std::map name2CutClassIdxMap_; frCollection constraints_; diff --git a/src/drt/src/distributed/drUpdate.h b/src/drt/src/distributed/drUpdate.h index 959dc6824e9..bd0b32616af 100644 --- a/src/drt/src/distributed/drUpdate.h +++ b/src/drt/src/distributed/drUpdate.h @@ -82,7 +82,7 @@ class drUpdate bool bottomConnected_{false}; bool topConnected_{false}; bool tapered_{false}; - frViaDef* viaDef_{nullptr}; + const frViaDef* viaDef_{nullptr}; frBlockObjectEnum obj_type_{frcBlock}; frMarker marker_; diff --git a/src/drt/src/dr/FlexDR.h b/src/drt/src/dr/FlexDR.h index 6a3620ad87a..624cd910197 100644 --- a/src/drt/src/dr/FlexDR.h +++ b/src/drt/src/dr/FlexDR.h @@ -853,7 +853,7 @@ class FlexDRWorker ModCostType type, frCoord width, frCoord minSpacing, - frViaDef* viaDef, + const frViaDef* viaDef, drEolSpacingConstraint drCon, bool isUpperVia, bool isCurrPs, diff --git a/src/drt/src/dr/FlexDR_init.cpp b/src/drt/src/dr/FlexDR_init.cpp index 5a0af3101fc..6fef352c4e0 100644 --- a/src/drt/src/dr/FlexDR_init.cpp +++ b/src/drt/src/dr/FlexDR_init.cpp @@ -3127,7 +3127,7 @@ void FlexDRWorker::initMazeCost_via_helper(drNet* net, bool isAddPathCost) } const Point bp = minCostAP->getPoint(); - frViaDef* viaDef = minCostAP->getAccessViaDef(); + const frViaDef* viaDef = minCostAP->getAccessViaDef(); via = std::make_unique(viaDef); via->setOrigin(bp); via->addToNet(net); diff --git a/src/drt/src/dr/FlexDR_maze.cpp b/src/drt/src/dr/FlexDR_maze.cpp index 8729ac35436..0b15c41e6a2 100644 --- a/src/drt/src/dr/FlexDR_maze.cpp +++ b/src/drt/src/dr/FlexDR_maze.cpp @@ -537,7 +537,7 @@ void FlexDRWorker::modMinimumcutCostVia(const Rect& box, frCoord width1 = box.minDXDY(); frCoord length1 = box.maxDXDY(); // default via dimension - frViaDef* viaDef = nullptr; + const frViaDef* viaDef = nullptr; if (isUpperVia) { viaDef = (lNum < gridGraph_.getMaxLayerNum()) ? getTech()->getLayer(lNum + 1)->getDefaultViaDef() @@ -659,7 +659,7 @@ void FlexDRWorker::modMinSpacingCostVia(const Rect& box, { // mod costs for non-NDR nets auto lNum = gridGraph_.getLayerNum(z); - frViaDef* defaultViaDef = nullptr; + const frViaDef* defaultViaDef = nullptr; if (isUpperVia) { defaultViaDef = (lNum < gridGraph_.getMaxLayerNum()) ? getTech()->getLayer(lNum + 1)->getDefaultViaDef() @@ -690,7 +690,7 @@ void FlexDRWorker::modMinSpacingCostVia(const Rect& box, // mod costs for ndrs for (auto ndr : ndrs_) { frCoord width = defaultWidth; - frViaDef* viadef = defaultViaDef; + const frViaDef* viadef = defaultViaDef; frCoord minSpacing = defaultMinSpacing; drEolSpacingConstraint ndrDrCon = ndr->getDrEolSpacingConstraint(z); if (isUpperVia && lNum < gridGraph_.getMaxLayerNum() @@ -723,7 +723,7 @@ void FlexDRWorker::modMinSpacingCostViaHelper(const Rect& box, ModCostType type, frCoord width, frCoord minSpacing, - frViaDef* viaDef, + const frViaDef* viaDef, drEolSpacingConstraint drCon, bool isUpperVia, bool isCurrPs, @@ -884,7 +884,7 @@ void FlexDRWorker::modEolSpacingCost_helper(const Rect& testbox, testbox.yMax() + halfwidth2 - 1); } else { // default via dimension - frViaDef* viaDef = nullptr; + const frViaDef* viaDef = nullptr; if (eolType == 1) { viaDef = (lNum > getTech()->getBottomLayerNum()) ? getTech()->getLayer(lNum - 1)->getDefaultViaDef() @@ -1184,7 +1184,7 @@ void FlexDRWorker::modAdjCutSpacingCost_fixedObj(const frDesign* design, // obj1 = curr obj // obj2 = other obj // default via dimension - frViaDef* viaDef = cutLayer->getDefaultViaDef(); + const frViaDef* viaDef = cutLayer->getDefaultViaDef(); frVia via(viaDef); Rect viaBox = via.getCutBBox(); @@ -1345,8 +1345,7 @@ void FlexDRWorker::modInterLayerCutSpacingCost(const Rect& box, frLayer* layer1 = getTech()->getLayer(cutLayerNum1); frLayer* layer2 = getTech()->getLayer(cutLayerNum2); - frViaDef* viaDef = nullptr; - viaDef = layer2->getDefaultViaDef(); + const frViaDef* viaDef = layer2->getDefaultViaDef(); if (viaDef == nullptr) { return; @@ -2010,7 +2009,7 @@ void FlexDRWorker::route_queue_main(std::queue& rerouteQueue) if (old_via->isLonely()) { auto cutLayer = getTech()->getLayer(old_via->getViaDef()->getCutLayerNum()); - frViaDef* replacement_via_def = nullptr; + const frViaDef* replacement_via_def = nullptr; if (cutLayer->getSecondaryViaDefs().size() <= numReroute) // no more secViaDefs to try { @@ -3177,9 +3176,9 @@ void FlexDRWorker::routeNet_AddCutSpcCost(std::vector& path) for (uint64_t i = 1; i < path.size(); i++) { if (path[i].z() != path[i - 1].z()) { frMIdx z = std::min(path[i].z(), path[i - 1].z()); - frViaDef* viaDef = design_->getTech() - ->getLayer(gridGraph_.getLayerNum(z) + 1) - ->getDefaultViaDef(); + const frViaDef* viaDef = design_->getTech() + ->getLayer(gridGraph_.getLayerNum(z) + 1) + ->getDefaultViaDef(); int x = gridGraph_.xCoord(path[i].x()); int y = gridGraph_.yCoord(path[i].y()); dbTransform xform(Point(x, y)); diff --git a/src/drt/src/dr/FlexGridGraph.cpp b/src/drt/src/dr/FlexGridGraph.cpp index 473a794fd0c..21686c29177 100644 --- a/src/drt/src/dr/FlexGridGraph.cpp +++ b/src/drt/src/dr/FlexGridGraph.cpp @@ -113,7 +113,7 @@ bool FlexGridGraph::outOfDieVia(frMIdx x, if (lNum > getTech()->getTopLayerNum()) { return false; } - frViaDef* via = getTech()->getLayer(lNum)->getDefaultViaDef(); + const frViaDef* via = getTech()->getLayer(lNum)->getDefaultViaDef(); if (!via) { return true; } @@ -130,7 +130,7 @@ bool FlexGridGraph::hasOutOfDieViol(frMIdx x, frMIdx y, frMIdx z) } Rect testBoxUp; if (lNum + 1 <= getTech()->getTopLayerNum()) { - frViaDef* via = getTech()->getLayer(lNum + 1)->getDefaultViaDef(); + const frViaDef* via = getTech()->getLayer(lNum + 1)->getDefaultViaDef(); if (via) { testBoxUp = via->getLayer1ShapeBox(); testBoxUp.merge(via->getLayer2ShapeBox()); @@ -142,7 +142,7 @@ bool FlexGridGraph::hasOutOfDieViol(frMIdx x, frMIdx y, frMIdx z) } Rect testBoxDown; if (lNum - 1 >= getTech()->getBottomLayerNum()) { - frViaDef* via = getTech()->getLayer(lNum - 1)->getDefaultViaDef(); + const frViaDef* via = getTech()->getLayer(lNum - 1)->getDefaultViaDef(); if (via) { testBoxDown = via->getLayer1ShapeBox(); testBoxDown.merge(via->getLayer2ShapeBox()); diff --git a/src/drt/src/gr/FlexGR_init.cpp b/src/drt/src/gr/FlexGR_init.cpp index d07a7d6d6a1..2af26ec78bb 100644 --- a/src/drt/src/gr/FlexGR_init.cpp +++ b/src/drt/src/gr/FlexGR_init.cpp @@ -82,8 +82,8 @@ void FlexGR::initLayerPitch() } // calculate line-2-via pitch - frViaDef* downVia = nullptr; - frViaDef* upVia = nullptr; + const frViaDef* downVia = nullptr; + const frViaDef* upVia = nullptr; if (getDesign()->getTech()->getBottomLayerNum() <= lNum - 1) { downVia = getDesign()->getTech()->getLayer(lNum - 1)->getDefaultViaDef(); } diff --git a/src/drt/src/io/io.cpp b/src/drt/src/io/io.cpp index 171a82d3e9c..acf14dda331 100644 --- a/src/drt/src/io/io.cpp +++ b/src/drt/src/io/io.cpp @@ -3466,7 +3466,7 @@ void io::Writer::fillConnFigs(bool isTA, int verbose) void io::Writer::writeViaDefToODB(odb::dbBlock* block, odb::dbTech* db_tech, - frViaDef* via) + const frViaDef* via) { if (!via->isAddedByRouter()) { return; @@ -3984,7 +3984,7 @@ void io::TopLayerBTermHandler::stackVias(odb::dbBTerm* bterm, for (auto layer : tech->getLayers()) { if (layer->getType() == odb::dbTechLayerType::CUT) { frLayer* fr_layer = fr_tech->getLayer(layer->getName()); - frViaDef* via_def = fr_layer->getDefaultViaDef(); + const frViaDef* via_def = fr_layer->getDefaultViaDef(); if (via_def == nullptr) { logger_->warn(utl::DRT, 204, diff --git a/src/drt/src/io/io.h b/src/drt/src/io/io.h index 7161d59d65f..a6ab56ce1e7 100644 --- a/src/drt/src/io/io.h +++ b/src/drt/src/io/io.h @@ -139,7 +139,7 @@ class Parser bool& foundCenterTracks, bool& hasPolys); void checkPins(); - void getViaRawPriority(frViaDef* viaDef, viaRawPriorityTuple& priority); + void getViaRawPriority(const frViaDef* viaDef, viaRawPriorityTuple& priority); void initDefaultVias_GF14(const std::string& node); void initCutLayerWidth(); void initConstraintLayerIdx(); @@ -203,7 +203,7 @@ class Writer void updateDbConn(odb::dbBlock* block, odb::dbTech* db_tech, bool snapshot); void writeViaDefToODB(odb::dbBlock* block, odb::dbTech* db_tech, - frViaDef* via); + const frViaDef* via); void updateDbAccessPoints(odb::dbBlock* block, odb::dbTech* db_tech); void updateDbAccessPoint(odb::dbAccessPoint* db_ap, frAccessPoint* ap, diff --git a/src/drt/src/io/io_parser_helper.cpp b/src/drt/src/io/io_parser_helper.cpp index 6879c2be72f..e3b4f3b06f1 100644 --- a/src/drt/src/io/io_parser_helper.cpp +++ b/src/drt/src/io/io_parser_helper.cpp @@ -103,9 +103,10 @@ void io::Parser::initDefaultVias() continue; } // Check whether viaDefs set is empty - std::set viaDefs = layer->getViaDefs(); + std::set viaDefs = layer->getViaDefs(); if (!viaDefs.empty()) { - std::map> cuts2ViaDefs; + std::map> + cuts2ViaDefs; for (auto& viaDef : viaDefs) { int cutNum = int(viaDef->getCutFigs().size()); viaRawPriorityTuple priority; @@ -280,9 +281,10 @@ void io::Parser::initSecondaryVias() if (!has_default_viadef || !has_max_spacing_constraints) { continue; } - std::set viadefs = layer->getViaDefs(); + std::set viadefs = layer->getViaDefs(); if (!viadefs.empty()) { - std::map> cuts_to_viadefs; + std::map> + cuts_to_viadefs; for (auto& viadef : viadefs) { int cut_num = int(viadef->getCutFigs().size()); viaRawPriorityTuple priority; @@ -486,7 +488,7 @@ void io::Parser::initCutLayerWidth() } } -void io::Parser::getViaRawPriority(frViaDef* viaDef, +void io::Parser::getViaRawPriority(const frViaDef* viaDef, viaRawPriorityTuple& priority) { bool isNotDefaultVia = !(viaDef->getDefault()); @@ -669,11 +671,11 @@ void io::Parser::convertLef58MinCutConstraints() = std::make_unique(); auto rptr = static_cast(uCon.get()); if (dbRule->isPerCutClass()) { - frViaDef* viaDefBelow = nullptr; + const frViaDef* viaDefBelow = nullptr; if (lNum > bottomLayerNum) { viaDefBelow = getTech()->getLayer(lNum - 1)->getDefaultViaDef(); } - frViaDef* viaDefAbove = nullptr; + const frViaDef* viaDefAbove = nullptr; if (lNum < topLayerNum) { viaDefAbove = getTech()->getLayer(lNum + 1)->getDefaultViaDef(); } diff --git a/src/drt/src/pa/FlexPA.h b/src/drt/src/pa/FlexPA.h index 3ba4a63fc11..bf1735ceee6 100644 --- a/src/drt/src/pa/FlexPA.h +++ b/src/drt/src/pa/FlexPA.h @@ -108,7 +108,8 @@ class FlexPA // helper structures std::vector> track_coords_; - std::map>> + std::map>> layer_num_to_via_defs_; frCollection target_insts_; @@ -126,7 +127,7 @@ class FlexPA unique_insts_.setDesign(in); } void applyPatternsFile(const char* file_path); - ViaRawPriorityTuple getViaRawPriority(frViaDef* via_def); + ViaRawPriorityTuple getViaRawPriority(const frViaDef* via_def); bool isSkipInstTermLocal(frInstTerm* in); bool isSkipInstTerm(frInstTerm* in); bool isDistributed() const { return !remote_host_.empty(); } @@ -156,7 +157,7 @@ class FlexPA const Point& pt, frLayerNum layer_num, const gtl::polygon_90_set_data& polyset, - std::vector>& via_defs); + std::vector>& via_defs); /** * @brief fully initializes a pin's access points diff --git a/src/drt/src/pa/FlexPA_acc_point.cpp b/src/drt/src/pa/FlexPA_acc_point.cpp index 73b356e7e8c..66034f79e81 100644 --- a/src/drt/src/pa/FlexPA_acc_point.cpp +++ b/src/drt/src/pa/FlexPA_acc_point.cpp @@ -133,7 +133,7 @@ void FlexPA::genAPEnclosedBoundary(std::map& coords, return; } // hardcode first two single vias - std::vector via_defs; + std::vector via_defs; int cnt = 0; for (auto& [tup, via] : layer_num_to_via_defs_[layer_num + 1][1]) { via_defs.push_back(via); @@ -741,7 +741,7 @@ void FlexPA::getViasFromMetalWidthMap( const Point& pt, const frLayerNum layer_num, const gtl::polygon_90_set_data& polyset, - std::vector>& via_defs) + std::vector>& via_defs) { const auto tech = getTech(); if (layer_num == tech->getTopLayerNum()) { @@ -840,7 +840,7 @@ void FlexPA::check_addViaAccess( } const int max_num_via_trial = 2; // use std:pair to ensure deterministic behavior - std::vector> via_defs; + std::vector> via_defs; getViasFromMetalWidthMap(begin_point, layer_num, polyset, via_defs); if (via_defs.empty()) { // no via map entry @@ -853,7 +853,7 @@ void FlexPA::check_addViaAccess( } } - std::set> valid_via_defs; + std::set> valid_via_defs; for (auto& [idx, via_def] : via_defs) { auto via = std::make_unique(via_def); via->setOrigin(begin_point); @@ -1515,4 +1515,4 @@ void FlexPA::revertAccessPoints() } } -} // namespace drt \ No newline at end of file +} // namespace drt diff --git a/src/drt/src/pa/FlexPA_init.cpp b/src/drt/src/pa/FlexPA_init.cpp index c8cdf5ae964..b0c6efefb78 100644 --- a/src/drt/src/pa/FlexPA_init.cpp +++ b/src/drt/src/pa/FlexPA_init.cpp @@ -45,7 +45,7 @@ void FlexPA::initViaRawPriority() != dbTechLayerType::CUT) { continue; } - for (auto& via_def : + for (const auto& via_def : design_->getTech()->getLayer(layer_num)->getViaDefs()) { const int cutNum = int(via_def->getCutFigs().size()); const ViaRawPriorityTuple priority = getViaRawPriority(via_def); @@ -54,7 +54,7 @@ void FlexPA::initViaRawPriority() } } -ViaRawPriorityTuple FlexPA::getViaRawPriority(frViaDef* via_def) +ViaRawPriorityTuple FlexPA::getViaRawPriority(const frViaDef* via_def) { const bool is_not_default_via = !(via_def->getDefault()); gtl::polygon_90_set_data via_layer_ps1; diff --git a/src/drt/src/rp/FlexRP.cpp b/src/drt/src/rp/FlexRP.cpp index 5e415a5fd4e..0a1709fe4af 100644 --- a/src/drt/src/rp/FlexRP.cpp +++ b/src/drt/src/rp/FlexRP.cpp @@ -32,6 +32,16 @@ namespace drt { +FlexRP::FlexRP(frDesign* design, + Logger* logger, + RouterConfiguration* router_cfg) + : design_(design), + tech_(design->getTech()), + logger_(logger), + router_cfg_(router_cfg) +{ +} + void FlexRP::main() { ProfileTask profile("RP:main"); diff --git a/src/drt/src/rp/FlexRP.h b/src/drt/src/rp/FlexRP.h index 28f5e9583e6..4169d2afa43 100644 --- a/src/drt/src/rp/FlexRP.h +++ b/src/drt/src/rp/FlexRP.h @@ -36,28 +36,11 @@ namespace drt { class FlexRP { public: - // constructor - FlexRP(frDesign* designIn, - frTechObject* techIn, - Logger* logger, - RouterConfiguration* router_cfg) - : design_(designIn), - tech_(techIn), - logger_(logger), - router_cfg_(router_cfg) - { - } - - frDesign* getDesign() const { return design_; } + FlexRP(frDesign* design, Logger* logger, RouterConfiguration* router_cfg); void main(); private: - frDesign* design_; - frTechObject* tech_; - Logger* logger_; - RouterConfiguration* router_cfg_; - // init void init(); @@ -67,17 +50,17 @@ class FlexRP // functions void prep_viaForbiddenThrough(); void prep_minStepViasCheck(); - bool hasMinStepViol(Rect& r1, Rect& r2, frLayerNum lNum); + bool hasMinStepViol(const Rect& r1, const Rect& r2, frLayerNum lNum); void prep_viaForbiddenThrough_helper(const frLayerNum& lNum, const int& tableLayerIdx, const int& tableEntryIdx, - frViaDef* viaDef, + const frViaDef* viaDef, bool isCurrDirX); bool prep_viaForbiddenThrough_minStep(const frLayerNum& lNum, - frViaDef* viaDef, + const frViaDef* viaDef, bool isCurrDirX); void prep_lineForbiddenLen(); - void prep_eolForbiddenLen_helper(frLayer* layer, + void prep_eolForbiddenLen_helper(const frLayer* layer, frCoord eolWidth, frCoord& eolSpace, frCoord& eolWithin); @@ -96,21 +79,21 @@ class FlexRP void prep_viaForbiddenPlanarLen_helper(const frLayerNum& lNum, const int& tableLayerIdx, const int& tableEntryIdx, - frViaDef* viaDef, + const frViaDef* viaDef, bool isCurrDirX); void prep_viaForbiddenPlanarLen_minStep(const frLayerNum& lNum, - frViaDef* viaDef, + const frViaDef* viaDef, bool isCurrDirX, ForbiddenRanges& forbiddenRanges); void prep_viaForbiddenTurnLen(frNonDefaultRule* ndr = nullptr); void prep_viaForbiddenTurnLen_helper(const frLayerNum& lNum, const int& tableLayerIdx, const int& tableEntryIdx, - frViaDef* viaDef, + const frViaDef* viaDef, bool isCurrDirX, frNonDefaultRule* ndr = nullptr); void prep_viaForbiddenTurnLen_minSpc(const frLayerNum& lNum, - frViaDef* viaDef, + const frViaDef* viaDef, bool isCurrDirX, ForbiddenRanges& forbiddenRanges, frNonDefaultRule* ndr = nullptr); @@ -118,18 +101,18 @@ class FlexRP void prep_via2viaForbiddenLen_helper(const frLayerNum& lNum, const int& tableLayerIdx, const int& tableEntryIdx, - frViaDef* viaDef1, - frViaDef* viaDef2, + const frViaDef* viaDef1, + const frViaDef* viaDef2, bool isHorizontal, frNonDefaultRule* ndr = nullptr); void prep_via2viaForbiddenLen_minStep(const frLayerNum& lNum, - frViaDef* viaDef1, - frViaDef* viaDef2, + const frViaDef* viaDef1, + const frViaDef* viaDef2, bool isVertical, ForbiddenRanges& forbiddenRanges); void prep_via2viaForbiddenLen_minimumCut(const frLayerNum& lNum, - frViaDef* viaDef1, - frViaDef* viaDef2, + const frViaDef* viaDef1, + const frViaDef* viaDef2, bool isCurrDirX, ForbiddenRanges& forbiddenRanges); void prep_via2viaForbiddenLen_widthViaMap(const frLayerNum& lNum, @@ -138,31 +121,31 @@ class FlexRP bool isCurrDirX, ForbiddenRanges& forbiddenRanges); void prep_via2viaForbiddenLen_cutSpc(const frLayerNum& lNum, - frViaDef* viaDef1, - frViaDef* viaDef2, + const frViaDef* viaDef1, + const frViaDef* viaDef2, bool isCurrDirX, ForbiddenRanges& forbiddenRanges); void prep_via2viaForbiddenLen_minSpc(frLayerNum lNum, - frViaDef* viaDef1, - frViaDef* viaDef2, + const frViaDef* viaDef1, + const frViaDef* viaDef2, bool isCurrDirX, ForbiddenRanges& forbiddenRanges, frNonDefaultRule* ndr = nullptr); void prep_via2viaPRL(frLayerNum lNum, - frViaDef* viaDef1, - frViaDef* viaDef2, + const frViaDef* viaDef1, + const frViaDef* viaDef2, bool isCurrDirX, frCoord& prl); void prep_via2viaForbiddenLen_lef58CutSpc(const frLayerNum& lNum, - frViaDef* viaDef1, - frViaDef* viaDef2, + const frViaDef* viaDef1, + const frViaDef* viaDef2, bool isCurrDirX, ForbiddenRanges& forbiddenRanges); void prep_via2viaForbiddenLen_lef58CutSpcTbl( const frLayerNum& lNum, - frViaDef* viaDef1, - frViaDef* viaDef2, + const frViaDef* viaDef1, + const frViaDef* viaDef2, bool isCurrDirX, ForbiddenRanges& forbiddenRanges); @@ -172,5 +155,10 @@ class FlexRP const Rect& cutBox, frCoord reqSpcVal, std::pair& range); + + frDesign* design_; + frTechObject* tech_; + Logger* logger_; + RouterConfiguration* router_cfg_; }; } // namespace drt diff --git a/src/drt/src/rp/FlexRP_init.cpp b/src/drt/src/rp/FlexRP_init.cpp index 336e3f58202..8a74633a77c 100644 --- a/src/drt/src/rp/FlexRP_init.cpp +++ b/src/drt/src/rp/FlexRP_init.cpp @@ -35,8 +35,8 @@ void FlexRP::init() { ProfileTask profile("RP:init"); - const auto bottomLayerNum = getDesign()->getTech()->getBottomLayerNum(); - const auto topLayerNum = getDesign()->getTech()->getTopLayerNum(); + const auto bottomLayerNum = tech_->getBottomLayerNum(); + const auto topLayerNum = tech_->getTopLayerNum(); for (auto lNum = bottomLayerNum; lNum <= topLayerNum; lNum++) { if (tech_->getLayer(lNum)->getType() != dbTechLayerType::ROUTING) { diff --git a/src/drt/src/rp/FlexRP_prep.cpp b/src/drt/src/rp/FlexRP_prep.cpp index 89f6b672578..d6dfe1fa111 100644 --- a/src/drt/src/rp/FlexRP_prep.cpp +++ b/src/drt/src/rp/FlexRP_prep.cpp @@ -50,7 +50,7 @@ void FlexRP::prep() prep_eolForbiddenLen(); prep_cutSpcTbl(); prep_viaForbiddenThrough(); - for (auto& ndr : tech_->nonDefaultRules_) { + for (const auto& ndr : tech_->nonDefaultRules_) { prep_via2viaForbiddenLen(ndr.get()); prep_viaForbiddenTurnLen(ndr.get()); } @@ -59,8 +59,8 @@ void FlexRP::prep() void FlexRP::prep_minStepViasCheck() { - auto bottomLayerNum = getDesign()->getTech()->getBottomLayerNum(); - auto topLayerNum = getDesign()->getTech()->getTopLayerNum(); + const auto bottomLayerNum = tech_->getBottomLayerNum(); + const auto topLayerNum = tech_->getTopLayerNum(); for (auto lNum = bottomLayerNum; lNum <= topLayerNum; lNum++) { frLayer* layer = tech_->getLayer(lNum); if (layer->getType() != dbTechLayerType::ROUTING) { @@ -69,10 +69,8 @@ void FlexRP::prep_minStepViasCheck() if (lNum - 2 < bottomLayerNum || lNum + 2 > topLayerNum) { continue; } - frViaDef* downVia - = getDesign()->getTech()->getLayer(lNum - 1)->getDefaultViaDef(); - frViaDef* upVia - = getDesign()->getTech()->getLayer(lNum + 1)->getDefaultViaDef(); + const frViaDef* downVia = tech_->getLayer(lNum - 1)->getDefaultViaDef(); + const frViaDef* upVia = tech_->getLayer(lNum + 1)->getDefaultViaDef(); if (!downVia || !upVia) { continue; } @@ -81,14 +79,14 @@ void FlexRP::prep_minStepViasCheck() continue; } - Rect upViaBox = upVia->getLayer1ShapeBox(); - Rect downViaBox = downVia->getLayer2ShapeBox(); - gtl::rectangle_data upViaRect( + const Rect upViaBox = upVia->getLayer1ShapeBox(); + const Rect downViaBox = downVia->getLayer2ShapeBox(); + const gtl::rectangle_data upViaRect( upViaBox.xMin(), upViaBox.yMin(), upViaBox.xMax(), upViaBox.yMax()); - gtl::rectangle_data downViaRect(downViaBox.xMin(), - downViaBox.yMin(), - downViaBox.xMax(), - downViaBox.yMax()); + const gtl::rectangle_data downViaRect(downViaBox.xMin(), + downViaBox.yMin(), + downViaBox.xMax(), + downViaBox.yMax()); // joining the two via rects in one polygon gtl::polygon_90_set_data set; @@ -104,8 +102,7 @@ void FlexRP::prep_minStepViasCheck() gtl::polygon_90_with_holes_data poly = *polys.begin(); std::unique_ptr uTestNet = std::make_unique(0); gcNet* testNet = uTestNet.get(); - std::unique_ptr uTestPin - = std::make_unique(poly, lNum, testNet); + auto uTestPin = std::make_unique(poly, lNum, testNet); gcPin* testPin = uTestPin.get(); testPin->setNet(testNet); @@ -147,7 +144,7 @@ void FlexRP::prep_minStepViasCheck() // check gc minstep violations FlexGCWorker worker(tech_, logger_, router_cfg_); worker.checkMinStep(testPin); - auto& markers = worker.getMarkers(); + const auto& markers = worker.getMarkers(); if (!markers.empty()) { tech_->setVia2ViaMinStep(true); layer->setHasVia2ViaMinStepViol(true); @@ -157,21 +154,21 @@ void FlexRP::prep_minStepViasCheck() void FlexRP::prep_viaForbiddenThrough() { - auto bottomLayerNum = getDesign()->getTech()->getBottomLayerNum(); - auto topLayerNum = getDesign()->getTech()->getTopLayerNum(); + const auto bottomLayerNum = tech_->getBottomLayerNum(); + const auto topLayerNum = tech_->getTopLayerNum(); int i = 0; for (auto lNum = bottomLayerNum; lNum <= topLayerNum; lNum++) { if (tech_->getLayer(lNum)->getType() != dbTechLayerType::ROUTING) { continue; } - frViaDef* downVia = nullptr; - frViaDef* upVia = nullptr; - if (getDesign()->getTech()->getBottomLayerNum() <= lNum - 1) { - downVia = getDesign()->getTech()->getLayer(lNum - 1)->getDefaultViaDef(); + const frViaDef* downVia = nullptr; + const frViaDef* upVia = nullptr; + if (tech_->getBottomLayerNum() <= lNum - 1) { + downVia = tech_->getLayer(lNum - 1)->getDefaultViaDef(); } - if (getDesign()->getTech()->getTopLayerNum() >= lNum + 1) { - upVia = getDesign()->getTech()->getLayer(lNum + 1)->getDefaultViaDef(); + if (tech_->getTopLayerNum() >= lNum + 1) { + upVia = tech_->getLayer(lNum + 1)->getDefaultViaDef(); } prep_viaForbiddenThrough_helper(lNum, i, 0, downVia, true); prep_viaForbiddenThrough_helper(lNum, i, 1, downVia, false); @@ -184,21 +181,16 @@ void FlexRP::prep_viaForbiddenThrough() void FlexRP::prep_viaForbiddenThrough_helper(const frLayerNum& lNum, const int& tableLayerIdx, const int& tableEntryIdx, - frViaDef* viaDef, - bool isCurrDirX) + const frViaDef* viaDef, + const bool isCurrDirX) { - bool isThroughAllowed = true; - - if (prep_viaForbiddenThrough_minStep(lNum, viaDef, isCurrDirX)) { - isThroughAllowed = false; - } - - tech_->viaForbiddenThrough_[tableLayerIdx][tableEntryIdx] = !isThroughAllowed; + tech_->viaForbiddenThrough_[tableLayerIdx][tableEntryIdx] + = prep_viaForbiddenThrough_minStep(lNum, viaDef, isCurrDirX); } bool FlexRP::prep_viaForbiddenThrough_minStep(const frLayerNum& lNum, - frViaDef* viaDef, - bool isCurrDirX) + const frViaDef* viaDef, + const bool isCurrDirX) { if (!viaDef) { return false; @@ -214,64 +206,64 @@ bool FlexRP::prep_viaForbiddenThrough_minStep(const frLayerNum& lNum, * @return the min eol width from the eol rules -1 or the default width if no * eol rules found. */ -inline frCoord getMinEol(frLayer* layer, frCoord minWidth) +frCoord getMinEol(const frLayer* layer, const frCoord minWidth) { frCoord eol = INT_MAX; if (layer->hasEolSpacing()) { - for (auto con : layer->getEolSpacing()) { + for (const auto con : layer->getEolSpacing()) { eol = std::min(eol, con->getEolWidth()); } } - for (auto con : layer->getLef58SpacingEndOfLineConstraints()) { + for (const auto con : layer->getLef58SpacingEndOfLineConstraints()) { eol = std::min(eol, con->getEolWidth()); } - for (auto con : layer->getLef58EolKeepOutConstraints()) { + for (const auto con : layer->getLef58EolKeepOutConstraints()) { eol = std::min(eol, con->getEolWidth()); } - for (auto con : layer->getLef58EolExtConstraints()) { + for (const auto con : layer->getLef58EolExtConstraints()) { eol = std::min(eol, con->getExtensionTable().getMinRow()); } if (eol == INT_MAX) { eol = minWidth; } else { - eol = std::max(eol - 1, (frCoord) minWidth); + eol = std::max(eol - 1, minWidth); } return eol; } -void FlexRP::prep_eolForbiddenLen_helper(frLayer* layer, +void FlexRP::prep_eolForbiddenLen_helper(const frLayer* layer, const frCoord eolWidth, frCoord& eolSpace, frCoord& eolWithin) { if (layer->hasEolSpacing()) { - for (auto con : layer->getEolSpacing()) { + for (const auto con : layer->getEolSpacing()) { if (eolWidth < con->getEolWidth()) { eolSpace = std::max(eolSpace, con->getMinSpacing()); eolWithin = std::max(eolWithin, con->getEolWithin()); } } } - for (auto con : layer->getLef58SpacingEndOfLineConstraints()) { + for (const auto con : layer->getLef58SpacingEndOfLineConstraints()) { if (eolWidth < con->getEolWidth()) { eolSpace = std::max(eolSpace, con->getEolSpace()); if (con->hasWithinConstraint()) { - auto withinCon = con->getWithinConstraint(); + const auto withinCon = con->getWithinConstraint(); eolWithin = std::max(eolWithin, withinCon->getEolWithin()); if (withinCon->hasEndToEndConstraint()) { - auto endToEndCon = withinCon->getEndToEndConstraint(); + const auto endToEndCon = withinCon->getEndToEndConstraint(); eolSpace = std::max(eolSpace, endToEndCon->getEndToEndSpace()); } } } } - for (auto con : layer->getLef58EolKeepOutConstraints()) { + for (const auto con : layer->getLef58EolKeepOutConstraints()) { if (eolWidth < con->getEolWidth()) { eolSpace = std::max(eolSpace, con->getForwardExt()); eolWithin = std::max(eolWithin, con->getSideExt()); } } - for (auto con : layer->getLef58EolExtConstraints()) { + for (const auto con : layer->getLef58EolExtConstraints()) { if (eolWidth < con->getExtensionTable().getMaxRow()) { eolSpace = std::max( eolSpace, @@ -282,11 +274,11 @@ void FlexRP::prep_eolForbiddenLen_helper(frLayer* layer, void FlexRP::prep_eolForbiddenLen() { - auto bottomLayerNum = getDesign()->getTech()->getBottomLayerNum(); - auto topLayerNum = getDesign()->getTech()->getTopLayerNum(); + const auto bottomLayerNum = tech_->getBottomLayerNum(); + const auto topLayerNum = tech_->getTopLayerNum(); for (auto lNum = bottomLayerNum; lNum <= topLayerNum; lNum++) { - auto layer = tech_->getLayer(lNum); + const auto layer = tech_->getLayer(lNum); if (layer->getType() != dbTechLayerType::ROUTING) { continue; } @@ -296,14 +288,14 @@ void FlexRP::prep_eolForbiddenLen() prep_eolForbiddenLen_helper(layer, eolWidth, eolSpace, eolWithin); layer->setDrEolSpacingConstraint(eolWidth, eolSpace, eolWithin); } - for (auto& ndr : tech_->getNondefaultRules()) { + for (const auto& ndr : tech_->getNondefaultRules()) { for (auto lNum = bottomLayerNum; lNum <= topLayerNum; lNum++) { - auto layer = tech_->getLayer(lNum); + const auto layer = tech_->getLayer(lNum); if (layer->getType() != dbTechLayerType::ROUTING) { continue; } - auto z = lNum / 2 - 1; - frCoord minWidth = ndr->getWidth(z); + const auto z = lNum / 2 - 1; + const frCoord minWidth = ndr->getWidth(z); if (minWidth == 0) { continue; } @@ -319,11 +311,11 @@ void FlexRP::prep_eolForbiddenLen() void FlexRP::prep_cutSpcTbl() { - auto bottomLayerNum = getDesign()->getTech()->getBottomLayerNum(); - auto topLayerNum = getDesign()->getTech()->getTopLayerNum(); + const auto bottomLayerNum = tech_->getBottomLayerNum(); + const auto topLayerNum = tech_->getTopLayerNum(); for (auto lNum = bottomLayerNum; lNum <= topLayerNum; lNum++) { - auto layer = tech_->getLayer(lNum); + const auto layer = tech_->getLayer(lNum); if (layer->getType() == odb::dbTechLayerType::CUT) { auto viaDef = layer->getDefaultViaDef(); if (viaDef == nullptr) { @@ -332,14 +324,14 @@ void FlexRP::prep_cutSpcTbl() frVia via(viaDef); Rect tmpBx = via.getCutBBox(); frString cutClass1; - auto cutClassIdx1 + const auto cutClassIdx1 = layer->getCutClassIdx(tmpBx.minDXDY(), tmpBx.maxDXDY()); if (cutClassIdx1 >= 0) { cutClass1 = layer->getCutClass(cutClassIdx1)->getName(); } if (layer->hasLef58DiffNetCutSpcTblConstraint()) { - auto con = layer->getLef58DiffNetCutSpcTblConstraint(); - auto dbRule = con->getODBRule(); + const auto con = layer->getLef58DiffNetCutSpcTblConstraint(); + const auto dbRule = con->getODBRule(); con->setDefaultSpacing( {dbRule->getMaxSpacing( cutClass1, @@ -355,15 +347,15 @@ void FlexRP::prep_cutSpcTbl() dbRule->isCenterAndEdge(cutClass1, cutClass1)); } if (layer->hasLef58DefaultInterCutSpcTblConstraint()) { - auto con = layer->getLef58DefaultInterCutSpcTblConstraint(); - auto dbRule = con->getODBRule(); - auto secondLayer = getDesign()->getTech()->getLayer( - dbRule->getSecondLayer()->getName()); + const auto con = layer->getLef58DefaultInterCutSpcTblConstraint(); + const auto dbRule = con->getODBRule(); + const auto secondLayer + = tech_->getLayer(dbRule->getSecondLayer()->getName()); viaDef = secondLayer->getDefaultViaDef(); if (viaDef != nullptr) { tmpBx = via.getCutBBox(); frString cutClass2; - auto cutClassIdx2 + const auto cutClassIdx2 = secondLayer->getCutClassIdx(tmpBx.minDXDY(), tmpBx.maxDXDY()); if (cutClassIdx2 >= 0) { cutClass2 = secondLayer->getCutClass(cutClassIdx2)->getName(); @@ -389,8 +381,8 @@ void FlexRP::prep_cutSpcTbl() void FlexRP::prep_lineForbiddenLen() { - auto bottomLayerNum = getDesign()->getTech()->getBottomLayerNum(); - auto topLayerNum = getDesign()->getTech()->getTopLayerNum(); + const auto bottomLayerNum = tech_->getBottomLayerNum(); + const auto topLayerNum = tech_->getTopLayerNum(); int i = 0; for (auto lNum = bottomLayerNum; lNum <= topLayerNum; lNum++) { @@ -438,13 +430,14 @@ void FlexRP::prep_lineForbiddenLen_minSpc(const frLayerNum& lNum, const bool isCurrDirX, ForbiddenRanges& forbiddenRanges) { - frCoord defaultWidth = tech_->getLayer(lNum)->getWidth(); + const frCoord defaultWidth = tech_->getLayer(lNum)->getWidth(); - frCoord minNonOverlapDist = defaultWidth; + const frCoord minNonOverlapDist = defaultWidth; frCoord minReqDist = INT_MIN; - frCoord prl = isZShape ? defaultWidth : tech_->getLayer(lNum)->getPitch(); - auto con = tech_->getLayer(lNum)->getMinSpacing(); + const frCoord prl + = isZShape ? defaultWidth : tech_->getLayer(lNum)->getPitch(); + const auto con = tech_->getLayer(lNum)->getMinSpacing(); if (con) { if (con->typeId() == frConstraintTypeEnum::frcSpacingConstraint) { minReqDist = static_cast(con)->getMinSpacing(); @@ -468,22 +461,21 @@ void FlexRP::prep_lineForbiddenLen_minSpc(const frLayerNum& lNum, void FlexRP::prep_viaForbiddenPlanarLen() { - auto bottomLayerNum = getDesign()->getTech()->getBottomLayerNum(); - auto topLayerNum = getDesign()->getTech()->getTopLayerNum(); + const auto bottomLayerNum = tech_->getBottomLayerNum(); + const auto topLayerNum = tech_->getTopLayerNum(); int i = 0; for (auto lNum = bottomLayerNum; lNum <= topLayerNum; lNum++) { - if (getDesign()->getTech()->getLayer(lNum)->getType() - != dbTechLayerType::ROUTING) { + if (tech_->getLayer(lNum)->getType() != dbTechLayerType::ROUTING) { continue; } - frViaDef* downVia = nullptr; - frViaDef* upVia = nullptr; - if (getDesign()->getTech()->getBottomLayerNum() <= lNum - 1) { - downVia = getDesign()->getTech()->getLayer(lNum - 1)->getDefaultViaDef(); + const frViaDef* downVia = nullptr; + const frViaDef* upVia = nullptr; + if (tech_->getBottomLayerNum() <= lNum - 1) { + downVia = tech_->getLayer(lNum - 1)->getDefaultViaDef(); } - if (getDesign()->getTech()->getTopLayerNum() >= lNum + 1) { - upVia = getDesign()->getTech()->getLayer(lNum + 1)->getDefaultViaDef(); + if (tech_->getTopLayerNum() >= lNum + 1) { + upVia = tech_->getLayer(lNum + 1)->getDefaultViaDef(); } prep_viaForbiddenPlanarLen_helper(lNum, i, 0, downVia, true); prep_viaForbiddenPlanarLen_helper(lNum, i, 1, downVia, false); @@ -497,7 +489,7 @@ void FlexRP::prep_viaForbiddenPlanarLen() void FlexRP::prep_viaForbiddenPlanarLen_helper(const frLayerNum& lNum, const int& tableLayerIdx, const int& tableEntryIdx, - frViaDef* viaDef, + const frViaDef* viaDef, bool isCurrDirX) { if (!viaDef) { @@ -509,7 +501,7 @@ void FlexRP::prep_viaForbiddenPlanarLen_helper(const frLayerNum& lNum, // merge forbidden ranges boost::icl::interval_set forbiddenIntvSet; - for (auto& range : forbiddenRanges) { + for (const auto& range : forbiddenRanges) { forbiddenIntvSet.insert( boost::icl::interval::closed(range.first, range.second)); } @@ -527,36 +519,35 @@ void FlexRP::prep_viaForbiddenPlanarLen_helper(const frLayerNum& lNum, void FlexRP::prep_viaForbiddenPlanarLen_minStep( const frLayerNum& lNum, - frViaDef* viaDef, - bool isCurrDirX, + const frViaDef* viaDef, + const bool isCurrDirX, ForbiddenRanges& forbiddenRanges) { } void FlexRP::prep_viaForbiddenTurnLen(frNonDefaultRule* ndr) { - auto bottomLayerNum = getDesign()->getTech()->getBottomLayerNum(); - auto topLayerNum = getDesign()->getTech()->getTopLayerNum(); - int bottom = router_cfg_->BOTTOM_ROUTING_LAYER; + const auto bottomLayerNum = tech_->getBottomLayerNum(); + const auto topLayerNum = tech_->getTopLayerNum(); + const int bottom = router_cfg_->BOTTOM_ROUTING_LAYER; int i = 0; for (auto lNum = bottomLayerNum; lNum <= topLayerNum; lNum++) { - if (getDesign()->getTech()->getLayer(lNum)->getType() - != dbTechLayerType::ROUTING) { + if (tech_->getLayer(lNum)->getType() != dbTechLayerType::ROUTING) { continue; } - frViaDef* downVia = nullptr; - frViaDef* upVia = nullptr; + const frViaDef* downVia = nullptr; + const frViaDef* upVia = nullptr; if (ndr && bottom < lNum && ndr->getPrefVia((lNum - 2) / 2 - 1)) { downVia = ndr->getPrefVia((lNum - 2) / 2 - 1); - } else if (getDesign()->getTech()->getBottomLayerNum() <= lNum - 1) { - downVia = getDesign()->getTech()->getLayer(lNum - 1)->getDefaultViaDef(); + } else if (tech_->getBottomLayerNum() <= lNum - 1) { + downVia = tech_->getLayer(lNum - 1)->getDefaultViaDef(); } - if (getDesign()->getTech()->getTopLayerNum() >= lNum + 1) { + if (tech_->getTopLayerNum() >= lNum + 1) { if (ndr && ndr->getPrefVia(lNum / 2 - 1)) { upVia = ndr->getPrefVia(lNum / 2 - 1); } else { - upVia = getDesign()->getTech()->getLayer(lNum + 1)->getDefaultViaDef(); + upVia = tech_->getLayer(lNum + 1)->getDefaultViaDef(); } } prep_viaForbiddenTurnLen_helper(lNum, i, 0, downVia, true, ndr); @@ -572,15 +563,15 @@ void FlexRP::prep_viaForbiddenTurnLen(frNonDefaultRule* ndr) void FlexRP::prep_viaForbiddenTurnLen_helper(const frLayerNum& lNum, const int& tableLayerIdx, const int& tableEntryIdx, - frViaDef* viaDef, - bool isCurrDirX, + const frViaDef* viaDef, + const bool isCurrDirX, frNonDefaultRule* ndr) { if (!viaDef) { return; } - auto tech = getDesign()->getTech(); + auto tech = tech_; ForbiddenRanges forbiddenRanges; prep_viaForbiddenTurnLen_minSpc( @@ -609,8 +600,8 @@ void FlexRP::prep_viaForbiddenTurnLen_helper(const frLayerNum& lNum, } void FlexRP::prep_viaForbiddenTurnLen_minSpc(const frLayerNum& lNum, - frViaDef* viaDef, - bool isCurrDirX, + const frViaDef* viaDef, + const bool isCurrDirX, ForbiddenRanges& forbiddenRanges, frNonDefaultRule* ndr) { @@ -618,29 +609,29 @@ void FlexRP::prep_viaForbiddenTurnLen_minSpc(const frLayerNum& lNum, return; } - frCoord defaultWidth = tech_->getLayer(lNum)->getWidth(); + const frCoord defaultWidth = tech_->getLayer(lNum)->getWidth(); frCoord width = defaultWidth; if (ndr) { width = std::max(width, ndr->getWidth(lNum / 2 - 1)); } - frVia via1(viaDef); + const frVia via1(viaDef); Rect viaBox1; if (viaDef->getLayer1Num() == lNum) { viaBox1 = via1.getLayer1BBox(); } else { viaBox1 = via1.getLayer2BBox(); } - int width1 = viaBox1.minDXDY(); - bool isVia1Fat = isCurrDirX ? (viaBox1.dy() > defaultWidth) - : (viaBox1.dx() > defaultWidth); - auto prl1 = isCurrDirX ? viaBox1.dy() : viaBox1.dx(); + const int width1 = viaBox1.minDXDY(); + const bool isVia1Fat = isCurrDirX ? (viaBox1.dy() > defaultWidth) + : (viaBox1.dx() > defaultWidth); + const auto prl1 = isCurrDirX ? viaBox1.dy() : viaBox1.dx(); - frCoord minNonOverlapDist = isCurrDirX ? ((viaBox1.dx() + width) / 2) - : ((viaBox1.dy() + width) / 2); + const frCoord minNonOverlapDist = isCurrDirX ? ((viaBox1.dx() + width) / 2) + : ((viaBox1.dy() + width) / 2); frCoord minReqDist = INT_MIN; if (isVia1Fat || ndr) { - auto con = getDesign()->getTech()->getLayer(lNum)->getMinSpacing(); + const auto con = tech_->getLayer(lNum)->getMinSpacing(); if (con) { if (con->typeId() == frConstraintTypeEnum::frcSpacingConstraint) { minReqDist = static_cast(con)->getMinSpacing(); @@ -668,27 +659,26 @@ void FlexRP::prep_viaForbiddenTurnLen_minSpc(const frLayerNum& lNum, void FlexRP::prep_via2viaForbiddenLen(frNonDefaultRule* ndr) { - auto bottomLayerNum = getDesign()->getTech()->getBottomLayerNum(); - auto topLayerNum = getDesign()->getTech()->getTopLayerNum(); - int bottom = router_cfg_->BOTTOM_ROUTING_LAYER; + const auto bottomLayerNum = tech_->getBottomLayerNum(); + const auto topLayerNum = tech_->getTopLayerNum(); + const int bottom = router_cfg_->BOTTOM_ROUTING_LAYER; int i = 0; for (auto lNum = bottomLayerNum; lNum <= topLayerNum; lNum++) { - if (getDesign()->getTech()->getLayer(lNum)->getType() - != dbTechLayerType::ROUTING) { + if (tech_->getLayer(lNum)->getType() != dbTechLayerType::ROUTING) { continue; } - frViaDef* downVia = nullptr; - frViaDef* upVia = nullptr; + const frViaDef* downVia = nullptr; + const frViaDef* upVia = nullptr; if (ndr && bottom < lNum && ndr->getPrefVia((lNum - 2) / 2 - 1)) { downVia = ndr->getPrefVia((lNum - 2) / 2 - 1); - } else if (getDesign()->getTech()->getBottomLayerNum() <= lNum - 1) { - downVia = getDesign()->getTech()->getLayer(lNum - 1)->getDefaultViaDef(); + } else if (tech_->getBottomLayerNum() <= lNum - 1) { + downVia = tech_->getLayer(lNum - 1)->getDefaultViaDef(); } - if (getDesign()->getTech()->getTopLayerNum() >= lNum + 1) { + if (tech_->getTopLayerNum() >= lNum + 1) { if (ndr && ndr->getPrefVia(lNum / 2 - 1)) { upVia = ndr->getPrefVia(lNum / 2 - 1); } else { - upVia = getDesign()->getTech()->getLayer(lNum + 1)->getDefaultViaDef(); + upVia = tech_->getLayer(lNum + 1)->getDefaultViaDef(); } } prep_via2viaForbiddenLen_helper(lNum, i, 0, downVia, downVia, true, ndr); @@ -709,12 +699,12 @@ void FlexRP::prep_via2viaForbiddenLen(frNonDefaultRule* ndr) void FlexRP::prep_via2viaForbiddenLen_helper(const frLayerNum& lNum, const int& tableLayerIdx, const int& tableEntryIdx, - frViaDef* viaDef1, - frViaDef* viaDef2, - bool isHorizontal, + const frViaDef* viaDef1, + const frViaDef* viaDef2, + const bool isHorizontal, frNonDefaultRule* ndr) { - auto tech = getDesign()->getTech(); + auto tech = tech_; // non-shape-based rule ForbiddenRanges forbiddenRanges; prep_via2viaForbiddenLen_minSpc( @@ -760,11 +750,13 @@ void FlexRP::prep_via2viaForbiddenLen_helper(const frLayerNum& lNum, } } -bool FlexRP::hasMinStepViol(Rect& r1, Rect& r2, frLayerNum lNum) +bool FlexRP::hasMinStepViol(const Rect& r1, + const Rect& r2, + const frLayerNum lNum) { - gtl::rectangle_data rect1( + const gtl::rectangle_data rect1( r1.xMin(), r1.yMin(), r1.xMax(), r1.yMax()); - gtl::rectangle_data rect2( + const gtl::rectangle_data rect2( r2.xMin(), r2.yMin(), r2.xMax(), r2.yMax()); // joining the two via rects in one polygon @@ -828,15 +820,16 @@ bool FlexRP::hasMinStepViol(Rect& r1, Rect& r2, frLayerNum lNum) } void FlexRP::prep_via2viaForbiddenLen_minStep(const frLayerNum& lNum, - frViaDef* viaDef1, - frViaDef* viaDef2, - bool isVertical, + const frViaDef* viaDef1, + const frViaDef* viaDef2, + const bool isVertical, ForbiddenRanges& forbiddenRanges) { if (!viaDef1 || !viaDef2) { return; } - frMinStepConstraint* con = tech_->getLayer(lNum)->getMinStepConstraint(); + const frMinStepConstraint* con + = tech_->getLayer(lNum)->getMinStepConstraint(); if (!con) { return; } @@ -844,8 +837,8 @@ void FlexRP::prep_via2viaForbiddenLen_minStep(const frLayerNum& lNum, return; } Rect enclosureBox1, enclosureBox2; - frVia via1(viaDef1); - frVia via2(viaDef2); + const frVia via1(viaDef1); + const frVia via2(viaDef2); if (viaDef1->getLayer1Num() == lNum) { enclosureBox1 = via1.getLayer1BBox(); enclosureBox2 = via2.getLayer2BBox(); @@ -933,8 +926,9 @@ void FlexRP::prep_via2viaForbiddenLen_minStep(const frLayerNum& lNum, if (con->getMaxLength() > 0) { int div = 2; int length = shiftingEdge; - int topEdge_shifting = isVertical ? shifting->dx() : shifting->dy(); - int topEdge_other = isVertical ? other->dy() : other->dx(); + const int topEdge_shifting + = isVertical ? shifting->dx() : shifting->dy(); + const int topEdge_other = isVertical ? other->dy() : other->dx(); if (topEdge_shifting < con->getMinStepLength()) { length += topEdge_shifting + shiftingEdge; if (otherEdge < con->getMinStepLength()) { @@ -996,9 +990,9 @@ void FlexRP::prep_via2viaForbiddenLen_minStep(const frLayerNum& lNum, // only partial support of GF14 void FlexRP::prep_via2viaForbiddenLen_lef58CutSpc( const frLayerNum& lNum, - frViaDef* viaDef1, - frViaDef* viaDef2, - bool isCurrDirX, + const frViaDef* viaDef1, + const frViaDef* viaDef2, + const bool isCurrDirX, ForbiddenRanges& forbiddenRanges) { if (!viaDef1 || !viaDef2) { @@ -1009,7 +1003,7 @@ void FlexRP::prep_via2viaForbiddenLen_lef58CutSpc( return; } - bool isCurrDirY = !isCurrDirX; + const bool isCurrDirY = !isCurrDirX; if (lNum != 10 || !isCurrDirY) { return; } @@ -1022,29 +1016,30 @@ void FlexRP::prep_via2viaForbiddenLen_lef58CutSpc( return; } - Rect enclosureBox1, enclosureBox2, cutBox1, cutBox2; - frVia via1(viaDef1); - frVia via2(viaDef2); + Rect enclosureBox1; + const frVia via1(viaDef1); + const frVia via2(viaDef2); if (viaDef1->getLayer1Num() == lNum) { enclosureBox1 = via1.getLayer1BBox(); } else { enclosureBox1 = via1.getLayer2BBox(); } + Rect enclosureBox2; if (viaDef2->getLayer1Num() == lNum) { enclosureBox2 = via2.getLayer1BBox(); } else { enclosureBox2 = via2.getLayer2BBox(); } - cutBox1 = via1.getCutBBox(); - cutBox2 = via2.getCutBBox(); + const Rect cutBox1 = via1.getCutBBox(); + const Rect cutBox2 = via2.getCutBBox(); std::pair range; frCoord reqSpcVal = 0; // check via1 cut layer to lNum - auto via1CutLNum = viaDef1->getCutLayerNum(); + const auto via1CutLNum = viaDef1->getCutLayerNum(); if (!tech_->getLayer(via1CutLNum) ->getLef58CutSpacingConstraints(false) .empty()) { - for (auto con : + for (const auto con : tech_->getLayer(via1CutLNum)->getLef58CutSpacingConstraints(false)) { if (con->getSecondLayerNum() != lNum) { continue; @@ -1058,7 +1053,7 @@ void FlexRP::prep_via2viaForbiddenLen_lef58CutSpc( forbiddenRanges.push_back(range); } } else { - for (auto con : + for (const auto con : tech_->getLayer(via1CutLNum)->getLef58CutSpacingConstraints(true)) { if (con->getSecondLayerNum() != lNum) { continue; @@ -1074,11 +1069,11 @@ void FlexRP::prep_via2viaForbiddenLen_lef58CutSpc( } // check via2 cut layer to lNum - auto via2CutLNum = viaDef2->getCutLayerNum(); + const auto via2CutLNum = viaDef2->getCutLayerNum(); if (!tech_->getLayer(via2CutLNum) ->getLef58CutSpacingConstraints(false) .empty()) { - for (auto con : + for (const auto con : tech_->getLayer(via2CutLNum)->getLef58CutSpacingConstraints(false)) { if (con->getSecondLayerNum() != lNum) { continue; @@ -1092,7 +1087,7 @@ void FlexRP::prep_via2viaForbiddenLen_lef58CutSpc( forbiddenRanges.push_back(range); } } else { - for (auto con : + for (const auto con : tech_->getLayer(via2CutLNum)->getLef58CutSpacingConstraints(true)) { if (con->getSecondLayerNum() != lNum) { continue; @@ -1110,50 +1105,47 @@ void FlexRP::prep_via2viaForbiddenLen_lef58CutSpc( void FlexRP::prep_via2viaForbiddenLen_lef58CutSpcTbl( const frLayerNum& lNum, - frViaDef* viaDef1, - frViaDef* viaDef2, - bool isCurrDirX, + const frViaDef* viaDef1, + const frViaDef* viaDef2, + const bool isCurrDirX, ForbiddenRanges& forbiddenRanges) { if (!viaDef1 || !viaDef2) { return; } - bool swapped = false; - if (viaDef2->getCutLayerNum() > viaDef1->getCutLayerNum()) { - // swap - frViaDef* temp = viaDef2; - viaDef2 = viaDef1; - viaDef1 = temp; - swapped = true; - } - bool isCurrDirY = !isCurrDirX; - frVia via1(viaDef1); - Rect viaBox1, viaBox2; + const bool swapped = viaDef2->getCutLayerNum() > viaDef1->getCutLayerNum(); + if (swapped) { + std::swap(viaDef2, viaDef1); + } + const bool isCurrDirY = !isCurrDirX; + const frVia via1(viaDef1); + Rect viaBox1; if (viaDef1->getLayer1Num() == lNum) { viaBox1 = via1.getLayer1BBox(); } else { viaBox1 = via1.getLayer2BBox(); } - frVia via2(viaDef2); + const frVia via2(viaDef2); + Rect viaBox2; if (viaDef2->getLayer1Num() == lNum) { viaBox2 = via2.getLayer1BBox(); } else { viaBox2 = via2.getLayer2BBox(); } - Rect cutBox1 = via1.getCutBBox(); - Rect cutBox2 = via2.getCutBBox(); - frCoord reqSpcVal = 0; - auto layer1 = tech_->getLayer(viaDef1->getCutLayerNum()); - auto layer2 = tech_->getLayer(viaDef2->getCutLayerNum()); - auto cutClassIdx1 + const Rect cutBox1 = via1.getCutBBox(); + const Rect cutBox2 = via2.getCutBBox(); + const auto layer1 = tech_->getLayer(viaDef1->getCutLayerNum()); + const auto layer2 = tech_->getLayer(viaDef2->getCutLayerNum()); + const auto cutClassIdx1 = layer1->getCutClassIdx(cutBox1.minDXDY(), cutBox1.maxDXDY()); - auto cutClassIdx2 + const auto cutClassIdx2 = layer2->getCutClassIdx(cutBox2.minDXDY(), cutBox2.maxDXDY()); - frString cutClass1, cutClass2; + frString cutClass1; if (cutClassIdx1 != -1) { cutClass1 = layer1->getCutClass(cutClassIdx1)->getName(); } + frString cutClass2; if (cutClassIdx2 != -1) { cutClass2 = layer2->getCutClass(cutClassIdx2)->getName(); } @@ -1167,7 +1159,7 @@ void FlexRP::prep_via2viaForbiddenLen_lef58CutSpcTbl( isSide2 = cutBox2.dx() < cutBox2.dy(); } if (layer1->getLayerNum() == layer2->getLayerNum()) { - frLef58CutSpacingTableConstraint* lef58con = nullptr; + const frLef58CutSpacingTableConstraint* lef58con = nullptr; if (layer1->hasLef58SameMetalCutSpcTblConstraint()) { lef58con = layer1->getLef58SameMetalCutSpcTblConstraint(); } else if (layer1->hasLef58SameNetCutSpcTblConstraint()) { @@ -1176,8 +1168,9 @@ void FlexRP::prep_via2viaForbiddenLen_lef58CutSpcTbl( lef58con = layer1->getLef58DiffNetCutSpcTblConstraint(); } if (lef58con != nullptr) { - auto dbRule = lef58con->getODBRule(); - reqSpcVal = dbRule->getSpacing(cutClass1, isSide1, cutClass2, isSide2); + const auto dbRule = lef58con->getODBRule(); + frCoord reqSpcVal + = dbRule->getSpacing(cutClass1, isSide1, cutClass2, isSide2); if (!dbRule->isCenterToCenter(cutClass1, cutClass2) && !dbRule->isCenterAndEdge(cutClass1, cutClass2)) { if (!swapped) { @@ -1191,7 +1184,7 @@ void FlexRP::prep_via2viaForbiddenLen_lef58CutSpcTbl( } } } else { - frLef58CutSpacingTableConstraint* con; + const frLef58CutSpacingTableConstraint* con; if (layer1->hasLef58SameMetalInterCutSpcTblConstraint()) { con = layer1->getLef58SameMetalInterCutSpcTblConstraint(); } else if (layer1->hasLef58SameNetInterCutSpcTblConstraint()) { @@ -1199,13 +1192,14 @@ void FlexRP::prep_via2viaForbiddenLen_lef58CutSpcTbl( } else { return; } - auto dbRule = con->getODBRule(); + const auto dbRule = con->getODBRule(); if (dbRule->isSameNet() || dbRule->isSameMetal()) { if (!dbRule->isNoStack()) { return; } } - reqSpcVal = dbRule->getSpacing(cutClass1, isSide1, cutClass2, isSide2); + frCoord reqSpcVal + = dbRule->getSpacing(cutClass1, isSide1, cutClass2, isSide2); if (reqSpcVal == 0) { return; } @@ -1222,7 +1216,7 @@ void FlexRP::prep_via2viaForbiddenLen_lef58CutSpc_helper( const Rect& enclosureBox1, const Rect& enclosureBox2, const Rect& cutBox, - frCoord reqSpcVal, + const frCoord reqSpcVal, std::pair& range) { frCoord overlapLen = std::min(enclosureBox1.dy(), enclosureBox2.dy()); @@ -1240,20 +1234,20 @@ void FlexRP::prep_via2viaForbiddenLen_lef58CutSpc_helper( // intersect the via pad. void FlexRP::prep_via2viaForbiddenLen_minimumCut( const frLayerNum& lNum, - frViaDef* viaDef1, - frViaDef* viaDef2, - bool isCurrDirX, + const frViaDef* viaDef1, + const frViaDef* viaDef2, + const bool isCurrDirX, ForbiddenRanges& forbiddenRanges) { if (!viaDef1 || !viaDef2) { return; } - bool isH = (getDesign()->getTech()->getLayer(lNum)->getDir() - == dbTechLayerDir::HORIZONTAL); + const bool isH + = (tech_->getLayer(lNum)->getDir() == dbTechLayerDir::HORIZONTAL); bool isVia1Above = false; - frVia via1(viaDef1); + const frVia via1(viaDef1); Rect viaBox1; if (viaDef1->getLayer1Num() == lNum) { viaBox1 = via1.getLayer1BBox(); @@ -1262,12 +1256,12 @@ void FlexRP::prep_via2viaForbiddenLen_minimumCut( viaBox1 = via1.getLayer2BBox(); isVia1Above = false; } - Rect cutBox1 = via1.getCutBBox(); - int width1 = viaBox1.minDXDY(); - int length1 = viaBox1.maxDXDY(); + const Rect cutBox1 = via1.getCutBBox(); + const int width1 = viaBox1.minDXDY(); + const int length1 = viaBox1.maxDXDY(); bool isVia2Above = false; - frVia via2(viaDef2); + const frVia via2(viaDef2); Rect viaBox2; if (viaDef2->getLayer1Num() == lNum) { viaBox2 = via2.getLayer1BBox(); @@ -1276,12 +1270,11 @@ void FlexRP::prep_via2viaForbiddenLen_minimumCut( viaBox2 = via2.getLayer2BBox(); isVia2Above = false; } - Rect cutBox2 = via2.getCutBBox(); - int width2 = viaBox2.minDXDY(); - int length2 = viaBox2.maxDXDY(); + const Rect cutBox2 = via2.getCutBBox(); + const int width2 = viaBox2.minDXDY(); + const int length2 = viaBox2.maxDXDY(); - for (auto& con : - getDesign()->getTech()->getLayer(lNum)->getMinimumcutConstraints()) { + for (auto& con : tech_->getLayer(lNum)->getMinimumcutConstraints()) { frCoord minReqDist = INT_MIN; // check via2cut to via1metal // no length OR metal1 shape satisfies --> check via2 @@ -1290,15 +1283,14 @@ void FlexRP::prep_via2viaForbiddenLen_minimumCut( bool checkVia2 = false; if (!con->hasConnection()) { checkVia2 = true; - } else { - if (con->getConnection() == frMinimumcutConnectionEnum::FROMABOVE - && isVia2Above) { - checkVia2 = true; - } else if (con->getConnection() == frMinimumcutConnectionEnum::FROMBELOW - && !isVia2Above) { - checkVia2 = true; - } + } else if (con->getConnection() == frMinimumcutConnectionEnum::FROMABOVE + && isVia2Above) { + checkVia2 = true; + } else if (con->getConnection() == frMinimumcutConnectionEnum::FROMBELOW + && !isVia2Above) { + checkVia2 = true; } + if (!checkVia2) { continue; } @@ -1315,7 +1307,7 @@ void FlexRP::prep_via2viaForbiddenLen_minimumCut( + std::max(cutBox2.yMax() - 0 + 0 - viaBox1.yMin(), viaBox1.yMax() - 0 + 0 - cutBox2.yMin())); } - forbiddenRanges.push_back(std::make_pair(0, minReqDist)); + forbiddenRanges.push_back({0, minReqDist}); } minReqDist = INT_MIN; // check via1cut to via2metal @@ -1324,15 +1316,14 @@ void FlexRP::prep_via2viaForbiddenLen_minimumCut( bool checkVia1 = false; if (!con->hasConnection()) { checkVia1 = true; - } else { - if (con->getConnection() == frMinimumcutConnectionEnum::FROMABOVE - && isVia1Above) { - checkVia1 = true; - } else if (con->getConnection() == frMinimumcutConnectionEnum::FROMBELOW - && !isVia1Above) { - checkVia1 = true; - } + } else if (con->getConnection() == frMinimumcutConnectionEnum::FROMABOVE + && isVia1Above) { + checkVia1 = true; + } else if (con->getConnection() == frMinimumcutConnectionEnum::FROMBELOW + && !isVia1Above) { + checkVia1 = true; } + if (!checkVia1) { continue; } @@ -1349,7 +1340,7 @@ void FlexRP::prep_via2viaForbiddenLen_minimumCut( + std::max(cutBox1.yMax() - 0 + 0 - viaBox2.yMin(), viaBox2.yMax() - 0 + 0 - cutBox1.yMin())); } - forbiddenRanges.push_back(std::make_pair(0, minReqDist)); + forbiddenRanges.push_back({0, minReqDist}); } } } @@ -1388,7 +1379,7 @@ void FlexRP::prep_via2viaForbiddenLen_widthViaMap( lowerViaDef = viaDef2; } - const auto tech = getDesign()->getTech(); + const auto tech = tech_; const auto cutLayer = tech->getLayer(lowerViaDef->getCutLayerNum()); bool allow_stacking = true; for (const auto rule : cutLayer->getMetalWidthViaConstraints()) { @@ -1423,7 +1414,7 @@ void FlexRP::prep_via2viaForbiddenLen_widthViaMap( cutBox1.yMax() - viaBox2.yMin(), viaBox2.yMax() - cutBox1.yMin()}); } - forbiddenRanges.push_back(std::make_pair(0, minReqDist)); + forbiddenRanges.push_back({0, minReqDist}); debugPrint(logger_, utl::DRT, @@ -1436,48 +1427,44 @@ void FlexRP::prep_via2viaForbiddenLen_widthViaMap( } void FlexRP::prep_via2viaForbiddenLen_cutSpc(const frLayerNum& lNum, - frViaDef* viaDef1, - frViaDef* viaDef2, - bool isCurrDirX, + const frViaDef* viaDef1, + const frViaDef* viaDef2, + const bool isCurrDirX, ForbiddenRanges& forbiddenRanges) { if (!viaDef1 || !viaDef2) { return; } - bool isCurrDirY = !isCurrDirX; + const bool isCurrDirY = !isCurrDirX; - frVia via1(viaDef1); + const frVia via1(viaDef1); Rect viaBox1; if (viaDef1->getLayer1Num() == lNum) { viaBox1 = via1.getLayer1BBox(); } else { viaBox1 = via1.getLayer2BBox(); } - Rect cutBox1 = via1.getCutBBox(); + const Rect cutBox1 = via1.getCutBBox(); - frVia via2(viaDef2); + const frVia via2(viaDef2); Rect viaBox2; if (viaDef2->getLayer1Num() == lNum) { viaBox2 = via2.getLayer1BBox(); } else { viaBox2 = via2.getLayer2BBox(); } - Rect cutBox2 = via2.getCutBBox(); + const Rect cutBox2 = via2.getCutBBox(); // same layer (use samenet rule if exist, otherwise use diffnet rule) if (viaDef1->getCutLayerNum() == viaDef2->getCutLayerNum()) { - auto samenetCons = getDesign() - ->getTech() - ->getLayer(viaDef1->getCutLayerNum()) - ->getCutSpacing(true); - auto diffnetCons = getDesign() - ->getTech() - ->getLayer(viaDef1->getCutLayerNum()) - ->getCutSpacing(false); + const auto samenetCons + = tech_->getLayer(viaDef1->getCutLayerNum())->getCutSpacing(true); + const auto diffnetCons + = tech_->getLayer(viaDef1->getCutLayerNum())->getCutSpacing(false); if (!samenetCons.empty()) { // check samenet spacing rule if exists - for (auto con : samenetCons) { + for (const auto con : samenetCons) { if (con == nullptr) { continue; } @@ -1496,7 +1483,7 @@ void FlexRP::prep_via2viaForbiddenLen_cutSpc(const frLayerNum& lNum, } else { // check diffnet spacing rule if samenet rule does not exist // filter rule, assuming default via will never trigger cutArea - for (auto con : diffnetCons) { + for (const auto con : diffnetCons) { if (con == nullptr) { continue; } @@ -1512,18 +1499,14 @@ void FlexRP::prep_via2viaForbiddenLen_cutSpc(const frLayerNum& lNum, } } } else { - auto layerNum1 = viaDef1->getCutLayerNum(); - auto layerNum2 = viaDef2->getCutLayerNum(); - frCutSpacingConstraint* samenetCon = nullptr; - if (getDesign()->getTech()->getLayer(layerNum1)->hasInterLayerCutSpacing( - layerNum2, true)) { - samenetCon = getDesign() - ->getTech() - ->getLayer(layerNum1) - ->getInterLayerCutSpacing(layerNum2, true); + const auto layerNum1 = viaDef1->getCutLayerNum(); + const auto layerNum2 = viaDef2->getCutLayerNum(); + const frCutSpacingConstraint* samenetCon = nullptr; + if (tech_->getLayer(layerNum1)->hasInterLayerCutSpacing(layerNum2, true)) { + samenetCon = tech_->getLayer(layerNum1)->getInterLayerCutSpacing( + layerNum2, true); } - if (getDesign()->getTech()->getLayer(layerNum2)->hasInterLayerCutSpacing( - layerNum1, true)) { + if (tech_->getLayer(layerNum2)->hasInterLayerCutSpacing(layerNum1, true)) { if (samenetCon) { logger_->warn(DRT, 92, @@ -1532,22 +1515,18 @@ void FlexRP::prep_via2viaForbiddenLen_cutSpc(const frLayerNum& lNum, layerNum2, layerNum1); } else { - samenetCon = getDesign() - ->getTech() - ->getLayer(layerNum2) - ->getInterLayerCutSpacing(layerNum1, true); + samenetCon = tech_->getLayer(layerNum2)->getInterLayerCutSpacing( + layerNum1, true); } } if (samenetCon == nullptr) { - if (getDesign()->getTech()->getLayer(layerNum1)->hasInterLayerCutSpacing( - layerNum2, false)) { - samenetCon = getDesign() - ->getTech() - ->getLayer(layerNum1) - ->getInterLayerCutSpacing(layerNum2, false); + if (tech_->getLayer(layerNum1)->hasInterLayerCutSpacing(layerNum2, + false)) { + samenetCon = tech_->getLayer(layerNum1)->getInterLayerCutSpacing( + layerNum2, false); } - if (getDesign()->getTech()->getLayer(layerNum2)->hasInterLayerCutSpacing( - layerNum1, false)) { + if (tech_->getLayer(layerNum2)->hasInterLayerCutSpacing(layerNum1, + false)) { if (samenetCon) { logger_->warn(DRT, 93, @@ -1556,35 +1535,29 @@ void FlexRP::prep_via2viaForbiddenLen_cutSpc(const frLayerNum& lNum, layerNum2, layerNum1); } else { - samenetCon = getDesign() - ->getTech() - ->getLayer(layerNum2) - ->getInterLayerCutSpacing(layerNum1, false); + samenetCon = tech_->getLayer(layerNum2)->getInterLayerCutSpacing( + layerNum1, false); } } } if (samenetCon) { // filter rule, assuming default via will never trigger cutArea auto reqSpcVal = samenetCon->getCutSpacing(); - if (reqSpcVal == 0) { - ; - } else { - if (!samenetCon->hasCenterToCenter()) { - reqSpcVal += isCurrDirY ? ((cutBox1.dy() + cutBox2.dy()) / 2) - : ((cutBox1.dx() + cutBox2.dx()) / 2); - } + if (reqSpcVal != 0 && !samenetCon->hasCenterToCenter()) { + reqSpcVal += isCurrDirY ? ((cutBox1.dy() + cutBox2.dy()) / 2) + : ((cutBox1.dx() + cutBox2.dx()) / 2); } if (reqSpcVal != 0 && !samenetCon->hasStack()) { - forbiddenRanges.push_back(std::make_pair(0, reqSpcVal)); + forbiddenRanges.push_back({0, reqSpcVal}); } } } } void FlexRP::prep_via2viaForbiddenLen_minSpc(frLayerNum lNum, - frViaDef* viaDef1, - frViaDef* viaDef2, - bool isCurrDirX, + const frViaDef* viaDef1, + const frViaDef* viaDef2, + const bool isCurrDirX, ForbiddenRanges& forbiddenRanges, frNonDefaultRule* ndr) { @@ -1593,9 +1566,9 @@ void FlexRP::prep_via2viaForbiddenLen_minSpc(frLayerNum lNum, } // bool isCurrDirY = !isCurrDirX; - frCoord defaultWidth = getDesign()->getTech()->getLayer(lNum)->getWidth(); + const frCoord defaultWidth = tech_->getLayer(lNum)->getWidth(); - frVia via1(viaDef1); + const frVia via1(viaDef1); Rect viaBox1; if (viaDef1->getLayer1Num() == lNum) { viaBox1 = via1.getLayer1BBox(); @@ -1603,21 +1576,21 @@ void FlexRP::prep_via2viaForbiddenLen_minSpc(frLayerNum lNum, viaBox1 = via1.getLayer2BBox(); } auto width1 = viaBox1.minDXDY(); - bool isVia1Fat = isCurrDirX ? (viaBox1.dy() > defaultWidth) - : (viaBox1.dx() > defaultWidth); + const bool isVia1Fat = isCurrDirX ? (viaBox1.dy() > defaultWidth) + : (viaBox1.dx() > defaultWidth); auto prl1 = isCurrDirX ? viaBox1.dy() : viaBox1.dx(); - frVia via2(viaDef2); + const frVia via2(viaDef2); Rect viaBox2; if (viaDef2->getLayer1Num() == lNum) { viaBox2 = via2.getLayer1BBox(); } else { viaBox2 = via2.getLayer2BBox(); } - auto width2 = viaBox2.minDXDY(); - bool isVia2Fat = isCurrDirX ? (viaBox2.dy() > defaultWidth) - : (viaBox2.dx() > defaultWidth); - auto prl2 = isCurrDirX ? viaBox2.dy() : viaBox2.dx(); + const auto width2 = viaBox2.minDXDY(); + const bool isVia2Fat = isCurrDirX ? (viaBox2.dy() > defaultWidth) + : (viaBox2.dx() > defaultWidth); + const auto prl2 = isCurrDirX ? viaBox2.dy() : viaBox2.dx(); frCoord minNonOverlapDist = isCurrDirX ? ((viaBox1.dx() + viaBox2.dx()) / 2) : ((viaBox1.dy() + viaBox2.dy()) / 2); @@ -1625,7 +1598,7 @@ void FlexRP::prep_via2viaForbiddenLen_minSpc(frLayerNum lNum, // check minSpc rule if (isVia1Fat && isVia2Fat) { - auto con = getDesign()->getTech()->getLayer(lNum)->getMinSpacing(); + const auto con = tech_->getLayer(lNum)->getMinSpacing(); if (con) { if (con->typeId() == frConstraintTypeEnum::frcSpacingConstraint) { minReqDist = static_cast(con)->getMinSpacing(); @@ -1665,7 +1638,7 @@ void FlexRP::prep_via2viaForbiddenLen_minSpc(frLayerNum lNum, width1 = viaBox1.minDXDY(); prl1 = isCurrDirX ? viaBox1.dy() : viaBox1.dx(); minReqDist = INT_MIN; - auto con = getDesign()->getTech()->getLayer(lNum)->getMinSpacing(); + const auto con = tech_->getLayer(lNum)->getMinSpacing(); if (con) { if (con->typeId() == frConstraintTypeEnum::frcSpacingConstraint) { minReqDist = static_cast(con)->getMinSpacing(); @@ -1692,23 +1665,23 @@ void FlexRP::prep_via2viaForbiddenLen_minSpc(frLayerNum lNum, } } -void FlexRP::prep_via2viaPRL(frLayerNum lNum, - frViaDef* viaDef1, - frViaDef* viaDef2, - bool isCurrDirX, +void FlexRP::prep_via2viaPRL(const frLayerNum lNum, + const frViaDef* viaDef1, + const frViaDef* viaDef2, + const bool isCurrDirX, frCoord& prl) { if (!viaDef1 || !viaDef2) { return; } - frVia via1(viaDef1); + const frVia via1(viaDef1); Rect viaBox1; if (viaDef1->getLayer1Num() == lNum) { viaBox1 = via1.getLayer1BBox(); } else { viaBox1 = via1.getLayer2BBox(); } - frVia via2(viaDef2); + const frVia via2(viaDef2); Rect viaBox2; if (viaDef2->getLayer1Num() == lNum) { viaBox2 = via2.getLayer1BBox(); diff --git a/src/drt/src/serialization.h b/src/drt/src/serialization.h index 7b3d9b04300..2368a2db573 100644 --- a/src/drt/src/serialization.h +++ b/src/drt/src/serialization.h @@ -738,7 +738,7 @@ void serializeBlockObject(Archive& ar, frBlockObject*& obj) } template -void serializeViaDef(Archive& ar, frViaDef*& viadef) +void serializeViaDef(Archive& ar, const frViaDef*& viadef) { frDesign* design = ar.getDesign(); if (is_loading(ar)) { diff --git a/src/drt/src/ta/FlexTA.h b/src/drt/src/ta/FlexTA.h index 60f347ddd42..a37e03e331b 100644 --- a/src/drt/src/ta/FlexTA.h +++ b/src/drt/src/ta/FlexTA.h @@ -228,7 +228,7 @@ class FlexTAWorker frCoord initFixedObjs_calcBloatDist(frBlockObject* obj, frLayerNum lNum, const Rect& box); - frCoord initFixedObjs_calcOBSBloatDistVia(frViaDef* viaDef, + frCoord initFixedObjs_calcOBSBloatDistVia(const frViaDef* viaDef, frLayerNum lNum, const Rect& box, bool isOBS = true); diff --git a/src/drt/src/ta/FlexTA_assign.cpp b/src/drt/src/ta/FlexTA_assign.cpp index dbe7b6b148a..0077bfbfc54 100644 --- a/src/drt/src/ta/FlexTA_assign.cpp +++ b/src/drt/src/ta/FlexTA_assign.cpp @@ -144,7 +144,7 @@ void FlexTAWorker::modMinSpacingCostVia( frCoord length1 = box.maxDXDY(); // obj2 = other obj // default via dimension - frViaDef* viaDef = nullptr; + const frViaDef* viaDef = nullptr; frLayerNum cutLNum = 0; if (isUpperVia) { viaDef @@ -326,7 +326,8 @@ void FlexTAWorker::modCutSpacingCost(const Rect& box, // obj1 = curr obj // obj2 = other obj // default via dimension - frViaDef* viaDef = getDesign()->getTech()->getLayer(lNum)->getDefaultViaDef(); + const frViaDef* viaDef + = getDesign()->getTech()->getLayer(lNum)->getDefaultViaDef(); frVia via(viaDef); Rect viaBox = via.getCutBBox(); @@ -590,7 +591,7 @@ void FlexTAWorker::assignIroute_availTracks(taPin* iroute, coordHigh--; // to avoid higher track == guide top/right if (getTech()->getLayer(lNum)->isUnidirectional()) { const Rect& dieBx = design_->getTopBlock()->getDieBox(); - frViaDef* via = nullptr; + const frViaDef* via = nullptr; Rect testBox; if (lNum + 1 <= getTech()->getTopLayerNum()) { via = getTech()->getLayer(lNum + 1)->getDefaultViaDef(); diff --git a/src/drt/src/ta/FlexTA_init.cpp b/src/drt/src/ta/FlexTA_init.cpp index f9ff51fbd08..02940b40f6a 100644 --- a/src/drt/src/ta/FlexTA_init.cpp +++ b/src/drt/src/ta/FlexTA_init.cpp @@ -487,7 +487,7 @@ void FlexTAWorker::initIroute(frGuide* guide) } // owner set when add to taPin iroute->addPinFig(std::move(ps)); - frViaDef* viaDef; + const frViaDef* viaDef; for (auto coord : upViaCoordSet) { if (guide->getNet()->getNondefaultRule() && guide->getNet()->getNondefaultRule()->getPrefVia(layerNum / 2 - 1)) { @@ -815,7 +815,7 @@ void FlexTAWorker::initFixedObjs() } } -frCoord FlexTAWorker::initFixedObjs_calcOBSBloatDistVia(frViaDef* viaDef, +frCoord FlexTAWorker::initFixedObjs_calcOBSBloatDistVia(const frViaDef* viaDef, const frLayerNum lNum, const Rect& box, bool isOBS) From 670e1fe23b1db9c1c42acc53261372d8bcd5ba6a Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Wed, 18 Dec 2024 03:36:02 +0000 Subject: [PATCH 81/98] ord: add to the commands_without_load.tcl test passing 1-3 args Catches a few more bugs Signed-off-by: Matt Liberty --- src/par/src/PartitionMgr.cpp | 6 ++++-- src/ppl/include/ppl/IOPlacer.h | 2 ++ src/ppl/src/IOPlacer.cpp | 8 +++++++- test/commands_without_load.tcl | 14 +++++++++++++- 4 files changed, 26 insertions(+), 4 deletions(-) diff --git a/src/par/src/PartitionMgr.cpp b/src/par/src/PartitionMgr.cpp index e1bce9f6fa5..f9a63c7d2b5 100644 --- a/src/par/src/PartitionMgr.cpp +++ b/src/par/src/PartitionMgr.cpp @@ -754,8 +754,10 @@ Instance* PartitionMgr::buildPartitionedTopInstance(const char* name, odb::dbBlock* PartitionMgr::getDbBlock() const { odb::dbChip* chip = db_->getChip(); - odb::dbBlock* block = chip->getBlock(); - return block; + if (!chip) { + return nullptr; + } + return chip->getBlock(); } void PartitionMgr::writePartitionVerilog(const char* file_name, diff --git a/src/ppl/include/ppl/IOPlacer.h b/src/ppl/include/ppl/IOPlacer.h index 808a2af9bb0..0f750ba0340 100644 --- a/src/ppl/include/ppl/IOPlacer.h +++ b/src/ppl/include/ppl/IOPlacer.h @@ -44,6 +44,7 @@ #include "odb/db.h" #include "odb/geom.h" #include "ppl/Parameters.h" +#include "utl/validation.h" namespace utl { class Logger; @@ -314,6 +315,7 @@ class IOPlacer std::map> layer_fixed_pins_shapes_; Logger* logger_ = nullptr; + std::unique_ptr validator_; std::unique_ptr parms_; std::vector slots_; std::vector top_layer_slots_; diff --git a/src/ppl/src/IOPlacer.cpp b/src/ppl/src/IOPlacer.cpp index 42edf120a87..47c1e906fee 100644 --- a/src/ppl/src/IOPlacer.cpp +++ b/src/ppl/src/IOPlacer.cpp @@ -70,11 +70,16 @@ void IOPlacer::init(odb::dbDatabase* db, Logger* logger) db_ = db; logger_ = logger; parms_ = std::make_unique(); + validator_ = std::make_unique(logger, PPL); } odb::dbBlock* IOPlacer::getBlock() const { - return db_->getChip()->getBlock(); + auto chip = db_->getChip(); + if (!chip) { + return nullptr; + } + return chip->getBlock(); } odb::dbTech* IOPlacer::getTech() const @@ -693,6 +698,7 @@ void IOPlacer::getBlockedRegionsFromDbObstructions() void IOPlacer::writePinPlacement(const char* file_name, const bool placed) { + validator_->check_non_null("Block", getBlock(), 113); std::string filename = file_name; if (filename.empty()) { return; diff --git a/test/commands_without_load.tcl b/test/commands_without_load.tcl index 90524b21fdf..7555acbbaab 100644 --- a/test/commands_without_load.tcl +++ b/test/commands_without_load.tcl @@ -1,15 +1,27 @@ # Ensure that running commands without loading a design doesn't crash. +source "helpers.tcl" +# make_port: parallaxsw/OpenSTA/issues/149 set skip { - define_corners + make_port + exit_summary + run_unit_test_and_exit + vwait exit } +set arg [make_result_file commands_without_load] + foreach command [info commands] { if {[lsearch $skip $command] != -1} { puts "skip $command" } else { + puts "TEST: $command" catch {$command} msg + catch {$command $arg} msg + catch {$command $arg $arg} msg + catch {$command $arg $arg $arg} msg + file delete $arg } } From 950000a2210876cf9f0bac9e019b59a2729ec813 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Wed, 18 Dec 2024 09:02:35 -0700 Subject: [PATCH 82/98] ord: remove charts from options as this is not optional anymore Signed-off-by: Peter Gadfort --- CMakeLists.txt | 1 - include/ord/OpenRoad.hh | 1 - src/Main.cc | 3 +-- src/OpenRoad.cc | 5 ----- src/OpenRoad.i | 6 ------ 5 files changed, 1 insertion(+), 15 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 6e43cfd959a..0cda2d501c2 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -174,7 +174,6 @@ add_subdirectory(test) target_compile_definitions(openroad PRIVATE GPU) target_compile_definitions(openroad PRIVATE BUILD_PYTHON) target_compile_definitions(openroad PRIVATE BUILD_GUI) -target_compile_definitions(openroad PRIVATE ENABLE_CHARTS) #################################################################### diff --git a/include/ord/OpenRoad.hh b/include/ord/OpenRoad.hh index 613b2a85f77..831f9f4c4b3 100644 --- a/include/ord/OpenRoad.hh +++ b/include/ord/OpenRoad.hh @@ -260,7 +260,6 @@ class OpenRoad static bool getGPUCompileOption(); static bool getPythonCompileOption(); static bool getGUICompileOption(); - static bool getChartsCompileOption(); protected: ~OpenRoad(); diff --git a/src/Main.cc b/src/Main.cc index 6231e558f62..69671b938b1 100644 --- a/src/Main.cc +++ b/src/Main.cc @@ -575,8 +575,7 @@ static void showSplash() ord::OpenRoad::getGitDescribe()); logger->report( "Features included (+) or not (-): " - "{}Charts {}GPU {}GUI {}Python{}", - ord::OpenRoad::getChartsCompileOption() ? "+" : "-", + "{}GPU {}GUI {}Python{}", ord::OpenRoad::getGPUCompileOption() ? "+" : "-", ord::OpenRoad::getGUICompileOption() ? "+" : "-", ord::OpenRoad::getPythonCompileOption() ? "+" : "-", diff --git a/src/OpenRoad.cc b/src/OpenRoad.cc index c9440420b13..cb91a3321c2 100644 --- a/src/OpenRoad.cc +++ b/src/OpenRoad.cc @@ -700,9 +700,4 @@ bool OpenRoad::getGUICompileOption() return BUILD_GUI; } -bool OpenRoad::getChartsCompileOption() -{ - return ENABLE_CHARTS; -} - } // namespace ord diff --git a/src/OpenRoad.i b/src/OpenRoad.i index b16a90c2a6a..ce1ca3690a4 100644 --- a/src/OpenRoad.i +++ b/src/OpenRoad.i @@ -323,12 +323,6 @@ openroad_gui_compiled() return ord::OpenRoad::getGUICompileOption(); } -const bool -openroad_charts_compiled() -{ - return ord::OpenRoad::getChartsCompileOption(); -} - void read_lef_cmd(const char *filename, const char *lib_name, From 2c69aa2f1e234ed15066ba4d6ce0607b751e6ce9 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Wed, 18 Dec 2024 09:22:57 -0700 Subject: [PATCH 83/98] gui: check for QThreads before updating cursors Signed-off-by: Peter Gadfort --- src/gui/src/heatMap.cpp | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/gui/src/heatMap.cpp b/src/gui/src/heatMap.cpp index d45d274dc20..d93bcb019c0 100644 --- a/src/gui/src/heatMap.cpp +++ b/src/gui/src/heatMap.cpp @@ -33,6 +33,7 @@ #include "gui/heatMap.h" #include +#include #include #include #include @@ -533,11 +534,15 @@ void HeatMapDataSource::ensureMap() if (build_map || !isPopulated()) { debugPrint(logger_, utl::GUI, "HeatMap", 1, "Populating map"); - if (gui::Gui::enabled()) { + const bool update_cursor + = gui::Gui::enabled() + && QApplication::instance()->thread() == QThread::currentThread(); + + if (update_cursor) { QApplication::setOverrideCursor(Qt::WaitCursor); } populated_ = populateMap(); - if (gui::Gui::enabled()) { + if (update_cursor) { QApplication::restoreOverrideCursor(); } From 5e86f360a7d483e8b4df0c9ceb139f1c02cb44ed Mon Sep 17 00:00:00 2001 From: luis201420 Date: Wed, 18 Dec 2024 16:48:51 +0000 Subject: [PATCH 84/98] ant: limit mutex lock scope Signed-off-by: luis201420 --- src/ant/src/AntennaChecker.cc | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/ant/src/AntennaChecker.cc b/src/ant/src/AntennaChecker.cc index 18a2c6b0a05..8d79b506dca 100644 --- a/src/ant/src/AntennaChecker.cc +++ b/src/ant/src/AntennaChecker.cc @@ -100,11 +100,13 @@ void AntennaChecker::initAntennaRules() odb::dbTech* tech = db_->getTech(); // initialize nets_to_report_ with all nets to avoid issues with // multithreading - std::lock_guard lock(map_mutex_); - if (net_to_report_.empty()) { - for (odb::dbNet* net : block_->getNets()) { - if (!net->isSpecial()) { - net_to_report_[net]; + { + std::lock_guard lock(map_mutex_); + if (net_to_report_.empty()) { + for (odb::dbNet* net : block_->getNets()) { + if (!net->isSpecial()) { + net_to_report_[net]; + } } } } From 06152a6c3ba33e96e00087894869a870ad4d19e3 Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Wed, 18 Dec 2024 16:50:00 +0000 Subject: [PATCH 85/98] rsz: handle dangling iterms in remove_buffers Signed-off-by: Matt Liberty --- src/rsz/src/Resizer.cc | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/rsz/src/Resizer.cc b/src/rsz/src/Resizer.cc index 73c26540c34..a6c32d4f1bc 100644 --- a/src/rsz/src/Resizer.cc +++ b/src/rsz/src/Resizer.cc @@ -342,13 +342,18 @@ bool Resizer::removeBuffer(Instance* buffer, dbNet* in_db_net = db_network_->staToDb(in_net); dbNet* out_db_net = db_network_->staToDb(out_net); // honor net dont-touch on input net or output net - if (in_db_net->isDoNotTouch() || out_db_net->isDoNotTouch()) { + if ((in_db_net && in_db_net->isDoNotTouch()) + || (out_db_net && out_db_net->isDoNotTouch())) { if (honorDontTouchFixed) { return false; } // remove net dont touch for manual ECO - in_db_net->setDoNotTouch(false); - out_db_net->setDoNotTouch(false); + if (in_db_net) { + in_db_net->setDoNotTouch(false); + } + if (out_db_net) { + out_db_net->setDoNotTouch(false); + } } bool out_net_ports = hasPort(out_net); Net *survivor, *removed; From 50bef4f50694d9308a1d234250b63bcdb3ffda5b Mon Sep 17 00:00:00 2001 From: luis201420 Date: Wed, 18 Dec 2024 17:53:01 +0000 Subject: [PATCH 86/98] ant: Refactor variable update to occur outside the function Signed-off-by: luis201420 --- src/ant/include/ant/AntennaChecker.hh | 14 +++---- src/ant/src/AntennaChecker.cc | 58 +++++++++------------------ 2 files changed, 25 insertions(+), 47 deletions(-) diff --git a/src/ant/include/ant/AntennaChecker.hh b/src/ant/include/ant/AntennaChecker.hh index 9a0ef13c521..ef830d03999 100644 --- a/src/ant/include/ant/AntennaChecker.hh +++ b/src/ant/include/ant/AntennaChecker.hh @@ -178,14 +178,12 @@ class AntennaChecker getViolatedWireLength(odb::dbNet* net, int routing_level); bool isValidGate(odb::dbMTerm* mterm); void buildLayerMaps(odb::dbNet* net, LayerToGraphNodes& node_by_layer_map); - void checkNet(odb::dbNet* net, - bool verbose, - bool save_report, - odb::dbMTerm* diode_mterm, - float ratio_margin, - int& net_violation_count, - int& pin_violation_count, - Violations& antenna_violations); + int checkNet(odb::dbNet* net, + bool verbose, + bool save_report, + odb::dbMTerm* diode_mterm, + float ratio_margin, + Violations& antenna_violations); void saveGates(odb::dbNet* db_net, LayerToGraphNodes& node_by_layer_map, int node_count); diff --git a/src/ant/src/AntennaChecker.cc b/src/ant/src/AntennaChecker.cc index 8d79b506dca..ed1f9e48c4e 100644 --- a/src/ant/src/AntennaChecker.cc +++ b/src/ant/src/AntennaChecker.cc @@ -1019,14 +1019,12 @@ void AntennaChecker::buildLayerMaps(odb::dbNet* db_net, saveGates(db_net, node_by_layer_map, node_count); } -void AntennaChecker::checkNet(odb::dbNet* db_net, - bool verbose, - bool save_report, - odb::dbMTerm* diode_mterm, - float ratio_margin, - int& net_violation_count, - int& pin_violation_count, - Violations& antenna_violations) +int AntennaChecker::checkNet(odb::dbNet* db_net, + bool verbose, + bool save_report, + odb::dbMTerm* diode_mterm, + float ratio_margin, + Violations& antenna_violations) { odb::dbWire* wire = db_net->getWire(); if (wire) { @@ -1047,10 +1045,7 @@ void AntennaChecker::checkNet(odb::dbNet* db_net, gate_info, antenna_violations); - if (pin_violations > 0) { - net_violation_count++; - pin_violation_count += pin_violations; - } + return pin_violations; } } @@ -1063,17 +1058,8 @@ Violations AntennaChecker::getAntennaViolations(odb::dbNet* net, return antenna_violations; } - int net_violation_count, pin_violation_count; - net_violation_count = 0; - pin_violation_count = 0; - checkNet(net, - false, - false, - diode_mterm, - ratio_margin, - net_violation_count, - pin_violation_count, - antenna_violations); + int pin_violation_count = checkNet( + net, false, false, diode_mterm, ratio_margin, antenna_violations); return antenna_violations; } @@ -1116,14 +1102,11 @@ int AntennaChecker::checkAntennas(odb::dbNet* net, if (net) { Violations antenna_violations; if (!net->isSpecial()) { - checkNet(net, - verbose, - true, - nullptr, - 0, - net_violation_count, - pin_violation_count, - antenna_violations); + pin_violation_count + += checkNet(net, verbose, true, nullptr, 0, antenna_violations); + if (pin_violation_count > 0) { + net_violation_count++; + } } else { logger_->error( ANT, 14, "Skipped net {} because it is special.", net->getName()); @@ -1141,14 +1124,11 @@ int AntennaChecker::checkAntennas(odb::dbNet* net, for (int i = 0; i < nets_.size(); i++) { odb::dbNet* net = nets_[i]; Violations antenna_violations; - checkNet(net, - verbose, - true, - nullptr, - 0, - net_violation_count, - pin_violation_count, - antenna_violations); + pin_violation_count + += checkNet(net, verbose, true, nullptr, 0, antenna_violations); + if (pin_violation_count > 0) { + net_violation_count++; + } } } From 24bb7a108f660f1169bed21d342e746dd7479c33 Mon Sep 17 00:00:00 2001 From: luis201420 Date: Wed, 18 Dec 2024 20:24:47 +0000 Subject: [PATCH 87/98] ant: Fixing small bugs Signed-off-by: luis201420 --- src/ant/src/AntennaChecker.cc | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/src/ant/src/AntennaChecker.cc b/src/ant/src/AntennaChecker.cc index ed1f9e48c4e..9f36785a97e 100644 --- a/src/ant/src/AntennaChecker.cc +++ b/src/ant/src/AntennaChecker.cc @@ -1027,6 +1027,7 @@ int AntennaChecker::checkNet(odb::dbNet* db_net, Violations& antenna_violations) { odb::dbWire* wire = db_net->getWire(); + int pin_violations = 0; if (wire) { LayerToGraphNodes node_by_layer_map; GateToLayerToNodeInfo gate_info; @@ -1037,16 +1038,15 @@ int AntennaChecker::checkNet(odb::dbNet* db_net, calculatePAR(gate_info); calculateCAR(gate_info); - int pin_violations = checkGates(db_net, - verbose, - save_report, - diode_mterm, - ratio_margin, - gate_info, - antenna_violations); - - return pin_violations; + pin_violations = checkGates(db_net, + verbose, + save_report, + diode_mterm, + ratio_margin, + gate_info, + antenna_violations); } + return pin_violations; } Violations AntennaChecker::getAntennaViolations(odb::dbNet* net, @@ -1058,8 +1058,7 @@ Violations AntennaChecker::getAntennaViolations(odb::dbNet* net, return antenna_violations; } - int pin_violation_count = checkNet( - net, false, false, diode_mterm, ratio_margin, antenna_violations); + checkNet(net, false, false, diode_mterm, ratio_margin, antenna_violations); return antenna_violations; } @@ -1124,10 +1123,11 @@ int AntennaChecker::checkAntennas(odb::dbNet* net, for (int i = 0; i < nets_.size(); i++) { odb::dbNet* net = nets_[i]; Violations antenna_violations; - pin_violation_count - += checkNet(net, verbose, true, nullptr, 0, antenna_violations); - if (pin_violation_count > 0) { + int pin_viol_count + = checkNet(net, verbose, true, nullptr, 0, antenna_violations); + if (pin_viol_count > 0) { net_violation_count++; + pin_violation_count += pin_viol_count; } } } From 2b0a9b4ff9f259a316269f400ce1929f677fd47f Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Thu, 19 Dec 2024 00:07:56 +0000 Subject: [PATCH 88/98] gui: display the source info in the inspector correctly Interpret the raw odb properties. Follow on work could enable it as a link. Signed-off-by: Matt Liberty --- src/gui/src/dbDescriptors.cpp | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/src/gui/src/dbDescriptors.cpp b/src/gui/src/dbDescriptors.cpp index 320a6b8013a..0bf0786963f 100644 --- a/src/gui/src/dbDescriptors.cpp +++ b/src/gui/src/dbDescriptors.cpp @@ -57,6 +57,8 @@ static void populateODBProperties(Descriptor::Properties& props, odb::dbObject* object, const std::string& prefix = "") { + std::optional src_file_id; + std::optional src_file_line; Descriptor::PropertyList prop_list; for (const auto prop : odb::dbProperty::getProperties(object)) { std::any value; @@ -88,7 +90,26 @@ static void populateODBProperties(Descriptor::Properties& props, value = static_cast(prop)->getValue(); break; } - prop_list.emplace_back(prop->getName(), value); + // Look for the file name properties from Verilog2db::storeLineInfo + if (prop->getName() == "src_file_id") { + src_file_id = std::any_cast(value); + } else if (prop->getName() == "src_file_line") { + src_file_line = std::any_cast(value); + } else { + prop_list.emplace_back(prop->getName(), value); + } + } + + if (src_file_id && src_file_line) { + auto block = object->getDb()->getChip()->getBlock(); + const auto src_file = fmt::format("src_file_{}", src_file_id.value()); + const auto file_name_prop + = odb::dbStringProperty::find(block, src_file.c_str()); + if (file_name_prop) { + const auto info = fmt::format( + "{}:{}", file_name_prop->getValue(), src_file_line.value()); + prop_list.emplace_back("Source", info); + } } if (!prop_list.empty()) { From 9df281c89586b64dc87f5ae40c7839eb38b65e90 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Wed, 18 Dec 2024 20:50:09 -0700 Subject: [PATCH 89/98] ord: allow exception to be traced via set_debug_level ORD trace 1 Signed-off-by: Peter Gadfort --- src/Exception.i | 18 ++++++++++++++++++ src/cmake/swig_lib.cmake | 8 +++++++- src/odb/src/swig/tcl/CMakeLists.txt | 1 + 3 files changed, 26 insertions(+), 1 deletion(-) diff --git a/src/Exception.i b/src/Exception.i index 91899547d9e..056b70469c6 100644 --- a/src/Exception.i +++ b/src/Exception.i @@ -16,6 +16,14 @@ %{ #include + +#ifndef TEST_BUILD +#include +#include + +#include "ord/OpenRoad.hh" +#include "utl/Logger.h" +#endif %} %exception { @@ -26,6 +34,16 @@ } // This catches std::runtime_error (utl::error) and sta::Exception. catch (std::exception &excp) { +%#ifndef TEST_BUILD + auto logger = ord::OpenRoad::openRoad()->getLogger(); + if (logger->debugCheck(utl::ORD, "trace", 1)) { + std::stringstream trace; + trace << boost::stacktrace::stacktrace(); + logger->report("Stack trace"); + logger->report(trace.str()); + } +%#endif + Tcl_ResetResult(interp); Tcl_AppendResult(interp, excp.what(), nullptr); return TCL_ERROR; diff --git a/src/cmake/swig_lib.cmake b/src/cmake/swig_lib.cmake index fa93b3fa217..e50f0fb4522 100644 --- a/src/cmake/swig_lib.cmake +++ b/src/cmake/swig_lib.cmake @@ -15,7 +15,7 @@ function(swig_lib) # Parse args set(options "") set(oneValueArgs I_FILE NAME NAMESPACE LANGUAGE RUNTIME_HEADER) - set(multiValueArgs SWIG_INCLUDES SCRIPTS) + set(multiValueArgs SWIG_INCLUDES SCRIPTS DEFINES) cmake_parse_arguments( ARG # prefix on the parsed args @@ -130,6 +130,12 @@ function(swig_lib) ) endif() + if (DEFINED ARG_DEFINES) + target_compile_definitions(${ARG_NAME} + PRIVATE ${ARG_DEFINES} + ) + endif() + # Generate the encoded of the script files. if (DEFINED ARG_SCRIPTS) set(LANG_INIT ${CMAKE_CURRENT_BINARY_DIR}/${ARG_NAME}-${ARG_LANGUAGE}InitVar.cc) diff --git a/src/odb/src/swig/tcl/CMakeLists.txt b/src/odb/src/swig/tcl/CMakeLists.txt index 46eed4301b9..5110e8c6342 100644 --- a/src/odb/src/swig/tcl/CMakeLists.txt +++ b/src/odb/src/swig/tcl/CMakeLists.txt @@ -5,6 +5,7 @@ swig_lib(NAME odbtcl I_FILE ../common/odb.i SWIG_INCLUDES ${PROJECT_SOURCE_DIR}/include ${PROJECT_SOURCE_DIR}/src/swig/tcl + DEFINES TEST_BUILD ) target_include_directories(odbtcl From 477798b4c5b79d21e1849a82ac23a2f1a721b573 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Wed, 18 Dec 2024 20:50:50 -0700 Subject: [PATCH 90/98] ord: use abort instead of exit to allow for stacktrace to be printed Signed-off-by: Peter Gadfort --- src/Exception.i | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/Exception.i b/src/Exception.i index 056b70469c6..6a9f045a43a 100644 --- a/src/Exception.i +++ b/src/Exception.i @@ -16,6 +16,7 @@ %{ #include +#include #ifndef TEST_BUILD #include @@ -30,7 +31,7 @@ try { $function } catch (std::bad_alloc &) { fprintf(stderr, "Error: out of memory."); - exit(1); + abort(); } // This catches std::runtime_error (utl::error) and sta::Exception. catch (std::exception &excp) { From 91c6498c135292ea38752eb41286ffb075ee789f Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 19 Dec 2024 09:48:00 -0700 Subject: [PATCH 91/98] ord: remove TEST_BUILD define and replace with correct stub.cpp Signed-off-by: Peter Gadfort --- src/Exception.i | 19 +++++++------ src/cmake/swig_lib.cmake | 8 +----- src/odb/src/swig/tcl/CMakeLists.txt | 4 ++- src/odb/src/swig/tcl/stub.cpp | 42 +++++++++++++++++++++++++++++ 4 files changed, 55 insertions(+), 18 deletions(-) create mode 100644 src/odb/src/swig/tcl/stub.cpp diff --git a/src/Exception.i b/src/Exception.i index 6a9f045a43a..ecea128991e 100644 --- a/src/Exception.i +++ b/src/Exception.i @@ -18,13 +18,11 @@ #include #include -#ifndef TEST_BUILD #include #include #include "ord/OpenRoad.hh" #include "utl/Logger.h" -#endif %} %exception { @@ -35,15 +33,16 @@ } // This catches std::runtime_error (utl::error) and sta::Exception. catch (std::exception &excp) { -%#ifndef TEST_BUILD - auto logger = ord::OpenRoad::openRoad()->getLogger(); - if (logger->debugCheck(utl::ORD, "trace", 1)) { - std::stringstream trace; - trace << boost::stacktrace::stacktrace(); - logger->report("Stack trace"); - logger->report(trace.str()); + auto* openroad = ord::OpenRoad::openRoad(); + if (openroad != nullptr) { + auto* logger = openroad->getLogger(); + if (logger->debugCheck(utl::ORD, "trace", 1)) { + std::stringstream trace; + trace << boost::stacktrace::stacktrace(); + logger->report("Stack trace"); + logger->report(trace.str()); + } } -%#endif Tcl_ResetResult(interp); Tcl_AppendResult(interp, excp.what(), nullptr); diff --git a/src/cmake/swig_lib.cmake b/src/cmake/swig_lib.cmake index e50f0fb4522..fa93b3fa217 100644 --- a/src/cmake/swig_lib.cmake +++ b/src/cmake/swig_lib.cmake @@ -15,7 +15,7 @@ function(swig_lib) # Parse args set(options "") set(oneValueArgs I_FILE NAME NAMESPACE LANGUAGE RUNTIME_HEADER) - set(multiValueArgs SWIG_INCLUDES SCRIPTS DEFINES) + set(multiValueArgs SWIG_INCLUDES SCRIPTS) cmake_parse_arguments( ARG # prefix on the parsed args @@ -130,12 +130,6 @@ function(swig_lib) ) endif() - if (DEFINED ARG_DEFINES) - target_compile_definitions(${ARG_NAME} - PRIVATE ${ARG_DEFINES} - ) - endif() - # Generate the encoded of the script files. if (DEFINED ARG_SCRIPTS) set(LANG_INIT ${CMAKE_CURRENT_BINARY_DIR}/${ARG_NAME}-${ARG_LANGUAGE}InitVar.cc) diff --git a/src/odb/src/swig/tcl/CMakeLists.txt b/src/odb/src/swig/tcl/CMakeLists.txt index 5110e8c6342..65f0722ade8 100644 --- a/src/odb/src/swig/tcl/CMakeLists.txt +++ b/src/odb/src/swig/tcl/CMakeLists.txt @@ -5,7 +5,6 @@ swig_lib(NAME odbtcl I_FILE ../common/odb.i SWIG_INCLUDES ${PROJECT_SOURCE_DIR}/include ${PROJECT_SOURCE_DIR}/src/swig/tcl - DEFINES TEST_BUILD ) target_include_directories(odbtcl @@ -26,11 +25,14 @@ target_link_libraries(odbtcl # Executable add_executable(odbtcl-bin main.cpp + stub.cpp ) target_include_directories(odbtcl-bin PUBLIC ${PROJECT_SOURCE_DIR}/include/odb + PRIVATE + ${OPENROAD_HOME}/include ) target_link_libraries(odbtcl-bin diff --git a/src/odb/src/swig/tcl/stub.cpp b/src/odb/src/swig/tcl/stub.cpp new file mode 100644 index 00000000000..d7780e36037 --- /dev/null +++ b/src/odb/src/swig/tcl/stub.cpp @@ -0,0 +1,42 @@ +/////////////////////////////////////////////////////////////////////////////// +// BSD 3-Clause License +// +// Copyright (c) 2024, The Regents of the University of California +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#include "ord/OpenRoad.hh" + +namespace ord { + +OpenRoad* OpenRoad::openRoad() +{ + return nullptr; +} + +} // namespace ord From 2c10b9f98fc4b98f9e29f576b9a02f8895f76f8a Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 19 Dec 2024 10:56:31 -0700 Subject: [PATCH 92/98] ord: add stacktrace to python exception Signed-off-by: Peter Gadfort --- src/Exception-py.i | 31 ++++++++++++++++++++++++++++++- src/par/CMakeLists.txt | 1 + 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/src/Exception-py.i b/src/Exception-py.i index 30686eec216..7d47627e4e4 100644 --- a/src/Exception-py.i +++ b/src/Exception-py.i @@ -32,20 +32,49 @@ /////////////////////////////////////////////////////////////////////////////// %{ +#include + +#include +#include + +#include "ord/OpenRoad.hh" +#include "utl/Logger.h" %} %exception { try { $function } catch (std::bad_alloc &) { fprintf(stderr, "Error: out of memory."); - exit(0); + abort(); } // This catches std::runtime_error (utl::error) and sta::Exception. catch (std::exception &excp) { + auto* openroad = ord::OpenRoad::openRoad(); + if (openroad != nullptr) { + auto* logger = openroad->getLogger(); + if (logger->debugCheck(utl::ORD, "trace", 1)) { + std::stringstream trace; + trace << boost::stacktrace::stacktrace(); + logger->report("Stack trace"); + logger->report(trace.str()); + } + } + PyErr_SetString(PyExc_RuntimeError, excp.what()); SWIG_fail; } catch (...) { + auto* openroad = ord::OpenRoad::openRoad(); + if (openroad != nullptr) { + auto* logger = openroad->getLogger(); + if (logger->debugCheck(utl::ORD, "trace", 1)) { + std::stringstream trace; + trace << boost::stacktrace::stacktrace(); + logger->report("Stack trace"); + logger->report(trace.str()); + } + } + PyErr_SetString(PyExc_Exception, "Unknown exception"); SWIG_fail; } diff --git a/src/par/CMakeLists.txt b/src/par/CMakeLists.txt index da78b853f76..dd274b9f315 100644 --- a/src/par/CMakeLists.txt +++ b/src/par/CMakeLists.txt @@ -154,6 +154,7 @@ if (Python3_FOUND AND BUILD_PYTHON) target_link_libraries(par_py PUBLIC par_lib + utl_lib ) endif() From a5d3c01a06f810bae35211ea0600d22d941ab168 Mon Sep 17 00:00:00 2001 From: Christian Costa Date: Thu, 19 Dec 2024 19:15:16 +0100 Subject: [PATCH 93/98] cts: Prevent crash when -buf_list or -root_buf has non existing master cell. Signed-off-by: Christian Costa --- src/cts/src/TritonCTS.cpp | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp index 52c1aff048b..0c2420c8ecd 100644 --- a/src/cts/src/TritonCTS.cpp +++ b/src/cts/src/TritonCTS.cpp @@ -611,6 +611,13 @@ void TritonCTS::setBufferList(const char* buffers) std::vector bufferList(begin, end); if (bufferList.empty()) { inferBufferList(bufferList); + } else { + for (const std::string& buffer : bufferList) { + if (db_->findMaster(buffer.c_str()) == nullptr) { + logger_->error( + CTS, 126, "No physical master cell found for buffer {}.", buffer); + } + } } options_->setBufferList(bufferList); } @@ -744,6 +751,12 @@ void TritonCTS::setRootBuffer(const char* buffers) std::istream_iterator begin(ss); std::istream_iterator end; std::vector bufferList(begin, end); + for (const std::string& buffer : bufferList) { + if (db_->findMaster(buffer.c_str()) == nullptr) { + logger_->error( + CTS, 127, "No physical master cell found for buffer {}.", buffer); + } + } rootBuffers_ = std::move(bufferList); } From 25952a95eeafe75868ba805706f6df45c2d2bfe7 Mon Sep 17 00:00:00 2001 From: Arthur Koucher Date: Thu, 19 Dec 2024 15:27:32 -0300 Subject: [PATCH 94/98] mpl2: throw error when PAR gives MPL2 a completely unbalanced solution Signed-off-by: Arthur Koucher --- src/mpl2/src/clusterEngine.cpp | 29 +++++++++++++++++++++++++++++ src/mpl2/src/clusterEngine.h | 2 ++ 2 files changed, 31 insertions(+) diff --git a/src/mpl2/src/clusterEngine.cpp b/src/mpl2/src/clusterEngine.cpp index 57acba0026a..c0d413d5d04 100644 --- a/src/mpl2/src/clusterEngine.cpp +++ b/src/mpl2/src/clusterEngine.cpp @@ -1452,6 +1452,14 @@ void ClusteringEngine::breakLargeFlatCluster(Cluster* parent) vertex_weight, hyperedge_weights); + if (partitionerSolutionIsFullyUnbalanced(part, num_other_cluster_vertices)) { + logger_->error(MPL, + 37, + "Couldn't break flat cluster {} with PAR. The solution is " + "fully unbalanced.", + parent->getName()); + } + parent->clearLeafStdCells(); parent->clearLeafMacros(); @@ -1481,6 +1489,27 @@ void ClusteringEngine::breakLargeFlatCluster(Cluster* parent) breakLargeFlatCluster(raw_part_1); } +bool ClusteringEngine::partitionerSolutionIsFullyUnbalanced( + const std::vector& solution, + const int num_other_cluster_vertices) +{ + // The partition of the first vertex which represents + // an actual macro or std cell. + const int first_vertex_partition = solution[num_other_cluster_vertices]; + const int number_of_vertices = static_cast(solution.size()); + + // Skip all the vertices that represent other clusters. + for (int vertex_id = num_other_cluster_vertices; + vertex_id < number_of_vertices; + ++vertex_id) { + if (solution[vertex_id] != first_vertex_partition) { + return false; + } + } + + return true; +} + // Recursively merge children whose number of std cells and macro // is below the current level thresholds. There are three cases: // 1) Children are closely connected. diff --git a/src/mpl2/src/clusterEngine.h b/src/mpl2/src/clusterEngine.h index 36059b83331..dbe21878065 100644 --- a/src/mpl2/src/clusterEngine.h +++ b/src/mpl2/src/clusterEngine.h @@ -194,6 +194,8 @@ class ClusteringEngine void createCluster(Cluster* parent); void updateSubTree(Cluster* parent); void breakLargeFlatCluster(Cluster* parent); + bool partitionerSolutionIsFullyUnbalanced(const std::vector& solution, + int num_other_cluster_vertices); void mergeChildrenBelowThresholds(std::vector& small_children); bool attemptMerge(Cluster* receiver, Cluster* incomer); void fetchMixedLeaves(Cluster* parent, From 2c666aa375b3e827dceb014d57ce8f42a2ed0d46 Mon Sep 17 00:00:00 2001 From: luis201420 Date: Thu, 19 Dec 2024 20:15:08 +0000 Subject: [PATCH 95/98] ant: Use mutex to protect variable updates Signed-off-by: luis201420 --- src/ant/src/AntennaChecker.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ant/src/AntennaChecker.cc b/src/ant/src/AntennaChecker.cc index 9f36785a97e..48ec7d117dd 100644 --- a/src/ant/src/AntennaChecker.cc +++ b/src/ant/src/AntennaChecker.cc @@ -1118,14 +1118,14 @@ int AntennaChecker::checkAntennas(odb::dbNet* net, } } omp_set_num_threads(num_threads); -#pragma omp parallel for schedule(dynamic) \ - reduction(+ : net_violation_count, pin_violation_count) +#pragma omp parallel for schedule(dynamic) for (int i = 0; i < nets_.size(); i++) { odb::dbNet* net = nets_[i]; Violations antenna_violations; int pin_viol_count = checkNet(net, verbose, true, nullptr, 0, antenna_violations); if (pin_viol_count > 0) { + std::lock_guard lock(map_mutex_); net_violation_count++; pin_violation_count += pin_viol_count; } From 5de801322a379ba33a955ef6c3fef15e0b2e0cb7 Mon Sep 17 00:00:00 2001 From: luis201420 Date: Thu, 19 Dec 2024 21:35:45 +0000 Subject: [PATCH 96/98] ant: Remove unnecessary mutex usage Signed-off-by: luis201420 --- src/ant/src/AntennaChecker.cc | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/src/ant/src/AntennaChecker.cc b/src/ant/src/AntennaChecker.cc index 48ec7d117dd..1e742570aac 100644 --- a/src/ant/src/AntennaChecker.cc +++ b/src/ant/src/AntennaChecker.cc @@ -100,13 +100,10 @@ void AntennaChecker::initAntennaRules() odb::dbTech* tech = db_->getTech(); // initialize nets_to_report_ with all nets to avoid issues with // multithreading - { - std::lock_guard lock(map_mutex_); - if (net_to_report_.empty()) { - for (odb::dbNet* net : block_->getNets()) { - if (!net->isSpecial()) { - net_to_report_[net]; - } + if (net_to_report_.empty()) { + for (odb::dbNet* net : block_->getNets()) { + if (!net->isSpecial()) { + net_to_report_[net]; } } } From bb06a3b6fca9adea2122319608749c3d5206bad7 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 19 Dec 2024 15:05:41 -0700 Subject: [PATCH 97/98] dst: add dl to link Signed-off-by: Peter Gadfort --- src/dst/test/cpp/CMakeLists.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/src/dst/test/cpp/CMakeLists.txt b/src/dst/test/cpp/CMakeLists.txt index 0beb1e33b16..fbfe2aeded2 100644 --- a/src/dst/test/cpp/CMakeLists.txt +++ b/src/dst/test/cpp/CMakeLists.txt @@ -1,5 +1,6 @@ set(TEST_LIBS dst + dl ${TCL_LIBRARY} ) From 799c6b34f070496a1a42b1ca4023da11332a9a89 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 19 Dec 2024 15:46:32 -0700 Subject: [PATCH 98/98] add dl to odbtcl-bin Signed-off-by: Peter Gadfort --- src/odb/src/swig/tcl/CMakeLists.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/src/odb/src/swig/tcl/CMakeLists.txt b/src/odb/src/swig/tcl/CMakeLists.txt index 65f0722ade8..313cdf62251 100644 --- a/src/odb/src/swig/tcl/CMakeLists.txt +++ b/src/odb/src/swig/tcl/CMakeLists.txt @@ -38,6 +38,7 @@ target_include_directories(odbtcl-bin target_link_libraries(odbtcl-bin PUBLIC odbtcl + dl ) set_target_properties(odbtcl-bin