diff --git a/etc/find_messages.py b/etc/find_messages.py
index ef5be4c11ee..2d8824a415b 100755
--- a/etc/find_messages.py
+++ b/etc/find_messages.py
@@ -96,7 +96,7 @@ def parse_args():
       \s+                              # white-space
       (?P<id>\d+)                      # id
       \s+                              # white-space
-      (?P<message>"(?:[^"\\]|\\.)+?")  # message
+      (?P<message>"(?:[^"]|\\.)+?")  # message
     """,
     re.VERBOSE | re.MULTILINE,
 )
diff --git a/src/Metrics.tcl b/src/Metrics.tcl
index 0de6e560287..d791afae590 100644
--- a/src/Metrics.tcl
+++ b/src/Metrics.tcl
@@ -239,6 +239,22 @@ proc report_design_area_metrics { args } {
     set stdcell_util -1.0
   }
 
+  set std_rows 0
+  set std_sites 0
+  set rows [dict create]
+  set sites [dict create]
+  foreach row [$block getRows] {
+    set site [$row getSite]
+
+    if { [$site getClass] == "NONE" || [$site getClass] == "CORE" } {
+      incr std_rows
+      set std_sites [expr { $std_sites + [$row getSiteCount] }]
+    }
+
+    dict incr rows [$site getName] 1
+    dict incr sites [$site getName] [$row getSiteCount]
+  }
+
   utl::metric_int "design__io" $num_ios
   utl::metric_float "design__die__area" $die_area
   utl::metric_float "design__core__area" $core_area
@@ -250,6 +266,16 @@ proc report_design_area_metrics { args } {
   utl::metric_float "design__instance__area__macros" $macro_area
   utl::metric_float "design__instance__utilization" $core_util
   utl::metric_float "design__instance__utilization__stdcell" $stdcell_util
+
+  utl::metric_int "design__rows" $std_rows
+  dict for {site_name count} $rows {
+    utl::metric_int "design__rows:$site_name" $count
+  }
+
+  utl::metric_int "design__sites" $std_sites
+  dict for {site_name count} $sites {
+    utl::metric_int "design__sites:$site_name" $count
+  }
 }
 
 # namespace
diff --git a/src/dpl/include/dpl/Opendp.h b/src/dpl/include/dpl/Opendp.h
index 2985d442a4a..fb636d96c50 100644
--- a/src/dpl/include/dpl/Opendp.h
+++ b/src/dpl/include/dpl/Opendp.h
@@ -41,8 +41,6 @@
 
 #include <boost/geometry.hpp>
 #include <boost/geometry/index/rtree.hpp>
-#include <boost/property_tree/json_parser.hpp>
-#include <boost/property_tree/ptree.hpp>
 #include <functional>
 #include <map>
 #include <memory>
@@ -186,9 +184,9 @@ class Opendp
   DbuPt pointOffMacro(const Cell& cell);
   void convertDbToCell(dbInst* db_inst, Cell& cell);
   // Return error count.
-  void processViolationsPtree(boost::property_tree::ptree& entry,
-                              const std::vector<Cell*>& failures,
-                              const std::string& violation_type = "") const;
+  void saveViolations(const std::vector<Cell*>& failures,
+                      odb::dbMarkerCategory* category,
+                      const std::string& violation_type = "") const;
   void importDb();
   void importClear();
   Rect getBbox(dbInst* inst);
@@ -288,14 +286,14 @@ class Opendp
       bool verbose,
       const std::function<void(Cell* cell)>& report_failure) const;
   void reportOverlapFailure(Cell* cell) const;
-  void writeJsonReport(const string& filename,
-                       const vector<Cell*>& placed_failures,
-                       const vector<Cell*>& in_rows_failures,
-                       const vector<Cell*>& overlap_failures,
-                       const vector<Cell*>& one_site_gap_failures,
-                       const vector<Cell*>& site_align_failures,
-                       const vector<Cell*>& region_placement_failures,
-                       const vector<Cell*>& placement_failures);
+  void saveFailures(const vector<Cell*>& placed_failures,
+                    const vector<Cell*>& in_rows_failures,
+                    const vector<Cell*>& overlap_failures,
+                    const vector<Cell*>& one_site_gap_failures,
+                    const vector<Cell*>& site_align_failures,
+                    const vector<Cell*>& region_placement_failures,
+                    const vector<Cell*>& placement_failures);
+  void writeJsonReport(const string& filename);
 
   void rectDist(const Cell* cell,
                 const Rect& rect,
diff --git a/src/dpl/src/CheckPlacement.cpp b/src/dpl/src/CheckPlacement.cpp
index 700ec80687f..83a26fb8907 100644
--- a/src/dpl/src/CheckPlacement.cpp
+++ b/src/dpl/src/CheckPlacement.cpp
@@ -32,8 +32,6 @@
 // POSSIBILITY OF SUCH DAMAGE.
 ///////////////////////////////////////////////////////////////////////////////
 
-#include <boost/property_tree/json_parser.hpp>
-#include <boost/property_tree/ptree.hpp>
 #include <cmath>
 #include <fstream>
 #include <limits>
@@ -106,15 +104,15 @@ void Opendp::checkPlacement(const bool verbose,
       }
     }
   }
+  saveFailures(placed_failures,
+               in_rows_failures,
+               overlap_failures,
+               one_site_gap_failures,
+               site_align_failures,
+               region_placement_failures,
+               {});
   if (!report_file_name.empty()) {
-    writeJsonReport(report_file_name,
-                    placed_failures,
-                    in_rows_failures,
-                    overlap_failures,
-                    one_site_gap_failures,
-                    site_align_failures,
-                    region_placement_failures,
-                    {});
+    writeJsonReport(report_file_name);
   }
   reportFailures(placed_failures, 3, "Placed", verbose);
   reportFailures(in_rows_failures, 4, "Placed in rows", verbose);
@@ -139,21 +137,20 @@ void Opendp::checkPlacement(const bool verbose,
   }
 }
 
-void Opendp::processViolationsPtree(boost::property_tree::ptree& entry,
-                                    const std::vector<Cell*>& failures,
-                                    const string& violation_type) const
+void Opendp::saveViolations(const std::vector<Cell*>& failures,
+                            odb::dbMarkerCategory* category,
+                            const string& violation_type) const
 {
-  using boost::property_tree::ptree;
-  ptree violations;
-  const double dbUnits
-      = block_->getDataBase()->getTech()->getDbUnitsPerMicron();
   const Rect core = grid_->getCore();
   for (auto failure : failures) {
-    ptree violation, shapes, source, sources, shape;
-    double xMin = (failure->x_ + core.xMin()).v / dbUnits;
-    double yMin = (failure->y_ + core.yMin()).v / dbUnits;
-    double xMax = (failure->x_ + failure->width_ + core.xMin()).v / dbUnits;
-    double yMax = (failure->y_ + failure->height_ + core.yMin()).v / dbUnits;
+    odb::dbMarker* marker = odb::dbMarker::create(category);
+    if (!marker) {
+      break;
+    }
+    int xMin = (failure->x_ + core.xMin()).v;
+    int yMin = (failure->y_ + core.yMin()).v;
+    int xMax = (failure->x_ + failure->width_ + core.xMin()).v;
+    int yMax = (failure->y_ + failure->height_ + core.yMin()).v;
 
     if (violation_type == "overlap") {
       const Cell* o_cell = checkOverlap(*failure);
@@ -175,112 +172,87 @@ void Opendp::processViolationsPtree(boost::property_tree::ptree& entry,
       odb::Rect overlap_rect;
       o_rect.intersection(f_rect, overlap_rect);
 
-      xMin = (overlap_rect.xMin() + core.xMin()) / dbUnits;
-      yMin = (overlap_rect.yMin() + core.yMin()) / dbUnits;
-      xMax = (overlap_rect.xMax() + core.xMin()) / dbUnits;
-      yMax = (overlap_rect.yMax() + core.yMin()) / dbUnits;
+      xMin = overlap_rect.xMin() + core.xMin();
+      yMin = overlap_rect.yMin() + core.yMin();
+      xMax = overlap_rect.xMax() + core.xMin();
+      yMax = overlap_rect.yMax() + core.yMin();
 
-      ptree overlap_source;
-      overlap_source.put("type", "inst");
-      overlap_source.put("name", o_cell->name());
-      sources.push_back(std::make_pair("", overlap_source));
+      marker->addSource(o_cell->db_inst_);
     }
-    shape.put("x", xMin);
-    shape.put("y", yMin);
-    shapes.push_back(std::make_pair("", shape));
-    shape.clear();
-    shape.put("x", xMax);
-    shape.put("y", yMax);
-    shapes.push_back(std::make_pair("", shape));
-
-    source.put("type", "inst");
-    source.put("name", failure->name());
-    sources.push_back(std::make_pair("", source));
-
-    violation.put("type", "box");
-    violation.add_child("shape", shapes);
-    violation.add_child("sources", sources);
-
-    violations.push_back(std::make_pair("", violation));
+    marker->addShape(Rect{xMin, yMin, xMax, yMax});
+    marker->addSource(failure->db_inst_);
   }
-  entry.add_child("violations", violations);
 }
 
-void Opendp::writeJsonReport(const string& filename,
-                             const vector<Cell*>& placed_failures,
-                             const vector<Cell*>& in_rows_failures,
-                             const vector<Cell*>& overlap_failures,
-                             const vector<Cell*>& one_site_gap_failures,
-                             const vector<Cell*>& site_align_failures,
-                             const vector<Cell*>& region_placement_failures,
-                             const vector<Cell*>& placement_failures_)
+void Opendp::saveFailures(const vector<Cell*>& placed_failures,
+                          const vector<Cell*>& in_rows_failures,
+                          const vector<Cell*>& overlap_failures,
+                          const vector<Cell*>& one_site_gap_failures,
+                          const vector<Cell*>& site_align_failures,
+                          const vector<Cell*>& region_placement_failures,
+                          const vector<Cell*>& placement_failures)
 {
-  std::ofstream json_file(filename);
-  if (!json_file.is_open()) {
-    logger_->error(DPL, 40, "Failed to open file {} for writing.", filename);
+  if (placed_failures.empty() && in_rows_failures.empty()
+      && overlap_failures.empty() && one_site_gap_failures.empty()
+      && site_align_failures.empty() && region_placement_failures.empty()
+      && placement_failures.empty()) {
+    return;
   }
-  try {
-    using boost::property_tree::ptree;
-    ptree root, drcArray;
-
-    if (!placed_failures.empty()) {
-      ptree entry;
-      entry.put("name", "Placement_failures");
-      entry.put("description", "Cells that were not placed.");
-      processViolationsPtree(entry, placed_failures);
-      drcArray.push_back(std::make_pair("", entry));
-    }
-    if (!in_rows_failures.empty()) {
-      ptree entry;
-      entry.put("name", "In_rows_failures");
-      entry.put("description",
-                "Cells that were not assigned to rows in the grid.");
-      processViolationsPtree(entry, in_rows_failures);
-      drcArray.push_back(std::make_pair("", entry));
-    }
-    if (!overlap_failures.empty()) {
-      ptree entry;
-      entry.put("name", "Overlap_failures");
-      entry.put("description", "Cells that are overlapping with other cells.");
-      processViolationsPtree(entry, overlap_failures, "overlap");
-      drcArray.push_back(std::make_pair("", entry));
-    }
-    if (!one_site_gap_failures.empty()) {
-      ptree entry;
-      entry.put("name", "One_site_gap_failures");
-      entry.put("description",
-                "Cells that violate the one site gap spacing rules.");
-      processViolationsPtree(entry, one_site_gap_failures);
-      drcArray.push_back(std::make_pair("", entry));
-    }
-    if (!site_align_failures.empty()) {
-      ptree entry;
-      entry.put("name", "Site_alignment_failures");
-      entry.put("description",
-                "Cells that are not aligned with placement sites.");
-      processViolationsPtree(entry, site_align_failures);
-      drcArray.push_back(std::make_pair("", entry));
-    }
-    if (!region_placement_failures.empty()) {
-      ptree entry;
-      entry.put("name", "Region_placement_failures");
-      entry.put("description",
-                "Cells that violate the region placement constraints.");
-      processViolationsPtree(entry, region_placement_failures);
-      drcArray.push_back(std::make_pair("", entry));
-    }
-    if (!placement_failures_.empty()) {
-      ptree entry;
-      entry.put("name", "Placement_failures");
-      entry.put("description", "Cells that DPL failed to place.");
-      processViolationsPtree(entry, placement_failures_);
-      drcArray.push_back(std::make_pair("", entry));
-    }
-    root.add_child("DRC", drcArray);
-    boost::property_tree::write_json(json_file, root);
-  } catch (std::exception& ex) {
-    logger_->error(
-        DPL, 45, "Failed to write JSON report. Exception: {}", ex.what());
+
+  auto* tool_category = odb::dbMarkerCategory::createOrReplace(block_, "DPL");
+  if (!placed_failures.empty()) {
+    auto category = odb::dbMarkerCategory::createOrReplace(
+        tool_category, "Placement failures");
+    category->setDescription("Cells that were not placed.");
+    saveViolations(placed_failures, category);
+  }
+  if (!in_rows_failures.empty()) {
+    auto category = odb::dbMarkerCategory::createOrReplace(tool_category,
+                                                           "In_rows_failures");
+    category->setDescription(
+        "Cells that were not assigned to rows in the grid.");
+    saveViolations(in_rows_failures, category);
+  }
+  if (!overlap_failures.empty()) {
+    auto category = odb::dbMarkerCategory::createOrReplace(tool_category,
+                                                           "Overlap_failures");
+    category->setDescription("Cells that are overlapping with other cells.");
+    saveViolations(overlap_failures, category, "overlap");
+  }
+  if (!one_site_gap_failures.empty()) {
+    auto category = odb::dbMarkerCategory::createOrReplace(
+        tool_category, "One_site_gap_failures");
+    category->setDescription(
+        "Cells that violate the one site gap spacing rules.");
+    saveViolations(one_site_gap_failures, category);
+  }
+  if (!site_align_failures.empty()) {
+    auto category = odb::dbMarkerCategory::createOrReplace(
+        tool_category, "Site_alignment_failures");
+    category->setDescription(
+        "Cells that are not aligned with placement sites.");
+    saveViolations(site_align_failures, category);
+  }
+  if (!region_placement_failures.empty()) {
+    auto category = odb::dbMarkerCategory::createOrReplace(
+        tool_category, "Region_placement_failures");
+    category->setDescription(
+        "Cells that violate the region placement constraints.");
+    saveViolations(region_placement_failures, category);
+  }
+  if (!placement_failures.empty()) {
+    auto category = odb::dbMarkerCategory::createOrReplace(
+        tool_category, "Placement_failures");
+    category->setDescription("Cells that DPL failed to place.");
+    saveViolations(placement_failures, category);
+  }
+}
+
+void Opendp::writeJsonReport(const string& filename)
+{
+  auto* tool_category = block_->findMarkerCategory("DPL");
+  if (tool_category) {
+    tool_category->writeJSON(filename);
   }
 }
 
diff --git a/src/dpl/src/Opendp.cpp b/src/dpl/src/Opendp.cpp
index 79465d927f3..02fb45b4079 100644
--- a/src/dpl/src/Opendp.cpp
+++ b/src/dpl/src/Opendp.cpp
@@ -158,9 +158,9 @@ void Opendp::detailedPlacement(const int max_displacement_x,
       logger_->info(DPL, 35, " {}", cell->name());
     }
 
+    saveFailures({}, {}, {}, {}, {}, {}, placement_failures_);
     if (!report_file_name.empty()) {
-      writeJsonReport(
-          report_file_name, {}, {}, {}, {}, {}, {}, placement_failures_);
+      writeJsonReport(report_file_name);
     }
     logger_->error(DPL, 36, "Detailed placement failed.");
   }
diff --git a/src/dpl/test/report_failures.jsonok b/src/dpl/test/report_failures.jsonok
index 6d7b31b8dc1..79d8dd2563b 100644
--- a/src/dpl/test/report_failures.jsonok
+++ b/src/dpl/test/report_failures.jsonok
@@ -1,67 +1,94 @@
 {
-    "DRC": [
-        {
-            "name": "Placement_failures",
-            "description": "Cells that DPL failed to place.",
-            "violations": [
-                {
-                    "type": "box",
-                    "shape": [
-                        {
-                            "x": "14",
-                            "y": "14"
-                        },
-                        {
-                            "x": "14.57",
-                            "y": "15.4"
-                        }
-                    ],
-                    "sources": [
-                        {
-                            "type": "inst",
-                            "name": "f2\/_285_"
-                        }
-                    ]
-                },
-                {
-                    "type": "box",
-                    "shape": [
-                        {
-                            "x": "14",
-                            "y": "14"
-                        },
-                        {
-                            "x": "14.57",
-                            "y": "15.4"
-                        }
-                    ],
-                    "sources": [
-                        {
-                            "type": "inst",
-                            "name": "f2\/_289_"
-                        }
-                    ]
-                },
-                {
-                    "type": "box",
-                    "shape": [
-                        {
-                            "x": "14",
-                            "y": "14"
-                        },
-                        {
-                            "x": "14.380000000000001",
-                            "y": "15.4"
-                        }
-                    ],
-                    "sources": [
-                        {
-                            "type": "inst",
-                            "name": "f2\/_293_"
-                        }
-                    ]
-                }
-            ]
+    "DPL": {
+        "description": "",
+        "source": "",
+        "max_markers": "10000",
+        "category": {
+            "Placement_failures": {
+                "description": "Cells that DPL failed to place.",
+                "source": "",
+                "max_markers": "10000",
+                "violations": [
+                    {
+                        "visited": "false",
+                        "visible": "true",
+                        "waived": "false",
+                        "shape": [
+                            {
+                                "type": "box",
+                                "points": [
+                                    {
+                                        "x": "14.0000",
+                                        "y": "14.0000"
+                                    },
+                                    {
+                                        "x": "14.5700",
+                                        "y": "15.4000"
+                                    }
+                                ]
+                            }
+                        ],
+                        "sources": [
+                            {
+                                "type": "inst",
+                                "name": "f2\/_285_"
+                            }
+                        ]
+                    },
+                    {
+                        "visited": "false",
+                        "visible": "true",
+                        "waived": "false",
+                        "shape": [
+                            {
+                                "type": "box",
+                                "points": [
+                                    {
+                                        "x": "14.0000",
+                                        "y": "14.0000"
+                                    },
+                                    {
+                                        "x": "14.5700",
+                                        "y": "15.4000"
+                                    }
+                                ]
+                            }
+                        ],
+                        "sources": [
+                            {
+                                "type": "inst",
+                                "name": "f2\/_289_"
+                            }
+                        ]
+                    },
+                    {
+                        "visited": "false",
+                        "visible": "true",
+                        "waived": "false",
+                        "shape": [
+                            {
+                                "type": "box",
+                                "points": [
+                                    {
+                                        "x": "14.0000",
+                                        "y": "14.0000"
+                                    },
+                                    {
+                                        "x": "14.3800",
+                                        "y": "15.4000"
+                                    }
+                                ]
+                            }
+                        ],
+                        "sources": [
+                            {
+                                "type": "inst",
+                                "name": "f2\/_293_"
+                            }
+                        ]
+                    }
+                ]
+            }
         }
-    ]
+    }
 }
diff --git a/src/drt/src/global.cpp b/src/drt/src/global.cpp
index df0a7ad8f41..dfe9828a529 100644
--- a/src/drt/src/global.cpp
+++ b/src/drt/src/global.cpp
@@ -61,7 +61,7 @@ std::string BOTTOM_ROUTING_LAYER_NAME;
 std::string TOP_ROUTING_LAYER_NAME;
 int BOTTOM_ROUTING_LAYER = 2;
 int TOP_ROUTING_LAYER = std::numeric_limits<frLayerNum>::max();
-bool ALLOW_PIN_AS_FEEDTHROUGH = false;
+bool ALLOW_PIN_AS_FEEDTHROUGH = true;
 bool USENONPREFTRACKS = true;
 bool USEMINSPACING_OBS = true;
 bool ENABLE_BOUNDARY_MAR_FIX = true;
diff --git a/src/drt/test/ndr_vias1.defok b/src/drt/test/ndr_vias1.defok
index 10cb737e38d..cbf801c8e2d 100644
--- a/src/drt/test/ndr_vias1.defok
+++ b/src/drt/test/ndr_vias1.defok
@@ -228,11 +228,9 @@ NETS 8 ;
       NEW met1 TAPER ( 130870 172890 ) ( 132710 * )
       NEW met1 ( 132710 172890 210 ) ( 152030 * 210 )
       NEW met1 ( 152030 169830 210 ) ( 167900 * 210 )
-      NEW met2 ( 152950 158700 210 ) ( * 169830 210 )
       NEW met1 ( 152950 118150 210 ) ( * 118490 210 )
       NEW met2 ( 152030 118150 210 ) ( * 150450 210 )
-      NEW met2 ( 152030 158700 210 ) ( 152950 * 210 )
-      NEW met2 ( 152030 150450 210 ) ( * 158700 210 )
+      NEW met2 ( 152950 151470 210 ) ( * 169830 210 )
       NEW met1 ( 152950 118490 210 ) ( 167900 * 210 )
       NEW met2 ( 119370 118150 210 ) ( * 118490 210 )
       NEW met2 ( 118450 118490 210 ) ( 119370 * 210 )
@@ -248,6 +246,8 @@ NETS 8 ;
       NEW li1 TAPER ( 152030 150450 ) L1M1_PR_R
       NEW met1 TAPER ( 152030 150450 ) M1M2_PR_R
       NEW met1 ( 152030 118150 ) M1M2_PR_R
+      NEW li1 TAPER ( 152950 151470 ) L1M1_PR_R
+      NEW met1 TAPER ( 152950 151470 ) M1M2_PR_R
       NEW met1 ( 119370 118150 ) M1M2_PR_R
       NEW met1 ( 118450 118490 ) M1M2_PR_R
       NEW li1 TAPER ( 116610 118490 ) L1M1_PR_R ;
@@ -266,9 +266,9 @@ NETS 8 ;
       NEW met2 ( 117530 115430 210 ) ( * 117810 210 )
       NEW met1 ( 117530 115430 210 ) ( 125350 * 210 )
       NEW met2 ( 111090 118150 210 ) ( * 120870 210 )
-      NEW met1 ( 111090 118150 210 ) ( 112010 * 210 )
-      NEW met1 ( 112010 117810 210 ) ( * 118150 210 )
-      NEW met1 ( 112010 117810 210 ) ( 115460 * 210 )
+      NEW met1 ( 111090 118150 210 ) ( 112470 * 210 )
+      NEW met1 ( 112470 117810 210 ) ( * 118150 210 )
+      NEW met1 ( 112470 117810 210 ) ( 115460 * 210 )
       NEW met1 TAPER ( 115460 117810 ) ( 117530 * )
       NEW met2 ( 111090 120870 210 ) ( * 134810 210 )
       NEW met1 ( 96600 118150 210 ) ( * 118490 210 )
@@ -428,10 +428,9 @@ NETS 8 ;
       NEW met1 TAPER ( 171580 175610 ) ( 173190 * )
       NEW met1 TAPER ( 169970 170510 ) ( 170890 * )
       NEW met2 ( 169970 170510 210 ) ( * 175610 210 )
-      NEW met2 ( 175030 164390 210 ) ( * 170510 210 )
-      NEW met1 TAPER ( 170890 170510 ) ( 173135 * )
-      NEW met1 ( 173135 170510 210 ) ( 175030 * 210 )
-      NEW met1 ( 175030 164390 210 ) ( 192050 * 210 )
+      NEW met2 ( 172730 164390 210 ) ( * 169490 210 )
+      NEW met1 TAPER ( 171350 169490 ) ( 172730 * )
+      NEW met1 ( 172730 164390 210 ) ( 192050 * 210 )
       NEW met2 ( 192050 153850 210 ) ( * 164390 210 )
       NEW met1 ( 153870 175610 210 ) ( * 176460 210 )
       NEW met1 TAPER ( 153870 176460 ) ( * 177990 )
@@ -455,8 +454,9 @@ NETS 8 ;
       NEW li1 TAPER ( 173190 175610 ) L1M1_PR_R
       NEW li1 TAPER ( 170890 170510 ) L1M1_PR_R
       NEW met1 TAPER ( 169970 170510 ) M1M2_PR_R
-      NEW met1 ( 175030 164390 ) M1M2_PR_R
-      NEW met1 ( 175030 170510 ) M1M2_PR_R
+      NEW met1 ( 172730 164390 ) M1M2_PR_R
+      NEW met1 TAPER ( 172730 169490 ) M1M2_PR_R
+      NEW li1 TAPER ( 171350 169490 ) L1M1_PR_R
       NEW li1 TAPER ( 192050 153850 ) L1M1_PR_R
       NEW met1 TAPER ( 192050 153850 ) M1M2_PR_R
       NEW li1 TAPER ( 154790 177990 ) L1M1_PR_R
diff --git a/src/drt/test/ndr_vias2.defok b/src/drt/test/ndr_vias2.defok
index cb400bbb4cd..0f9685c403f 100644
--- a/src/drt/test/ndr_vias2.defok
+++ b/src/drt/test/ndr_vias2.defok
@@ -352,7 +352,7 @@ NETS 8 ;
       NEW met2 ( 199410 131100 210 ) ( 200330 * 210 )
       NEW met2 ( 199410 131100 210 ) ( * 137190 210 )
       NEW met2 ( 171350 118830 210 ) ( * 124100 210 )
-      NEW met3 ( 171350 124100 450 ) ( 178940 * 450 )
+      NEW met3 ( 171350 124100 450 ) ( 177100 * 450 )
       NEW met2 ( 156170 124780 210 ) ( * 129370 210 )
       NEW met3 ( 156170 124780 450 ) ( 158700 * 450 )
       NEW met3 ( 158700 124100 450 ) ( * 124780 450 )
@@ -360,17 +360,19 @@ NETS 8 ;
       NEW met3 ( 156170 129540 450 ) ( 157780 * 450 )
       NEW met2 ( 156170 129370 210 ) ( * 129540 210 )
       NEW met2 ( 178710 91290 210 ) ( * 91460 210 )
-      NEW met3 ( 178710 91460 450 ) ( 178940 * 450 )
-      NEW met4 ( 178940 91460 450 ) ( * 124100 450 )
-      NEW met2 ( 164450 88230 210 ) ( * 91290 210 )
-      NEW met1 ( 164450 91290 210 ) ( 177100 * 210 )
-      NEW met1 TAPER ( 177100 91290 ) ( 178710 * )
-      NEW met2 ( 158010 96900 210 ) ( * 102170 210 )
-      NEW met2 ( 158010 96900 210 ) ( 158930 * 210 )
-      NEW met2 ( 158930 88230 210 ) ( * 96900 210 )
-      NEW met1 ( 158930 88230 210 ) ( 162610 * 210 )
-      NEW met1 TAPER ( 162610 88230 ) ( 164450 * )
-      NEW met5 ( 178940 124100 2400 ) ( 200100 * 2400 )
+      NEW met3 ( 177100 91460 450 ) ( 178710 * 450 )
+      NEW met4 ( 177100 91460 450 ) ( * 124100 450 )
+      NEW met2 ( 164450 88230 210 ) ( * 89420 210 )
+      NEW met3 ( 164450 89420 450 ) ( 172500 * 450 )
+      NEW met3 ( 172500 89420 450 ) ( * 90100 450 )
+      NEW met3 ( 172500 90100 450 ) ( 177100 * 450 )
+      NEW met3 ( 177100 90100 450 ) ( * 91460 450 )
+      NEW met1 TAPER ( 157090 101830 ) ( 158010 * )
+      NEW met2 ( 157090 101660 210 ) ( * 101830 210 )
+      NEW met3 ( 157090 101660 450 ) ( 158700 * 450 )
+      NEW met4 ( 158700 89420 450 ) ( * 101660 450 )
+      NEW met3 ( 158700 89420 450 ) ( 164450 * 450 )
+      NEW met5 ( 177100 124100 2400 ) ( 200100 * 2400 )
       NEW met3 ( 152950 147220 450 ) ( 157780 * 450 )
       NEW met2 ( 152950 147220 210 ) ( * 148070 210 )
       NEW met4 ( 157780 129540 450 ) ( * 147220 450 )
@@ -390,8 +392,8 @@ NETS 8 ;
       NEW li1 TAPER ( 171350 118830 ) L1M1_PR_R
       NEW met1 TAPER ( 171350 118830 ) M1M2_PR_R
       NEW met2 ( 171350 124100 ) M2M3_PR_R
-      NEW met3 ( 178940 124100 ) M3M4_PR_R
-      NEW met4 ( 178940 124100 ) M4M5_PR_R
+      NEW met3 ( 177100 124100 ) M3M4_PR_R
+      NEW met4 ( 177100 124100 ) M4M5_PR_R
       NEW li1 TAPER ( 156170 129370 ) L1M1_PR_R
       NEW met1 TAPER ( 156170 129370 ) M1M2_PR_R
       NEW met2 ( 156170 124780 ) M2M3_PR_R
@@ -400,19 +402,20 @@ NETS 8 ;
       NEW li1 TAPER ( 178710 91290 ) L1M1_PR_R
       NEW met1 TAPER ( 178710 91290 ) M1M2_PR_R
       NEW met2 ( 178710 91460 ) M2M3_PR_R
-      NEW met3 ( 178940 91460 ) M3M4_PR_R
+      NEW met3 ( 177100 91460 ) M3M4_PR_R
       NEW li1 TAPER ( 164450 88230 ) L1M1_PR_R
       NEW met1 TAPER ( 164450 88230 ) M1M2_PR_R
-      NEW met1 ( 164450 91290 ) M1M2_PR_R
-      NEW li1 TAPER ( 158010 102170 ) L1M1_PR_R
-      NEW met1 TAPER ( 158010 102170 ) M1M2_PR_R
-      NEW met1 ( 158930 88230 ) M1M2_PR_R
+      NEW met2 ( 164450 89420 ) M2M3_PR_R
+      NEW li1 TAPER ( 158010 101830 ) L1M1_PR_R
+      NEW met1 TAPER ( 157090 101830 ) M1M2_PR_R
+      NEW met2 ( 157090 101660 ) M2M3_PR_R
+      NEW met3 ( 158700 101660 ) M3M4_PR_R
+      NEW met3 ( 158700 89420 ) M3M4_PR_R
       NEW met3 ( 157780 147220 ) M3M4_PR_R
       NEW met2 ( 152950 147220 ) M2M3_PR_R
       NEW li1 TAPER ( 152950 148070 ) L1M1_PR_R
       NEW met1 TAPER ( 152950 148070 ) M1M2_PR_R
-      NEW met3 TAPER ( 200330 126140 ) RECT ( 0 -150 390 150 ) 
-      NEW met3 TAPER ( 178710 91460 ) RECT ( -390 -150 0 150 )  ;
+      NEW met3 TAPER ( 200330 126140 ) RECT ( 0 -150 390 150 )  ;
     - clknet_2_2__leaf_clk ( _411_ CLK ) ( _413_ CLK ) ( _415_ CLK ) ( _416_ CLK ) ( _417_ CLK ) ( _421_ CLK ) ( _430_ CLK )
       ( _431_ CLK ) ( _433_ CLK ) ( _437_ CLK ) ( clkbuf_2_2__f_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S
       + ROUTED met2 ( 125810 183770 210 ) ( * 183940 210 )
diff --git a/src/gui/src/gui.cpp b/src/gui/src/gui.cpp
index b84a7fcfdd2..8c655422c67 100644
--- a/src/gui/src/gui.cpp
+++ b/src/gui/src/gui.cpp
@@ -96,7 +96,7 @@ static void message_handler(QtMsgType type,
   }
   switch (type) {
     case QtDebugMsg:
-      logger->debug(utl::GUI, "qt", print_msg);
+      debugPrint(logger, utl::GUI, "qt", 1, print_msg);
       break;
     case QtInfoMsg:
       logger->info(utl::GUI, 75, print_msg);
diff --git a/src/gui/src/inspector.cpp b/src/gui/src/inspector.cpp
index 82dbda1062f..de6e0cf375e 100644
--- a/src/gui/src/inspector.cpp
+++ b/src/gui/src/inspector.cpp
@@ -34,6 +34,7 @@
 
 #include <QApplication>
 #include <QComboBox>
+#include <QDebug>
 #include <QHeaderView>
 #include <QLineEdit>
 #include <QPushButton>
@@ -812,6 +813,12 @@ void Inspector::inspect(const Selected& object)
     navigation_history_.clear();
   }
 
+  if (object) {
+    qDebug() << "Inspector change selection to"
+             << QString::fromStdString(object.getName());
+  } else {
+    qDebug() << "Inspector change selection to nothing";
+  }
   selection_ = object;
   emit selection(object);
 
@@ -1141,7 +1148,8 @@ void Inspector::navigateBack()
     }
   }
 
-  emit inspect(next);
+  qDebug() << "Navigate to" << QString::fromStdString(next.getName());
+  emit selected(next);
 }
 
 ////////////
diff --git a/src/pdn/src/pdn.tcl b/src/pdn/src/pdn.tcl
index 906460fc435..0274f6fed6f 100644
--- a/src/pdn/src/pdn.tcl
+++ b/src/pdn/src/pdn.tcl
@@ -156,7 +156,7 @@ proc set_voltage_domain { args } {
     } else {
       set signal_type [$switched_power getSigType]
       if { $signal_type != "POWER" } {
-        utl::error PDN 199 "Net $switched_power_net_name already exists in the design,\
+        utl::error PDN 212 "Net $switched_power_net_name already exists in the design,\
           but is of signal type ${signal_type}."
       }
     }
diff --git a/src/ppl/include/ppl/IOPlacer.h b/src/ppl/include/ppl/IOPlacer.h
index b7a6ac52ec1..d51f33ce094 100644
--- a/src/ppl/include/ppl/IOPlacer.h
+++ b/src/ppl/include/ppl/IOPlacer.h
@@ -286,6 +286,9 @@ class IOPlacer
   odb::dbBlock* getBlock() const;
   odb::dbTech* getTech() const;
   std::string getEdgeString(Edge edge);
+  std::string getDirectionString(Direction direction);
+  template <class PinSetOrList>
+  std::string getPinSetOrListString(const PinSetOrList& group);
 
   std::unique_ptr<Netlist> netlist_;
   std::unique_ptr<Core> core_;
diff --git a/src/ppl/src/IOPlacer.cpp b/src/ppl/src/IOPlacer.cpp
index 576aff13bd3..895b7fedc3a 100644
--- a/src/ppl/src/IOPlacer.cpp
+++ b/src/ppl/src/IOPlacer.cpp
@@ -123,6 +123,24 @@ std::string IOPlacer::getEdgeString(Edge edge)
   return edge_str;
 }
 
+std::string IOPlacer::getDirectionString(Direction direction)
+{
+  std::string direction_str;
+  if (direction == Direction::input) {
+    direction_str = "INPUT";
+  } else if (direction == Direction::output) {
+    direction_str = "OUTPUT";
+  } else if (direction == Direction::inout) {
+    direction_str = "INOUT";
+  } else if (direction == Direction::feedthru) {
+    direction_str = "FEEDTHRU";
+  } else if (direction == Direction::invalid) {
+    direction_str = "INVALID";
+  }
+
+  return direction_str;
+}
+
 void IOPlacer::initNetlistAndCore(const std::set<int>& hor_layer_idx,
                                   const std::set<int>& ver_layer_idx)
 {
@@ -1620,24 +1638,14 @@ void IOPlacer::addNamesConstraint(PinSet* pins, Edge edge, int begin, int end)
 {
   Interval interval(edge, begin, end);
   bool inserted = false;
-  std::string pin_names;
-  int pin_cnt = 0;
-  for (odb::dbBTerm* pin : *pins) {
-    pin_names += pin->getName() + " ";
-    pin_cnt++;
-    if (pin_cnt >= pins_per_report_
-        && !logger_->debugCheck(utl::PPL, "pin_groups", 1)) {
-      pin_names += "... ";
-      break;
-    }
-  }
+  std::string pin_names = getPinSetOrListString(*pins);
 
   if (logger_->debugCheck(utl::PPL, "pin_groups", 1)) {
     debugPrint(logger_,
                utl::PPL,
                "pin_groups",
                1,
-               "Restrict pins [ {}] to region {:.2f}u-{:.2f}u at the {} edge.",
+               "Restrict pins [ {} ] to region {:.2f}u-{:.2f}u at the {} edge.",
                pin_names,
                getBlock()->dbuToMicrons(begin),
                getBlock()->dbuToMicrons(end),
@@ -1646,7 +1654,7 @@ void IOPlacer::addNamesConstraint(PinSet* pins, Edge edge, int begin, int end)
     logger_->info(
         utl::PPL,
         48,
-        "Restrict pins [ {}] to region {:.2f}u-{:.2f}u at the {} edge.",
+        "Restrict pins [ {} ] to region {:.2f}u-{:.2f}u at the {} edge.",
         pin_names,
         getBlock()->dbuToMicrons(begin),
         getBlock()->dbuToMicrons(end),
@@ -1672,6 +1680,14 @@ void IOPlacer::addDirectionConstraint(Direction direction,
                                       int end)
 {
   Interval interval(edge, begin, end);
+  logger_->info(utl::PPL,
+                67,
+                "Restrict {} pins to region {}u-{}u, in the {} edge.",
+                getDirectionString(direction),
+                getBlock()->dbuToMicrons(begin),
+                getBlock()->dbuToMicrons(end),
+                getEdgeString(edge));
+
   Constraint constraint(PinSet(), direction, interval);
   constraints_.push_back(constraint);
 }
@@ -1679,6 +1695,19 @@ void IOPlacer::addDirectionConstraint(Direction direction,
 void IOPlacer::addTopLayerConstraint(PinSet* pins, const odb::Rect& region)
 {
   Constraint constraint(*pins, Direction::invalid, region);
+  std::string pin_names = getPinSetOrListString(*pins);
+
+  logger_->info(utl::PPL,
+                60,
+                "Restrict pins [ {} ] to region ({:.2f}u, {:.2f}u)-({:.2f}u, "
+                "{:.2f}u) at routing layer {}.",
+                pin_names,
+                getBlock()->dbuToMicrons(region.xMin()),
+                getBlock()->dbuToMicrons(region.yMin()),
+                getBlock()->dbuToMicrons(region.xMax()),
+                getBlock()->dbuToMicrons(region.yMax()),
+                getTopLayer()->getConstName());
+
   constraints_.push_back(constraint);
   for (odb::dbBTerm* bterm : *pins) {
     if (!bterm->getFirstPinPlacementStatus().isFixed()) {
@@ -1975,25 +2004,33 @@ Direction IOPlacer::getDirection(const std::string& direction)
   return Direction::feedthru;
 }
 
-void IOPlacer::addPinGroup(PinList* group, bool order)
+/* static */
+template <class PinSetOrList>
+std::string IOPlacer::getPinSetOrListString(const PinSetOrList& group)
 {
   std::string pin_names;
   int pin_cnt = 0;
-  for (odb::dbBTerm* pin : *group) {
-    pin_names += pin->getName() + " ";
+  for (odb::dbBTerm* pin : group) {
+    pin_names += (pin_cnt ? " " : "") + pin->getName();
     pin_cnt++;
     if (pin_cnt >= pins_per_report_
         && !logger_->debugCheck(utl::PPL, "pin_groups", 1)) {
-      pin_names += "... ";
+      pin_names += " ...";
       break;
     }
   }
+  return pin_names;
+}
+
+void IOPlacer::addPinGroup(PinList* group, bool order)
+{
+  std::string pin_names = getPinSetOrListString(*group);
 
   if (logger_->debugCheck(utl::PPL, "pin_groups", 1)) {
     debugPrint(
-        logger_, utl::PPL, "pin_groups", 1, "Pin group: [ {}]", pin_names);
+        logger_, utl::PPL, "pin_groups", 1, "Pin group: [ {} ]", pin_names);
   } else {
-    logger_->info(utl::PPL, 44, "Pin group: [ {}]", pin_names);
+    logger_->info(utl::PPL, 44, "Pin group: [ {} ]", pin_names);
   }
   pin_groups_.push_back({*group, order});
 }
diff --git a/src/ppl/src/IOPlacer.tcl b/src/ppl/src/IOPlacer.tcl
index 62f04de8b94..8c181f6c619 100644
--- a/src/ppl/src/IOPlacer.tcl
+++ b/src/ppl/src/IOPlacer.tcl
@@ -172,9 +172,6 @@ proc set_io_pin_constraint { args } {
       if { [info exists keys(-direction)] } {
         set direction $keys(-direction)
         set dir [ppl::parse_direction "set_io_pin_constraint" $direction]
-        utl::info PPL 49 "Restrict $direction pins to region\
-          [ord::dbu_to_microns $begin]u-[ord::dbu_to_microns $end]u,\
-          in the $edge edge."
         ppl::add_direction_constraint $dir $edge_ $begin $end
       }
 
@@ -622,7 +619,6 @@ proc place_pins { args } {
   if { [llength $pin_groups] != 0 } {
     set group_idx 0
     foreach group $pin_groups {
-      utl::info PPL 41 "Pin group $group_idx: \[$group\]"
       set pin_list {}
       foreach pin_name $group {
         set db_bterm [$dbBlock findBTerm $pin_name]
@@ -732,10 +728,6 @@ proc add_pins_to_top_layer { cmd names llx lly urx ury } {
   }
 
   set top_layer_name [$top_layer getConstName]
-  utl::info PPL 60 "Restrict pins \[$names\] to region\
-    ([ord::dbu_to_microns $llx]u, [ord::dbu_to_microns $lly]u)-\
-    ([ord::dbu_to_microns $urx]u, [ord::dbu_to_microns $urx]u) at\
-    routing layer $top_layer_name."
   set pin_list [ppl::parse_pin_names $cmd $names]
   ppl::add_top_layer_constraint $pin_list $llx $lly $urx $ury
 }
diff --git a/src/ppl/test/add_constraint1.ok b/src/ppl/test/add_constraint1.ok
index ec50cd45058..10d1487a03f 100644
--- a/src/ppl/test/add_constraint1.ok
+++ b/src/ppl/test/add_constraint1.ok
@@ -3,6 +3,7 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0067] Restrict INPUT pins to region 0.0u-100.13u, in the TOP edge.
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           2494
 [INFO PPL-0002] Number of I/O             54
diff --git a/src/ppl/test/add_constraint10.ok b/src/ppl/test/add_constraint10.ok
index 52f31f110aa..0c78c906e9f 100644
--- a/src/ppl/test/add_constraint10.ok
+++ b/src/ppl/test/add_constraint10.ok
@@ -3,6 +3,8 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0048] Restrict pins [ clk resp_msg[13] resp_msg[12] resp_msg[11] resp_msg[10] ... ] to region 0.00u-100.13u at the BOTTOM edge.
+[INFO PPL-0048] Restrict pins [ req_msg[13] req_msg[12] req_msg[11] req_msg[10] req_rdy ... ] to region 0.00u-18.00u at the TOP edge.
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           2494
 [INFO PPL-0002] Number of I/O             54
diff --git a/src/ppl/test/add_constraint11.ok b/src/ppl/test/add_constraint11.ok
index 8341c38787a..8ea43506d00 100644
--- a/src/ppl/test/add_constraint11.ok
+++ b/src/ppl/test/add_constraint11.ok
@@ -3,6 +3,7 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0048] Restrict pins [ clk resp_msg[12] resp_msg[11] resp_msg[10] resp_msg[1] ... ] to region 0.00u-100.13u at the BOTTOM edge.
 [INFO PPL-0044] Pin group: [ resp_msg[0] resp_msg[1] clk resp_val resp_rdy ... ]
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           2494
diff --git a/src/ppl/test/add_constraint12.ok b/src/ppl/test/add_constraint12.ok
index 75cfc466630..68969863487 100644
--- a/src/ppl/test/add_constraint12.ok
+++ b/src/ppl/test/add_constraint12.ok
@@ -3,6 +3,8 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0048] Restrict pins [ req_val resp_msg[14] resp_msg[3] resp_msg[2] ] to region 0.00u-18.00u at the TOP edge.
+[INFO PPL-0048] Restrict pins [ req_msg[13] req_msg[12] req_msg[11] req_msg[10] req_rdy ... ] to region 0.00u-18.00u at the BOTTOM edge.
 [INFO PPL-0044] Pin group: [ resp_msg[3] resp_msg[2] resp_msg[14] req_val ]
 [INFO PPL-0044] Pin group: [ req_rdy req_msg[10] req_msg[11] req_msg[12] req_msg[13] ... ]
 Found 0 macro blocks.
diff --git a/src/ppl/test/add_constraint13.ok b/src/ppl/test/add_constraint13.ok
index 3e742e1cb8f..773175f2c2a 100644
--- a/src/ppl/test/add_constraint13.ok
+++ b/src/ppl/test/add_constraint13.ok
@@ -3,6 +3,8 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0048] Restrict pins [ req_val resp_msg[14] resp_msg[3] resp_msg[2] ] to region 0.00u-18.00u at the TOP edge.
+[INFO PPL-0048] Restrict pins [ req_msg[13] req_msg[12] req_msg[11] req_msg[10] req_rdy ... ] to region 0.00u-18.00u at the BOTTOM edge.
 [INFO PPL-0044] Pin group: [ resp_msg[3] resp_msg[2] resp_msg[14] req_val ]
 [INFO PPL-0044] Pin group: [ req_rdy req_msg[10] req_msg[11] req_msg[12] req_msg[13] ... ]
 Found 0 macro blocks.
diff --git a/src/ppl/test/add_constraint14.ok b/src/ppl/test/add_constraint14.ok
index 8341c38787a..8ea43506d00 100644
--- a/src/ppl/test/add_constraint14.ok
+++ b/src/ppl/test/add_constraint14.ok
@@ -3,6 +3,7 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0048] Restrict pins [ clk resp_msg[12] resp_msg[11] resp_msg[10] resp_msg[1] ... ] to region 0.00u-100.13u at the BOTTOM edge.
 [INFO PPL-0044] Pin group: [ resp_msg[0] resp_msg[1] clk resp_val resp_rdy ... ]
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           2494
diff --git a/src/ppl/test/add_constraint15.ok b/src/ppl/test/add_constraint15.ok
index c0683e81520..c5144b9f52f 100644
--- a/src/ppl/test/add_constraint15.ok
+++ b/src/ppl/test/add_constraint15.ok
@@ -3,6 +3,7 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0048] Restrict pins [ req_msg[31] req_msg[30] req_msg[29] req_msg[28] req_msg[27] ... ] to region 0.00u-100.13u at the BOTTOM edge.
 [INFO PPL-0044] Pin group: [ req_msg[0] req_msg[1] req_msg[2] req_msg[3] req_msg[4] ... ]
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           1008
diff --git a/src/ppl/test/add_constraint16.ok b/src/ppl/test/add_constraint16.ok
index 494531dcbfd..84072683563 100644
--- a/src/ppl/test/add_constraint16.ok
+++ b/src/ppl/test/add_constraint16.ok
@@ -3,7 +3,9 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0048] Restrict pins [ req_msg[31] req_msg[30] req_msg[29] req_msg[28] req_msg[27] ... ] to region 0.00u-100.13u at the BOTTOM edge.
 [INFO PPL-0044] Pin group: [ req_msg[0] req_msg[1] req_msg[2] req_msg[3] req_msg[4] ... ]
+[INFO PPL-0048] Restrict pins [ resp_msg[15] resp_msg[14] resp_msg[13] resp_msg[12] resp_msg[11] ... ] to region 0.00u-100.13u at the BOTTOM edge.
 [INFO PPL-0044] Pin group: [ resp_msg[0] resp_msg[1] resp_msg[2] resp_msg[3] resp_msg[4] ... ]
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           1008
diff --git a/src/ppl/test/add_constraint2.ok b/src/ppl/test/add_constraint2.ok
index 8369ed9172a..762a1804d31 100644
--- a/src/ppl/test/add_constraint2.ok
+++ b/src/ppl/test/add_constraint2.ok
@@ -3,6 +3,7 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0067] Restrict INPUT pins to region 0.0u-100.13u, in the BOTTOM edge.
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           2494
 [INFO PPL-0002] Number of I/O             54
diff --git a/src/ppl/test/add_constraint3.ok b/src/ppl/test/add_constraint3.ok
index 8ec19637c92..7840a1fee16 100644
--- a/src/ppl/test/add_constraint3.ok
+++ b/src/ppl/test/add_constraint3.ok
@@ -3,6 +3,7 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0067] Restrict INPUT pins to region 0.0u-100.8u, in the LEFT edge.
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           2494
 [INFO PPL-0002] Number of I/O             54
diff --git a/src/ppl/test/add_constraint4.ok b/src/ppl/test/add_constraint4.ok
index 545ced0db10..fc321cd1f71 100644
--- a/src/ppl/test/add_constraint4.ok
+++ b/src/ppl/test/add_constraint4.ok
@@ -3,6 +3,7 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0067] Restrict INPUT pins to region 0.0u-100.8u, in the RIGHT edge.
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           2494
 [INFO PPL-0002] Number of I/O             54
diff --git a/src/ppl/test/add_constraint5.ok b/src/ppl/test/add_constraint5.ok
index 90dfbf86fc0..812fc05ba01 100644
--- a/src/ppl/test/add_constraint5.ok
+++ b/src/ppl/test/add_constraint5.ok
@@ -3,6 +3,10 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0067] Restrict INPUT pins to region 0.0u-100.8u, in the RIGHT edge.
+[INFO PPL-0067] Restrict OUTPUT pins to region 0.0u-100.8u, in the LEFT edge.
+[INFO PPL-0048] Restrict pins [ req_rdy req_val resp_rdy resp_val ] to region 0.00u-100.13u at the BOTTOM edge.
+[INFO PPL-0048] Restrict pins [ req_msg[15] req_msg[14] resp_msg[15] resp_msg[14] ] to region 0.00u-100.13u at the TOP edge.
 Found 0 macro blocks.
 [ERROR PPL-0098] Pins  req_msg[15] req_msg[14] req_rdy req_val resp_msg[15] resp_msg[14] resp_rdy resp_val are assigned to multiple constraints.
 PPL-0098
diff --git a/src/ppl/test/add_constraint6.ok b/src/ppl/test/add_constraint6.ok
index 7842616021c..568e489327a 100644
--- a/src/ppl/test/add_constraint6.ok
+++ b/src/ppl/test/add_constraint6.ok
@@ -3,6 +3,8 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0048] Restrict pins [ req_msg[31] req_msg[30] req_msg[29] req_msg[28] req_msg[27] ... ] to region 0.00u-100.13u at the BOTTOM edge.
+[INFO PPL-0048] Restrict pins [ req_msg[15] req_msg[14] resp_msg[15] resp_msg[14] ] to region 0.00u-100.13u at the TOP edge.
 Found 0 macro blocks.
 Using 2 tracks default min distance between IO pins.
 [ERROR PPL-0098] Pins  req_msg[15] req_msg[14] are assigned to multiple constraints.
diff --git a/src/ppl/test/add_constraint7.ok b/src/ppl/test/add_constraint7.ok
index 16f75807a9a..e6b38e56584 100644
--- a/src/ppl/test/add_constraint7.ok
+++ b/src/ppl/test/add_constraint7.ok
@@ -3,6 +3,7 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0048] Restrict pins [ req_msg[31] req_msg[30] req_msg[29] req_msg[28] req_msg[27] ... ] to region 0.00u-100.13u at the BOTTOM edge.
 Found 0 macro blocks.
 Using 2 tracks default min distance between IO pins.
 [INFO PPL-0007] Random pin placement.
diff --git a/src/ppl/test/add_constraint8.ok b/src/ppl/test/add_constraint8.ok
index 1535c65be97..c7e62e245e5 100644
--- a/src/ppl/test/add_constraint8.ok
+++ b/src/ppl/test/add_constraint8.ok
@@ -3,6 +3,8 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0048] Restrict pins [ req_msg[31] req_msg[30] req_msg[29] req_msg[28] req_msg[27] ... ] to region 0.00u-18.00u at the BOTTOM edge.
+[INFO PPL-0048] Restrict pins [ resp_msg[15] resp_msg[14] resp_msg[13] resp_msg[12] resp_msg[11] ... ] to region 10.00u-20.00u at the BOTTOM edge.
 Found 0 macro blocks.
 Using 2 tracks default min distance between IO pins.
 [INFO PPL-0001] Number of slots           1228
diff --git a/src/ppl/test/add_constraint_error3.ok b/src/ppl/test/add_constraint_error3.ok
index 237236104f5..cc4b2d1bf27 100644
--- a/src/ppl/test/add_constraint_error3.ok
+++ b/src/ppl/test/add_constraint_error3.ok
@@ -3,5 +3,6 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0067] Restrict INPUT pins to region 0.0u-100.13u, in the TOP edge.
 [ERROR PPL-0058] The -pin_names argument is required when using -group flag.
 PPL-0058
diff --git a/src/ppl/test/add_constraint_error5.ok b/src/ppl/test/add_constraint_error5.ok
index c52e83d5412..bb0e085946a 100644
--- a/src/ppl/test/add_constraint_error5.ok
+++ b/src/ppl/test/add_constraint_error5.ok
@@ -3,5 +3,6 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0048] Restrict pins [ req_val resp_msg[14] resp_msg[3] resp_msg[2] ] to region 0.00u-100.13u at the TOP edge.
 [ERROR PPL-0095] -order cannot be used without -group.
 PPL-0095
diff --git a/src/ppl/test/add_constraint_error7.ok b/src/ppl/test/add_constraint_error7.ok
index 2129c137c22..344d5786cd4 100644
--- a/src/ppl/test/add_constraint_error7.ok
+++ b/src/ppl/test/add_constraint_error7.ok
@@ -3,6 +3,7 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0048] Restrict pins [ clk req_msg[31] req_msg[30] req_msg[29] req_msg[28] ... ] to region 10.00u-30.00u at the TOP edge.
 Found 0 macro blocks.
 Using 2 tracks default min distance between IO pins.
 [WARNING PPL-0110] Constraint has 54 pins, but only 52 available slots.
diff --git a/src/ppl/test/annealing_constraint1.ok b/src/ppl/test/annealing_constraint1.ok
index f5525397318..f7432b413e6 100644
--- a/src/ppl/test/annealing_constraint1.ok
+++ b/src/ppl/test/annealing_constraint1.ok
@@ -3,6 +3,8 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0067] Restrict INPUT pins to region 0.0u-100.13u, in the TOP edge.
+[INFO PPL-0067] Restrict OUTPUT pins to region 0.0u-100.13u, in the BOTTOM edge.
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           2494
 [INFO PPL-0002] Number of I/O             54
diff --git a/src/ppl/test/annealing_constraint2.ok b/src/ppl/test/annealing_constraint2.ok
index 1c93b8a341c..8c5414618cb 100644
--- a/src/ppl/test/annealing_constraint2.ok
+++ b/src/ppl/test/annealing_constraint2.ok
@@ -3,6 +3,8 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0067] Restrict INPUT pins to region 0.0u-100.13u, in the BOTTOM edge.
+[INFO PPL-0067] Restrict OUTPUT pins to region 0.0u-100.13u, in the TOP edge.
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           2494
 [INFO PPL-0002] Number of I/O             54
diff --git a/src/ppl/test/annealing_constraint3.ok b/src/ppl/test/annealing_constraint3.ok
index 3b09df0fa3c..8f8f86f50e1 100644
--- a/src/ppl/test/annealing_constraint3.ok
+++ b/src/ppl/test/annealing_constraint3.ok
@@ -3,6 +3,8 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0067] Restrict INPUT pins to region 0.0u-100.8u, in the LEFT edge.
+[INFO PPL-0067] Restrict OUTPUT pins to region 0.0u-100.8u, in the RIGHT edge.
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           2494
 [INFO PPL-0002] Number of I/O             54
diff --git a/src/ppl/test/annealing_constraint4.ok b/src/ppl/test/annealing_constraint4.ok
index d053d1834bc..cb58a256f86 100644
--- a/src/ppl/test/annealing_constraint4.ok
+++ b/src/ppl/test/annealing_constraint4.ok
@@ -3,6 +3,8 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0067] Restrict INPUT pins to region 0.0u-100.8u, in the RIGHT edge.
+[INFO PPL-0067] Restrict OUTPUT pins to region 0.0u-100.8u, in the LEFT edge.
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           2494
 [INFO PPL-0002] Number of I/O             54
diff --git a/src/ppl/test/annealing_constraint5.ok b/src/ppl/test/annealing_constraint5.ok
index 02fb25d6507..1511bc4c36c 100644
--- a/src/ppl/test/annealing_constraint5.ok
+++ b/src/ppl/test/annealing_constraint5.ok
@@ -3,6 +3,8 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0048] Restrict pins [ req_msg[31] req_msg[30] req_msg[29] req_msg[28] req_msg[27] ... ] to region 0.00u-100.13u at the BOTTOM edge.
+[INFO PPL-0048] Restrict pins [ resp_msg[15] resp_msg[14] resp_msg[13] resp_msg[12] resp_msg[11] ... ] to region 0.00u-100.80u at the RIGHT edge.
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           2494
 [INFO PPL-0002] Number of I/O             54
diff --git a/src/ppl/test/annealing_constraint6.ok b/src/ppl/test/annealing_constraint6.ok
index 15b9baf77c8..f01c557543a 100644
--- a/src/ppl/test/annealing_constraint6.ok
+++ b/src/ppl/test/annealing_constraint6.ok
@@ -3,7 +3,9 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0048] Restrict pins [ req_msg[31] req_msg[30] req_msg[29] req_msg[28] req_msg[27] ... ] to region 0.00u-100.13u at the BOTTOM edge.
 [INFO PPL-0044] Pin group: [ req_msg[0] req_msg[1] req_msg[2] req_msg[3] req_msg[4] ... ]
+[INFO PPL-0048] Restrict pins [ resp_msg[15] resp_msg[14] resp_msg[13] resp_msg[12] resp_msg[11] ... ] to region 0.00u-100.13u at the TOP edge.
 [INFO PPL-0044] Pin group: [ resp_msg[0] resp_msg[1] resp_msg[2] resp_msg[3] resp_msg[4] ... ]
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           1008
diff --git a/src/ppl/test/annealing_constraint7.ok b/src/ppl/test/annealing_constraint7.ok
index fcd65a07349..70c498a9eb9 100644
--- a/src/ppl/test/annealing_constraint7.ok
+++ b/src/ppl/test/annealing_constraint7.ok
@@ -3,7 +3,9 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0048] Restrict pins [ req_msg[31] req_msg[30] req_msg[29] req_msg[28] req_msg[27] ... ] to region 0.00u-100.80u at the LEFT edge.
 [INFO PPL-0044] Pin group: [ req_msg[0] req_msg[1] req_msg[2] req_msg[3] req_msg[4] ... ]
+[INFO PPL-0048] Restrict pins [ resp_msg[15] resp_msg[14] resp_msg[13] resp_msg[12] resp_msg[11] ... ] to region 0.00u-100.80u at the RIGHT edge.
 [INFO PPL-0044] Pin group: [ resp_msg[0] resp_msg[1] resp_msg[2] resp_msg[3] resp_msg[4] ... ]
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           1008
diff --git a/src/ppl/test/annealing_constraint8.ok b/src/ppl/test/annealing_constraint8.ok
index 49735fb8b92..8c3cf4f15f0 100644
--- a/src/ppl/test/annealing_constraint8.ok
+++ b/src/ppl/test/annealing_constraint8.ok
@@ -3,6 +3,10 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0048] Restrict pins [ resp_val ] to region 0.00u-100.13u at the BOTTOM edge.
+[INFO PPL-0048] Restrict pins [ clk ] to region 0.00u-100.13u at the TOP edge.
+[INFO PPL-0048] Restrict pins [ reset ] to region 0.00u-100.80u at the LEFT edge.
+[INFO PPL-0048] Restrict pins [ resp_rdy ] to region 0.00u-100.80u at the RIGHT edge.
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           2494
 [INFO PPL-0002] Number of I/O             54
diff --git a/src/ppl/test/annealing_mirrored3.ok b/src/ppl/test/annealing_mirrored3.ok
index 917ffd47789..96b1238c224 100644
--- a/src/ppl/test/annealing_mirrored3.ok
+++ b/src/ppl/test/annealing_mirrored3.ok
@@ -3,6 +3,7 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0048] Restrict pins [ req_msg[10] req_msg[9] req_msg[8] req_msg[7] req_msg[6] ... ] to region 0.00u-100.13u at the BOTTOM edge.
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           2494
 [INFO PPL-0002] Number of I/O             54
diff --git a/src/ppl/test/annealing_mirrored4.ok b/src/ppl/test/annealing_mirrored4.ok
index 7757c541bd8..11782459cba 100644
--- a/src/ppl/test/annealing_mirrored4.ok
+++ b/src/ppl/test/annealing_mirrored4.ok
@@ -3,6 +3,7 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0048] Restrict pins [ req_msg[10] req_msg[9] req_msg[8] req_msg[7] req_msg[6] ... ] to region 0.00u-100.13u at the BOTTOM edge.
 [INFO PPL-0044] Pin group: [ req_msg[0] req_msg[1] req_msg[2] req_msg[3] req_msg[4] ... ]
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           2494
diff --git a/src/ppl/test/annealing_mirrored5.ok b/src/ppl/test/annealing_mirrored5.ok
index 94f087d078f..10b64b38932 100644
--- a/src/ppl/test/annealing_mirrored5.ok
+++ b/src/ppl/test/annealing_mirrored5.ok
@@ -3,6 +3,7 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0048] Restrict pins [ req_msg[10] req_msg[9] req_msg[8] req_msg[7] req_msg[6] ... ] to region 0.00u-100.13u at the BOTTOM edge.
 [INFO PPL-0044] Pin group: [ req_msg[0] req_msg[1] req_msg[2] req_msg[3] req_msg[4] ... ]
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           2494
diff --git a/src/ppl/test/cells_not_placed.ok b/src/ppl/test/cells_not_placed.ok
index 8f877723591..252938438bf 100644
--- a/src/ppl/test/cells_not_placed.ok
+++ b/src/ppl/test/cells_not_placed.ok
@@ -3,6 +3,8 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 295 components and 1600 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 164 connections.
+[INFO PPL-0067] Restrict INPUT pins to region 0.0u-100.13u, in the TOP edge.
+[INFO PPL-0067] Restrict OUTPUT pins to region 0.0u-100.13u, in the BOTTOM edge.
 Found 0 macro blocks.
 Using 2 tracks default min distance between IO pins.
 [INFO PPL-0001] Number of slots           1228
diff --git a/src/ppl/test/group_pins10.ok b/src/ppl/test/group_pins10.ok
index 107d90eb8a9..7cd72335a48 100644
--- a/src/ppl/test/group_pins10.ok
+++ b/src/ppl/test/group_pins10.ok
@@ -3,7 +3,9 @@
 [INFO ODB-0130]     Created 103 pins.
 [INFO ODB-0131]     Created 103 components and 412 component-terminals.
 [INFO ODB-0133]     Created 103 nets and 103 connections.
+[INFO PPL-0048] Restrict pins [ bus[0] bus[1] bus[2] bus[3] bus[4] ... ] to region 0.00u-100.80u at the LEFT edge.
 [INFO PPL-0044] Pin group: [ bus[0] bus[1] bus[2] bus[3] bus[4] ... ]
+[INFO PPL-0048] Restrict pins [ clk ] to region 0.00u-100.80u at the LEFT edge.
 [INFO PPL-0044] Pin group: [ clk ]
 Found 0 macro blocks.
 Using 2 tracks default min distance between IO pins.
diff --git a/src/ppl/test/group_pins4.ok b/src/ppl/test/group_pins4.ok
index 06c88d31f98..279a5aeed83 100644
--- a/src/ppl/test/group_pins4.ok
+++ b/src/ppl/test/group_pins4.ok
@@ -3,6 +3,10 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 294 components and 1577 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 131 connections.
+[INFO PPL-0048] Restrict pins [ req_msg[0] req_msg[10] req_msg[11] req_msg[12] req_msg[13] ... ] to region 25.00u-95.00u at the LEFT edge.
+[INFO PPL-0048] Restrict pins [ req_msg[24] req_msg[25] req_msg[26] req_msg[27] req_msg[28] ... ] to region 5.00u-95.00u at the BOTTOM edge.
+[INFO PPL-0048] Restrict pins [ clk req_rdy req_val reset resp_msg[0] ... ] to region 15.00u-95.00u at the TOP edge.
+[INFO PPL-0048] Restrict pins [ resp_msg[1] resp_msg[2] resp_msg[3] resp_msg[4] resp_msg[5] ... ] to region 35.00u-75.00u at the RIGHT edge.
 Found 0 macro blocks.
 [INFO PPL-0044] Pin group: [ req_msg[10] req_msg[11] req_msg[12] req_msg[13] req_msg[14] ... ]
 [INFO PPL-0044] Pin group: [ req_msg[24] req_msg[25] req_msg[26] req_msg[27] req_msg[28] ... ]
diff --git a/src/ppl/test/group_pins6.ok b/src/ppl/test/group_pins6.ok
index f73a1041958..92a88a31d50 100644
--- a/src/ppl/test/group_pins6.ok
+++ b/src/ppl/test/group_pins6.ok
@@ -3,6 +3,10 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 294 components and 1577 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 131 connections.
+[INFO PPL-0048] Restrict pins [ req_msg[0] req_msg[10] req_msg[11] req_msg[12] req_msg[13] ... ] to region 25.00u-95.00u at the LEFT edge.
+[INFO PPL-0048] Restrict pins [ req_msg[24] req_msg[25] req_msg[26] req_msg[27] req_msg[28] ... ] to region 5.00u-95.00u at the BOTTOM edge.
+[INFO PPL-0048] Restrict pins [ clk req_rdy req_val reset resp_msg[0] ... ] to region 15.00u-95.00u at the TOP edge.
+[INFO PPL-0048] Restrict pins [ resp_msg[1] resp_msg[2] resp_msg[3] resp_msg[4] resp_msg[5] ... ] to region 35.00u-75.00u at the RIGHT edge.
 Found 0 macro blocks.
 [INFO PPL-0044] Pin group: [ req_msg[10] req_msg[11] req_msg[12] req_msg[13] req_msg[14] ... ]
 [INFO PPL-0044] Pin group: [ req_msg[24] req_msg[25] req_msg[26] req_msg[27] req_msg[28] ... ]
diff --git a/src/ppl/test/group_pins7.ok b/src/ppl/test/group_pins7.ok
index 12530deb96d..a5303199127 100644
--- a/src/ppl/test/group_pins7.ok
+++ b/src/ppl/test/group_pins7.ok
@@ -3,6 +3,10 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 294 components and 1577 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 131 connections.
+[INFO PPL-0048] Restrict pins [ req_msg[0] req_msg[10] req_msg[11] req_msg[12] req_msg[13] ... ] to region 0.00u-100.80u at the LEFT edge.
+[INFO PPL-0048] Restrict pins [ req_msg[24] req_msg[25] req_msg[26] req_msg[27] req_msg[28] ... ] to region 0.00u-100.13u at the BOTTOM edge.
+[INFO PPL-0048] Restrict pins [ clk req_rdy req_val reset resp_msg[0] ... ] to region 0.00u-100.13u at the TOP edge.
+[INFO PPL-0048] Restrict pins [ resp_msg[1] resp_msg[2] resp_msg[3] resp_msg[4] resp_msg[5] ... ] to region 0.00u-100.80u at the RIGHT edge.
 Found 0 macro blocks.
 [INFO PPL-0044] Pin group: [ req_msg[10] req_msg[11] req_msg[12] req_msg[13] req_msg[14] ... ]
 [INFO PPL-0044] Pin group: [ req_msg[24] req_msg[25] req_msg[26] req_msg[27] req_msg[28] ... ]
diff --git a/src/ppl/test/large_groups3.ok b/src/ppl/test/large_groups3.ok
index 13cd23ecf2e..51646ed15cc 100644
--- a/src/ppl/test/large_groups3.ok
+++ b/src/ppl/test/large_groups3.ok
@@ -3,7 +3,9 @@
 [INFO ODB-0130]     Created 400 pins.
 [INFO ODB-0131]     Created 1 components and 6 component-terminals.
 [INFO ODB-0133]     Created 1 nets and 1 connections.
+[INFO PPL-0048] Restrict pins [ pin0 pin1 pin10 pin100 pin101 ... ] to region 0.00u-100.13u at the TOP edge.
 [INFO PPL-0044] Pin group: [ pin0 pin1 pin2 pin3 pin4 ... ]
+[INFO PPL-0048] Restrict pins [ pin300 pin301 pin302 pin303 pin304 ... ] to region 0.00u-100.13u at the TOP edge.
 [INFO PPL-0044] Pin group: [ pin300 pin301 pin302 pin303 pin304 ... ]
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           1754
diff --git a/src/ppl/test/large_groups4.ok b/src/ppl/test/large_groups4.ok
index 7c089d9db3e..62347d6af67 100644
--- a/src/ppl/test/large_groups4.ok
+++ b/src/ppl/test/large_groups4.ok
@@ -3,7 +3,9 @@
 [INFO ODB-0130]     Created 400 pins.
 [INFO ODB-0131]     Created 1 components and 6 component-terminals.
 [INFO ODB-0133]     Created 1 nets and 1 connections.
+[INFO PPL-0048] Restrict pins [ pin0 pin1 pin10 pin100 pin101 ... ] to region 0.00u-100.13u at the TOP edge.
 [INFO PPL-0044] Pin group: [ pin0 pin1 pin2 pin3 pin4 ... ]
+[INFO PPL-0048] Restrict pins [ pin300 pin301 pin302 pin303 pin304 ... ] to region 0.00u-100.13u at the BOTTOM edge.
 [INFO PPL-0044] Pin group: [ pin300 pin301 pin302 pin303 pin304 ... ]
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           1754
diff --git a/src/ppl/test/random3.ok b/src/ppl/test/random3.ok
index 16f75807a9a..d8f2ce9834c 100644
--- a/src/ppl/test/random3.ok
+++ b/src/ppl/test/random3.ok
@@ -3,6 +3,8 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0067] Restrict INPUT pins to region 0.0u-100.13u, in the TOP edge.
+[INFO PPL-0067] Restrict OUTPUT pins to region 0.0u-100.13u, in the BOTTOM edge.
 Found 0 macro blocks.
 Using 2 tracks default min distance between IO pins.
 [INFO PPL-0007] Random pin placement.
diff --git a/src/ppl/test/random4.ok b/src/ppl/test/random4.ok
index 16f75807a9a..af11a5c1e79 100644
--- a/src/ppl/test/random4.ok
+++ b/src/ppl/test/random4.ok
@@ -3,6 +3,8 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0048] Restrict pins [ req_rdy req_val resp_rdy resp_val ] to region 0.00u-100.13u at the BOTTOM edge.
+[INFO PPL-0048] Restrict pins [ req_msg[15] req_msg[14] resp_msg[15] resp_msg[14] ] to region 0.00u-100.13u at the TOP edge.
 Found 0 macro blocks.
 Using 2 tracks default min distance between IO pins.
 [INFO PPL-0007] Random pin placement.
diff --git a/src/ppl/test/random5.ok b/src/ppl/test/random5.ok
index 16f75807a9a..ee7932b0a41 100644
--- a/src/ppl/test/random5.ok
+++ b/src/ppl/test/random5.ok
@@ -3,6 +3,7 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0060] Restrict pins [ clk req_rdy req_val reset resp_rdy ... ] to region (0.10u, 0.07u)-(90.00u, 90.00u) at routing layer metal10.
 Found 0 macro blocks.
 Using 2 tracks default min distance between IO pins.
 [INFO PPL-0007] Random pin placement.
diff --git a/src/ppl/test/random6.ok b/src/ppl/test/random6.ok
index 16f75807a9a..e10c2138093 100644
--- a/src/ppl/test/random6.ok
+++ b/src/ppl/test/random6.ok
@@ -3,6 +3,7 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0060] Restrict pins [ clk req_msg[31] req_msg[30] req_msg[29] req_msg[28] ... ] to region (0.10u, 0.07u)-(90.00u, 90.00u) at routing layer metal10.
 Found 0 macro blocks.
 Using 2 tracks default min distance between IO pins.
 [INFO PPL-0007] Random pin placement.
diff --git a/src/ppl/test/random8.ok b/src/ppl/test/random8.ok
index bcc98ead385..6499662fe8e 100644
--- a/src/ppl/test/random8.ok
+++ b/src/ppl/test/random8.ok
@@ -3,6 +3,9 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0067] Restrict INPUT pins to region 0.0u-100.13u, in the TOP edge.
+[INFO PPL-0067] Restrict OUTPUT pins to region 0.0u-100.13u, in the BOTTOM edge.
+[INFO PPL-0048] Restrict pins [ req_msg[17] req_msg[16] req_msg[15] req_msg[14] ] to region 0.00u-100.80u at the LEFT edge.
 Found 0 macro blocks.
 Using 2 tracks default min distance between IO pins.
 [INFO PPL-0044] Pin group: [ req_msg[14] req_msg[15] req_msg[16] req_msg[17] ]
diff --git a/src/ppl/test/random9.ok b/src/ppl/test/random9.ok
index 16f75807a9a..2cb7c6b9ea4 100644
--- a/src/ppl/test/random9.ok
+++ b/src/ppl/test/random9.ok
@@ -3,6 +3,7 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0048] Restrict pins [ req_msg[15] req_msg[14] ] to region 0.00u-100.13u at the TOP edge.
 Found 0 macro blocks.
 Using 2 tracks default min distance between IO pins.
 [INFO PPL-0007] Random pin placement.
diff --git a/src/ppl/test/top_layer1.ok b/src/ppl/test/top_layer1.ok
index 2c7e2fe7337..fbf1503296e 100644
--- a/src/ppl/test/top_layer1.ok
+++ b/src/ppl/test/top_layer1.ok
@@ -5,6 +5,7 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 253 components and 1357 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 155 connections.
+[INFO PPL-0060] Restrict pins [ clk req_rdy req_val reset resp_rdy ... ] to region (0.00u, 0.00u)-(279.96u, 280.13u) at routing layer met5.
 Found 1 macro blocks.
 Using 2 tracks default min distance between IO pins.
 [INFO PPL-0001] Number of slots           1016
diff --git a/src/ppl/test/top_layer2.ok b/src/ppl/test/top_layer2.ok
index f8c52739f16..8c7ab159d92 100644
--- a/src/ppl/test/top_layer2.ok
+++ b/src/ppl/test/top_layer2.ok
@@ -5,6 +5,7 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 253 components and 1357 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 155 connections.
+[INFO PPL-0060] Restrict pins [ clk req_rdy req_val reset resp_rdy ... ] to region (170.00u, 200.00u)-(250.00u, 250.00u) at routing layer met5.
 Found 1 macro blocks.
 Using 2 tracks default min distance between IO pins.
 [INFO PPL-0001] Number of slots           1016
diff --git a/src/ppl/test/top_layer3.ok b/src/ppl/test/top_layer3.ok
index e49bfff5894..38f70e3a098 100644
--- a/src/ppl/test/top_layer3.ok
+++ b/src/ppl/test/top_layer3.ok
@@ -3,6 +3,7 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0060] Restrict pins [ clk req_rdy req_val reset resp_rdy ... ] to region (70.00u, 50.00u)-(95.00u, 100.00u) at routing layer metal10.
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           2494
 [INFO PPL-0062] Number of top layer slots 361
diff --git a/src/ppl/test/top_layer4.ok b/src/ppl/test/top_layer4.ok
index 98df54a4b3a..908f725eb75 100644
--- a/src/ppl/test/top_layer4.ok
+++ b/src/ppl/test/top_layer4.ok
@@ -3,6 +3,7 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0060] Restrict pins [ clk req_msg[31] req_msg[30] req_msg[29] req_msg[28] ... ] to region (0.10u, 0.07u)-(90.00u, 90.00u) at routing layer metal10.
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           2494
 [INFO PPL-0062] Number of top layer slots 441
diff --git a/src/ppl/test/top_layer5.ok b/src/ppl/test/top_layer5.ok
index f22b7410663..bb164ff8b83 100644
--- a/src/ppl/test/top_layer5.ok
+++ b/src/ppl/test/top_layer5.ok
@@ -3,6 +3,7 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0060] Restrict pins [ req_msg[31] req_msg[30] req_msg[29] req_msg[28] req_msg[27] ... ] to region (0.10u, 0.07u)-(90.00u, 90.00u) at routing layer metal10.
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           2494
 [INFO PPL-0062] Number of top layer slots 441
diff --git a/src/ppl/test/top_layer6.ok b/src/ppl/test/top_layer6.ok
index d71e73ac9aa..a11ab734da0 100644
--- a/src/ppl/test/top_layer6.ok
+++ b/src/ppl/test/top_layer6.ok
@@ -4,6 +4,7 @@
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
 [INFO PPL-0070] Pin clk placed at (4.80um, 4.80um).
+[INFO PPL-0060] Restrict pins [ clk req_msg[31] req_msg[30] req_msg[29] req_msg[28] ... ] to region (0.00u, 0.00u)-(100.13u, 100.80u) at routing layer metal10.
 Found 0 macro blocks.
 Using 2 tracks default min distance between IO pins.
 [INFO PPL-0007] Random pin placement.
diff --git a/src/ppl/test/top_layer7.ok b/src/ppl/test/top_layer7.ok
index 604c31147ae..815acb7abd2 100644
--- a/src/ppl/test/top_layer7.ok
+++ b/src/ppl/test/top_layer7.ok
@@ -2,6 +2,7 @@
 [INFO ODB-0128] Design: gcd
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0132]     Created 2 special nets and 0 connections.
+[INFO PPL-0060] Restrict pins [ clk req_msg[0] req_msg[10] req_msg[11] req_msg[12] ... ] to region (0.00u, 0.00u)-(100.13u, 100.80u) at routing layer metal7.
 Found 0 macro blocks.
 Using 2 tracks default min distance between IO pins.
 [INFO PPL-0007] Random pin placement.
diff --git a/src/ppl/test/top_layer_error2.ok b/src/ppl/test/top_layer_error2.ok
index d442297ea89..882f75cd15f 100644
--- a/src/ppl/test/top_layer_error2.ok
+++ b/src/ppl/test/top_layer_error2.ok
@@ -2,6 +2,7 @@
 [INFO ODB-0128] Design: gcd
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0132]     Created 2 special nets and 0 connections.
+[INFO PPL-0060] Restrict pins [ clk req_msg[0] req_msg[10] req_msg[11] req_msg[12] ... ] to region (0.00u, 0.00u)-(100.13u, 100.80u) at routing layer metal7.
 Found 0 macro blocks.
 Using 2 tracks default min distance between IO pins.
 [ERROR PPL-0011] Number of IO pins assigned to the top layer (54) exceeds maximum number of available top layer positions (40).
diff --git a/src/ppl/test/write_pin_placement1.ok b/src/ppl/test/write_pin_placement1.ok
index 044855c61b0..952503190f6 100644
--- a/src/ppl/test/write_pin_placement1.ok
+++ b/src/ppl/test/write_pin_placement1.ok
@@ -3,7 +3,9 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0048] Restrict pins [ req_msg[31] req_msg[30] req_msg[29] req_msg[28] req_msg[27] ... ] to region 0.00u-100.13u at the BOTTOM edge.
 [INFO PPL-0044] Pin group: [ req_msg[0] req_msg[1] req_msg[2] req_msg[3] req_msg[4] ... ]
+[INFO PPL-0048] Restrict pins [ resp_msg[15] resp_msg[14] resp_msg[13] resp_msg[12] resp_msg[11] ... ] to region 0.00u-100.13u at the TOP edge.
 [INFO PPL-0044] Pin group: [ resp_msg[0] resp_msg[1] resp_msg[2] resp_msg[3] resp_msg[4] ... ]
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           1008
diff --git a/src/ppl/test/write_pin_placement3.ok b/src/ppl/test/write_pin_placement3.ok
index 931ae1df273..c198fd7df4b 100644
--- a/src/ppl/test/write_pin_placement3.ok
+++ b/src/ppl/test/write_pin_placement3.ok
@@ -3,6 +3,7 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0048] Restrict pins [ req_msg[10] req_msg[9] req_msg[8] req_msg[7] req_msg[6] ... ] to region 0.00u-100.13u at the BOTTOM edge.
 [INFO PPL-0044] Pin group: [ req_msg[0] req_msg[1] req_msg[2] req_msg[3] req_msg[4] ... ]
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           2494
diff --git a/src/ppl/test/write_pin_placement4.ok b/src/ppl/test/write_pin_placement4.ok
index 44d5fb989e8..66cf1837fa3 100644
--- a/src/ppl/test/write_pin_placement4.ok
+++ b/src/ppl/test/write_pin_placement4.ok
@@ -3,6 +3,7 @@
 [INFO ODB-0130]     Created 54 pins.
 [INFO ODB-0131]     Created 88 components and 422 component-terminals.
 [INFO ODB-0133]     Created 54 nets and 88 connections.
+[INFO PPL-0048] Restrict pins [ req_msg[10] req_msg[9] req_msg[8] req_msg[7] req_msg[6] ... ] to region 0.00u-100.13u at the BOTTOM edge.
 [INFO PPL-0044] Pin group: [ req_msg[0] req_msg[1] req_msg[2] req_msg[3] req_msg[4] ... ]
 Found 0 macro blocks.
 [INFO PPL-0001] Number of slots           2494
diff --git a/src/rsz/include/rsz/Resizer.hh b/src/rsz/include/rsz/Resizer.hh
index e4b9f96e221..c0dba8182f9 100644
--- a/src/rsz/include/rsz/Resizer.hh
+++ b/src/rsz/include/rsz/Resizer.hh
@@ -286,6 +286,7 @@ class Resizer : public dbStaState
   void repairSetup(double setup_margin,
                    double repair_tns_end_percent,
                    int max_passes,
+                   bool match_cell_footprint,
                    bool verbose,
                    bool skip_pin_swap,
                    bool skip_gate_cloning,
@@ -308,6 +309,7 @@ class Resizer : public dbStaState
                   // Max buffer count as percent of design instance count.
                   float max_buffer_percent,
                   int max_passes,
+                  bool match_cell_footprint,
                   bool verbose);
   void repairHold(const Pin* end_pin,
                   double setup_margin,
@@ -318,7 +320,7 @@ class Resizer : public dbStaState
   int holdBufferCount() const;
 
   ////////////////////////////////////////////////////////////////
-  void recoverPower(float recover_power_percent);
+  void recoverPower(float recover_power_percent, bool match_cell_footprint);
 
   ////////////////////////////////////////////////////////////////
   // Area of the design in meter^2.
@@ -348,6 +350,7 @@ class Resizer : public dbStaState
       double slew_margin,      // 0.0-1.0
       double cap_margin,       // 0.0-1.0
       double buffer_gain,
+      bool match_cell_footprint,
       bool verbose);
   int repairDesignBufferCount() const;
   // for debugging
@@ -443,7 +446,7 @@ class Resizer : public dbStaState
   LibertyCell* halfDrivingPowerCell(Instance* inst);
   LibertyCell* halfDrivingPowerCell(LibertyCell* cell);
   LibertyCell* closestDriver(LibertyCell* cell,
-                             LibertyCellSeq* candidates,
+                             const LibertyCellSeq& candidates,
                              float scale);
   std::vector<sta::LibertyPort*> libraryPins(Instance* inst) const;
   std::vector<sta::LibertyPort*> libraryPins(LibertyCell* cell) const;
@@ -473,6 +476,9 @@ class Resizer : public dbStaState
   bool hasMultipleOutputs(const Instance* inst);
 
   void resizePreamble();
+  LibertyCellSeq getSwappableCells(LibertyCell* source_cell);
+  bool footprintsMatch(LibertyCell* source, LibertyCell* target);
+
   // Resize drvr_pin instance to target slew.
   // Return 1 if resized.
   int resizeToTargetSlew(const Pin* drvr_pin);
@@ -740,6 +746,7 @@ class Resizer : public dbStaState
   int removed_buffer_count_ = 0;
   bool exclude_clock_buffers_ = true;
   bool buffer_moved_into_core_ = false;
+  bool match_cell_footprint_ = false;
   // Slack map variables.
   // This is the minimum length of wire that is worth while to split and
   // insert a buffer in the middle of. Theoretically computed using the smallest
diff --git a/src/rsz/src/PreChecks.cc b/src/rsz/src/PreChecks.cc
index 5927dbf1b10..7178e41d291 100644
--- a/src/rsz/src/PreChecks.cc
+++ b/src/rsz/src/PreChecks.cc
@@ -59,16 +59,14 @@ void PreChecks::checkSlewLimit(float ref_cap, float max_load_slew)
   // Ensure the max slew value specified is something the library can
   // potentially handle
   if (!best_case_slew_computed_ || ref_cap < best_case_slew_load_) {
-    LibertyCellSeq* equiv_cells
-        = sta_->equivCells(resizer_->buffer_lowest_drive_);
+    LibertyCellSeq swappable_cells
+        = resizer_->getSwappableCells(resizer_->buffer_lowest_drive_);
     float slew = resizer_->bufferSlew(
         resizer_->buffer_lowest_drive_, ref_cap, resizer_->tgt_slew_dcalc_ap_);
-    if (equiv_cells != nullptr) {
-      for (LibertyCell* buffer : *equiv_cells) {
-        slew = std::min(slew,
-                        resizer_->bufferSlew(
-                            buffer, ref_cap, resizer_->tgt_slew_dcalc_ap_));
-      }
+    for (LibertyCell* buffer : swappable_cells) {
+      slew = std::min(
+          slew,
+          resizer_->bufferSlew(buffer, ref_cap, resizer_->tgt_slew_dcalc_ap_));
     }
     best_case_slew_computed_ = true;
     best_case_slew_load_ = ref_cap;
diff --git a/src/rsz/src/RecoverPower.cc b/src/rsz/src/RecoverPower.cc
index 04fb4807e7c..b71ede74e34 100644
--- a/src/rsz/src/RecoverPower.cc
+++ b/src/rsz/src/RecoverPower.cc
@@ -378,16 +378,16 @@ bool RecoverPower::downsizeDrvr(const PathRef* drvr_path,
 }
 
 bool RecoverPower::meetsSizeCriteria(const LibertyCell* cell,
-                                     const LibertyCell* equiv,
+                                     const LibertyCell* candidate,
                                      const bool match_size)
 {
   if (!match_size) {
     return true;
   }
-  const dbMaster* equivalent_cell = db_network_->staToDb(equiv);
+  const dbMaster* candidate_cell = db_network_->staToDb(candidate);
   const dbMaster* curr_cell = db_network_->staToDb(cell);
-  if (equivalent_cell->getWidth() <= curr_cell->getWidth()
-      && equivalent_cell->getHeight() == curr_cell->getHeight()) {
+  if (candidate_cell->getWidth() <= curr_cell->getWidth()
+      && candidate_cell->getHeight() == curr_cell->getHeight()) {
     return true;
   }
   return false;
@@ -403,46 +403,47 @@ LibertyCell* RecoverPower::downsizeCell(const LibertyPort* in_port,
 {
   const int lib_ap = dcalc_ap->libertyIndex();
   LibertyCell* cell = drvr_port->libertyCell();
-  LibertyCellSeq* equiv_cells = sta_->equivCells(cell);
+  LibertyCellSeq swappable_cells = resizer_->getSwappableCells(cell);
   constexpr double delay_margin = 1.5;  // Prevent overly aggressive downsizing
 
-  if (equiv_cells) {
+  if (!swappable_cells.empty()) {
     const char* in_port_name = in_port->name();
     const char* drvr_port_name = drvr_port->name();
-    sort(equiv_cells, [=](const LibertyCell* cell1, const LibertyCell* cell2) {
-      LibertyPort* port1
-          = cell1->findLibertyPort(drvr_port_name)->cornerPort(lib_ap);
-      const LibertyPort* port2
-          = cell2->findLibertyPort(drvr_port_name)->cornerPort(lib_ap);
-      const float drive1 = port1->driveResistance();
-      const float drive2 = port2->driveResistance();
-      const ArcDelay intrinsic1 = port1->intrinsicDelay(this);
-      const ArcDelay intrinsic2 = port2->intrinsicDelay(this);
-      return (std::tie(drive1, intrinsic2) < std::tie(drive2, intrinsic1));
-    });
+    sort(&swappable_cells,
+         [=](const LibertyCell* cell1, const LibertyCell* cell2) {
+           LibertyPort* port1
+               = cell1->findLibertyPort(drvr_port_name)->cornerPort(lib_ap);
+           const LibertyPort* port2
+               = cell2->findLibertyPort(drvr_port_name)->cornerPort(lib_ap);
+           const float drive1 = port1->driveResistance();
+           const float drive2 = port2->driveResistance();
+           const ArcDelay intrinsic1 = port1->intrinsicDelay(this);
+           const ArcDelay intrinsic2 = port2->intrinsicDelay(this);
+           return (std::tie(drive1, intrinsic2) < std::tie(drive2, intrinsic1));
+         });
     const float drive = drvr_port->cornerPort(lib_ap)->driveResistance();
     const float delay
         = resizer_->gateDelay(drvr_port, load_cap, resizer_->tgt_slew_dcalc_ap_)
           + prev_drive * in_port->cornerPort(lib_ap)->capacitance();
 
     LibertyCell* best_cell = nullptr;
-    for (LibertyCell* equiv : *equiv_cells) {
-      const LibertyCell* equiv_corner = equiv->cornerCell(lib_ap);
-      const LibertyPort* equiv_drvr
-          = equiv_corner->findLibertyPort(drvr_port_name);
-      const LibertyPort* equiv_input
-          = equiv_corner->findLibertyPort(in_port_name);
-      const float current_drive = equiv_drvr->driveResistance();
-      // Include delay of previous driver into equiv gate.
+    for (LibertyCell* swappable : swappable_cells) {
+      const LibertyCell* swappable_corner = swappable->cornerCell(lib_ap);
+      const LibertyPort* swappable_drvr
+          = swappable_corner->findLibertyPort(drvr_port_name);
+      const LibertyPort* swappable_input
+          = swappable_corner->findLibertyPort(in_port_name);
+      const float current_drive = swappable_drvr->driveResistance();
+      // Include delay of previous driver into swappable gate.
       const float current_delay
-          = resizer_->gateDelay(equiv_drvr, load_cap, dcalc_ap)
-            + prev_drive * equiv_input->capacitance();
+          = resizer_->gateDelay(swappable_drvr, load_cap, dcalc_ap)
+            + prev_drive * swappable_input->capacitance();
 
-      if (!resizer_->dontUse(equiv) && current_drive > drive
+      if (!resizer_->dontUse(swappable) && current_drive > drive
           && current_delay > delay
           && (current_delay - delay) * delay_margin < path_slack  // add margin
-          && meetsSizeCriteria(cell, equiv, match_size)) {
-        best_cell = equiv;
+          && meetsSizeCriteria(cell, swappable, match_size)) {
+        best_cell = swappable;
       }
     }
     if (best_cell != nullptr) {
diff --git a/src/rsz/src/RecoverPower.hh b/src/rsz/src/RecoverPower.hh
index 40b274d8152..4060d7ecfc2 100644
--- a/src/rsz/src/RecoverPower.hh
+++ b/src/rsz/src/RecoverPower.hh
@@ -87,7 +87,7 @@ class RecoverPower : public sta::dbStaState
   void init();
   Vertex* recoverPower(const PathRef& path, Slack path_slack);
   bool meetsSizeCriteria(const LibertyCell* cell,
-                         const LibertyCell* equiv,
+                         const LibertyCell* candidate,
                          bool match_size);
   bool downsizeDrvr(const PathRef* drvr_path,
                     int drvr_index,
diff --git a/src/rsz/src/RepairDesign.cc b/src/rsz/src/RepairDesign.cc
index 1806aec37b0..3c418c79608 100644
--- a/src/rsz/src/RepairDesign.cc
+++ b/src/rsz/src/RepairDesign.cc
@@ -1907,15 +1907,15 @@ LibertyCell* RepairDesign::findBufferUnderSlew(float max_slew, float load_cap)
 {
   LibertyCell* min_slew_buffer = resizer_->buffer_lowest_drive_;
   float min_slew = INF;
-  LibertyCellSeq* equiv_cells
-      = sta_->equivCells(resizer_->buffer_lowest_drive_);
-  if (equiv_cells) {
-    sort(equiv_cells,
+  LibertyCellSeq swappable_cells
+      = resizer_->getSwappableCells(resizer_->buffer_lowest_drive_);
+  if (!swappable_cells.empty()) {
+    sort(swappable_cells,
          [this](const LibertyCell* buffer1, const LibertyCell* buffer2) {
            return resizer_->bufferDriveResistance(buffer1)
                   > resizer_->bufferDriveResistance(buffer2);
          });
-    for (LibertyCell* buffer : *equiv_cells) {
+    for (LibertyCell* buffer : swappable_cells) {
       if (!resizer_->dontUse(buffer) && resizer_->isLinkCell(buffer)) {
         float slew = resizer_->bufferSlew(
             buffer, load_cap, resizer_->tgt_slew_dcalc_ap_);
diff --git a/src/rsz/src/RepairSetup.cc b/src/rsz/src/RepairSetup.cc
index d985b7ac8d4..3e1bee3cd4e 100644
--- a/src/rsz/src/RepairSetup.cc
+++ b/src/rsz/src/RepairSetup.cc
@@ -1116,41 +1116,44 @@ LibertyCell* RepairSetup::upsizeCell(LibertyPort* in_port,
 {
   const int lib_ap = dcalc_ap->libertyIndex();
   LibertyCell* cell = drvr_port->libertyCell();
-  LibertyCellSeq* equiv_cells = sta_->equivCells(cell);
-  if (equiv_cells) {
+  LibertyCellSeq swappable_cells = resizer_->getSwappableCells(cell);
+  if (!swappable_cells.empty()) {
     const char* in_port_name = in_port->name();
     const char* drvr_port_name = drvr_port->name();
-    sort(equiv_cells, [=](const LibertyCell* cell1, const LibertyCell* cell2) {
-      LibertyPort* port1
-          = cell1->findLibertyPort(drvr_port_name)->cornerPort(lib_ap);
-      LibertyPort* port2
-          = cell2->findLibertyPort(drvr_port_name)->cornerPort(lib_ap);
-      const float drive1 = port1->driveResistance();
-      const float drive2 = port2->driveResistance();
-      const ArcDelay intrinsic1 = port1->intrinsicDelay(this);
-      const ArcDelay intrinsic2 = port2->intrinsicDelay(this);
-      return drive1 > drive2
-             || ((drive1 == drive2 && intrinsic1 < intrinsic2)
-                 || (intrinsic1 == intrinsic2
-                     && port1->capacitance() < port2->capacitance()));
-    });
+    sort(swappable_cells,
+         [=](const LibertyCell* cell1, const LibertyCell* cell2) {
+           LibertyPort* port1
+               = cell1->findLibertyPort(drvr_port_name)->cornerPort(lib_ap);
+           LibertyPort* port2
+               = cell2->findLibertyPort(drvr_port_name)->cornerPort(lib_ap);
+           const float drive1 = port1->driveResistance();
+           const float drive2 = port2->driveResistance();
+           const ArcDelay intrinsic1 = port1->intrinsicDelay(this);
+           const ArcDelay intrinsic2 = port2->intrinsicDelay(this);
+           return drive1 > drive2
+                  || ((drive1 == drive2 && intrinsic1 < intrinsic2)
+                      || (intrinsic1 == intrinsic2
+                          && port1->capacitance() < port2->capacitance()));
+         });
     const float drive = drvr_port->cornerPort(lib_ap)->driveResistance();
     const float delay
         = resizer_->gateDelay(drvr_port, load_cap, resizer_->tgt_slew_dcalc_ap_)
           + prev_drive * in_port->cornerPort(lib_ap)->capacitance();
 
-    for (LibertyCell* equiv : *equiv_cells) {
-      LibertyCell* equiv_corner = equiv->cornerCell(lib_ap);
-      LibertyPort* equiv_drvr = equiv_corner->findLibertyPort(drvr_port_name);
-      LibertyPort* equiv_input = equiv_corner->findLibertyPort(in_port_name);
-      const float equiv_drive = equiv_drvr->driveResistance();
-      // Include delay of previous driver into equiv gate.
-      const float equiv_delay
-          = resizer_->gateDelay(equiv_drvr, load_cap, dcalc_ap)
-            + prev_drive * equiv_input->capacitance();
-      if (!resizer_->dontUse(equiv) && equiv_drive < drive
-          && equiv_delay < delay) {
-        return equiv;
+    for (LibertyCell* swappable : swappable_cells) {
+      LibertyCell* swappable_corner = swappable->cornerCell(lib_ap);
+      LibertyPort* swappable_drvr
+          = swappable_corner->findLibertyPort(drvr_port_name);
+      LibertyPort* swappable_input
+          = swappable_corner->findLibertyPort(in_port_name);
+      const float swappable_drive = swappable_drvr->driveResistance();
+      // Include delay of previous driver into swappable gate.
+      const float swappable_delay
+          = resizer_->gateDelay(swappable_drvr, load_cap, dcalc_ap)
+            + prev_drive * swappable_input->capacitance();
+      if (!resizer_->dontUse(swappable) && swappable_drive < drive
+          && swappable_delay < delay) {
+        return swappable;
       }
     }
   }
diff --git a/src/rsz/src/Resizer.cc b/src/rsz/src/Resizer.cc
index 5412c028458..ed46ae0ba6e 100644
--- a/src/rsz/src/Resizer.cc
+++ b/src/rsz/src/Resizer.cc
@@ -450,11 +450,8 @@ void Resizer::balanceBin(const vector<odb::dbInst*>& bin,
       }
       Instance* sta_inst = db_network_->dbToSta(inst);
       LibertyCell* cell = network_->libertyCell(sta_inst);
-      LibertyCellSeq* equiv_cells = sta_->equivCells(cell);
-      if (!equiv_cells) {
-        continue;
-      }
-      for (LibertyCell* target_cell : *equiv_cells) {
+      LibertyCellSeq swappable_cells = getSwappableCells(cell);
+      for (LibertyCell* target_cell : swappable_cells) {
         if (dontUse(target_cell)) {
           continue;
         }
@@ -857,7 +854,7 @@ LibertyCell* Resizer::halfDrivingPowerCell(Instance* inst)
 }
 LibertyCell* Resizer::halfDrivingPowerCell(LibertyCell* cell)
 {
-  return closestDriver(cell, sta_->equivCells(cell), 0.5);
+  return closestDriver(cell, getSwappableCells(cell), 0.5);
 }
 
 bool Resizer::isSingleOutputCombinational(Instance* inst) const
@@ -917,18 +914,17 @@ std::vector<sta::LibertyPort*> Resizer::libraryPins(LibertyCell* cell) const
 }
 
 LibertyCell* Resizer::closestDriver(LibertyCell* cell,
-                                    LibertyCellSeq* candidates,
+                                    const LibertyCellSeq& candidates,
                                     float scale)
 {
   LibertyCell* closest = nullptr;
-  if (candidates == nullptr || candidates->empty()
-      || !isSingleOutputCombinational(cell)) {
+  if (candidates.empty() || !isSingleOutputCombinational(cell)) {
     return nullptr;
   }
   const auto output_pin = libraryOutputPins(cell)[0];
   const auto current_limit = scale * maxLoad(output_pin->cell());
   auto diff = sta::INF;
-  for (auto& cand : *candidates) {
+  for (auto& cand : candidates) {
     if (dontUse(cand)) {
       continue;
     }
@@ -1015,6 +1011,32 @@ void Resizer::resizePreamble()
   findTargetLoads();
 }
 
+// Filter equivalent cells based on the following liberty attributes:
+// - Footprint (Optional - Honored if enforced by user): Cells with the
+//   same footprint have the same layout boundary.
+LibertyCellSeq Resizer::getSwappableCells(LibertyCell* source_cell)
+{
+  LibertyCellSeq swappable_cells;
+  LibertyCellSeq* equiv_cells = sta_->equivCells(source_cell);
+
+  if (equiv_cells) {
+    for (LibertyCell* equiv_cell : *equiv_cells) {
+      if (match_cell_footprint_ && !footprintsMatch(source_cell, equiv_cell)) {
+        continue;
+      }
+
+      swappable_cells.push_back(equiv_cell);
+    }
+  }
+
+  return swappable_cells;
+}
+
+bool Resizer::footprintsMatch(LibertyCell* source, LibertyCell* target)
+{
+  return sta::stringEqIf(source->footprint(), target->footprint());
+}
+
 void Resizer::checkLibertyForAllCorners()
 {
   for (Corner* corner : *sta_->corners()) {
@@ -1115,8 +1137,8 @@ LibertyCell* Resizer::findTargetCell(LibertyCell* cell,
                                      bool revisiting_inst)
 {
   LibertyCell* best_cell = cell;
-  LibertyCellSeq* equiv_cells = sta_->equivCells(cell);
-  if (equiv_cells) {
+  LibertyCellSeq swappable_cells = getSwappableCells(cell);
+  if (!swappable_cells.empty()) {
     bool is_buf_inv = cell->isBuffer() || cell->isInverter();
     float target_load = (*target_load_map_)[cell];
     float best_load = target_load;
@@ -1132,7 +1154,7 @@ LibertyCell* Resizer::findTargetCell(LibertyCell* cell,
                units_->capacitanceUnit()->asString(load_cap),
                best_dist,
                delayAsString(best_delay, sta_, 3));
-    for (LibertyCell* target_cell : *equiv_cells) {
+    for (LibertyCell* target_cell : swappable_cells) {
       if (!dontUse(target_cell) && isLinkCell(target_cell)) {
         float target_load = (*target_load_map_)[target_cell];
         float delay = is_buf_inv ? bufferDelay(
@@ -2668,8 +2690,11 @@ void Resizer::repairDesign(double max_wire_length,
                            double slew_margin,
                            double cap_margin,
                            double buffer_gain,
+                           bool match_cell_footprint,
                            bool verbose)
 {
+  utl::SetAndRestore<bool> set_match_footprint(match_cell_footprint_,
+                                               match_cell_footprint);
   resizePreamble();
   if (parasitics_src_ == ParasiticsSrc::global_routing) {
     opendp_->initMacrosAndGrid();
@@ -2814,6 +2839,7 @@ void Resizer::cloneClkInverter(Instance* inv)
 void Resizer::repairSetup(double setup_margin,
                           double repair_tns_end_percent,
                           int max_passes,
+                          bool match_cell_footprint,
                           bool verbose,
                           bool skip_pin_swap,
                           bool skip_gate_cloning,
@@ -2821,6 +2847,8 @@ void Resizer::repairSetup(double setup_margin,
                           bool skip_buffer_removal,
                           bool skip_last_gasp)
 {
+  utl::SetAndRestore<bool> set_match_footprint(match_cell_footprint_,
+                                               match_cell_footprint);
   resizePreamble();
   if (parasitics_src_ == ParasiticsSrc::global_routing) {
     opendp_->initMacrosAndGrid();
@@ -2863,8 +2891,11 @@ void Resizer::repairHold(
     // Max buffer count as percent of design instance count.
     float max_buffer_percent,
     int max_passes,
+    bool match_cell_footprint,
     bool verbose)
 {
+  utl::SetAndRestore<bool> set_match_footprint(match_cell_footprint_,
+                                               match_cell_footprint);
   // Some technologies such as nangate45 don't have delay cells. Hence,
   // until we have a better approach, it's better to consider clock buffers
   // for hold violation repairing as these buffers' delay may be slighty
@@ -2916,8 +2947,11 @@ int Resizer::holdBufferCount() const
 }
 
 ////////////////////////////////////////////////////////////////
-void Resizer::recoverPower(float recover_power_percent)
+void Resizer::recoverPower(float recover_power_percent,
+                           bool match_cell_footprint)
 {
+  utl::SetAndRestore<bool> set_match_footprint(match_cell_footprint_,
+                                               match_cell_footprint);
   resizePreamble();
   if (parasitics_src_ == ParasiticsSrc::global_routing) {
     opendp_->initMacrosAndGrid();
diff --git a/src/rsz/src/Resizer.i b/src/rsz/src/Resizer.i
index a40f974d263..5240fcc06e3 100644
--- a/src/rsz/src/Resizer.i
+++ b/src/rsz/src/Resizer.i
@@ -36,6 +36,7 @@
 %{
 
 #include <cstdint>
+#include <fstream>
 
 #include "sta/Liberty.hh"
 #include "sta/Network.hh"
@@ -542,11 +543,17 @@ repair_design_cmd(double max_length,
                   double slew_margin,
                   double cap_margin,
                   double buffer_gain,
+                  bool match_cell_footprint,
                   bool verbose)
 {
   ensureLinked();
   Resizer *resizer = getResizer();
-  resizer->repairDesign(max_length, slew_margin, cap_margin, buffer_gain, verbose);
+  resizer->repairDesign(max_length,
+                        slew_margin,
+                        cap_margin,
+                        buffer_gain,
+                        match_cell_footprint,
+                        verbose);
 }
 
 int
@@ -587,7 +594,7 @@ void
 repair_setup(double setup_margin,
              double repair_tns_end_percent,
              int max_passes,
-             bool verbose,
+             bool match_cell_footprint, bool verbose,
              bool skip_pin_swap, bool skip_gate_cloning,
              bool skip_buffering, bool skip_buffer_removal,
              bool skip_last_gasp)
@@ -595,7 +602,7 @@ repair_setup(double setup_margin,
   ensureLinked();
   Resizer *resizer = getResizer();
   resizer->repairSetup(setup_margin, repair_tns_end_percent,
-                       max_passes, verbose,
+                       max_passes, match_cell_footprint, verbose,
                        skip_pin_swap, skip_gate_cloning,
                        skip_buffering, skip_buffer_removal,
                        skip_last_gasp);
@@ -623,6 +630,7 @@ repair_hold(double setup_margin,
             bool allow_setup_violations,
             float max_buffer_percent,
             int max_passes,
+            bool match_cell_footprint,
             bool verbose)
 {
   ensureLinked();
@@ -630,7 +638,7 @@ repair_hold(double setup_margin,
   resizer->repairHold(setup_margin, hold_margin,
                       allow_setup_violations,
                       max_buffer_percent, max_passes,
-                      verbose);
+                      match_cell_footprint, verbose);
 }
 
 void
@@ -657,11 +665,11 @@ hold_buffer_count()
 
 ////////////////////////////////////////////////////////////////
 void
-recover_power(float recover_power_percent)
+recover_power(float recover_power_percent, bool match_cell_footprint)
 {
   ensureLinked();
   Resizer *resizer = getResizer();
-  resizer->recoverPower(recover_power_percent);
+  resizer->recoverPower(recover_power_percent, match_cell_footprint);
 }
 
 ////////////////////////////////////////////////////////////////
diff --git a/src/rsz/src/Resizer.tcl b/src/rsz/src/Resizer.tcl
index 1ff42423d53..19b765a95f9 100644
--- a/src/rsz/src/Resizer.tcl
+++ b/src/rsz/src/Resizer.tcl
@@ -438,12 +438,13 @@ sta::define_cmd_args "repair_design" {[-max_wire_length max_wire_length] \
                                       [-slew_margin slack_margin] \
                                       [-cap_margin cap_margin] \
                                       [-buffer_gain gain] \
+                                      [-match_cell_footprint] \
                                       [-verbose]}
 
 proc repair_design { args } {
   sta::parse_key_args "repair_design" args \
     keys {-max_wire_length -max_utilization -slew_margin -cap_margin -buffer_gain} \
-    flags {-verbose}
+    flags {-match_cell_footprint -verbose}
 
   set max_wire_length [rsz::parse_max_wire_length keys]
   set slew_margin [rsz::parse_percent_margin_arg "-slew_margin" keys]
@@ -458,8 +459,10 @@ proc repair_design { args } {
   sta::check_argc_eq0 "repair_design" $args
   rsz::check_parasitics
   set max_wire_length [rsz::check_max_wire_length $max_wire_length]
+  set match_cell_footprint [info exists flags(-match_cell_footprint)]
   set verbose [info exists flags(-verbose)]
-  rsz::repair_design_cmd $max_wire_length $slew_margin $cap_margin $buffer_gain $verbose
+  rsz::repair_design_cmd $max_wire_length $slew_margin $cap_margin \
+    $buffer_gain $match_cell_footprint $verbose
 }
 
 sta::define_cmd_args "repair_clock_nets" {[-max_wire_length max_wire_length]}
@@ -536,6 +539,7 @@ sta::define_cmd_args "repair_timing" {[-setup] [-hold]\
                                         [-max_passes passes]\
                                         [-max_buffer_percent buffer_percent]\
                                         [-max_utilization util] \
+                                        [-match_cell_footprint] \
                                         [-verbose]}
 
 proc repair_timing { args } {
@@ -544,7 +548,8 @@ proc repair_timing { args } {
             -libraries -max_utilization -max_buffer_percent \
             -recover_power -repair_tns -max_passes} \
     flags {-setup -hold -allow_setup_violations -skip_pin_swap -skip_gate_cloning \
-           -skip_buffering -skip_buffer_removal -skip_last_gasp -verbose}
+           -skip_buffering -skip_buffer_removal -skip_last_gasp -match_cell_footprint \
+           -verbose}
 
   set setup [info exists flags(-setup)]
   set hold [info exists flags(-hold)]
@@ -606,21 +611,24 @@ proc repair_timing { args } {
   if { [info exists keys(-max_passes)] } {
     set max_passes $keys(-max_passes)
   }
+
+  set match_cell_footprint [info exists flags(-match_cell_footprint)]
+
   sta::check_argc_eq0 "repair_timing" $args
   rsz::check_parasitics
   if { $recover_power_percent >= 0 } {
-    rsz::recover_power $recover_power_percent
+    rsz::recover_power $recover_power_percent $match_cell_footprint
   } else {
     if { $setup } {
       rsz::repair_setup $setup_margin $repair_tns_end_percent $max_passes \
-        $verbose \
+        $match_cell_footprint $verbose \
         $skip_pin_swap $skip_gate_cloning $skip_buffering \
         $skip_buffer_removal $skip_last_gasp
     }
     if { $hold } {
       rsz::repair_hold $setup_margin $hold_margin \
         $allow_setup_violations $max_buffer_percent $max_passes \
-        $verbose
+        $match_cell_footprint $verbose
     }
   }
 }
@@ -752,7 +760,7 @@ proc check_corner_wire_caps { } {
   set have_rc 1
   foreach corner [sta::corners] {
     if { [rsz::wire_signal_capacitance $corner] == 0.0 } {
-      utl::warn RSZ 14 "wire capacitance for corner [$corner name] is zero.\
+      utl::warn RSZ 18 "wire capacitance for corner [$corner name] is zero.\
         Use the set_wire_rc command to set wire resistance and capacitance."
       set have_rc 0
     }
diff --git a/src/rsz/test/repair_wire3.ok b/src/rsz/test/repair_wire3.ok
index a061793b518..0c8d82a07a4 100644
--- a/src/rsz/test/repair_wire3.ok
+++ b/src/rsz/test/repair_wire3.ok
@@ -8,7 +8,7 @@
 [WARNING RSZ-0011] Signal/clock vertical wire resistance is 0.
 [WARNING RSZ-0012] Signal/clock horizontal wire capacitance is 0.
 [WARNING RSZ-0013] Signal/clock vertical wire capacitance is 0.
-[WARNING RSZ-0014] wire capacitance for corner default is zero. Use the set_wire_rc command to set wire resistance and capacitance.
+[WARNING RSZ-0018] wire capacitance for corner default is zero. Use the set_wire_rc command to set wire resistance and capacitance.
 Driver    length delay
 u2/Z manhtn 1998.8 steiner 1998.8 0.00
 u3/Z manhtn 1.3 steiner 1.3 0.00
diff --git a/test/aes_sky130hs.metrics b/test/aes_sky130hs.metrics
index 202755d1020..d12b07d3daa 100644
--- a/test/aes_sky130hs.metrics
+++ b/test/aes_sky130hs.metrics
@@ -29,73 +29,111 @@
 	"DPL::design_area": "361737",
 	"route__net": 18788,
 	"route__net__special": 2,
-	"grt__antenna_diodes_count": 1270,
+	"grt__antenna_diodes_count": 1249,
 	"grt__antenna__violating__nets": 0,
 	"grt__antenna__violating__pins": 0,
 	"GRT::ANT::errors": "0",
 	"route__net": 18788,
 	"route__net__special": 2,
-	"route__drc_errors__iter:1": 6522,
-	"route__wirelength__iter:1": 1831609,
-	"route__drc_errors__iter:2": 1287,
-	"route__wirelength__iter:2": 1826279,
-	"route__drc_errors__iter:3": 1015,
-	"route__wirelength__iter:3": 1824833,
-	"route__drc_errors__iter:4": 18,
-	"route__wirelength__iter:4": 1824955,
+	"route__drc_errors__iter:1": 5730,
+	"route__wirelength__iter:1": 1834250,
+	"route__drc_errors__iter:2": 1340,
+	"route__wirelength__iter:2": 1824672,
+	"route__drc_errors__iter:3": 947,
+	"route__wirelength__iter:3": 1822238,
+	"route__drc_errors__iter:4": 26,
+	"route__wirelength__iter:4": 1822258,
 	"route__drc_errors__iter:5": 0,
-	"route__wirelength__iter:5": 1824940,
+	"route__wirelength__iter:5": 1822243,
 	"route__drc_errors": 0,
-	"route__wirelength": 1824940,
-	"route__vias": 160442,
-	"route__vias__singlecut": 160442,
+	"route__wirelength": 1822243,
+	"route__vias": 161849,
+	"route__vias__singlecut": 161849,
 	"route__vias__multicut": 0,
 	"DRT::drv": "0",
-	"drt__repair_antennas__pre_repair__antenna__violating__nets": 31,
-	"drt__repair_antennas__pre_repair__antenna__violating__pins": 32,
-	"drt__repair_antennas__iter_0__antenna_diodes_count": 1302,
-	"drt__repair_antennas__iter_0__route__drc_errors__iter:1": 234,
-	"drt__repair_antennas__iter_0__route__wirelength__iter:1": 1825214,
-	"drt__repair_antennas__iter_0__route__drc_errors__iter:2": 22,
-	"drt__repair_antennas__iter_0__route__wirelength__iter:2": 1825187,
-	"drt__repair_antennas__iter_0__route__drc_errors__iter:3": 25,
-	"drt__repair_antennas__iter_0__route__wirelength__iter:3": 1825178,
-	"drt__repair_antennas__iter_0__route__drc_errors__iter:4": 0,
-	"drt__repair_antennas__iter_0__route__wirelength__iter:4": 1825163,
+	"drt__repair_antennas__pre_repair__antenna__violating__nets": 36,
+	"drt__repair_antennas__pre_repair__antenna__violating__pins": 37,
+	"drt__repair_antennas__iter_0__antenna_diodes_count": 1300,
+	"drt__repair_antennas__iter_0__route__drc_errors__iter:1": 233,
+	"drt__repair_antennas__iter_0__route__wirelength__iter:1": 1822600,
+	"drt__repair_antennas__iter_0__route__drc_errors__iter:2": 20,
+	"drt__repair_antennas__iter_0__route__wirelength__iter:2": 1822508,
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diff --git a/test/aes_sky130hs.metrics_limits b/test/aes_sky130hs.metrics_limits
index eb474f703d1..0a6a60e85fd 100644
--- a/test/aes_sky130hs.metrics_limits
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diff --git a/test/gcd_sky130hd.metrics b/test/gcd_sky130hd.metrics
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diff --git a/test/gcd_sky130hd.metrics_limits b/test/gcd_sky130hd.metrics_limits
index dadeda56fb5..087d7d382e6 100644
--- a/test/gcd_sky130hd.metrics_limits
+++ b/test/gcd_sky130hd.metrics_limits
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diff --git a/test/gcd_sky130hs.metrics b/test/gcd_sky130hs.metrics
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diff --git a/test/gcd_sky130hs.metrics_limits b/test/gcd_sky130hs.metrics_limits
index cd32bc70d4c..ffa84577166 100644
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+ ,"DRT::worst_slack_min" : "-0.07533384373987964"
+ ,"DRT::worst_slack_max" : "-0.4293022083779875"
+ ,"DRT::tns_max" : "-6.635259126727411"
+ ,"DRT::clock_skew" : "0.015166668350504968"
  ,"DRT::max_slew_slack" : "0"
  ,"DRT::max_capacitance_slack" : "0"
  ,"DRT::max_fanout_slack" : "0"
diff --git a/test/helpers.py b/test/helpers.py
index e84f06c1f75..8cf60a5f2f5 100644
--- a/test/helpers.py
+++ b/test/helpers.py
@@ -66,17 +66,11 @@ def diff_files(file1, file2, ignore=None):
 # Finished DEF file
 utl.suppress_message(utl.ODB, 134)
 
-# suppress PPL info messages
-utl.suppress_message(utl.PPL, 41)
-utl.suppress_message(utl.PPL, 48)
-utl.suppress_message(utl.PPL, 49)
-utl.suppress_message(utl.PPL, 60)
-
 # suppress tap info messages
 utl.suppress_message(utl.TAP, 100)
 utl.suppress_message(utl.TAP, 101)
 
-# suppress par messages with files' names
+# suppress par messages with filenames
 utl.suppress_message(utl.PAR, 6)
 utl.suppress_message(utl.PAR, 38)
 
diff --git a/test/helpers.tcl b/test/helpers.tcl
index 34d0a9aa782..9dca284176d 100644
--- a/test/helpers.tcl
+++ b/test/helpers.tcl
@@ -203,18 +203,11 @@ suppress_message ODB 127
 # Finished DEF file
 suppress_message ODB 134
 
-# suppress ppl info messages. The ones defined in tcl can never
-# match between tcl and Python
-suppress_message PPL 41
-suppress_message PPL 48
-suppress_message PPL 49
-suppress_message PPL 60
-
 # suppress tap info messages
 suppress_message TAP 100
 suppress_message TAP 101
 
-# suppress par messages with files' names
+# suppress par messages with filenames
 suppress_message PAR 6
 suppress_message PAR 38
 
diff --git a/test/ibex_sky130hd.metrics b/test/ibex_sky130hd.metrics
index 094cb17603a..2d42995ee0a 100644
--- a/test/ibex_sky130hd.metrics
+++ b/test/ibex_sky130hd.metrics
@@ -35,55 +35,59 @@
 	"GRT::ANT::errors": "0",
 	"route__net": 15575,
 	"route__net__special": 2,
-	"route__drc_errors__iter:1": 6531,
-	"route__wirelength__iter:1": 968384,
-	"route__drc_errors__iter:2": 2156,
-	"route__wirelength__iter:2": 962008,
-	"route__drc_errors__iter:3": 1657,
-	"route__wirelength__iter:3": 960173,
-	"route__drc_errors__iter:4": 201,
-	"route__wirelength__iter:4": 960228,
-	"route__drc_errors__iter:5": 48,
-	"route__wirelength__iter:5": 960254,
-	"route__drc_errors__iter:6": 10,
-	"route__wirelength__iter:6": 960250,
-	"route__drc_errors__iter:7": 6,
-	"route__wirelength__iter:7": 960250,
+	"route__drc_errors__iter:1": 6329,
+	"route__wirelength__iter:1": 964401,
+	"route__drc_errors__iter:2": 1918,
+	"route__wirelength__iter:2": 957933,
+	"route__drc_errors__iter:3": 1428,
+	"route__wirelength__iter:3": 955938,
+	"route__drc_errors__iter:4": 250,
+	"route__wirelength__iter:4": 956071,
+	"route__drc_errors__iter:5": 81,
+	"route__wirelength__iter:5": 956043,
+	"route__drc_errors__iter:6": 19,
+	"route__wirelength__iter:6": 956037,
+	"route__drc_errors__iter:7": 7,
+	"route__wirelength__iter:7": 956041,
 	"route__drc_errors__iter:8": 0,
-	"route__wirelength__iter:8": 960229,
+	"route__wirelength__iter:8": 956042,
 	"route__drc_errors": 0,
-	"route__wirelength": 960229,
-	"route__vias": 131663,
-	"route__vias__singlecut": 131663,
+	"route__wirelength": 956042,
+	"route__vias": 132519,
+	"route__vias__singlecut": 132519,
 	"route__vias__multicut": 0,
 	"DRT::drv": "0",
-	"drt__repair_antennas__pre_repair__antenna__violating__nets": 31,
-	"drt__repair_antennas__pre_repair__antenna__violating__pins": 32,
-	"drt__repair_antennas__iter_0__antenna_diodes_count": 413,
-	"drt__repair_antennas__iter_0__route__drc_errors__iter:1": 591,
-	"drt__repair_antennas__iter_0__route__wirelength__iter:1": 959915,
-	"drt__repair_antennas__iter_0__route__drc_errors__iter:2": 133,
-	"drt__repair_antennas__iter_0__route__wirelength__iter:2": 959797,
-	"drt__repair_antennas__iter_0__route__drc_errors__iter:3": 83,
-	"drt__repair_antennas__iter_0__route__wirelength__iter:3": 959781,
-	"drt__repair_antennas__iter_0__route__drc_errors__iter:4": 4,
-	"drt__repair_antennas__iter_0__route__wirelength__iter:4": 959750,
-	"drt__repair_antennas__iter_0__route__drc_errors__iter:5": 0,
-	"drt__repair_antennas__iter_0__route__wirelength__iter:5": 959747,
+	"drt__repair_antennas__pre_repair__antenna__violating__nets": 41,
+	"drt__repair_antennas__pre_repair__antenna__violating__pins": 48,
+	"drt__repair_antennas__iter_0__antenna_diodes_count": 442,
+	"drt__repair_antennas__iter_0__route__drc_errors__iter:1": 749,
+	"drt__repair_antennas__iter_0__route__wirelength__iter:1": 955989,
+	"drt__repair_antennas__iter_0__route__drc_errors__iter:2": 162,
+	"drt__repair_antennas__iter_0__route__wirelength__iter:2": 955776,
+	"drt__repair_antennas__iter_0__route__drc_errors__iter:3": 131,
+	"drt__repair_antennas__iter_0__route__wirelength__iter:3": 955747,
+	"drt__repair_antennas__iter_0__route__drc_errors__iter:4": 6,
+	"drt__repair_antennas__iter_0__route__wirelength__iter:4": 955720,
+	"drt__repair_antennas__iter_0__route__drc_errors__iter:5": 4,
+	"drt__repair_antennas__iter_0__route__wirelength__iter:5": 955720,
+	"drt__repair_antennas__iter_0__route__drc_errors__iter:6": 0,
+	"drt__repair_antennas__iter_0__route__wirelength__iter:6": 955727,
 	"drt__repair_antennas__iter_0__route__drc_errors": 0,
-	"drt__repair_antennas__iter_0__route__wirelength": 959747,
-	"drt__repair_antennas__iter_0__route__vias": 131807,
-	"drt__repair_antennas__iter_0__route__vias__singlecut": 131807,
+	"drt__repair_antennas__iter_0__route__wirelength": 955727,
+	"drt__repair_antennas__iter_0__route__vias": 132846,
+	"drt__repair_antennas__iter_0__route__vias__singlecut": 132846,
 	"drt__repair_antennas__iter_0__route__vias__multicut": 0,
-	"drt__repair_antennas__iter_0__antenna__violating__nets": 1,
-	"drt__repair_antennas__iter_0__antenna__violating__pins": 2,
-	"drt__repair_antennas__iter_1__antenna_diodes_count": 415,
-	"drt__repair_antennas__iter_1__route__drc_errors__iter:1": 0,
-	"drt__repair_antennas__iter_1__route__wirelength__iter:1": 959770,
+	"drt__repair_antennas__iter_0__antenna__violating__nets": 2,
+	"drt__repair_antennas__iter_0__antenna__violating__pins": 3,
+	"drt__repair_antennas__iter_1__antenna_diodes_count": 445,
+	"drt__repair_antennas__iter_1__route__drc_errors__iter:1": 20,
+	"drt__repair_antennas__iter_1__route__wirelength__iter:1": 955739,
+	"drt__repair_antennas__iter_1__route__drc_errors__iter:2": 0,
+	"drt__repair_antennas__iter_1__route__wirelength__iter:2": 955745,
 	"drt__repair_antennas__iter_1__route__drc_errors": 0,
-	"drt__repair_antennas__iter_1__route__wirelength": 959770,
-	"drt__repair_antennas__iter_1__route__vias": 131811,
-	"drt__repair_antennas__iter_1__route__vias__singlecut": 131811,
+	"drt__repair_antennas__iter_1__route__wirelength": 955745,
+	"drt__repair_antennas__iter_1__route__vias": 132855,
+	"drt__repair_antennas__iter_1__route__vias__singlecut": 132855,
 	"drt__repair_antennas__iter_1__route__vias__multicut": 0,
 	"drt__repair_antennas__iter_1__antenna__violating__nets": 0,
 	"drt__repair_antennas__iter_1__antenna__violating__pins": 0,
@@ -93,13 +97,13 @@
 	"design__violations": 0,
 	"timing__drv__floating__nets": 0,
 	"timing__drv__floating__pins": 0,
-	"DRT::worst_slack_min": "-0.44916938106952004",
-	"DRT::worst_slack_max": "-2.9066971874386254",
-	"DRT::tns_max": "-179.6365205209744",
-	"DRT::clock_skew": "2.6177274422381474",
-	"DRT::max_slew_slack": "-1.3924195120731988",
+	"DRT::worst_slack_min": "-0.5065912277501585",
+	"DRT::worst_slack_max": "-3.0107419631785644",
+	"DRT::tns_max": "-186.86758624962098",
+	"DRT::clock_skew": "2.6634939452320303",
+	"DRT::max_slew_slack": "-3.487891455491384",
 	"DRT::max_fanout_slack": "100.0",
-	"DRT::max_capacitance_slack": "-2.8179279056679203",
+	"DRT::max_capacitance_slack": "0.1676710884303128",
 	"DRT::clock_period": "15.155000",
 	"flow__warnings__count": 92,
 	"flow__errors__count": 0
diff --git a/test/ibex_sky130hd.metrics_limits b/test/ibex_sky130hd.metrics_limits
index 1b3050d13a6..185e5444f13 100644
--- a/test/ibex_sky130hd.metrics_limits
+++ b/test/ibex_sky130hd.metrics_limits
@@ -12,12 +12,12 @@
  ,"RSZ::hold_buffer_count" : "387"
  ,"GRT::ANT::errors" : "0"
  ,"DRT::drv" : "0"
- ,"DRT::worst_slack_min" : "-1.9646693810695202"
- ,"DRT::worst_slack_max" : "-4.422197187438625"
- ,"DRT::tns_max" : "-2558.365320520975"
- ,"DRT::clock_skew" : "3.1412729306857767"
- ,"DRT::max_slew_slack" : "-1.6709034144878385"
- ,"DRT::max_capacitance_slack" : "-3.3815134868015044"
+ ,"DRT::worst_slack_min" : "-2.022091227750159"
+ ,"DRT::worst_slack_max" : "-4.526241963178564"
+ ,"DRT::tns_max" : "-2565.5963862496214"
+ ,"DRT::clock_skew" : "3.196192734278436"
+ ,"DRT::max_slew_slack" : "-4.185469746589661"
+ ,"DRT::max_capacitance_slack" : "0"
  ,"DRT::max_fanout_slack" : "0"
  ,"DRT::clock_period" : "15.155"
  ,"DRT::ANT::errors" : "0"
diff --git a/test/ibex_sky130hs.metrics b/test/ibex_sky130hs.metrics
index 7fe07981888..398aa13d84a 100644
--- a/test/ibex_sky130hs.metrics
+++ b/test/ibex_sky130hs.metrics
@@ -35,61 +35,61 @@
 	"GRT::ANT::errors": "1",
 	"route__net": 14571,
 	"route__net__special": 2,
-	"route__drc_errors__iter:1": 4657,
-	"route__wirelength__iter:1": 978415,
-	"route__drc_errors__iter:2": 806,
-	"route__wirelength__iter:2": 973971,
-	"route__drc_errors__iter:3": 536,
-	"route__wirelength__iter:3": 973171,
-	"route__drc_errors__iter:4": 18,
-	"route__wirelength__iter:4": 973088,
+	"route__drc_errors__iter:1": 4275,
+	"route__wirelength__iter:1": 972504,
+	"route__drc_errors__iter:2": 721,
+	"route__wirelength__iter:2": 967700,
+	"route__drc_errors__iter:3": 498,
+	"route__wirelength__iter:3": 966644,
+	"route__drc_errors__iter:4": 19,
+	"route__wirelength__iter:4": 966605,
 	"route__drc_errors__iter:5": 0,
-	"route__wirelength__iter:5": 973066,
+	"route__wirelength__iter:5": 966566,
 	"route__drc_errors": 0,
-	"route__wirelength": 973066,
-	"route__vias": 119473,
-	"route__vias__singlecut": 119473,
+	"route__wirelength": 966566,
+	"route__vias": 120518,
+	"route__vias__singlecut": 120518,
 	"route__vias__multicut": 0,
 	"DRT::drv": "0",
-	"drt__repair_antennas__pre_repair__antenna__violating__nets": 15,
-	"drt__repair_antennas__pre_repair__antenna__violating__pins": 15,
-	"drt__repair_antennas__iter_0__antenna_diodes_count": 181,
-	"drt__repair_antennas__iter_0__route__drc_errors__iter:1": 160,
-	"drt__repair_antennas__iter_0__route__wirelength__iter:1": 973110,
-	"drt__repair_antennas__iter_0__route__drc_errors__iter:2": 25,
-	"drt__repair_antennas__iter_0__route__wirelength__iter:2": 973092,
-	"drt__repair_antennas__iter_0__route__drc_errors__iter:3": 20,
-	"drt__repair_antennas__iter_0__route__wirelength__iter:3": 973073,
+	"drt__repair_antennas__pre_repair__antenna__violating__nets": 13,
+	"drt__repair_antennas__pre_repair__antenna__violating__pins": 14,
+	"drt__repair_antennas__iter_0__antenna_diodes_count": 180,
+	"drt__repair_antennas__iter_0__route__drc_errors__iter:1": 119,
+	"drt__repair_antennas__iter_0__route__wirelength__iter:1": 966567,
+	"drt__repair_antennas__iter_0__route__drc_errors__iter:2": 23,
+	"drt__repair_antennas__iter_0__route__wirelength__iter:2": 966526,
+	"drt__repair_antennas__iter_0__route__drc_errors__iter:3": 19,
+	"drt__repair_antennas__iter_0__route__wirelength__iter:3": 966518,
 	"drt__repair_antennas__iter_0__route__drc_errors__iter:4": 0,
-	"drt__repair_antennas__iter_0__route__wirelength__iter:4": 973099,
+	"drt__repair_antennas__iter_0__route__wirelength__iter:4": 966510,
 	"drt__repair_antennas__iter_0__route__drc_errors": 0,
-	"drt__repair_antennas__iter_0__route__wirelength": 973099,
-	"drt__repair_antennas__iter_0__route__vias": 119508,
-	"drt__repair_antennas__iter_0__route__vias__singlecut": 119508,
+	"drt__repair_antennas__iter_0__route__wirelength": 966510,
+	"drt__repair_antennas__iter_0__route__vias": 120560,
+	"drt__repair_antennas__iter_0__route__vias__singlecut": 120560,
 	"drt__repair_antennas__iter_0__route__vias__multicut": 0,
 	"drt__repair_antennas__iter_0__antenna__violating__nets": 1,
 	"drt__repair_antennas__iter_0__antenna__violating__pins": 2,
-	"drt__repair_antennas__iter_1__antenna_diodes_count": 183,
-	"drt__repair_antennas__iter_1__route__drc_errors__iter:1": 8,
-	"drt__repair_antennas__iter_1__route__wirelength__iter:1": 973127,
+	"drt__repair_antennas__iter_1__antenna_diodes_count": 182,
+	"drt__repair_antennas__iter_1__route__drc_errors__iter:1": 4,
+	"drt__repair_antennas__iter_1__route__wirelength__iter:1": 966543,
 	"drt__repair_antennas__iter_1__route__drc_errors__iter:2": 0,
-	"drt__repair_antennas__iter_1__route__wirelength__iter:2": 973119,
+	"drt__repair_antennas__iter_1__route__wirelength__iter:2": 966530,
 	"drt__repair_antennas__iter_1__route__drc_errors": 0,
-	"drt__repair_antennas__iter_1__route__wirelength": 973119,
-	"drt__repair_antennas__iter_1__route__vias": 119515,
-	"drt__repair_antennas__iter_1__route__vias__singlecut": 119515,
+	"drt__repair_antennas__iter_1__route__wirelength": 966530,
+	"drt__repair_antennas__iter_1__route__vias": 120567,
+	"drt__repair_antennas__iter_1__route__vias__singlecut": 120567,
 	"drt__repair_antennas__iter_1__route__vias__multicut": 0,
 	"drt__repair_antennas__iter_1__antenna__violating__nets": 1,
 	"drt__repair_antennas__iter_1__antenna__violating__pins": 1,
-	"drt__repair_antennas__iter_2__antenna_diodes_count": 184,
-	"drt__repair_antennas__iter_2__route__drc_errors__iter:1": 8,
-	"drt__repair_antennas__iter_2__route__wirelength__iter:1": 973136,
+	"drt__repair_antennas__iter_2__antenna_diodes_count": 183,
+	"drt__repair_antennas__iter_2__route__drc_errors__iter:1": 4,
+	"drt__repair_antennas__iter_2__route__wirelength__iter:1": 966538,
 	"drt__repair_antennas__iter_2__route__drc_errors__iter:2": 0,
-	"drt__repair_antennas__iter_2__route__wirelength__iter:2": 973128,
+	"drt__repair_antennas__iter_2__route__wirelength__iter:2": 966536,
 	"drt__repair_antennas__iter_2__route__drc_errors": 0,
-	"drt__repair_antennas__iter_2__route__wirelength": 973128,
-	"drt__repair_antennas__iter_2__route__vias": 119520,
-	"drt__repair_antennas__iter_2__route__vias__singlecut": 119520,
+	"drt__repair_antennas__iter_2__route__wirelength": 966536,
+	"drt__repair_antennas__iter_2__route__vias": 120570,
+	"drt__repair_antennas__iter_2__route__vias__singlecut": 120570,
 	"drt__repair_antennas__iter_2__route__vias__multicut": 0,
 	"drt__repair_antennas__iter_2__antenna__violating__nets": 0,
 	"drt__repair_antennas__iter_2__antenna__violating__pins": 0,
@@ -99,13 +99,13 @@
 	"design__violations": 0,
 	"timing__drv__floating__nets": 0,
 	"timing__drv__floating__pins": 0,
-	"DRT::worst_slack_min": "-0.3102131972436714",
-	"DRT::worst_slack_max": "-0.5673790486920518",
-	"DRT::tns_max": "-24.249946737048887",
-	"DRT::clock_skew": "1.9754953787520404",
-	"DRT::max_slew_slack": "-31.294924020767212",
+	"DRT::worst_slack_min": "-0.3099010025203174",
+	"DRT::worst_slack_max": "-0.5958460560269624",
+	"DRT::tns_max": "-23.02643474403086",
+	"DRT::clock_skew": "1.9721744795468603",
+	"DRT::max_slew_slack": "-29.968363046646118",
 	"DRT::max_fanout_slack": "100.0",
-	"DRT::max_capacitance_slack": "-35.072557432280306",
+	"DRT::max_capacitance_slack": "-33.650917265418705",
 	"DRT::clock_period": "11.290000",
 	"flow__warnings__count": 49,
 	"flow__errors__count": 0
diff --git a/test/ibex_sky130hs.metrics_limits b/test/ibex_sky130hs.metrics_limits
index 8a71f74ab5e..3ccd598ac6d 100644
--- a/test/ibex_sky130hs.metrics_limits
+++ b/test/ibex_sky130hs.metrics_limits
@@ -12,12 +12,12 @@
  ,"RSZ::hold_buffer_count" : "409"
  ,"GRT::ANT::errors" : "1"
  ,"DRT::drv" : "0"
- ,"DRT::worst_slack_min" : "-1.4392131972436715"
- ,"DRT::worst_slack_max" : "-1.6963790486920518"
- ,"DRT::tns_max" : "-1597.511446737049"
- ,"DRT::clock_skew" : "2.370594454502448"
- ,"DRT::max_slew_slack" : "-37.553908824920654"
- ,"DRT::max_capacitance_slack" : "-42.087068918736364"
+ ,"DRT::worst_slack_min" : "-1.4389010025203173"
+ ,"DRT::worst_slack_max" : "-1.7248460560269625"
+ ,"DRT::tns_max" : "-1596.287934744031"
+ ,"DRT::clock_skew" : "2.3666093754562323"
+ ,"DRT::max_slew_slack" : "-35.96203565597534"
+ ,"DRT::max_capacitance_slack" : "-40.381100718502445"
  ,"DRT::max_fanout_slack" : "0"
  ,"DRT::clock_period" : "11.29"
  ,"DRT::ANT::errors" : "0"
diff --git a/test/jpeg_sky130hd.metrics b/test/jpeg_sky130hd.metrics
index 43dbdb26d8d..6772f80f6b7 100644
--- a/test/jpeg_sky130hd.metrics
+++ b/test/jpeg_sky130hd.metrics
@@ -35,112 +35,82 @@
 	"GRT::ANT::errors": "3",
 	"route__net": 57279,
 	"route__net__special": 2,
-	"route__drc_errors__iter:1": 7440,
-	"route__wirelength__iter:1": 1755725,
-	"route__drc_errors__iter:2": 1199,
-	"route__wirelength__iter:2": 1743755,
-	"route__drc_errors__iter:3": 657,
-	"route__wirelength__iter:3": 1742149,
-	"route__drc_errors__iter:4": 7,
-	"route__wirelength__iter:4": 1742023,
+	"route__drc_errors__iter:1": 7022,
+	"route__wirelength__iter:1": 1746599,
+	"route__drc_errors__iter:2": 1041,
+	"route__wirelength__iter:2": 1733682,
+	"route__drc_errors__iter:3": 624,
+	"route__wirelength__iter:3": 1732079,
+	"route__drc_errors__iter:4": 11,
+	"route__wirelength__iter:4": 1731993,
 	"route__drc_errors__iter:5": 0,
-	"route__wirelength__iter:5": 1742030,
+	"route__wirelength__iter:5": 1731992,
 	"route__drc_errors": 0,
-	"route__wirelength": 1742030,
-	"route__vias": 308734,
-	"route__vias__singlecut": 308734,
+	"route__wirelength": 1731992,
+	"route__vias": 310157,
+	"route__vias__singlecut": 310157,
 	"route__vias__multicut": 0,
 	"DRT::drv": "0",
-	"drt__repair_antennas__pre_repair__antenna__violating__nets": 42,
-	"drt__repair_antennas__pre_repair__antenna__violating__pins": 46,
-	"drt__repair_antennas__iter_0__antenna_diodes_count": 1035,
-	"drt__repair_antennas__iter_0__route__drc_errors__iter:1": 749,
-	"drt__repair_antennas__iter_0__route__wirelength__iter:1": 1742779,
-	"drt__repair_antennas__iter_0__route__drc_errors__iter:2": 113,
-	"drt__repair_antennas__iter_0__route__wirelength__iter:2": 1742566,
-	"drt__repair_antennas__iter_0__route__drc_errors__iter:3": 53,
-	"drt__repair_antennas__iter_0__route__wirelength__iter:3": 1742555,
+	"drt__repair_antennas__pre_repair__antenna__violating__nets": 49,
+	"drt__repair_antennas__pre_repair__antenna__violating__pins": 61,
+	"drt__repair_antennas__iter_0__antenna_diodes_count": 1096,
+	"drt__repair_antennas__iter_0__route__drc_errors__iter:1": 841,
+	"drt__repair_antennas__iter_0__route__wirelength__iter:1": 1733124,
+	"drt__repair_antennas__iter_0__route__drc_errors__iter:2": 98,
+	"drt__repair_antennas__iter_0__route__wirelength__iter:2": 1732823,
+	"drt__repair_antennas__iter_0__route__drc_errors__iter:3": 70,
+	"drt__repair_antennas__iter_0__route__wirelength__iter:3": 1732802,
 	"drt__repair_antennas__iter_0__route__drc_errors__iter:4": 0,
-	"drt__repair_antennas__iter_0__route__wirelength__iter:4": 1742568,
+	"drt__repair_antennas__iter_0__route__wirelength__iter:4": 1732806,
 	"drt__repair_antennas__iter_0__route__drc_errors": 0,
-	"drt__repair_antennas__iter_0__route__wirelength": 1742568,
-	"drt__repair_antennas__iter_0__route__vias": 308946,
-	"drt__repair_antennas__iter_0__route__vias__singlecut": 308946,
+	"drt__repair_antennas__iter_0__route__wirelength": 1732806,
+	"drt__repair_antennas__iter_0__route__vias": 310609,
+	"drt__repair_antennas__iter_0__route__vias__singlecut": 310609,
 	"drt__repair_antennas__iter_0__route__vias__multicut": 0,
-	"drt__repair_antennas__iter_0__antenna__violating__nets": 5,
+	"drt__repair_antennas__iter_0__antenna__violating__nets": 4,
 	"drt__repair_antennas__iter_0__antenna__violating__pins": 5,
-	"drt__repair_antennas__iter_1__antenna_diodes_count": 1040,
-	"drt__repair_antennas__iter_1__route__drc_errors__iter:1": 115,
-	"drt__repair_antennas__iter_1__route__wirelength__iter:1": 1742629,
-	"drt__repair_antennas__iter_1__route__drc_errors__iter:2": 9,
-	"drt__repair_antennas__iter_1__route__wirelength__iter:2": 1742584,
-	"drt__repair_antennas__iter_1__route__drc_errors__iter:3": 2,
-	"drt__repair_antennas__iter_1__route__wirelength__iter:3": 1742582,
+	"drt__repair_antennas__iter_1__antenna_diodes_count": 1101,
+	"drt__repair_antennas__iter_1__route__drc_errors__iter:1": 70,
+	"drt__repair_antennas__iter_1__route__wirelength__iter:1": 1732789,
+	"drt__repair_antennas__iter_1__route__drc_errors__iter:2": 1,
+	"drt__repair_antennas__iter_1__route__wirelength__iter:2": 1732738,
+	"drt__repair_antennas__iter_1__route__drc_errors__iter:3": 1,
+	"drt__repair_antennas__iter_1__route__wirelength__iter:3": 1732738,
 	"drt__repair_antennas__iter_1__route__drc_errors__iter:4": 0,
-	"drt__repair_antennas__iter_1__route__wirelength__iter:4": 1742580,
+	"drt__repair_antennas__iter_1__route__wirelength__iter:4": 1732739,
 	"drt__repair_antennas__iter_1__route__drc_errors": 0,
-	"drt__repair_antennas__iter_1__route__wirelength": 1742580,
-	"drt__repair_antennas__iter_1__route__vias": 308963,
-	"drt__repair_antennas__iter_1__route__vias__singlecut": 308963,
+	"drt__repair_antennas__iter_1__route__wirelength": 1732739,
+	"drt__repair_antennas__iter_1__route__vias": 310631,
+	"drt__repair_antennas__iter_1__route__vias__singlecut": 310631,
 	"drt__repair_antennas__iter_1__route__vias__multicut": 0,
 	"drt__repair_antennas__iter_1__antenna__violating__nets": 1,
 	"drt__repair_antennas__iter_1__antenna__violating__pins": 1,
-	"drt__repair_antennas__iter_2__antenna_diodes_count": 1041,
-	"drt__repair_antennas__iter_2__route__drc_errors__iter:1": 76,
-	"drt__repair_antennas__iter_2__route__wirelength__iter:1": 1742599,
-	"drt__repair_antennas__iter_2__route__drc_errors__iter:2": 17,
-	"drt__repair_antennas__iter_2__route__wirelength__iter:2": 1742597,
-	"drt__repair_antennas__iter_2__route__drc_errors__iter:3": 0,
-	"drt__repair_antennas__iter_2__route__wirelength__iter:3": 1742595,
+	"drt__repair_antennas__iter_2__antenna_diodes_count": 1102,
+	"drt__repair_antennas__iter_2__route__drc_errors__iter:1": 26,
+	"drt__repair_antennas__iter_2__route__wirelength__iter:1": 1732786,
+	"drt__repair_antennas__iter_2__route__drc_errors__iter:2": 0,
+	"drt__repair_antennas__iter_2__route__wirelength__iter:2": 1732761,
 	"drt__repair_antennas__iter_2__route__drc_errors": 0,
-	"drt__repair_antennas__iter_2__route__wirelength": 1742595,
-	"drt__repair_antennas__iter_2__route__vias": 308959,
-	"drt__repair_antennas__iter_2__route__vias__singlecut": 308959,
+	"drt__repair_antennas__iter_2__route__wirelength": 1732761,
+	"drt__repair_antennas__iter_2__route__vias": 310634,
+	"drt__repair_antennas__iter_2__route__vias__singlecut": 310634,
 	"drt__repair_antennas__iter_2__route__vias__multicut": 0,
-	"drt__repair_antennas__iter_2__antenna__violating__nets": 1,
-	"drt__repair_antennas__iter_2__antenna__violating__pins": 1,
-	"drt__repair_antennas__iter_3__antenna_diodes_count": 1042,
-	"drt__repair_antennas__iter_3__route__drc_errors__iter:1": 71,
-	"drt__repair_antennas__iter_3__route__wirelength__iter:1": 1742604,
-	"drt__repair_antennas__iter_3__route__drc_errors__iter:2": 16,
-	"drt__repair_antennas__iter_3__route__wirelength__iter:2": 1742605,
-	"drt__repair_antennas__iter_3__route__drc_errors__iter:3": 0,
-	"drt__repair_antennas__iter_3__route__wirelength__iter:3": 1742603,
-	"drt__repair_antennas__iter_3__route__drc_errors": 0,
-	"drt__repair_antennas__iter_3__route__wirelength": 1742603,
-	"drt__repair_antennas__iter_3__route__vias": 308964,
-	"drt__repair_antennas__iter_3__route__vias__singlecut": 308964,
-	"drt__repair_antennas__iter_3__route__vias__multicut": 0,
-	"drt__repair_antennas__iter_3__antenna__violating__nets": 1,
-	"drt__repair_antennas__iter_3__antenna__violating__pins": 2,
-	"drt__repair_antennas__iter_4__antenna_diodes_count": 1044,
-	"drt__repair_antennas__iter_4__route__drc_errors__iter:1": 75,
-	"drt__repair_antennas__iter_4__route__wirelength__iter:1": 1742594,
-	"drt__repair_antennas__iter_4__route__drc_errors__iter:2": 17,
-	"drt__repair_antennas__iter_4__route__wirelength__iter:2": 1742597,
-	"drt__repair_antennas__iter_4__route__drc_errors__iter:3": 0,
-	"drt__repair_antennas__iter_4__route__wirelength__iter:3": 1742595,
-	"drt__repair_antennas__iter_4__route__drc_errors": 0,
-	"drt__repair_antennas__iter_4__route__wirelength": 1742595,
-	"drt__repair_antennas__iter_4__route__vias": 308963,
-	"drt__repair_antennas__iter_4__route__vias__singlecut": 308963,
-	"drt__repair_antennas__iter_4__route__vias__multicut": 0,
-	"drt__repair_antennas__iter_4__antenna__violating__nets": 1,
-	"drt__repair_antennas__iter_4__antenna__violating__pins": 1,
-	"drt__antenna__violating__nets": 1,
-	"drt__antenna__violating__pins": 1,
-	"DRT::ANT::errors": "1",
+	"drt__repair_antennas__iter_2__antenna__violating__nets": 0,
+	"drt__repair_antennas__iter_2__antenna__violating__pins": 0,
+	"drt__antenna__violating__nets": 0,
+	"drt__antenna__violating__pins": 0,
+	"DRT::ANT::errors": "0",
 	"design__violations": 0,
 	"timing__drv__floating__nets": 0,
 	"timing__drv__floating__pins": 0,
-	"DRT::worst_slack_min": "-0.235491188770227",
-	"DRT::worst_slack_max": "-0.6303642231064286",
-	"DRT::tns_max": "-22.692238064241725",
-	"DRT::clock_skew": "0.6035925263780672",
-	"DRT::max_slew_slack": "-10.649577776590984",
+	"DRT::worst_slack_min": "-0.088321796820521",
+	"DRT::worst_slack_max": "-0.7905383238451821",
+	"DRT::tns_max": "-32.87254295147692",
+	"DRT::clock_skew": "0.5943281590647659",
+	"DRT::max_slew_slack": "-7.94659157594045",
 	"DRT::max_fanout_slack": "100.0",
-	"DRT::max_capacitance_slack": "-7.3253633816230135",
+	"DRT::max_capacitance_slack": "-6.32495578424572",
 	"DRT::clock_period": "8.000000",
-	"flow__warnings__count": 223,
+	"flow__warnings__count": 175,
 	"flow__errors__count": 0
 }
\ No newline at end of file
diff --git a/test/jpeg_sky130hd.metrics_limits b/test/jpeg_sky130hd.metrics_limits
index f98ea95d4b3..68ce3b65c30 100644
--- a/test/jpeg_sky130hd.metrics_limits
+++ b/test/jpeg_sky130hd.metrics_limits
@@ -12,13 +12,13 @@
  ,"RSZ::hold_buffer_count" : "112"
  ,"GRT::ANT::errors" : "3"
  ,"DRT::drv" : "0"
- ,"DRT::worst_slack_min" : "-1.035491188770227"
- ,"DRT::worst_slack_max" : "-1.4303642231064286"
- ,"DRT::tns_max" : "-3673.4122380642425"
- ,"DRT::clock_skew" : "0.7243110316536806"
- ,"DRT::max_slew_slack" : "-12.779493331909181"
- ,"DRT::max_capacitance_slack" : "-8.790436057947616"
+ ,"DRT::worst_slack_min" : "-0.888321796820521"
+ ,"DRT::worst_slack_max" : "-1.5905383238451822"
+ ,"DRT::tns_max" : "-3683.5925429514778"
+ ,"DRT::clock_skew" : "0.7131937908777191"
+ ,"DRT::max_slew_slack" : "-9.53590989112854"
+ ,"DRT::max_capacitance_slack" : "-7.589946941094864"
  ,"DRT::max_fanout_slack" : "0"
  ,"DRT::clock_period" : "8.0"
- ,"DRT::ANT::errors" : "1"
+ ,"DRT::ANT::errors" : "0"
 }