From 73af0d07a40df1e522c6fcf8d353b6819461224a Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Tue, 24 Sep 2024 17:45:12 -0400 Subject: [PATCH 1/7] pad: clarify where the rotations are based Signed-off-by: Peter Gadfort --- src/pad/README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/pad/README.md b/src/pad/README.md index 7a86f4898d1..1cd38a814f4 100644 --- a/src/pad/README.md +++ b/src/pad/README.md @@ -167,9 +167,9 @@ make_io_sites | `-vertical_site` | Name of the site for the vertical pads (north and south). | | `-corner_site` | Name of the site for the corner cells. | | `-offset` | Offset from the die edge to place the rows. | -| `-rotation_horizontal` | Rotation to apply to the horizontal sites to ensure pads are placed correctly. The default value is `R0`. | -| `-rotation_vertical` | Rotation to apply to the vertical sites to ensure pads are placed correctly. The default value is `R0`. | -| `-rotation_corner` | Rotation to apply to the corner sites to ensure pads are placed correctly. The default value is `R0`. | +| `-rotation_horizontal` | Rotation to apply to the horizontal sites to ensure pads are placed correctly. The default value is `R0` for the eastern (right) row. | +| `-rotation_vertical` | Rotation to apply to the vertical sites to ensure pads are placed correctly. The default value is `R0` for the southern (bottom) row. | +| `-rotation_corner` | Rotation to apply to the corner sites to ensure pads are placed correctly. The default value is `R0` for the south west (lower left) corner. | | `-ring_index` | Used to specify the index of the ring in case of multiple rings. | From 0e0a30450fd2bd9bc8cc5008dea6aaf502026f5e Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Tue, 24 Sep 2024 17:45:49 -0400 Subject: [PATCH 2/7] pad: correct row orientation concatenation order Signed-off-by: Peter Gadfort --- src/pad/src/ICeWall.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/pad/src/ICeWall.cpp b/src/pad/src/ICeWall.cpp index 63952eed8b2..75c8c53e10c 100644 --- a/src/pad/src/ICeWall.cpp +++ b/src/pad/src/ICeWall.cpp @@ -447,8 +447,8 @@ void ICeWall::makeIORow(odb::dbSite* horizontal_site, const odb::dbRowDir& direction, int site_width) { const std::string row_name = getRowName(name, ring_index); - odb::dbTransform rotation(orient); - rotation.concat(row_rotation); + odb::dbTransform rotation(row_rotation); + rotation.concat(orient); odb::dbRow::create(block, row_name.c_str(), site, From ad4f34d14524b04dbc7b8b3e979b305ef41c4c20 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Tue, 24 Sep 2024 20:32:30 -0400 Subject: [PATCH 3/7] pad: add test for site rotations Signed-off-by: Peter Gadfort --- src/pad/test/Nangate45_io/dummy_pads.lef | 6 + src/pad/test/make_io_sites_rotations.defok | 793 +++++++++++++++++++++ src/pad/test/make_io_sites_rotations.ok | 7 + src/pad/test/make_io_sites_rotations.tcl | 17 + src/pad/test/regression_tests.tcl | 1 + 5 files changed, 824 insertions(+) create mode 100644 src/pad/test/make_io_sites_rotations.defok create mode 100644 src/pad/test/make_io_sites_rotations.ok create mode 100644 src/pad/test/make_io_sites_rotations.tcl diff --git a/src/pad/test/Nangate45_io/dummy_pads.lef b/src/pad/test/Nangate45_io/dummy_pads.lef index a325c61a0b3..297aa3e8a36 100644 --- a/src/pad/test/Nangate45_io/dummy_pads.lef +++ b/src/pad/test/Nangate45_io/dummy_pads.lef @@ -14,6 +14,12 @@ SITE IOSITE SIZE 1.000 BY 140.000 ; END IOSITE +SITE IOSITE2 + SYMMETRY Y ; + CLASS PAD ; + SIZE 1.000 BY 140.000 ; +END IOSITE2 + MACRO PAD CLASS COVER ; ORIGIN 0 0 ; diff --git a/src/pad/test/make_io_sites_rotations.defok b/src/pad/test/make_io_sites_rotations.defok new file mode 100644 index 00000000000..ce9fab123ed --- /dev/null +++ b/src/pad/test/make_io_sites_rotations.defok @@ -0,0 +1,793 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN soc_bsg_black_parrot ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 6000000 6000000 ) ; +ROW IO_CORNER_NORTH_WEST IOSITE 30000 5690000 FS DO 140 BY 1 STEP 2000 0 ; +ROW IO_CORNER_NORTH_EAST IOSITE 5690000 5690000 S DO 140 BY 1 STEP 2000 0 ; +ROW IO_CORNER_SOUTH_EAST IOSITE 5690000 30000 FN DO 140 BY 1 STEP 2000 0 ; +ROW IO_CORNER_SOUTH_WEST IOSITE 30000 30000 N DO 140 BY 1 STEP 2000 0 ; +ROW IO_NORTH IOSITE2 310000 5690000 S DO 2690 BY 1 STEP 2000 0 ; +ROW IO_EAST IOSITE 5690000 310000 W DO 1 BY 2690 STEP 0 2000 ; +ROW IO_SOUTH IOSITE2 310000 30000 FN DO 2690 BY 1 STEP 2000 0 ; +ROW IO_WEST IOSITE 30000 310000 FW DO 1 BY 2690 STEP 0 2000 ; +TRACKS X 190 DO 21428 STEP 280 LAYER metal1 ; +TRACKS Y 140 DO 21428 STEP 280 LAYER metal1 ; +TRACKS X 190 DO 15789 STEP 380 LAYER metal2 ; +TRACKS Y 140 DO 15789 STEP 380 LAYER metal2 ; +TRACKS X 190 DO 21428 STEP 280 LAYER metal3 ; +TRACKS Y 140 DO 21428 STEP 280 LAYER metal3 ; +TRACKS X 190 DO 10714 STEP 560 LAYER metal4 ; +TRACKS Y 140 DO 10714 STEP 560 LAYER metal4 ; +TRACKS X 190 DO 10714 STEP 560 LAYER metal5 ; +TRACKS Y 140 DO 10714 STEP 560 LAYER metal5 ; +TRACKS X 190 DO 10714 STEP 560 LAYER metal6 ; +TRACKS Y 140 DO 10714 STEP 560 LAYER metal6 ; +TRACKS X 1790 DO 3749 STEP 1600 LAYER metal7 ; +TRACKS Y 1740 DO 3749 STEP 1600 LAYER metal7 ; +TRACKS X 1790 DO 3749 STEP 1600 LAYER metal8 ; +TRACKS Y 1740 DO 3749 STEP 1600 LAYER metal8 ; +TRACKS X 3390 DO 1874 STEP 3200 LAYER metal9 ; +TRACKS Y 3340 DO 1874 STEP 3200 LAYER metal9 ; +TRACKS X 3390 DO 1874 STEP 3200 LAYER metal10 ; +TRACKS Y 3340 DO 1874 STEP 3200 LAYER metal10 ; +COMPONENTS 267 ; + - u_bsg_tag_clk_i PADCELL_SIG_H ; + - u_bsg_tag_clk_o PADCELL_SIG_H ; + - u_bsg_tag_data_i PADCELL_SIG_H ; + - u_bsg_tag_data_o PADCELL_SIG_H ; + - u_bsg_tag_en_i PADCELL_SIG_H ; + - u_ci2_0_o PADCELL_SIG_V ; + - u_ci2_1_o PADCELL_SIG_V ; + - u_ci2_2_o PADCELL_SIG_V ; + - u_ci2_3_o PADCELL_SIG_V ; + - u_ci2_4_o PADCELL_SIG_V ; + - u_ci2_5_o PADCELL_SIG_V ; + - u_ci2_6_o PADCELL_SIG_V ; + - u_ci2_7_o PADCELL_SIG_V ; + - u_ci2_8_o PADCELL_SIG_V ; + - u_ci2_clk_o PADCELL_SIG_V ; + - u_ci2_tkn_i PADCELL_SIG_V ; + - u_ci2_v_o PADCELL_SIG_V ; + - u_ci_0_i PADCELL_SIG_H ; + - u_ci_1_i PADCELL_SIG_H ; + - u_ci_2_i PADCELL_SIG_H ; + - u_ci_3_i PADCELL_SIG_H ; + - u_ci_4_i PADCELL_SIG_H ; + - u_ci_5_i PADCELL_SIG_H ; + - u_ci_6_i PADCELL_SIG_H ; + - u_ci_7_i PADCELL_SIG_H ; + - u_ci_8_i PADCELL_SIG_H ; + - u_ci_clk_i PADCELL_SIG_H ; + - u_ci_tkn_o PADCELL_SIG_H ; + - u_ci_v_i PADCELL_SIG_H ; + - u_clk_A_i PADCELL_SIG_V ; + - u_clk_B_i PADCELL_SIG_V ; + - u_clk_C_i PADCELL_SIG_V ; + - u_clk_async_reset_i PADCELL_SIG_V ; + - u_clk_o PADCELL_SIG_V ; + - u_co2_0_o PADCELL_SIG_H ; + - u_co2_1_o PADCELL_SIG_H ; + - u_co2_2_o PADCELL_SIG_H ; + - u_co2_3_o PADCELL_SIG_H ; + - u_co2_4_o PADCELL_SIG_H ; + - u_co2_5_o PADCELL_SIG_H ; + - u_co2_6_o PADCELL_SIG_H ; + - u_co2_7_o PADCELL_SIG_H ; + - u_co2_8_o PADCELL_SIG_H ; + - u_co2_clk_o PADCELL_SIG_H ; + - u_co2_tkn_i PADCELL_SIG_H ; + - u_co2_v_o PADCELL_SIG_H ; + - u_co_0_i PADCELL_SIG_V ; + - u_co_1_i PADCELL_SIG_V ; + - u_co_2_i PADCELL_SIG_V ; + - u_co_3_i PADCELL_SIG_V ; + - u_co_4_i PADCELL_SIG_V ; + - u_co_5_i PADCELL_SIG_V ; + - u_co_6_i PADCELL_SIG_V ; + - u_co_7_i PADCELL_SIG_V ; + - u_co_8_i PADCELL_SIG_V ; + - u_co_clk_i PADCELL_SIG_V ; + - u_co_tkn_o PADCELL_SIG_V ; + - u_co_v_i PADCELL_SIG_V ; + - u_core_async_reset_i PADCELL_SIG_V ; + - u_ddr_addr_0_o PADCELL_SIG_V ; + - u_ddr_addr_10_o PADCELL_SIG_V ; + - u_ddr_addr_11_o PADCELL_SIG_V ; + - u_ddr_addr_12_o PADCELL_SIG_V ; + - u_ddr_addr_13_o PADCELL_SIG_V ; + - u_ddr_addr_14_o PADCELL_SIG_V ; + - u_ddr_addr_15_o PADCELL_SIG_V ; + - u_ddr_addr_1_o PADCELL_SIG_V ; + - u_ddr_addr_2_o PADCELL_SIG_V ; + - u_ddr_addr_3_o PADCELL_SIG_V ; + - u_ddr_addr_4_o PADCELL_SIG_V ; + - u_ddr_addr_5_o PADCELL_SIG_V ; + - u_ddr_addr_6_o PADCELL_SIG_V ; + - u_ddr_addr_7_o PADCELL_SIG_V ; + - u_ddr_addr_8_o PADCELL_SIG_V ; + - u_ddr_addr_9_o PADCELL_SIG_V ; + - u_ddr_ba_0_o PADCELL_SIG_V ; + - u_ddr_ba_1_o PADCELL_SIG_V ; + - u_ddr_ba_2_o PADCELL_SIG_V ; + - u_ddr_cas_n_o PADCELL_SIG_V ; + - u_ddr_ck_n_o PADCELL_SIG_V ; + - u_ddr_ck_p_o PADCELL_SIG_V ; + - u_ddr_cke_o PADCELL_SIG_V ; + - u_ddr_cs_n_o PADCELL_SIG_V ; + - u_ddr_dm_0_o PADCELL_SIG_H ; + - u_ddr_dm_1_o PADCELL_SIG_V ; + - u_ddr_dm_2_o PADCELL_SIG_V ; + - u_ddr_dm_3_o PADCELL_SIG_H ; + - u_ddr_dq_0_io PADCELL_SIG_H ; + - u_ddr_dq_10_io PADCELL_SIG_H ; + - u_ddr_dq_11_io PADCELL_SIG_H ; + - u_ddr_dq_12_io PADCELL_SIG_H ; + - u_ddr_dq_13_io PADCELL_SIG_H ; + - u_ddr_dq_14_io PADCELL_SIG_H ; + - u_ddr_dq_15_io PADCELL_SIG_H ; + - u_ddr_dq_16_io PADCELL_SIG_H ; + - u_ddr_dq_17_io PADCELL_SIG_H ; + - u_ddr_dq_18_io PADCELL_SIG_H ; + - u_ddr_dq_19_io PADCELL_SIG_H ; + - u_ddr_dq_1_io PADCELL_SIG_H ; + - u_ddr_dq_20_io PADCELL_SIG_H ; + - u_ddr_dq_21_io PADCELL_SIG_H ; + - u_ddr_dq_22_io PADCELL_SIG_H ; + - u_ddr_dq_23_io PADCELL_SIG_H ; + - u_ddr_dq_24_io PADCELL_SIG_H ; + - u_ddr_dq_25_io PADCELL_SIG_H ; + - u_ddr_dq_26_io PADCELL_SIG_H ; + - u_ddr_dq_27_io PADCELL_SIG_H ; + - u_ddr_dq_28_io PADCELL_SIG_H ; + - u_ddr_dq_29_io PADCELL_SIG_H ; + - u_ddr_dq_2_io PADCELL_SIG_H ; + - u_ddr_dq_30_io PADCELL_SIG_H ; + - u_ddr_dq_31_io PADCELL_SIG_H ; + - u_ddr_dq_3_io PADCELL_SIG_H ; + - u_ddr_dq_4_io PADCELL_SIG_H ; + - u_ddr_dq_5_io PADCELL_SIG_H ; + - u_ddr_dq_6_io PADCELL_SIG_H ; + - u_ddr_dq_7_io PADCELL_SIG_H ; + - u_ddr_dq_8_io PADCELL_SIG_H ; + - u_ddr_dq_9_io PADCELL_SIG_H ; + - u_ddr_dqs_n_0_io PADCELL_SIG_H ; + - u_ddr_dqs_n_1_io PADCELL_SIG_V ; + - u_ddr_dqs_n_2_io PADCELL_SIG_V ; + - u_ddr_dqs_n_3_io PADCELL_SIG_H ; + - u_ddr_dqs_p_0_io PADCELL_SIG_H ; + - u_ddr_dqs_p_1_io PADCELL_SIG_V ; + - u_ddr_dqs_p_2_io PADCELL_SIG_V ; + - u_ddr_dqs_p_3_io PADCELL_SIG_H ; + - u_ddr_odt_o PADCELL_SIG_V ; + - u_ddr_ras_n_o PADCELL_SIG_V ; + - u_ddr_reset_n_o PADCELL_SIG_V ; + - u_ddr_we_n_o PADCELL_SIG_V ; + - u_misc_o PADCELL_SIG_V ; + - u_sel_0_i PADCELL_SIG_V ; + - u_sel_1_i PADCELL_SIG_V ; + - u_sel_2_i PADCELL_SIG_V ; + - u_v18_1 PADCELL_VDDIO_V ; + - u_v18_10 PADCELL_VDDIO_H ; + - u_v18_11 PADCELL_VDDIO_H ; + - u_v18_12 PADCELL_VDDIO_H ; + - u_v18_13 PADCELL_VDDIO_H ; + - u_v18_14 PADCELL_VDDIO_H ; + - u_v18_15 PADCELL_VDDIO_H ; + - u_v18_16 PADCELL_VDDIO_H ; + - u_v18_17 PADCELL_VDDIO_V ; + - u_v18_18 PADCELL_VDDIO_V ; + - u_v18_19 PADCELL_VDDIO_V ; + - u_v18_2 PADCELL_VDDIO_V ; + - u_v18_20 PADCELL_VDDIO_V ; + - u_v18_21 PADCELL_VDDIO_V ; + - u_v18_22 PADCELL_VDDIO_V ; + - u_v18_23 PADCELL_VDDIO_V ; + - u_v18_24 PADCELL_VDDIO_V ; + - u_v18_25 PADCELL_VDDIO_H ; + - u_v18_26 PADCELL_VDDIO_H ; + - u_v18_27 PADCELL_VDDIO_H ; + - u_v18_28 PADCELL_VDDIO_H ; + - u_v18_29 PADCELL_VDDIO_H ; + - u_v18_3 PADCELL_VDDIO_V ; + - u_v18_30 PADCELL_VDDIO_H ; + - u_v18_31 PADCELL_VDDIO_H ; + - u_v18_32 PADCELL_VDDIO_H ; + - u_v18_4 PADCELL_VDDIO_V ; + - u_v18_5 PADCELL_VDDIO_V ; + - u_v18_6 PADCELL_VDDIO_V ; + - u_v18_7 PADCELL_VDDIO_V ; + - u_v18_8 PADCELL_VDDIO_V ; + - u_v18_9 PADCELL_VDDIO_H ; + - u_vdd_1 PADCELL_VDD_V ; + - u_vdd_10 PADCELL_VDD_H ; + - u_vdd_11 PADCELL_VDD_H ; + - u_vdd_12 PADCELL_VDD_H ; + - u_vdd_13 PADCELL_VDD_H ; + - u_vdd_14 PADCELL_VDD_H ; + - u_vdd_15 PADCELL_VDD_H ; + - u_vdd_16 PADCELL_VDD_H ; + - u_vdd_17 PADCELL_VDD_V ; + - u_vdd_18 PADCELL_VDD_V ; + - u_vdd_19 PADCELL_VDD_V ; + - u_vdd_2 PADCELL_VDD_V ; + - u_vdd_20 PADCELL_VDD_V ; + - u_vdd_21 PADCELL_VDD_V ; + - u_vdd_22 PADCELL_VDD_V ; + - u_vdd_23 PADCELL_VDD_V ; + - u_vdd_24 PADCELL_VDD_V ; + - u_vdd_25 PADCELL_VDD_H ; + - u_vdd_26 PADCELL_VDD_H ; + - u_vdd_27 PADCELL_VDD_H ; + - u_vdd_28 PADCELL_VDD_H ; + - u_vdd_29 PADCELL_VDD_H ; + - u_vdd_3 PADCELL_VDD_V ; + - u_vdd_30 PADCELL_VDD_H ; + - u_vdd_31 PADCELL_VDD_H ; + - u_vdd_32 PADCELL_VDD_H ; + - u_vdd_4 PADCELL_VDD_V ; + - u_vdd_5 PADCELL_VDD_V ; + - u_vdd_6 PADCELL_VDD_V ; + - u_vdd_7 PADCELL_VDD_V ; + - u_vdd_8 PADCELL_VDD_H ; + - u_vdd_9 PADCELL_VDD_H ; + - u_vdd_pll PADCELL_VDD_V ; + - u_vss_0 PADCELL_VSS_V ; + - u_vss_1 PADCELL_VSS_V ; + - u_vss_10 PADCELL_VSS_H ; + - u_vss_11 PADCELL_VSS_H ; + - u_vss_12 PADCELL_VSS_H ; + - u_vss_13 PADCELL_VSS_H ; + - u_vss_14 PADCELL_VSS_H ; + - u_vss_15 PADCELL_VSS_H ; + - u_vss_16 PADCELL_VSS_H ; + - u_vss_17 PADCELL_VSS_V ; + - u_vss_18 PADCELL_VSS_V ; + - u_vss_19 PADCELL_VSS_V ; + - u_vss_2 PADCELL_VSS_V ; + - u_vss_20 PADCELL_VSS_V ; + - u_vss_21 PADCELL_VSS_V ; + - u_vss_22 PADCELL_VSS_V ; + - u_vss_23 PADCELL_VSS_V ; + - u_vss_24 PADCELL_VSS_V ; + - u_vss_25 PADCELL_VSS_H ; + - u_vss_26 PADCELL_VSS_H ; + - u_vss_27 PADCELL_VSS_H ; + - u_vss_28 PADCELL_VSS_H ; + - u_vss_29 PADCELL_VSS_H ; + - u_vss_3 PADCELL_VSS_V ; + - u_vss_30 PADCELL_VSS_H ; + - u_vss_31 PADCELL_VSS_H ; + - u_vss_32 PADCELL_VSS_H ; + - u_vss_4 PADCELL_VSS_V ; + - u_vss_5 PADCELL_VSS_V ; + - u_vss_6 PADCELL_VSS_V ; + - u_vss_7 PADCELL_VSS_V ; + - u_vss_8 PADCELL_VSS_H ; + - u_vss_9 PADCELL_VSS_H ; + - u_vss_pll PADCELL_VSS_V ; + - u_vzz_0 PADCELL_VSSIO_V ; + - u_vzz_1 PADCELL_VSSIO_V ; + - u_vzz_10 PADCELL_VSSIO_H ; + - u_vzz_11 PADCELL_VSSIO_H ; + - u_vzz_12 PADCELL_VSSIO_H ; + - u_vzz_13 PADCELL_VSSIO_H ; + - u_vzz_14 PADCELL_VSSIO_H ; + - u_vzz_15 PADCELL_VSSIO_H ; + - u_vzz_16 PADCELL_VSSIO_H ; + - u_vzz_17 PADCELL_VSSIO_V ; + - u_vzz_18 PADCELL_VSSIO_V ; + - u_vzz_19 PADCELL_VSSIO_V ; + - u_vzz_2 PADCELL_VSSIO_V ; + - u_vzz_20 PADCELL_VSSIO_V ; + - u_vzz_21 PADCELL_VSSIO_V ; + - u_vzz_22 PADCELL_VSSIO_V ; + - u_vzz_23 PADCELL_VSSIO_V ; + - u_vzz_24 PADCELL_VSSIO_V ; + - u_vzz_25 PADCELL_VSSIO_H ; + - u_vzz_26 PADCELL_VSSIO_H ; + - u_vzz_27 PADCELL_VSSIO_H ; + - u_vzz_28 PADCELL_VSSIO_H ; + - u_vzz_29 PADCELL_VSSIO_H ; + - u_vzz_3 PADCELL_VSSIO_V ; + - u_vzz_30 PADCELL_VSSIO_H ; + - u_vzz_31 PADCELL_VSSIO_H ; + - u_vzz_32 PADCELL_VSSIO_H ; + - u_vzz_4 PADCELL_VSSIO_V ; + - u_vzz_5 PADCELL_VSSIO_V ; + - u_vzz_6 PADCELL_VSSIO_V ; + - u_vzz_7 PADCELL_VSSIO_V ; + - u_vzz_8 PADCELL_VSSIO_V ; + - u_vzz_9 PADCELL_VSSIO_H ; +END COMPONENTS +PINS 135 ; + - p_bsg_tag_clk_i + NET p_bsg_tag_clk_i + DIRECTION INPUT + USE SIGNAL ; + - p_bsg_tag_clk_o + NET p_bsg_tag_clk_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_bsg_tag_data_i + NET p_bsg_tag_data_i + DIRECTION INPUT + USE SIGNAL ; + - p_bsg_tag_data_o + NET p_bsg_tag_data_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_bsg_tag_en_i + NET p_bsg_tag_en_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci2_0_o + NET p_ci2_0_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_1_o + NET p_ci2_1_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_2_o + NET p_ci2_2_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_3_o + NET p_ci2_3_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_4_o + NET p_ci2_4_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_5_o + NET p_ci2_5_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_6_o + NET p_ci2_6_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_7_o + NET p_ci2_7_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_8_o + NET p_ci2_8_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_clk_o + NET p_ci2_clk_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_tkn_i + NET p_ci2_tkn_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci2_v_o + NET p_ci2_v_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci_0_i + NET p_ci_0_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_1_i + NET p_ci_1_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_2_i + NET p_ci_2_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_3_i + NET p_ci_3_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_4_i + NET p_ci_4_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_5_i + NET p_ci_5_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_6_i + NET p_ci_6_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_7_i + NET p_ci_7_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_8_i + NET p_ci_8_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_clk_i + NET p_ci_clk_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_tkn_o + NET p_ci_tkn_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci_v_i + NET p_ci_v_i + DIRECTION INPUT + USE SIGNAL ; + - p_clk_A_i + NET p_clk_A_i + DIRECTION INPUT + USE SIGNAL ; + - p_clk_B_i + NET p_clk_B_i + DIRECTION INPUT + USE SIGNAL ; + - p_clk_C_i + NET p_clk_C_i + DIRECTION INPUT + USE SIGNAL ; + - p_clk_async_reset_i + NET p_clk_async_reset_i + DIRECTION INPUT + USE SIGNAL ; + - p_clk_o + NET p_clk_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_0_o + NET p_co2_0_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_1_o + NET p_co2_1_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_2_o + NET p_co2_2_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_3_o + NET p_co2_3_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_4_o + NET p_co2_4_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_5_o + NET p_co2_5_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_6_o + NET p_co2_6_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_7_o + NET p_co2_7_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_8_o + NET p_co2_8_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_clk_o + NET p_co2_clk_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_tkn_i + NET p_co2_tkn_i + DIRECTION INPUT + USE SIGNAL ; + - p_co2_v_o + NET p_co2_v_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co_0_i + NET p_co_0_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_1_i + NET p_co_1_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_2_i + NET p_co_2_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_3_i + NET p_co_3_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_4_i + NET p_co_4_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_5_i + NET p_co_5_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_6_i + NET p_co_6_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_7_i + NET p_co_7_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_8_i + NET p_co_8_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_clk_i + NET p_co_clk_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_tkn_o + NET p_co_tkn_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co_v_i + NET p_co_v_i + DIRECTION INPUT + USE SIGNAL ; + - p_core_async_reset_i + NET p_core_async_reset_i + DIRECTION INPUT + USE SIGNAL ; + - p_ddr_addr_0_o + NET p_ddr_addr_0_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_10_o + NET p_ddr_addr_10_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_11_o + NET p_ddr_addr_11_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_12_o + NET p_ddr_addr_12_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_13_o + NET p_ddr_addr_13_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_14_o + NET p_ddr_addr_14_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_15_o + NET p_ddr_addr_15_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_1_o + NET p_ddr_addr_1_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_2_o + NET p_ddr_addr_2_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_3_o + NET p_ddr_addr_3_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_4_o + NET p_ddr_addr_4_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_5_o + NET p_ddr_addr_5_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_6_o + NET p_ddr_addr_6_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_7_o + NET p_ddr_addr_7_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_8_o + NET p_ddr_addr_8_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_9_o + NET p_ddr_addr_9_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_ba_0_o + NET p_ddr_ba_0_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_ba_1_o + NET p_ddr_ba_1_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_ba_2_o + NET p_ddr_ba_2_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_cas_n_o + NET p_ddr_cas_n_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_ck_n_o + NET p_ddr_ck_n_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_ck_p_o + NET p_ddr_ck_p_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_cke_o + NET p_ddr_cke_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_cs_n_o + NET p_ddr_cs_n_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_dm_0_o + NET p_ddr_dm_0_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_dm_1_o + NET p_ddr_dm_1_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_dm_2_o + NET p_ddr_dm_2_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_dm_3_o + NET p_ddr_dm_3_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_dq_0_io + NET p_ddr_dq_0_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_10_io + NET p_ddr_dq_10_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_11_io + NET p_ddr_dq_11_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_12_io + NET p_ddr_dq_12_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_13_io + NET p_ddr_dq_13_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_14_io + NET p_ddr_dq_14_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_15_io + NET p_ddr_dq_15_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_16_io + NET p_ddr_dq_16_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_17_io + NET p_ddr_dq_17_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_18_io + NET p_ddr_dq_18_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_19_io + NET p_ddr_dq_19_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_1_io + NET p_ddr_dq_1_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_20_io + NET p_ddr_dq_20_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_21_io + NET p_ddr_dq_21_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_22_io + NET p_ddr_dq_22_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_23_io + NET p_ddr_dq_23_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_24_io + NET p_ddr_dq_24_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_25_io + NET p_ddr_dq_25_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_26_io + NET p_ddr_dq_26_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_27_io + NET p_ddr_dq_27_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_28_io + NET p_ddr_dq_28_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_29_io + NET p_ddr_dq_29_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_2_io + NET p_ddr_dq_2_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_30_io + NET p_ddr_dq_30_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_31_io + NET p_ddr_dq_31_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_3_io + NET p_ddr_dq_3_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_4_io + NET p_ddr_dq_4_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_5_io + NET p_ddr_dq_5_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_6_io + NET p_ddr_dq_6_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_7_io + NET p_ddr_dq_7_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_8_io + NET p_ddr_dq_8_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_9_io + NET p_ddr_dq_9_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_n_0_io + NET p_ddr_dqs_n_0_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_n_1_io + NET p_ddr_dqs_n_1_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_n_2_io + NET p_ddr_dqs_n_2_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_n_3_io + NET p_ddr_dqs_n_3_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_p_0_io + NET p_ddr_dqs_p_0_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_p_1_io + NET p_ddr_dqs_p_1_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_p_2_io + NET p_ddr_dqs_p_2_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_p_3_io + NET p_ddr_dqs_p_3_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_odt_o + NET p_ddr_odt_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_ras_n_o + NET p_ddr_ras_n_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_reset_n_o + NET p_ddr_reset_n_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_we_n_o + NET p_ddr_we_n_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_misc_o + NET p_misc_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_sel_0_i + NET p_sel_0_i + DIRECTION INPUT + USE SIGNAL ; + - p_sel_1_i + NET p_sel_1_i + DIRECTION INPUT + USE SIGNAL ; + - p_sel_2_i + NET p_sel_2_i + DIRECTION INPUT + USE SIGNAL ; +END PINS +NETS 350 ; + - core_bsg_tag_clk_i ( u_bsg_tag_clk_i Y ) + USE SIGNAL ; + - core_bsg_tag_clk_o ( u_bsg_tag_clk_o A ) + USE SIGNAL ; + - core_bsg_tag_data_i ( u_bsg_tag_data_i Y ) + USE SIGNAL ; + - core_bsg_tag_data_o ( u_bsg_tag_data_o A ) + USE SIGNAL ; + - core_bsg_tag_en_i ( u_bsg_tag_en_i Y ) + USE SIGNAL ; + - core_ci2_0_o ( u_ci2_0_o A ) + USE SIGNAL ; + - core_ci2_1_o ( u_ci2_1_o A ) + USE SIGNAL ; + - core_ci2_2_o ( u_ci2_2_o A ) + USE SIGNAL ; + - core_ci2_3_o ( u_ci2_3_o A ) + USE SIGNAL ; + - core_ci2_4_o ( u_ci2_4_o A ) + USE SIGNAL ; + - core_ci2_5_o ( u_ci2_5_o A ) + USE SIGNAL ; + - core_ci2_6_o ( u_ci2_6_o A ) + USE SIGNAL ; + - core_ci2_7_o ( u_ci2_7_o A ) + USE SIGNAL ; + - core_ci2_8_o ( u_ci2_8_o A ) + USE SIGNAL ; + - core_ci2_clk_o ( u_ci2_clk_o A ) + USE SIGNAL ; + - core_ci2_tkn_i ( u_ci2_tkn_i Y ) + USE SIGNAL ; + - core_ci2_v_o ( u_ci2_v_o A ) + USE SIGNAL ; + - core_ci_0_i ( u_ci_0_i Y ) + USE SIGNAL ; + - core_ci_1_i ( u_ci_1_i Y ) + USE SIGNAL ; + - core_ci_2_i ( u_ci_2_i Y ) + USE SIGNAL ; + - core_ci_3_i ( u_ci_3_i Y ) + USE SIGNAL ; + - core_ci_4_i ( u_ci_4_i Y ) + USE SIGNAL ; + - core_ci_5_i ( u_ci_5_i Y ) + USE SIGNAL ; + - core_ci_6_i ( u_ci_6_i Y ) + USE SIGNAL ; + - core_ci_7_i ( u_ci_7_i Y ) + USE SIGNAL ; + - core_ci_8_i ( u_ci_8_i Y ) + USE SIGNAL ; + - core_ci_clk_i ( u_ci_clk_i Y ) + USE SIGNAL ; + - core_ci_tkn_o ( u_ci_tkn_o A ) + USE SIGNAL ; + - core_ci_v_i ( u_ci_v_i Y ) + USE SIGNAL ; + - core_clk_A_i ( u_clk_A_i Y ) + USE SIGNAL ; + - core_clk_B_i ( u_clk_B_i Y ) + USE SIGNAL ; + - core_clk_C_i ( u_clk_C_i Y ) + USE SIGNAL ; + - core_clk_async_reset_i ( u_clk_async_reset_i Y ) + USE SIGNAL ; + - core_clk_o ( u_clk_o A ) + USE SIGNAL ; + - core_co2_0_o ( u_co2_0_o A ) + USE SIGNAL ; + - core_co2_1_o ( u_co2_1_o A ) + USE SIGNAL ; + - core_co2_2_o ( u_co2_2_o A ) + USE SIGNAL ; + - core_co2_3_o ( u_co2_3_o A ) + USE SIGNAL ; + - core_co2_4_o ( u_co2_4_o A ) + USE SIGNAL ; + - core_co2_5_o ( u_co2_5_o A ) + USE SIGNAL ; + - core_co2_6_o ( u_co2_6_o A ) + USE SIGNAL ; + - core_co2_7_o ( u_co2_7_o A ) + USE SIGNAL ; + - core_co2_8_o ( u_co2_8_o A ) + USE SIGNAL ; + - core_co2_clk_o ( u_co2_clk_o A ) + USE SIGNAL ; + - core_co2_tkn_i ( u_co2_tkn_i Y ) + USE SIGNAL ; + - core_co2_v_o ( u_co2_v_o A ) + USE SIGNAL ; + - core_co_0_i ( u_co_0_i Y ) + USE SIGNAL ; + - core_co_1_i ( u_co_1_i Y ) + USE SIGNAL ; + - core_co_2_i ( u_co_2_i Y ) + USE SIGNAL ; + - core_co_3_i ( u_co_3_i Y ) + USE SIGNAL ; + - core_co_4_i ( u_co_4_i Y ) + USE SIGNAL ; + - core_co_5_i ( u_co_5_i Y ) + USE SIGNAL ; + - core_co_6_i ( u_co_6_i Y ) + USE SIGNAL ; + - core_co_7_i ( u_co_7_i Y ) + USE SIGNAL ; + - core_co_8_i ( u_co_8_i Y ) + USE SIGNAL ; + - core_co_clk_i ( u_co_clk_i Y ) + USE SIGNAL ; + - core_co_tkn_o ( u_co_tkn_o A ) + USE SIGNAL ; + - core_co_v_i ( u_co_v_i Y ) + USE SIGNAL ; + - core_core_async_reset_i ( u_core_async_reset_i Y ) + USE SIGNAL ; + - core_ddr_addr_0_o ( u_ddr_addr_0_o A ) + USE SIGNAL ; + - core_ddr_addr_10_o ( u_ddr_addr_10_o A ) + USE SIGNAL ; + - core_ddr_addr_11_o ( u_ddr_addr_11_o A ) + USE SIGNAL ; + - core_ddr_addr_12_o ( u_ddr_addr_12_o A ) + USE SIGNAL ; + - core_ddr_addr_13_o ( u_ddr_addr_13_o A ) + USE SIGNAL ; + - core_ddr_addr_14_o ( u_ddr_addr_14_o A ) + USE SIGNAL ; + - core_ddr_addr_15_o ( u_ddr_addr_15_o A ) + USE SIGNAL ; + - core_ddr_addr_1_o ( u_ddr_addr_1_o A ) + USE SIGNAL ; + - core_ddr_addr_2_o ( u_ddr_addr_2_o A ) + USE SIGNAL ; + - core_ddr_addr_3_o ( u_ddr_addr_3_o A ) + USE SIGNAL ; + - core_ddr_addr_4_o ( u_ddr_addr_4_o A ) + USE SIGNAL ; + - core_ddr_addr_5_o ( u_ddr_addr_5_o A ) + USE SIGNAL ; + - core_ddr_addr_6_o ( u_ddr_addr_6_o A ) + USE SIGNAL ; + - core_ddr_addr_7_o ( u_ddr_addr_7_o A ) + USE SIGNAL ; + - core_ddr_addr_8_o ( u_ddr_addr_8_o A ) + USE SIGNAL ; + - core_ddr_addr_9_o ( u_ddr_addr_9_o A ) + USE SIGNAL ; + - core_ddr_ba_0_o ( u_ddr_ba_0_o A ) + USE SIGNAL ; + - core_ddr_ba_1_o ( u_ddr_ba_1_o A ) + USE SIGNAL ; + - core_ddr_ba_2_o ( u_ddr_ba_2_o A ) + USE SIGNAL ; + - core_ddr_cas_n_o ( u_ddr_cas_n_o A ) + USE SIGNAL ; + - core_ddr_ck_n_o ( u_ddr_ck_n_o A ) + USE SIGNAL ; + - core_ddr_ck_p_o ( u_ddr_ck_p_o A ) + USE SIGNAL ; + - core_ddr_cke_o ( u_ddr_cke_o A ) + USE SIGNAL ; + - core_ddr_cs_n_o ( u_ddr_cs_n_o A ) + USE SIGNAL ; + - core_ddr_dm_0_o ( u_ddr_dm_0_o A ) + USE SIGNAL ; + - core_ddr_dm_1_o ( u_ddr_dm_1_o A ) + USE SIGNAL ; + - core_ddr_dm_2_o ( u_ddr_dm_2_o A ) + USE SIGNAL ; + - core_ddr_dm_3_o ( u_ddr_dm_3_o A ) + USE SIGNAL ; + - core_ddr_dq_0_i ( u_ddr_dq_0_io Y ) + USE SIGNAL ; + - core_ddr_dq_0_o ( u_ddr_dq_0_io A ) + USE SIGNAL ; + - core_ddr_dq_0_sel ( u_ddr_dq_0_io PU ) ( u_ddr_dq_0_io OE ) + USE SIGNAL ; + - core_ddr_dq_10_i ( u_ddr_dq_10_io Y ) + USE SIGNAL ; + - core_ddr_dq_10_o ( u_ddr_dq_10_io A ) + USE SIGNAL ; + - core_ddr_dq_10_sel ( u_ddr_dq_10_io PU ) ( u_ddr_dq_10_io OE ) + USE SIGNAL ; + - core_ddr_dq_11_i ( u_ddr_dq_11_io Y ) + USE SIGNAL ; + - core_ddr_dq_11_o ( u_ddr_dq_11_io A ) + USE SIGNAL ; + - core_ddr_dq_11_sel ( u_ddr_dq_11_io PU ) ( u_ddr_dq_11_io OE ) + USE SIGNAL ; + - core_ddr_dq_12_i ( u_ddr_dq_12_io Y ) + USE SIGNAL ; + - core_ddr_dq_12_o ( u_ddr_dq_12_io A ) + USE SIGNAL ; + - core_ddr_dq_12_sel ( u_ddr_dq_12_io PU ) ( u_ddr_dq_12_io OE ) + USE SIGNAL ; + - core_ddr_dq_13_i ( u_ddr_dq_13_io Y ) + USE SIGNAL ; + - core_ddr_dq_13_o ( u_ddr_dq_13_io A ) + USE SIGNAL ; + - core_ddr_dq_13_sel ( u_ddr_dq_13_io PU ) ( u_ddr_dq_13_io OE ) + USE SIGNAL ; + - core_ddr_dq_14_i ( u_ddr_dq_14_io Y ) + USE SIGNAL ; + - core_ddr_dq_14_o ( u_ddr_dq_14_io A ) + USE SIGNAL ; + - core_ddr_dq_14_sel ( u_ddr_dq_14_io PU ) ( u_ddr_dq_14_io OE ) + USE SIGNAL ; + - core_ddr_dq_15_i ( u_ddr_dq_15_io Y ) + USE SIGNAL ; + - core_ddr_dq_15_o ( u_ddr_dq_15_io A ) + USE SIGNAL ; + - core_ddr_dq_15_sel ( u_ddr_dq_15_io PU ) ( u_ddr_dq_15_io OE ) + USE SIGNAL ; + - core_ddr_dq_16_i ( u_ddr_dq_16_io Y ) + USE SIGNAL ; + - core_ddr_dq_16_o ( u_ddr_dq_16_io A ) + USE SIGNAL ; + - core_ddr_dq_16_sel ( u_ddr_dq_16_io PU ) ( u_ddr_dq_16_io OE ) + USE SIGNAL ; + - core_ddr_dq_17_i ( u_ddr_dq_17_io Y ) + USE SIGNAL ; + - core_ddr_dq_17_o ( u_ddr_dq_17_io A ) + USE SIGNAL ; + - core_ddr_dq_17_sel ( u_ddr_dq_17_io PU ) ( u_ddr_dq_17_io OE ) + USE SIGNAL ; + - core_ddr_dq_18_i ( u_ddr_dq_18_io Y ) + USE SIGNAL ; + - core_ddr_dq_18_o ( u_ddr_dq_18_io A ) + USE SIGNAL ; + - core_ddr_dq_18_sel ( u_ddr_dq_18_io PU ) ( u_ddr_dq_18_io OE ) + USE SIGNAL ; + - core_ddr_dq_19_i ( u_ddr_dq_19_io Y ) + USE SIGNAL ; + - core_ddr_dq_19_o ( u_ddr_dq_19_io A ) + USE SIGNAL ; + - core_ddr_dq_19_sel ( u_ddr_dq_19_io PU ) ( u_ddr_dq_19_io OE ) + USE SIGNAL ; + - core_ddr_dq_1_i ( u_ddr_dq_1_io Y ) + USE SIGNAL ; + - core_ddr_dq_1_o ( u_ddr_dq_1_io A ) + USE SIGNAL ; + - core_ddr_dq_1_sel ( u_ddr_dq_1_io PU ) ( u_ddr_dq_1_io OE ) + USE SIGNAL ; + - core_ddr_dq_20_i ( u_ddr_dq_20_io Y ) + USE SIGNAL ; + - core_ddr_dq_20_o ( u_ddr_dq_20_io A ) + USE SIGNAL ; + - core_ddr_dq_20_sel ( u_ddr_dq_20_io PU ) ( u_ddr_dq_20_io OE ) + USE SIGNAL ; + - core_ddr_dq_21_i ( u_ddr_dq_21_io Y ) + USE SIGNAL ; + - core_ddr_dq_21_o ( u_ddr_dq_21_io A ) + USE SIGNAL ; + - core_ddr_dq_21_sel ( u_ddr_dq_21_io PU ) ( u_ddr_dq_21_io OE ) + USE SIGNAL ; + - core_ddr_dq_22_i ( u_ddr_dq_22_io Y ) + USE SIGNAL ; + - core_ddr_dq_22_o ( u_ddr_dq_22_io A ) + USE SIGNAL ; + - core_ddr_dq_22_sel ( u_ddr_dq_22_io PU ) ( u_ddr_dq_22_io OE ) + USE SIGNAL ; + - core_ddr_dq_23_i ( u_ddr_dq_23_io Y ) + USE SIGNAL ; + - core_ddr_dq_23_o ( u_ddr_dq_23_io A ) + USE SIGNAL ; + - core_ddr_dq_23_sel ( u_ddr_dq_23_io PU ) ( u_ddr_dq_23_io OE ) + USE SIGNAL ; + - core_ddr_dq_24_i ( u_ddr_dq_24_io Y ) + USE SIGNAL ; + - core_ddr_dq_24_o ( u_ddr_dq_24_io A ) + USE SIGNAL ; + - core_ddr_dq_24_sel ( u_ddr_dq_24_io PU ) ( u_ddr_dq_24_io OE ) + USE SIGNAL ; + - core_ddr_dq_25_i ( u_ddr_dq_25_io Y ) + USE SIGNAL ; + - core_ddr_dq_25_o ( u_ddr_dq_25_io A ) + USE SIGNAL ; + - core_ddr_dq_25_sel ( u_ddr_dq_25_io PU ) ( u_ddr_dq_25_io OE ) + USE SIGNAL ; + - core_ddr_dq_26_i ( u_ddr_dq_26_io Y ) + USE SIGNAL ; + - core_ddr_dq_26_o ( u_ddr_dq_26_io A ) + USE SIGNAL ; + - core_ddr_dq_26_sel ( u_ddr_dq_26_io PU ) ( u_ddr_dq_26_io OE ) + USE SIGNAL ; + - core_ddr_dq_27_i ( u_ddr_dq_27_io Y ) + USE SIGNAL ; + - core_ddr_dq_27_o ( u_ddr_dq_27_io A ) + USE SIGNAL ; + - core_ddr_dq_27_sel ( u_ddr_dq_27_io PU ) ( u_ddr_dq_27_io OE ) + USE SIGNAL ; + - core_ddr_dq_28_i ( u_ddr_dq_28_io Y ) + USE SIGNAL ; + - core_ddr_dq_28_o ( u_ddr_dq_28_io A ) + USE SIGNAL ; + - core_ddr_dq_28_sel ( u_ddr_dq_28_io PU ) ( u_ddr_dq_28_io OE ) + USE SIGNAL ; + - core_ddr_dq_29_i ( u_ddr_dq_29_io Y ) + USE SIGNAL ; + - core_ddr_dq_29_o ( u_ddr_dq_29_io A ) + USE SIGNAL ; + - core_ddr_dq_29_sel ( u_ddr_dq_29_io PU ) ( u_ddr_dq_29_io OE ) + USE SIGNAL ; + - core_ddr_dq_2_i ( u_ddr_dq_2_io Y ) + USE SIGNAL ; + - core_ddr_dq_2_o ( u_ddr_dq_2_io A ) + USE SIGNAL ; + - core_ddr_dq_2_sel ( u_ddr_dq_2_io PU ) ( u_ddr_dq_2_io OE ) + USE SIGNAL ; + - core_ddr_dq_30_i ( u_ddr_dq_30_io Y ) + USE SIGNAL ; + - core_ddr_dq_30_o ( u_ddr_dq_30_io A ) + USE SIGNAL ; + - core_ddr_dq_30_sel ( u_ddr_dq_30_io PU ) ( u_ddr_dq_30_io OE ) + USE SIGNAL ; + - core_ddr_dq_31_i ( u_ddr_dq_31_io Y ) + USE SIGNAL ; + - core_ddr_dq_31_o ( u_ddr_dq_31_io A ) + USE SIGNAL ; + - core_ddr_dq_31_sel ( u_ddr_dq_31_io PU ) ( u_ddr_dq_31_io OE ) + USE SIGNAL ; + - core_ddr_dq_3_i ( u_ddr_dq_3_io Y ) + USE SIGNAL ; + - core_ddr_dq_3_o ( u_ddr_dq_3_io A ) + USE SIGNAL ; + - core_ddr_dq_3_sel ( u_ddr_dq_3_io PU ) ( u_ddr_dq_3_io OE ) + USE SIGNAL ; + - core_ddr_dq_4_i ( u_ddr_dq_4_io Y ) + USE SIGNAL ; + - core_ddr_dq_4_o ( u_ddr_dq_4_io A ) + USE SIGNAL ; + - core_ddr_dq_4_sel ( u_ddr_dq_4_io PU ) ( u_ddr_dq_4_io OE ) + USE SIGNAL ; + - core_ddr_dq_5_i ( u_ddr_dq_5_io Y ) + USE SIGNAL ; + - core_ddr_dq_5_o ( u_ddr_dq_5_io A ) + USE SIGNAL ; + - core_ddr_dq_5_sel ( u_ddr_dq_5_io PU ) ( u_ddr_dq_5_io OE ) + USE SIGNAL ; + - core_ddr_dq_6_i ( u_ddr_dq_6_io Y ) + USE SIGNAL ; + - core_ddr_dq_6_o ( u_ddr_dq_6_io A ) + USE SIGNAL ; + - core_ddr_dq_6_sel ( u_ddr_dq_6_io PU ) ( u_ddr_dq_6_io OE ) + USE SIGNAL ; + - core_ddr_dq_7_i ( u_ddr_dq_7_io Y ) + USE SIGNAL ; + - core_ddr_dq_7_o ( u_ddr_dq_7_io A ) + USE SIGNAL ; + - core_ddr_dq_7_sel ( u_ddr_dq_7_io PU ) ( u_ddr_dq_7_io OE ) + USE SIGNAL ; + - core_ddr_dq_8_i ( u_ddr_dq_8_io Y ) + USE SIGNAL ; + - core_ddr_dq_8_o ( u_ddr_dq_8_io A ) + USE SIGNAL ; + - core_ddr_dq_8_sel ( u_ddr_dq_8_io PU ) ( u_ddr_dq_8_io OE ) + USE SIGNAL ; + - core_ddr_dq_9_i ( u_ddr_dq_9_io Y ) + USE SIGNAL ; + - core_ddr_dq_9_o ( u_ddr_dq_9_io A ) + USE SIGNAL ; + - core_ddr_dq_9_sel ( u_ddr_dq_9_io PU ) ( u_ddr_dq_9_io OE ) + USE SIGNAL ; + - core_ddr_dqs_n_0_i ( u_ddr_dqs_n_0_io Y ) + USE SIGNAL ; + - core_ddr_dqs_n_0_o ( u_ddr_dqs_n_0_io A ) + USE SIGNAL ; + - core_ddr_dqs_n_0_sel ( u_ddr_dqs_n_0_io PU ) ( u_ddr_dqs_n_0_io OE ) + USE SIGNAL ; + - core_ddr_dqs_n_1_i ( u_ddr_dqs_n_1_io Y ) + USE SIGNAL ; + - core_ddr_dqs_n_1_o ( u_ddr_dqs_n_1_io A ) + USE SIGNAL ; + - core_ddr_dqs_n_1_sel ( u_ddr_dqs_n_1_io PU ) ( u_ddr_dqs_n_1_io OE ) + USE SIGNAL ; + - core_ddr_dqs_n_2_i ( u_ddr_dqs_n_2_io Y ) + USE SIGNAL ; + - core_ddr_dqs_n_2_o ( u_ddr_dqs_n_2_io A ) + USE SIGNAL ; + - core_ddr_dqs_n_2_sel ( u_ddr_dqs_n_2_io PU ) ( u_ddr_dqs_n_2_io OE ) + USE SIGNAL ; + - core_ddr_dqs_n_3_i ( u_ddr_dqs_n_3_io Y ) + USE SIGNAL ; + - core_ddr_dqs_n_3_o ( u_ddr_dqs_n_3_io A ) + USE SIGNAL ; + - core_ddr_dqs_n_3_sel ( u_ddr_dqs_n_3_io PU ) ( u_ddr_dqs_n_3_io OE ) + USE SIGNAL ; + - core_ddr_dqs_p_0_i ( u_ddr_dqs_p_0_io Y ) + USE SIGNAL ; + - core_ddr_dqs_p_0_o ( u_ddr_dqs_p_0_io A ) + USE SIGNAL ; + - core_ddr_dqs_p_0_sel ( u_ddr_dqs_p_0_io PU ) ( u_ddr_dqs_p_0_io OE ) + USE SIGNAL ; + - core_ddr_dqs_p_1_i ( u_ddr_dqs_p_1_io Y ) + USE SIGNAL ; + - core_ddr_dqs_p_1_o ( u_ddr_dqs_p_1_io A ) + USE SIGNAL ; + - core_ddr_dqs_p_1_sel ( u_ddr_dqs_p_1_io PU ) ( u_ddr_dqs_p_1_io OE ) + USE SIGNAL ; + - core_ddr_dqs_p_2_i ( u_ddr_dqs_p_2_io Y ) + USE SIGNAL ; + - core_ddr_dqs_p_2_o ( u_ddr_dqs_p_2_io A ) + USE SIGNAL ; + - core_ddr_dqs_p_2_sel ( u_ddr_dqs_p_2_io PU ) ( u_ddr_dqs_p_2_io OE ) + USE SIGNAL ; + - core_ddr_dqs_p_3_i ( u_ddr_dqs_p_3_io Y ) + USE SIGNAL ; + - core_ddr_dqs_p_3_o ( u_ddr_dqs_p_3_io A ) + USE SIGNAL ; + - core_ddr_dqs_p_3_sel ( u_ddr_dqs_p_3_io PU ) ( u_ddr_dqs_p_3_io OE ) + USE SIGNAL ; + - core_ddr_odt_o ( u_ddr_odt_o A ) + USE SIGNAL ; + - core_ddr_ras_n_o ( u_ddr_ras_n_o A ) + USE SIGNAL ; + - core_ddr_reset_n_o ( u_ddr_reset_n_o A ) + USE SIGNAL ; + - core_ddr_we_n_o ( u_ddr_we_n_o A ) + USE SIGNAL ; + - core_misc_o ( u_misc_o A ) + USE SIGNAL ; + - core_sel_0_i ( u_sel_0_i Y ) + USE SIGNAL ; + - core_sel_1_i ( u_sel_1_i Y ) + USE SIGNAL ; + - core_sel_2_i ( u_sel_2_i Y ) + USE SIGNAL ; + - p_bsg_tag_clk_i ( PIN p_bsg_tag_clk_i ) ( u_bsg_tag_clk_i PAD ) + USE SIGNAL ; + - p_bsg_tag_clk_o ( PIN p_bsg_tag_clk_o ) ( u_bsg_tag_clk_o PAD ) + USE SIGNAL ; + - p_bsg_tag_data_i ( PIN p_bsg_tag_data_i ) ( u_bsg_tag_data_i PAD ) + USE SIGNAL ; + - p_bsg_tag_data_o ( PIN p_bsg_tag_data_o ) ( u_bsg_tag_data_o PAD ) + USE SIGNAL ; + - p_bsg_tag_en_i ( PIN p_bsg_tag_en_i ) ( u_bsg_tag_en_i PAD ) + USE SIGNAL ; + - p_ci2_0_o ( PIN p_ci2_0_o ) ( u_ci2_0_o PAD ) + USE SIGNAL ; + - p_ci2_1_o ( PIN p_ci2_1_o ) ( u_ci2_1_o PAD ) + USE SIGNAL ; + - p_ci2_2_o ( PIN p_ci2_2_o ) ( u_ci2_2_o PAD ) + USE SIGNAL ; + - p_ci2_3_o ( PIN p_ci2_3_o ) ( u_ci2_3_o PAD ) + USE SIGNAL ; + - p_ci2_4_o ( PIN p_ci2_4_o ) ( u_ci2_4_o PAD ) + USE SIGNAL ; + - p_ci2_5_o ( PIN p_ci2_5_o ) ( u_ci2_5_o PAD ) + USE SIGNAL ; + - p_ci2_6_o ( PIN p_ci2_6_o ) ( u_ci2_6_o PAD ) + USE SIGNAL ; + - p_ci2_7_o ( PIN p_ci2_7_o ) ( u_ci2_7_o PAD ) + USE SIGNAL ; + - p_ci2_8_o ( PIN p_ci2_8_o ) ( u_ci2_8_o PAD ) + USE SIGNAL ; + - p_ci2_clk_o ( PIN p_ci2_clk_o ) ( u_ci2_clk_o PAD ) + USE SIGNAL ; + - p_ci2_tkn_i ( PIN p_ci2_tkn_i ) ( u_ci2_tkn_i PAD ) + USE SIGNAL ; + - p_ci2_v_o ( PIN p_ci2_v_o ) ( u_ci2_v_o PAD ) + USE SIGNAL ; + - p_ci_0_i ( PIN p_ci_0_i ) ( u_ci_0_i PAD ) + USE SIGNAL ; + - p_ci_1_i ( PIN p_ci_1_i ) ( u_ci_1_i PAD ) + USE SIGNAL ; + - p_ci_2_i ( PIN p_ci_2_i ) ( u_ci_2_i PAD ) + USE SIGNAL ; + - p_ci_3_i ( PIN p_ci_3_i ) ( u_ci_3_i PAD ) + USE SIGNAL ; + - p_ci_4_i ( PIN p_ci_4_i ) ( u_ci_4_i PAD ) + USE SIGNAL ; + - p_ci_5_i ( PIN p_ci_5_i ) ( u_ci_5_i PAD ) + USE SIGNAL ; + - p_ci_6_i ( PIN p_ci_6_i ) ( u_ci_6_i PAD ) + USE SIGNAL ; + - p_ci_7_i ( PIN p_ci_7_i ) ( u_ci_7_i PAD ) + USE SIGNAL ; + - p_ci_8_i ( PIN p_ci_8_i ) ( u_ci_8_i PAD ) + USE SIGNAL ; + - p_ci_clk_i ( PIN p_ci_clk_i ) ( u_ci_clk_i PAD ) + USE SIGNAL ; + - p_ci_tkn_o ( PIN p_ci_tkn_o ) ( u_ci_tkn_o PAD ) + USE SIGNAL ; + - p_ci_v_i ( PIN p_ci_v_i ) ( u_ci_v_i PAD ) + USE SIGNAL ; + - p_clk_A_i ( PIN p_clk_A_i ) ( u_clk_A_i PAD ) + USE SIGNAL ; + - p_clk_B_i ( PIN p_clk_B_i ) ( u_clk_B_i PAD ) + USE SIGNAL ; + - p_clk_C_i ( PIN p_clk_C_i ) ( u_clk_C_i PAD ) + USE SIGNAL ; + - p_clk_async_reset_i ( PIN p_clk_async_reset_i ) ( u_clk_async_reset_i PAD ) + USE SIGNAL ; + - p_clk_o ( PIN p_clk_o ) ( u_clk_o PAD ) + USE SIGNAL ; + - p_co2_0_o ( PIN p_co2_0_o ) ( u_co2_0_o PAD ) + USE SIGNAL ; + - p_co2_1_o ( PIN p_co2_1_o ) ( u_co2_1_o PAD ) + USE SIGNAL ; + - p_co2_2_o ( PIN p_co2_2_o ) ( u_co2_2_o PAD ) + USE SIGNAL ; + - p_co2_3_o ( PIN p_co2_3_o ) ( u_co2_3_o PAD ) + USE SIGNAL ; + - p_co2_4_o ( PIN p_co2_4_o ) ( u_co2_4_o PAD ) + USE SIGNAL ; + - p_co2_5_o ( PIN p_co2_5_o ) ( u_co2_5_o PAD ) + USE SIGNAL ; + - p_co2_6_o ( PIN p_co2_6_o ) ( u_co2_6_o PAD ) + USE SIGNAL ; + - p_co2_7_o ( PIN p_co2_7_o ) ( u_co2_7_o PAD ) + USE SIGNAL ; + - p_co2_8_o ( PIN p_co2_8_o ) ( u_co2_8_o PAD ) + USE SIGNAL ; + - p_co2_clk_o ( PIN p_co2_clk_o ) ( u_co2_clk_o PAD ) + USE SIGNAL ; + - p_co2_tkn_i ( PIN p_co2_tkn_i ) ( u_co2_tkn_i PAD ) + USE SIGNAL ; + - p_co2_v_o ( PIN p_co2_v_o ) ( u_co2_v_o PAD ) + USE SIGNAL ; + - p_co_0_i ( PIN p_co_0_i ) ( u_co_0_i PAD ) + USE SIGNAL ; + - p_co_1_i ( PIN p_co_1_i ) ( u_co_1_i PAD ) + USE SIGNAL ; + - p_co_2_i ( PIN p_co_2_i ) ( u_co_2_i PAD ) + USE SIGNAL ; + - p_co_3_i ( PIN p_co_3_i ) ( u_co_3_i PAD ) + USE SIGNAL ; + - p_co_4_i ( PIN p_co_4_i ) ( u_co_4_i PAD ) + USE SIGNAL ; + - p_co_5_i ( PIN p_co_5_i ) ( u_co_5_i PAD ) + USE SIGNAL ; + - p_co_6_i ( PIN p_co_6_i ) ( u_co_6_i PAD ) + USE SIGNAL ; + - p_co_7_i ( PIN p_co_7_i ) ( u_co_7_i PAD ) + USE SIGNAL ; + - p_co_8_i ( PIN p_co_8_i ) ( u_co_8_i PAD ) + USE SIGNAL ; + - p_co_clk_i ( PIN p_co_clk_i ) ( u_co_clk_i PAD ) + USE SIGNAL ; + - p_co_tkn_o ( PIN p_co_tkn_o ) ( u_co_tkn_o PAD ) + USE SIGNAL ; + - p_co_v_i ( PIN p_co_v_i ) ( u_co_v_i PAD ) + USE SIGNAL ; + - p_core_async_reset_i ( PIN p_core_async_reset_i ) ( u_core_async_reset_i PAD ) + USE SIGNAL ; + - p_ddr_addr_0_o ( PIN p_ddr_addr_0_o ) ( u_ddr_addr_0_o PAD ) + USE SIGNAL ; + - p_ddr_addr_10_o ( PIN p_ddr_addr_10_o ) ( u_ddr_addr_10_o PAD ) + USE SIGNAL ; + - p_ddr_addr_11_o ( PIN p_ddr_addr_11_o ) ( u_ddr_addr_11_o PAD ) + USE SIGNAL ; + - p_ddr_addr_12_o ( PIN p_ddr_addr_12_o ) ( u_ddr_addr_12_o PAD ) + USE SIGNAL ; + - p_ddr_addr_13_o ( PIN p_ddr_addr_13_o ) ( u_ddr_addr_13_o PAD ) + USE SIGNAL ; + - p_ddr_addr_14_o ( PIN p_ddr_addr_14_o ) ( u_ddr_addr_14_o PAD ) + USE SIGNAL ; + - p_ddr_addr_15_o ( PIN p_ddr_addr_15_o ) ( u_ddr_addr_15_o PAD ) + USE SIGNAL ; + - p_ddr_addr_1_o ( PIN p_ddr_addr_1_o ) ( u_ddr_addr_1_o PAD ) + USE SIGNAL ; + - p_ddr_addr_2_o ( PIN p_ddr_addr_2_o ) ( u_ddr_addr_2_o PAD ) + USE SIGNAL ; + - p_ddr_addr_3_o ( PIN p_ddr_addr_3_o ) ( u_ddr_addr_3_o PAD ) + USE SIGNAL ; + - p_ddr_addr_4_o ( PIN p_ddr_addr_4_o ) ( u_ddr_addr_4_o PAD ) + USE SIGNAL ; + - p_ddr_addr_5_o ( PIN p_ddr_addr_5_o ) ( u_ddr_addr_5_o PAD ) + USE SIGNAL ; + - p_ddr_addr_6_o ( PIN p_ddr_addr_6_o ) ( u_ddr_addr_6_o PAD ) + USE SIGNAL ; + - p_ddr_addr_7_o ( PIN p_ddr_addr_7_o ) ( u_ddr_addr_7_o PAD ) + USE SIGNAL ; + - p_ddr_addr_8_o ( PIN p_ddr_addr_8_o ) ( u_ddr_addr_8_o PAD ) + USE SIGNAL ; + - p_ddr_addr_9_o ( PIN p_ddr_addr_9_o ) ( u_ddr_addr_9_o PAD ) + USE SIGNAL ; + - p_ddr_ba_0_o ( PIN p_ddr_ba_0_o ) ( u_ddr_ba_0_o PAD ) + USE SIGNAL ; + - p_ddr_ba_1_o ( PIN p_ddr_ba_1_o ) ( u_ddr_ba_1_o PAD ) + USE SIGNAL ; + - p_ddr_ba_2_o ( PIN p_ddr_ba_2_o ) ( u_ddr_ba_2_o PAD ) + USE SIGNAL ; + - p_ddr_cas_n_o ( PIN p_ddr_cas_n_o ) ( u_ddr_cas_n_o PAD ) + USE SIGNAL ; + - p_ddr_ck_n_o ( PIN p_ddr_ck_n_o ) ( u_ddr_ck_n_o PAD ) + USE SIGNAL ; + - p_ddr_ck_p_o ( PIN p_ddr_ck_p_o ) ( u_ddr_ck_p_o PAD ) + USE SIGNAL ; + - p_ddr_cke_o ( PIN p_ddr_cke_o ) ( u_ddr_cke_o PAD ) + USE SIGNAL ; + - p_ddr_cs_n_o ( PIN p_ddr_cs_n_o ) ( u_ddr_cs_n_o PAD ) + USE SIGNAL ; + - p_ddr_dm_0_o ( PIN p_ddr_dm_0_o ) ( u_ddr_dm_0_o PAD ) + USE SIGNAL ; + - p_ddr_dm_1_o ( PIN p_ddr_dm_1_o ) ( u_ddr_dm_1_o PAD ) + USE SIGNAL ; + - p_ddr_dm_2_o ( PIN p_ddr_dm_2_o ) ( u_ddr_dm_2_o PAD ) + USE SIGNAL ; + - p_ddr_dm_3_o ( PIN p_ddr_dm_3_o ) ( u_ddr_dm_3_o PAD ) + USE SIGNAL ; + - p_ddr_dq_0_io ( PIN p_ddr_dq_0_io ) ( u_ddr_dq_0_io PAD ) + USE SIGNAL ; + - p_ddr_dq_10_io ( PIN p_ddr_dq_10_io ) ( u_ddr_dq_10_io PAD ) + USE SIGNAL ; + - p_ddr_dq_11_io ( PIN p_ddr_dq_11_io ) ( u_ddr_dq_11_io PAD ) + USE SIGNAL ; + - p_ddr_dq_12_io ( PIN p_ddr_dq_12_io ) ( u_ddr_dq_12_io PAD ) + USE SIGNAL ; + - p_ddr_dq_13_io ( PIN p_ddr_dq_13_io ) ( u_ddr_dq_13_io PAD ) + USE SIGNAL ; + - p_ddr_dq_14_io ( PIN p_ddr_dq_14_io ) ( u_ddr_dq_14_io PAD ) + USE SIGNAL ; + - p_ddr_dq_15_io ( PIN p_ddr_dq_15_io ) ( u_ddr_dq_15_io PAD ) + USE SIGNAL ; + - p_ddr_dq_16_io ( PIN p_ddr_dq_16_io ) ( u_ddr_dq_16_io PAD ) + USE SIGNAL ; + - p_ddr_dq_17_io ( PIN p_ddr_dq_17_io ) ( u_ddr_dq_17_io PAD ) + USE SIGNAL ; + - p_ddr_dq_18_io ( PIN p_ddr_dq_18_io ) ( u_ddr_dq_18_io PAD ) + USE SIGNAL ; + - p_ddr_dq_19_io ( PIN p_ddr_dq_19_io ) ( u_ddr_dq_19_io PAD ) + USE SIGNAL ; + - p_ddr_dq_1_io ( PIN p_ddr_dq_1_io ) ( u_ddr_dq_1_io PAD ) + USE SIGNAL ; + - p_ddr_dq_20_io ( PIN p_ddr_dq_20_io ) ( u_ddr_dq_20_io PAD ) + USE SIGNAL ; + - p_ddr_dq_21_io ( PIN p_ddr_dq_21_io ) ( u_ddr_dq_21_io PAD ) + USE SIGNAL ; + - p_ddr_dq_22_io ( PIN p_ddr_dq_22_io ) ( u_ddr_dq_22_io PAD ) + USE SIGNAL ; + - p_ddr_dq_23_io ( PIN p_ddr_dq_23_io ) ( u_ddr_dq_23_io PAD ) + USE SIGNAL ; + - p_ddr_dq_24_io ( PIN p_ddr_dq_24_io ) ( u_ddr_dq_24_io PAD ) + USE SIGNAL ; + - p_ddr_dq_25_io ( PIN p_ddr_dq_25_io ) ( u_ddr_dq_25_io PAD ) + USE SIGNAL ; + - p_ddr_dq_26_io ( PIN p_ddr_dq_26_io ) ( u_ddr_dq_26_io PAD ) + USE SIGNAL ; + - p_ddr_dq_27_io ( PIN p_ddr_dq_27_io ) ( u_ddr_dq_27_io PAD ) + USE SIGNAL ; + - p_ddr_dq_28_io ( PIN p_ddr_dq_28_io ) ( u_ddr_dq_28_io PAD ) + USE SIGNAL ; + - p_ddr_dq_29_io ( PIN p_ddr_dq_29_io ) ( u_ddr_dq_29_io PAD ) + USE SIGNAL ; + - p_ddr_dq_2_io ( PIN p_ddr_dq_2_io ) ( u_ddr_dq_2_io PAD ) + USE SIGNAL ; + - p_ddr_dq_30_io ( PIN p_ddr_dq_30_io ) ( u_ddr_dq_30_io PAD ) + USE SIGNAL ; + - p_ddr_dq_31_io ( PIN p_ddr_dq_31_io ) ( u_ddr_dq_31_io PAD ) + USE SIGNAL ; + - p_ddr_dq_3_io ( PIN p_ddr_dq_3_io ) ( u_ddr_dq_3_io PAD ) + USE SIGNAL ; + - p_ddr_dq_4_io ( PIN p_ddr_dq_4_io ) ( u_ddr_dq_4_io PAD ) + USE SIGNAL ; + - p_ddr_dq_5_io ( PIN p_ddr_dq_5_io ) ( u_ddr_dq_5_io PAD ) + USE SIGNAL ; + - p_ddr_dq_6_io ( PIN p_ddr_dq_6_io ) ( u_ddr_dq_6_io PAD ) + USE SIGNAL ; + - p_ddr_dq_7_io ( PIN p_ddr_dq_7_io ) ( u_ddr_dq_7_io PAD ) + USE SIGNAL ; + - p_ddr_dq_8_io ( PIN p_ddr_dq_8_io ) ( u_ddr_dq_8_io PAD ) + USE SIGNAL ; + - p_ddr_dq_9_io ( PIN p_ddr_dq_9_io ) ( u_ddr_dq_9_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_n_0_io ( PIN p_ddr_dqs_n_0_io ) ( u_ddr_dqs_n_0_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_n_1_io ( PIN p_ddr_dqs_n_1_io ) ( u_ddr_dqs_n_1_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_n_2_io ( PIN p_ddr_dqs_n_2_io ) ( u_ddr_dqs_n_2_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_n_3_io ( PIN p_ddr_dqs_n_3_io ) ( u_ddr_dqs_n_3_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_p_0_io ( PIN p_ddr_dqs_p_0_io ) ( u_ddr_dqs_p_0_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_p_1_io ( PIN p_ddr_dqs_p_1_io ) ( u_ddr_dqs_p_1_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_p_2_io ( PIN p_ddr_dqs_p_2_io ) ( u_ddr_dqs_p_2_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_p_3_io ( PIN p_ddr_dqs_p_3_io ) ( u_ddr_dqs_p_3_io PAD ) + USE SIGNAL ; + - p_ddr_odt_o ( PIN p_ddr_odt_o ) ( u_ddr_odt_o PAD ) + USE SIGNAL ; + - p_ddr_ras_n_o ( PIN p_ddr_ras_n_o ) ( u_ddr_ras_n_o PAD ) + USE SIGNAL ; + - p_ddr_reset_n_o ( PIN p_ddr_reset_n_o ) ( u_ddr_reset_n_o PAD ) + USE SIGNAL ; + - p_ddr_we_n_o ( PIN p_ddr_we_n_o ) ( u_ddr_we_n_o PAD ) + USE SIGNAL ; + - p_misc_o ( PIN p_misc_o ) ( u_misc_o PAD ) + USE SIGNAL ; + - p_sel_0_i ( PIN p_sel_0_i ) ( u_sel_0_i PAD ) + USE SIGNAL ; + - p_sel_1_i ( PIN p_sel_1_i ) ( u_sel_1_i PAD ) + USE SIGNAL ; + - p_sel_2_i ( PIN p_sel_2_i ) ( u_sel_2_i PAD ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/src/pad/test/make_io_sites_rotations.ok b/src/pad/test/make_io_sites_rotations.ok new file mode 100644 index 00000000000..ec16d7b7955 --- /dev/null +++ b/src/pad/test/make_io_sites_rotations.ok @@ -0,0 +1,7 @@ +[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells +[INFO ODB-0227] LEF file: Nangate45_io/dummy_pads.lef, created 25 library cells +[INFO ODB-0128] Design: soc_bsg_black_parrot +[INFO ODB-0130] Created 135 pins. +[INFO ODB-0131] Created 267 components and 2277 component-terminals. +[INFO ODB-0133] Created 350 nets and 390 connections. +No differences found. diff --git a/src/pad/test/make_io_sites_rotations.tcl b/src/pad/test/make_io_sites_rotations.tcl new file mode 100644 index 00000000000..667c6961a14 --- /dev/null +++ b/src/pad/test/make_io_sites_rotations.tcl @@ -0,0 +1,17 @@ +# Test for making sites for the IO sites +source "helpers.tcl" + +# Init chip +read_lef Nangate45/Nangate45.lef +read_lef Nangate45_io/dummy_pads.lef + +read_def Nangate45_blackparrot/floorplan.def + +# Test make_io_sites +make_io_sites -horizontal_site IOSITE -vertical_site IOSITE2 -corner_site IOSITE -offset 15 \ + -rotation_horizontal R90 \ + -rotation_vertical MY + +set def_file [make_result_file "make_io_sites_rotations.def"] +write_def $def_file +diff_files $def_file "make_io_sites_rotations.defok" diff --git a/src/pad/test/regression_tests.tcl b/src/pad/test/regression_tests.tcl index 1308af95dc0..d35891b39bd 100644 --- a/src/pad/test/regression_tests.tcl +++ b/src/pad/test/regression_tests.tcl @@ -8,6 +8,7 @@ record_tests { make_corner_sites make_io_sites make_io_sites_different_sites + make_io_sites_rotations non_top_layer place_pad place_pad_with_bumps From 078d7b9c1b8028a2769faf47385cc1cf54a40af4 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Wed, 25 Sep 2024 09:44:35 -0400 Subject: [PATCH 4/7] pad: fix make_corner_sites test to ensure corners are inside the die Signed-off-by: Peter Gadfort --- src/pad/test/make_corner_sites.defok | 16 ++++++++-------- src/pad/test/make_corner_sites.tcl | 2 +- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/pad/test/make_corner_sites.defok b/src/pad/test/make_corner_sites.defok index fd10ae3a900..3e7c2d20780 100644 --- a/src/pad/test/make_corner_sites.defok +++ b/src/pad/test/make_corner_sites.defok @@ -4,14 +4,14 @@ BUSBITCHARS "[]" ; DESIGN soc_bsg_black_parrot ; UNITS DISTANCE MICRONS 2000 ; DIEAREA ( 0 0 ) ( 6000000 6000000 ) ; -ROW IO_CORNER_NORTH_WEST IOSITE 30000 5690000 FW DO 140 BY 1 STEP 2000 0 ; -ROW IO_CORNER_NORTH_EAST IOSITE 5690000 5690000 W DO 140 BY 1 STEP 2000 0 ; -ROW IO_CORNER_SOUTH_EAST IOSITE 5690000 30000 FE DO 140 BY 1 STEP 2000 0 ; -ROW IO_CORNER_SOUTH_WEST IOSITE 30000 30000 E DO 140 BY 1 STEP 2000 0 ; -ROW IO_NORTH IOSITE 588000 5690000 FS DO 2690 BY 1 STEP 2000 0 ; -ROW IO_EAST IOSITE 5690000 32000 W DO 1 BY 2690 STEP 0 2000 ; -ROW IO_SOUTH IOSITE 588000 30000 N DO 2690 BY 1 STEP 2000 0 ; -ROW IO_WEST IOSITE 30000 32000 FW DO 1 BY 2690 STEP 0 2000 ; +ROW IO_CORNER_NORTH_WEST IOSITE 30000 5690000 S DO 140 BY 1 STEP 2000 0 ; +ROW IO_CORNER_NORTH_EAST IOSITE 5690000 5690000 FS DO 140 BY 1 STEP 2000 0 ; +ROW IO_CORNER_SOUTH_EAST IOSITE 5690000 30000 N DO 140 BY 1 STEP 2000 0 ; +ROW IO_CORNER_SOUTH_WEST IOSITE 30000 30000 FN DO 140 BY 1 STEP 2000 0 ; +ROW IO_NORTH IOSITE 310000 5690000 FS DO 2690 BY 1 STEP 2000 0 ; +ROW IO_EAST IOSITE 5690000 310000 W DO 1 BY 2690 STEP 0 2000 ; +ROW IO_SOUTH IOSITE 310000 30000 N DO 2690 BY 1 STEP 2000 0 ; +ROW IO_WEST IOSITE 30000 310000 FW DO 1 BY 2690 STEP 0 2000 ; TRACKS X 190 DO 21428 STEP 280 LAYER metal1 ; TRACKS Y 140 DO 21428 STEP 280 LAYER metal1 ; TRACKS X 190 DO 15789 STEP 380 LAYER metal2 ; diff --git a/src/pad/test/make_corner_sites.tcl b/src/pad/test/make_corner_sites.tcl index 2bd31611388..e6e84ff9c88 100644 --- a/src/pad/test/make_corner_sites.tcl +++ b/src/pad/test/make_corner_sites.tcl @@ -13,7 +13,7 @@ make_io_sites \ -vertical_site IOSITE \ -corner_site IOSITE \ -offset 15 \ - -rotation_corner R270 + -rotation_corner MY set def_file [make_result_file "make_corner_sites.def"] write_def $def_file From 01fa3af11501005e7f833244b34c7ce4207b7868 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Wed, 25 Sep 2024 09:46:50 -0400 Subject: [PATCH 5/7] pad: make_io_sites_different_sites use custom CORNER site to make test easier to view Signed-off-by: Peter Gadfort --- src/pad/test/make_io_sites_different_sites.defok | 16 ++++++++-------- src/pad/test/make_io_sites_different_sites.tcl | 3 ++- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/src/pad/test/make_io_sites_different_sites.defok b/src/pad/test/make_io_sites_different_sites.defok index e77bce8651d..ed3855508c1 100644 --- a/src/pad/test/make_io_sites_different_sites.defok +++ b/src/pad/test/make_io_sites_different_sites.defok @@ -4,14 +4,14 @@ BUSBITCHARS "[]" ; DESIGN soc_bsg_black_parrot ; UNITS DISTANCE MICRONS 2000 ; DIEAREA ( 0 0 ) ( 6000000 6000000 ) ; -ROW IO_CORNER_NORTH_WEST IOSITE 30000 5690000 FS DO 50 BY 1 STEP 2000 0 ; -ROW IO_CORNER_NORTH_EAST IOSITE 5968000 5690000 S DO 50 BY 1 STEP 2000 0 ; -ROW IO_CORNER_SOUTH_EAST IOSITE 5968000 30000 FN DO 50 BY 1 STEP 2000 0 ; -ROW IO_CORNER_SOUTH_WEST IOSITE 30000 30000 N DO 50 BY 1 STEP 2000 0 ; -ROW IO_NORTH VERTICAL 130000 5870000 FS DO 2968 BY 1 STEP 2000 0 ; -ROW IO_EAST HORIZONTAL 5870000 310000 N DO 1 BY 2690 STEP 0 2000 ; -ROW IO_SOUTH VERTICAL 130000 30000 N DO 2968 BY 1 STEP 2000 0 ; -ROW IO_WEST HORIZONTAL 30000 310000 FN DO 1 BY 2690 STEP 0 2000 ; +ROW IO_CORNER_NORTH_WEST CORNER 30000 5870000 FS DO 1 BY 1 STEP 100000 0 ; +ROW IO_CORNER_NORTH_EAST CORNER 5870000 5870000 S DO 1 BY 1 STEP 100000 0 ; +ROW IO_CORNER_SOUTH_EAST CORNER 5870000 30000 FN DO 1 BY 1 STEP 100000 0 ; +ROW IO_CORNER_SOUTH_WEST CORNER 30000 30000 N DO 1 BY 1 STEP 100000 0 ; +ROW IO_NORTH VERTICAL 130000 5870000 FS DO 2870 BY 1 STEP 2000 0 ; +ROW IO_EAST HORIZONTAL 5870000 130000 FN DO 1 BY 2870 STEP 0 2000 ; +ROW IO_SOUTH VERTICAL 130000 30000 N DO 2870 BY 1 STEP 2000 0 ; +ROW IO_WEST HORIZONTAL 30000 130000 N DO 1 BY 2870 STEP 0 2000 ; TRACKS X 190 DO 21428 STEP 280 LAYER metal1 ; TRACKS Y 140 DO 21428 STEP 280 LAYER metal1 ; TRACKS X 190 DO 15789 STEP 380 LAYER metal2 ; diff --git a/src/pad/test/make_io_sites_different_sites.tcl b/src/pad/test/make_io_sites_different_sites.tcl index ba8c849a05b..81a07206a92 100644 --- a/src/pad/test/make_io_sites_different_sites.tcl +++ b/src/pad/test/make_io_sites_different_sites.tcl @@ -9,9 +9,10 @@ read_def Nangate45_blackparrot/floorplan.def make_fake_io_site -name HORIZONTAL -width 50 -height 1 make_fake_io_site -name VERTICAL -width 1 -height 50 +make_fake_io_site -name CORNER -width 50 -height 50 # Test make_io_sites -make_io_sites -horizontal_site HORIZONTAL -vertical_site VERTICAL -corner_site IOSITE -offset 15 +make_io_sites -horizontal_site HORIZONTAL -vertical_site VERTICAL -corner_site CORNER -offset 15 set def_file [make_result_file "make_io_sites_different_sites.def"] write_def $def_file From 2b9a53966af8edbd3b02dafbf273b95b68bc51f9 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Wed, 25 Sep 2024 09:56:36 -0400 Subject: [PATCH 6/7] pad: reference south and west as base rotations Signed-off-by: Peter Gadfort --- src/pad/src/ICeWall.cpp | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/src/pad/src/ICeWall.cpp b/src/pad/src/ICeWall.cpp index 75c8c53e10c..86094e96d91 100644 --- a/src/pad/src/ICeWall.cpp +++ b/src/pad/src/ICeWall.cpp @@ -459,19 +459,22 @@ void ICeWall::makeIORow(odb::dbSite* horizontal_site, sites, site_width); }; + const odb::dbOrientType south_rotation_ver = odb::dbOrientType::R0; + const odb::dbOrientType north_rotation_ver = south_rotation_ver.flipX(); + odb::dbOrientType west_rotation_hor = odb::dbOrientType::MXR90; + if (vertical_site != horizontal_site) { + west_rotation_hor = odb::dbOrientType::R0; + } + const odb::dbOrientType east_rotation_hor = west_rotation_hor.flipY(); create_row(row_north_, vertical_site, x_sites, {nw->getBBox().xMax(), outer_io.yMax() - static_cast(vertical_box.maxDXDY())}, - odb::dbOrientType::MX, + north_rotation_ver, rotation_ver, odb::dbRowDir::HORIZONTAL, vertical_box.minDXDY()); - odb::dbOrientType east_rotation_hor = odb::dbOrientType::R90; - if (vertical_site != horizontal_site) { - east_rotation_hor = odb::dbOrientType::R0; - } create_row(row_east_, horizontal_site, y_sites, @@ -485,11 +488,10 @@ void ICeWall::makeIORow(odb::dbSite* horizontal_site, vertical_site, x_sites, {sw->getBBox().xMax(), outer_io.yMin()}, - odb::dbOrientType::R0, + south_rotation_ver, rotation_ver, odb::dbRowDir::HORIZONTAL, vertical_box.minDXDY()); - const odb::dbOrientType west_rotation_hor = east_rotation_hor.flipY(); create_row(row_west_, horizontal_site, y_sites, From 0a8d33aa21a553e51d4747e0966aeb249e0f76f3 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Wed, 25 Sep 2024 09:57:59 -0400 Subject: [PATCH 7/7] pad: fix test and update README to reflect the new base rotations Signed-off-by: Peter Gadfort --- src/pad/README.md | 2 +- src/pad/test/make_io_sites_rotations.tcl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/pad/README.md b/src/pad/README.md index 1cd38a814f4..50195d11581 100644 --- a/src/pad/README.md +++ b/src/pad/README.md @@ -167,7 +167,7 @@ make_io_sites | `-vertical_site` | Name of the site for the vertical pads (north and south). | | `-corner_site` | Name of the site for the corner cells. | | `-offset` | Offset from the die edge to place the rows. | -| `-rotation_horizontal` | Rotation to apply to the horizontal sites to ensure pads are placed correctly. The default value is `R0` for the eastern (right) row. | +| `-rotation_horizontal` | Rotation to apply to the horizontal sites to ensure pads are placed correctly. The default value is `R0` for the western (left) row when different sites are specified for hortizontal and vertical rows, the default value is `MXR90` when the same site is specified. | | `-rotation_vertical` | Rotation to apply to the vertical sites to ensure pads are placed correctly. The default value is `R0` for the southern (bottom) row. | | `-rotation_corner` | Rotation to apply to the corner sites to ensure pads are placed correctly. The default value is `R0` for the south west (lower left) corner. | | `-ring_index` | Used to specify the index of the ring in case of multiple rings. | diff --git a/src/pad/test/make_io_sites_rotations.tcl b/src/pad/test/make_io_sites_rotations.tcl index 667c6961a14..7d83fd8e3dd 100644 --- a/src/pad/test/make_io_sites_rotations.tcl +++ b/src/pad/test/make_io_sites_rotations.tcl @@ -9,7 +9,7 @@ read_def Nangate45_blackparrot/floorplan.def # Test make_io_sites make_io_sites -horizontal_site IOSITE -vertical_site IOSITE2 -corner_site IOSITE -offset 15 \ - -rotation_horizontal R90 \ + -rotation_horizontal MXR90 \ -rotation_vertical MY set def_file [make_result_file "make_io_sites_rotations.def"]