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Turn on hierarchical clock test. Code clean up for tidy. Signed-off-b…
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…y: Andy Fox <[email protected]>

Signed-off-by: andyfox-rushc <[email protected]>
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@andyfox-rushc
andyfox-rushc committed May 23, 2024
2 parents e7897ff + 0371d6e commit d583a7b
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Showing 53 changed files with 999 additions and 708 deletions.
10 changes: 8 additions & 2 deletions docker/Dockerfile.dev
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Original file line number Diff line number Diff line change
Expand Up @@ -8,9 +8,15 @@ ARG fromImage=ubuntu:22.04
FROM $fromImage

ARG INSTALLER_ARGS=""
RUN echo $INSTALLER_ARGS
ARG fromImage

COPY DependencyInstaller.sh /tmp/.
RUN echo $INSTALLER_ARGS

RUN /tmp/DependencyInstaller.sh -base
RUN /tmp/DependencyInstaller.sh -common $INSTALLER_ARGS

RUN echo "$fromImage" | grep -q "ubuntu" && \
strip --remove-section=.note.ABI-tag /usr/lib/x86_64-linux-gnu/libQt5Core.so || \
echo "Skipping strip command as fromImage does not contain 'ubuntu'"

RUN rm -f /tmp/DependencyInstaller.sh
3 changes: 0 additions & 3 deletions etc/DependencyInstaller.sh
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Original file line number Diff line number Diff line change
Expand Up @@ -287,9 +287,6 @@ _installUbuntuPackages() {
libqt5charts5-dev \
qt5-default
fi

# need the strip "hack" above to run on docker
strip --remove-section=.note.ABI-tag /usr/lib/x86_64-linux-gnu/libQt5Core.so
}

_installRHELCleanUp() {
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258 changes: 129 additions & 129 deletions src/cts/test/array.ok
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Original file line number Diff line number Diff line change
Expand Up @@ -65,19 +65,19 @@
[INFO CTS-0207] Leaf load cells 62
[INFO RSZ-0058] Using max wire length 693um.
[INFO RSZ-0047] Found 33 long wires.
[INFO RSZ-0048] Inserted 92 buffers in 33 nets.
[INFO RSZ-0048] Inserted 93 buffers in 33 nets.
Placement Analysis
---------------------------------
total displacement 3153.9 u
total displacement 3225.9 u
average displacement 1.1 u
max displacement 111.5 u
original HPWL 133100.0 u
legalized HPWL 133444.7 u
max displacement 132.5 u
original HPWL 132907.5 u
legalized HPWL 133404.8 u
delta HPWL 0 %

Clock clk
1.27 source latency inst_7_12/clk ^
-1.14 target latency inst_8_12/clk ^
1.26 source latency inst_7_12/clk ^
-1.13 target latency inst_8_12/clk ^
0.00 CRPR
--------------
0.13 setup skew
Expand All @@ -92,72 +92,72 @@ Path Type: max
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock source latency
0.00 0.00 ^ clk (in)
0.03 0.03 ^ wire7/Z (BUF_X8)
0.06 0.09 ^ wire6/Z (BUF_X16)
0.07 0.15 ^ wire5/Z (BUF_X32)
0.06 0.22 ^ wire4/Z (BUF_X32)
0.06 0.28 ^ wire3/Z (BUF_X32)
0.06 0.34 ^ wire2/Z (BUF_X32)
0.06 0.41 ^ wire1/Z (BUF_X32)
0.06 0.47 ^ clkbuf_0_clk/Z (BUF_X4)
0.04 0.51 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
0.03 0.54 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
0.04 0.58 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
0.03 0.61 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
0.04 0.66 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
0.05 0.70 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
0.03 0.74 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
0.03 0.77 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
0.03 0.80 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
0.03 0.84 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
0.03 0.87 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
0.03 0.90 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
0.04 0.94 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
0.04 0.98 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
0.03 1.01 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
0.03 1.04 ^ clkbuf_4_0_2_clk/Z (BUF_X4)
0.04 1.08 ^ clkbuf_5_0_0_clk/Z (BUF_X4)
0.03 1.11 ^ max_length10/Z (BUF_X8)
0.04 1.15 ^ inst_1_1/clk (array_tile)
0.21 1.36 ^ inst_1_1/e_out (array_tile)
0.00 1.36 ^ inst_2_1/w_in (array_tile)
1.36 data arrival time
0.04 0.04 ^ wire7/Z (BUF_X8)
0.03 0.07 ^ wire6/Z (BUF_X16)
0.07 0.14 ^ wire5/Z (BUF_X32)
0.06 0.20 ^ wire4/Z (BUF_X32)
0.06 0.27 ^ wire3/Z (BUF_X32)
0.06 0.33 ^ wire2/Z (BUF_X32)
0.06 0.39 ^ wire1/Z (BUF_X32)
0.06 0.46 ^ clkbuf_0_clk/Z (BUF_X4)
0.04 0.49 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
0.03 0.53 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
0.04 0.56 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
0.03 0.60 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
0.04 0.64 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
0.05 0.69 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
0.03 0.72 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
0.03 0.76 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
0.03 0.79 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
0.03 0.82 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
0.03 0.86 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
0.03 0.89 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
0.04 0.93 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
0.04 0.96 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
0.03 1.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
0.03 1.03 ^ clkbuf_4_0_2_clk/Z (BUF_X4)
0.04 1.07 ^ clkbuf_5_0_0_clk/Z (BUF_X4)
0.03 1.10 ^ max_length10/Z (BUF_X8)
0.04 1.14 ^ inst_1_1/clk (array_tile)
0.21 1.35 ^ inst_1_1/e_out (array_tile)
0.00 1.35 ^ inst_2_1/w_in (array_tile)
1.35 data arrival time

5.00 5.00 clock clk (rise edge)
0.00 5.00 clock source latency
0.00 5.00 ^ clk (in)
0.03 5.03 ^ wire7/Z (BUF_X8)
0.06 5.09 ^ wire6/Z (BUF_X16)
0.07 5.15 ^ wire5/Z (BUF_X32)
0.06 5.22 ^ wire4/Z (BUF_X32)
0.06 5.28 ^ wire3/Z (BUF_X32)
0.06 5.34 ^ wire2/Z (BUF_X32)
0.06 5.41 ^ wire1/Z (BUF_X32)
0.06 5.47 ^ clkbuf_0_clk/Z (BUF_X4)
0.04 5.51 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
0.03 5.54 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
0.04 5.58 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
0.03 5.61 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
0.04 5.66 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
0.05 5.70 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
0.03 5.74 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
0.03 5.77 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
0.03 5.80 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
0.03 5.84 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
0.03 5.87 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
0.03 5.90 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
0.04 5.94 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
0.04 5.98 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
0.03 6.01 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
0.03 6.04 ^ clkbuf_4_0_2_clk/Z (BUF_X4)
0.04 6.08 ^ clkbuf_5_1_0_clk/Z (BUF_X4)
0.01 6.09 ^ inst_2_1/clk (array_tile)
0.00 6.09 clock reconvergence pessimism
-0.05 6.04 library setup time
6.04 data required time
0.04 5.04 ^ wire7/Z (BUF_X8)
0.03 5.07 ^ wire6/Z (BUF_X16)
0.07 5.14 ^ wire5/Z (BUF_X32)
0.06 5.20 ^ wire4/Z (BUF_X32)
0.06 5.27 ^ wire3/Z (BUF_X32)
0.06 5.33 ^ wire2/Z (BUF_X32)
0.06 5.39 ^ wire1/Z (BUF_X32)
0.06 5.46 ^ clkbuf_0_clk/Z (BUF_X4)
0.04 5.49 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
0.03 5.53 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
0.04 5.56 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
0.03 5.60 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
0.04 5.64 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
0.05 5.69 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
0.03 5.72 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
0.03 5.76 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
0.03 5.79 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
0.03 5.82 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
0.03 5.86 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
0.03 5.89 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
0.04 5.93 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
0.04 5.96 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
0.03 6.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
0.03 6.03 ^ clkbuf_4_0_2_clk/Z (BUF_X4)
0.04 6.07 ^ clkbuf_5_1_0_clk/Z (BUF_X4)
0.01 6.07 ^ inst_2_1/clk (array_tile)
0.00 6.07 clock reconvergence pessimism
-0.05 6.02 library setup time
6.02 data required time
---------------------------------------------------------
6.04 data required time
-1.36 data arrival time
6.02 data required time
-1.35 data arrival time
---------------------------------------------------------
4.67 slack (MET)

Expand All @@ -172,72 +172,72 @@ Path Type: max
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock source latency
0.00 0.00 ^ clk (in)
0.03 0.03 ^ wire7/Z (BUF_X8)
0.06 0.09 ^ wire6/Z (BUF_X16)
0.07 0.15 ^ wire5/Z (BUF_X32)
0.06 0.22 ^ wire4/Z (BUF_X32)
0.06 0.28 ^ wire3/Z (BUF_X32)
0.06 0.34 ^ wire2/Z (BUF_X32)
0.06 0.41 ^ wire1/Z (BUF_X32)
0.06 0.47 ^ clkbuf_0_clk/Z (BUF_X4)
0.04 0.51 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
0.03 0.54 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
0.04 0.58 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
0.03 0.61 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
0.04 0.66 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
0.05 0.70 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
0.03 0.74 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
0.03 0.77 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
0.03 0.80 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
0.03 0.84 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
0.03 0.87 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
0.03 0.90 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
0.04 0.94 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
0.04 0.98 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
0.03 1.01 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
0.03 1.04 ^ clkbuf_4_0_2_clk/Z (BUF_X4)
0.04 1.08 ^ clkbuf_5_1_0_clk/Z (BUF_X4)
0.01 1.09 ^ inst_2_1/clk (array_tile)
0.21 1.30 ^ inst_2_1/w_out (array_tile)
0.00 1.30 ^ inst_1_1/e_in (array_tile)
1.30 data arrival time
0.04 0.04 ^ wire7/Z (BUF_X8)
0.03 0.07 ^ wire6/Z (BUF_X16)
0.07 0.14 ^ wire5/Z (BUF_X32)
0.06 0.20 ^ wire4/Z (BUF_X32)
0.06 0.27 ^ wire3/Z (BUF_X32)
0.06 0.33 ^ wire2/Z (BUF_X32)
0.06 0.39 ^ wire1/Z (BUF_X32)
0.06 0.46 ^ clkbuf_0_clk/Z (BUF_X4)
0.04 0.49 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
0.03 0.53 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
0.04 0.56 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
0.03 0.60 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
0.04 0.64 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
0.05 0.69 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
0.03 0.72 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
0.03 0.76 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
0.03 0.79 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
0.03 0.82 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
0.03 0.86 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
0.03 0.89 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
0.04 0.93 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
0.04 0.96 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
0.03 1.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
0.03 1.03 ^ clkbuf_4_0_2_clk/Z (BUF_X4)
0.04 1.07 ^ clkbuf_5_1_0_clk/Z (BUF_X4)
0.01 1.07 ^ inst_2_1/clk (array_tile)
0.21 1.29 ^ inst_2_1/w_out (array_tile)
0.00 1.29 ^ inst_1_1/e_in (array_tile)
1.29 data arrival time

5.00 5.00 clock clk (rise edge)
0.00 5.00 clock source latency
0.00 5.00 ^ clk (in)
0.03 5.03 ^ wire7/Z (BUF_X8)
0.06 5.09 ^ wire6/Z (BUF_X16)
0.07 5.15 ^ wire5/Z (BUF_X32)
0.06 5.22 ^ wire4/Z (BUF_X32)
0.06 5.28 ^ wire3/Z (BUF_X32)
0.06 5.34 ^ wire2/Z (BUF_X32)
0.06 5.41 ^ wire1/Z (BUF_X32)
0.06 5.47 ^ clkbuf_0_clk/Z (BUF_X4)
0.04 5.51 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
0.03 5.54 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
0.04 5.58 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
0.03 5.61 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
0.04 5.66 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
0.05 5.70 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
0.03 5.74 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
0.03 5.77 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
0.03 5.80 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
0.03 5.84 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
0.03 5.87 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
0.03 5.90 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
0.04 5.94 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
0.04 5.98 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
0.03 6.01 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
0.03 6.04 ^ clkbuf_4_0_2_clk/Z (BUF_X4)
0.04 6.08 ^ clkbuf_5_0_0_clk/Z (BUF_X4)
0.03 6.11 ^ max_length10/Z (BUF_X8)
0.04 6.15 ^ inst_1_1/clk (array_tile)
0.00 6.15 clock reconvergence pessimism
-0.05 6.10 library setup time
6.10 data required time
0.04 5.04 ^ wire7/Z (BUF_X8)
0.03 5.07 ^ wire6/Z (BUF_X16)
0.07 5.14 ^ wire5/Z (BUF_X32)
0.06 5.20 ^ wire4/Z (BUF_X32)
0.06 5.27 ^ wire3/Z (BUF_X32)
0.06 5.33 ^ wire2/Z (BUF_X32)
0.06 5.39 ^ wire1/Z (BUF_X32)
0.06 5.46 ^ clkbuf_0_clk/Z (BUF_X4)
0.04 5.49 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
0.03 5.53 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
0.04 5.56 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
0.03 5.60 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
0.04 5.64 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
0.05 5.69 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
0.03 5.72 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
0.03 5.76 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
0.03 5.79 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
0.03 5.82 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
0.03 5.86 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
0.03 5.89 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
0.04 5.93 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
0.04 5.96 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
0.03 6.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
0.03 6.03 ^ clkbuf_4_0_2_clk/Z (BUF_X4)
0.04 6.07 ^ clkbuf_5_0_0_clk/Z (BUF_X4)
0.03 6.10 ^ max_length10/Z (BUF_X8)
0.04 6.14 ^ inst_1_1/clk (array_tile)
0.00 6.14 clock reconvergence pessimism
-0.05 6.09 library setup time
6.09 data required time
---------------------------------------------------------
6.10 data required time
-1.30 data arrival time
6.09 data required time
-1.29 data arrival time
---------------------------------------------------------
4.80 slack (MET)

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