diff --git a/docker/Dockerfile.dev b/docker/Dockerfile.dev index b3551df19a2..c8f2edc7a52 100644 --- a/docker/Dockerfile.dev +++ b/docker/Dockerfile.dev @@ -8,9 +8,15 @@ ARG fromImage=ubuntu:22.04 FROM $fromImage ARG INSTALLER_ARGS="" -RUN echo $INSTALLER_ARGS +ARG fromImage + COPY DependencyInstaller.sh /tmp/. -RUN echo $INSTALLER_ARGS + RUN /tmp/DependencyInstaller.sh -base RUN /tmp/DependencyInstaller.sh -common $INSTALLER_ARGS + +RUN echo "$fromImage" | grep -q "ubuntu" && \ + strip --remove-section=.note.ABI-tag /usr/lib/x86_64-linux-gnu/libQt5Core.so || \ + echo "Skipping strip command as fromImage does not contain 'ubuntu'" + RUN rm -f /tmp/DependencyInstaller.sh diff --git a/etc/DependencyInstaller.sh b/etc/DependencyInstaller.sh index 39931ae6595..0d859a80194 100755 --- a/etc/DependencyInstaller.sh +++ b/etc/DependencyInstaller.sh @@ -287,9 +287,6 @@ _installUbuntuPackages() { libqt5charts5-dev \ qt5-default fi - - # need the strip "hack" above to run on docker - strip --remove-section=.note.ABI-tag /usr/lib/x86_64-linux-gnu/libQt5Core.so } _installRHELCleanUp() { diff --git a/src/cts/test/array.ok b/src/cts/test/array.ok index 5353616f2d7..b0a7dff90d2 100644 --- a/src/cts/test/array.ok +++ b/src/cts/test/array.ok @@ -65,19 +65,19 @@ [INFO CTS-0207] Leaf load cells 62 [INFO RSZ-0058] Using max wire length 693um. [INFO RSZ-0047] Found 33 long wires. -[INFO RSZ-0048] Inserted 92 buffers in 33 nets. +[INFO RSZ-0048] Inserted 93 buffers in 33 nets. Placement Analysis --------------------------------- -total displacement 3153.9 u +total displacement 3225.9 u average displacement 1.1 u -max displacement 111.5 u -original HPWL 133100.0 u -legalized HPWL 133444.7 u +max displacement 132.5 u +original HPWL 132907.5 u +legalized HPWL 133404.8 u delta HPWL 0 % Clock clk - 1.27 source latency inst_7_12/clk ^ - -1.14 target latency inst_8_12/clk ^ + 1.26 source latency inst_7_12/clk ^ + -1.13 target latency inst_8_12/clk ^ 0.00 CRPR -------------- 0.13 setup skew @@ -92,72 +92,72 @@ Path Type: max 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock source latency 0.00 0.00 ^ clk (in) - 0.03 0.03 ^ wire7/Z (BUF_X8) - 0.06 0.09 ^ wire6/Z (BUF_X16) - 0.07 0.15 ^ wire5/Z (BUF_X32) - 0.06 0.22 ^ wire4/Z (BUF_X32) - 0.06 0.28 ^ wire3/Z (BUF_X32) - 0.06 0.34 ^ wire2/Z (BUF_X32) - 0.06 0.41 ^ wire1/Z (BUF_X32) - 0.06 0.47 ^ clkbuf_0_clk/Z (BUF_X4) - 0.04 0.51 ^ clkbuf_1_0_0_clk/Z (BUF_X4) - 0.03 0.54 ^ clkbuf_1_0_1_clk/Z (BUF_X4) - 0.04 0.58 ^ clkbuf_1_0_2_clk/Z (BUF_X4) - 0.03 0.61 ^ clkbuf_1_0_3_clk/Z (BUF_X4) - 0.04 0.66 ^ clkbuf_1_0_4_clk/Z (BUF_X4) - 0.05 0.70 ^ clkbuf_2_0_0_clk/Z (BUF_X4) - 0.03 0.74 ^ clkbuf_2_0_1_clk/Z (BUF_X4) - 0.03 0.77 ^ clkbuf_2_0_2_clk/Z (BUF_X4) - 0.03 0.80 ^ clkbuf_2_0_3_clk/Z (BUF_X4) - 0.03 0.84 ^ clkbuf_2_0_4_clk/Z (BUF_X4) - 0.03 0.87 ^ clkbuf_3_0_0_clk/Z (BUF_X4) - 0.03 0.90 ^ clkbuf_3_0_1_clk/Z (BUF_X4) - 0.04 0.94 ^ clkbuf_3_0_2_clk/Z (BUF_X4) - 0.04 0.98 ^ clkbuf_4_0_0_clk/Z (BUF_X4) - 0.03 1.01 ^ clkbuf_4_0_1_clk/Z (BUF_X4) - 0.03 1.04 ^ clkbuf_4_0_2_clk/Z (BUF_X4) - 0.04 1.08 ^ clkbuf_5_0_0_clk/Z (BUF_X4) - 0.03 1.11 ^ max_length10/Z (BUF_X8) - 0.04 1.15 ^ inst_1_1/clk (array_tile) - 0.21 1.36 ^ inst_1_1/e_out (array_tile) - 0.00 1.36 ^ inst_2_1/w_in (array_tile) - 1.36 data arrival time + 0.04 0.04 ^ wire7/Z (BUF_X8) + 0.03 0.07 ^ wire6/Z (BUF_X16) + 0.07 0.14 ^ wire5/Z (BUF_X32) + 0.06 0.20 ^ wire4/Z (BUF_X32) + 0.06 0.27 ^ wire3/Z (BUF_X32) + 0.06 0.33 ^ wire2/Z (BUF_X32) + 0.06 0.39 ^ wire1/Z (BUF_X32) + 0.06 0.46 ^ clkbuf_0_clk/Z (BUF_X4) + 0.04 0.49 ^ clkbuf_1_0_0_clk/Z (BUF_X4) + 0.03 0.53 ^ clkbuf_1_0_1_clk/Z (BUF_X4) + 0.04 0.56 ^ clkbuf_1_0_2_clk/Z (BUF_X4) + 0.03 0.60 ^ clkbuf_1_0_3_clk/Z (BUF_X4) + 0.04 0.64 ^ clkbuf_1_0_4_clk/Z (BUF_X4) + 0.05 0.69 ^ clkbuf_2_0_0_clk/Z (BUF_X4) + 0.03 0.72 ^ clkbuf_2_0_1_clk/Z (BUF_X4) + 0.03 0.76 ^ clkbuf_2_0_2_clk/Z (BUF_X4) + 0.03 0.79 ^ clkbuf_2_0_3_clk/Z (BUF_X4) + 0.03 0.82 ^ clkbuf_2_0_4_clk/Z (BUF_X4) + 0.03 0.86 ^ clkbuf_3_0_0_clk/Z (BUF_X4) + 0.03 0.89 ^ clkbuf_3_0_1_clk/Z (BUF_X4) + 0.04 0.93 ^ clkbuf_3_0_2_clk/Z (BUF_X4) + 0.04 0.96 ^ clkbuf_4_0_0_clk/Z (BUF_X4) + 0.03 1.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4) + 0.03 1.03 ^ clkbuf_4_0_2_clk/Z (BUF_X4) + 0.04 1.07 ^ clkbuf_5_0_0_clk/Z (BUF_X4) + 0.03 1.10 ^ max_length10/Z (BUF_X8) + 0.04 1.14 ^ inst_1_1/clk (array_tile) + 0.21 1.35 ^ inst_1_1/e_out (array_tile) + 0.00 1.35 ^ inst_2_1/w_in (array_tile) + 1.35 data arrival time 5.00 5.00 clock clk (rise edge) 0.00 5.00 clock source latency 0.00 5.00 ^ clk (in) - 0.03 5.03 ^ wire7/Z (BUF_X8) - 0.06 5.09 ^ wire6/Z (BUF_X16) - 0.07 5.15 ^ wire5/Z (BUF_X32) - 0.06 5.22 ^ wire4/Z (BUF_X32) - 0.06 5.28 ^ wire3/Z (BUF_X32) - 0.06 5.34 ^ wire2/Z (BUF_X32) - 0.06 5.41 ^ wire1/Z (BUF_X32) - 0.06 5.47 ^ clkbuf_0_clk/Z (BUF_X4) - 0.04 5.51 ^ clkbuf_1_0_0_clk/Z (BUF_X4) - 0.03 5.54 ^ clkbuf_1_0_1_clk/Z (BUF_X4) - 0.04 5.58 ^ clkbuf_1_0_2_clk/Z (BUF_X4) - 0.03 5.61 ^ clkbuf_1_0_3_clk/Z (BUF_X4) - 0.04 5.66 ^ clkbuf_1_0_4_clk/Z (BUF_X4) - 0.05 5.70 ^ clkbuf_2_0_0_clk/Z (BUF_X4) - 0.03 5.74 ^ clkbuf_2_0_1_clk/Z (BUF_X4) - 0.03 5.77 ^ clkbuf_2_0_2_clk/Z (BUF_X4) - 0.03 5.80 ^ clkbuf_2_0_3_clk/Z (BUF_X4) - 0.03 5.84 ^ clkbuf_2_0_4_clk/Z (BUF_X4) - 0.03 5.87 ^ clkbuf_3_0_0_clk/Z (BUF_X4) - 0.03 5.90 ^ clkbuf_3_0_1_clk/Z (BUF_X4) - 0.04 5.94 ^ clkbuf_3_0_2_clk/Z (BUF_X4) - 0.04 5.98 ^ clkbuf_4_0_0_clk/Z (BUF_X4) - 0.03 6.01 ^ clkbuf_4_0_1_clk/Z (BUF_X4) - 0.03 6.04 ^ clkbuf_4_0_2_clk/Z (BUF_X4) - 0.04 6.08 ^ clkbuf_5_1_0_clk/Z (BUF_X4) - 0.01 6.09 ^ inst_2_1/clk (array_tile) - 0.00 6.09 clock reconvergence pessimism - -0.05 6.04 library setup time - 6.04 data required time + 0.04 5.04 ^ wire7/Z (BUF_X8) + 0.03 5.07 ^ wire6/Z (BUF_X16) + 0.07 5.14 ^ wire5/Z (BUF_X32) + 0.06 5.20 ^ wire4/Z (BUF_X32) + 0.06 5.27 ^ wire3/Z (BUF_X32) + 0.06 5.33 ^ wire2/Z (BUF_X32) + 0.06 5.39 ^ wire1/Z (BUF_X32) + 0.06 5.46 ^ clkbuf_0_clk/Z (BUF_X4) + 0.04 5.49 ^ clkbuf_1_0_0_clk/Z (BUF_X4) + 0.03 5.53 ^ clkbuf_1_0_1_clk/Z (BUF_X4) + 0.04 5.56 ^ clkbuf_1_0_2_clk/Z (BUF_X4) + 0.03 5.60 ^ clkbuf_1_0_3_clk/Z (BUF_X4) + 0.04 5.64 ^ clkbuf_1_0_4_clk/Z (BUF_X4) + 0.05 5.69 ^ clkbuf_2_0_0_clk/Z (BUF_X4) + 0.03 5.72 ^ clkbuf_2_0_1_clk/Z (BUF_X4) + 0.03 5.76 ^ clkbuf_2_0_2_clk/Z (BUF_X4) + 0.03 5.79 ^ clkbuf_2_0_3_clk/Z (BUF_X4) + 0.03 5.82 ^ clkbuf_2_0_4_clk/Z (BUF_X4) + 0.03 5.86 ^ clkbuf_3_0_0_clk/Z (BUF_X4) + 0.03 5.89 ^ clkbuf_3_0_1_clk/Z (BUF_X4) + 0.04 5.93 ^ clkbuf_3_0_2_clk/Z (BUF_X4) + 0.04 5.96 ^ clkbuf_4_0_0_clk/Z (BUF_X4) + 0.03 6.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4) + 0.03 6.03 ^ clkbuf_4_0_2_clk/Z (BUF_X4) + 0.04 6.07 ^ clkbuf_5_1_0_clk/Z (BUF_X4) + 0.01 6.07 ^ inst_2_1/clk (array_tile) + 0.00 6.07 clock reconvergence pessimism + -0.05 6.02 library setup time + 6.02 data required time --------------------------------------------------------- - 6.04 data required time - -1.36 data arrival time + 6.02 data required time + -1.35 data arrival time --------------------------------------------------------- 4.67 slack (MET) @@ -172,72 +172,72 @@ Path Type: max 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock source latency 0.00 0.00 ^ clk (in) - 0.03 0.03 ^ wire7/Z (BUF_X8) - 0.06 0.09 ^ wire6/Z (BUF_X16) - 0.07 0.15 ^ wire5/Z (BUF_X32) - 0.06 0.22 ^ wire4/Z (BUF_X32) - 0.06 0.28 ^ wire3/Z (BUF_X32) - 0.06 0.34 ^ wire2/Z (BUF_X32) - 0.06 0.41 ^ wire1/Z (BUF_X32) - 0.06 0.47 ^ clkbuf_0_clk/Z (BUF_X4) - 0.04 0.51 ^ clkbuf_1_0_0_clk/Z (BUF_X4) - 0.03 0.54 ^ clkbuf_1_0_1_clk/Z (BUF_X4) - 0.04 0.58 ^ clkbuf_1_0_2_clk/Z (BUF_X4) - 0.03 0.61 ^ clkbuf_1_0_3_clk/Z (BUF_X4) - 0.04 0.66 ^ clkbuf_1_0_4_clk/Z (BUF_X4) - 0.05 0.70 ^ clkbuf_2_0_0_clk/Z (BUF_X4) - 0.03 0.74 ^ clkbuf_2_0_1_clk/Z (BUF_X4) - 0.03 0.77 ^ clkbuf_2_0_2_clk/Z (BUF_X4) - 0.03 0.80 ^ clkbuf_2_0_3_clk/Z (BUF_X4) - 0.03 0.84 ^ clkbuf_2_0_4_clk/Z (BUF_X4) - 0.03 0.87 ^ clkbuf_3_0_0_clk/Z (BUF_X4) - 0.03 0.90 ^ clkbuf_3_0_1_clk/Z (BUF_X4) - 0.04 0.94 ^ clkbuf_3_0_2_clk/Z (BUF_X4) - 0.04 0.98 ^ clkbuf_4_0_0_clk/Z (BUF_X4) - 0.03 1.01 ^ clkbuf_4_0_1_clk/Z (BUF_X4) - 0.03 1.04 ^ clkbuf_4_0_2_clk/Z (BUF_X4) - 0.04 1.08 ^ clkbuf_5_1_0_clk/Z (BUF_X4) - 0.01 1.09 ^ inst_2_1/clk (array_tile) - 0.21 1.30 ^ inst_2_1/w_out (array_tile) - 0.00 1.30 ^ inst_1_1/e_in (array_tile) - 1.30 data arrival time + 0.04 0.04 ^ wire7/Z (BUF_X8) + 0.03 0.07 ^ wire6/Z (BUF_X16) + 0.07 0.14 ^ wire5/Z (BUF_X32) + 0.06 0.20 ^ wire4/Z (BUF_X32) + 0.06 0.27 ^ wire3/Z (BUF_X32) + 0.06 0.33 ^ wire2/Z (BUF_X32) + 0.06 0.39 ^ wire1/Z (BUF_X32) + 0.06 0.46 ^ clkbuf_0_clk/Z (BUF_X4) + 0.04 0.49 ^ clkbuf_1_0_0_clk/Z (BUF_X4) + 0.03 0.53 ^ clkbuf_1_0_1_clk/Z (BUF_X4) + 0.04 0.56 ^ clkbuf_1_0_2_clk/Z (BUF_X4) + 0.03 0.60 ^ clkbuf_1_0_3_clk/Z (BUF_X4) + 0.04 0.64 ^ clkbuf_1_0_4_clk/Z (BUF_X4) + 0.05 0.69 ^ clkbuf_2_0_0_clk/Z (BUF_X4) + 0.03 0.72 ^ clkbuf_2_0_1_clk/Z (BUF_X4) + 0.03 0.76 ^ clkbuf_2_0_2_clk/Z (BUF_X4) + 0.03 0.79 ^ clkbuf_2_0_3_clk/Z (BUF_X4) + 0.03 0.82 ^ clkbuf_2_0_4_clk/Z (BUF_X4) + 0.03 0.86 ^ clkbuf_3_0_0_clk/Z (BUF_X4) + 0.03 0.89 ^ clkbuf_3_0_1_clk/Z (BUF_X4) + 0.04 0.93 ^ clkbuf_3_0_2_clk/Z (BUF_X4) + 0.04 0.96 ^ clkbuf_4_0_0_clk/Z (BUF_X4) + 0.03 1.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4) + 0.03 1.03 ^ clkbuf_4_0_2_clk/Z (BUF_X4) + 0.04 1.07 ^ clkbuf_5_1_0_clk/Z (BUF_X4) + 0.01 1.07 ^ inst_2_1/clk (array_tile) + 0.21 1.29 ^ inst_2_1/w_out (array_tile) + 0.00 1.29 ^ inst_1_1/e_in (array_tile) + 1.29 data arrival time 5.00 5.00 clock clk (rise edge) 0.00 5.00 clock source latency 0.00 5.00 ^ clk (in) - 0.03 5.03 ^ wire7/Z (BUF_X8) - 0.06 5.09 ^ wire6/Z (BUF_X16) - 0.07 5.15 ^ wire5/Z (BUF_X32) - 0.06 5.22 ^ wire4/Z (BUF_X32) - 0.06 5.28 ^ wire3/Z (BUF_X32) - 0.06 5.34 ^ wire2/Z (BUF_X32) - 0.06 5.41 ^ wire1/Z (BUF_X32) - 0.06 5.47 ^ clkbuf_0_clk/Z (BUF_X4) - 0.04 5.51 ^ clkbuf_1_0_0_clk/Z (BUF_X4) - 0.03 5.54 ^ clkbuf_1_0_1_clk/Z (BUF_X4) - 0.04 5.58 ^ clkbuf_1_0_2_clk/Z (BUF_X4) - 0.03 5.61 ^ clkbuf_1_0_3_clk/Z (BUF_X4) - 0.04 5.66 ^ clkbuf_1_0_4_clk/Z (BUF_X4) - 0.05 5.70 ^ clkbuf_2_0_0_clk/Z (BUF_X4) - 0.03 5.74 ^ clkbuf_2_0_1_clk/Z (BUF_X4) - 0.03 5.77 ^ clkbuf_2_0_2_clk/Z (BUF_X4) - 0.03 5.80 ^ clkbuf_2_0_3_clk/Z (BUF_X4) - 0.03 5.84 ^ clkbuf_2_0_4_clk/Z (BUF_X4) - 0.03 5.87 ^ clkbuf_3_0_0_clk/Z (BUF_X4) - 0.03 5.90 ^ clkbuf_3_0_1_clk/Z (BUF_X4) - 0.04 5.94 ^ clkbuf_3_0_2_clk/Z (BUF_X4) - 0.04 5.98 ^ clkbuf_4_0_0_clk/Z (BUF_X4) - 0.03 6.01 ^ clkbuf_4_0_1_clk/Z (BUF_X4) - 0.03 6.04 ^ clkbuf_4_0_2_clk/Z (BUF_X4) - 0.04 6.08 ^ clkbuf_5_0_0_clk/Z (BUF_X4) - 0.03 6.11 ^ max_length10/Z (BUF_X8) - 0.04 6.15 ^ inst_1_1/clk (array_tile) - 0.00 6.15 clock reconvergence pessimism - -0.05 6.10 library setup time - 6.10 data required time + 0.04 5.04 ^ wire7/Z (BUF_X8) + 0.03 5.07 ^ wire6/Z (BUF_X16) + 0.07 5.14 ^ wire5/Z (BUF_X32) + 0.06 5.20 ^ wire4/Z (BUF_X32) + 0.06 5.27 ^ wire3/Z (BUF_X32) + 0.06 5.33 ^ wire2/Z (BUF_X32) + 0.06 5.39 ^ wire1/Z (BUF_X32) + 0.06 5.46 ^ clkbuf_0_clk/Z (BUF_X4) + 0.04 5.49 ^ clkbuf_1_0_0_clk/Z (BUF_X4) + 0.03 5.53 ^ clkbuf_1_0_1_clk/Z (BUF_X4) + 0.04 5.56 ^ clkbuf_1_0_2_clk/Z (BUF_X4) + 0.03 5.60 ^ clkbuf_1_0_3_clk/Z (BUF_X4) + 0.04 5.64 ^ clkbuf_1_0_4_clk/Z (BUF_X4) + 0.05 5.69 ^ clkbuf_2_0_0_clk/Z (BUF_X4) + 0.03 5.72 ^ clkbuf_2_0_1_clk/Z (BUF_X4) + 0.03 5.76 ^ clkbuf_2_0_2_clk/Z (BUF_X4) + 0.03 5.79 ^ clkbuf_2_0_3_clk/Z (BUF_X4) + 0.03 5.82 ^ clkbuf_2_0_4_clk/Z (BUF_X4) + 0.03 5.86 ^ clkbuf_3_0_0_clk/Z (BUF_X4) + 0.03 5.89 ^ clkbuf_3_0_1_clk/Z (BUF_X4) + 0.04 5.93 ^ clkbuf_3_0_2_clk/Z (BUF_X4) + 0.04 5.96 ^ clkbuf_4_0_0_clk/Z (BUF_X4) + 0.03 6.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4) + 0.03 6.03 ^ clkbuf_4_0_2_clk/Z (BUF_X4) + 0.04 6.07 ^ clkbuf_5_0_0_clk/Z (BUF_X4) + 0.03 6.10 ^ max_length10/Z (BUF_X8) + 0.04 6.14 ^ inst_1_1/clk (array_tile) + 0.00 6.14 clock reconvergence pessimism + -0.05 6.09 library setup time + 6.09 data required time --------------------------------------------------------- - 6.10 data required time - -1.30 data arrival time + 6.09 data required time + -1.29 data arrival time --------------------------------------------------------- 4.80 slack (MET) diff --git a/src/cts/test/array_ins_delay.ok b/src/cts/test/array_ins_delay.ok index 4d4027b1c73..ee31fcd1886 100644 --- a/src/cts/test/array_ins_delay.ok +++ b/src/cts/test/array_ins_delay.ok @@ -117,22 +117,22 @@ [INFO CTS-0207] Leaf load cells 4 [INFO RSZ-0058] Using max wire length 693um. [INFO RSZ-0047] Found 56 long wires. -[INFO RSZ-0048] Inserted 114 buffers in 56 nets. +[INFO RSZ-0048] Inserted 113 buffers in 56 nets. Placement Analysis --------------------------------- -total displacement 4567.7 u -average displacement 1.5 u -max displacement 153.0 u -original HPWL 185794.9 u -legalized HPWL 186281.3 u +total displacement 3930.5 u +average displacement 1.3 u +max displacement 132.4 u +original HPWL 185797.7 u +legalized HPWL 186439.5 u delta HPWL 0 % Clock clk - 1.24 source latency inst_8_12/clk ^ + 1.25 source latency inst_8_12/clk ^ -1.09 target latency inst_10_12/clk ^ 0.00 CRPR -------------- - 0.15 setup skew + 0.16 setup skew Startpoint: inst_1_1 (rising edge-triggered flip-flop clocked by clk) Endpoint: inst_2_1 (rising edge-triggered flip-flop clocked by clk) @@ -145,32 +145,32 @@ Path Type: max 0.00 0.00 clock source latency 0.00 0.00 ^ clk (in) 0.04 0.04 ^ wire7/Z (BUF_X8) - 0.04 0.08 ^ wire6/Z (BUF_X16) - 0.07 0.14 ^ wire5/Z (BUF_X32) - 0.06 0.20 ^ wire4/Z (BUF_X32) - 0.06 0.27 ^ wire3/Z (BUF_X32) - 0.06 0.33 ^ wire2/Z (BUF_X32) - 0.06 0.39 ^ wire1/Z (BUF_X32) - 0.06 0.45 ^ clkbuf_0_clk/Z (BUF_X4) - 0.04 0.49 ^ delaybuf_0_clk/Z (BUF_X4) + 0.03 0.07 ^ wire6/Z (BUF_X16) + 0.06 0.12 ^ wire5/Z (BUF_X16) + 0.06 0.19 ^ wire4/Z (BUF_X32) + 0.06 0.25 ^ wire3/Z (BUF_X32) + 0.06 0.32 ^ wire2/Z (BUF_X32) + 0.06 0.38 ^ wire1/Z (BUF_X32) + 0.07 0.45 ^ clkbuf_0_clk/Z (BUF_X4) + 0.04 0.48 ^ delaybuf_0_clk/Z (BUF_X4) 0.03 0.52 ^ clkbuf_1_0_0_clk/Z (BUF_X4) 0.03 0.55 ^ clkbuf_1_0_1_clk/Z (BUF_X4) - 0.03 0.59 ^ clkbuf_1_0_2_clk/Z (BUF_X4) + 0.03 0.58 ^ clkbuf_1_0_2_clk/Z (BUF_X4) 0.03 0.62 ^ clkbuf_1_0_3_clk/Z (BUF_X4) 0.04 0.66 ^ clkbuf_1_0_4_clk/Z (BUF_X4) 0.03 0.69 ^ clkbuf_2_0_0_clk/Z (BUF_X4) - 0.03 0.73 ^ clkbuf_2_0_1_clk/Z (BUF_X4) + 0.03 0.72 ^ clkbuf_2_0_1_clk/Z (BUF_X4) 0.03 0.76 ^ clkbuf_2_0_2_clk/Z (BUF_X4) - 0.03 0.80 ^ clkbuf_2_0_3_clk/Z (BUF_X4) + 0.03 0.79 ^ clkbuf_2_0_3_clk/Z (BUF_X4) 0.04 0.83 ^ clkbuf_2_0_4_clk/Z (BUF_X4) - 0.03 0.87 ^ clkbuf_3_0_0_clk/Z (BUF_X4) + 0.03 0.86 ^ clkbuf_3_0_0_clk/Z (BUF_X4) 0.03 0.90 ^ clkbuf_3_0_1_clk/Z (BUF_X4) 0.04 0.94 ^ clkbuf_3_0_2_clk/Z (BUF_X4) - 0.03 0.97 ^ clkbuf_4_0_0_clk/Z (BUF_X4) - 0.03 1.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4) + 0.03 0.96 ^ clkbuf_4_0_0_clk/Z (BUF_X4) + 0.03 0.99 ^ clkbuf_4_0_1_clk/Z (BUF_X4) 0.05 1.04 ^ clkbuf_4_0_2_clk/Z (BUF_X4) - 0.04 1.09 ^ clkbuf_5_0_0_clk/Z (BUF_X4) - 0.03 1.12 ^ max_length8/Z (BUF_X8) + 0.04 1.08 ^ clkbuf_5_0_0_clk/Z (BUF_X4) + 0.03 1.11 ^ max_length8/Z (BUF_X8) 0.04 1.15 ^ inst_1_1/clk (array_tile) 0.21 1.36 ^ inst_1_1/e_out (array_tile) 0.00 1.36 ^ inst_2_1/w_in (array_tile) @@ -180,32 +180,32 @@ Path Type: max 0.00 5.00 clock source latency 0.00 5.00 ^ clk (in) 0.04 5.04 ^ wire7/Z (BUF_X8) - 0.04 5.08 ^ wire6/Z (BUF_X16) - 0.07 5.14 ^ wire5/Z (BUF_X32) - 0.06 5.20 ^ wire4/Z (BUF_X32) - 0.06 5.27 ^ wire3/Z (BUF_X32) - 0.06 5.33 ^ wire2/Z (BUF_X32) - 0.06 5.39 ^ wire1/Z (BUF_X32) - 0.06 5.45 ^ clkbuf_0_clk/Z (BUF_X4) - 0.04 5.49 ^ delaybuf_0_clk/Z (BUF_X4) + 0.03 5.07 ^ wire6/Z (BUF_X16) + 0.06 5.12 ^ wire5/Z (BUF_X16) + 0.06 5.19 ^ wire4/Z (BUF_X32) + 0.06 5.25 ^ wire3/Z (BUF_X32) + 0.06 5.32 ^ wire2/Z (BUF_X32) + 0.06 5.38 ^ wire1/Z (BUF_X32) + 0.07 5.45 ^ clkbuf_0_clk/Z (BUF_X4) + 0.04 5.48 ^ delaybuf_0_clk/Z (BUF_X4) 0.03 5.52 ^ clkbuf_1_0_0_clk/Z (BUF_X4) 0.03 5.55 ^ clkbuf_1_0_1_clk/Z (BUF_X4) - 0.03 5.59 ^ clkbuf_1_0_2_clk/Z (BUF_X4) + 0.03 5.58 ^ clkbuf_1_0_2_clk/Z (BUF_X4) 0.03 5.62 ^ clkbuf_1_0_3_clk/Z (BUF_X4) 0.04 5.66 ^ clkbuf_1_0_4_clk/Z (BUF_X4) 0.03 5.69 ^ clkbuf_2_0_0_clk/Z (BUF_X4) - 0.03 5.73 ^ clkbuf_2_0_1_clk/Z (BUF_X4) + 0.03 5.72 ^ clkbuf_2_0_1_clk/Z (BUF_X4) 0.03 5.76 ^ clkbuf_2_0_2_clk/Z (BUF_X4) - 0.03 5.80 ^ clkbuf_2_0_3_clk/Z (BUF_X4) + 0.03 5.79 ^ clkbuf_2_0_3_clk/Z (BUF_X4) 0.04 5.83 ^ clkbuf_2_0_4_clk/Z (BUF_X4) - 0.03 5.87 ^ clkbuf_3_0_0_clk/Z (BUF_X4) + 0.03 5.86 ^ clkbuf_3_0_0_clk/Z (BUF_X4) 0.03 5.90 ^ clkbuf_3_0_1_clk/Z (BUF_X4) 0.04 5.94 ^ clkbuf_3_0_2_clk/Z (BUF_X4) - 0.03 5.97 ^ clkbuf_4_0_0_clk/Z (BUF_X4) - 0.03 6.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4) + 0.03 5.96 ^ clkbuf_4_0_0_clk/Z (BUF_X4) + 0.03 5.99 ^ clkbuf_4_0_1_clk/Z (BUF_X4) 0.05 6.04 ^ clkbuf_4_0_2_clk/Z (BUF_X4) - 0.04 6.09 ^ clkbuf_5_1_0_clk/Z (BUF_X4) - 0.03 6.12 ^ max_length13/Z (BUF_X8) + 0.04 6.08 ^ clkbuf_5_1_0_clk/Z (BUF_X4) + 0.03 6.11 ^ max_length13/Z (BUF_X8) 0.04 6.15 ^ inst_2_1/clk (array_tile) 0.00 6.15 clock reconvergence pessimism -0.05 6.10 library setup time @@ -228,74 +228,74 @@ Path Type: max 0.00 0.00 clock source latency 0.00 0.00 ^ clk (in) 0.04 0.04 ^ wire7/Z (BUF_X8) - 0.04 0.08 ^ wire6/Z (BUF_X16) - 0.07 0.14 ^ wire5/Z (BUF_X32) - 0.06 0.20 ^ wire4/Z (BUF_X32) - 0.06 0.27 ^ wire3/Z (BUF_X32) - 0.06 0.33 ^ wire2/Z (BUF_X32) - 0.06 0.39 ^ wire1/Z (BUF_X32) - 0.06 0.45 ^ clkbuf_0_clk/Z (BUF_X4) - 0.04 0.49 ^ delaybuf_0_clk/Z (BUF_X4) + 0.03 0.07 ^ wire6/Z (BUF_X16) + 0.06 0.12 ^ wire5/Z (BUF_X16) + 0.06 0.19 ^ wire4/Z (BUF_X32) + 0.06 0.25 ^ wire3/Z (BUF_X32) + 0.06 0.32 ^ wire2/Z (BUF_X32) + 0.06 0.38 ^ wire1/Z (BUF_X32) + 0.07 0.45 ^ clkbuf_0_clk/Z (BUF_X4) + 0.04 0.48 ^ delaybuf_0_clk/Z (BUF_X4) 0.03 0.52 ^ clkbuf_1_0_0_clk/Z (BUF_X4) 0.03 0.55 ^ clkbuf_1_0_1_clk/Z (BUF_X4) - 0.03 0.59 ^ clkbuf_1_0_2_clk/Z (BUF_X4) + 0.03 0.58 ^ clkbuf_1_0_2_clk/Z (BUF_X4) 0.03 0.62 ^ clkbuf_1_0_3_clk/Z (BUF_X4) 0.04 0.66 ^ clkbuf_1_0_4_clk/Z (BUF_X4) 0.03 0.69 ^ clkbuf_2_0_0_clk/Z (BUF_X4) - 0.03 0.73 ^ clkbuf_2_0_1_clk/Z (BUF_X4) + 0.03 0.72 ^ clkbuf_2_0_1_clk/Z (BUF_X4) 0.03 0.76 ^ clkbuf_2_0_2_clk/Z (BUF_X4) - 0.03 0.80 ^ clkbuf_2_0_3_clk/Z (BUF_X4) + 0.03 0.79 ^ clkbuf_2_0_3_clk/Z (BUF_X4) 0.04 0.83 ^ clkbuf_2_0_4_clk/Z (BUF_X4) - 0.03 0.87 ^ clkbuf_3_0_0_clk/Z (BUF_X4) + 0.03 0.86 ^ clkbuf_3_0_0_clk/Z (BUF_X4) 0.03 0.90 ^ clkbuf_3_0_1_clk/Z (BUF_X4) 0.04 0.94 ^ clkbuf_3_0_2_clk/Z (BUF_X4) - 0.03 0.97 ^ clkbuf_4_0_0_clk/Z (BUF_X4) - 0.03 1.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4) + 0.03 0.96 ^ clkbuf_4_0_0_clk/Z (BUF_X4) + 0.03 0.99 ^ clkbuf_4_0_1_clk/Z (BUF_X4) 0.05 1.04 ^ clkbuf_4_0_2_clk/Z (BUF_X4) - 0.04 1.09 ^ clkbuf_5_1_0_clk/Z (BUF_X4) - 0.03 1.12 ^ max_length13/Z (BUF_X8) + 0.04 1.08 ^ clkbuf_5_1_0_clk/Z (BUF_X4) + 0.03 1.11 ^ max_length13/Z (BUF_X8) 0.04 1.15 ^ inst_2_1/clk (array_tile) - 0.21 1.37 ^ inst_2_1/w_out (array_tile) - 0.00 1.37 ^ inst_1_1/e_in (array_tile) - 1.37 data arrival time + 0.21 1.36 ^ inst_2_1/w_out (array_tile) + 0.00 1.36 ^ inst_1_1/e_in (array_tile) + 1.36 data arrival time 5.00 5.00 clock clk (rise edge) 0.00 5.00 clock source latency 0.00 5.00 ^ clk (in) 0.04 5.04 ^ wire7/Z (BUF_X8) - 0.04 5.08 ^ wire6/Z (BUF_X16) - 0.07 5.14 ^ wire5/Z (BUF_X32) - 0.06 5.20 ^ wire4/Z (BUF_X32) - 0.06 5.27 ^ wire3/Z (BUF_X32) - 0.06 5.33 ^ wire2/Z (BUF_X32) - 0.06 5.39 ^ wire1/Z (BUF_X32) - 0.06 5.45 ^ clkbuf_0_clk/Z (BUF_X4) - 0.04 5.49 ^ delaybuf_0_clk/Z (BUF_X4) + 0.03 5.07 ^ wire6/Z (BUF_X16) + 0.06 5.12 ^ wire5/Z (BUF_X16) + 0.06 5.19 ^ wire4/Z (BUF_X32) + 0.06 5.25 ^ wire3/Z (BUF_X32) + 0.06 5.32 ^ wire2/Z (BUF_X32) + 0.06 5.38 ^ wire1/Z (BUF_X32) + 0.07 5.45 ^ clkbuf_0_clk/Z (BUF_X4) + 0.04 5.48 ^ delaybuf_0_clk/Z (BUF_X4) 0.03 5.52 ^ clkbuf_1_0_0_clk/Z (BUF_X4) 0.03 5.55 ^ clkbuf_1_0_1_clk/Z (BUF_X4) - 0.03 5.59 ^ clkbuf_1_0_2_clk/Z (BUF_X4) + 0.03 5.58 ^ clkbuf_1_0_2_clk/Z (BUF_X4) 0.03 5.62 ^ clkbuf_1_0_3_clk/Z (BUF_X4) 0.04 5.66 ^ clkbuf_1_0_4_clk/Z (BUF_X4) 0.03 5.69 ^ clkbuf_2_0_0_clk/Z (BUF_X4) - 0.03 5.73 ^ clkbuf_2_0_1_clk/Z (BUF_X4) + 0.03 5.72 ^ clkbuf_2_0_1_clk/Z (BUF_X4) 0.03 5.76 ^ clkbuf_2_0_2_clk/Z (BUF_X4) - 0.03 5.80 ^ clkbuf_2_0_3_clk/Z (BUF_X4) + 0.03 5.79 ^ clkbuf_2_0_3_clk/Z (BUF_X4) 0.04 5.83 ^ clkbuf_2_0_4_clk/Z (BUF_X4) - 0.03 5.87 ^ clkbuf_3_0_0_clk/Z (BUF_X4) + 0.03 5.86 ^ clkbuf_3_0_0_clk/Z (BUF_X4) 0.03 5.90 ^ clkbuf_3_0_1_clk/Z (BUF_X4) 0.04 5.94 ^ clkbuf_3_0_2_clk/Z (BUF_X4) - 0.03 5.97 ^ clkbuf_4_0_0_clk/Z (BUF_X4) - 0.03 6.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4) + 0.03 5.96 ^ clkbuf_4_0_0_clk/Z (BUF_X4) + 0.03 5.99 ^ clkbuf_4_0_1_clk/Z (BUF_X4) 0.05 6.04 ^ clkbuf_4_0_2_clk/Z (BUF_X4) - 0.04 6.09 ^ clkbuf_5_0_0_clk/Z (BUF_X4) - 0.03 6.12 ^ max_length8/Z (BUF_X8) + 0.04 6.08 ^ clkbuf_5_0_0_clk/Z (BUF_X4) + 0.03 6.11 ^ max_length8/Z (BUF_X8) 0.04 6.15 ^ inst_1_1/clk (array_tile) 0.00 6.15 clock reconvergence pessimism -0.05 6.10 library setup time 6.10 data required time --------------------------------------------------------- 6.10 data required time - -1.37 data arrival time + -1.36 data arrival time --------------------------------------------------------- 4.74 slack (MET) diff --git a/src/cts/test/array_no_blockages.ok b/src/cts/test/array_no_blockages.ok index efd306e6652..b28537e88ee 100644 --- a/src/cts/test/array_no_blockages.ok +++ b/src/cts/test/array_no_blockages.ok @@ -65,20 +65,20 @@ [INFO CTS-0207] Leaf load cells 62 [INFO RSZ-0058] Using max wire length 693um. [INFO RSZ-0047] Found 33 long wires. -[INFO RSZ-0048] Inserted 92 buffers in 33 nets. +[INFO RSZ-0048] Inserted 93 buffers in 33 nets. Placement Analysis --------------------------------- -total displacement 2281.2 u +total displacement 2318.0 u average displacement 0.8 u -max displacement 84.5 u -original HPWL 133297.1 u -legalized HPWL 133608.9 u +max displacement 80.9 u +original HPWL 133115.2 u +legalized HPWL 133434.3 u delta HPWL 0 % Clock clk - 1.25 source latency inst_8_14/clk ^ - -1.11 target latency inst_10_14/clk ^ + 1.18 source latency inst_1_11/clk ^ + -1.06 target latency inst_2_11/clk ^ 0.00 CRPR -------------- - 0.14 setup skew + 0.12 setup skew diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc index aa2d0dcc41e..7a597b1400d 100644 --- a/src/dbSta/src/dbNetwork.cc +++ b/src/dbSta/src/dbNetwork.cc @@ -440,7 +440,8 @@ Term* DbNetTermIterator::next() dbBTerm* bterm = *iter_; iter_++; return network_->dbToStaTerm(bterm); - } else if (mod_iter_ != mod_end_ && (network_->hasHierarchy())) { + } + if (mod_iter_ != mod_end_ && (network_->hasHierarchy())) { dbModBTerm* modbterm = *mod_iter_; mod_iter_++; return network_->dbToStaTerm(modbterm); @@ -843,10 +844,12 @@ Net* dbNetwork::net(const Pin* pin) const // that we have both a mod net and a dbinst net. // In the case of writing out a hierachical network we always // choose the mnet. - if (mnet) + if (mnet) { return dbToSta(mnet); - if (dnet) + } + if (dnet) { return dbToSta(dnet); + } } // only pins which act as bterms are top levels and have no net if (bterm) { @@ -1092,7 +1095,8 @@ const char* dbNetwork::name(const Net* net) const if (dnet) { const char* name = dnet->getConstName(); return tmpStringCopy(name); - } else if (modnet) { + } + if (modnet) { std::string net_name = modnet->getName(); return tmpStringCopy(net_name.c_str()); } @@ -1134,8 +1138,9 @@ void dbNetwork::visitConnectedPins(const Net* net, dbModNet* mod_net = nullptr; dbNet* db_net = nullptr; - if (visited_nets.hasKey(net)) + if (visited_nets.hasKey(net)) { return; + } visited_nets.insert(net); staToDb(net, db_net, mod_net); @@ -1230,7 +1235,8 @@ Pin* dbNetwork::pin(const Term* term) const staToDb(term, iterm, bterm, moditerm, modbterm); if (bterm) { return dbToSta(bterm); - } else if (modbterm) { + } + if (modbterm) { // get the moditerm dbModule* cur_module = modbterm->getParent(); dbModInst* cur_mod_inst = cur_module->getModInst(); @@ -1257,11 +1263,13 @@ Net* dbNetwork::net(const Term* term) const } if (bterm) { dbModNet* mod_net = bterm->getModNet(); - if (mod_net) + if (mod_net) { return dbToSta(mod_net); + } dbNet* dnet = bterm->getNet(); - if (dnet) + if (dnet) { return dbToSta(dnet); + } } return nullptr; } diff --git a/src/dbSta/test/regression_tests.tcl b/src/dbSta/test/regression_tests.tcl index 7c2d5b165c0..eff10ed8edc 100644 --- a/src/dbSta/test/regression_tests.tcl +++ b/src/dbSta/test/regression_tests.tcl @@ -1,4 +1,5 @@ record_tests { + hierclock hier2 readdb_hier constant1 diff --git a/src/dpo/src/Optdp.cpp b/src/dpo/src/Optdp.cpp index 330143b1c60..5f00094efec 100644 --- a/src/dpo/src/Optdp.cpp +++ b/src/dpo/src/Optdp.cpp @@ -61,6 +61,7 @@ namespace dpo { using utl::DPO; using odb::dbBlock; +using odb::dbBlockage; using odb::dbBox; using odb::dbBTerm; using odb::dbInst; @@ -376,11 +377,6 @@ void Optdp::setupMasterPowers() //////////////////////////////////////////////////////////////// void Optdp::createNetwork() { - std::unordered_map::iterator it_n; - std::unordered_map::iterator it_e; - std::unordered_map::iterator it_p; - std::unordered_map>::iterator it_m; - dbBlock* block = db_->getChip()->getBlock(); pwrLayers_.clear(); @@ -388,21 +384,13 @@ void Optdp::createNetwork() // I allocate things statically, so I need to do some counting. - std::vector insts; - for (dbInst* inst : block->getInsts()) { - insts.push_back(inst); - } + auto block_insts = block->getInsts(); + std::vector insts(block_insts.begin(), block_insts.end()); std::stable_sort(insts.begin(), insts.end(), [](dbInst* a, dbInst* b) { return a->getName() < b->getName(); }); - dbSet nets = block->getNets(); - dbSet bterms = block->getBTerms(); - // Number of this and that. - int nTerminals = bterms.size(); int nNodes = 0; - int nEdges = 0; - int nPins = 0; for (dbInst* inst : insts) { // Skip instances which are not placeable. if (!inst->getMaster()->isCoreAutoPlaceable()) { @@ -411,6 +399,9 @@ void Optdp::createNetwork() ++nNodes; } + dbSet nets = block->getNets(); + int nEdges = 0; + int nPins = 0; for (dbNet* net : nets) { // Skip supply nets. if (net->getSigType().isSupply()) { @@ -429,14 +420,26 @@ void Optdp::createNetwork() nPins += net->getBTerms().size(); } + dbSet bterms = block->getBTerms(); + const int nTerminals = bterms.size(); + + int nBlockages = 0; + for (dbBlockage* blockage : block->getBlockages()) { + if (!blockage->isSoft()) { + network_->createAndAddBlockage(blockage->getBBox()->getBox()); + ++nBlockages; + } + } + logger_->info(DPO, 100, "Creating network with {:d} cells, {:d} terminals, " - "{:d} edges and {:d} pins.", + "{:d} edges, {:d} pins, and {:d} blockages.", nNodes, nTerminals, nEdges, - nPins); + nPins, + nBlockages); // Create and allocate the nodes. I require nodes for // placeable instances as well as terminals. @@ -504,7 +507,7 @@ void Optdp::createNetwork() ndi->setLeftEdgeType(EDGETYPE_DEFAULT); // Set the top and bottom power. - it_m = masterPwrs_.find(inst->getMaster()); + auto it_m = masterPwrs_.find(inst->getMaster()); if (masterPwrs_.end() == it_m) { ndi->setBottomPower(Architecture::Row::Power_UNK); ndi->setTopPower(Architecture::Row::Power_UNK); @@ -586,7 +589,7 @@ void Optdp::createNetwork() continue; } - it_n = instMap_.find(iTerm->getInst()); + auto it_n = instMap_.find(iTerm->getInst()); if (instMap_.end() != it_n) { n = it_n->second->getId(); // The node id. @@ -627,7 +630,7 @@ void Optdp::createNetwork() } } for (dbBTerm* bTerm : net->getBTerms()) { - it_p = termMap_.find(bTerm); + auto it_p = termMap_.find(bTerm); if (termMap_.end() != it_p) { n = it_p->second->getId(); // The node id. diff --git a/src/dpo/src/detailed_manager.cxx b/src/dpo/src/detailed_manager.cxx index adf34c4c5b1..2e91b92f0ab 100644 --- a/src/dpo/src/detailed_manager.cxx +++ b/src/dpo/src/detailed_manager.cxx @@ -213,6 +213,23 @@ void DetailedMgr::findBlockages(bool includeRouteBlockages) } } + for (int i = 0; i < network_->getNumBlockages(); i++) { + const odb::Rect& blockage = network_->getBlockage(i); + const int xmin = std::max(arch_->getMinX(), blockage.xMin()); + const int xmax = std::min(arch_->getMaxX(), blockage.xMax()); + const int ymin = std::max(arch_->getMinY(), blockage.yMin()); + const int ymax = std::min(arch_->getMaxY(), blockage.yMax()); + + for (int r = 0; r < numSingleHeightRows_; r++) { + int yb = arch_->getRow(r)->getBottom(); + int yt = arch_->getRow(r)->getTop(); + + if (!(ymin >= yt || ymax <= yb)) { + blockages_[r].push_back(std::pair(xmin, xmax)); + } + } + } + if (includeRouteBlockages && rt_ != nullptr) { // Turn M1 and M2 routing blockages into placement blockages. The idea // here is to be quite conservative and prevent the possibility of pin diff --git a/src/dpo/src/network.cxx b/src/dpo/src/network.cxx index 8689183cd66..f03e5c5c14c 100644 --- a/src/dpo/src/network.cxx +++ b/src/dpo/src/network.cxx @@ -192,6 +192,12 @@ Node* Network::createAndAddNode() } //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// +void Network::createAndAddBlockage(const odb::Rect& bounds) +{ + blockages_.emplace_back(bounds); +} +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// Node* Network::createAndAddFillerNode(int left, int bottom, int width, diff --git a/src/dpo/src/network.h b/src/dpo/src/network.h index dc7cfd395e9..322b49c825c 100644 --- a/src/dpo/src/network.h +++ b/src/dpo/src/network.h @@ -44,6 +44,7 @@ #include #include "architecture.h" +#include "odb/geom.h" #include "orientation.h" namespace dpo { @@ -290,6 +291,9 @@ class Network int getNumPins() const { return (int) pins_.size(); } + int getNumBlockages() const { return (int) blockages_.size(); } + odb::Rect getBlockage(int i) const { return blockages_[i]; } + // For creating and adding pins. Pin* createAndAddPin(Node* nd, Edge* ed); @@ -303,6 +307,8 @@ class Network // For creating and adding edges. Edge* createAndAddEdge(); + void createAndAddBlockage(const odb::Rect& bounds); + private: Pin* createAndAddPin(); @@ -310,7 +316,8 @@ class Network std::unordered_map edgeNames_; // Names of edges... std::vector nodes_; // The nodes in the netlist... std::unordered_map nodeNames_; // Names of nodes... - std::vector pins_; // The pins in the network... + std::vector pins_; // The pins in the network... + std::vector blockages_; // The placement blockages ... }; } // namespace dpo diff --git a/src/dpo/test/aes.ok b/src/dpo/test/aes.ok index beedb6e5bd6..961a415f2a8 100644 --- a/src/dpo/test/aes.ok +++ b/src/dpo/test/aes.ok @@ -5,7 +5,7 @@ [INFO ODB-0133] Created 19675 nets and 65708 connections. Detailed placement improvement. Importing netlist into detailed improver. -[INFO DPO-0100] Creating network with 21340 cells, 391 terminals, 19675 edges and 66099 pins. +[INFO DPO-0100] Creating network with 21340 cells, 391 terminals, 19675 edges, 66099 pins, and 0 blockages. [INFO DPO-0109] Network stats: inst 21731, edges 19675, pins 66099 [INFO DPO-0110] Number of regions is 1 [INFO DPO-0401] Setting random seed to 1. diff --git a/src/dpo/test/blockage1.def b/src/dpo/test/blockage1.def new file mode 100644 index 00000000000..7823bfc9627 --- /dev/null +++ b/src/dpo/test/blockage1.def @@ -0,0 +1,73 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN gcd ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 86840 86840 ) ; +ROW ROW_0 unithd 1380 2720 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_1 unithd 1380 5440 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_2 unithd 1380 8160 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_3 unithd 1380 10880 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_4 unithd 1380 13600 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_5 unithd 1380 16320 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_6 unithd 1380 19040 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_7 unithd 1380 21760 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_8 unithd 1380 24480 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_9 unithd 1380 27200 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_10 unithd 1380 29920 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_11 unithd 1380 32640 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_12 unithd 1380 35360 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_13 unithd 1380 38080 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_14 unithd 1380 40800 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_15 unithd 1380 43520 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_16 unithd 1380 46240 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_17 unithd 1380 48960 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_18 unithd 1380 51680 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_19 unithd 1380 54400 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_20 unithd 1380 57120 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_21 unithd 1380 59840 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_22 unithd 1380 62560 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_23 unithd 1380 65280 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_24 unithd 1380 68000 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_25 unithd 1380 70720 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_26 unithd 1380 73440 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_27 unithd 1380 76160 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_28 unithd 1380 78880 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_29 unithd 1380 81600 FS DO 183 BY 1 STEP 460 0 ; +TRACKS X 230 DO 189 STEP 460 LAYER li1 ; +TRACKS Y 170 DO 255 STEP 340 LAYER li1 ; +TRACKS X 170 DO 255 STEP 340 LAYER met1 ; +TRACKS Y 170 DO 255 STEP 340 LAYER met1 ; +TRACKS X 230 DO 189 STEP 460 LAYER met2 ; +TRACKS Y 230 DO 189 STEP 460 LAYER met2 ; +TRACKS X 340 DO 127 STEP 680 LAYER met3 ; +TRACKS Y 340 DO 127 STEP 680 LAYER met3 ; +TRACKS X 460 DO 94 STEP 920 LAYER met4 ; +TRACKS Y 460 DO 94 STEP 920 LAYER met4 ; +TRACKS X 1700 DO 25 STEP 3400 LAYER met5 ; +TRACKS Y 1700 DO 25 STEP 3400 LAYER met5 ; +GCELLGRID X 0 DO 12 STEP 6900 ; +GCELLGRID Y 0 DO 12 STEP 6900 ; +VIAS 4 ; + - via2_3_1600_480_1_5_320_320 + VIARULE M1M2_PR + CUTSIZE 150 150 + LAYERS met1 via met2 + CUTSPACING 170 170 + ENCLOSURE 85 165 55 85 + ROWCOL 1 5 ; + - via3_4_1600_480_1_4_400_400 + VIARULE M2M3_PR + CUTSIZE 200 200 + LAYERS met2 via2 met3 + CUTSPACING 200 200 + ENCLOSURE 40 85 65 65 + ROWCOL 1 4 ; + - via4_5_1600_480_1_4_400_400 + VIARULE M3M4_PR + CUTSIZE 200 200 + LAYERS met3 via3 met4 + CUTSPACING 200 200 + ENCLOSURE 90 60 100 65 + ROWCOL 1 4 ; + - via5_6_1600_1600_1_1_1600_1600 + VIARULE M4M5_PR + CUTSIZE 800 800 + LAYERS met4 via4 met5 + CUTSPACING 800 800 + ENCLOSURE 400 190 310 400 ; +END VIAS +COMPONENTS 1 ; + - dpath.a_lt_b$in0\[11\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 41400 51680 ) N ; +END COMPONENTS +PINS 1 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 400 71060 ) N ; +END PINS +BLOCKAGES 1 ; + - PLACEMENT RECT ( 29440 18800 ) ( 41289 73680 ) ; +END BLOCKAGES +NETS 2 ; + - clk ( PIN clk ) ( dpath.a_lt_b$in0\[11\]$_DFFE_PP_ CLK ) + USE CLOCK ; + - ctrl.state.out\[1\] + USE SIGNAL ; +END NETS +END DESIGN diff --git a/src/dpo/test/blockage1.defok b/src/dpo/test/blockage1.defok new file mode 100644 index 00000000000..eab5efd7076 --- /dev/null +++ b/src/dpo/test/blockage1.defok @@ -0,0 +1,73 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN gcd ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 86840 86840 ) ; +ROW ROW_0 unithd 1380 2720 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_1 unithd 1380 5440 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_2 unithd 1380 8160 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_3 unithd 1380 10880 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_4 unithd 1380 13600 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_5 unithd 1380 16320 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_6 unithd 1380 19040 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_7 unithd 1380 21760 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_8 unithd 1380 24480 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_9 unithd 1380 27200 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_10 unithd 1380 29920 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_11 unithd 1380 32640 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_12 unithd 1380 35360 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_13 unithd 1380 38080 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_14 unithd 1380 40800 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_15 unithd 1380 43520 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_16 unithd 1380 46240 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_17 unithd 1380 48960 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_18 unithd 1380 51680 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_19 unithd 1380 54400 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_20 unithd 1380 57120 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_21 unithd 1380 59840 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_22 unithd 1380 62560 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_23 unithd 1380 65280 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_24 unithd 1380 68000 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_25 unithd 1380 70720 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_26 unithd 1380 73440 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_27 unithd 1380 76160 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_28 unithd 1380 78880 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_29 unithd 1380 81600 FS DO 183 BY 1 STEP 460 0 ; +TRACKS X 230 DO 189 STEP 460 LAYER li1 ; +TRACKS Y 170 DO 255 STEP 340 LAYER li1 ; +TRACKS X 170 DO 255 STEP 340 LAYER met1 ; +TRACKS Y 170 DO 255 STEP 340 LAYER met1 ; +TRACKS X 230 DO 189 STEP 460 LAYER met2 ; +TRACKS Y 230 DO 189 STEP 460 LAYER met2 ; +TRACKS X 340 DO 127 STEP 680 LAYER met3 ; +TRACKS Y 340 DO 127 STEP 680 LAYER met3 ; +TRACKS X 460 DO 94 STEP 920 LAYER met4 ; +TRACKS Y 460 DO 94 STEP 920 LAYER met4 ; +TRACKS X 1700 DO 25 STEP 3400 LAYER met5 ; +TRACKS Y 1700 DO 25 STEP 3400 LAYER met5 ; +GCELLGRID X 0 DO 12 STEP 6900 ; +GCELLGRID Y 0 DO 12 STEP 6900 ; +VIAS 4 ; + - via2_3_1600_480_1_5_320_320 + VIARULE M1M2_PR + CUTSIZE 150 150 + LAYERS met1 via met2 + CUTSPACING 170 170 + ENCLOSURE 85 165 55 85 + ROWCOL 1 5 ; + - via3_4_1600_480_1_4_400_400 + VIARULE M2M3_PR + CUTSIZE 200 200 + LAYERS met2 via2 met3 + CUTSPACING 200 200 + ENCLOSURE 40 85 65 65 + ROWCOL 1 4 ; + - via4_5_1600_480_1_4_400_400 + VIARULE M3M4_PR + CUTSIZE 200 200 + LAYERS met3 via3 met4 + CUTSPACING 200 200 + ENCLOSURE 90 60 100 65 + ROWCOL 1 4 ; + - via5_6_1600_1600_1_1_1600_1600 + VIARULE M4M5_PR + CUTSIZE 800 800 + LAYERS met4 via4 met5 + CUTSPACING 800 800 + ENCLOSURE 400 190 310 400 ; +END VIAS +COMPONENTS 1 ; + - dpath.a_lt_b$in0\[11\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 41860 54400 ) FS ; +END COMPONENTS +PINS 1 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 400 71060 ) N ; +END PINS +BLOCKAGES 1 ; + - PLACEMENT RECT ( 29440 18800 ) ( 41289 73680 ) ; +END BLOCKAGES +NETS 2 ; + - clk ( PIN clk ) ( dpath.a_lt_b$in0\[11\]$_DFFE_PP_ CLK ) + USE CLOCK ; + - ctrl.state.out\[1\] + USE SIGNAL ; +END NETS +END DESIGN diff --git a/src/dpo/test/blockage1.ok b/src/dpo/test/blockage1.ok new file mode 100644 index 00000000000..f56cb315f99 --- /dev/null +++ b/src/dpo/test/blockage1.ok @@ -0,0 +1,67 @@ +[INFO ODB-0227] LEF file: sky130hd/sky130hd.tlef, created 13 layers, 25 vias +[INFO ODB-0227] LEF file: sky130hd/sky130hd_std_cell.lef, created 437 library cells +[INFO ODB-0128] Design: gcd +[INFO ODB-0130] Created 1 pins. +[INFO ODB-0131] Created 1 components and 5 component-terminals. +[INFO ODB-0133] Created 2 nets and 1 connections. +Detailed placement improvement. +Importing netlist into detailed improver. +[INFO DPO-0100] Creating network with 1 cells, 1 terminals, 2 edges, 2 pins, and 1 blockages. +[INFO DPO-0109] Network stats: inst 2, edges 2, pins 2 +[INFO DPO-0110] Number of regions is 1 +[INFO DPO-0401] Setting random seed to 1. +[INFO DPO-0402] Setting maximum displacement 5 1 to 13600 2720 units. +[INFO DPO-0320] Collected 1 fixed cells (excluded terminal_NI). +[INFO DPO-0318] Collected 1 single height cells. +[INFO DPO-0321] Collected 0 wide cells. +[INFO DPO-0322] Image (1380, 2720) - (85560, 84320) +[INFO DPO-0310] Assigned 1 cells into segments. Movement in X-direction is 0.000000, movement in Y-direction is 0.000000. +[INFO DPO-0313] Found 0 cells in wrong regions. +[INFO DPO-0315] Found 0 row alignment problems. +[INFO DPO-0314] Found 0 site alignment problems. +[INFO DPO-0311] Found 0 overlaps between adjacent cells. +[INFO DPO-0312] Found 0 edge spacing violations and 0 padding violations. +[INFO DPO-0303] Running algorithm for independent set matching. +[INFO DPO-0300] Set matching objective is wirelength. +[INFO DPO-0301] Pass 1 of matching; objective is 5.887000e+04. +[INFO DPO-0302] End of matching; objective is 5.887000e+04, improvement is 0.00 percent. +[INFO DPO-0303] Running algorithm for global swaps. +[INFO DPO-0306] Pass 1 of global swaps; hpwl is 5.887000e+04. +[INFO DPO-0307] End of global swaps; objective is 5.887000e+04, improvement is 0.00 percent. +[INFO DPO-0303] Running algorithm for vertical swaps. +[INFO DPO-0308] Pass 1 of vertical swaps; hpwl is 5.887000e+04. +[INFO DPO-0309] End of vertical swaps; objective is 5.887000e+04, improvement is 0.00 percent. +[INFO DPO-0303] Running algorithm for reordering. +[INFO DPO-0304] Pass 1 of reordering; objective is 5.887000e+04. +[INFO DPO-0305] End of reordering; objective is 5.887000e+04, improvement is 0.00 percent. +[INFO DPO-0303] Running algorithm for random improvement. +[INFO DPO-0324] Random improver is using displacement generator. +[INFO DPO-0325] Random improver is using hpwl objective. +[INFO DPO-0326] Random improver cost string is (a). +[INFO DPO-0332] End of pass, Generator displacement called 20 times. +[INFO DPO-0335] Generator displacement, Cumulative attempts 20, swaps 0, moves 17 since last reset. +[INFO DPO-0333] End of pass, Objective hpwl, Initial cost 5.887000e+04, Scratch cost 5.661000e+04, Incremental cost 5.661000e+04, Mismatch? N +[INFO DPO-0338] End of pass, Total cost is 5.661000e+04. +[INFO DPO-0327] Pass 1 of random improver; improvement in cost is 3.84 percent. +[INFO DPO-0332] End of pass, Generator displacement called 20 times. +[INFO DPO-0335] Generator displacement, Cumulative attempts 40, swaps 0, moves 32 since last reset. +[INFO DPO-0333] End of pass, Objective hpwl, Initial cost 5.661000e+04, Scratch cost 5.661000e+04, Incremental cost 5.661000e+04, Mismatch? N +[INFO DPO-0338] End of pass, Total cost is 5.661000e+04. +[INFO DPO-0327] Pass 2 of random improver; improvement in cost is 0.00 percent. +[INFO DPO-0328] End of random improver; improvement is 3.838967 percent. +[INFO DPO-0380] Cell flipping. +[INFO DPO-0382] Changed 1 cell orientations for row compatibility. +[INFO DPO-0383] Performed 0 cell flips. +[INFO DPO-0384] End of flipping; objective is 5.714000e+04, improvement is -0.94 percent. +[INFO DPO-0313] Found 0 cells in wrong regions. +[INFO DPO-0315] Found 0 row alignment problems. +[INFO DPO-0314] Found 0 site alignment problems. +[INFO DPO-0311] Found 0 overlaps between adjacent cells. +[INFO DPO-0312] Found 0 edge spacing violations and 0 padding violations. +Detailed Improvement Results +------------------------------------------ +Original HPWL 59.3 u +Final HPWL 57.0 u +Delta HPWL -4.0 % + +No differences found. diff --git a/src/dpo/test/blockage1.tcl b/src/dpo/test/blockage1.tcl new file mode 100644 index 00000000000..cf99688684a --- /dev/null +++ b/src/dpo/test/blockage1.tcl @@ -0,0 +1,10 @@ +source "helpers.tcl" +read_lef sky130hd/sky130hd.tlef +read_lef sky130hd/sky130hd_std_cell.lef +read_def blockage1.def +improve_placement -max_displacement {5 1} +check_placement + +set def_file [make_result_file blockage1.def] +write_def $def_file +diff_file $def_file blockage1.defok diff --git a/src/dpo/test/gcd.ok b/src/dpo/test/gcd.ok index a722aecc21d..fbba206bcb9 100644 --- a/src/dpo/test/gcd.ok +++ b/src/dpo/test/gcd.ok @@ -5,7 +5,7 @@ [INFO ODB-0133] Created 364 nets and 1068 connections. Detailed placement improvement. Importing netlist into detailed improver. -[INFO DPO-0100] Creating network with 549 cells, 54 terminals, 364 edges and 1122 pins. +[INFO DPO-0100] Creating network with 549 cells, 54 terminals, 364 edges, 1122 pins, and 0 blockages. [INFO DPO-0109] Network stats: inst 603, edges 364, pins 1122 [INFO DPO-0110] Number of regions is 1 [INFO DPO-0401] Setting random seed to 1. diff --git a/src/dpo/test/gcd_no_one_site_gaps.ok b/src/dpo/test/gcd_no_one_site_gaps.ok index 5194d0dd4a6..bcec05501ee 100644 --- a/src/dpo/test/gcd_no_one_site_gaps.ok +++ b/src/dpo/test/gcd_no_one_site_gaps.ok @@ -5,7 +5,7 @@ [INFO ODB-0133] Created 364 nets and 1068 connections. Detailed placement improvement. Importing netlist into detailed improver. -[INFO DPO-0100] Creating network with 549 cells, 54 terminals, 364 edges and 1122 pins. +[INFO DPO-0100] Creating network with 549 cells, 54 terminals, 364 edges, 1122 pins, and 0 blockages. [INFO DPO-0109] Network stats: inst 603, edges 364, pins 1122 [INFO DPO-0110] Number of regions is 1 [INFO DPO-0401] Setting random seed to 1. diff --git a/src/dpo/test/ibex.ok b/src/dpo/test/ibex.ok index 90537fa92cb..6b8807fc313 100644 --- a/src/dpo/test/ibex.ok +++ b/src/dpo/test/ibex.ok @@ -5,7 +5,7 @@ [INFO ODB-0133] Created 33171 nets and 104681 connections. Detailed placement improvement. Importing netlist into detailed improver. -[INFO DPO-0100] Creating network with 34184 cells, 231 terminals, 33171 edges and 104912 pins. +[INFO DPO-0100] Creating network with 34184 cells, 231 terminals, 33171 edges, 104912 pins, and 0 blockages. [INFO DPO-0109] Network stats: inst 34415, edges 33171, pins 104912 [INFO DPO-0110] Number of regions is 1 [INFO DPO-0401] Setting random seed to 1. diff --git a/src/dpo/test/multi_height1.ok b/src/dpo/test/multi_height1.ok index d329c867a3f..06c85988a8e 100644 --- a/src/dpo/test/multi_height1.ok +++ b/src/dpo/test/multi_height1.ok @@ -6,7 +6,7 @@ [INFO ODB-0133] Created 6 nets and 0 connections. Detailed placement improvement. Importing netlist into detailed improver. -[INFO DPO-0100] Creating network with 5 cells, 6 terminals, 6 edges and 6 pins. +[INFO DPO-0100] Creating network with 5 cells, 6 terminals, 6 edges, 6 pins, and 0 blockages. [INFO DPO-0109] Network stats: inst 11, edges 6, pins 6 [WARNING DPO-0108] Skipping all the rows with sites [DoubleHeightSite] as their height is 5600 and the single-height is 2800. [WARNING DPO-0108] Skipping all the rows with sites [TripleHeightSite] as their height is 8400 and the single-height is 2800. diff --git a/src/dpo/test/regions1.ok b/src/dpo/test/regions1.ok index 19e65b3bbf1..d6321c7aa27 100644 --- a/src/dpo/test/regions1.ok +++ b/src/dpo/test/regions1.ok @@ -5,7 +5,7 @@ [INFO ODB-0133] Created 2 nets and 2 connections. Detailed placement improvement. Importing netlist into detailed improver. -[INFO DPO-0100] Creating network with 5 cells, 2 terminals, 2 edges and 4 pins. +[INFO DPO-0100] Creating network with 5 cells, 2 terminals, 2 edges, 4 pins, and 0 blockages. [INFO DPO-0109] Network stats: inst 7, edges 2, pins 4 [INFO DPO-0110] Number of regions is 3 [INFO DPO-0401] Setting random seed to 1. diff --git a/src/dpo/test/regions2.ok b/src/dpo/test/regions2.ok index 45344a42f03..1f66b192d9b 100644 --- a/src/dpo/test/regions2.ok +++ b/src/dpo/test/regions2.ok @@ -5,7 +5,7 @@ [INFO ODB-0133] Created 2 nets and 2 connections. Detailed placement improvement. Importing netlist into detailed improver. -[INFO DPO-0100] Creating network with 4 cells, 2 terminals, 2 edges and 4 pins. +[INFO DPO-0100] Creating network with 4 cells, 2 terminals, 2 edges, 4 pins, and 0 blockages. [INFO DPO-0109] Network stats: inst 6, edges 2, pins 4 [INFO DPO-0110] Number of regions is 3 [INFO DPO-0401] Setting random seed to 1. diff --git a/src/dpo/test/regression_tests.tcl b/src/dpo/test/regression_tests.tcl index c18407eef28..713b3ea49a3 100644 --- a/src/dpo/test/regression_tests.tcl +++ b/src/dpo/test/regression_tests.tcl @@ -1,5 +1,6 @@ record_tests { aes + blockage1 gcd ibex multi_height1 diff --git a/src/dpo/test/sky130hd b/src/dpo/test/sky130hd new file mode 120000 index 00000000000..2363d2b2e2a --- /dev/null +++ b/src/dpo/test/sky130hd @@ -0,0 +1 @@ +../../../test/sky130hd \ No newline at end of file diff --git a/src/grt/src/fastroute/src/FastRoute.cpp b/src/grt/src/fastroute/src/FastRoute.cpp index 4dc070b85c5..a0474e7e2ef 100644 --- a/src/grt/src/fastroute/src/FastRoute.cpp +++ b/src/grt/src/fastroute/src/FastRoute.cpp @@ -816,6 +816,9 @@ void FastRouteCore::getBlockage(odb::dbTechLayer* layer, void FastRouteCore::updateDbCongestion() { + if (h_edges_3D_.num_elements() == 0) { // no information + return; + } auto block = db_->getChip()->getBlock(); auto db_gcell = block->getGCellGrid(); if (db_gcell) diff --git a/src/mpl2/README.md b/src/mpl2/README.md index 861e16e30c1..0d84aa6a7a7 100644 --- a/src/mpl2/README.md +++ b/src/mpl2/README.md @@ -73,7 +73,7 @@ rtl_macro_placer | `-snap_layer` | Snap macro origins to this routing layer track. The default value is 4, and the allowed values are integers `[1, MAX_LAYER]`). | | `-bus_planning` | Flag to enable bus planning. We recommend to enable bus planning for technologies with very limited routing layers such as SKY130 and GF180. As for technologies such as NanGate45 and ASAP7, we recommend to keep it disabled. | | `-report_directory` | Save reports to this directory. | -| `-write_macro_placement` | Generates a file with the placement of the macros placed by HierRTLMP flow in the format of multiple calls for the `place_macro` command. | +| `-write_macro_placement` | Generates a file with the design's macro placement in the format of calls for the `place_macro` command. | #### Simulated Annealing Weight parameters @@ -92,7 +92,7 @@ Do note that while action probabilities are normalized to 1.0, the weights are n ### Place Macro -Command for placement of one specific macro. +Command for manual placement of a single macro. ```tcl place_macro diff --git a/src/mpl2/src/SimulatedAnnealingCore.cpp b/src/mpl2/src/SimulatedAnnealingCore.cpp index 0dc6877b5f8..bcc8f8e249e 100644 --- a/src/mpl2/src/SimulatedAnnealingCore.cpp +++ b/src/mpl2/src/SimulatedAnnealingCore.cpp @@ -642,6 +642,8 @@ void SimulatedAnnealingCore::attemptCentralization(const float pre_cost) // revert centralization if (calNormCost() > pre_cost) { + centralization_was_reverted_ = true; + for (int& id : pos_seq_) { macros_[id].setX(clusters_locations[id].first); macros_[id].setY(clusters_locations[id].second); diff --git a/src/mpl2/src/SimulatedAnnealingCore.h b/src/mpl2/src/SimulatedAnnealingCore.h index 53651173072..825a5a399bf 100644 --- a/src/mpl2/src/SimulatedAnnealingCore.h +++ b/src/mpl2/src/SimulatedAnnealingCore.h @@ -97,6 +97,7 @@ class SimulatedAnnealingCore { centralization_on_ = centralization_on; }; + bool centralizationWasReverted() { return centralization_was_reverted_; } void setNets(const std::vector& nets); // Fence corresponds to each macro (macro_id, fence) @@ -243,6 +244,7 @@ class SimulatedAnnealingCore bool has_initial_sequence_pair_ = false; bool centralization_on_ = false; + bool centralization_was_reverted_ = false; }; // SACore wrapper function diff --git a/src/mpl2/src/hier_rtlmp.cpp b/src/mpl2/src/hier_rtlmp.cpp index 97cc43b4fbc..b7990aff229 100644 --- a/src/mpl2/src/hier_rtlmp.cpp +++ b/src/mpl2/src/hier_rtlmp.cpp @@ -46,6 +46,7 @@ #include "db_sta/dbNetwork.hh" #include "object.h" #include "odb/db.h" +#include "odb/util.h" #include "par/PartitionMgr.h" #include "sta/Liberty.hh" #include "utl/Logger.h" @@ -3926,8 +3927,12 @@ void HierRTLMP::runHierarchicalMacroPlacement(Cluster* parent) logger_->error(MPL, 5, "Failed on cluster {}", parent->getName()); } - best_sa->alignMacroClusters(); + + if (best_sa->centralizationWasReverted()) { + best_sa->alignMacroClusters(); + } best_sa->fillDeadSpace(); + // update the clusters and do bus planning std::vector shaped_macros; best_sa->getMacros(shaped_macros); @@ -4179,8 +4184,12 @@ void HierRTLMP::runHierarchicalMacroPlacement(Cluster* parent) logger_->error(MPL, 6, "Failed on cluster {}", parent->getName()); } - best_sa->alignMacroClusters(); + + if (best_sa->centralizationWasReverted()) { + best_sa->alignMacroClusters(); + } best_sa->fillDeadSpace(); + // update the clusters and do bus planning best_sa->getMacros(shaped_macros); } @@ -4715,7 +4724,9 @@ void HierRTLMP::runHierarchicalMacroPlacementWithoutBusPlanning(Cluster* parent) runEnhancedHierarchicalMacroPlacement(parent); } else { - best_sa->alignMacroClusters(); + if (best_sa->centralizationWasReverted()) { + best_sa->alignMacroClusters(); + } best_sa->fillDeadSpace(); std::vector shaped_macros; @@ -5198,8 +5209,12 @@ void HierRTLMP::runEnhancedHierarchicalMacroPlacement(Cluster* parent) } logger_->error(MPL, 40, "Failed on cluster {}", parent->getName()); } - best_sa->alignMacroClusters(); + + if (best_sa->centralizationWasReverted()) { + best_sa->alignMacroClusters(); + } best_sa->fillDeadSpace(); + // update the clusters and do bus planning std::vector shaped_macros; best_sa->getMacros(shaped_macros); @@ -6196,26 +6211,13 @@ void HierRTLMP::writeMacroPlacement(const std::string& file_name) return; } - logger_->warn(MPL, - 39, - "The flag -write_macro_placement is deprecated. Use the .tcl " - "command write_macro_placement instead."); - std::ofstream out(file_name); if (!out) { logger_->error(MPL, 11, "Cannot open file {}.", file_name); } - // Use only insts that were placed by mpl2 - for (auto& [inst, hard_macro] : hard_macro_map_) { - const float x = dbuToMicron(inst->getLocation().x(), dbu_); - const float y = dbuToMicron(inst->getLocation().y(), dbu_); - - out << "place_macro -macro_name " << inst->getName() << " -location {" << x - << " " << y << "} -orientation " << inst->getOrient().getString() - << '\n'; - } + out << odb::generateMacroPlacementString(block_); } void HierRTLMP::clear() diff --git a/src/odb/src/db/dbArrayTable.hpp b/src/odb/src/db/dbArrayTable.hpp index d1a048b913b..a9d2de558be 100644 --- a/src/odb/src/db/dbArrayTable.hpp +++ b/src/odb/src/db/dbArrayTable.hpp @@ -248,9 +248,10 @@ T* dbArrayTable::create() } _dbFreeObject* o = popQ(_free_list); - o->_oid |= DB_ALLOC_BIT; + const uint oid = o->_oid; new (o) T(_db); T* t = (T*) o; + t->_oid = oid | DB_ALLOC_BIT; dbArrayTablePage* page = (dbArrayTablePage*) t->getObjectPage(); page->_alloccnt++; @@ -302,8 +303,9 @@ void dbArrayTable::destroy(T* t) _dbFreeObject* o = (_dbFreeObject*) t; page->_alloccnt--; + const uint oid = t->_oid; t->~T(); // call destructor - o->_oid &= ~DB_ALLOC_BIT; + o->_oid = oid & ~DB_ALLOC_BIT; // Add to freelist pushQ(_free_list, o); @@ -395,8 +397,8 @@ void dbArrayTable::copy_page(uint page_id, dbArrayTablePage* page) for (; t < e; t++, o++) { if (t->_oid & DB_ALLOC_BIT) { - o->_oid = t->_oid; new (o) T(_db, *t); + o->_oid = t->_oid; } else { *((_dbFreeObject*) o) = *((_dbFreeObject*) t); } diff --git a/src/odb/src/db/dbTable.hpp b/src/odb/src/db/dbTable.hpp index a9073a04139..2800fb5d1af 100644 --- a/src/odb/src/db/dbTable.hpp +++ b/src/odb/src/db/dbTable.hpp @@ -249,9 +249,10 @@ T* dbTable::create() } _dbFreeObject* o = popQ(_free_list); + const uint oid = o->_oid; new (o) T(_db); - o->_oid |= DB_ALLOC_BIT; T* t = (T*) o; + t->_oid = oid | DB_ALLOC_BIT; dbTablePage* page = (dbTablePage*) t->getObjectPage(); page->_alloccnt++; @@ -279,9 +280,10 @@ T* dbTable::duplicate(T* c) } _dbFreeObject* o = popQ(_free_list); - o->_oid |= DB_ALLOC_BIT; + uint oid = o->_oid; new (o) T(_db, *c); T* t = (T*) o; + t->_oid = oid | DB_ALLOC_BIT; dbTablePage* page = (dbTablePage*) t->getObjectPage(); page->_alloccnt++; @@ -422,8 +424,9 @@ void dbTable::destroy(T* t) _dbFreeObject* o = (_dbFreeObject*) t; page->_alloccnt--; + const uint oid = t->_oid; t->~T(); // call destructor - o->_oid &= ~DB_ALLOC_BIT; + o->_oid = oid & ~DB_ALLOC_BIT; uint offset = t - (T*) page->_objects; uint id = page->_page_addr + offset; @@ -613,8 +616,8 @@ void dbTable::copy_page(uint page_id, dbTablePage* page) for (; t < e; t++, o++) { if (t->_oid & DB_ALLOC_BIT) { - o->_oid = t->_oid; new (o) T(_db, *t); + o->_oid = t->_oid; } else { *((_dbFreeObject*) o) = *((_dbFreeObject*) t); } diff --git a/src/rmp/src/CMakeLists.txt b/src/rmp/src/CMakeLists.txt index 67681919752..fec6f3d3b36 100644 --- a/src/rmp/src/CMakeLists.txt +++ b/src/rmp/src/CMakeLists.txt @@ -90,6 +90,7 @@ target_link_libraries(rmp_abc_library dbSta_lib libabc utl_lib + ${ABC_LIBRARY} ) if (Python3_FOUND AND BUILD_PYTHON) diff --git a/src/rsz/src/RepairDesign.cc b/src/rsz/src/RepairDesign.cc index 67f88d33023..32ea02dd422 100644 --- a/src/rsz/src/RepairDesign.cc +++ b/src/rsz/src/RepairDesign.cc @@ -851,7 +851,8 @@ void RepairDesign::repairNetWire( level, units_->distanceUnit()->asString(dbuToMeters(wire_length), 1), units_->distanceUnit()->asString(dbuToMeters(max_length_), 1)); - split_length = min(split_length, max(max_length_ - wire_length_ref, 0)); + split_length = min(max_length_, length / 2); + split_wire = true; } if (wire_cap > 0.0 && load_cap > max_cap_) { diff --git a/src/rsz/test/buffer_varying_lengths.defok b/src/rsz/test/buffer_varying_lengths.defok index f201e240fbf..ae302e8bbb3 100644 --- a/src/rsz/test/buffer_varying_lengths.defok +++ b/src/rsz/test/buffer_varying_lengths.defok @@ -3,7 +3,7 @@ DIVIDERCHAR "|" ; BUSBITCHARS "[]" ; DESIGN top ; UNITS DISTANCE MICRONS 2000 ; -COMPONENTS 558 ; +COMPONENTS 562 ; - i1-1 BUF_X1 + PLACED ( 0 20000 ) N ; - i1-10 BUF_X1 + PLACED ( 0 200000 ) N ; - i1-100 BUF_X8 + PLACED ( 0 2000000 ) N ; @@ -73,20 +73,20 @@ COMPONENTS 558 ; - i1-159 BUF_X8 + PLACED ( 0 3180000 ) N ; - i1-16 BUF_X1 + PLACED ( 0 320000 ) N ; - i1-160 BUF_X8 + PLACED ( 0 3200000 ) N ; - - i1-161 BUF_X4 + PLACED ( 0 3220000 ) N ; - - i1-162 BUF_X4 + PLACED ( 0 3240000 ) N ; - - i1-163 BUF_X4 + PLACED ( 0 3260000 ) N ; - - i1-164 BUF_X4 + PLACED ( 0 3280000 ) N ; - - i1-165 BUF_X4 + PLACED ( 0 3300000 ) N ; - - i1-166 BUF_X4 + PLACED ( 0 3320000 ) N ; - - i1-167 BUF_X4 + PLACED ( 0 3340000 ) N ; - - i1-168 BUF_X4 + PLACED ( 0 3360000 ) N ; - - i1-169 BUF_X4 + PLACED ( 0 3380000 ) N ; + - i1-161 BUF_X8 + PLACED ( 0 3220000 ) N ; + - i1-162 BUF_X8 + PLACED ( 0 3240000 ) N ; + - i1-163 BUF_X8 + PLACED ( 0 3260000 ) N ; + - i1-164 BUF_X8 + PLACED ( 0 3280000 ) N ; + - i1-165 BUF_X8 + PLACED ( 0 3300000 ) N ; + - i1-166 BUF_X8 + PLACED ( 0 3320000 ) N ; + - i1-167 BUF_X8 + PLACED ( 0 3340000 ) N ; + - i1-168 BUF_X8 + PLACED ( 0 3360000 ) N ; + - i1-169 BUF_X8 + PLACED ( 0 3380000 ) N ; - i1-17 BUF_X1 + PLACED ( 0 340000 ) N ; - - i1-170 BUF_X4 + PLACED ( 0 3400000 ) N ; - - i1-171 BUF_X4 + PLACED ( 0 3420000 ) N ; - - i1-172 BUF_X4 + PLACED ( 0 3440000 ) N ; - - i1-173 BUF_X4 + PLACED ( 0 3460000 ) N ; + - i1-170 BUF_X8 + PLACED ( 0 3400000 ) N ; + - i1-171 BUF_X8 + PLACED ( 0 3420000 ) N ; + - i1-172 BUF_X8 + PLACED ( 0 3440000 ) N ; + - i1-173 BUF_X8 + PLACED ( 0 3460000 ) N ; - i1-174 BUF_X8 + PLACED ( 0 3480000 ) N ; - i1-175 BUF_X8 + PLACED ( 0 3500000 ) N ; - i1-176 BUF_X8 + PLACED ( 0 3520000 ) N ; @@ -105,19 +105,19 @@ COMPONENTS 558 ; - i1-188 BUF_X8 + PLACED ( 0 3760000 ) N ; - i1-189 BUF_X8 + PLACED ( 0 3780000 ) N ; - i1-19 CLKBUF_X2 + PLACED ( 0 380000 ) N ; - - i1-190 BUF_X8 + PLACED ( 0 3800000 ) N ; - - i1-191 BUF_X8 + PLACED ( 0 3820000 ) N ; - - i1-192 BUF_X8 + PLACED ( 0 3840000 ) N ; - - i1-193 BUF_X8 + PLACED ( 0 3860000 ) N ; - - i1-194 BUF_X8 + PLACED ( 0 3880000 ) N ; - - i1-195 BUF_X8 + PLACED ( 0 3900000 ) N ; - - i1-196 BUF_X8 + PLACED ( 0 3920000 ) N ; - - i1-197 BUF_X8 + PLACED ( 0 3940000 ) N ; - - i1-198 BUF_X8 + PLACED ( 0 3960000 ) N ; - - i1-199 BUF_X8 + PLACED ( 0 3980000 ) N ; + - i1-190 BUF_X16 + PLACED ( 0 3800000 ) N ; + - i1-191 BUF_X16 + PLACED ( 0 3820000 ) N ; + - i1-192 BUF_X16 + PLACED ( 0 3840000 ) N ; + - i1-193 BUF_X16 + PLACED ( 0 3860000 ) N ; + - i1-194 BUF_X16 + PLACED ( 0 3880000 ) N ; + - i1-195 BUF_X16 + PLACED ( 0 3900000 ) N ; + - i1-196 BUF_X16 + PLACED ( 0 3920000 ) N ; + - i1-197 BUF_X16 + PLACED ( 0 3940000 ) N ; + - i1-198 BUF_X16 + PLACED ( 0 3960000 ) N ; + - i1-199 BUF_X16 + PLACED ( 0 3980000 ) N ; - i1-2 BUF_X1 + PLACED ( 0 40000 ) N ; - i1-20 CLKBUF_X2 + PLACED ( 0 400000 ) N ; - - i1-200 BUF_X8 + PLACED ( 0 4000000 ) N ; + - i1-200 BUF_X16 + PLACED ( 0 4000000 ) N ; - i1-21 CLKBUF_X2 + PLACED ( 0 420000 ) N ; - i1-22 CLKBUF_X2 + PLACED ( 0 440000 ) N ; - i1-23 BUF_X2 + PLACED ( 0 460000 ) N ; @@ -199,7 +199,7 @@ COMPONENTS 558 ; - i1-92 BUF_X4 + PLACED ( 0 1840000 ) N ; - i1-93 BUF_X4 + PLACED ( 0 1860000 ) N ; - i1-94 BUF_X4 + PLACED ( 0 1880000 ) N ; - - i1-95 BUF_X4 + PLACED ( 0 1900000 ) N ; + - i1-95 BUF_X8 + PLACED ( 0 1900000 ) N ; - i1-96 BUF_X8 + PLACED ( 0 1920000 ) N ; - i1-97 BUF_X8 + PLACED ( 0 1940000 ) N ; - i1-98 BUF_X8 + PLACED ( 0 1960000 ) N ; @@ -404,164 +404,168 @@ COMPONENTS 558 ; - i2-97 BUF_X1 + PLACED ( 1940000 1940000 ) N ; - i2-98 BUF_X1 + PLACED ( 1960000 1960000 ) N ; - i2-99 BUF_X1 + PLACED ( 1980000 1980000 ) N ; - - wire1 BUF_X8 + SOURCE TIMING + PLACED ( 417981 1981326 ) N ; - - wire10 BUF_X4 + SOURCE TIMING + PLACED ( 237991 1801336 ) N ; - - wire100 BUF_X8 + SOURCE TIMING + PLACED ( 1597943 3161288 ) N ; - - wire101 BUF_X8 + SOURCE TIMING + PLACED ( 1577943 3141288 ) N ; - - wire102 BUF_X8 + SOURCE TIMING + PLACED ( 1557944 3121289 ) N ; - - wire103 BUF_X8 + SOURCE TIMING + PLACED ( 1537944 3101289 ) N ; - - wire104 BUF_X8 + SOURCE TIMING + PLACED ( 1517944 3081289 ) N ; - - wire105 BUF_X8 + SOURCE TIMING + PLACED ( 1497945 3061290 ) N ; - - wire106 BUF_X8 + SOURCE TIMING + PLACED ( 1477945 3041290 ) N ; - - wire107 BUF_X8 + SOURCE TIMING + PLACED ( 1457946 3021291 ) N ; - - wire108 BUF_X8 + SOURCE TIMING + PLACED ( 1437946 3001291 ) N ; - - wire109 BUF_X8 + SOURCE TIMING + PLACED ( 1417947 2981292 ) N ; - - wire11 BUF_X4 + SOURCE TIMING + PLACED ( 217992 1781337 ) N ; - - wire110 BUF_X8 + SOURCE TIMING + PLACED ( 1397947 2961292 ) N ; - - wire111 BUF_X8 + SOURCE TIMING + PLACED ( 1377948 2941293 ) N ; - - wire112 BUF_X8 + SOURCE TIMING + PLACED ( 1357948 2921293 ) N ; - - wire113 BUF_X8 + SOURCE TIMING + PLACED ( 1337949 2901294 ) N ; - - wire114 BUF_X8 + SOURCE TIMING + PLACED ( 1317949 2881294 ) N ; - - wire115 BUF_X8 + SOURCE TIMING + PLACED ( 1297949 2861294 ) N ; - - wire116 BUF_X8 + SOURCE TIMING + PLACED ( 1277950 2841295 ) N ; - - wire117 BUF_X8 + SOURCE TIMING + PLACED ( 1257950 2821295 ) N ; - - wire118 BUF_X8 + SOURCE TIMING + PLACED ( 1237951 2801296 ) N ; - - wire119 BUF_X8 + SOURCE TIMING + PLACED ( 1217952 2781297 ) N ; - - wire12 BUF_X4 + SOURCE TIMING + PLACED ( 197993 1761338 ) N ; - - wire120 BUF_X8 + SOURCE TIMING + PLACED ( 1197952 2761297 ) N ; - - wire121 BUF_X8 + SOURCE TIMING + PLACED ( 1177953 2741298 ) N ; - - wire122 BUF_X8 + SOURCE TIMING + PLACED ( 1157953 2721298 ) N ; - - wire123 BUF_X8 + SOURCE TIMING + PLACED ( 1137954 2701299 ) N ; - - wire124 BUF_X8 + SOURCE TIMING + PLACED ( 1117954 2681299 ) N ; - - wire125 BUF_X8 + SOURCE TIMING + PLACED ( 1097955 2661300 ) N ; - - wire126 BUF_X8 + SOURCE TIMING + PLACED ( 1077955 2641300 ) N ; - - wire127 BUF_X8 + SOURCE TIMING + PLACED ( 1057956 2621301 ) N ; - - wire128 BUF_X8 + SOURCE TIMING + PLACED ( 1037957 2601302 ) N ; - - wire129 BUF_X8 + SOURCE TIMING + PLACED ( 1017957 2581302 ) N ; - - wire13 BUF_X4 + SOURCE TIMING + PLACED ( 177995 1741340 ) N ; - - wire130 BUF_X8 + SOURCE TIMING + PLACED ( 997958 2561303 ) N ; - - wire131 BUF_X8 + SOURCE TIMING + PLACED ( 977958 2541303 ) N ; - - wire132 BUF_X8 + SOURCE TIMING + PLACED ( 957959 2521304 ) N ; - - wire133 BUF_X8 + SOURCE TIMING + PLACED ( 937960 2501305 ) N ; - - wire134 BUF_X8 + SOURCE TIMING + PLACED ( 917960 2481305 ) N ; - - wire135 BUF_X8 + SOURCE TIMING + PLACED ( 897961 2461306 ) N ; - - wire136 BUF_X8 + SOURCE TIMING + PLACED ( 877962 2441307 ) N ; - - wire137 BUF_X8 + SOURCE TIMING + PLACED ( 857962 2421307 ) N ; - - wire138 BUF_X8 + SOURCE TIMING + PLACED ( 837963 2401308 ) N ; - - wire139 BUF_X8 + SOURCE TIMING + PLACED ( 817964 2381309 ) N ; - - wire14 BUF_X4 + SOURCE TIMING + PLACED ( 157996 1721341 ) N ; - - wire140 BUF_X8 + SOURCE TIMING + PLACED ( 797964 2361309 ) N ; - - wire141 BUF_X8 + SOURCE TIMING + PLACED ( 777965 2341310 ) N ; - - wire142 BUF_X8 + SOURCE TIMING + PLACED ( 757966 2321311 ) N ; - - wire143 BUF_X8 + SOURCE TIMING + PLACED ( 737967 2301312 ) N ; - - wire144 BUF_X8 + SOURCE TIMING + PLACED ( 717967 2281312 ) N ; - - wire145 BUF_X8 + SOURCE TIMING + PLACED ( 697968 2261313 ) N ; - - wire146 BUF_X8 + SOURCE TIMING + PLACED ( 677969 2241314 ) N ; - - wire147 BUF_X8 + SOURCE TIMING + PLACED ( 657970 2221315 ) N ; - - wire148 BUF_X8 + SOURCE TIMING + PLACED ( 637971 2201316 ) N ; - - wire149 BUF_X8 + SOURCE TIMING + PLACED ( 617971 2181316 ) N ; - - wire15 BUF_X4 + SOURCE TIMING + PLACED ( 137997 1701342 ) N ; - - wire150 BUF_X8 + SOURCE TIMING + PLACED ( 597972 2161317 ) N ; - - wire151 BUF_X8 + SOURCE TIMING + PLACED ( 577973 2141318 ) N ; - - wire152 BUF_X8 + SOURCE TIMING + PLACED ( 557974 2121319 ) N ; - - wire153 BUF_X8 + SOURCE TIMING + PLACED ( 537975 2101320 ) N ; - - wire154 BUF_X8 + SOURCE TIMING + PLACED ( 517976 2081321 ) N ; - - wire155 BUF_X8 + SOURCE TIMING + PLACED ( 497977 2061322 ) N ; - - wire156 BUF_X8 + SOURCE TIMING + PLACED ( 477978 2041323 ) N ; - - wire157 BUF_X8 + SOURCE TIMING + PLACED ( 457979 2021324 ) N ; - - wire158 BUF_X8 + SOURCE TIMING + PLACED ( 437980 2001325 ) N ; - - wire16 BUF_X4 + SOURCE TIMING + PLACED ( 117999 1681344 ) N ; - - wire17 BUF_X4 + SOURCE TIMING + PLACED ( 98000 1661345 ) N ; + - wire1 BUF_X8 + SOURCE TIMING + PLACED ( 1041175 1981285 ) N ; + - wire10 BUF_X4 + SOURCE TIMING + PLACED ( 945929 1801285 ) N ; + - wire100 BUF_X8 + SOURCE TIMING + PLACED ( 1671175 3181285 ) N ; + - wire101 BUF_X4 + SOURCE TIMING + PLACED ( 878911 3181317 ) N ; + - wire102 BUF_X8 + SOURCE TIMING + PLACED ( 1660675 3161285 ) N ; + - wire103 BUF_X4 + SOURCE TIMING + PLACED ( 873398 3161317 ) N ; + - wire104 BUF_X8 + SOURCE TIMING + PLACED ( 1650175 3141285 ) N ; + - wire105 BUF_X4 + SOURCE TIMING + PLACED ( 867886 3141317 ) N ; + - wire106 BUF_X8 + SOURCE TIMING + PLACED ( 1639675 3121285 ) N ; + - wire107 BUF_X8 + SOURCE TIMING + PLACED ( 1629175 3101285 ) N ; + - wire108 BUF_X8 + SOURCE TIMING + PLACED ( 1618675 3081285 ) N ; + - wire109 BUF_X8 + SOURCE TIMING + PLACED ( 1608175 3061285 ) N ; + - wire11 BUF_X4 + SOURCE TIMING + PLACED ( 935429 1781285 ) N ; + - wire110 BUF_X8 + SOURCE TIMING + PLACED ( 1597675 3041285 ) N ; + - wire111 BUF_X8 + SOURCE TIMING + PLACED ( 1587175 3021285 ) N ; + - wire112 BUF_X8 + SOURCE TIMING + PLACED ( 1576675 3001285 ) N ; + - wire113 BUF_X8 + SOURCE TIMING + PLACED ( 1566175 2981285 ) N ; + - wire114 BUF_X8 + SOURCE TIMING + PLACED ( 1555675 2961285 ) N ; + - wire115 BUF_X8 + SOURCE TIMING + PLACED ( 1545175 2941285 ) N ; + - wire116 BUF_X8 + SOURCE TIMING + PLACED ( 1534675 2921285 ) N ; + - wire117 BUF_X8 + SOURCE TIMING + PLACED ( 1524175 2901285 ) N ; + - wire118 BUF_X8 + SOURCE TIMING + PLACED ( 1513675 2881285 ) N ; + - wire119 BUF_X8 + SOURCE TIMING + PLACED ( 1503175 2861285 ) N ; + - wire12 BUF_X4 + SOURCE TIMING + PLACED ( 924929 1761285 ) N ; + - wire120 BUF_X8 + SOURCE TIMING + PLACED ( 1492675 2841285 ) N ; + - wire121 BUF_X8 + SOURCE TIMING + PLACED ( 1482175 2821285 ) N ; + - wire122 BUF_X8 + SOURCE TIMING + PLACED ( 1471675 2801285 ) N ; + - wire123 BUF_X8 + SOURCE TIMING + PLACED ( 1461175 2781285 ) N ; + - wire124 BUF_X8 + SOURCE TIMING + PLACED ( 1450675 2761285 ) N ; + - wire125 BUF_X8 + SOURCE TIMING + PLACED ( 1440175 2741285 ) N ; + - wire126 BUF_X8 + SOURCE TIMING + PLACED ( 1429675 2721285 ) N ; + - wire127 BUF_X8 + SOURCE TIMING + PLACED ( 1419175 2701285 ) N ; + - wire128 BUF_X8 + SOURCE TIMING + PLACED ( 1408675 2681285 ) N ; + - wire129 BUF_X8 + SOURCE TIMING + PLACED ( 1398175 2661285 ) N ; + - wire13 BUF_X4 + SOURCE TIMING + PLACED ( 914429 1741285 ) N ; + - wire130 BUF_X8 + SOURCE TIMING + PLACED ( 1387675 2641285 ) N ; + - wire131 BUF_X8 + SOURCE TIMING + PLACED ( 1377175 2621285 ) N ; + - wire132 BUF_X8 + SOURCE TIMING + PLACED ( 1366675 2601285 ) N ; + - wire133 BUF_X8 + SOURCE TIMING + PLACED ( 1356175 2581285 ) N ; + - wire134 BUF_X8 + SOURCE TIMING + PLACED ( 1345675 2561285 ) N ; + - wire135 BUF_X8 + SOURCE TIMING + PLACED ( 1335175 2541285 ) N ; + - wire136 BUF_X8 + SOURCE TIMING + PLACED ( 1324675 2521285 ) N ; + - wire137 BUF_X8 + SOURCE TIMING + PLACED ( 1314175 2501285 ) N ; + - wire138 BUF_X8 + SOURCE TIMING + PLACED ( 1303675 2481285 ) N ; + - wire139 BUF_X8 + SOURCE TIMING + PLACED ( 1293175 2461285 ) N ; + - wire14 BUF_X4 + SOURCE TIMING + PLACED ( 903929 1721285 ) N ; + - wire140 BUF_X8 + SOURCE TIMING + PLACED ( 1282675 2441285 ) N ; + - wire141 BUF_X8 + SOURCE TIMING + PLACED ( 1272175 2421285 ) N ; + - wire142 BUF_X8 + SOURCE TIMING + PLACED ( 1261675 2401285 ) N ; + - wire143 BUF_X8 + SOURCE TIMING + PLACED ( 1251175 2381285 ) N ; + - wire144 BUF_X8 + SOURCE TIMING + PLACED ( 1240675 2361285 ) N ; + - wire145 BUF_X8 + SOURCE TIMING + PLACED ( 1230175 2341285 ) N ; + - wire146 BUF_X8 + SOURCE TIMING + PLACED ( 1219675 2321285 ) N ; + - wire147 BUF_X8 + SOURCE TIMING + PLACED ( 1209175 2301285 ) N ; + - wire148 BUF_X8 + SOURCE TIMING + PLACED ( 1198675 2281285 ) N ; + - wire149 BUF_X8 + SOURCE TIMING + PLACED ( 1188175 2261285 ) N ; + - wire15 BUF_X4 + SOURCE TIMING + PLACED ( 893429 1701285 ) N ; + - wire150 BUF_X8 + SOURCE TIMING + PLACED ( 1177675 2241285 ) N ; + - wire151 BUF_X8 + SOURCE TIMING + PLACED ( 1167175 2221285 ) N ; + - wire152 BUF_X8 + SOURCE TIMING + PLACED ( 1156675 2201285 ) N ; + - wire153 BUF_X8 + SOURCE TIMING + PLACED ( 1146175 2181285 ) N ; + - wire154 BUF_X8 + SOURCE TIMING + PLACED ( 1135675 2161285 ) N ; + - wire155 BUF_X8 + SOURCE TIMING + PLACED ( 1125175 2141285 ) N ; + - wire156 BUF_X8 + SOURCE TIMING + PLACED ( 1114675 2121285 ) N ; + - wire157 BUF_X8 + SOURCE TIMING + PLACED ( 1104175 2101285 ) N ; + - wire158 BUF_X8 + SOURCE TIMING + PLACED ( 1093675 2081285 ) N ; + - wire159 BUF_X8 + SOURCE TIMING + PLACED ( 1083175 2061285 ) N ; + - wire16 BUF_X4 + SOURCE TIMING + PLACED ( 882929 1681285 ) N ; + - wire160 BUF_X8 + SOURCE TIMING + PLACED ( 1072675 2041285 ) N ; + - wire161 BUF_X8 + SOURCE TIMING + PLACED ( 1062175 2021285 ) N ; + - wire162 BUF_X8 + SOURCE TIMING + PLACED ( 1051675 2001285 ) N ; + - wire17 BUF_X4 + SOURCE TIMING + PLACED ( 872429 1661285 ) N ; - wire18 BUF_X16 + SOURCE TIMING + PLACED ( 2437968 4001136 ) N ; - - wire19 BUF_X8 + SOURCE TIMING + PLACED ( 875686 4001048 ) N ; - - wire2 BUF_X8 + SOURCE TIMING + PLACED ( 397982 1961327 ) N ; + - wire19 BUF_X8 + SOURCE TIMING + PLACED ( 1282994 4001071 ) N ; + - wire2 BUF_X8 + SOURCE TIMING + PLACED ( 1030675 1961285 ) N ; - wire20 BUF_X16 + SOURCE TIMING + PLACED ( 2417968 3981136 ) N ; - - wire21 BUF_X8 + SOURCE TIMING + PLACED ( 855686 3981047 ) N ; + - wire21 BUF_X8 + SOURCE TIMING + PLACED ( 1272494 3981071 ) N ; - wire22 BUF_X16 + SOURCE TIMING + PLACED ( 2397968 3961136 ) N ; - - wire23 BUF_X8 + SOURCE TIMING + PLACED ( 835687 3961047 ) N ; + - wire23 BUF_X8 + SOURCE TIMING + PLACED ( 1261994 3961071 ) N ; - wire24 BUF_X16 + SOURCE TIMING + PLACED ( 2377969 3941135 ) N ; - - wire25 BUF_X8 + SOURCE TIMING + PLACED ( 815688 3941046 ) N ; + - wire25 BUF_X8 + SOURCE TIMING + PLACED ( 1251495 3941070 ) N ; - wire26 BUF_X16 + SOURCE TIMING + PLACED ( 2357969 3921135 ) N ; - - wire27 BUF_X8 + SOURCE TIMING + PLACED ( 795689 3921045 ) N ; + - wire27 BUF_X8 + SOURCE TIMING + PLACED ( 1240995 3921070 ) N ; - wire28 BUF_X16 + SOURCE TIMING + PLACED ( 2337970 3901134 ) N ; - - wire29 BUF_X8 + SOURCE TIMING + PLACED ( 775690 3901044 ) N ; - - wire3 BUF_X8 + SOURCE TIMING + PLACED ( 377983 1941328 ) N ; + - wire29 BUF_X8 + SOURCE TIMING + PLACED ( 1230495 3901070 ) N ; + - wire3 BUF_X8 + SOURCE TIMING + PLACED ( 1020175 1941285 ) N ; - wire30 BUF_X16 + SOURCE TIMING + PLACED ( 2317970 3881134 ) N ; - - wire31 BUF_X8 + SOURCE TIMING + PLACED ( 755691 3881043 ) N ; + - wire31 BUF_X8 + SOURCE TIMING + PLACED ( 1219995 3881070 ) N ; - wire32 BUF_X16 + SOURCE TIMING + PLACED ( 2297971 3861133 ) N ; - - wire33 BUF_X8 + SOURCE TIMING + PLACED ( 735692 3861042 ) N ; + - wire33 BUF_X8 + SOURCE TIMING + PLACED ( 1209496 3861069 ) N ; - wire34 BUF_X16 + SOURCE TIMING + PLACED ( 2277971 3841133 ) N ; - - wire35 BUF_X8 + SOURCE TIMING + PLACED ( 715693 3841041 ) N ; + - wire35 BUF_X8 + SOURCE TIMING + PLACED ( 1198996 3841069 ) N ; - wire36 BUF_X16 + SOURCE TIMING + PLACED ( 2257972 3821132 ) N ; - - wire37 BUF_X8 + SOURCE TIMING + PLACED ( 695694 3821040 ) N ; + - wire37 BUF_X8 + SOURCE TIMING + PLACED ( 1188496 3821069 ) N ; - wire38 BUF_X8 + SOURCE TIMING + PLACED ( 2237972 3801132 ) N ; - - wire39 BUF_X8 + SOURCE TIMING + PLACED ( 675695 3801039 ) N ; - - wire4 BUF_X8 + SOURCE TIMING + PLACED ( 357984 1921329 ) N ; + - wire39 BUF_X8 + SOURCE TIMING + PLACED ( 1177996 3801069 ) N ; + - wire4 BUF_X8 + SOURCE TIMING + PLACED ( 1009675 1921285 ) N ; - wire40 BUF_X8 + SOURCE TIMING + PLACED ( 2217932 3781277 ) N ; - - wire41 BUF_X8 + SOURCE TIMING + PLACED ( 655615 3781330 ) N ; + - wire41 BUF_X8 + SOURCE TIMING + PLACED ( 1165958 3781313 ) N ; - wire42 BUF_X8 + SOURCE TIMING + PLACED ( 2197933 3761278 ) N ; - - wire43 BUF_X8 + SOURCE TIMING + PLACED ( 635616 3761331 ) N ; + - wire43 BUF_X8 + SOURCE TIMING + PLACED ( 1155459 3761313 ) N ; - wire44 BUF_X8 + SOURCE TIMING + PLACED ( 2177933 3741278 ) N ; - - wire45 BUF_X8 + SOURCE TIMING + PLACED ( 615616 3741331 ) N ; + - wire45 BUF_X8 + SOURCE TIMING + PLACED ( 1144959 3741313 ) N ; - wire46 BUF_X8 + SOURCE TIMING + PLACED ( 2157933 3721278 ) N ; - - wire47 BUF_X8 + SOURCE TIMING + PLACED ( 595617 3721332 ) N ; + - wire47 BUF_X8 + SOURCE TIMING + PLACED ( 1134459 3721313 ) N ; - wire48 BUF_X8 + SOURCE TIMING + PLACED ( 2137934 3701279 ) N ; - - wire49 BUF_X8 + SOURCE TIMING + PLACED ( 575618 3701333 ) N ; - - wire5 BUF_X8 + SOURCE TIMING + PLACED ( 337985 1901330 ) N ; + - wire49 BUF_X8 + SOURCE TIMING + PLACED ( 1123960 3701314 ) N ; + - wire5 BUF_X8 + SOURCE TIMING + PLACED ( 999175 1901285 ) N ; - wire50 BUF_X8 + SOURCE TIMING + PLACED ( 2117934 3681279 ) N ; - - wire51 BUF_X8 + SOURCE TIMING + PLACED ( 555618 3681333 ) N ; + - wire51 BUF_X8 + SOURCE TIMING + PLACED ( 1113460 3681314 ) N ; - wire52 BUF_X8 + SOURCE TIMING + PLACED ( 2097934 3661279 ) N ; - - wire53 BUF_X8 + SOURCE TIMING + PLACED ( 535619 3661334 ) N ; + - wire53 BUF_X8 + SOURCE TIMING + PLACED ( 1102960 3661314 ) N ; - wire54 BUF_X8 + SOURCE TIMING + PLACED ( 2077934 3641279 ) N ; - - wire55 BUF_X8 + SOURCE TIMING + PLACED ( 515619 3641334 ) N ; + - wire55 BUF_X8 + SOURCE TIMING + PLACED ( 1092460 3641314 ) N ; - wire56 BUF_X8 + SOURCE TIMING + PLACED ( 2057935 3621280 ) N ; - - wire57 BUF_X8 + SOURCE TIMING + PLACED ( 495620 3621335 ) N ; + - wire57 BUF_X8 + SOURCE TIMING + PLACED ( 1081960 3621314 ) N ; - wire58 BUF_X8 + SOURCE TIMING + PLACED ( 2037935 3601280 ) N ; - - wire59 BUF_X8 + SOURCE TIMING + PLACED ( 475621 3601336 ) N ; - - wire6 BUF_X4 + SOURCE TIMING + PLACED ( 317986 1881331 ) N ; + - wire59 BUF_X8 + SOURCE TIMING + PLACED ( 1071460 3601314 ) N ; + - wire6 BUF_X4 + SOURCE TIMING + PLACED ( 987929 1881285 ) N ; - wire60 BUF_X8 + SOURCE TIMING + PLACED ( 2017935 3581280 ) N ; - - wire61 BUF_X8 + SOURCE TIMING + PLACED ( 455621 3581336 ) N ; + - wire61 BUF_X8 + SOURCE TIMING + PLACED ( 1060960 3581314 ) N ; - wire62 BUF_X8 + SOURCE TIMING + PLACED ( 1997936 3561281 ) N ; - - wire63 BUF_X8 + SOURCE TIMING + PLACED ( 435622 3561337 ) N ; + - wire63 BUF_X8 + SOURCE TIMING + PLACED ( 1050461 3561315 ) N ; - wire64 BUF_X8 + SOURCE TIMING + PLACED ( 1977936 3541281 ) N ; - - wire65 BUF_X8 + SOURCE TIMING + PLACED ( 415622 3541337 ) N ; + - wire65 BUF_X8 + SOURCE TIMING + PLACED ( 1039961 3541315 ) N ; - wire66 BUF_X8 + SOURCE TIMING + PLACED ( 1957936 3521281 ) N ; - - wire67 BUF_X8 + SOURCE TIMING + PLACED ( 395623 3521338 ) N ; + - wire67 BUF_X8 + SOURCE TIMING + PLACED ( 1029461 3521315 ) N ; - wire68 BUF_X8 + SOURCE TIMING + PLACED ( 1937937 3501282 ) N ; - - wire69 BUF_X8 + SOURCE TIMING + PLACED ( 375624 3501339 ) N ; - - wire7 BUF_X4 + SOURCE TIMING + PLACED ( 297987 1861332 ) N ; + - wire69 BUF_X8 + SOURCE TIMING + PLACED ( 1018961 3501315 ) N ; + - wire7 BUF_X4 + SOURCE TIMING + PLACED ( 977429 1861285 ) N ; - wire70 BUF_X8 + SOURCE TIMING + PLACED ( 1917937 3481282 ) N ; - - wire71 BUF_X8 + SOURCE TIMING + PLACED ( 355624 3481339 ) N ; + - wire71 BUF_X8 + SOURCE TIMING + PLACED ( 1008461 3481315 ) N ; - wire72 BUF_X8 + SOURCE TIMING + PLACED ( 1897937 3461282 ) N ; - - wire73 BUF_X8 + SOURCE TIMING + PLACED ( 335625 3461340 ) N ; + - wire73 BUF_X8 + SOURCE TIMING + PLACED ( 997961 3461315 ) N ; - wire74 BUF_X8 + SOURCE TIMING + PLACED ( 1877938 3441283 ) N ; - - wire75 BUF_X8 + SOURCE TIMING + PLACED ( 315626 3441341 ) N ; + - wire75 BUF_X8 + SOURCE TIMING + PLACED ( 987462 3441316 ) N ; - wire76 BUF_X8 + SOURCE TIMING + PLACED ( 1857938 3421283 ) N ; - - wire77 BUF_X8 + SOURCE TIMING + PLACED ( 295626 3421341 ) N ; + - wire77 BUF_X8 + SOURCE TIMING + PLACED ( 976962 3421316 ) N ; - wire78 BUF_X8 + SOURCE TIMING + PLACED ( 1837938 3401283 ) N ; - - wire79 BUF_X8 + SOURCE TIMING + PLACED ( 275627 3401342 ) N ; - - wire8 BUF_X4 + SOURCE TIMING + PLACED ( 277988 1841333 ) N ; + - wire79 BUF_X8 + SOURCE TIMING + PLACED ( 966462 3401316 ) N ; + - wire8 BUF_X4 + SOURCE TIMING + PLACED ( 966929 1841285 ) N ; - wire80 BUF_X8 + SOURCE TIMING + PLACED ( 1817939 3381284 ) N ; - - wire81 BUF_X8 + SOURCE TIMING + PLACED ( 255628 3381343 ) N ; + - wire81 BUF_X8 + SOURCE TIMING + PLACED ( 955962 3381316 ) N ; - wire82 BUF_X8 + SOURCE TIMING + PLACED ( 1797939 3361284 ) N ; - - wire83 BUF_X8 + SOURCE TIMING + PLACED ( 235629 3361344 ) N ; + - wire83 BUF_X8 + SOURCE TIMING + PLACED ( 945462 3361316 ) N ; - wire84 BUF_X8 + SOURCE TIMING + PLACED ( 1777939 3341284 ) N ; - - wire85 BUF_X8 + SOURCE TIMING + PLACED ( 215629 3341344 ) N ; + - wire85 BUF_X8 + SOURCE TIMING + PLACED ( 934962 3341316 ) N ; - wire86 BUF_X8 + SOURCE TIMING + PLACED ( 1757940 3321285 ) N ; - - wire87 BUF_X8 + SOURCE TIMING + PLACED ( 195630 3321345 ) N ; + - wire87 BUF_X8 + SOURCE TIMING + PLACED ( 924463 3321317 ) N ; - wire88 BUF_X8 + SOURCE TIMING + PLACED ( 1737940 3301285 ) N ; - - wire89 BUF_X8 + SOURCE TIMING + PLACED ( 175631 3301346 ) N ; - - wire9 BUF_X4 + SOURCE TIMING + PLACED ( 257989 1821334 ) N ; - - wire90 BUF_X8 + SOURCE TIMING + PLACED ( 1717941 3281286 ) N ; - - wire91 BUF_X8 + SOURCE TIMING + PLACED ( 155632 3281347 ) N ; - - wire92 BUF_X8 + SOURCE TIMING + PLACED ( 1697941 3261286 ) N ; - - wire93 BUF_X8 + SOURCE TIMING + PLACED ( 135632 3261347 ) N ; - - wire94 BUF_X8 + SOURCE TIMING + PLACED ( 1677941 3241286 ) N ; - - wire95 BUF_X4 + SOURCE TIMING + PLACED ( 115633 3241348 ) N ; - - wire96 BUF_X8 + SOURCE TIMING + PLACED ( 1657942 3221287 ) N ; - - wire97 BUF_X4 + SOURCE TIMING + PLACED ( 95634 3221349 ) N ; - - wire98 BUF_X8 + SOURCE TIMING + PLACED ( 1637942 3201287 ) N ; - - wire99 BUF_X8 + SOURCE TIMING + PLACED ( 1617942 3181287 ) N ; + - wire89 BUF_X8 + SOURCE TIMING + PLACED ( 913963 3301317 ) N ; + - wire9 BUF_X4 + SOURCE TIMING + PLACED ( 956429 1821285 ) N ; + - wire90 BUF_X8 + SOURCE TIMING + PLACED ( 1723675 3281285 ) N ; + - wire91 BUF_X8 + SOURCE TIMING + PLACED ( 906473 3281317 ) N ; + - wire92 BUF_X8 + SOURCE TIMING + PLACED ( 1713175 3261285 ) N ; + - wire93 BUF_X8 + SOURCE TIMING + PLACED ( 900961 3261317 ) N ; + - wire94 BUF_X8 + SOURCE TIMING + PLACED ( 1702675 3241285 ) N ; + - wire95 BUF_X8 + SOURCE TIMING + PLACED ( 895448 3241317 ) N ; + - wire96 BUF_X8 + SOURCE TIMING + PLACED ( 1692175 3221285 ) N ; + - wire97 BUF_X8 + SOURCE TIMING + PLACED ( 889936 3221317 ) N ; + - wire98 BUF_X8 + SOURCE TIMING + PLACED ( 1681675 3201285 ) N ; + - wire99 BUF_X4 + SOURCE TIMING + PLACED ( 884423 3201317 ) N ; END COMPONENTS PINS 400 ; - p1-1 + NET n1-1 + DIRECTION INPUT + USE SIGNAL @@ -2165,7 +2169,7 @@ PINS 400 ; + LAYER metal1 ( -50 -50 ) ( 50 50 ) + PLACED ( 1980050 1980050 ) N ; END PINS -NETS 758 ; +NETS 762 ; - n1-1 ( PIN p1-1 ) ( i1-1 A ) + USE SIGNAL ; - n1-10 ( PIN p1-10 ) ( i1-10 A ) + USE SIGNAL ; - n1-100 ( PIN p1-100 ) ( i1-100 A ) + USE SIGNAL ; @@ -2368,73 +2372,73 @@ NETS 758 ; - n1-99 ( PIN p1-99 ) ( i1-99 A ) + USE SIGNAL ; - n2-1 ( i2-1 A ) ( i1-1 Z ) + USE SIGNAL ; - n2-10 ( i2-10 A ) ( i1-10 Z ) + USE SIGNAL ; - - n2-100 ( wire158 A ) ( i1-100 Z ) + USE SIGNAL ; - - n2-101 ( wire157 A ) ( i1-101 Z ) + USE SIGNAL ; - - n2-102 ( wire156 A ) ( i1-102 Z ) + USE SIGNAL ; - - n2-103 ( wire155 A ) ( i1-103 Z ) + USE SIGNAL ; - - n2-104 ( wire154 A ) ( i1-104 Z ) + USE SIGNAL ; - - n2-105 ( wire153 A ) ( i1-105 Z ) + USE SIGNAL ; - - n2-106 ( wire152 A ) ( i1-106 Z ) + USE SIGNAL ; - - n2-107 ( wire151 A ) ( i1-107 Z ) + USE SIGNAL ; - - n2-108 ( wire150 A ) ( i1-108 Z ) + USE SIGNAL ; - - n2-109 ( wire149 A ) ( i1-109 Z ) + USE SIGNAL ; + - n2-100 ( wire162 A ) ( i1-100 Z ) + USE SIGNAL ; + - n2-101 ( wire161 A ) ( i1-101 Z ) + USE SIGNAL ; + - n2-102 ( wire160 A ) ( i1-102 Z ) + USE SIGNAL ; + - n2-103 ( wire159 A ) ( i1-103 Z ) + USE SIGNAL ; + - n2-104 ( wire158 A ) ( i1-104 Z ) + USE SIGNAL ; + - n2-105 ( wire157 A ) ( i1-105 Z ) + USE SIGNAL ; + - n2-106 ( wire156 A ) ( i1-106 Z ) + USE SIGNAL ; + - n2-107 ( wire155 A ) ( i1-107 Z ) + USE SIGNAL ; + - n2-108 ( wire154 A ) ( i1-108 Z ) + USE SIGNAL ; + - n2-109 ( wire153 A ) ( i1-109 Z ) + USE SIGNAL ; - n2-11 ( i2-11 A ) ( i1-11 Z ) + USE SIGNAL ; - - n2-110 ( wire148 A ) ( i1-110 Z ) + USE SIGNAL ; - - n2-111 ( wire147 A ) ( i1-111 Z ) + USE SIGNAL ; - - n2-112 ( wire146 A ) ( i1-112 Z ) + USE SIGNAL ; - - n2-113 ( wire145 A ) ( i1-113 Z ) + USE SIGNAL ; - - n2-114 ( wire144 A ) ( i1-114 Z ) + USE SIGNAL ; - - n2-115 ( wire143 A ) ( i1-115 Z ) + USE SIGNAL ; - - n2-116 ( wire142 A ) ( i1-116 Z ) + USE SIGNAL ; - - n2-117 ( wire141 A ) ( i1-117 Z ) + USE SIGNAL ; - - n2-118 ( wire140 A ) ( i1-118 Z ) + USE SIGNAL ; - - n2-119 ( wire139 A ) ( i1-119 Z ) + USE SIGNAL ; + - n2-110 ( wire152 A ) ( i1-110 Z ) + USE SIGNAL ; + - n2-111 ( wire151 A ) ( i1-111 Z ) + USE SIGNAL ; + - n2-112 ( wire150 A ) ( i1-112 Z ) + USE SIGNAL ; + - n2-113 ( wire149 A ) ( i1-113 Z ) + USE SIGNAL ; + - n2-114 ( wire148 A ) ( i1-114 Z ) + USE SIGNAL ; + - n2-115 ( wire147 A ) ( i1-115 Z ) + USE SIGNAL ; + - n2-116 ( wire146 A ) ( i1-116 Z ) + USE SIGNAL ; + - n2-117 ( wire145 A ) ( i1-117 Z ) + USE SIGNAL ; + - n2-118 ( wire144 A ) ( i1-118 Z ) + USE SIGNAL ; + - n2-119 ( wire143 A ) ( i1-119 Z ) + USE SIGNAL ; - n2-12 ( i2-12 A ) ( i1-12 Z ) + USE SIGNAL ; - - n2-120 ( wire138 A ) ( i1-120 Z ) + USE SIGNAL ; - - n2-121 ( wire137 A ) ( i1-121 Z ) + USE SIGNAL ; - - n2-122 ( wire136 A ) ( i1-122 Z ) + USE SIGNAL ; - - n2-123 ( wire135 A ) ( i1-123 Z ) + USE SIGNAL ; - - n2-124 ( wire134 A ) ( i1-124 Z ) + USE SIGNAL ; - - n2-125 ( wire133 A ) ( i1-125 Z ) + USE SIGNAL ; - - n2-126 ( wire132 A ) ( i1-126 Z ) + USE SIGNAL ; - - n2-127 ( wire131 A ) ( i1-127 Z ) + USE SIGNAL ; - - n2-128 ( wire130 A ) ( i1-128 Z ) + USE SIGNAL ; - - n2-129 ( wire129 A ) ( i1-129 Z ) + USE SIGNAL ; + - n2-120 ( wire142 A ) ( i1-120 Z ) + USE SIGNAL ; + - n2-121 ( wire141 A ) ( i1-121 Z ) + USE SIGNAL ; + - n2-122 ( wire140 A ) ( i1-122 Z ) + USE SIGNAL ; + - n2-123 ( wire139 A ) ( i1-123 Z ) + USE SIGNAL ; + - n2-124 ( wire138 A ) ( i1-124 Z ) + USE SIGNAL ; + - n2-125 ( wire137 A ) ( i1-125 Z ) + USE SIGNAL ; + - n2-126 ( wire136 A ) ( i1-126 Z ) + USE SIGNAL ; + - n2-127 ( wire135 A ) ( i1-127 Z ) + USE SIGNAL ; + - n2-128 ( wire134 A ) ( i1-128 Z ) + USE SIGNAL ; + - n2-129 ( wire133 A ) ( i1-129 Z ) + USE SIGNAL ; - n2-13 ( i2-13 A ) ( i1-13 Z ) + USE SIGNAL ; - - n2-130 ( wire128 A ) ( i1-130 Z ) + USE SIGNAL ; - - n2-131 ( wire127 A ) ( i1-131 Z ) + USE SIGNAL ; - - n2-132 ( wire126 A ) ( i1-132 Z ) + USE SIGNAL ; - - n2-133 ( wire125 A ) ( i1-133 Z ) + USE SIGNAL ; - - n2-134 ( wire124 A ) ( i1-134 Z ) + USE SIGNAL ; - - n2-135 ( wire123 A ) ( i1-135 Z ) + USE SIGNAL ; - - n2-136 ( wire122 A ) ( i1-136 Z ) + USE SIGNAL ; - - n2-137 ( wire121 A ) ( i1-137 Z ) + USE SIGNAL ; - - n2-138 ( wire120 A ) ( i1-138 Z ) + USE SIGNAL ; - - n2-139 ( wire119 A ) ( i1-139 Z ) + USE SIGNAL ; + - n2-130 ( wire132 A ) ( i1-130 Z ) + USE SIGNAL ; + - n2-131 ( wire131 A ) ( i1-131 Z ) + USE SIGNAL ; + - n2-132 ( wire130 A ) ( i1-132 Z ) + USE SIGNAL ; + - n2-133 ( wire129 A ) ( i1-133 Z ) + USE SIGNAL ; + - n2-134 ( wire128 A ) ( i1-134 Z ) + USE SIGNAL ; + - n2-135 ( wire127 A ) ( i1-135 Z ) + USE SIGNAL ; + - n2-136 ( wire126 A ) ( i1-136 Z ) + USE SIGNAL ; + - n2-137 ( wire125 A ) ( i1-137 Z ) + USE SIGNAL ; + - n2-138 ( wire124 A ) ( i1-138 Z ) + USE SIGNAL ; + - n2-139 ( wire123 A ) ( i1-139 Z ) + USE SIGNAL ; - n2-14 ( i2-14 A ) ( i1-14 Z ) + USE SIGNAL ; - - n2-140 ( wire118 A ) ( i1-140 Z ) + USE SIGNAL ; - - n2-141 ( wire117 A ) ( i1-141 Z ) + USE SIGNAL ; - - n2-142 ( wire116 A ) ( i1-142 Z ) + USE SIGNAL ; - - n2-143 ( wire115 A ) ( i1-143 Z ) + USE SIGNAL ; - - n2-144 ( wire114 A ) ( i1-144 Z ) + USE SIGNAL ; - - n2-145 ( wire113 A ) ( i1-145 Z ) + USE SIGNAL ; - - n2-146 ( wire112 A ) ( i1-146 Z ) + USE SIGNAL ; - - n2-147 ( wire111 A ) ( i1-147 Z ) + USE SIGNAL ; - - n2-148 ( wire110 A ) ( i1-148 Z ) + USE SIGNAL ; - - n2-149 ( wire109 A ) ( i1-149 Z ) + USE SIGNAL ; + - n2-140 ( wire122 A ) ( i1-140 Z ) + USE SIGNAL ; + - n2-141 ( wire121 A ) ( i1-141 Z ) + USE SIGNAL ; + - n2-142 ( wire120 A ) ( i1-142 Z ) + USE SIGNAL ; + - n2-143 ( wire119 A ) ( i1-143 Z ) + USE SIGNAL ; + - n2-144 ( wire118 A ) ( i1-144 Z ) + USE SIGNAL ; + - n2-145 ( wire117 A ) ( i1-145 Z ) + USE SIGNAL ; + - n2-146 ( wire116 A ) ( i1-146 Z ) + USE SIGNAL ; + - n2-147 ( wire115 A ) ( i1-147 Z ) + USE SIGNAL ; + - n2-148 ( wire114 A ) ( i1-148 Z ) + USE SIGNAL ; + - n2-149 ( wire113 A ) ( i1-149 Z ) + USE SIGNAL ; - n2-15 ( i2-15 A ) ( i1-15 Z ) + USE SIGNAL ; - - n2-150 ( wire108 A ) ( i1-150 Z ) + USE SIGNAL ; - - n2-151 ( wire107 A ) ( i1-151 Z ) + USE SIGNAL ; - - n2-152 ( wire106 A ) ( i1-152 Z ) + USE SIGNAL ; - - n2-153 ( wire105 A ) ( i1-153 Z ) + USE SIGNAL ; - - n2-154 ( wire104 A ) ( i1-154 Z ) + USE SIGNAL ; - - n2-155 ( wire103 A ) ( i1-155 Z ) + USE SIGNAL ; - - n2-156 ( wire102 A ) ( i1-156 Z ) + USE SIGNAL ; - - n2-157 ( wire101 A ) ( i1-157 Z ) + USE SIGNAL ; - - n2-158 ( wire100 A ) ( i1-158 Z ) + USE SIGNAL ; - - n2-159 ( wire99 A ) ( i1-159 Z ) + USE SIGNAL ; + - n2-150 ( wire112 A ) ( i1-150 Z ) + USE SIGNAL ; + - n2-151 ( wire111 A ) ( i1-151 Z ) + USE SIGNAL ; + - n2-152 ( wire110 A ) ( i1-152 Z ) + USE SIGNAL ; + - n2-153 ( wire109 A ) ( i1-153 Z ) + USE SIGNAL ; + - n2-154 ( wire108 A ) ( i1-154 Z ) + USE SIGNAL ; + - n2-155 ( wire107 A ) ( i1-155 Z ) + USE SIGNAL ; + - n2-156 ( wire106 A ) ( i1-156 Z ) + USE SIGNAL ; + - n2-157 ( wire105 A ) ( i1-157 Z ) + USE SIGNAL ; + - n2-158 ( wire103 A ) ( i1-158 Z ) + USE SIGNAL ; + - n2-159 ( wire101 A ) ( i1-159 Z ) + USE SIGNAL ; - n2-16 ( i2-16 A ) ( i1-16 Z ) + USE SIGNAL ; - - n2-160 ( wire98 A ) ( i1-160 Z ) + USE SIGNAL ; + - n2-160 ( wire99 A ) ( i1-160 Z ) + USE SIGNAL ; - n2-161 ( wire97 A ) ( i1-161 Z ) + USE SIGNAL ; - n2-162 ( wire95 A ) ( i1-162 Z ) + USE SIGNAL ; - n2-163 ( wire93 A ) ( i1-163 Z ) + USE SIGNAL ; @@ -2768,71 +2772,75 @@ NETS 758 ; - n3-99 ( PIN p3-99 ) ( i2-99 Z ) + USE SIGNAL ; - net1 ( wire1 Z ) ( i2-99 A ) + USE SIGNAL ; - net10 ( wire10 Z ) ( i2-90 A ) + USE SIGNAL ; - - net100 ( wire100 Z ) ( i2-158 A ) + USE SIGNAL ; - - net101 ( wire101 Z ) ( i2-157 A ) + USE SIGNAL ; - - net102 ( wire102 Z ) ( i2-156 A ) + USE SIGNAL ; - - net103 ( wire103 Z ) ( i2-155 A ) + USE SIGNAL ; - - net104 ( wire104 Z ) ( i2-154 A ) + USE SIGNAL ; - - net105 ( wire105 Z ) ( i2-153 A ) + USE SIGNAL ; - - net106 ( wire106 Z ) ( i2-152 A ) + USE SIGNAL ; - - net107 ( wire107 Z ) ( i2-151 A ) + USE SIGNAL ; - - net108 ( wire108 Z ) ( i2-150 A ) + USE SIGNAL ; - - net109 ( wire109 Z ) ( i2-149 A ) + USE SIGNAL ; + - net100 ( wire100 Z ) ( i2-159 A ) + USE SIGNAL ; + - net101 ( wire101 Z ) ( wire100 A ) + USE SIGNAL ; + - net102 ( wire102 Z ) ( i2-158 A ) + USE SIGNAL ; + - net103 ( wire103 Z ) ( wire102 A ) + USE SIGNAL ; + - net104 ( wire104 Z ) ( i2-157 A ) + USE SIGNAL ; + - net105 ( wire105 Z ) ( wire104 A ) + USE SIGNAL ; + - net106 ( wire106 Z ) ( i2-156 A ) + USE SIGNAL ; + - net107 ( wire107 Z ) ( i2-155 A ) + USE SIGNAL ; + - net108 ( wire108 Z ) ( i2-154 A ) + USE SIGNAL ; + - net109 ( wire109 Z ) ( i2-153 A ) + USE SIGNAL ; - net11 ( wire11 Z ) ( i2-89 A ) + USE SIGNAL ; - - net110 ( wire110 Z ) ( i2-148 A ) + USE SIGNAL ; - - net111 ( wire111 Z ) ( i2-147 A ) + USE SIGNAL ; - - net112 ( wire112 Z ) ( i2-146 A ) + USE SIGNAL ; - - net113 ( wire113 Z ) ( i2-145 A ) + USE SIGNAL ; - - net114 ( wire114 Z ) ( i2-144 A ) + USE SIGNAL ; - - net115 ( wire115 Z ) ( i2-143 A ) + USE SIGNAL ; - - net116 ( wire116 Z ) ( i2-142 A ) + USE SIGNAL ; - - net117 ( wire117 Z ) ( i2-141 A ) + USE SIGNAL ; - - net118 ( wire118 Z ) ( i2-140 A ) + USE SIGNAL ; - - net119 ( wire119 Z ) ( i2-139 A ) + USE SIGNAL ; + - net110 ( wire110 Z ) ( i2-152 A ) + USE SIGNAL ; + - net111 ( wire111 Z ) ( i2-151 A ) + USE SIGNAL ; + - net112 ( wire112 Z ) ( i2-150 A ) + USE SIGNAL ; + - net113 ( wire113 Z ) ( i2-149 A ) + USE SIGNAL ; + - net114 ( wire114 Z ) ( i2-148 A ) + USE SIGNAL ; + - net115 ( wire115 Z ) ( i2-147 A ) + USE SIGNAL ; + - net116 ( wire116 Z ) ( i2-146 A ) + USE SIGNAL ; + - net117 ( wire117 Z ) ( i2-145 A ) + USE SIGNAL ; + - net118 ( wire118 Z ) ( i2-144 A ) + USE SIGNAL ; + - net119 ( wire119 Z ) ( i2-143 A ) + USE SIGNAL ; - net12 ( wire12 Z ) ( i2-88 A ) + USE SIGNAL ; - - net120 ( wire120 Z ) ( i2-138 A ) + USE SIGNAL ; - - net121 ( wire121 Z ) ( i2-137 A ) + USE SIGNAL ; - - net122 ( wire122 Z ) ( i2-136 A ) + USE SIGNAL ; - - net123 ( wire123 Z ) ( i2-135 A ) + USE SIGNAL ; - - net124 ( wire124 Z ) ( i2-134 A ) + USE SIGNAL ; - - net125 ( wire125 Z ) ( i2-133 A ) + USE SIGNAL ; - - net126 ( wire126 Z ) ( i2-132 A ) + USE SIGNAL ; - - net127 ( wire127 Z ) ( i2-131 A ) + USE SIGNAL ; - - net128 ( wire128 Z ) ( i2-130 A ) + USE SIGNAL ; - - net129 ( wire129 Z ) ( i2-129 A ) + USE SIGNAL ; + - net120 ( wire120 Z ) ( i2-142 A ) + USE SIGNAL ; + - net121 ( wire121 Z ) ( i2-141 A ) + USE SIGNAL ; + - net122 ( wire122 Z ) ( i2-140 A ) + USE SIGNAL ; + - net123 ( wire123 Z ) ( i2-139 A ) + USE SIGNAL ; + - net124 ( wire124 Z ) ( i2-138 A ) + USE SIGNAL ; + - net125 ( wire125 Z ) ( i2-137 A ) + USE SIGNAL ; + - net126 ( wire126 Z ) ( i2-136 A ) + USE SIGNAL ; + - net127 ( wire127 Z ) ( i2-135 A ) + USE SIGNAL ; + - net128 ( wire128 Z ) ( i2-134 A ) + USE SIGNAL ; + - net129 ( wire129 Z ) ( i2-133 A ) + USE SIGNAL ; - net13 ( wire13 Z ) ( i2-87 A ) + USE SIGNAL ; - - net130 ( wire130 Z ) ( i2-128 A ) + USE SIGNAL ; - - net131 ( wire131 Z ) ( i2-127 A ) + USE SIGNAL ; - - net132 ( wire132 Z ) ( i2-126 A ) + USE SIGNAL ; - - net133 ( wire133 Z ) ( i2-125 A ) + USE SIGNAL ; - - net134 ( wire134 Z ) ( i2-124 A ) + USE SIGNAL ; - - net135 ( wire135 Z ) ( i2-123 A ) + USE SIGNAL ; - - net136 ( wire136 Z ) ( i2-122 A ) + USE SIGNAL ; - - net137 ( wire137 Z ) ( i2-121 A ) + USE SIGNAL ; - - net138 ( wire138 Z ) ( i2-120 A ) + USE SIGNAL ; - - net139 ( wire139 Z ) ( i2-119 A ) + USE SIGNAL ; + - net130 ( wire130 Z ) ( i2-132 A ) + USE SIGNAL ; + - net131 ( wire131 Z ) ( i2-131 A ) + USE SIGNAL ; + - net132 ( wire132 Z ) ( i2-130 A ) + USE SIGNAL ; + - net133 ( wire133 Z ) ( i2-129 A ) + USE SIGNAL ; + - net134 ( wire134 Z ) ( i2-128 A ) + USE SIGNAL ; + - net135 ( wire135 Z ) ( i2-127 A ) + USE SIGNAL ; + - net136 ( wire136 Z ) ( i2-126 A ) + USE SIGNAL ; + - net137 ( wire137 Z ) ( i2-125 A ) + USE SIGNAL ; + - net138 ( wire138 Z ) ( i2-124 A ) + USE SIGNAL ; + - net139 ( wire139 Z ) ( i2-123 A ) + USE SIGNAL ; - net14 ( wire14 Z ) ( i2-86 A ) + USE SIGNAL ; - - net140 ( wire140 Z ) ( i2-118 A ) + USE SIGNAL ; - - net141 ( wire141 Z ) ( i2-117 A ) + USE SIGNAL ; - - net142 ( wire142 Z ) ( i2-116 A ) + USE SIGNAL ; - - net143 ( wire143 Z ) ( i2-115 A ) + USE SIGNAL ; - - net144 ( wire144 Z ) ( i2-114 A ) + USE SIGNAL ; - - net145 ( wire145 Z ) ( i2-113 A ) + USE SIGNAL ; - - net146 ( wire146 Z ) ( i2-112 A ) + USE SIGNAL ; - - net147 ( wire147 Z ) ( i2-111 A ) + USE SIGNAL ; - - net148 ( wire148 Z ) ( i2-110 A ) + USE SIGNAL ; - - net149 ( wire149 Z ) ( i2-109 A ) + USE SIGNAL ; + - net140 ( wire140 Z ) ( i2-122 A ) + USE SIGNAL ; + - net141 ( wire141 Z ) ( i2-121 A ) + USE SIGNAL ; + - net142 ( wire142 Z ) ( i2-120 A ) + USE SIGNAL ; + - net143 ( wire143 Z ) ( i2-119 A ) + USE SIGNAL ; + - net144 ( wire144 Z ) ( i2-118 A ) + USE SIGNAL ; + - net145 ( wire145 Z ) ( i2-117 A ) + USE SIGNAL ; + - net146 ( wire146 Z ) ( i2-116 A ) + USE SIGNAL ; + - net147 ( wire147 Z ) ( i2-115 A ) + USE SIGNAL ; + - net148 ( wire148 Z ) ( i2-114 A ) + USE SIGNAL ; + - net149 ( wire149 Z ) ( i2-113 A ) + USE SIGNAL ; - net15 ( wire15 Z ) ( i2-85 A ) + USE SIGNAL ; - - net150 ( wire150 Z ) ( i2-108 A ) + USE SIGNAL ; - - net151 ( wire151 Z ) ( i2-107 A ) + USE SIGNAL ; - - net152 ( wire152 Z ) ( i2-106 A ) + USE SIGNAL ; - - net153 ( wire153 Z ) ( i2-105 A ) + USE SIGNAL ; - - net154 ( wire154 Z ) ( i2-104 A ) + USE SIGNAL ; - - net155 ( wire155 Z ) ( i2-103 A ) + USE SIGNAL ; - - net156 ( wire156 Z ) ( i2-102 A ) + USE SIGNAL ; - - net157 ( wire157 Z ) ( i2-101 A ) + USE SIGNAL ; - - net158 ( wire158 Z ) ( i2-100 A ) + USE SIGNAL ; + - net150 ( wire150 Z ) ( i2-112 A ) + USE SIGNAL ; + - net151 ( wire151 Z ) ( i2-111 A ) + USE SIGNAL ; + - net152 ( wire152 Z ) ( i2-110 A ) + USE SIGNAL ; + - net153 ( wire153 Z ) ( i2-109 A ) + USE SIGNAL ; + - net154 ( wire154 Z ) ( i2-108 A ) + USE SIGNAL ; + - net155 ( wire155 Z ) ( i2-107 A ) + USE SIGNAL ; + - net156 ( wire156 Z ) ( i2-106 A ) + USE SIGNAL ; + - net157 ( wire157 Z ) ( i2-105 A ) + USE SIGNAL ; + - net158 ( wire158 Z ) ( i2-104 A ) + USE SIGNAL ; + - net159 ( wire159 Z ) ( i2-103 A ) + USE SIGNAL ; - net16 ( wire16 Z ) ( i2-84 A ) + USE SIGNAL ; + - net160 ( wire160 Z ) ( i2-102 A ) + USE SIGNAL ; + - net161 ( wire161 Z ) ( i2-101 A ) + USE SIGNAL ; + - net162 ( wire162 Z ) ( i2-100 A ) + USE SIGNAL ; - net17 ( wire17 Z ) ( i2-83 A ) + USE SIGNAL ; - net18 ( wire18 Z ) ( i2-200 A ) + USE SIGNAL ; - net19 ( wire19 Z ) ( wire18 A ) + USE SIGNAL ; @@ -2923,6 +2931,6 @@ NETS 758 ; - net96 ( wire96 Z ) ( i2-161 A ) + USE SIGNAL ; - net97 ( wire97 Z ) ( wire96 A ) + USE SIGNAL ; - net98 ( wire98 Z ) ( i2-160 A ) + USE SIGNAL ; - - net99 ( wire99 Z ) ( i2-159 A ) + USE SIGNAL ; + - net99 ( wire99 Z ) ( wire98 A ) + USE SIGNAL ; END NETS END DESIGN diff --git a/src/rsz/test/buffer_varying_lengths.ok b/src/rsz/test/buffer_varying_lengths.ok index 1d18aacb0a3..35e75126f0b 100644 --- a/src/rsz/test/buffer_varying_lengths.ok +++ b/src/rsz/test/buffer_varying_lengths.ok @@ -1,10 +1,10 @@ [INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells [INFO RSZ-0058] Using max wire length 822um. [INFO RSZ-0037] Found 118 long wires. -[INFO RSZ-0038] Inserted 158 buffers in 118 nets. -[INFO RSZ-0039] Resized 208 instances. +[INFO RSZ-0038] Inserted 162 buffers in 118 nets. +[INFO RSZ-0039] Resized 183 instances. [INFO RSZ-0094] Found 200 endpoints with setup violations. -[INFO RSZ-0041] Resized 3 instances. +[INFO RSZ-0041] Resized 2 instances. [WARNING RSZ-0062] Unable to repair all setup violations. [INFO RSZ-0033] No hold violations found. No differences found. diff --git a/src/rsz/test/repair_clk_nets1.ok b/src/rsz/test/repair_clk_nets1.ok index 9e8d3ef8f20..714dc610cea 100644 --- a/src/rsz/test/repair_clk_nets1.ok +++ b/src/rsz/test/repair_clk_nets1.ok @@ -22,15 +22,15 @@ Path Type: max 0.01 0.00 0.02 ^ u2/A (BUF_X1) 6.59 0.02 0.03 0.05 ^ u2/Z (BUF_X1) 0.02 0.00 0.05 ^ wire3/A (BUF_X8) - 55.14 0.01 0.03 0.08 ^ wire3/Z (BUF_X8) - 0.06 0.05 0.13 ^ wire2/A (BUF_X16) - 55.02 0.01 0.03 0.16 ^ wire2/Z (BUF_X16) - 0.06 0.05 0.21 ^ wire1/A (BUF_X16) - 43.61 0.01 0.03 0.24 ^ wire1/Z (BUF_X16) - 0.04 0.03 0.27 ^ u3/A (BUF_X1) - 0.00 0.01 0.02 0.30 ^ u3/Z (BUF_X1) - 0.01 0.00 0.30 ^ out1 (out) - 0.30 data arrival time + 42.96 0.01 0.03 0.08 ^ wire3/Z (BUF_X8) + 0.04 0.03 0.11 ^ wire2/A (BUF_X16) + 55.02 0.01 0.03 0.14 ^ wire2/Z (BUF_X16) + 0.06 0.05 0.19 ^ wire1/A (BUF_X16) + 43.61 0.01 0.03 0.22 ^ wire1/Z (BUF_X16) + 0.04 0.03 0.25 ^ u3/A (BUF_X1) + 0.00 0.01 0.02 0.27 ^ u3/Z (BUF_X1) + 0.01 0.00 0.27 ^ out1 (out) + 0.27 data arrival time ----------------------------------------------------------------------- (Path is unconstrained) diff --git a/src/rsz/test/repair_setup2.ok b/src/rsz/test/repair_setup2.ok index 72c1aea5a99..c2ae41ee526 100644 --- a/src/rsz/test/repair_setup2.ok +++ b/src/rsz/test/repair_setup2.ok @@ -10,7 +10,6 @@ worst slack -0.28 [INFO RSZ-0038] Inserted 3 buffers in 3 nets. [INFO RSZ-0039] Resized 2 instances. [INFO RSZ-0094] Found 2 endpoints with setup violations. -[INFO RSZ-0041] Resized 1 instances. [WARNING RSZ-0062] Unable to repair all setup violations. Repair timing output passed/skipped equivalence test worst slack -0.12 diff --git a/src/rsz/test/repair_slew12.ok b/src/rsz/test/repair_slew12.ok index 605b69fc80c..2d803420cd9 100644 --- a/src/rsz/test/repair_slew12.ok +++ b/src/rsz/test/repair_slew12.ok @@ -7,5 +7,5 @@ [INFO RSZ-0058] Using max wire length 693um. [INFO RSZ-0034] Found 1 slew violations. [INFO RSZ-0037] Found 1 long wires. -[INFO RSZ-0038] Inserted 2 buffers in 2 nets. +[INFO RSZ-0038] Inserted 3 buffers in 2 nets. [INFO RSZ-0039] Resized 2 instances. diff --git a/src/rsz/test/repair_wire1.ok b/src/rsz/test/repair_wire1.ok index b8d9dea292a..cff2f87b08a 100644 --- a/src/rsz/test/repair_wire1.ok +++ b/src/rsz/test/repair_wire1.ok @@ -34,8 +34,8 @@ in1 manhtn 0.7 steiner 0.7 0.00 [INFO RSZ-0039] Resized 2 instances. Driver length delay wire1/Z manhtn 757.2 steiner 757.2 0.08 -wire2/Z manhtn 757.0 steiner 757.0 0.08 -u2/Z manhtn 476.8 steiner 476.8 0.03 +u2/Z manhtn 649.6 steiner 649.6 0.06 +wire2/Z manhtn 584.1 steiner 584.1 0.05 u3/Z manhtn 1.3 steiner 1.3 0.00 in1 manhtn 0.7 steiner 0.7 0.00 Startpoint: in1 (input port) @@ -50,15 +50,15 @@ Path Type: max 0.000 0.000 0.000 ^ u1/A (CLKBUF_X2) 12.443 0.017 0.035 0.035 ^ u1/Z (CLKBUF_X2) 0.017 0.000 0.035 ^ u2/A (BUF_X16) - 48.244 0.007 0.024 0.059 ^ u2/Z (BUF_X16) - 0.047 0.038 0.097 ^ wire2/A (BUF_X16) - 69.308 0.009 0.030 0.127 ^ wire2/Z (BUF_X16) - 0.097 0.080 0.207 ^ wire1/A (BUF_X16) - 57.885 0.011 0.033 0.240 ^ wire1/Z (BUF_X16) - 0.071 0.058 0.298 ^ u3/A (BUF_X1) - 0.000 0.006 0.027 0.325 ^ u3/Z (BUF_X1) - 0.006 0.000 0.325 ^ out1 (out) - 0.325 data arrival time + 61.238 0.007 0.025 0.060 ^ u2/Z (BUF_X16) + 0.076 0.062 0.122 ^ wire2/A (BUF_X16) + 56.314 0.010 0.032 0.153 ^ wire2/Z (BUF_X16) + 0.064 0.052 0.206 ^ wire1/A (BUF_X16) + 57.885 0.010 0.032 0.238 ^ wire1/Z (BUF_X16) + 0.070 0.057 0.295 ^ u3/A (BUF_X1) + 0.000 0.006 0.027 0.322 ^ u3/Z (BUF_X1) + 0.006 0.000 0.322 ^ out1 (out) + 0.322 data arrival time --------------------------------------------------------------------------- (Path is unconstrained) diff --git a/src/rsz/test/repair_wire10.ok b/src/rsz/test/repair_wire10.ok index b12bd6c16c9..632ac4ffee7 100644 --- a/src/rsz/test/repair_wire10.ok +++ b/src/rsz/test/repair_wire10.ok @@ -56,20 +56,20 @@ Path Type: max 0.00 0.00 0.00 v u1/A (BUF_X1) 11.19 0.01 0.04 0.04 v u1/Z (BUF_X1) 0.01 0.00 0.04 v u2/A (BUF_X16) - 41.87 0.01 0.03 0.06 v u2/Z (BUF_X16) - 0.04 0.03 0.09 v wire2/A (BUF_X8) - 63.11 0.01 0.04 0.14 v wire2/Z (BUF_X8) - 0.08 0.07 0.20 v wire1/A (BUF_X8) - 58.05 0.01 0.06 0.26 v wire1/Z (BUF_X8) + 52.03 0.01 0.03 0.07 v u2/Z (BUF_X16) + 0.06 0.05 0.11 v wire2/A (BUF_X4) + 50.21 0.01 0.05 0.16 v wire2/Z (BUF_X4) + 0.06 0.05 0.21 v wire1/A (BUF_X8) + 58.05 0.01 0.05 0.26 v wire1/Z (BUF_X8) 0.07 0.06 0.32 v u3/A (BUF_X1) - 0.24 0.01 0.05 0.37 v u3/Z (BUF_X1) - 0.01 0.00 0.37 v out1 (out) - 0.37 data arrival time + 0.24 0.01 0.05 0.36 v u3/Z (BUF_X1) + 0.01 0.00 0.36 v out1 (out) + 0.36 data arrival time ----------------------------------------------------------------------- (Path is unconstrained) Driver length delay -wire2/Z manhtn 758.6 steiner 758.6 0.00 wire1/Z manhtn 758.4 steiner 758.4 0.00 -u2/Z manhtn 475.6 steiner 475.6 0.00 +u2/Z manhtn 647.6 steiner 647.6 0.00 +wire2/Z manhtn 587.4 steiner 587.4 0.00 diff --git a/src/rsz/test/repair_wire11.ok b/src/rsz/test/repair_wire11.ok index c6049aa0122..8cea8df8d57 100644 --- a/src/rsz/test/repair_wire11.ok +++ b/src/rsz/test/repair_wire11.ok @@ -24,7 +24,7 @@ u1/Z 60.65 149.17 -88.52 (VIOLATED) [INFO RSZ-0034] Found 1 slew violations. [INFO RSZ-0037] Found 1 long wires. [INFO RSZ-0038] Inserted 3 buffers in 1 nets. -[INFO RSZ-0039] Resized 2 instances. +[INFO RSZ-0039] Resized 1 instances. max slew Pin Limit Slew Slack diff --git a/src/rsz/test/repair_wire2.ok b/src/rsz/test/repair_wire2.ok index 69c0496846e..1d051e0ed26 100644 --- a/src/rsz/test/repair_wire2.ok +++ b/src/rsz/test/repair_wire2.ok @@ -53,15 +53,15 @@ u4/Z manhtn 1.1 steiner 1.1 0.00 in1 manhtn 0.7 steiner 0.7 0.00 u1/Z manhtn 0.4 steiner 0.4 0.00 [INFO RSZ-0037] Found 1 long wires. -[INFO RSZ-0038] Inserted 3 buffers in 1 nets. -[INFO RSZ-0039] Resized 3 instances. +[INFO RSZ-0038] Inserted 2 buffers in 1 nets. +[INFO RSZ-0039] Resized 2 instances. Driver length delay -wire2/Z manhtn 974.5 steiner 974.5 0.13 -wire1/Z manhtn 952.7 steiner 952.7 0.12 -wire3/Z manhtn 948.4 steiner 948.4 0.12 -u2/Z manhtn 120.2 steiner 120.2 0.00 +wire2/Z manhtn 1494.2 steiner 1494.2 0.30 +u2/Z manhtn 785.1 steiner 785.1 0.08 +wire1/Z manhtn 715.2 steiner 715.2 0.07 u3/Z manhtn 1.1 steiner 1.1 0.00 u4/Z manhtn 1.1 steiner 1.1 0.00 +u1/Z manhtn 0.8 steiner 0.8 0.00 in1 manhtn 0.7 steiner 0.7 0.00 Startpoint: in1 (input port) Endpoint: out1 (output port) @@ -71,19 +71,17 @@ Path Type: max Cap Slew Delay Time Description --------------------------------------------------------------------------- 0.000 0.000 ^ input external delay - 1.456 0.000 0.000 0.000 ^ in1 (in) - 0.000 0.000 0.000 ^ u1/A (CLKBUF_X2) - 12.443 0.017 0.035 0.035 ^ u1/Z (CLKBUF_X2) - 0.017 0.000 0.035 ^ u2/A (BUF_X16) - 15.623 0.006 0.022 0.057 ^ u2/Z (BUF_X16) - 0.007 0.004 0.061 ^ wire3/A (BUF_X8) - 83.696 0.015 0.029 0.090 ^ wire3/Z (BUF_X8) - 0.147 0.120 0.210 ^ wire2/A (BUF_X16) - 86.665 0.012 0.032 0.242 ^ wire2/Z (BUF_X16) - 0.097 0.078 0.320 ^ u3/A (BUF_X1) - 0.000 0.007 0.028 0.348 ^ u3/Z (BUF_X1) - 0.007 0.000 0.348 ^ out1 (out) - 0.348 data arrival time + 3.451 0.000 0.000 0.000 ^ in1 (in) + 0.000 0.000 0.000 ^ u1/A (BUF_X4) + 26.763 0.018 0.030 0.030 ^ u1/Z (BUF_X4) + 0.018 0.000 0.030 ^ u2/A (BUF_X32) + 71.422 0.006 0.023 0.053 ^ u2/Z (BUF_X32) + 0.102 0.083 0.136 ^ wire2/A (BUF_X16) + 125.723 0.011 0.034 0.170 ^ wire2/Z (BUF_X16) + 0.220 0.179 0.349 ^ u3/A (BUF_X1) + 0.000 0.011 0.026 0.375 ^ u3/Z (BUF_X1) + 0.011 0.000 0.375 ^ out1 (out) + 0.375 data arrival time --------------------------------------------------------------------------- (Path is unconstrained) @@ -96,21 +94,19 @@ Path Type: max Cap Slew Delay Time Description --------------------------------------------------------------------------- 0.000 0.000 ^ input external delay - 1.456 0.000 0.000 0.000 ^ in1 (in) - 0.000 0.000 0.000 ^ u1/A (CLKBUF_X2) - 12.443 0.017 0.035 0.035 ^ u1/Z (CLKBUF_X2) - 0.017 0.000 0.035 ^ u2/A (BUF_X16) - 15.623 0.006 0.022 0.057 ^ u2/Z (BUF_X16) - 0.007 0.004 0.061 ^ wire3/A (BUF_X8) - 83.696 0.015 0.029 0.090 ^ wire3/Z (BUF_X8) - 0.147 0.120 0.210 ^ wire2/A (BUF_X16) - 86.665 0.012 0.032 0.242 ^ wire2/Z (BUF_X16) - 0.153 0.125 0.367 ^ wire1/A (BUF_X16) - 72.581 0.014 0.035 0.402 ^ wire1/Z (BUF_X16) - 0.110 0.090 0.491 ^ u4/A (BUF_X1) - 0.000 0.008 0.028 0.519 ^ u4/Z (BUF_X1) - 0.008 0.000 0.519 ^ out2 (out) - 0.519 data arrival time + 3.451 0.000 0.000 0.000 ^ in1 (in) + 0.000 0.000 0.000 ^ u1/A (BUF_X4) + 26.763 0.018 0.030 0.030 ^ u1/Z (BUF_X4) + 0.018 0.000 0.030 ^ u2/A (BUF_X32) + 71.422 0.006 0.023 0.053 ^ u2/Z (BUF_X32) + 0.102 0.083 0.136 ^ wire2/A (BUF_X16) + 125.723 0.011 0.034 0.170 ^ wire2/Z (BUF_X16) + 0.321 0.263 0.433 ^ wire1/A (BUF_X16) + 54.731 0.019 0.030 0.463 ^ wire1/Z (BUF_X16) + 0.065 0.053 0.516 ^ u4/A (BUF_X1) + 0.000 0.006 0.027 0.543 ^ u4/Z (BUF_X1) + 0.006 0.000 0.543 ^ out2 (out) + 0.543 data arrival time --------------------------------------------------------------------------- (Path is unconstrained) diff --git a/src/rsz/test/repair_wire4.ok b/src/rsz/test/repair_wire4.ok index 60a6d74b283..dc9a67d5d7c 100644 --- a/src/rsz/test/repair_wire4.ok +++ b/src/rsz/test/repair_wire4.ok @@ -14,10 +14,10 @@ u1/Z manhtn 0.4 steiner 0.4 0.00 [INFO RSZ-0038] Inserted 3 buffers in 1 nets. [INFO RSZ-0039] Resized 2 instances. Driver length delay -wire1/Z manhtn 858.7 steiner 858.7 0.10 -wire2/Z manhtn 857.7 steiner 857.7 0.10 -u2/Z manhtn 650.2 steiner 650.2 0.06 -max_length3/Z manhtn 648.4 steiner 648.4 0.06 +u2/Z manhtn 792.7 steiner 792.7 0.08 +max_length3/Z manhtn 790.8 steiner 790.8 0.08 +wire1/Z manhtn 716.2 steiner 716.2 0.07 +wire2/Z manhtn 715.3 steiner 715.3 0.07 u3/Z manhtn 1.1 steiner 1.1 0.00 u4/Z manhtn 1.1 steiner 1.1 0.00 u1/Z manhtn 0.8 steiner 0.8 0.00 diff --git a/src/rsz/test/repair_wire5.ok b/src/rsz/test/repair_wire5.ok index 3f571557434..f50b1d2b38d 100644 --- a/src/rsz/test/repair_wire5.ok +++ b/src/rsz/test/repair_wire5.ok @@ -21,5 +21,5 @@ u1/Z 60.65 104.42 -43.76 (VIOLATED) [INFO RSZ-0034] Found 1 slew violations. [INFO RSZ-0037] Found 1 long wires. [INFO RSZ-0038] Inserted 2 buffers in 1 nets. -[INFO RSZ-0039] Resized 2 instances. +[INFO RSZ-0039] Resized 1 instances. pad1 (809120 2000000) outside of core (0 0 1599800 1598800) diff --git a/src/rsz/test/repair_wire6.ok b/src/rsz/test/repair_wire6.ok index 252b5a38f4b..d801c34c65f 100644 --- a/src/rsz/test/repair_wire6.ok +++ b/src/rsz/test/repair_wire6.ok @@ -32,9 +32,9 @@ u1/Z manhtn 0.4 steiner 0.4 0.00 [INFO RSZ-0038] Inserted 2 buffers in 1 nets. [INFO RSZ-0039] Resized 2 instances. Driver length delay -wire2/Z manhtn 568.6 steiner 568.6 0.04 wire1/Z manhtn 567.3 steiner 567.3 0.04 -u2/Z manhtn 357.8 steiner 357.8 0.02 +u2/Z manhtn 487.3 steiner 487.3 0.03 +wire2/Z manhtn 439.0 steiner 439.0 0.03 in1 manhtn 0.7 steiner 0.7 0.00 Startpoint: in1 (input port) Endpoint: out1 (output port) @@ -48,13 +48,13 @@ Path Type: max 0.000 0.000 0.000 ^ u1/A (CLKBUF_X2) 12.443 0.017 0.035 0.035 ^ u1/Z (CLKBUF_X2) 0.017 0.000 0.035 ^ u2/A (BUF_X16) - 33.478 0.006 0.023 0.058 ^ u2/Z (BUF_X16) - 0.024 0.019 0.077 ^ wire2/A (BUF_X8) - 55.143 0.011 0.029 0.107 ^ wire2/Z (BUF_X8) - 0.065 0.052 0.159 ^ wire1/A (BUF_X16) - 42.637 0.009 0.031 0.189 ^ wire1/Z (BUF_X16) - 0.039 0.032 0.221 ^ out1 (out) - 0.221 data arrival time + 43.207 0.007 0.024 0.059 ^ u2/Z (BUF_X16) + 0.039 0.032 0.091 ^ wire2/A (BUF_X8) + 45.408 0.011 0.031 0.122 ^ wire2/Z (BUF_X8) + 0.044 0.035 0.157 ^ wire1/A (BUF_X16) + 42.637 0.008 0.029 0.186 ^ wire1/Z (BUF_X16) + 0.039 0.032 0.217 ^ out1 (out) + 0.217 data arrival time --------------------------------------------------------------------------- (Path is unconstrained) diff --git a/src/rsz/test/repair_wire7.ok b/src/rsz/test/repair_wire7.ok index 08c969fe87c..6532b3e40dc 100644 --- a/src/rsz/test/repair_wire7.ok +++ b/src/rsz/test/repair_wire7.ok @@ -34,10 +34,10 @@ u2/Z manhtn 0.4 steiner 0.4 0.00 [INFO RSZ-0037] Found 1 long wires. [INFO RSZ-0038] Inserted 3 buffers in 1 nets. Driver length delay -wire3/Z manhtn 568.4 steiner 568.4 0.04 wire2/Z manhtn 567.0 steiner 567.0 0.04 wire1/Z manhtn 566.9 steiner 566.9 0.04 -in1 manhtn 291.4 steiner 291.4 0.01 +in1 manhtn 452.6 steiner 452.6 0.03 +wire3/Z manhtn 407.3 steiner 407.3 0.02 Startpoint: in1 (input port) Endpoint: out1 (output port) Path Group: unconstrained @@ -46,21 +46,21 @@ Path Type: max Cap Slew Delay Time Description --------------------------------------------------------------------------- 0.000 0.000 ^ input external delay - 28.486 0.000 0.000 0.000 ^ in1 (in) - 0.015 0.013 0.013 ^ wire3/A (BUF_X8) - 55.135 0.011 0.028 0.040 ^ wire3/Z (BUF_X8) - 0.065 0.052 0.092 ^ wire2/A (BUF_X16) - 55.028 0.009 0.031 0.123 ^ wire2/Z (BUF_X16) - 0.061 0.050 0.173 ^ wire1/A (BUF_X16) - 43.586 0.009 0.030 0.203 ^ wire1/Z (BUF_X16) - 0.040 0.033 0.236 ^ u1/A (BUF_X1) - 1.008 0.007 0.028 0.264 ^ u1/Z (BUF_X1) - 0.007 0.000 0.264 ^ u2/A (BUF_X1) - 1.008 0.006 0.019 0.283 ^ u2/Z (BUF_X1) - 0.006 0.000 0.283 ^ u3/A (BUF_X1) - 0.083 0.004 0.016 0.299 ^ u3/Z (BUF_X1) - 0.004 0.000 0.299 ^ out1 (out) - 0.299 data arrival time + 40.601 0.000 0.000 0.000 ^ in1 (in) + 0.032 0.026 0.026 ^ wire3/A (BUF_X8) + 43.020 0.010 0.029 0.056 ^ wire3/Z (BUF_X8) + 0.040 0.031 0.087 ^ wire2/A (BUF_X16) + 55.028 0.008 0.029 0.116 ^ wire2/Z (BUF_X16) + 0.061 0.050 0.165 ^ wire1/A (BUF_X16) + 43.586 0.009 0.030 0.196 ^ wire1/Z (BUF_X16) + 0.040 0.033 0.229 ^ u1/A (BUF_X1) + 1.008 0.007 0.028 0.257 ^ u1/Z (BUF_X1) + 0.007 0.000 0.257 ^ u2/A (BUF_X1) + 1.008 0.006 0.019 0.276 ^ u2/Z (BUF_X1) + 0.006 0.000 0.276 ^ u3/A (BUF_X1) + 0.083 0.004 0.016 0.292 ^ u3/Z (BUF_X1) + 0.004 0.000 0.292 ^ out1 (out) + 0.292 data arrival time --------------------------------------------------------------------------- (Path is unconstrained) diff --git a/src/rsz/test/repair_wire8.ok b/src/rsz/test/repair_wire8.ok index e19d33b7e23..bf9c0826422 100644 --- a/src/rsz/test/repair_wire8.ok +++ b/src/rsz/test/repair_wire8.ok @@ -33,13 +33,13 @@ Corner: slow 0.000 0.000 0.000 ^ u1/A (BUF_X2) 12.306 0.060 0.088 0.088 ^ u1/Z (BUF_X2) 0.060 0.000 0.088 ^ u2/A (BUF_X16) - 74.616 0.032 0.085 0.173 ^ u2/Z (BUF_X16) - 0.124 0.099 0.272 ^ wire1/A (BUF_X16) - 88.451 0.038 0.110 0.382 ^ wire1/Z (BUF_X16) - 0.173 0.140 0.522 ^ u3/A (BUF_X1) - 0.000 0.017 0.096 0.618 ^ u3/Z (BUF_X1) - 0.017 0.000 0.618 ^ out1 (out) - 0.618 data arrival time + 91.087 0.035 0.089 0.177 ^ u2/Z (BUF_X16) + 0.182 0.147 0.324 ^ wire1/A (BUF_X16) + 71.982 0.036 0.117 0.441 ^ wire1/Z (BUF_X16) + 0.117 0.094 0.535 ^ u3/A (BUF_X1) + 0.000 0.014 0.084 0.619 ^ u3/Z (BUF_X1) + 0.014 0.000 0.619 ^ out1 (out) + 0.619 data arrival time --------------------------------------------------------------------------- (Path is unconstrained) diff --git a/src/rsz/test/resize_slack1.ok b/src/rsz/test/resize_slack1.ok index c173d8dce00..d3a7514a0b1 100644 --- a/src/rsz/test/resize_slack1.ok +++ b/src/rsz/test/resize_slack1.ok @@ -5,4 +5,4 @@ [INFO ODB-0132] Created 2 special nets and 34 connections. [INFO ODB-0133] Created 7 nets and 30 connections. [INFO RSZ-0026] Removed 5 buffers. -r1q 0.749 +r1q 0.751 diff --git a/src/rsz/test/resize_slack3.ok b/src/rsz/test/resize_slack3.ok index c173d8dce00..d3a7514a0b1 100644 --- a/src/rsz/test/resize_slack3.ok +++ b/src/rsz/test/resize_slack3.ok @@ -5,4 +5,4 @@ [INFO ODB-0132] Created 2 special nets and 34 connections. [INFO ODB-0133] Created 7 nets and 30 connections. [INFO RSZ-0026] Removed 5 buffers. -r1q 0.749 +r1q 0.751 diff --git a/test/tinyRocket_nangate45.metrics b/test/tinyRocket_nangate45.metrics index 94cbfb41aef..cc5abd1e48c 100644 --- a/test/tinyRocket_nangate45.metrics +++ b/test/tinyRocket_nangate45.metrics @@ -3,53 +3,53 @@ "IFP::instance_count": "23878", "floorplan__design__instance__count__macros": 2, "floorplan__design__io": 269, - "design__io__hpwl": 37337478, - "design__instance__displacement__total": 25741.3, - "design__instance__displacement__mean": 1.078, - "design__instance__displacement__max": 9.722, - "route__wirelength__estimated": 480348, - "RSZ::repair_design_buffer_count": "524", - "RSZ::max_slew_slack": "32.36975340786154", + "design__io__hpwl": 37607937, + "design__instance__displacement__total": 25876.4, + "design__instance__displacement__mean": 1.084, + "design__instance__displacement__max": 7.427, + "route__wirelength__estimated": 479089, + "RSZ::repair_design_buffer_count": "515", + "RSZ::max_slew_slack": "40.53570401918181", "RSZ::max_fanout_slack": "100.0", - "RSZ::max_capacitance_slack": "34.74309796237679", - "design__instance__displacement__total": 221.337, - "design__instance__displacement__mean": 0.009, - "design__instance__displacement__max": 3.11, - "route__wirelength__estimated": 493986, + "RSZ::max_capacitance_slack": "35.658236045488195", + "design__instance__displacement__total": 437.308, + "design__instance__displacement__mean": 0.018, + "design__instance__displacement__max": 15.754, + "route__wirelength__estimated": 492762, "design__instance__count__setup_buffer": 0, "design__instance__count__hold_buffer": 0, - "RSZ::worst_slack_min": "0.07630954417683011", - "RSZ::worst_slack_max": "0.19483437636939074", + "RSZ::worst_slack_min": "0.06525749569871833", + "RSZ::worst_slack_max": "0.2572222507796264", "RSZ::tns_max": "0.0", "RSZ::hold_buffer_count": "0", "design__instance__displacement__total": 0, "design__instance__displacement__mean": 0, "design__instance__displacement__max": 0, - "route__wirelength__estimated": 493986, + "route__wirelength__estimated": 492762, "DPL::utilization": "25.4", - "DPL::design_area": "58235", - "route__net": 27918, + "DPL::design_area": "58353", + "route__net": 27908, "route__net__special": 2, "antenna__violating__nets": 0, "antenna__violating__pins": 0, "GRT::ANT::errors": "0", "design__violations": 0, - "route__net": 27918, + "route__net": 27908, "route__net__special": 2, - "route__drc_errors__iter:1": 8929, - "route__wirelength__iter:1": 603638, - "route__drc_errors__iter:2": 729, - "route__wirelength__iter:2": 601391, - "route__drc_errors__iter:3": 354, - "route__wirelength__iter:3": 600940, - "route__drc_errors__iter:4": 5, - "route__wirelength__iter:4": 600999, + "route__drc_errors__iter:1": 7055, + "route__wirelength__iter:1": 598035, + "route__drc_errors__iter:2": 264, + "route__wirelength__iter:2": 595628, + "route__drc_errors__iter:3": 71, + "route__wirelength__iter:3": 595453, + "route__drc_errors__iter:4": 4, + "route__wirelength__iter:4": 595447, "route__drc_errors__iter:5": 0, - "route__wirelength__iter:5": 600996, + "route__wirelength__iter:5": 595447, "route__drc_errors": 0, - "route__wirelength": 600996, - "route__vias": 178281, - "route__vias__singlecut": 178281, + "route__wirelength": 595447, + "route__vias": 181692, + "route__vias__singlecut": 181692, "route__vias__multicut": 0, "DRT::drv": "0", "antenna__violating__nets": 0, @@ -57,12 +57,14 @@ "DRT::ANT::errors": "0", "timing__drv__floating__nets": 0, "timing__drv__floating__pins": 0, - "DRT::worst_slack_min": "0.07826711722478875", - "DRT::worst_slack_max": "0.14311818801827295", + "DRT::worst_slack_min": "0.061957996042942984", + "DRT::worst_slack_max": "0.16320145696792088", "DRT::tns_max": "0.0", - "DRT::clock_skew": "0.04427475178465581", - "DRT::max_slew_slack": "9.541076911114217", + "DRT::clock_skew": "0.040499174604669", + "DRT::max_slew_slack": "-5.549395941353963", "DRT::max_fanout_slack": "100.0", - "DRT::max_capacitance_slack": "27.934368381154783", - "DRT::clock_period": "2.030000" + "DRT::max_capacitance_slack": "19.095310042168748", + "DRT::clock_period": "2.030000", + "flow__warnings__count": 428, + "flow__errors__count": 0 } \ No newline at end of file diff --git a/test/tinyRocket_nangate45.metrics_limits b/test/tinyRocket_nangate45.metrics_limits index 7da880c5790..134244cdfb1 100644 --- a/test/tinyRocket_nangate45.metrics_limits +++ b/test/tinyRocket_nangate45.metrics_limits @@ -1,22 +1,22 @@ { "IFP::instance_count" : "28653.6" - ,"DPL::design_area" : "69882.0" + ,"DPL::design_area" : "70023.59999999999" ,"DPL::utilization" : "30.479999999999997" - ,"RSZ::repair_design_buffer_count" : "628" + ,"RSZ::repair_design_buffer_count" : "618" ,"RSZ::max_slew_slack" : "0" ,"RSZ::max_capacitance_slack" : "0" ,"RSZ::max_fanout_slack" : "0" - ,"RSZ::worst_slack_min" : "-0.12669045582316987" - ,"RSZ::worst_slack_max" : "-0.008165623630609242" + ,"RSZ::worst_slack_min" : "-0.13774250430128165" + ,"RSZ::worst_slack_max" : "0.05422225077962642" ,"RSZ::tns_max" : "-484.72339999999997" ,"RSZ::hold_buffer_count" : "0" ,"GRT::ANT::errors" : "0" ,"DRT::drv" : "0" - ,"DRT::worst_slack_min" : "-0.12473288277521123" - ,"DRT::worst_slack_max" : "-0.05988181198172704" + ,"DRT::worst_slack_min" : "-0.14104200395705702" + ,"DRT::worst_slack_max" : "-0.03979854303207911" ,"DRT::tns_max" : "-484.72339999999997" - ,"DRT::clock_skew" : "0.053129702141586965" - ,"DRT::max_slew_slack" : "0" + ,"DRT::clock_skew" : "0.0485990095256028" + ,"DRT::max_slew_slack" : "-6.659275129624755" ,"DRT::max_capacitance_slack" : "0" ,"DRT::max_fanout_slack" : "0" ,"DRT::clock_period" : "2.03" diff --git a/test/upf_aes.ok b/test/upf_aes.ok index 3ea5a713714..f85ddb26b83 100644 --- a/test/upf_aes.ok +++ b/test/upf_aes.ok @@ -1019,7 +1019,7 @@ delta HPWL 7 % Detailed placement improvement. Importing netlist into detailed improver. -[INFO DPO-0100] Creating network with 51385 cells, 391 terminals, 51670 edges and 199030 pins. +[INFO DPO-0100] Creating network with 51385 cells, 391 terminals, 51670 edges, 199030 pins, and 0 blockages. [INFO DPO-0109] Network stats: inst 51776, edges 51670, pins 199030 [INFO DPO-0110] Number of regions is 3 [INFO DPO-0401] Setting random seed to 1. diff --git a/test/upf_test.ok b/test/upf_test.ok index 6bc96830a1c..5c047c69f42 100644 --- a/test/upf_test.ok +++ b/test/upf_test.ok @@ -190,7 +190,7 @@ delta HPWL 11 % Detailed placement improvement. Importing netlist into detailed improver. -[INFO DPO-0100] Creating network with 25 cells, 5 terminals, 29 edges and 69 pins. +[INFO DPO-0100] Creating network with 25 cells, 5 terminals, 29 edges, 69 pins, and 0 blockages. [INFO DPO-0109] Network stats: inst 30, edges 29, pins 69 [INFO DPO-0110] Number of regions is 3 [INFO DPO-0401] Setting random seed to 1.