diff --git a/src/cts/include/cts/TritonCTS.h b/src/cts/include/cts/TritonCTS.h
index 0c0cad89ad5..d8c207b4888 100644
--- a/src/cts/include/cts/TritonCTS.h
+++ b/src/cts/include/cts/TritonCTS.h
@@ -58,6 +58,8 @@ class Clock;
 class dbNetwork;
 class Unit;
 class LibertyCell;
+class Vertex;
+class Graph;
 }  // namespace sta
 
 namespace stt {
@@ -119,15 +121,18 @@ class TritonCTS
   // db functions
   bool masterExists(const std::string& master) const;
   void populateTritonCTS();
-  void writeClockNetsToDb(Clock& clockNet, std::set<odb::dbNet*>& clkLeafNets);
+  void writeClockNetsToDb(TreeBuilder* builder,
+                          std::set<odb::dbNet*>& clkLeafNets);
   void writeClockNDRsToDb(const std::set<odb::dbNet*>& clkLeafNets);
   void incrementNumClocks() { ++numberOfClocks_; }
   void clearNumClocks() { numberOfClocks_ = 0; }
   unsigned getNumClocks() const { return numberOfClocks_; }
   void initOneClockTree(odb::dbNet* driverNet,
+                        odb::dbNet* clkInputNet,
                         const std::string& sdcClockName,
                         TreeBuilder* parent);
-  TreeBuilder* initClock(odb::dbNet* net,
+  TreeBuilder* initClock(odb::dbNet* firstNet,
+                         odb::dbNet* clkInputNet,
                          const std::string& sdcClock,
                          TreeBuilder* parentBuilder);
   void disconnectAllSinksFromNet(odb::dbNet* net);
@@ -135,7 +140,8 @@ class TritonCTS
   void checkUpstreamConnections(odb::dbNet* net);
   void createClockBuffers(Clock& clockNet, odb::dbModule* parent);
   HTreeBuilder* initClockTreeForMacrosAndRegs(
-      odb::dbNet*& net,
+      odb::dbNet*& firstNet,
+      odb::dbNet* clkInputNet,
       const std::unordered_set<odb::dbMaster*>& buffer_masters,
       Clock& ClockNet,
       TreeBuilder* parentBuilder);
@@ -155,7 +161,8 @@ class TritonCTS
       Clock& clockNet,
       const std::vector<std::pair<odb::dbInst*, odb::dbMTerm*>>& registerSinks,
       odb::dbNet*& firstNet,
-      odb::dbNet*& secondNet);
+      odb::dbNet*& secondNet,
+      std::string& topBufferName);
   void computeITermPosition(odb::dbITerm* term, int& x, int& y) const;
   void countSinksPostDbWrite(TreeBuilder* builder,
                              odb::dbNet* net,
@@ -200,11 +207,18 @@ class TritonCTS
                         ClockInst& dummyClock);
   void printClockNetwork(const Clock& clockNet) const;
   void balanceMacroRegisterLatencies();
-  void computeAveSinkArrivals(TreeBuilder* builder);
+  float getVertexClkArrival(sta::Vertex* sinkVertex,
+                            odb::dbNet* topNet,
+                            odb::dbITerm* iterm);
+  void computeAveSinkArrivals(TreeBuilder* builder, sta::Graph* graph);
+  void computeSinkArrivalRecur(odb::dbNet* topClokcNet,
+                               odb::dbITerm* iterm,
+                               float& sumArrivals,
+                               unsigned& numSinks,
+                               sta::Graph* graph);
   void adjustLatencies(TreeBuilder* macroBuilder, TreeBuilder* registerBuilder);
   void computeTopBufferDelay(TreeBuilder* builder);
   odb::dbInst* insertDelayBuffer(odb::dbInst* driver,
-                                 int index,
                                  const std::string& clockName,
                                  int locX,
                                  int locY);
@@ -232,6 +246,11 @@ class TritonCTS
   // root buffer and sink bufer candidates
   std::vector<std::string> rootBuffers_;
   std::vector<std::string> sinkBuffers_;
+
+  // register tree root buffer indices
+  unsigned regTreeRootBufIndex_ = 0;
+  // index for delay buffer added for latency adjustment
+  unsigned delayBufIndex_ = 0;
 };
 
 }  // namespace cts
diff --git a/src/cts/src/TreeBuilder.h b/src/cts/src/TreeBuilder.h
index 8ac102bc759..9323d6e80c5 100644
--- a/src/cts/src/TreeBuilder.h
+++ b/src/cts/src/TreeBuilder.h
@@ -247,6 +247,12 @@ class TreeBuilder
   void setTopBufferDelay(float delay) { topBufferDelay_ = delay; }
   odb::dbInst* getTopBuffer() const { return topBuffer_; }
   void setTopBuffer(odb::dbInst* inst) { topBuffer_ = inst; }
+  std::string getTopBufferName() const { return topBufferName_; }
+  void setTopBufferName(std::string name) { topBufferName_ = std::move(name); }
+  odb::dbNet* getTopInputNet() const { return topInputNet_; }
+  void setTopInputNet(odb::dbNet* net) { topInputNet_ = net; }
+  odb::dbNet* getDrivingNet() const { return drivingNet_; }
+  void setDrivingNet(odb::dbNet* net) { drivingNet_ = net; }
 
  protected:
   CtsOptions* options_ = nullptr;
@@ -276,6 +282,9 @@ class TreeBuilder
   float aveArrival_ = 0.0;
   float topBufferDelay_ = 0.0;
   odb::dbInst* topBuffer_ = nullptr;
+  std::string topBufferName_;
+  odb::dbNet* drivingNet_ = nullptr;
+  odb::dbNet* topInputNet_ = nullptr;
 };
 
 }  // namespace cts
diff --git a/src/cts/src/TritonCTS.cpp b/src/cts/src/TritonCTS.cpp
index 6dbaefdc4ef..52c1aff048b 100644
--- a/src/cts/src/TritonCTS.cpp
+++ b/src/cts/src/TritonCTS.cpp
@@ -55,7 +55,12 @@
 #include "ord/OpenRoad.hh"
 #include "rsz/Resizer.hh"
 #include "sta/Fuzzy.hh"
+#include "sta/Graph.hh"
+#include "sta/GraphDelayCalc.hh"
 #include "sta/Liberty.hh"
+#include "sta/PathAnalysisPt.hh"
+#include "sta/PathEnd.hh"
+#include "sta/PathExpanded.hh"
 #include "sta/PatternMatch.hh"
 #include "sta/Sdc.hh"
 #include "utl/Logger.h"
@@ -268,6 +273,7 @@ void TritonCTS::buildClockTrees()
 }
 
 void TritonCTS::initOneClockTree(odb::dbNet* driverNet,
+                                 odb::dbNet* clkInputNet,
                                  const std::string& sdcClockName,
                                  TreeBuilder* parent)
 {
@@ -276,7 +282,7 @@ void TritonCTS::initOneClockTree(odb::dbNet* driverNet,
     logger_->info(
         CTS, 116, "Special net \"{}\" skipped.", driverNet->getName());
   } else {
-    clockBuilder = initClock(driverNet, sdcClockName, parent);
+    clockBuilder = initClock(driverNet, clkInputNet, sdcClockName, parent);
   }
   // Treat gated clocks as separate clock trees
   // TODO: include sinks from gated clocks together with other sinks and build
@@ -293,7 +299,8 @@ void TritonCTS::initOneClockTree(odb::dbNet* driverNet,
           if (visitedClockNets_.find(outputNet) == visitedClockNets_.end()
               && !openSta_->sdc()->isLeafPinClock(
                   network_->dbToSta(outputPin))) {
-            initOneClockTree(outputNet, sdcClockName, clockBuilder);
+            initOneClockTree(
+                outputNet, clkInputNet, sdcClockName, clockBuilder);
           }
         }
       }
@@ -453,7 +460,7 @@ void TritonCTS::writeDataToDb()
   std::unordered_set<odb::dbInst*> clkDummies;
 
   for (TreeBuilder* builder : *builders_) {
-    writeClockNetsToDb(builder->getClock(), clkLeafNets);
+    writeClockNetsToDb(builder, clkLeafNets);
     if (options_->applyNDR()) {
       writeClockNDRsToDb(clkLeafNets);
     }
@@ -934,7 +941,7 @@ void TritonCTS::populateTritonCTS()
         // Initializes the net in TritonCTS. If the number of sinks is less than
         // 2, the net is discarded.
         if (visitedClockNets_.find(net) == visitedClockNets_.end()) {
-          initOneClockTree(net, clkName, nullptr);
+          initOneClockTree(net, net, clkName, nullptr);
         }
       } else {
         logger_->warn(
@@ -955,6 +962,7 @@ void TritonCTS::populateTritonCTS()
 }
 
 TreeBuilder* TritonCTS::initClock(odb::dbNet* firstNet,
+                                  odb::dbNet* clkInputNet,
                                   const std::string& sdcClock,
                                   TreeBuilder* parentBuilder)
 {
@@ -1010,7 +1018,7 @@ TreeBuilder* TritonCTS::initClock(odb::dbNet* firstNet,
   // Build a clock tree to drive macro cells with insertion delays
   // separated from registers or leaves without insertion delays
   HTreeBuilder* builder = initClockTreeForMacrosAndRegs(
-      firstNet, buffer_masters, clockNet, parentBuilder);
+      firstNet, clkInputNet, buffer_masters, clockNet, parentBuilder);
   return builder;
 }
 
@@ -1033,6 +1041,7 @@ TreeBuilder* TritonCTS::initClock(odb::dbNet* firstNet,
 //
 HTreeBuilder* TritonCTS::initClockTreeForMacrosAndRegs(
     odb::dbNet*& firstNet,
+    odb::dbNet* clkInputNet,
     const std::unordered_set<odb::dbMaster*>& buffer_masters,
     Clock& clockNet,
     TreeBuilder* parentBuilder)
@@ -1093,12 +1102,14 @@ HTreeBuilder* TritonCTS::initClockTreeForMacrosAndRegs(
                       "macros");
   if (firstBuilder) {
     firstBuilder->setTreeType(TreeType::MacroTree);
+    firstBuilder->setTopInputNet(clkInputNet);
   }
 
   // create a new net 'secondNet' to drive register sinks
   odb::dbNet* secondNet;
-  Clock clockNet2
-      = forkRegisterClockNetwork(clockNet, registerSinks, firstNet, secondNet);
+  std::string topBufferName;
+  Clock clockNet2 = forkRegisterClockNetwork(
+      clockNet, registerSinks, firstNet, secondNet, topBufferName);
 
   // add register sinks to secondNet
   HTreeBuilder* secondBuilder = addClockSinks(
@@ -1109,6 +1120,9 @@ HTreeBuilder* TritonCTS::initClockTreeForMacrosAndRegs(
       "registers");
   if (secondBuilder) {
     secondBuilder->setTreeType(TreeType::RegisterTree);
+    secondBuilder->setTopBufferName(topBufferName);
+    secondBuilder->setDrivingNet(firstNet);
+    secondBuilder->setTopInputNet(clkInputNet);
   }
 
   return secondBuilder;
@@ -1137,7 +1151,8 @@ bool TritonCTS::separateMacroRegSinks(
 
     if (iterm->isInputSignal() && inst->isPlaced()) {
       odb::dbMTerm* mterm = iterm->getMTerm();
-      if (hasInsertionDelay(inst, mterm)) {
+      // Treat clock gaters like macro sink
+      if (hasInsertionDelay(inst, mterm) || !isSink(iterm)) {
         macroSinks.emplace_back(inst, mterm);
       } else {
         registerSinks.emplace_back(inst, mterm);
@@ -1185,7 +1200,8 @@ Clock TritonCTS::forkRegisterClockNetwork(
     Clock& clockNet,
     const std::vector<std::pair<odb::dbInst*, odb::dbMTerm*>>& registerSinks,
     odb::dbNet*& firstNet,
-    odb::dbNet*& secondNet)
+    odb::dbNet*& secondNet,
+    std::string& topBufferName)
 {
   // create a new clock net to drive register sinks
   std::string newClockName = clockNet.getName() + "_regs";
@@ -1213,11 +1229,10 @@ Clock TritonCTS::forkRegisterClockNetwork(
 
   // create a new clock buffer
   odb::dbMaster* master = db_->findMaster(options_->getRootBuffer().c_str());
-  std::string cellName = "clkbuf_regs_0_" + clockNet.getSdcName();
-
+  topBufferName = "clkbuf_regs_" + std::to_string(regTreeRootBufIndex_++) + "_"
+                  + clockNet.getSdcName();
   odb::dbInst* clockBuf = odb::dbInst::create(
-      block_, master, cellName.c_str(), false, target_module);
-
+      block_, master, topBufferName.c_str(), false, target_module);
   odb::dbITerm* inputTerm = getFirstInput(clockBuf);
   odb::dbITerm* outputTerm = clockBuf->getFirstOutput();
   inputTerm->connect(firstNet);
@@ -1262,26 +1277,25 @@ void TritonCTS::computeITermPosition(odb::dbITerm* term, int& x, int& y) const
   }
 };
 
-void TritonCTS::writeClockNetsToDb(Clock& clockNet,
+void TritonCTS::writeClockNetsToDb(TreeBuilder* builder,
                                    std::set<odb::dbNet*>& clkLeafNets)
 {
+  Clock& clockNet = builder->getClock();
   odb::dbNet* topClockNet = clockNet.getNetObj();
   // gets the module for the driver for the net
   odb::dbModule* top_module
       = network_->getNetDriverParentModule(network_->dbToSta(topClockNet));
 
-  const std::string topRegBufferName = "clkbuf_regs_0_" + clockNet.getSdcName();
-  odb::dbInst* topRegBuffer = block_->findInst(topRegBufferName.c_str());
-  odb::dbNet* topNet = nullptr;
-  if (topRegBuffer) {
-    topNet = getFirstInput(topRegBuffer)->getNet();
-  }
-
   disconnectAllSinksFromNet(topClockNet);
 
   // re-connect top buffer that separates macros from registers
-  if (topRegBuffer) {
-    getFirstInput(topRegBuffer)->connect(topNet);
+  if (builder->getTreeType() == TreeType::RegisterTree) {
+    odb::dbInst* topRegBuffer
+        = block_->findInst(builder->getTopBufferName().c_str());
+    if (topRegBuffer) {
+      odb::dbITerm* topRegBufferInputPin = getFirstInput(topRegBuffer);
+      topRegBufferInputPin->connect(builder->getDrivingNet());
+    }
   }
 
   createClockBuffers(clockNet, top_module);
@@ -2048,53 +2062,90 @@ void TritonCTS::balanceMacroRegisterLatencies()
     return;
   }
 
-  for (TreeBuilder* registerBuilder : *builders_) {
+  // Visit builders from bottom up such that latencies are adjusted near bottom
+  // trees first
+  openSta_->ensureGraph();
+  openSta_->searchPreamble();
+  openSta_->ensureClkNetwork();
+  sta::Graph* graph = openSta_->graph();
+  for (auto iter = builders_->rbegin(); iter != builders_->rend(); ++iter) {
+    TreeBuilder* registerBuilder = *iter;
     if (registerBuilder->getTreeType() == TreeType::RegisterTree) {
       TreeBuilder* macroBuilder = registerBuilder->getParent();
       if (macroBuilder) {
-        computeAveSinkArrivals(registerBuilder);
-        computeAveSinkArrivals(macroBuilder);
+        // Update graph information after possible buffers inserted
+        openSta_->updateTiming(false);
+        computeAveSinkArrivals(registerBuilder, graph);
+        computeAveSinkArrivals(macroBuilder, graph);
         adjustLatencies(macroBuilder, registerBuilder);
       }
     }
   }
 }
 
-void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder)
+float TritonCTS::getVertexClkArrival(sta::Vertex* sinkVertex,
+                                     odb::dbNet* topNet,
+                                     odb::dbITerm* iterm)
+{
+  sta::VertexPathIterator pathIter(sinkVertex, openSta_);
+  float clkPathArrival = 0.0;
+  while (pathIter.hasNext()) {
+    sta::Path* path = pathIter.next();
+    if (path->clkEdge(openSta_)->transition() != sta::RiseFall::rise()) {
+      // only populate with rising edges
+      continue;
+    }
+
+    if (path->dcalcAnalysisPt(openSta_)->delayMinMax() != sta::MinMax::max()) {
+      continue;
+      // only populate with max delay
+    }
+
+    const sta::Clock* clock = path->clock(openSta_);
+    if (clock) {
+      sta::PathExpanded expand(path, openSta_);
+      const sta::PathRef* start = expand.startPath();
+
+      odb::dbNet* pathStartNet = nullptr;
+
+      odb::dbITerm* term;
+      odb::dbBTerm* port;
+      odb::dbModITerm* modIterm;
+      odb::dbModBTerm* modBterm;
+      network_->staToDb(start->pin(openSta_), term, port, modIterm, modBterm);
+      if (term) {
+        pathStartNet = term->getNet();
+      }
+      if (port) {
+        pathStartNet = port->getNet();
+      }
+      if (pathStartNet == topNet) {
+        clkPathArrival = path->arrival(openSta_);
+        return clkPathArrival;
+      }
+    }
+  }
+  logger_->warn(CTS, 2, "No paths found for pin {}.", iterm->getName());
+  return clkPathArrival;
+}
+
+void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder, sta::Graph* graph)
 {
   Clock clock = builder->getClock();
+  odb::dbNet* topInputClockNet = clock.getNetObj();
+  if (builder->getTopInputNet() != nullptr) {
+    topInputClockNet = builder->getTopInputNet();
+  }
   // compute average input arrival at all sinks
-  float arrival = 0.0;
-  float ins_delay = 0.0;
+  float sumArrivals = 0.0;
+  unsigned numSinks = 0;
   clock.forEachSink([&](const ClockInst& sink) {
     odb::dbITerm* iterm = sink.getDbInputPin();
-    odb::dbInst* inst = iterm->getInst();
-    sta::Pin* pin = network_->dbToSta(iterm);
-    // ignore arrival fall (no inverters in current clock tree)
-    arrival
-        += openSta_->pinArrival(pin, sta::RiseFall::rise(), sta::MinMax::max());
-    // add insertion delay
-    ins_delay = 0.0;
-    sta::LibertyCell* libCell = network_->libertyCell(network_->dbToSta(inst));
-    odb::dbMTerm* mterm = iterm->getMTerm();
-    if (libCell && mterm) {
-      sta::LibertyPort* libPort
-          = libCell->findLibertyPort(mterm->getConstName());
-      if (libPort) {
-        const float rise = libPort->clkTreeDelay(
-            0.0, sta::RiseFall::rise(), sta::MinMax::max());
-        const float fall = libPort->clkTreeDelay(
-            0.0, sta::RiseFall::fall(), sta::MinMax::max());
-
-        if (rise != 0 || fall != 0) {
-          ins_delay = (rise + fall) / 2.0;
-        }
-      }
-    }
-    arrival += ins_delay;
+    computeSinkArrivalRecur(
+        topInputClockNet, iterm, sumArrivals, numSinks, graph);
   });
-  arrival = arrival / (float) clock.getNumSinks();
-  builder->setAveSinkArrival(arrival);
+  float aveArrival = sumArrivals / (float) numSinks;
+  builder->setAveSinkArrival(aveArrival);
   debugPrint(logger_,
              CTS,
              "insertion delay",
@@ -2106,6 +2157,65 @@ void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder)
              builder->getAveSinkArrival());
 }
 
+void TritonCTS::computeSinkArrivalRecur(odb::dbNet* topClokcNet,
+                                        odb::dbITerm* iterm,
+                                        float& sumArrivals,
+                                        unsigned& numSinks,
+                                        sta::Graph* graph)
+{
+  if (iterm) {
+    odb::dbInst* inst = iterm->getInst();
+    if (inst) {
+      if (isSink(iterm)) {
+        // either register or macro input pin
+        sta::Pin* pin = network_->dbToSta(iterm);
+        if (pin) {
+          sta::Vertex* sinkVertex = graph->pinDrvrVertex(pin);
+          float arrival = getVertexClkArrival(sinkVertex, topClokcNet, iterm);
+          // add insertion delay
+          float insDelay = 0.0;
+          sta::LibertyCell* libCell
+              = network_->libertyCell(network_->dbToSta(inst));
+          odb::dbMTerm* mterm = iterm->getMTerm();
+          if (libCell && mterm) {
+            sta::LibertyPort* libPort
+                = libCell->findLibertyPort(mterm->getConstName());
+            if (libPort) {
+              const float rise = libPort->clkTreeDelay(
+                  0.0, sta::RiseFall::rise(), sta::MinMax::max());
+              const float fall = libPort->clkTreeDelay(
+                  0.0, sta::RiseFall::fall(), sta::MinMax::max());
+
+              if (rise != 0 || fall != 0) {
+                insDelay = (rise + fall) / 2.0;
+              }
+            }
+          }
+          sumArrivals += (arrival + insDelay);
+          numSinks++;
+        }
+      } else {
+        // not a sink, but a clock gater
+        odb::dbITerm* outTerm = inst->getFirstOutput();
+        if (outTerm) {
+          odb::dbNet* outNet = outTerm->getNet();
+          if (outNet) {
+            odb::dbSet<odb::dbITerm> iterms = outNet->getITerms();
+            odb::dbSet<odb::dbITerm>::iterator iter;
+            for (iter = iterms.begin(); iter != iterms.end(); ++iter) {
+              odb::dbITerm* inTerm = *iter;
+              if (inTerm->getIoType() == odb::dbIoType::INPUT) {
+                computeSinkArrivalRecur(
+                    topClokcNet, inTerm, sumArrivals, numSinks, graph);
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}
+
 // Balance latencies between macro tree and register tree
 // by adding delay buffers to one tree
 void TritonCTS::adjustLatencies(TreeBuilder* macroBuilder,
@@ -2170,7 +2280,6 @@ void TritonCTS::adjustLatencies(TreeBuilder* macroBuilder,
         = builder->legalizeOneBuffer(bufferLoc, options_->getRootBuffer());
     odb::dbInst* buffer
         = insertDelayBuffer(driver,
-                            i,
                             builder->getClock().getSdcName(),
                             legalBufferLoc.getX() * scalingFactor,
                             legalBufferLoc.getY() * scalingFactor);
@@ -2188,7 +2297,7 @@ void TritonCTS::computeTopBufferDelay(TreeBuilder* builder)
   Clock clock = builder->getClock();
   std::string topBufferName;
   if (builder->getTreeType() == TreeType::RegisterTree) {
-    topBufferName = "clkbuf_regs_0_" + clock.getSdcName();
+    topBufferName = builder->getTopBufferName();
   } else {
     topBufferName = "clkbuf_0_" + clock.getName();
   }
@@ -2222,20 +2331,19 @@ void TritonCTS::computeTopBufferDelay(TreeBuilder* builder)
 // Create a new delay buffer and connect output pin of driver to input pin of
 // new buffer. Output pin of new buffer will be connected later.
 odb::dbInst* TritonCTS::insertDelayBuffer(odb::dbInst* driver,
-                                          int index,
                                           const std::string& clockName,
                                           int locX,
                                           int locY)
 {
   // creat a new input net
   std::string newNetName
-      = "delaynet_" + std::to_string(index) + "_" + clockName;
+      = "delaynet_" + std::to_string(delayBufIndex_) + "_" + clockName;
   odb::dbNet* newNet = odb::dbNet::create(block_, newNetName.c_str());
   newNet->setSigType(odb::dbSigType::CLOCK);
 
   // create a new delay buffer
   std::string newBufName
-      = "delaybuf_" + std::to_string(index) + "_" + clockName;
+      = "delaybuf_" + std::to_string(delayBufIndex_++) + "_" + clockName;
   odb::dbMaster* master = db_->findMaster(options_->getRootBuffer().c_str());
   odb::dbInst* newBuf = odb::dbInst::create(block_, master, newBufName.c_str());
 
diff --git a/src/cts/test/balance_levels.defok b/src/cts/test/balance_levels.defok
index 37dd5644672..27fc13e0e6d 100644
--- a/src/cts/test/balance_levels.defok
+++ b/src/cts/test/balance_levels.defok
@@ -4,103 +4,58 @@ BUSBITCHARS "[]" ;
 DESIGN multi_sink ;
 UNITS DISTANCE MICRONS 2000 ;
 DIEAREA ( 0 0 ) ( 200000 200000 ) ;
-COMPONENTS 413 ;
+COMPONENTS 368 ;
     - CELL/CKGATE BUF_X1 + PLACED ( 100000 100000 ) N ;
     - clkbuf_0_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 103228 140117 ) N ;
-    - clkbuf_0_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 103228 51229 ) N ;
+    - clkbuf_0_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 100250 101225 ) N ;
+    - clkbuf_0_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 103228 51229 ) N ;
+    - clkbuf_1_0__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 100250 87225 ) N ;
     - clkbuf_4_0__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 35318 119627 ) N ;
-    - clkbuf_4_0__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 37046 24385 ) N ;
+    - clkbuf_4_0__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 37181 26644 ) N ;
     - clkbuf_4_10__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 169474 113337 ) N ;
-    - clkbuf_4_10__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 169474 24449 ) N ;
+    - clkbuf_4_10__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 169474 24449 ) N ;
     - clkbuf_4_11__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 176988 120851 ) N ;
-    - clkbuf_4_11__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 176988 31963 ) N ;
+    - clkbuf_4_11__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 176988 31963 ) N ;
     - clkbuf_4_12__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 136180 148710 ) N ;
-    - clkbuf_4_12__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 135454 59367 ) N ;
+    - clkbuf_4_12__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 135454 59367 ) N ;
     - clkbuf_4_13__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 138264 161152 ) N ;
-    - clkbuf_4_13__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 137599 71599 ) N ;
+    - clkbuf_4_13__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 137599 71599 ) N ;
     - clkbuf_4_14__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 175261 148092 ) N ;
-    - clkbuf_4_14__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 175738 59340 ) N ;
+    - clkbuf_4_14__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 175738 59340 ) N ;
     - clkbuf_4_15__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 173171 159411 ) N ;
-    - clkbuf_4_15__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 173942 71102 ) N ;
+    - clkbuf_4_15__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 173942 71102 ) N ;
     - clkbuf_4_1__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 31476 129670 ) N ;
-    - clkbuf_4_1__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 30387 31043 ) N ;
+    - clkbuf_4_1__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 28978 35266 ) N ;
     - clkbuf_4_2__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 68717 119605 ) N ;
-    - clkbuf_4_2__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 64508 26508 ) N ;
+    - clkbuf_4_2__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 66913 28914 ) N ;
     - clkbuf_4_3__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 71061 131581 ) N ;
-    - clkbuf_4_3__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 71219 35368 ) N ;
+    - clkbuf_4_3__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 69122 41782 ) N ;
     - clkbuf_4_4__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 31714 150934 ) N ;
-    - clkbuf_4_4__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 31830 61223 ) N ;
+    - clkbuf_4_4__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 30369 61835 ) N ;
     - clkbuf_4_5__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 33478 164353 ) N ;
-    - clkbuf_4_5__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 33728 74610 ) N ;
+    - clkbuf_4_5__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 31247 76899 ) N ;
     - clkbuf_4_6__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 70729 156126 ) N ;
-    - clkbuf_4_6__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 68707 60992 ) N ;
+    - clkbuf_4_6__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 68700 66662 ) N ;
     - clkbuf_4_7__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 64318 165027 ) N ;
-    - clkbuf_4_7__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 66599 73858 ) N ;
+    - clkbuf_4_7__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 64650 75806 ) N ;
     - clkbuf_4_8__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 141948 115396 ) N ;
-    - clkbuf_4_8__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 141948 26508 ) N ;
+    - clkbuf_4_8__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 141948 26508 ) N ;
     - clkbuf_4_9__f_CELL\/clk2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 135237 124256 ) N ;
-    - clkbuf_4_9__f_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 135237 35368 ) N ;
-    - clkbuf_level_0_1_1027_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 133484 35513 ) N ;
-    - clkbuf_level_0_1_10_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 36329 22762 ) N ;
-    - clkbuf_level_0_1_1130_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 170571 22017 ) N ;
-    - clkbuf_level_0_1_1233_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 179381 31532 ) N ;
-    - clkbuf_level_0_1_1336_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 134033 58567 ) N ;
-    - clkbuf_level_0_1_1439_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 136203 73072 ) N ;
-    - clkbuf_level_0_1_1542_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 177253 58502 ) N ;
-    - clkbuf_level_0_1_1645_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 175553 72615 ) N ;
-    - clkbuf_level_0_1_23_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 27455 30225 ) N ;
-    - clkbuf_level_0_1_36_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 66780 23660 ) N ;
-    - clkbuf_level_0_1_49_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 72971 35513 ) N ;
-    - clkbuf_level_0_1_512_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 30235 60113 ) N ;
-    - clkbuf_level_0_1_615_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 31658 77098 ) N ;
-    - clkbuf_level_0_1_718_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 70393 59940 ) N ;
-    - clkbuf_level_0_1_821_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 68117 75839 ) N ;
-    - clkbuf_level_0_1_924_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 139675 23660 ) N ;
-    - clkbuf_level_1_1_1028_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 131732 35659 ) N ;
-    - clkbuf_level_1_1_1131_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 171668 19585 ) N ;
-    - clkbuf_level_1_1_11_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 35613 21140 ) N ;
-    - clkbuf_level_1_1_1234_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 181774 31102 ) N ;
-    - clkbuf_level_1_1_1337_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 132612 57767 ) N ;
-    - clkbuf_level_1_1_1440_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 134807 74545 ) N ;
-    - clkbuf_level_1_1_1543_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 178768 57665 ) N ;
-    - clkbuf_level_1_1_1646_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 177165 74128 ) N ;
-    - clkbuf_level_1_1_24_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 24524 29407 ) N ;
-    - clkbuf_level_1_1_37_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 69053 20813 ) N ;
-    - clkbuf_level_1_1_410_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 74723 35659 ) N ;
-    - clkbuf_level_1_1_513_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 28640 59003 ) N ;
-    - clkbuf_level_1_1_616_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 29589 79586 ) N ;
-    - clkbuf_level_1_1_719_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 72079 58888 ) N ;
-    - clkbuf_level_1_1_822_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 69636 77821 ) N ;
-    - clkbuf_level_1_1_925_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 137402 20813 ) N ;
-    - clkbuf_level_2_1_1029_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 129980 35805 ) N ;
-    - clkbuf_level_2_1_1132_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 172765 17153 ) N ;
-    - clkbuf_level_2_1_1235_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 184167 30671 ) N ;
-    - clkbuf_level_2_1_12_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 34897 19518 ) N ;
-    - clkbuf_level_2_1_1338_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 131192 56967 ) N ;
-    - clkbuf_level_2_1_1441_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 133411 76018 ) N ;
-    - clkbuf_level_2_1_1544_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 180283 56828 ) N ;
-    - clkbuf_level_2_1_1647_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 178776 75641 ) N ;
-    - clkbuf_level_2_1_25_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 21592 28590 ) N ;
-    - clkbuf_level_2_1_38_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 71326 17965 ) N ;
-    - clkbuf_level_2_1_411_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 76476 35805 ) N ;
-    - clkbuf_level_2_1_514_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 27046 57894 ) N ;
-    - clkbuf_level_2_1_617_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 27520 82074 ) N ;
-    - clkbuf_level_2_1_720_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 73765 57836 ) N ;
-    - clkbuf_level_2_1_823_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 71154 79802 ) N ;
-    - clkbuf_level_2_1_926_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 135130 17965 ) N ;
-    - clkload0 CLKBUF_X3 + SOURCE TIMING + PLACED ( 37046 24385 ) N ;
-    - clkload1 CLKBUF_X3 + SOURCE TIMING + PLACED ( 30387 31043 ) N ;
-    - clkload10 CLKBUF_X3 + SOURCE TIMING + PLACED ( 176988 31963 ) N ;
-    - clkload11 CLKBUF_X3 + SOURCE TIMING + PLACED ( 135454 59367 ) N ;
-    - clkload12 CLKBUF_X3 + SOURCE TIMING + PLACED ( 137599 71599 ) N ;
-    - clkload13 CLKBUF_X3 + SOURCE TIMING + PLACED ( 175738 59340 ) N ;
-    - clkload14 CLKBUF_X3 + SOURCE TIMING + PLACED ( 173942 71102 ) N ;
+    - clkbuf_4_9__f_clk_regs CLKBUF_X3 + SOURCE TIMING + PLACED ( 135237 35368 ) N ;
+    - clkbuf_regs_0_clk CLKBUF_X3 + SOURCE TIMING + PLACED ( 99481 48451 ) N ;
+    - clkload0 INV_X2 + SOURCE TIMING + PLACED ( 37181 26644 ) N ;
+    - clkload1 INV_X4 + SOURCE TIMING + PLACED ( 28978 35266 ) N ;
+    - clkload10 INV_X2 + SOURCE TIMING + PLACED ( 176988 31963 ) N ;
+    - clkload11 INV_X2 + SOURCE TIMING + PLACED ( 135454 59367 ) N ;
+    - clkload12 INV_X2 + SOURCE TIMING + PLACED ( 137599 71599 ) N ;
+    - clkload13 INV_X4 + SOURCE TIMING + PLACED ( 175738 59340 ) N ;
+    - clkload14 INV_X2 + SOURCE TIMING + PLACED ( 173942 71102 ) N ;
     - clkload15 INV_X2 + SOURCE TIMING + PLACED ( 35318 119627 ) N ;
     - clkload16 INV_X4 + SOURCE TIMING + PLACED ( 31476 129670 ) N ;
     - clkload17 CLKBUF_X3 + SOURCE TIMING + PLACED ( 68717 119605 ) N ;
     - clkload18 INV_X2 + SOURCE TIMING + PLACED ( 71061 131581 ) N ;
     - clkload19 INV_X2 + SOURCE TIMING + PLACED ( 31714 150934 ) N ;
-    - clkload2 CLKBUF_X3 + SOURCE TIMING + PLACED ( 64508 26508 ) N ;
+    - clkload2 INV_X2 + SOURCE TIMING + PLACED ( 69122 41782 ) N ;
     - clkload20 INV_X1 + SOURCE TIMING + PLACED ( 33478 164353 ) N ;
     - clkload21 INV_X2 + SOURCE TIMING + PLACED ( 70729 156126 ) N ;
     - clkload22 CLKBUF_X3 + SOURCE TIMING + PLACED ( 64318 165027 ) N ;
@@ -111,13 +66,13 @@ COMPONENTS 413 ;
     - clkload27 INV_X2 + SOURCE TIMING + PLACED ( 136180 148710 ) N ;
     - clkload28 INV_X4 + SOURCE TIMING + PLACED ( 175261 148092 ) N ;
     - clkload29 INV_X2 + SOURCE TIMING + PLACED ( 173171 159411 ) N ;
-    - clkload3 CLKBUF_X3 + SOURCE TIMING + PLACED ( 71219 35368 ) N ;
-    - clkload4 CLKBUF_X3 + SOURCE TIMING + PLACED ( 31830 61223 ) N ;
-    - clkload5 CLKBUF_X3 + SOURCE TIMING + PLACED ( 33728 74610 ) N ;
-    - clkload6 CLKBUF_X3 + SOURCE TIMING + PLACED ( 68707 60992 ) N ;
-    - clkload7 CLKBUF_X3 + SOURCE TIMING + PLACED ( 141948 26508 ) N ;
-    - clkload8 CLKBUF_X3 + SOURCE TIMING + PLACED ( 135237 35368 ) N ;
-    - clkload9 CLKBUF_X3 + SOURCE TIMING + PLACED ( 169474 24449 ) N ;
+    - clkload3 INV_X4 + SOURCE TIMING + PLACED ( 30369 61835 ) N ;
+    - clkload4 INV_X1 + SOURCE TIMING + PLACED ( 31247 76899 ) N ;
+    - clkload5 INV_X4 + SOURCE TIMING + PLACED ( 68700 66662 ) N ;
+    - clkload6 INV_X2 + SOURCE TIMING + PLACED ( 64650 75806 ) N ;
+    - clkload7 INV_X1 + SOURCE TIMING + PLACED ( 141948 26508 ) N ;
+    - clkload8 INV_X4 + SOURCE TIMING + PLACED ( 135237 35368 ) N ;
+    - clkload9 INV_X4 + SOURCE TIMING + PLACED ( 169474 24449 ) N ;
     - ff0 DFF_X1 + PLACED ( 5555 5555 ) N ;
     - ff1 DFF_X1 + PLACED ( 16666 5555 ) N ;
     - ff10 DFF_X1 + PLACED ( 116665 5555 ) N ;
@@ -425,126 +380,81 @@ PINS 1 ;
         + LAYER metal6 ( -140 -140 ) ( 140 140 )
         + FIXED ( 100000 199860 ) N ;
 END PINS
-NETS 84 ;
+NETS 39 ;
     - CELL/clk2 ( clkbuf_0_CELL\/clk2 A ) ( CELL/CKGATE Z ) + USE CLOCK ;
-    - clk ( PIN clk ) ( clkbuf_0_clk A ) + USE CLOCK ;
+    - clk ( PIN clk ) ( clkbuf_regs_0_clk A ) ( clkbuf_0_clk A ) + USE CLOCK ;
+    - clk_regs ( clkbuf_regs_0_clk Z ) ( clkbuf_0_clk_regs A ) + USE CLOCK ;
     - clknet_0_CELL\/clk2 ( clkbuf_4_15__f_CELL\/clk2 A ) ( clkbuf_4_14__f_CELL\/clk2 A ) ( clkbuf_4_13__f_CELL\/clk2 A ) ( clkbuf_4_12__f_CELL\/clk2 A ) ( clkbuf_4_11__f_CELL\/clk2 A ) ( clkbuf_4_10__f_CELL\/clk2 A ) ( clkbuf_4_9__f_CELL\/clk2 A )
       ( clkbuf_4_8__f_CELL\/clk2 A ) ( clkbuf_4_7__f_CELL\/clk2 A ) ( clkbuf_4_6__f_CELL\/clk2 A ) ( clkbuf_4_5__f_CELL\/clk2 A ) ( clkbuf_4_4__f_CELL\/clk2 A ) ( clkbuf_4_3__f_CELL\/clk2 A ) ( clkbuf_4_2__f_CELL\/clk2 A ) ( clkbuf_4_1__f_CELL\/clk2 A )
       ( clkbuf_4_0__f_CELL\/clk2 A ) ( clkbuf_0_CELL\/clk2 Z ) + USE CLOCK ;
-    - clknet_0_clk ( clkbuf_4_15__f_clk A ) ( clkbuf_4_14__f_clk A ) ( clkbuf_4_13__f_clk A ) ( clkbuf_4_12__f_clk A ) ( clkbuf_4_11__f_clk A ) ( clkbuf_4_10__f_clk A ) ( clkbuf_4_9__f_clk A )
-      ( clkbuf_4_8__f_clk A ) ( clkbuf_4_7__f_clk A ) ( clkbuf_4_6__f_clk A ) ( clkbuf_4_5__f_clk A ) ( clkbuf_4_4__f_clk A ) ( clkbuf_4_3__f_clk A ) ( clkbuf_4_2__f_clk A ) ( clkbuf_4_1__f_clk A )
-      ( clkbuf_4_0__f_clk A ) ( clkbuf_0_clk Z ) + USE CLOCK ;
+    - clknet_0_clk ( clkbuf_1_0__f_clk A ) ( clkbuf_0_clk Z ) + USE CLOCK ;
+    - clknet_0_clk_regs ( clkbuf_4_15__f_clk_regs A ) ( clkbuf_4_14__f_clk_regs A ) ( clkbuf_4_13__f_clk_regs A ) ( clkbuf_4_12__f_clk_regs A ) ( clkbuf_4_11__f_clk_regs A ) ( clkbuf_4_10__f_clk_regs A ) ( clkbuf_4_9__f_clk_regs A )
+      ( clkbuf_4_8__f_clk_regs A ) ( clkbuf_4_7__f_clk_regs A ) ( clkbuf_4_6__f_clk_regs A ) ( clkbuf_4_5__f_clk_regs A ) ( clkbuf_4_4__f_clk_regs A ) ( clkbuf_4_3__f_clk_regs A ) ( clkbuf_4_2__f_clk_regs A ) ( clkbuf_4_1__f_clk_regs A )
+      ( clkbuf_4_0__f_clk_regs A ) ( clkbuf_0_clk_regs Z ) + USE CLOCK ;
+    - clknet_1_0__leaf_clk ( CELL/CKGATE A ) ( clkbuf_1_0__f_clk Z ) + USE CLOCK ;
     - clknet_4_0__leaf_CELL\/clk2 ( clkload15 A ) ( ff162 CK ) ( ff163 CK ) ( ff164 CK ) ( ff165 CK ) ( ff180 CK ) ( ff181 CK )
       ( ff182 CK ) ( ff183 CK ) ( ff184 CK ) ( clkbuf_4_0__f_CELL\/clk2 Z ) + USE CLOCK ;
-    - clknet_4_0__leaf_clk ( clkload0 A ) ( clkbuf_level_0_1_10_clk A ) ( clkbuf_4_0__f_clk Z ) + USE CLOCK ;
+    - clknet_4_0__leaf_clk_regs ( clkload0 A ) ( ff0 CK ) ( ff1 CK ) ( ff2 CK ) ( ff3 CK ) ( ff18 CK ) ( ff19 CK )
+      ( ff20 CK ) ( ff21 CK ) ( ff39 CK ) ( ff40 CK ) ( clkbuf_4_0__f_clk_regs Z ) + USE CLOCK ;
     - clknet_4_10__leaf_CELL\/clk2 ( clkload25 A ) ( ff158 CK ) ( ff159 CK ) ( ff160 CK ) ( ff176 CK ) ( ff177 CK ) ( ff178 CK )
       ( ff194 CK ) ( clkbuf_4_10__f_CELL\/clk2 Z ) + USE CLOCK ;
-    - clknet_4_10__leaf_clk ( clkload9 A ) ( clkbuf_level_0_1_1130_clk A ) ( clkbuf_4_10__f_clk Z ) + USE CLOCK ;
+    - clknet_4_10__leaf_clk_regs ( clkload9 A ) ( ff14 CK ) ( ff15 CK ) ( ff16 CK ) ( ff32 CK ) ( ff33 CK ) ( ff34 CK )
+      ( ff50 CK ) ( clkbuf_4_10__f_clk_regs Z ) + USE CLOCK ;
     - clknet_4_11__leaf_CELL\/clk2 ( clkload26 A ) ( ff161 CK ) ( ff179 CK ) ( ff195 CK ) ( ff196 CK ) ( ff197 CK ) ( ff212 CK )
       ( ff213 CK ) ( ff214 CK ) ( ff215 CK ) ( clkbuf_4_11__f_CELL\/clk2 Z ) + USE CLOCK ;
-    - clknet_4_11__leaf_clk ( clkload10 A ) ( clkbuf_level_0_1_1233_clk A ) ( clkbuf_4_11__f_clk Z ) + USE CLOCK ;
+    - clknet_4_11__leaf_clk_regs ( clkload10 A ) ( ff17 CK ) ( ff35 CK ) ( ff51 CK ) ( ff52 CK ) ( ff53 CK ) ( ff68 CK )
+      ( ff69 CK ) ( ff70 CK ) ( ff71 CK ) ( clkbuf_4_11__f_clk_regs Z ) + USE CLOCK ;
     - clknet_4_12__leaf_CELL\/clk2 ( clkload27 A ) ( ff225 CK ) ( ff226 CK ) ( ff227 CK ) ( ff228 CK ) ( ff229 CK ) ( ff243 CK )
       ( ff244 CK ) ( ff245 CK ) ( ff246 CK ) ( ff247 CK ) ( clkbuf_4_12__f_CELL\/clk2 Z ) + USE CLOCK ;
-    - clknet_4_12__leaf_clk ( clkload11 A ) ( clkbuf_level_0_1_1336_clk A ) ( clkbuf_4_12__f_clk Z ) + USE CLOCK ;
+    - clknet_4_12__leaf_clk_regs ( clkload11 A ) ( ff81 CK ) ( ff82 CK ) ( ff83 CK ) ( ff84 CK ) ( ff85 CK ) ( ff99 CK )
+      ( ff100 CK ) ( ff101 CK ) ( ff103 CK ) ( clkbuf_4_12__f_clk_regs Z ) + USE CLOCK ;
     - clknet_4_13__leaf_CELL\/clk2 ( ff261 CK ) ( ff262 CK ) ( ff263 CK ) ( ff264 CK ) ( ff265 CK ) ( ff279 CK ) ( ff280 CK )
       ( ff281 CK ) ( ff282 CK ) ( ff283 CK ) ( ff297 CK ) ( ff298 CK ) ( ff299 CK ) ( clkbuf_4_13__f_CELL\/clk2 Z ) + USE CLOCK ;
-    - clknet_4_13__leaf_clk ( clkload12 A ) ( clkbuf_level_0_1_1439_clk A ) ( clkbuf_4_13__f_clk Z ) + USE CLOCK ;
+    - clknet_4_13__leaf_clk_regs ( clkload12 A ) ( ff102 CK ) ( ff117 CK ) ( ff118 CK ) ( ff119 CK ) ( ff120 CK ) ( ff121 CK )
+      ( ff135 CK ) ( ff136 CK ) ( ff137 CK ) ( ff138 CK ) ( ff139 CK ) ( clkbuf_4_13__f_clk_regs Z ) + USE CLOCK ;
     - clknet_4_14__leaf_CELL\/clk2 ( clkload28 A ) ( ff230 CK ) ( ff231 CK ) ( ff232 CK ) ( ff233 CK ) ( ff248 CK ) ( ff250 CK )
       ( ff251 CK ) ( clkbuf_4_14__f_CELL\/clk2 Z ) + USE CLOCK ;
-    - clknet_4_14__leaf_clk ( clkload13 A ) ( clkbuf_level_0_1_1542_clk A ) ( clkbuf_4_14__f_clk Z ) + USE CLOCK ;
+    - clknet_4_14__leaf_clk_regs ( clkload13 A ) ( ff86 CK ) ( ff87 CK ) ( ff88 CK ) ( ff89 CK ) ( ff104 CK ) ( ff106 CK )
+      ( ff107 CK ) ( clkbuf_4_14__f_clk_regs Z ) + USE CLOCK ;
     - clknet_4_15__leaf_CELL\/clk2 ( clkload29 A ) ( ff249 CK ) ( ff266 CK ) ( ff267 CK ) ( ff268 CK ) ( ff269 CK ) ( ff284 CK )
       ( ff285 CK ) ( ff286 CK ) ( ff287 CK ) ( clkbuf_4_15__f_CELL\/clk2 Z ) + USE CLOCK ;
-    - clknet_4_15__leaf_clk ( clkload14 A ) ( clkbuf_level_0_1_1645_clk A ) ( clkbuf_4_15__f_clk Z ) + USE CLOCK ;
+    - clknet_4_15__leaf_clk_regs ( clkload14 A ) ( ff105 CK ) ( ff122 CK ) ( ff123 CK ) ( ff124 CK ) ( ff125 CK ) ( ff140 CK )
+      ( ff141 CK ) ( ff142 CK ) ( ff143 CK ) ( clkbuf_4_15__f_clk_regs Z ) + USE CLOCK ;
     - clknet_4_1__leaf_CELL\/clk2 ( clkload16 A ) ( ff198 CK ) ( ff199 CK ) ( ff200 CK ) ( ff201 CK ) ( ff202 CK ) ( ff216 CK )
       ( clkbuf_4_1__f_CELL\/clk2 Z ) + USE CLOCK ;
-    - clknet_4_1__leaf_clk ( clkload1 A ) ( clkbuf_level_0_1_23_clk A ) ( clkbuf_4_1__f_clk Z ) + USE CLOCK ;
+    - clknet_4_1__leaf_clk_regs ( clkload1 A ) ( ff36 CK ) ( ff37 CK ) ( ff38 CK ) ( ff54 CK ) ( ff55 CK ) ( ff56 CK )
+      ( ff57 CK ) ( clkbuf_4_1__f_clk_regs Z ) + USE CLOCK ;
     - clknet_4_2__leaf_CELL\/clk2 ( clkload17 A ) ( ff150 CK ) ( ff151 CK ) ( ff152 CK ) ( ff166 CK ) ( ff167 CK ) ( ff168 CK )
       ( ff169 CK ) ( ff170 CK ) ( ff185 CK ) ( ff186 CK ) ( ff187 CK ) ( ff188 CK ) ( clkbuf_4_2__f_CELL\/clk2 Z ) + USE CLOCK ;
-    - clknet_4_2__leaf_clk ( clkload2 A ) ( clkbuf_level_0_1_36_clk A ) ( clkbuf_4_2__f_clk Z ) + USE CLOCK ;
+    - clknet_4_2__leaf_clk_regs ( ff4 CK ) ( ff5 CK ) ( ff6 CK ) ( ff7 CK ) ( ff8 CK ) ( ff22 CK ) ( ff23 CK )
+      ( ff24 CK ) ( ff25 CK ) ( ff26 CK ) ( ff41 CK ) ( ff42 CK ) ( ff43 CK ) ( ff44 CK ) ( clkbuf_4_2__f_clk_regs Z ) + USE CLOCK ;
     - clknet_4_3__leaf_CELL\/clk2 ( clkload18 A ) ( ff203 CK ) ( ff204 CK ) ( ff205 CK ) ( ff206 CK ) ( ff220 CK ) ( ff221 CK )
       ( ff222 CK ) ( ff223 CK ) ( ff224 CK ) ( clkbuf_4_3__f_CELL\/clk2 Z ) + USE CLOCK ;
-    - clknet_4_3__leaf_clk ( clkload3 A ) ( clkbuf_level_0_1_49_clk A ) ( clkbuf_4_3__f_clk Z ) + USE CLOCK ;
+    - clknet_4_3__leaf_clk_regs ( clkload2 A ) ( ff58 CK ) ( ff59 CK ) ( ff60 CK ) ( ff61 CK ) ( ff62 CK ) ( ff76 CK )
+      ( ff77 CK ) ( ff78 CK ) ( ff79 CK ) ( ff80 CK ) ( clkbuf_4_3__f_clk_regs Z ) + USE CLOCK ;
     - clknet_4_4__leaf_CELL\/clk2 ( clkload19 A ) ( ff217 CK ) ( ff218 CK ) ( ff219 CK ) ( ff234 CK ) ( ff235 CK ) ( ff236 CK )
       ( ff237 CK ) ( ff254 CK ) ( clkbuf_4_4__f_CELL\/clk2 Z ) + USE CLOCK ;
-    - clknet_4_4__leaf_clk ( clkload4 A ) ( clkbuf_level_0_1_512_clk A ) ( clkbuf_4_4__f_clk Z ) + USE CLOCK ;
+    - clknet_4_4__leaf_clk_regs ( clkload3 A ) ( ff72 CK ) ( ff73 CK ) ( ff74 CK ) ( ff75 CK ) ( ff90 CK ) ( ff91 CK )
+      ( ff92 CK ) ( ff93 CK ) ( clkbuf_4_4__f_clk_regs Z ) + USE CLOCK ;
     - clknet_4_5__leaf_CELL\/clk2 ( clkload20 A ) ( ff252 CK ) ( ff253 CK ) ( ff255 CK ) ( ff270 CK ) ( ff271 CK ) ( ff272 CK )
       ( ff273 CK ) ( ff288 CK ) ( ff289 CK ) ( ff290 CK ) ( ff291 CK ) ( clkbuf_4_5__f_CELL\/clk2 Z ) + USE CLOCK ;
-    - clknet_4_5__leaf_clk ( clkload5 A ) ( clkbuf_level_0_1_615_clk A ) ( clkbuf_4_5__f_clk Z ) + USE CLOCK ;
+    - clknet_4_5__leaf_clk_regs ( clkload4 A ) ( ff108 CK ) ( ff109 CK ) ( ff110 CK ) ( ff111 CK ) ( ff126 CK ) ( ff127 CK )
+      ( ff128 CK ) ( ff129 CK ) ( ff144 CK ) ( ff145 CK ) ( ff146 CK ) ( ff147 CK ) ( clkbuf_4_5__f_clk_regs Z ) + USE CLOCK ;
     - clknet_4_6__leaf_CELL\/clk2 ( clkload21 A ) ( ff238 CK ) ( ff239 CK ) ( ff240 CK ) ( ff241 CK ) ( ff242 CK ) ( ff257 CK )
       ( ff259 CK ) ( ff260 CK ) ( clkbuf_4_6__f_CELL\/clk2 Z ) + USE CLOCK ;
-    - clknet_4_6__leaf_clk ( clkload6 A ) ( clkbuf_level_0_1_718_clk A ) ( clkbuf_4_6__f_clk Z ) + USE CLOCK ;
+    - clknet_4_6__leaf_clk_regs ( clkload5 A ) ( ff94 CK ) ( ff95 CK ) ( ff96 CK ) ( ff97 CK ) ( ff98 CK ) ( ff113 CK )
+      ( ff114 CK ) ( clkbuf_4_6__f_clk_regs Z ) + USE CLOCK ;
     - clknet_4_7__leaf_CELL\/clk2 ( clkload22 A ) ( ff256 CK ) ( ff258 CK ) ( ff274 CK ) ( ff275 CK ) ( ff276 CK ) ( ff277 CK )
       ( ff278 CK ) ( ff292 CK ) ( ff293 CK ) ( ff294 CK ) ( ff295 CK ) ( ff296 CK ) ( clkbuf_4_7__f_CELL\/clk2 Z ) + USE CLOCK ;
-    - clknet_4_7__leaf_clk ( CELL/CKGATE A ) ( clkbuf_level_0_1_821_clk A ) ( clkbuf_4_7__f_clk Z ) + USE CLOCK ;
+    - clknet_4_7__leaf_clk_regs ( clkload6 A ) ( ff112 CK ) ( ff115 CK ) ( ff116 CK ) ( ff130 CK ) ( ff131 CK ) ( ff132 CK )
+      ( ff133 CK ) ( ff134 CK ) ( ff148 CK ) ( ff149 CK ) ( clkbuf_4_7__f_clk_regs Z ) + USE CLOCK ;
     - clknet_4_8__leaf_CELL\/clk2 ( clkload23 A ) ( ff153 CK ) ( ff154 CK ) ( ff155 CK ) ( ff156 CK ) ( ff157 CK ) ( ff171 CK )
       ( ff172 CK ) ( ff173 CK ) ( ff174 CK ) ( ff175 CK ) ( ff191 CK ) ( ff193 CK ) ( clkbuf_4_8__f_CELL\/clk2 Z ) + USE CLOCK ;
-    - clknet_4_8__leaf_clk ( clkload7 A ) ( clkbuf_level_0_1_924_clk A ) ( clkbuf_4_8__f_clk Z ) + USE CLOCK ;
+    - clknet_4_8__leaf_clk_regs ( clkload7 A ) ( ff9 CK ) ( ff10 CK ) ( ff11 CK ) ( ff12 CK ) ( ff13 CK ) ( ff27 CK )
+      ( ff28 CK ) ( ff29 CK ) ( ff30 CK ) ( ff31 CK ) ( ff47 CK ) ( ff49 CK ) ( clkbuf_4_8__f_clk_regs Z ) + USE CLOCK ;
     - clknet_4_9__leaf_CELL\/clk2 ( clkload24 A ) ( ff189 CK ) ( ff190 CK ) ( ff192 CK ) ( ff207 CK ) ( ff208 CK ) ( ff209 CK )
       ( ff210 CK ) ( ff211 CK ) ( clkbuf_4_9__f_CELL\/clk2 Z ) + USE CLOCK ;
-    - clknet_4_9__leaf_clk ( clkload8 A ) ( clkbuf_level_0_1_1027_clk A ) ( clkbuf_4_9__f_clk Z ) + USE CLOCK ;
-    - clknet_level_0_1_1027_clk ( clkbuf_level_1_1_1028_clk A ) ( clkbuf_level_0_1_1027_clk Z ) + USE CLOCK ;
-    - clknet_level_0_1_10_clk ( clkbuf_level_1_1_11_clk A ) ( clkbuf_level_0_1_10_clk Z ) + USE CLOCK ;
-    - clknet_level_0_1_1130_clk ( clkbuf_level_1_1_1131_clk A ) ( clkbuf_level_0_1_1130_clk Z ) + USE CLOCK ;
-    - clknet_level_0_1_1233_clk ( clkbuf_level_1_1_1234_clk A ) ( clkbuf_level_0_1_1233_clk Z ) + USE CLOCK ;
-    - clknet_level_0_1_1336_clk ( clkbuf_level_1_1_1337_clk A ) ( clkbuf_level_0_1_1336_clk Z ) + USE CLOCK ;
-    - clknet_level_0_1_1439_clk ( clkbuf_level_1_1_1440_clk A ) ( clkbuf_level_0_1_1439_clk Z ) + USE CLOCK ;
-    - clknet_level_0_1_1542_clk ( clkbuf_level_1_1_1543_clk A ) ( clkbuf_level_0_1_1542_clk Z ) + USE CLOCK ;
-    - clknet_level_0_1_1645_clk ( clkbuf_level_1_1_1646_clk A ) ( clkbuf_level_0_1_1645_clk Z ) + USE CLOCK ;
-    - clknet_level_0_1_23_clk ( clkbuf_level_1_1_24_clk A ) ( clkbuf_level_0_1_23_clk Z ) + USE CLOCK ;
-    - clknet_level_0_1_36_clk ( clkbuf_level_1_1_37_clk A ) ( clkbuf_level_0_1_36_clk Z ) + USE CLOCK ;
-    - clknet_level_0_1_49_clk ( clkbuf_level_1_1_410_clk A ) ( clkbuf_level_0_1_49_clk Z ) + USE CLOCK ;
-    - clknet_level_0_1_512_clk ( clkbuf_level_1_1_513_clk A ) ( clkbuf_level_0_1_512_clk Z ) + USE CLOCK ;
-    - clknet_level_0_1_615_clk ( clkbuf_level_1_1_616_clk A ) ( clkbuf_level_0_1_615_clk Z ) + USE CLOCK ;
-    - clknet_level_0_1_718_clk ( clkbuf_level_1_1_719_clk A ) ( clkbuf_level_0_1_718_clk Z ) + USE CLOCK ;
-    - clknet_level_0_1_821_clk ( clkbuf_level_1_1_822_clk A ) ( clkbuf_level_0_1_821_clk Z ) + USE CLOCK ;
-    - clknet_level_0_1_924_clk ( clkbuf_level_1_1_925_clk A ) ( clkbuf_level_0_1_924_clk Z ) + USE CLOCK ;
-    - clknet_level_1_1_1028_clk ( clkbuf_level_2_1_1029_clk A ) ( clkbuf_level_1_1_1028_clk Z ) + USE CLOCK ;
-    - clknet_level_1_1_1131_clk ( clkbuf_level_2_1_1132_clk A ) ( clkbuf_level_1_1_1131_clk Z ) + USE CLOCK ;
-    - clknet_level_1_1_11_clk ( clkbuf_level_2_1_12_clk A ) ( clkbuf_level_1_1_11_clk Z ) + USE CLOCK ;
-    - clknet_level_1_1_1234_clk ( clkbuf_level_2_1_1235_clk A ) ( clkbuf_level_1_1_1234_clk Z ) + USE CLOCK ;
-    - clknet_level_1_1_1337_clk ( clkbuf_level_2_1_1338_clk A ) ( clkbuf_level_1_1_1337_clk Z ) + USE CLOCK ;
-    - clknet_level_1_1_1440_clk ( clkbuf_level_2_1_1441_clk A ) ( clkbuf_level_1_1_1440_clk Z ) + USE CLOCK ;
-    - clknet_level_1_1_1543_clk ( clkbuf_level_2_1_1544_clk A ) ( clkbuf_level_1_1_1543_clk Z ) + USE CLOCK ;
-    - clknet_level_1_1_1646_clk ( clkbuf_level_2_1_1647_clk A ) ( clkbuf_level_1_1_1646_clk Z ) + USE CLOCK ;
-    - clknet_level_1_1_24_clk ( clkbuf_level_2_1_25_clk A ) ( clkbuf_level_1_1_24_clk Z ) + USE CLOCK ;
-    - clknet_level_1_1_37_clk ( clkbuf_level_2_1_38_clk A ) ( clkbuf_level_1_1_37_clk Z ) + USE CLOCK ;
-    - clknet_level_1_1_410_clk ( clkbuf_level_2_1_411_clk A ) ( clkbuf_level_1_1_410_clk Z ) + USE CLOCK ;
-    - clknet_level_1_1_513_clk ( clkbuf_level_2_1_514_clk A ) ( clkbuf_level_1_1_513_clk Z ) + USE CLOCK ;
-    - clknet_level_1_1_616_clk ( clkbuf_level_2_1_617_clk A ) ( clkbuf_level_1_1_616_clk Z ) + USE CLOCK ;
-    - clknet_level_1_1_719_clk ( clkbuf_level_2_1_720_clk A ) ( clkbuf_level_1_1_719_clk Z ) + USE CLOCK ;
-    - clknet_level_1_1_822_clk ( clkbuf_level_2_1_823_clk A ) ( clkbuf_level_1_1_822_clk Z ) + USE CLOCK ;
-    - clknet_level_1_1_925_clk ( clkbuf_level_2_1_926_clk A ) ( clkbuf_level_1_1_925_clk Z ) + USE CLOCK ;
-    - clknet_level_2_1_1029_clk ( ff45 CK ) ( ff46 CK ) ( ff48 CK ) ( ff63 CK ) ( ff64 CK ) ( ff65 CK ) ( ff66 CK )
-      ( ff67 CK ) ( clkbuf_level_2_1_1029_clk Z ) + USE CLOCK ;
-    - clknet_level_2_1_1132_clk ( ff14 CK ) ( ff15 CK ) ( ff16 CK ) ( ff32 CK ) ( ff33 CK ) ( ff34 CK ) ( ff50 CK )
-      ( clkbuf_level_2_1_1132_clk Z ) + USE CLOCK ;
-    - clknet_level_2_1_1235_clk ( ff17 CK ) ( ff35 CK ) ( ff51 CK ) ( ff52 CK ) ( ff53 CK ) ( ff68 CK ) ( ff69 CK )
-      ( ff70 CK ) ( ff71 CK ) ( clkbuf_level_2_1_1235_clk Z ) + USE CLOCK ;
-    - clknet_level_2_1_12_clk ( ff0 CK ) ( ff2 CK ) ( ff3 CK ) ( ff20 CK ) ( ff21 CK ) ( ff39 CK ) ( ff57 CK )
-      ( clkbuf_level_2_1_12_clk Z ) + USE CLOCK ;
-    - clknet_level_2_1_1338_clk ( ff81 CK ) ( ff82 CK ) ( ff83 CK ) ( ff84 CK ) ( ff85 CK ) ( ff99 CK ) ( ff100 CK )
-      ( ff101 CK ) ( ff103 CK ) ( clkbuf_level_2_1_1338_clk Z ) + USE CLOCK ;
-    - clknet_level_2_1_1441_clk ( ff102 CK ) ( ff117 CK ) ( ff118 CK ) ( ff119 CK ) ( ff120 CK ) ( ff121 CK ) ( ff135 CK )
-      ( ff136 CK ) ( ff137 CK ) ( ff138 CK ) ( ff139 CK ) ( clkbuf_level_2_1_1441_clk Z ) + USE CLOCK ;
-    - clknet_level_2_1_1544_clk ( ff86 CK ) ( ff87 CK ) ( ff88 CK ) ( ff89 CK ) ( ff104 CK ) ( ff106 CK ) ( ff107 CK )
-      ( clkbuf_level_2_1_1544_clk Z ) + USE CLOCK ;
-    - clknet_level_2_1_1647_clk ( ff105 CK ) ( ff122 CK ) ( ff123 CK ) ( ff124 CK ) ( ff125 CK ) ( ff140 CK ) ( ff141 CK )
-      ( ff142 CK ) ( ff143 CK ) ( clkbuf_level_2_1_1647_clk Z ) + USE CLOCK ;
-    - clknet_level_2_1_25_clk ( ff1 CK ) ( ff18 CK ) ( ff19 CK ) ( ff36 CK ) ( ff37 CK ) ( ff38 CK ) ( ff54 CK )
-      ( ff55 CK ) ( ff56 CK ) ( clkbuf_level_2_1_25_clk Z ) + USE CLOCK ;
-    - clknet_level_2_1_38_clk ( ff4 CK ) ( ff5 CK ) ( ff6 CK ) ( ff7 CK ) ( ff8 CK ) ( ff22 CK ) ( ff23 CK )
-      ( ff24 CK ) ( ff25 CK ) ( ff26 CK ) ( ff40 CK ) ( ff42 CK ) ( clkbuf_level_2_1_38_clk Z ) + USE CLOCK ;
-    - clknet_level_2_1_411_clk ( ff41 CK ) ( ff43 CK ) ( ff44 CK ) ( ff58 CK ) ( ff59 CK ) ( ff60 CK ) ( ff61 CK )
-      ( ff62 CK ) ( clkbuf_level_2_1_411_clk Z ) + USE CLOCK ;
-    - clknet_level_2_1_514_clk ( ff72 CK ) ( ff73 CK ) ( ff74 CK ) ( ff75 CK ) ( ff90 CK ) ( ff91 CK ) ( ff92 CK )
-      ( ff93 CK ) ( clkbuf_level_2_1_514_clk Z ) + USE CLOCK ;
-    - clknet_level_2_1_617_clk ( ff108 CK ) ( ff109 CK ) ( ff110 CK ) ( ff111 CK ) ( ff126 CK ) ( ff127 CK ) ( ff128 CK )
-      ( ff129 CK ) ( ff144 CK ) ( ff145 CK ) ( ff146 CK ) ( ff147 CK ) ( clkbuf_level_2_1_617_clk Z ) + USE CLOCK ;
-    - clknet_level_2_1_720_clk ( ff76 CK ) ( ff77 CK ) ( ff78 CK ) ( ff79 CK ) ( ff80 CK ) ( ff94 CK ) ( ff95 CK )
-      ( ff96 CK ) ( ff97 CK ) ( ff98 CK ) ( clkbuf_level_2_1_720_clk Z ) + USE CLOCK ;
-    - clknet_level_2_1_823_clk ( ff112 CK ) ( ff113 CK ) ( ff114 CK ) ( ff115 CK ) ( ff116 CK ) ( ff130 CK ) ( ff131 CK )
-      ( ff132 CK ) ( ff133 CK ) ( ff134 CK ) ( ff148 CK ) ( ff149 CK ) ( clkbuf_level_2_1_823_clk Z ) + USE CLOCK ;
-    - clknet_level_2_1_926_clk ( ff9 CK ) ( ff10 CK ) ( ff11 CK ) ( ff12 CK ) ( ff13 CK ) ( ff27 CK ) ( ff28 CK )
-      ( ff29 CK ) ( ff30 CK ) ( ff31 CK ) ( ff47 CK ) ( ff49 CK ) ( clkbuf_level_2_1_926_clk Z ) + USE CLOCK ;
+    - clknet_4_9__leaf_clk_regs ( clkload8 A ) ( ff45 CK ) ( ff46 CK ) ( ff48 CK ) ( ff63 CK ) ( ff64 CK ) ( ff65 CK )
+      ( ff66 CK ) ( ff67 CK ) ( clkbuf_4_9__f_clk_regs Z ) + USE CLOCK ;
 END NETS
 END DESIGN
diff --git a/src/cts/test/balance_levels.ok b/src/cts/test/balance_levels.ok
index db4d578ee6c..9ee00fc2d59 100644
--- a/src/cts/test/balance_levels.ok
+++ b/src/cts/test/balance_levels.ok
@@ -5,14 +5,34 @@
                     CLKBUF_X3
 [INFO CTS-0049] Characterization buffer is CLKBUF_X3.
 [INFO CTS-0007] Net "clk" found for clock "clk".
-[INFO CTS-0010]  Clock net "clk" has 151 sinks.
+[INFO CTS-0011]  Clock net "clk" for macros has 1 sinks.
+[INFO CTS-0011]  Clock net "clk_regs" for registers has 150 sinks.
 [INFO CTS-0010]  Clock net "CELL/clk2" has 150 sinks.
-[INFO CTS-0008] TritonCTS found 2 clock nets.
+[INFO CTS-0008] TritonCTS found 3 clock nets.
 [INFO CTS-0097] Characterization used 1 buffer(s) types.
 [INFO CTS-0200] 0 placement blockages have been identified.
 [INFO CTS-0201] 0 placed hard macros will be treated like blockages.
 [INFO CTS-0027] Generating H-Tree topology for net clk.
-[INFO CTS-0028]  Total number of sinks: 151.
+[INFO CTS-0028]  Total number of sinks: 1.
+[INFO CTS-0029]  Sinks will be clustered in groups of up to 5 and with maximum cluster diameter of 60.0 um.
+[INFO CTS-0030]  Number of static layers: 1.
+[INFO CTS-0020]  Wire segment unit: 14000  dbu (7 um).
+[INFO CTS-0021]  Distance between buffers: 7 units (100 um).
+[INFO CTS-0023]  Original sink region: [(100250, 101225), (100250, 101225)].
+[INFO CTS-0024]  Normalized sink region: [(7.16071, 7.23036), (7.16071, 7.23036)].
+[INFO CTS-0025]     Width:  0.0000.
+[INFO CTS-0026]     Height: 0.0000.
+ Level 1
+    Direction: Vertical
+    Sinks per sub-region: 1
+    Sub-region size: 0.0000 X 0.0000
+[INFO CTS-0034]     Segment length (rounded): 1.
+[INFO CTS-0032]  Stop criterion found. Max number of sinks is 15.
+[INFO CTS-0035]  Number of sinks covered: 1.
+[INFO CTS-0200] 0 placement blockages have been identified.
+[INFO CTS-0201] 0 placed hard macros will be treated like blockages.
+[INFO CTS-0027] Generating H-Tree topology for net clk_regs.
+[INFO CTS-0028]  Total number of sinks: 150.
 [INFO CTS-0029]  Sinks will be clustered in groups of up to 5 and with maximum cluster diameter of 60.0 um.
 [INFO CTS-0030]  Number of static layers: 1.
 [INFO CTS-0020]  Wire segment unit: 14000  dbu (7 um).
@@ -23,7 +43,7 @@
 [INFO CTS-0026]     Height: 6.3491.
  Level 1
     Direction: Horizontal
-    Sinks per sub-region: 76
+    Sinks per sub-region: 75
     Sub-region size: 6.7460 X 6.3491
 [INFO CTS-0034]     Segment length (rounded): 4.
  Level 2
@@ -42,7 +62,7 @@
     Sub-region size: 3.3730 X 1.5873
 [INFO CTS-0034]     Segment length (rounded): 1.
 [INFO CTS-0032]  Stop criterion found. Max number of sinks is 15.
-[INFO CTS-0035]  Number of sinks covered: 151.
+[INFO CTS-0035]  Number of sinks covered: 150.
 [INFO CTS-0200] 0 placement blockages have been identified.
 [INFO CTS-0201] 0 placed hard macros will be treated like blockages.
 [INFO CTS-0027] Generating H-Tree topology for net CELL\/clk2.
@@ -77,13 +97,17 @@
 [INFO CTS-0034]     Segment length (rounded): 1.
 [INFO CTS-0032]  Stop criterion found. Max number of sinks is 15.
 [INFO CTS-0035]  Number of sinks covered: 150.
-[INFO CTS-0093] Fixing tree levels for max depth 5
-Fixing from level 2 (parent=0 + current=2) to max 5 for driver clk
-[INFO CTS-0018]     Created 65 clock buffers.
+[INFO CTS-0018]     Created 2 clock buffers.
+[INFO CTS-0012]     Minimum number of buffers in the clock path: 2.
+[INFO CTS-0013]     Maximum number of buffers in the clock path: 2.
+[INFO CTS-0015]     Created 2 clock nets.
+[INFO CTS-0016]     Fanout distribution for the current clock = 1:1..
+[INFO CTS-0017]     Max level of the clock tree: 1.
+[INFO CTS-0018]     Created 17 clock buffers.
 [INFO CTS-0012]     Minimum number of buffers in the clock path: 2.
-[INFO CTS-0013]     Maximum number of buffers in the clock path: 5.
-[INFO CTS-0015]     Created 65 clock nets.
-[INFO CTS-0016]     Fanout distribution for the current clock = 2:1, 7:3, 8:3, 9:4, 10:1, 11:1, 12:4..
+[INFO CTS-0013]     Maximum number of buffers in the clock path: 2.
+[INFO CTS-0015]     Created 17 clock nets.
+[INFO CTS-0016]     Fanout distribution for the current clock = 7:4, 8:2, 9:3, 10:3, 11:1, 12:2, 14:1..
 [INFO CTS-0017]     Max level of the clock tree: 4.
 [INFO CTS-0018]     Created 17 clock buffers.
 [INFO CTS-0012]     Minimum number of buffers in the clock path: 2.
@@ -91,11 +115,13 @@ Fixing from level 2 (parent=0 + current=2) to max 5 for driver clk
 [INFO CTS-0015]     Created 17 clock nets.
 [INFO CTS-0016]     Fanout distribution for the current clock = 6:1, 7:2, 8:3, 9:4, 10:1, 11:1, 12:3, 13:1..
 [INFO CTS-0017]     Max level of the clock tree: 4.
-[INFO CTS-0098] Clock net "clk"
-[INFO CTS-0099]  Sinks 151
+[INFO CTS-0124] Clock net "clk"
+[INFO CTS-0125]  Sinks 1
+[INFO CTS-0098] Clock net "clk_regs"
+[INFO CTS-0099]  Sinks 165
 [INFO CTS-0100]  Leaf buffers 0
-[INFO CTS-0101]  Average sink wire length 125.08 um
-[INFO CTS-0102]  Path depth 2 - 5
+[INFO CTS-0101]  Average sink wire length 48.10 um
+[INFO CTS-0102]  Path depth 2 - 2
 [INFO CTS-0207]  Leaf load cells 30
 [INFO CTS-0098] Clock net "CELL\/clk2"
 [INFO CTS-0099]  Sinks 165
diff --git a/src/cts/test/lvt_lib.ok b/src/cts/test/lvt_lib.ok
index 9560c02ec12..d754950c415 100644
--- a/src/cts/test/lvt_lib.ok
+++ b/src/cts/test/lvt_lib.ok
@@ -7,14 +7,32 @@
                     CLKBUF_X1_L
 [INFO CTS-0049] Characterization buffer is CLKBUF_X1_L.
 [INFO CTS-0007] Net "clk" found for clock "clk".
-[INFO CTS-0010]  Clock net "clk" has 151 sinks.
+[INFO CTS-0011]  Clock net "clk" for macros has 1 sinks.
+[INFO CTS-0011]  Clock net "clk_regs" for registers has 150 sinks.
 [INFO CTS-0010]  Clock net "CELL/clk2" has 150 sinks.
-[INFO CTS-0008] TritonCTS found 2 clock nets.
+[INFO CTS-0008] TritonCTS found 3 clock nets.
 [INFO CTS-0097] Characterization used 1 buffer(s) types.
 [INFO CTS-0200] 0 placement blockages have been identified.
 [INFO CTS-0201] 0 placed hard macros will be treated like blockages.
 [INFO CTS-0027] Generating H-Tree topology for net clk.
-[INFO CTS-0028]  Total number of sinks: 151.
+[INFO CTS-0028]  Total number of sinks: 1.
+[INFO CTS-0030]  Number of static layers: 0.
+[INFO CTS-0020]  Wire segment unit: 14000  dbu (7 um).
+[INFO CTS-0023]  Original sink region: [(100250, 101225), (100250, 101225)].
+[INFO CTS-0024]  Normalized sink region: [(7.16071, 7.23036), (7.16071, 7.23036)].
+[INFO CTS-0025]     Width:  0.0000.
+[INFO CTS-0026]     Height: 0.0000.
+ Level 1
+    Direction: Vertical
+    Sinks per sub-region: 1
+    Sub-region size: 0.0000 X 0.0000
+[INFO CTS-0034]     Segment length (rounded): 1.
+[INFO CTS-0032]  Stop criterion found. Max number of sinks is 15.
+[INFO CTS-0035]  Number of sinks covered: 1.
+[INFO CTS-0200] 0 placement blockages have been identified.
+[INFO CTS-0201] 0 placed hard macros will be treated like blockages.
+[INFO CTS-0027] Generating H-Tree topology for net clk_regs.
+[INFO CTS-0028]  Total number of sinks: 150.
 [INFO CTS-0030]  Number of static layers: 0.
 [INFO CTS-0020]  Wire segment unit: 14000  dbu (7 um).
 [INFO CTS-0023]  Original sink region: [(8785, 6785), (197672, 95673)].
@@ -23,7 +41,7 @@
 [INFO CTS-0026]     Height: 6.3491.
  Level 1
     Direction: Horizontal
-    Sinks per sub-region: 76
+    Sinks per sub-region: 75
     Sub-region size: 6.7460 X 6.3491
 [INFO CTS-0034]     Segment length (rounded): 4.
  Level 2
@@ -42,7 +60,7 @@
     Sub-region size: 3.3730 X 1.5873
 [INFO CTS-0034]     Segment length (rounded): 1.
 [INFO CTS-0032]  Stop criterion found. Max number of sinks is 15.
-[INFO CTS-0035]  Number of sinks covered: 151.
+[INFO CTS-0035]  Number of sinks covered: 150.
 [INFO CTS-0200] 0 placement blockages have been identified.
 [INFO CTS-0201] 0 placed hard macros will be treated like blockages.
 [INFO CTS-0027] Generating H-Tree topology for net CELL\/clk2.
@@ -75,11 +93,17 @@
 [INFO CTS-0034]     Segment length (rounded): 1.
 [INFO CTS-0032]  Stop criterion found. Max number of sinks is 15.
 [INFO CTS-0035]  Number of sinks covered: 150.
+[INFO CTS-0018]     Created 2 clock buffers.
+[INFO CTS-0012]     Minimum number of buffers in the clock path: 2.
+[INFO CTS-0013]     Maximum number of buffers in the clock path: 2.
+[INFO CTS-0015]     Created 2 clock nets.
+[INFO CTS-0016]     Fanout distribution for the current clock = 1:1..
+[INFO CTS-0017]     Max level of the clock tree: 1.
 [INFO CTS-0018]     Created 17 clock buffers.
 [INFO CTS-0012]     Minimum number of buffers in the clock path: 2.
 [INFO CTS-0013]     Maximum number of buffers in the clock path: 2.
 [INFO CTS-0015]     Created 17 clock nets.
-[INFO CTS-0016]     Fanout distribution for the current clock = 7:1, 8:4, 9:5, 10:3, 12:2, 13:1..
+[INFO CTS-0016]     Fanout distribution for the current clock = 7:1, 8:4, 9:6, 10:2, 12:2, 13:1..
 [INFO CTS-0017]     Max level of the clock tree: 4.
 [INFO CTS-0018]     Created 17 clock buffers.
 [INFO CTS-0012]     Minimum number of buffers in the clock path: 2.
@@ -87,10 +111,12 @@
 [INFO CTS-0015]     Created 17 clock nets.
 [INFO CTS-0016]     Fanout distribution for the current clock = 7:3, 8:2, 9:4, 10:4, 12:2, 13:1..
 [INFO CTS-0017]     Max level of the clock tree: 4.
-[INFO CTS-0098] Clock net "clk"
-[INFO CTS-0099]  Sinks 166
+[INFO CTS-0124] Clock net "clk"
+[INFO CTS-0125]  Sinks 1
+[INFO CTS-0098] Clock net "clk_regs"
+[INFO CTS-0099]  Sinks 165
 [INFO CTS-0100]  Leaf buffers 0
-[INFO CTS-0101]  Average sink wire length 121.61 um
+[INFO CTS-0101]  Average sink wire length 48.97 um
 [INFO CTS-0102]  Path depth 2 - 2
 [INFO CTS-0207]  Leaf load cells 30
 [INFO CTS-0098] Clock net "CELL\/clk2"
diff --git a/test/ibex_sky130hd.metrics_limits b/test/ibex_sky130hd.metrics_limits
index 185e5444f13..11585434c29 100644
--- a/test/ibex_sky130hd.metrics_limits
+++ b/test/ibex_sky130hd.metrics_limits
@@ -1,22 +1,22 @@
 {
   "IFP::instance_count" : "18835.2"
- ,"DPL::design_area" : "201139.19999999998"
- ,"DPL::utilization" : "33.12"
+ ,"DPL::design_area" : "197145.6"
+ ,"DPL::utilization" : "32.52"
  ,"RSZ::repair_design_buffer_count" : "403"
  ,"RSZ::max_slew_slack" : "0"
  ,"RSZ::max_capacitance_slack" : "0"
  ,"RSZ::max_fanout_slack" : "0"
- ,"RSZ::worst_slack_min" : "-1.514693533972104"
- ,"RSZ::worst_slack_max" : "-3.4550099408817325"
- ,"RSZ::tns_max" : "-2410.336839746874"
- ,"RSZ::hold_buffer_count" : "387"
+ ,"RSZ::worst_slack_min" : "-1.0439922649094353"
+ ,"RSZ::worst_slack_max" : "-2.3114357842543503"
+ ,"RSZ::tns_max" : "-2381.8289966316056"
+ ,"RSZ::hold_buffer_count" : "0"
  ,"GRT::ANT::errors" : "0"
  ,"DRT::drv" : "0"
- ,"DRT::worst_slack_min" : "-2.022091227750159"
- ,"DRT::worst_slack_max" : "-4.526241963178564"
- ,"DRT::tns_max" : "-2565.5963862496214"
- ,"DRT::clock_skew" : "3.196192734278436"
- ,"DRT::max_slew_slack" : "-4.185469746589661"
+ ,"DRT::worst_slack_min" : "-1.2937988918086523"
+ ,"DRT::worst_slack_max" : "-3.319472133845383"
+ ,"DRT::tns_max" : "-2397.881877888032"
+ ,"DRT::clock_skew" : "3.1835918802282483"
+ ,"DRT::max_slew_slack" : "-5.152180790901185"
  ,"DRT::max_capacitance_slack" : "0"
  ,"DRT::max_fanout_slack" : "0"
  ,"DRT::clock_period" : "15.155"
diff --git a/test/ibex_sky130hs.metrics_limits b/test/ibex_sky130hs.metrics_limits
index 3ccd598ac6d..ad127349cd9 100644
--- a/test/ibex_sky130hs.metrics_limits
+++ b/test/ibex_sky130hs.metrics_limits
@@ -1,23 +1,23 @@
 {
   "IFP::instance_count" : "16722.0"
- ,"DPL::design_area" : "303136.8"
- ,"DPL::utilization" : "50.16"
+ ,"DPL::design_area" : "297738.0"
+ ,"DPL::utilization" : "49.199999999999996"
  ,"RSZ::repair_design_buffer_count" : "562"
  ,"RSZ::max_slew_slack" : "0"
  ,"RSZ::max_capacitance_slack" : "0"
  ,"RSZ::max_fanout_slack" : "0"
- ,"RSZ::worst_slack_min" : "-1.1252660978179787"
- ,"RSZ::worst_slack_max" : "-1.1080318832747007"
+ ,"RSZ::worst_slack_min" : "-0.8296003753220063"
+ ,"RSZ::worst_slack_max" : "-0.3892583777709363"
  ,"RSZ::tns_max" : "-1573.2615"
- ,"RSZ::hold_buffer_count" : "409"
- ,"GRT::ANT::errors" : "1"
+ ,"RSZ::hold_buffer_count" : "0"
+ ,"GRT::ANT::errors" : "0"
  ,"DRT::drv" : "0"
- ,"DRT::worst_slack_min" : "-1.4389010025203173"
- ,"DRT::worst_slack_max" : "-1.7248460560269625"
- ,"DRT::tns_max" : "-1596.287934744031"
- ,"DRT::clock_skew" : "2.3666093754562323"
- ,"DRT::max_slew_slack" : "-35.96203565597534"
- ,"DRT::max_capacitance_slack" : "-40.381100718502445"
+ ,"DRT::worst_slack_min" : "-0.8301188494891697"
+ ,"DRT::worst_slack_max" : "-1.0005294288490796"
+ ,"DRT::tns_max" : "-1573.2615"
+ ,"DRT::clock_skew" : "2.3486445453242455"
+ ,"DRT::max_slew_slack" : "-43.21588397026062"
+ ,"DRT::max_capacitance_slack" : "-48.642419470111655"
  ,"DRT::max_fanout_slack" : "0"
  ,"DRT::clock_period" : "11.29"
  ,"DRT::ANT::errors" : "0"