diff --git a/doc/source/API/FilterSolutions.rst b/doc/source/API/FilterSolutions.rst
index 0eec03a6cd5..29ae74aa783 100644
--- a/doc/source/API/FilterSolutions.rst
+++ b/doc/source/API/FilterSolutions.rst
@@ -60,6 +60,8 @@ Distributed filters rely on transmission lines and resonators.
 * ``DistributedSubstrate`` to define attributes and  parameters of the substrate used in distributed filters.
 * ``DistributedGeometry`` to define attributes and parameters of the substrate geometry used in distributed filters.
 * ``DistributedRadial`` to define attributes and parameters of the substrate radial used in distributed filters.
+* ``DistributedParasitics`` to define attributes and parameters of parasitic values associated with lumped elements.
+
 
 
 They are accessible through:
@@ -76,6 +78,7 @@ They are accessible through:
    distributed_substrate.DistributedSubstrate
    distributed_geometry.DistributedGeometry
    distributed_radial.DistributedRadial
+   distributed_parasitics.DistributedParasitics
 
 ``Distributed Filter`` example:
 
diff --git a/src/ansys/aedt/core/filtersolutions.py b/src/ansys/aedt/core/filtersolutions.py
index 39cb2c46440..f54284c3b09 100644
--- a/src/ansys/aedt/core/filtersolutions.py
+++ b/src/ansys/aedt/core/filtersolutions.py
@@ -26,6 +26,7 @@
 import ansys.aedt.core.filtersolutions_core
 from ansys.aedt.core.filtersolutions_core.attributes import Attributes
 from ansys.aedt.core.filtersolutions_core.distributed_geometry import DistributedGeometry
+from ansys.aedt.core.filtersolutions_core.distributed_parasitics import DistributedParasitics
 from ansys.aedt.core.filtersolutions_core.distributed_radial import DistributedRadial
 from ansys.aedt.core.filtersolutions_core.distributed_substrate import DistributedSubstrate
 from ansys.aedt.core.filtersolutions_core.distributed_topology import DistributedTopology
@@ -128,6 +129,7 @@ def _init_distributed_design(self):
         self.substrate = DistributedSubstrate()
         self.geometry = DistributedGeometry()
         self.radial = DistributedRadial()
+        self.parasitics = DistributedParasitics()
 
     def _set_distributed_implementation(self):
         """Set ``FilterSolutions`` implementation to ``Distributed Design``."""
diff --git a/src/ansys/aedt/core/filtersolutions_core/distributed_parasitics.py b/src/ansys/aedt/core/filtersolutions_core/distributed_parasitics.py
new file mode 100644
index 00000000000..48c31354989
--- /dev/null
+++ b/src/ansys/aedt/core/filtersolutions_core/distributed_parasitics.py
@@ -0,0 +1,320 @@
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates.
+# SPDX-License-Identifier: MIT
+#
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in all
+# copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+from ctypes import c_char_p
+from ctypes import c_int
+
+import ansys.aedt.core
+
+
+class DistributedParasitics:
+    """Defines parasitic parameters of distributed filters.
+
+    This class allows you to define and modify the layout parasitics parameters of distributed filters.
+    """
+
+    def __init__(self):
+        self._dll = ansys.aedt.core.filtersolutions_core._dll_interface()._dll
+        self._dll_interface = ansys.aedt.core.filtersolutions_core._dll_interface()
+        self._define_parasitics_dll_functions()
+
+    def _define_parasitics_dll_functions(self):
+        """Define C++ API DLL functions."""
+        self._dll.setDistributedCapacitorQ.argtype = c_char_p
+        self._dll.setDistributedCapacitorQ.restype = c_int
+        self._dll.getDistributedCapacitorQ.argtypes = [c_char_p, c_int]
+        self._dll.getDistributedCapacitorQ.restype = c_int
+
+        self._dll.setDistributedCapacitorRs.argtype = c_char_p
+        self._dll.setDistributedCapacitorRs.restype = c_int
+        self._dll.getDistributedCapacitorRs.argtypes = [c_char_p, c_int]
+        self._dll.getDistributedCapacitorRs.restype = c_int
+
+        self._dll.setDistributedCapacitorRp.argtype = c_char_p
+        self._dll.setDistributedCapacitorRp.restype = c_int
+        self._dll.getDistributedCapacitorRp.argtypes = [c_char_p, c_int]
+        self._dll.getDistributedCapacitorRp.restype = c_int
+
+        self._dll.setDistributedCapacitorLs.argtype = c_char_p
+        self._dll.setDistributedCapacitorLs.restype = c_int
+        self._dll.getDistributedCapacitorLs.argtypes = [c_char_p, c_int]
+        self._dll.getDistributedCapacitorLs.restype = c_int
+
+        self._dll.setDistributedInductorQ.argtype = c_char_p
+        self._dll.setDistributedInductorQ.restype = c_int
+        self._dll.getDistributedInductorQ.argtypes = [c_char_p, c_int]
+        self._dll.getDistributedInductorQ.restype = c_int
+
+        self._dll.setDistributedInductorRs.argtype = c_char_p
+        self._dll.setDistributedInductorRs.restype = c_int
+        self._dll.getDistributedInductorRs.argtypes = [c_char_p, c_int]
+        self._dll.getDistributedInductorRs.restype = c_int
+
+        self._dll.setDistributedInductorRp.argtype = c_char_p
+        self._dll.setDistributedInductorRp.restype = c_int
+        self._dll.getDistributedInductorRp.argtypes = [c_char_p, c_int]
+        self._dll.getDistributedInductorRp.restype = c_int
+
+        self._dll.setDistributedInductorCp.argtype = c_char_p
+        self._dll.setDistributedInductorCp.restype = c_int
+        self._dll.getDistributedInductorCp.argtypes = [c_char_p, c_int]
+        self._dll.getDistributedInductorCp.restype = c_int
+
+        self._dll.setDistributedOddResistance.argtype = c_char_p
+        self._dll.setDistributedOddResistance.restype = c_int
+        self._dll.getDistributedOddResistance.argtypes = [c_char_p, c_int]
+        self._dll.getDistributedOddResistance.restype = c_int
+
+        self._dll.setDistributedEvenResistance.argtype = c_char_p
+        self._dll.setDistributedEvenResistance.restype = c_int
+        self._dll.getDistributedEvenResistance.argtypes = [c_char_p, c_int]
+        self._dll.getDistributedEvenResistance.restype = c_int
+
+        self._dll.setDistributedOddConductance.argtype = c_char_p
+        self._dll.setDistributedOddConductance.restype = c_int
+        self._dll.getDistributedOddConductance.argtypes = [c_char_p, c_int]
+        self._dll.getDistributedOddConductance.restype = c_int
+
+        self._dll.setDistributedEvenConductance.argtype = c_char_p
+        self._dll.setDistributedEvenConductance.restype = c_int
+        self._dll.getDistributedEvenConductance.argtypes = [c_char_p, c_int]
+        self._dll.getDistributedEvenConductance.restype = c_int
+
+        self._dll.setDistributedMinSegmentLength.argtype = c_char_p
+        self._dll.setDistributedMinSegmentLength.restype = c_int
+        self._dll.getDistributedMinSegmentLength.argtypes = [c_char_p, c_int]
+        self._dll.getDistributedMinSegmentLength.restype = c_int
+
+    @property
+    def capacitor_q(self) -> str:
+        """Q factor value of non-ideal capacitors in the synthesized circuit.
+        The default is ``infinite``.
+
+        Returns
+        -------
+        str
+        """
+        capacitor_q_string = self._dll_interface.get_string(self._dll.getDistributedCapacitorQ)
+        return capacitor_q_string
+
+    @capacitor_q.setter
+    def capacitor_q(self, capacitor_q_string):
+        self._dll_interface.set_string(self._dll.setDistributedCapacitorQ, capacitor_q_string)
+
+    @property
+    def capacitor_rs(self) -> str:
+        """Series resistor value of non-ideal capacitors in the synthesized circuit.
+        The default is ``0``.
+
+        Returns
+        -------
+        str
+        """
+        capacitor_rs_string = self._dll_interface.get_string(self._dll.getDistributedCapacitorRs)
+        return capacitor_rs_string
+
+    @capacitor_rs.setter
+    def capacitor_rs(self, capacitor_rs_string):
+        self._dll_interface.set_string(self._dll.setDistributedCapacitorRs, capacitor_rs_string)
+
+    @property
+    def capacitor_rp(self) -> str:
+        """Shunt resistor value of non-ideal capacitors in the synthesized circuit.
+        The default is ``infinite``.
+
+        Returns
+        -------
+        str
+        """
+        capacitor_rp_string = self._dll_interface.get_string(self._dll.getDistributedCapacitorRp)
+        return capacitor_rp_string
+
+    @capacitor_rp.setter
+    def capacitor_rp(self, capacitor_rp_string):
+        self._dll_interface.set_string(self._dll.setDistributedCapacitorRp, capacitor_rp_string)
+
+    @property
+    def capacitor_ls(self) -> str:
+        """Series inductance value of non-ideal capacitors in the synthesized circuit.
+        The default is ``0``.
+
+        Returns
+        -------
+        str
+        """
+        capacitor_ls_string = self._dll_interface.get_string(self._dll.getDistributedCapacitorLs)
+        return capacitor_ls_string
+
+    @capacitor_ls.setter
+    def capacitor_ls(self, capacitor_ls_string):
+        self._dll_interface.set_string(self._dll.setDistributedCapacitorLs, capacitor_ls_string)
+
+    @property
+    def inductor_q(self) -> str:
+        """Q factor value of non-ideal inductors in the synthesized circuit.
+        The default is ``infinite``.
+
+        Returns
+        -------
+        str
+        """
+        inductor_q_string = self._dll_interface.get_string(self._dll.getDistributedInductorQ)
+        return inductor_q_string
+
+    @inductor_q.setter
+    def inductor_q(self, inductor_q_string):
+        self._dll_interface.set_string(self._dll.setDistributedInductorQ, inductor_q_string)
+
+    @property
+    def inductor_rs(self) -> str:
+        """Series resistor value of non-ideal inductors in the synthesized circuit.
+        The default is` ``0``.
+
+        Returns
+        -------
+        str
+        """
+        inductor_rs_string = self._dll_interface.get_string(self._dll.getDistributedInductorRs)
+        return inductor_rs_string
+
+    @inductor_rs.setter
+    def inductor_rs(self, inductor_rs_string):
+        self._dll_interface.set_string(self._dll.setDistributedInductorRs, inductor_rs_string)
+
+    @property
+    def inductor_rp(self) -> str:
+        """Shunt resistor value of non-ideal inductors in the synthesized circuit.
+        The default is ``infinite``.
+
+        Returns
+        -------
+        str
+        """
+        inductor_rp_string = self._dll_interface.get_string(self._dll.getDistributedInductorRp)
+        return inductor_rp_string
+
+    @inductor_rp.setter
+    def inductor_rp(self, inductor_rp_string):
+        self._dll_interface.set_string(self._dll.setDistributedInductorRp, inductor_rp_string)
+
+    @property
+    def inductor_cp(self) -> str:
+        """Shunt capacitor value of non-ideal inductors in the synthesized circuit.
+        The default is ``0``.
+
+        Returns
+        -------
+        str
+        """
+        inductor_cp_string = self._dll_interface.get_string(self._dll.getDistributedInductorCp)
+        return inductor_cp_string
+
+    @inductor_cp.setter
+    def inductor_cp(self, inductor_cp_string):
+        self._dll_interface.set_string(self._dll.setDistributedInductorCp, inductor_cp_string)
+
+    @property
+    def line_odd_resistance(self) -> str:
+        """Odd-mode conductor resistance value of the line per unit length."
+        This parameter is defined for standard ``RLGC`` transmission line model substrate types.
+        The default is ``0``.
+
+        Returns
+        -------
+        str
+        """
+        odd_resistance_string = self._dll_interface.get_string(self._dll.getDistributedOddResistance)
+        return odd_resistance_string
+
+    @line_odd_resistance.setter
+    def line_odd_resistance(self, odd_resistance_string):
+        self._dll_interface.set_string(self._dll.setDistributedOddResistance, odd_resistance_string)
+
+    @property
+    def line_even_resistance(self) -> str:
+        """Even-mode conductor resistance value of the line per unit length."
+        This parameter is defined for standard ``RLGC`` transmission line model substrate types.
+        The default is ``0``.
+
+        Returns
+        -------
+        str
+        """
+        even_resistance_string = self._dll_interface.get_string(self._dll.getDistributedEvenResistance)
+        return even_resistance_string
+
+    @line_even_resistance.setter
+    def line_even_resistance(self, even_resistance_string):
+        self._dll_interface.set_string(self._dll.setDistributedEvenResistance, even_resistance_string)
+
+    @property
+    def line_odd_conductance(self) -> str:
+        """Odd-mode dielectric conductance of the line per unit length.
+        This parameter is defined for standard ``RLGC`` transmission line model substrate types.
+        The default is ``0``.
+
+        Returns
+        -------
+        str
+        """
+        odd_conductance_string = self._dll_interface.get_string(self._dll.getDistributedOddConductance)
+        return odd_conductance_string
+
+    @line_odd_conductance.setter
+    def line_odd_conductance(self, odd_conductance_string):
+        self._dll_interface.set_string(self._dll.setDistributedOddConductance, odd_conductance_string)
+
+    @property
+    def line_even_conductance(self) -> str:
+        """Even-mode dielectric conductance of the line per unit length.
+        This parameter is defined for standard ``RLGC`` transmission line model substrate types.
+        The default is ``0``.
+
+        Returns
+        -------
+        str
+        """
+        even_conductance_string = self._dll_interface.get_string(self._dll.getDistributedEvenConductance)
+        return even_conductance_string
+
+    @line_even_conductance.setter
+    def line_even_conductance(self, even_conductance_string):
+        self._dll_interface.set_string(self._dll.setDistributedEvenConductance, even_conductance_string)
+
+    @property
+    def line_min_segment_lengths(self) -> str:
+        """Default value for the minimum segment lengths between stubs.
+        This parameter is defined for standard ``RLGC`` transmission line model substrate types.
+        The default is ``0``.
+
+        Returns
+        -------
+        str
+        """
+        line_min_segment_length_string = self._dll_interface.get_string(self._dll.getDistributedMinSegmentLength)
+        return line_min_segment_length_string
+
+    @line_min_segment_lengths.setter
+    def line_min_segment_lengths(self, line_min_segment_length_string):
+        self._dll_interface.set_string(self._dll.setDistributedMinSegmentLength, line_min_segment_length_string)
diff --git a/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/capacitor_ls_1n.ckt b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/capacitor_ls_1n.ckt
new file mode 100644
index 00000000000..982129e7efa
--- /dev/null
+++ b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/capacitor_ls_1n.ckt
@@ -0,0 +1,32 @@
+*
+*Length Units: Meters
+*
+V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0
+Rg 1 2 50
+MT1S1 2 5 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MTSeg0 2 3 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MT1S2 3 7 Wid=0.00508 Len=0.01008 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MTSeg1 3 4 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MT1S3 4 9 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+Rl 4 0 50
+*
+* The Following Dummy Resistors May Be Required For Spice.
+*
+Rstb2 5 0 5E+09
+Rstb3 6 0 5E+09
+Rseg4 3 0 5E+09
+Rstb5 7 0 5E+09
+Rstb6 8 0 5E+09
+Rstb7 9 0 5E+09
+Rstb8 10 0 5E+09
+*
+* End Dummy Resistors
+*
+*
+.AC DEC 200 2E+08 5E+09
+.PLOT AC VDB(Rl) -70 0
+.PLOT AC VP(Rl) -200 200
+.PLOT AC VG(Rl) -1E-08 2E-09
+.TRAN  5E-11 1E-08 0
+.PLOT TRAN V(Rl) -0.1 0.6
+.END
diff --git a/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/capacitor_q_100.ckt b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/capacitor_q_100.ckt
new file mode 100644
index 00000000000..49434e28b58
--- /dev/null
+++ b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/capacitor_q_100.ckt
@@ -0,0 +1,29 @@
+*
+*Length Units: Meters
+*
+V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0
+Rg 1 2 50
+C1S1 2 0 1.967E-12
+R1Sq1 2 0 8090
+MTSeg0 2 3 Wid=0.0003175 Len=0.01974 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+C1S2 3 0 6.366E-12
+R1Sq2 3 0 2500
+MTSeg1 3 4 Wid=0.0003175 Len=0.01974 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+C1S3 4 0 1.967E-12
+R1Sq3 4 0 8090
+Rl 4 0 50
+*
+* The Following Dummy Resistors May Be Required For Spice.
+*
+Rseg2 3 0 5E+09
+*
+* End Dummy Resistors
+*
+*
+.AC DEC 200 2E+08 5E+09
+.PLOT AC VDB(Rl) -50 0
+.PLOT AC VP(Rl) -200 200
+.PLOT AC VG(Rl) 0 2.5E-09
+.TRAN  5E-11 1E-08 0
+.PLOT TRAN V(Rl) -0.1 0.6
+.END
diff --git a/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/capacitor_rp_1000.ckt b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/capacitor_rp_1000.ckt
new file mode 100644
index 00000000000..982129e7efa
--- /dev/null
+++ b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/capacitor_rp_1000.ckt
@@ -0,0 +1,32 @@
+*
+*Length Units: Meters
+*
+V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0
+Rg 1 2 50
+MT1S1 2 5 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MTSeg0 2 3 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MT1S2 3 7 Wid=0.00508 Len=0.01008 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MTSeg1 3 4 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MT1S3 4 9 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+Rl 4 0 50
+*
+* The Following Dummy Resistors May Be Required For Spice.
+*
+Rstb2 5 0 5E+09
+Rstb3 6 0 5E+09
+Rseg4 3 0 5E+09
+Rstb5 7 0 5E+09
+Rstb6 8 0 5E+09
+Rstb7 9 0 5E+09
+Rstb8 10 0 5E+09
+*
+* End Dummy Resistors
+*
+*
+.AC DEC 200 2E+08 5E+09
+.PLOT AC VDB(Rl) -70 0
+.PLOT AC VP(Rl) -200 200
+.PLOT AC VG(Rl) -1E-08 2E-09
+.TRAN  5E-11 1E-08 0
+.PLOT TRAN V(Rl) -0.1 0.6
+.END
diff --git a/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/capacitor_rs_1.ckt b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/capacitor_rs_1.ckt
new file mode 100644
index 00000000000..982129e7efa
--- /dev/null
+++ b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/capacitor_rs_1.ckt
@@ -0,0 +1,32 @@
+*
+*Length Units: Meters
+*
+V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0
+Rg 1 2 50
+MT1S1 2 5 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MTSeg0 2 3 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MT1S2 3 7 Wid=0.00508 Len=0.01008 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MTSeg1 3 4 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MT1S3 4 9 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+Rl 4 0 50
+*
+* The Following Dummy Resistors May Be Required For Spice.
+*
+Rstb2 5 0 5E+09
+Rstb3 6 0 5E+09
+Rseg4 3 0 5E+09
+Rstb5 7 0 5E+09
+Rstb6 8 0 5E+09
+Rstb7 9 0 5E+09
+Rstb8 10 0 5E+09
+*
+* End Dummy Resistors
+*
+*
+.AC DEC 200 2E+08 5E+09
+.PLOT AC VDB(Rl) -70 0
+.PLOT AC VP(Rl) -200 200
+.PLOT AC VG(Rl) -1E-08 2E-09
+.TRAN  5E-11 1E-08 0
+.PLOT TRAN V(Rl) -0.1 0.6
+.END
diff --git a/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/inductor_cp_1n.ckt b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/inductor_cp_1n.ckt
new file mode 100644
index 00000000000..982129e7efa
--- /dev/null
+++ b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/inductor_cp_1n.ckt
@@ -0,0 +1,32 @@
+*
+*Length Units: Meters
+*
+V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0
+Rg 1 2 50
+MT1S1 2 5 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MTSeg0 2 3 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MT1S2 3 7 Wid=0.00508 Len=0.01008 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MTSeg1 3 4 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MT1S3 4 9 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+Rl 4 0 50
+*
+* The Following Dummy Resistors May Be Required For Spice.
+*
+Rstb2 5 0 5E+09
+Rstb3 6 0 5E+09
+Rseg4 3 0 5E+09
+Rstb5 7 0 5E+09
+Rstb6 8 0 5E+09
+Rstb7 9 0 5E+09
+Rstb8 10 0 5E+09
+*
+* End Dummy Resistors
+*
+*
+.AC DEC 200 2E+08 5E+09
+.PLOT AC VDB(Rl) -70 0
+.PLOT AC VP(Rl) -200 200
+.PLOT AC VG(Rl) -1E-08 2E-09
+.TRAN  5E-11 1E-08 0
+.PLOT TRAN V(Rl) -0.1 0.6
+.END
diff --git a/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/inductor_q_100.ckt b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/inductor_q_100.ckt
new file mode 100644
index 00000000000..982129e7efa
--- /dev/null
+++ b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/inductor_q_100.ckt
@@ -0,0 +1,32 @@
+*
+*Length Units: Meters
+*
+V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0
+Rg 1 2 50
+MT1S1 2 5 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MTSeg0 2 3 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MT1S2 3 7 Wid=0.00508 Len=0.01008 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MTSeg1 3 4 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MT1S3 4 9 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+Rl 4 0 50
+*
+* The Following Dummy Resistors May Be Required For Spice.
+*
+Rstb2 5 0 5E+09
+Rstb3 6 0 5E+09
+Rseg4 3 0 5E+09
+Rstb5 7 0 5E+09
+Rstb6 8 0 5E+09
+Rstb7 9 0 5E+09
+Rstb8 10 0 5E+09
+*
+* End Dummy Resistors
+*
+*
+.AC DEC 200 2E+08 5E+09
+.PLOT AC VDB(Rl) -70 0
+.PLOT AC VP(Rl) -200 200
+.PLOT AC VG(Rl) -1E-08 2E-09
+.TRAN  5E-11 1E-08 0
+.PLOT TRAN V(Rl) -0.1 0.6
+.END
diff --git a/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/inductor_rp_1000.ckt b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/inductor_rp_1000.ckt
new file mode 100644
index 00000000000..982129e7efa
--- /dev/null
+++ b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/inductor_rp_1000.ckt
@@ -0,0 +1,32 @@
+*
+*Length Units: Meters
+*
+V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0
+Rg 1 2 50
+MT1S1 2 5 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MTSeg0 2 3 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MT1S2 3 7 Wid=0.00508 Len=0.01008 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MTSeg1 3 4 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MT1S3 4 9 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+Rl 4 0 50
+*
+* The Following Dummy Resistors May Be Required For Spice.
+*
+Rstb2 5 0 5E+09
+Rstb3 6 0 5E+09
+Rseg4 3 0 5E+09
+Rstb5 7 0 5E+09
+Rstb6 8 0 5E+09
+Rstb7 9 0 5E+09
+Rstb8 10 0 5E+09
+*
+* End Dummy Resistors
+*
+*
+.AC DEC 200 2E+08 5E+09
+.PLOT AC VDB(Rl) -70 0
+.PLOT AC VP(Rl) -200 200
+.PLOT AC VG(Rl) -1E-08 2E-09
+.TRAN  5E-11 1E-08 0
+.PLOT TRAN V(Rl) -0.1 0.6
+.END
diff --git a/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/inductor_rs_1.ckt b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/inductor_rs_1.ckt
new file mode 100644
index 00000000000..982129e7efa
--- /dev/null
+++ b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/inductor_rs_1.ckt
@@ -0,0 +1,32 @@
+*
+*Length Units: Meters
+*
+V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0
+Rg 1 2 50
+MT1S1 2 5 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MTSeg0 2 3 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MT1S2 3 7 Wid=0.00508 Len=0.01008 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MTSeg1 3 4 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MT1S3 4 9 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+Rl 4 0 50
+*
+* The Following Dummy Resistors May Be Required For Spice.
+*
+Rstb2 5 0 5E+09
+Rstb3 6 0 5E+09
+Rseg4 3 0 5E+09
+Rstb5 7 0 5E+09
+Rstb6 8 0 5E+09
+Rstb7 9 0 5E+09
+Rstb8 10 0 5E+09
+*
+* End Dummy Resistors
+*
+*
+.AC DEC 200 2E+08 5E+09
+.PLOT AC VDB(Rl) -70 0
+.PLOT AC VP(Rl) -200 200
+.PLOT AC VG(Rl) -1E-08 2E-09
+.TRAN  5E-11 1E-08 0
+.PLOT TRAN V(Rl) -0.1 0.6
+.END
diff --git a/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/line_even_conductance_1.ckt b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/line_even_conductance_1.ckt
new file mode 100644
index 00000000000..982129e7efa
--- /dev/null
+++ b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/line_even_conductance_1.ckt
@@ -0,0 +1,32 @@
+*
+*Length Units: Meters
+*
+V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0
+Rg 1 2 50
+MT1S1 2 5 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MTSeg0 2 3 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MT1S2 3 7 Wid=0.00508 Len=0.01008 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MTSeg1 3 4 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MT1S3 4 9 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+Rl 4 0 50
+*
+* The Following Dummy Resistors May Be Required For Spice.
+*
+Rstb2 5 0 5E+09
+Rstb3 6 0 5E+09
+Rseg4 3 0 5E+09
+Rstb5 7 0 5E+09
+Rstb6 8 0 5E+09
+Rstb7 9 0 5E+09
+Rstb8 10 0 5E+09
+*
+* End Dummy Resistors
+*
+*
+.AC DEC 200 2E+08 5E+09
+.PLOT AC VDB(Rl) -70 0
+.PLOT AC VP(Rl) -200 200
+.PLOT AC VG(Rl) -1E-08 2E-09
+.TRAN  5E-11 1E-08 0
+.PLOT TRAN V(Rl) -0.1 0.6
+.END
diff --git a/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/line_even_resistance_1.ckt b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/line_even_resistance_1.ckt
new file mode 100644
index 00000000000..982129e7efa
--- /dev/null
+++ b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/line_even_resistance_1.ckt
@@ -0,0 +1,32 @@
+*
+*Length Units: Meters
+*
+V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0
+Rg 1 2 50
+MT1S1 2 5 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MTSeg0 2 3 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MT1S2 3 7 Wid=0.00508 Len=0.01008 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MTSeg1 3 4 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MT1S3 4 9 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+Rl 4 0 50
+*
+* The Following Dummy Resistors May Be Required For Spice.
+*
+Rstb2 5 0 5E+09
+Rstb3 6 0 5E+09
+Rseg4 3 0 5E+09
+Rstb5 7 0 5E+09
+Rstb6 8 0 5E+09
+Rstb7 9 0 5E+09
+Rstb8 10 0 5E+09
+*
+* End Dummy Resistors
+*
+*
+.AC DEC 200 2E+08 5E+09
+.PLOT AC VDB(Rl) -70 0
+.PLOT AC VP(Rl) -200 200
+.PLOT AC VG(Rl) -1E-08 2E-09
+.TRAN  5E-11 1E-08 0
+.PLOT TRAN V(Rl) -0.1 0.6
+.END
diff --git a/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/line_min_segment_lengths_1.ckt b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/line_min_segment_lengths_1.ckt
new file mode 100644
index 00000000000..982129e7efa
--- /dev/null
+++ b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/line_min_segment_lengths_1.ckt
@@ -0,0 +1,32 @@
+*
+*Length Units: Meters
+*
+V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0
+Rg 1 2 50
+MT1S1 2 5 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MTSeg0 2 3 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MT1S2 3 7 Wid=0.00508 Len=0.01008 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MTSeg1 3 4 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MT1S3 4 9 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+Rl 4 0 50
+*
+* The Following Dummy Resistors May Be Required For Spice.
+*
+Rstb2 5 0 5E+09
+Rstb3 6 0 5E+09
+Rseg4 3 0 5E+09
+Rstb5 7 0 5E+09
+Rstb6 8 0 5E+09
+Rstb7 9 0 5E+09
+Rstb8 10 0 5E+09
+*
+* End Dummy Resistors
+*
+*
+.AC DEC 200 2E+08 5E+09
+.PLOT AC VDB(Rl) -70 0
+.PLOT AC VP(Rl) -200 200
+.PLOT AC VG(Rl) -1E-08 2E-09
+.TRAN  5E-11 1E-08 0
+.PLOT TRAN V(Rl) -0.1 0.6
+.END
diff --git a/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/line_odd_conductance_1.ckt b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/line_odd_conductance_1.ckt
new file mode 100644
index 00000000000..982129e7efa
--- /dev/null
+++ b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/line_odd_conductance_1.ckt
@@ -0,0 +1,32 @@
+*
+*Length Units: Meters
+*
+V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0
+Rg 1 2 50
+MT1S1 2 5 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MTSeg0 2 3 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MT1S2 3 7 Wid=0.00508 Len=0.01008 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MTSeg1 3 4 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MT1S3 4 9 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+Rl 4 0 50
+*
+* The Following Dummy Resistors May Be Required For Spice.
+*
+Rstb2 5 0 5E+09
+Rstb3 6 0 5E+09
+Rseg4 3 0 5E+09
+Rstb5 7 0 5E+09
+Rstb6 8 0 5E+09
+Rstb7 9 0 5E+09
+Rstb8 10 0 5E+09
+*
+* End Dummy Resistors
+*
+*
+.AC DEC 200 2E+08 5E+09
+.PLOT AC VDB(Rl) -70 0
+.PLOT AC VP(Rl) -200 200
+.PLOT AC VG(Rl) -1E-08 2E-09
+.TRAN  5E-11 1E-08 0
+.PLOT TRAN V(Rl) -0.1 0.6
+.END
diff --git a/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/line_odd_resistance_1.ckt b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/line_odd_resistance_1.ckt
new file mode 100644
index 00000000000..982129e7efa
--- /dev/null
+++ b/tests/system/solvers/test_45_FilterSolutions/resources/Distributed/line_odd_resistance_1.ckt
@@ -0,0 +1,32 @@
+*
+*Length Units: Meters
+*
+V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0
+Rg 1 2 50
+MT1S1 2 5 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MTSeg0 2 3 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MT1S2 3 7 Wid=0.00508 Len=0.01008 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MTSeg1 3 4 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+MT1S3 4 9 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005
+Rl 4 0 50
+*
+* The Following Dummy Resistors May Be Required For Spice.
+*
+Rstb2 5 0 5E+09
+Rstb3 6 0 5E+09
+Rseg4 3 0 5E+09
+Rstb5 7 0 5E+09
+Rstb6 8 0 5E+09
+Rstb7 9 0 5E+09
+Rstb8 10 0 5E+09
+*
+* End Dummy Resistors
+*
+*
+.AC DEC 200 2E+08 5E+09
+.PLOT AC VDB(Rl) -70 0
+.PLOT AC VP(Rl) -200 200
+.PLOT AC VG(Rl) -1E-08 2E-09
+.TRAN  5E-11 1E-08 0
+.PLOT TRAN V(Rl) -0.1 0.6
+.END
diff --git a/tests/system/solvers/test_45_FilterSolutions/test_distributed_filter/test_distributed_parasitics.py b/tests/system/solvers/test_45_FilterSolutions/test_distributed_filter/test_distributed_parasitics.py
new file mode 100644
index 00000000000..0eefd3317c6
--- /dev/null
+++ b/tests/system/solvers/test_45_FilterSolutions/test_distributed_filter/test_distributed_parasitics.py
@@ -0,0 +1,141 @@
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates.
+# SPDX-License-Identifier: MIT
+#
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in all
+# copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+from ansys.aedt.core.filtersolutions_core.distributed_topology import TopologyType
+from ansys.aedt.core.generic.general_methods import is_linux
+import pytest
+
+from tests.system.general.conftest import config
+
+from ..resources import read_resource_file
+
+
+@pytest.mark.skipif(is_linux, reason="FilterSolutions API is not applicable on Linux.")
+@pytest.mark.skipif(config["desktopVersion"] < "2025.2", reason="Skipped on versions earlier than 2025.2")
+class TestClass:
+
+    def test_distributed_capacitor_q_100(self, distributed_design):
+        distributed_design.topology.topology_type = TopologyType.INDUCTOR_TRANSLATION
+        assert distributed_design.parasitics.capacitor_q == "Inf"
+        distributed_design.parasitics.capacitor_q = "100"
+        assert distributed_design.parasitics.capacitor_q == "100"
+        assert distributed_design.topology.netlist().splitlines() == read_resource_file(
+            "capacitor_q_100.ckt", "Distributed"
+        )
+
+    def test_distributed_capacitor_rs_1(self, distributed_design):
+        assert distributed_design.parasitics.capacitor_rs == "0"
+        distributed_design.parasitics.capacitor_rs = "1"
+        assert distributed_design.parasitics.capacitor_rs == "1"
+        assert distributed_design.topology.netlist().splitlines() == read_resource_file(
+            "capacitor_rs_1.ckt", "Distributed"
+        )
+
+    def test_distributed_capacitor_rp_1000(self, distributed_design):
+        assert distributed_design.parasitics.capacitor_rp == "Inf"
+        distributed_design.parasitics.capacitor_rp = "1000"
+        assert distributed_design.parasitics.capacitor_rp == "1000"
+        assert distributed_design.topology.netlist().splitlines() == read_resource_file(
+            "capacitor_rp_1000.ckt", "Distributed"
+        )
+
+    def test_distributed_capacitor_ls_1n(self, distributed_design):
+        assert distributed_design.parasitics.capacitor_ls == "0"
+        distributed_design.parasitics.capacitor_ls = "1n"
+        assert distributed_design.parasitics.capacitor_ls == "1n"
+        assert distributed_design.topology.netlist().splitlines() == read_resource_file(
+            "capacitor_ls_1n.ckt", "Distributed"
+        )
+
+    def test_distributed_inductor_q_100(self, distributed_design):
+        assert distributed_design.parasitics.inductor_q == "Inf"
+        distributed_design.parasitics.inductor_q = "100"
+        assert distributed_design.parasitics.inductor_q == "100"
+        assert distributed_design.topology.netlist().splitlines() == read_resource_file(
+            "inductor_q_100.ckt", "Distributed"
+        )
+
+    def test_distributed_inductor_rs_1(self, distributed_design):
+        assert distributed_design.parasitics.inductor_rs == "0"
+        distributed_design.parasitics.inductor_rs = "1"
+        assert distributed_design.parasitics.inductor_rs == "1"
+        assert distributed_design.topology.netlist().splitlines() == read_resource_file(
+            "inductor_rs_1.ckt", "Distributed"
+        )
+
+    def test_distributed_inductor_rp_1000(self, distributed_design):
+        assert distributed_design.parasitics.inductor_rp == "Inf"
+        distributed_design.parasitics.inductor_rp = "1000"
+        assert distributed_design.parasitics.inductor_rp == "1000"
+        assert distributed_design.topology.netlist().splitlines() == read_resource_file(
+            "inductor_rp_1000.ckt", "Distributed"
+        )
+
+    def test_distributed_inductor_cp_1n(self, distributed_design):
+        assert distributed_design.parasitics.inductor_cp == "0"
+        distributed_design.parasitics.inductor_cp = "1n"
+        assert distributed_design.parasitics.inductor_cp == "1n"
+        assert distributed_design.topology.netlist().splitlines() == read_resource_file(
+            "inductor_cp_1n.ckt", "Distributed"
+        )
+
+    def test_line_odd_resistance_1(self, distributed_design):
+        assert distributed_design.parasitics.line_odd_resistance == "0"
+        distributed_design.parasitics.line_odd_resistance = "1"
+        assert distributed_design.parasitics.line_odd_resistance == "1"
+        assert distributed_design.topology.netlist().splitlines() == read_resource_file(
+            "line_odd_resistance_1.ckt", "Distributed"
+        )
+
+    def test_line_even_resistance_1(self, distributed_design):
+        assert distributed_design.parasitics.line_even_resistance == "0"
+        distributed_design.parasitics.line_even_resistance = "1"
+        assert distributed_design.parasitics.line_even_resistance == "1"
+        assert distributed_design.topology.netlist().splitlines() == read_resource_file(
+            "line_even_resistance_1.ckt", "Distributed"
+        )
+
+    def test_line_odd_conductance_1(self, distributed_design):
+        assert distributed_design.parasitics.line_odd_conductance == "0"
+        distributed_design.parasitics.line_odd_conductance = "1"
+        assert distributed_design.parasitics.line_odd_conductance == "1"
+        assert distributed_design.topology.netlist().splitlines() == read_resource_file(
+            "line_odd_conductance_1.ckt", "Distributed"
+        )
+
+    def test_line_even_conductance_1(self, distributed_design):
+        assert distributed_design.parasitics.line_even_conductance == "0"
+        distributed_design.parasitics.line_even_conductance = "1"
+        assert distributed_design.parasitics.line_even_conductance == "1"
+        assert distributed_design.topology.netlist().splitlines() == read_resource_file(
+            "line_even_conductance_1.ckt", "Distributed"
+        )
+
+    def test_line_min_segment_lengths_1(self, distributed_design):
+        assert distributed_design.parasitics.line_min_segment_lengths == "0"
+        distributed_design.parasitics.line_min_segment_lengths = "1"
+        assert distributed_design.parasitics.line_min_segment_lengths == "1"
+        assert distributed_design.topology.netlist().splitlines() == read_resource_file(
+            "line_min_segment_lengths_1.ckt", "Distributed"
+        )