diff --git a/docs/source/data_center_rdimm_ddr4_tester.md b/docs/source/data_center_rdimm_ddr4_tester.md new file mode 100644 index 000000000..e59cc5ba7 --- /dev/null +++ b/docs/source/data_center_rdimm_ddr4_tester.md @@ -0,0 +1,82 @@ +# Data Center RDIMM DDR4 Tester + +```{image} images/data-center-rdimm-ddr4-tester-1.2.0.png +``` + +The Data Center RDIMM DDR4 Tester is an open source hardware test platform that enables testing and experimenting with various DDR4 RDIMMs (Registered Dual In-Line Memory Module). + +The hardware is open and can be found on GitHub: + + +The following instructions explain how to set up the board. + +## IO map +A map of on-board connectors, status LEDs, control buttons and I/O interfaces is provided below. + +:::{figure-md} +![](images/data-center-rdimm-ddr4-tester-descriptions.png) + +DDR4 data center dram tester interface map +::: + +Connectors: +* [`J3`](#data-center-dram-tester_J3) - main DC barrel jack power connector, voltage between 7-15V is supported +* [`J9`](#data-center-dram-tester_J9) - USB-C debug connector used for programming FPGA or Flash memory +* [`J1`](#data-center-dram-tester_J1) - standard 14-pin JTAG connector used for programming FPGA or Flash memory +* [`J6`](#data-center-dram-tester_J6) - HDMI connector +* [`J2`](#data-center-dram-tester_J2) - Ethernet connector used for data exchange with on-board FPGA and power supply via PoE +* [`U14`](#data-center-dram-tester_U14) - 288-pin RDIMM connector for connecting DDR4 memory modules +* [`J8`](#data-center-dram-tester_J8) - optional 5V fan connector +* [`J7`](#data-center-dram-tester_J7) - socket for SD card +* [`J5`](#data-center-dram-tester_J5) - FMC HPC connector reserved for future use + +Switches and buttons: +* Power ON/OFF button [`S3`](#data-center-dram-tester_S3) - push button to power up a device, hold for 8s to turn the device off +* FPGA programming button [`PROG_B1`](#data-center-dram-tester_PROG_B1) - push button to start programming from Flash +* Configuration mode selector [`S2`](#data-center-dram-tester_S2) - Swipe left/right to specify SPI/JTAG programming mode +* HOT SWAP eject button [`S1`](#data-center-dram-tester_S1) - reserved for future use to turn off a DDR memory and allow hot swapping it + +LEDs: +* 3V3 Power indicator [`PWR1`](#data-center-dram-tester_PWR1) - indicates presence of stabilized 3.3V voltage +* PoE indicator [`D15`](#data-center-dram-tester_D15) - indicates negotiated PoE voltage supply +* FPGA programming INIT [`D10`](#data-center-dram-tester_D10) - indicates current FPGA configuration state +* FPGA programming DONE [`D1`](#data-center-dram-tester_D1) - indicates completion of FPGA programming +* HOT SWAP status [`D17`](#data-center-dram-tester_D17) - RGY LED indicating status of hot swap process +* 5x User ([`D5`](#data-center-dram-tester_D5), [`D6`](#data-center-dram-tester_D6), [`D7`](#data-center-dram-tester_D7), [`D8`](#data-center-dram-tester_D8), [`D9`](#data-center-dram-tester_D9)) - LEDs for user's definition + +## Board configuration + +Connect power supply (7-15VDC) to [`J3`](#data-center-dram-tester_J3) barrel jack. Then connect the board USB cable ([`J9`](#data-center-dram-tester_J9)) and Ethernet cable ([`J2`](#data-center-dram-tester_J2)) to your computer and insert the memory module to the socket [`U14`](#data-center-dram-tester_U14). +To turn the board on, use power switch [`S3`](#data-center-dram-tester_S3). + +After power is up, configure the network. The board's IP address will be `192.168.100.50` (so you could e.g. use `192.168.100.2/24`). The `IP_ADDRESS` environment variable can be used to modify the board's address. + +Next, generate the FPGA bitstream: + +```sh +export TARGET=ddr4_datacenter_test_board +make build +``` + +```{note} +By typing `make` (without `build`) LiteX will generate build files without invoking Vivado. +``` + +The results will be located in: `build/ddr4_datacenter_test_board/gateware/antmicro_datacenter_ddr4_test_board.bit`. To upload it, use: + +```sh +export TARGET=ddr4_datacenter_test_board +make upload +``` + +To save bitstream in flash memory, use: + +```sh +export TARGET=ddr4_datacenter_test_board +make flash +``` + +There is a JTAG/SPI switch [`S2`](#data-center-rdimm-ddr4-tester_S2) on the right side of the board, near JTAG connector. +It defines whether the bitstream will be loaded via JTAG or SPI Flash memory. + +Bitstream will be loaded from flash memory upon device power-on or after a [`PROG_B1`](#data-center-dram-tester_PROG_B1) button press. diff --git a/docs/source/ddr5_tester.md b/docs/source/data_center_rdimm_ddr5_tester.md similarity index 85% rename from docs/source/ddr5_tester.md rename to docs/source/data_center_rdimm_ddr5_tester.md index 0f349de3e..78c0747bd 100644 --- a/docs/source/ddr5_tester.md +++ b/docs/source/data_center_rdimm_ddr5_tester.md @@ -10,6 +10,38 @@ The hardware is open and can be found on GitHub: The following instructions explain how to set up the board. +## IO map +A map of on-board connectors, status LEDs, control buttons and I/O interfaces is provided below. + +:::{figure-md} +![](images/rdimm-ddr5-tester-descriptions.png) + +DDR5 tester interface map +::: + +Connectors: +* [`J1`](#ddr5-tester_J1) - main DC barrel jack power connector, voltage between 12-15V is supported +* [`J6`](#ddr5-tester_J6) - USB Micro-B debug connector used for programming FPGA or Flash memory +* [`J3`](#ddr5-tester_J3) - standard 14-pin JTAG connector used for programming FPGA or Flash memory +* [`J5`](#ddr5-tester_J5) - HDMI connector +* [`J4`](#ddr5-tester_J4) - Ethernet connector used for data exchange with on-board FPGA +* [`U12`](#ddr5-tester_U12) - 288-pin RDIMM connector for connecting DDR5 memory modules +* [`MODE1`](#ddr5-tester_MODE1) - configuration mode selector, short proper pins with jumper to specify programming mode +* [`J2`](#ddr5-tester_J2) - optional 5V fan connector +* [`J7`](#ddr5-tester_J7) - socket for SD card +* [`J8`](#ddr5-tester_J8) - 2.54mm goldpin connector with exposed I2C and I3C signals + +Switches and buttons: +* Power ON/OFF button [`S1`](#ddr5-tester_S1) - swipe up to power up a device, swipe down to turn the device off +* FPGA programming button [`PROG_B1`](#ddr5-tester_PROG_B1) - push button to start programming from Flash +* 4x User button ([`PROG_B2`](#ddr5-tester_PROG_B2), [`PROG_B3`](#ddr5-tester_PROG_B3), [`PROG_B4`](#ddr5-tester_PROG_B4), [`PROG_B5`](#ddr5-tester_PROG_B5)) - buttons for user's definition + +LEDs: +* 3V3 Power indicator [`PWR1`](#ddr5-tester_PWR1) - indicates presence of stabilized 3.3V voltage +* FPGA programming INIT [`D6`](#ddr5-tester_D6) - indicates current FPGA configuration state +* FPGA programming DONE [`D5`](#ddr5-tester_D5) - indicates completion of FPGA programming +* 5x User ([`D7`](#ddr5-tester_D7), [`D8`](#ddr5-tester_D8), [`D9`](#ddr5-tester_D9), [`D10`](#ddr5-tester_D10), [`D11`](#ddr5-tester_D11)) - LEDs for user's definition + ## Rowhammer Tester Target Configuration Connect power supply (12-15VDC) to [`J1`](#ddr5-tester_J1) barrel jack. Then connect the board USB cable ([`J6`](#ddr5-tester_J6)) and Ethernet cable ([`J4`](#ddr5-tester_J4)) to your computer and insert the memory module to the socket [`U12`](#ddr5-tester_U12). diff --git a/docs/source/ddr4_datacenter_dram_tester.md b/docs/source/ddr4_datacenter_dram_tester.md deleted file mode 100644 index 81d43e7f1..000000000 --- a/docs/source/ddr4_datacenter_dram_tester.md +++ /dev/null @@ -1,45 +0,0 @@ -# Data Center RDIMM DDR4 Tester - -```{image} images/data-center-rdimm-ddr4-tester-1.2.0.png -``` - -The Data Center RDIMM DDR4 Tester is an open source hardware test platform that enables testing and experimenting with various DDR4 RDIMMs (Registered Dual In-Line Memory Module). - -The hardware is open and can be found on GitHub: - - -The following instructions explain how to set up the board. - -## Board configuration - -Connect power supply (7-15VDC) to [`J3`](#data-center-dram-tester_J3) barrel jack. Then connect the board USB cable ([`J9`](#data-center-dram-tester_J9)) and Ethernet cable ([`J2`](#data-center-dram-tester_J2)) to your computer and insert the memory module to the socket [`U14`](#data-center-dram-tester_U14). -To turn the board on, use power switch [`S3`](#data-center-dram-tester_S3). - -After power is up, configure the network. The board's IP address will be `192.168.100.50` (so you could e.g. use `192.168.100.2/24`). The `IP_ADDRESS` environment variable can be used to modify the board's address. - -Next, generate the FPGA bitstream: - -```sh -export TARGET=ddr4_datacenter_test_board -make build -``` - -```{note} -By typing `make` (without `build`) LiteX will generate build files without invoking Vivado. -``` - -The results will be located in: `build/ddr4_datacenter_test_board/gateware/antmicro_datacenter_ddr4_test_board.bit`. To upload it, use: - -```sh -export TARGET=ddr4_datacenter_test_board -make upload -``` - -To save bitstream in flash memory, use: - -```sh -export TARGET=ddr4_datacenter_test_board -make flash -``` - -Bitstream will be loaded from flash memory upon device power-on or after a [`PROG_B1`](#data-center-dram-tester_PROG_B1) button press. diff --git a/docs/source/images/data-center-dram-tester/D1.png b/docs/source/images/data-center-dram-tester/D1.png new file mode 100644 index 000000000..24907c3c5 Binary files /dev/null and b/docs/source/images/data-center-dram-tester/D1.png differ diff --git a/docs/source/images/data-center-dram-tester/D10.png b/docs/source/images/data-center-dram-tester/D10.png new file mode 100644 index 000000000..1a9a60a2e Binary files /dev/null and b/docs/source/images/data-center-dram-tester/D10.png differ diff --git a/docs/source/images/data-center-dram-tester/D15.png b/docs/source/images/data-center-dram-tester/D15.png index f45836b34..db807061e 100644 Binary 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a/docs/source/index.md b/docs/source/index.md index 279d25eb4..3634d7036 100644 --- a/docs/source/index.md +++ b/docs/source/index.md @@ -15,11 +15,11 @@ dram_modules.md arty.md zcu104.md -lpddr4_tb.md -ddr5_test_board.md -ddr4_datacenter_dram_tester.md -ddr5_tester.md -sodimm_ddr5_tester.md +lpddr4_test_board.md +lpddr4_test_board_with_ddr5_testbed.md +data_center_rdimm_ddr4_tester.md +data_center_rdimm_ddr5_tester.md +so_dimm_ddr5_tester.md ``` ```{toctree} diff --git a/docs/source/lpddr4_tb.md b/docs/source/lpddr4_tb.md deleted file mode 100644 index 2d540c74c..000000000 --- a/docs/source/lpddr4_tb.md +++ /dev/null @@ -1,55 +0,0 @@ -# LPDDR4 Test Board - -```{image} images/lpddr4-test-board.jpg -``` - -LPDDR4 Test Board is a platform developed by Antmicro for testing LPDDR4 memory. -It uses Xilinx Kintex-7 FPGA (XC7K70T-FBG484) and by default includes a custom SO-DIMM module with Micron's MT53E256M16D1 LPDDR4 DRAM. - -The hardware is open and can be found on GitHub: - -- Test board: -- Testbed: - -## Board configuration - -First insert the LPDDR4 DRAM module into the socket [``](#lpddr4-test-board_) and make sure that jumpers are set in correct positions: - -- VDDQ switch ([`J7`](#lpddr4-test-board_J7)) should be set in position 1V1 -- [`MODE1`](#lpddr4-test-board_MODE1) switch should be set in position FLASH - -Connect power supply (7-15VDC) to [`J6`](#lpddr4-test-board_J6) barrel jack. -Then connect the board's USB-C [`J1`](#lpddr4-test-board_J1) and Ethernet [`J5`](#lpddr4-test-board_J5) interfaces to your computer. -Turn the board on using power switch [`S1`](#lpddr4-test-board_S1). -Then configure the network. The board's IP address will be `192.168.100.50` (so you could e.g. use `192.168.100.2/24`). The `IP_ADDRESS` environment variable can be used to modify the board's address. -Next, generate the FPGA bitstream: - -```sh -export TARGET=lpddr4_test_board -make build -``` - -The results will be located in: `build/lpddr4_test_board/gateware/antmicro_lpddr4_test_board.bit`. To upload it, use: - -```sh -export TARGET=lpddr4_test_board -make upload -``` - -```{note} -By typing `make` (without `build`) LiteX will generate build files without invoking Vivado. -``` - -To save bitstream in flash memory, use: - -```sh -export TARGET=lpddr4_test_board -make flash -``` - -```{warning} -There is a JTAG/FLASH jumper [`MODE1`](#lpddr4-test-board_MODE1) on the right side of the board. -Unless it's set to the FLASH setting, the FPGA will load the bitstream received via JTAG ([`J4`](#lpddr4-test-board_J4)). -``` - -Bitstream will be loaded from flash memory upon device power-on or after a PROG button ([`PROG_B1`](#lpddr4-test-board_PROG_B1)) press. diff --git a/docs/source/lpddr4_test_board.md b/docs/source/lpddr4_test_board.md new file mode 100644 index 000000000..1f5a28ebd --- /dev/null +++ b/docs/source/lpddr4_test_board.md @@ -0,0 +1,85 @@ +# LPDDR4 Test Board + +```{image} images/lpddr4-test-board.jpg +``` + +LPDDR4 Test Board is a platform developed by Antmicro for testing LPDDR4 memory. +It uses Xilinx Kintex-7 FPGA (XC7K70T-FBG484) and by default includes a custom SO-DIMM module with Micron's MT53E256M16D1 LPDDR4 DRAM. + +The hardware is open and can be found on GitHub: + +- Test board: +- Testbed: + +## IO map +A map of on-board connectors, status LEDs, control buttons and I/O interfaces is provided below. + +:::{figure-md} +![](images/lpddr4-test-board-descriptions.png) + +LPDDR4 test board interface map +::: + +Connectors: +* [`J6`](#lpddr4-test-board_J6) - main DC barrel jack power connector, voltage between 7-15V is supported +* [`J1`](#lpddr4-test-board_J1) - USB Micro-B debug connector used for programming FPGA or Flash memory +* [`J4`](#lpddr4-test-board_J4) - standard 14-pin JTAG connector used for programming FPGA or Flash memory +* [`J2`](#lpddr4-test-board_J2) - HDMI connector +* [`J5`](#lpddr4-test-board_J5) - Ethernet connector used for data exchange with on-board FPGA +* [`J9`](#lpddr4-test-board_J9) - 260-pin SO-DIMM connector for connecting LPDDR4 memory +* [`MODE1`](#lpddr4-test-board_MODE1) - configuration mode selector, short proper pins with jumper to specify programming mode +* [`J7`](#lpddr4-test-board_J7) - VDDQ selector used for specifying value of VDDQ voltage +* [`J8`](#lpddr4-test-board_J8) - optional 5V fan connector +* [`J3`](#lpddr4-test-board_J3) - socket for SD card + +Switches and buttons: +* Power switch [`S1`](#lpddr4-test-board_S1) - swipe up to power up a device, swipe down to turn the device off +* FPGA programming button [`PROG_B1`](#lpddr4-test-board_PROG_B1) - push to start programming from Flash +* 4x User button ([`USR_BTN1`](#lpddr4-test-board_USR_BTN1),[`USR_BTN2`](#lpddr4-test-board_USR_BTN2),[`USR_BTN3`](#lpddr4-test-board_USR_BTN3),[`USR_BTN4`](#lpddr4-test-board_USR_BTN4)) - buttons for user's definition + +LEDs: +* Power indicators ([`PWR1`](#lpddr4-test-board_PWR1), [`PWR2`](#lpddr4-test-board_PWR2), [`PWR3`](#lpddr4-test-board_PWR3), [`PWR4`](#lpddr4-test-board_PWR4), [`PWR5`](#lpddr4-test-board_PWR5), [`PWR6`](#lpddr4-test-board_PWR6)) - indicates presence of stabilized voltages: 5V, 3V3, 1V8, 1V2, 1V1, 1V0 +* FPGA programming INIT [`D9`](#lpddr4-test-board_D9) - indicates current FPGA configuration state +* FPGA programming DONE [`D8`](#lpddr4-test-board_D8) - indicates completion of FPGA programming +* 5x User ([`D1`](#lpddr4-test-board_D1), [`D2`](#lpddr4-test-board_D2), [`D3`](#lpddr4-test-board_D3), [`D5`](#lpddr4-test-board_D5), [`D6`](#lpddr4-test-board_D6)) - LEDs for user's definition + +## Board configuration + +First insert the LPDDR4 DRAM module into the socket [`J9`](#lpddr4-test-board_J9) and make sure that jumpers are set in correct positions: + +- VDDQ switch ([`J7`](#lpddr4-test-board_J7)) should be set in position 1V1 +- [`MODE1`](#lpddr4-test-board_MODE1) switch should be set in position FLASH + +Connect power supply (7-15VDC) to [`J6`](#lpddr4-test-board_J6) barrel jack. +Then connect the board's USB-C [`J1`](#lpddr4-test-board_J1) and Ethernet [`J5`](#lpddr4-test-board_J5) interfaces to your computer. +Turn the board on using power switch [`S1`](#lpddr4-test-board_S1). +Then configure the network. The board's IP address will be `192.168.100.50` (so you could e.g. use `192.168.100.2/24`). The `IP_ADDRESS` environment variable can be used to modify the board's address. +Next, generate the FPGA bitstream: + +```sh +export TARGET=lpddr4_test_board +make build +``` + +The results will be located in: `build/lpddr4_test_board/gateware/antmicro_lpddr4_test_board.bit`. To upload it, use: + +```sh +export TARGET=lpddr4_test_board +make upload +``` + +```{note} +By typing `make` (without `build`) LiteX will generate build files without invoking Vivado. +``` + +To save bitstream in flash memory, use: + +```sh +export TARGET=lpddr4_test_board +make flash +``` + +There is a JTAG/FLASH jumper [`MODE1`](#lpddr4-test-board_MODE1) on the right side of the board. +It defines whether the bitstream will be loaded via JTAG or FLASH memory. + +Bitstream will be loaded from flash memory upon device power-on or after a FPGA programming button ([`PROG_B1`](#lpddr4-test-board_PROG_B1)) press. diff --git a/docs/source/ddr5_test_board.md b/docs/source/lpddr4_test_board_with_ddr5_testbed.md similarity index 100% rename from docs/source/ddr5_test_board.md rename to docs/source/lpddr4_test_board_with_ddr5_testbed.md diff --git a/docs/source/references.md b/docs/source/references.md index e4a862a5d..4206f0fa9 100644 --- a/docs/source/references.md +++ b/docs/source/references.md @@ -1,5 +1,14 @@ # Image references +```{image} images/data-center-dram-tester/PWR1.png +:name: data-center-dram-tester_PWR1 +``` +```{image} images/data-center-dram-tester/D1.png +:name: data-center-dram-tester_D1 +``` +```{image} images/data-center-dram-tester/D10.png +:name: data-center-dram-tester_D10 +``` ```{image} images/data-center-dram-tester/D15.png :name: data-center-dram-tester_D15 ``` @@ -51,7 +60,7 @@ ```{image} images/data-center-dram-tester/S1.png :name: data-center-dram-tester_S1 ``` -```{image} images/data-center-dram-tester/S3.png +```{image} images/data-center-dram-tester/S2.png :name: data-center-dram-tester_S2 ``` ```{image} images/data-center-dram-tester/S3.png diff --git a/docs/source/so_dimm_ddr5_tester.md b/docs/source/so_dimm_ddr5_tester.md new file mode 100644 index 000000000..85ac756cb --- /dev/null +++ b/docs/source/so_dimm_ddr5_tester.md @@ -0,0 +1,116 @@ +# SO-DIMM DDR5 Tester + +```{image} images/sodimm-ddr5-tester.png +``` + +The SO-DIMM DDR5 tester is an open source hardware test platform that enables testing and experimenting with various DDR5 SO-DIMM modules and Antmicro LPDDR5 testbed. + +The hardware is open and can be found on GitHub: + + +## IO map +A map of on-board connectors, status LEDs, control buttons and I/O interfaces is provided below. + +:::{figure-md} +![](images/sodimm-ddr5-tester-descriptions.png) + +SO-DIMM DDR5 tester interface map +::: + +Connectors: +* [`J7`](#sodimm-ddr5-tester_J7) - main DC barrel jack power connector, voltage between 7-15V is supported +* [`J3`](#sodimm-ddr5-tester_J3) - USB-C debug connector used for programming FPGA or Flash memory +* [`J1`](#sodimm-ddr5-tester_J1) - standard 14-pin JTAG connector used for programming FPGA or Flash memory +* [`J4`](#sodimm-ddr5-tester_J4) - HDMI connector +* [`J6`](#sodimm-ddr5-tester_J6) - Ethernet connector used for data exchange with on-board FPGA +* [`J2`](#sodimm-ddr5-tester_J2) - 262-pin SO-DIMM connector for connecting DDR5 memory modules +* [`J8`](#sodimm-ddr5-tester_J8) - optional 5V fan connector +* [`J5`](#sodimm-ddr5-tester_J5) - socket for SD card + +Switches and buttons: +* Power button [`SW5`](#sodimm-ddr5-tester_SW5) - push button to power up the device, push button again to turn the device off +* Configuration mode selector [`SW1`](#sodimm-ddr5-tester_SW1) - switch proper slides to specify programming mode (options described later) +* FPGA programming button [`SW2`](#sodimm-ddr5-tester_SW2) - push button to start programming from Flash +* PCIe present selector [`SW6`](#sodimm-ddr5-tester_SW6) - switch slide do set PCIe present to X1 and X4 +* HOT SWAP eject button [`SW3`](#sodimm-ddr5-tester_SW3) - reserved for future use to turn off a DDR memory and allow hot swapping it +* Config switch [`SW4`](#sodimm-ddr5-tester_SW4) - switch for setting several configuration options (options described later) + +LEDs: +* 3V3 Power indicator [`D1`](#sodimm-ddr5-tester_D1) - indicates presence of stabilized 3.3V voltage +* FPGA programming INIT [`D3`](#sodimm-ddr5-tester_D3) - indicates current FPGA configuration state +* FPGA programming DONE [`D2`](#sodimm-ddr5-tester_D2) - indicates completion of FPGA programming +* 5x User ([`D4`](#sodimm-ddr5-tester_D4), [`D5`](#sodimm-ddr5-tester_D5), [`D6`](#sodimm-ddr5-tester_D6), [`D7`](#sodimm-ddr5-tester_D7), [`D8`](#sodimm-ddr5-tester_D8)) - LEDs for user's definition +* HOT SWAP status [`D9`](#sodimm-ddr5-tester_D9) - RGY LED indicating status of hot swap process +* UART0 and UART1 status ([`D10`](#sodimm-ddr5-tester_D10), [`D11`](#sodimm-ddr5-tester_D11), [`D12`](#sodimm-ddr5-tester_D12), [`D13`](#sodimm-ddr5-tester_D13)) - indicates status of RX/TX lines of UART protocols + +## Rowhammer Tester Target Configuration + +The following instructions explain how to set up the board. + +Set configuration mode selectors [`SW1`](#sodimm-ddr5-tester_SW1) in proper positions. Based on those 3 switches user can set modes: +| Configuration mode | MODE[2] | MODE[1] | MODE[0] | +|--------------------|---------|---------|---------| +| Master Serial | 0 | 0 | 0 | +| Master SPI | 0 | 0 | 1 | +| Master BPI | 0 | 1 | 0 | +| Master SelectMAP | 1 | 0 | 0 | +| JTAG | 1 | 0 | 1 | +| Slave SelectMAP | 1 | 1 | 0 | +| Slave Serial | 1 | 1 | 1 | + +For JTAG programming set ```JTAG``` mode. If the bitstream needs to be loaded from the Flash memory, select ```Master SPI``` mode. This configuration is set by default. +Bitstream will be loaded from flash memory upon device power-on or after a [`SW2`](#sodimm-ddr5-tester_SW2) button press. + +Set config switch [`SW4`](#sodimm-ddr5-tester_SW4) in proper positions. Possible options: +* PB- CTRL - automatically turn on board or use power button [`SW5`](#sodimm-ddr5-tester_SW5) +* INSTANT OFF - pushing power button [`SW5`](#sodimm-ddr5-tester_SW5) will turn off device instantly or after 8s +* I2C MUX IN1 - configure switch of I2C on board (described below) +* I2C MUX IN2 - configure switch of I2C on board (described below) +* PWR I2C SDA - disable I2C in 3V3 powered IC's +* PWR I2C SCL - disable I2C in 3V3 powered IC's +* QDCDC2 I2C - enable I2C in main DCDC converter +* FTDI JTAG OFF - disable on-board FTDI which communicates with FPGA and Flash memory via JTAG + +Configure power up of I2C on board: +| PWR I2C | IN1 | IN2 | +| ------- | --- | --- | +| OFF | L | L | +| FPGA DDR I2C | H | L | +| FPGA PWR I2C | L | H | +| FTDI | H | H | + +Connect power supply (7-15VDC) to [`J7`](#sodimm-ddr5-tester_J7) barrel jack. +Then connect the board's USB-C [`J3`](#sodimm-ddr5-tester_J3) and Ethernet [`J6`](#sodimm-ddr5-tester_J6) interfaces to your computer, insert the memory module into the [`J2`](#sodimm-ddr5-tester_J2) socket and turn it on using power switch [`SW5`](#sodimm-ddr5-tester_SW5). Then configure the network. The board's IP address will be `192.168.100.50` (you can use `192.168.100.2/24`). The `IP_ADDRESS` environment variable can be used to modify the board's address. +Next, generate the FPGA bitstream: + +```sh +export TARGET=sodimm_ddr5_tester +make build TARGET_ARGS="--l2-size 256 --build --iodelay-clk-freq 400e6 --bios-lto --rw-bios --no-sdram-hw-test" +``` + +```{note} +--l2-size 256 sets L2 cache size to 256 bytes + +--no-sdram-hw-test disables hw accelerated memory test +``` + +```{note} +By typing `make` (without `build`) LiteX will generate build files without invoking Vivado. +``` + +The results will be located in: `build/sodimm_ddr5_tester/gateware/antmicro_sodimm_ddr5_tester.bit`. To upload it, use: + +```sh +export TARGET=sodimm_ddr5_tester +make upload +``` + +To save bitstream in flash memory, use: + +```sh +export TARGET=sodimm_ddr5_tester +make flash +``` + + + diff --git a/docs/source/sodimm_ddr5_tester.md b/docs/source/sodimm_ddr5_tester.md deleted file mode 100644 index ffa148aea..000000000 --- a/docs/source/sodimm_ddr5_tester.md +++ /dev/null @@ -1,65 +0,0 @@ -# SO-DIMM DDR5 Tester - -```{image} images/sodimm-ddr5-tester.png -``` - -The SO-DIMM DDR5 tester is an open source hardware test platform that enables testing and experimenting with various DDR5 SO-DIMM modules and Antmicro LPDDR5 testbed. - -The hardware is open and can be found on GitHub: - - -## Rowhammer Tester Target Configuration - -The following instructions explain how to set up the board. - -Connect power supply (7-15VDC) to [`J7`](#sodimm-ddr5-tester_J7) barrel jack. -Then connect the board's USB-C [`J3`](#sodimm-ddr5-tester_J3) and Ethernet [`J6`](#sodimm-ddr5-tester_J6) interfaces to your computer, insert the memory module into the [`J2`](#sodimm-ddr5-tester_J2) socket and turn it on using power switch [`SW5`](#sodimm-ddr5-tester_SW5). Then configure the network. The board's IP address will be `192.168.100.50` (you can use `192.168.100.2/24`). The `IP_ADDRESS` environment variable can be used to modify the board's address. -Next, generate the FPGA bitstream: - -```sh -export TARGET=sodimm_ddr5_tester -make build TARGET_ARGS="--l2-size 256 --build --iodelay-clk-freq 400e6 --bios-lto --rw-bios --no-sdram-hw-test" -``` - -```{note} ---l2-size 256 sets L2 cache size to 256 bytes - ---no-sdram-hw-test disables hw accelerated memory test -``` - -```{note} -By typing `make` (without `build`) LiteX will generate build files without invoking Vivado. -``` - -The results will be located in: `build/sodimm_ddr5_tester/gateware/antmicro_sodimm_ddr5_tester.bit`. To upload it, use: - -```sh -export TARGET=sodimm_ddr5_tester -make upload -``` - -To save bitstream in flash memory, use: - -```sh -export TARGET=sodimm_ddr5_tester -make flash -``` - -```{warning} -There is a [`SW1`](#sodimm-ddr5-tester_SW1) selector to the right of the FPGA ([`U4`](#sodimm-ddr5-tester_U4)). -If the bitstream needs to be loaded from the Flash memory, select ```Master SPI``` mode. This configuration is set by default. - -| Configuration mode | MODE[2] | MODE[1] | MODE[0] | -|--------------------|---------|---------|---------| -| Master Serial | 0 | 0 | 0 | -| Master SPI | 0 | 0 | 1 | -| Master BPI | 0 | 1 | 0 | -| Master SelectMAP | 1 | 0 | 0 | -| JTAG | 1 | 0 | 1 | -| Slave SelectMAP | 1 | 1 | 0 | -| Slave Serial | 1 | 1 | 1 | - -Bitstream will be loaded from flash memory upon device power-on or after a [`SW2`](#sodimm-ddr5-tester_SW2) button press. -``` - -