From 55bdf048a84fdb58dd7856afd83cb5ad5f4c2ca0 Mon Sep 17 00:00:00 2001
From: Sebastian Holzapfel <me@sebholzapfel.com>
Date: Mon, 18 Mar 2024 08:18:27 +0100
Subject: [PATCH] add litex-sys library, fetch constants that svd2rust can't
 parse from svf from litex-sys instead

---
 .gitmodules                   |  3 +++
 firmware/deps/litex-sys       |  1 +
 firmware/litex-fw/Cargo.lock  | 51 ++++++++++++++++++++++++++++++-----
 firmware/litex-fw/Cargo.toml  |  1 +
 firmware/litex-fw/src/main.rs |  8 +++---
 5 files changed, 53 insertions(+), 11 deletions(-)
 create mode 160000 firmware/deps/litex-sys

diff --git a/.gitmodules b/.gitmodules
index c0fb05a..54ef6d8 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -46,3 +46,6 @@
 [submodule "deps/pythondata-cpu-vexriscv_smp"]
 	path = deps/pythondata-cpu-vexriscv_smp
 	url = https://github.com/litex-hub/pythondata-cpu-vexriscv_smp.git
+[submodule "firmware/deps/litex-sys"]
+	path = firmware/deps/litex-sys
+	url = git@github.com:schnommus/litex-sys.git
diff --git a/firmware/deps/litex-sys b/firmware/deps/litex-sys
new file mode 160000
index 0000000..a76b1a1
--- /dev/null
+++ b/firmware/deps/litex-sys
@@ -0,0 +1 @@
+Subproject commit a76b1a1a9d9d3f3bc95b43a0ccc484e63672175b
diff --git a/firmware/litex-fw/Cargo.lock b/firmware/litex-fw/Cargo.lock
index 02ddd40..74f3e8a 100644
--- a/firmware/litex-fw/Cargo.lock
+++ b/firmware/litex-fw/Cargo.lock
@@ -64,6 +64,29 @@ dependencies = [
  "which",
 ]
 
+[[package]]
+name = "bindgen"
+version = "0.69.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "a00dc851838a2120612785d195287475a3ac45514741da670b735818822129a0"
+dependencies = [
+ "bitflags 2.4.0",
+ "cexpr",
+ "clang-sys",
+ "itertools",
+ "lazy_static",
+ "lazycell",
+ "log",
+ "prettyplease",
+ "proc-macro2",
+ "quote",
+ "regex",
+ "rustc-hash",
+ "shlex",
+ "syn 2.0.32",
+ "which",
+]
+
 [[package]]
 name = "bit_field"
 version = "0.10.2"
@@ -96,12 +119,9 @@ checksum = "14c189c53d098945499cdfa7ecc63567cf3886b3332b312a5b4585d8d3a6a610"
 
 [[package]]
 name = "cc"
-version = "1.0.83"
+version = "1.0.90"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f1174fb0b6ec23863f8b971027804a42614e347eafb0a95bf0b12cdae21fc4d0"
-dependencies = [
- "libc",
-]
+checksum = "8cd6604a82acf3039f1144f54b8eb34e91ffba622051189e71b781822d5ee1f5"
 
 [[package]]
 name = "cexpr"
@@ -280,6 +300,15 @@ dependencies = [
  "windows-sys",
 ]
 
+[[package]]
+name = "itertools"
+version = "0.12.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "ba291022dbbd398a455acf126c1e341954079855bc60dfdda641363bd6922569"
+dependencies = [
+ "either",
+]
+
 [[package]]
 name = "lazy_static"
 version = "1.4.0"
@@ -319,11 +348,12 @@ name = "litex-fw"
 version = "0.1.0"
 dependencies = [
  "aligned-array",
- "bindgen",
+ "bindgen 0.68.1",
  "fixed",
  "heapless",
  "litex-hal",
  "litex-pac",
+ "litex-sys",
  "micromath",
  "panic-halt",
  "riscv 0.10.1 (git+https://github.com/rust-embedded/riscv?branch=master)",
@@ -349,6 +379,15 @@ dependencies = [
  "vcell",
 ]
 
+[[package]]
+name = "litex-sys"
+version = "0.1.0"
+dependencies = [
+ "bindgen 0.69.4",
+ "cc",
+ "glob",
+]
+
 [[package]]
 name = "lock_api"
 version = "0.4.10"
diff --git a/firmware/litex-fw/Cargo.toml b/firmware/litex-fw/Cargo.toml
index 2d27ddd..550b6f7 100644
--- a/firmware/litex-fw/Cargo.toml
+++ b/firmware/litex-fw/Cargo.toml
@@ -14,6 +14,7 @@ riscv-rt = "*"
 panic-halt = "*"
 litex-hal = { path = "../deps/rust-litex-hal" }
 litex-pac = { path = "../deps/generated-litex-pac", features = ["rt"] }
+litex-sys = { path = "../deps/litex-sys" }
 micromath = "2.0.0"
 heapless = { version = "0.7.16", default-features = false, features = ["ufmt-impl", "atomic-polyfill"] }
 ufmt = "0.2.0"
diff --git a/firmware/litex-fw/src/main.rs b/firmware/litex-fw/src/main.rs
index 500e820..928a690 100644
--- a/firmware/litex-fw/src/main.rs
+++ b/firmware/litex-fw/src/main.rs
@@ -21,6 +21,7 @@ use heapless::*;
 use litex_hal::prelude::*;
 use litex_hal::uart::UartError;
 use litex_pac as pac;
+use litex_sys;
 use riscv_rt::entry;
 use riscv;
 use core::arch::asm;
@@ -33,9 +34,6 @@ use log::*;
 use plic::*;
 use dsp::*;
 
-/// TODO: Modify `svd2rust` so this can be automatically forwarded?
-const SYSTEM_CLOCK_FREQUENCY: u32 = 75_000_000;
-
 /// Number of channels per section (4x input, 4x output)
 const N_CHANNELS: usize = 4;
 
@@ -66,7 +64,7 @@ static mut KARLSEN_LPF: Option<KarlsenLpf> = None;
 
 // Map the RISCV IRQ PLIC onto the fixed address present in the VexRISCV implementation.
 // TODO: ideally fetch this from the svf, its currently not exported by `svd2rust`!
-riscv::plic_context!(PLIC0, 0xf0c0_0000, 0, VexInterrupt, VexPriority);
+riscv::plic_context!(PLIC0, litex_sys::PLIC_BASE, 0, VexInterrupt, VexPriority);
 
 // Create the HAL bindings for the remaining LiteX peripherals.
 
@@ -180,7 +178,7 @@ fn main() -> ! {
     log::init(peripherals.UART);
     log::info!("hello from litex-fw!");
 
-    let mut timer = Timer::new(peripherals.TIMER0, SYSTEM_CLOCK_FREQUENCY);
+    let mut timer = Timer::new(peripherals.TIMER0, litex_sys::CONFIG_CLOCK_FREQUENCY);
 
     unsafe {
         // Create an instance of our DSP function which has some internal state.