From 1bd6dda198eb44f6f34f3646c628dc248e5699fe Mon Sep 17 00:00:00 2001 From: Stijn Tintel Date: Tue, 15 Oct 2024 00:23:36 +0300 Subject: [PATCH 01/32] qoriq: add missing kernel config symbol Dropping the source-only flag from qoriq and adding it to the buildbots exposed a missing kernel config symbol: CONFIG_DRM_OFDRM. Addd it as disabled to the qoriq kernel config, as the only device currently supported in the qoriq target does not have any display hardware. Reported-by: Mieczyslaw Nalewaj Signed-off-by: Stijn Tintel --- target/linux/qoriq/config-6.6 | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/qoriq/config-6.6 b/target/linux/qoriq/config-6.6 index 750e6c65510227..70edd18bd0d78b 100644 --- a/target/linux/qoriq/config-6.6 +++ b/target/linux/qoriq/config-6.6 @@ -103,6 +103,7 @@ CONFIG_DMA_ENGINE=y CONFIG_DMA_OF=y CONFIG_DMA_OPS=y CONFIG_DMA_OPS_BYPASS=y +# CONFIG_DRM_OFDRM is not set CONFIG_DTC=y CONFIG_DUMMY_CONSOLE=y # CONFIG_E5500_CPU is not set From 506d0c421b1b0df6adb75506b3b20622b264b15f Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Tue, 15 Oct 2024 10:21:47 +0200 Subject: [PATCH 02/32] kernel: fix mtk_eth_soc memory corruption issue on fq dma init Signed-off-by: Felix Fietkau --- ..._eth_soc-fix-memory-corruption-durin.patch | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 target/linux/generic/pending-6.6/735-net-ethernet-mtk_eth_soc-fix-memory-corruption-durin.patch diff --git a/target/linux/generic/pending-6.6/735-net-ethernet-mtk_eth_soc-fix-memory-corruption-durin.patch b/target/linux/generic/pending-6.6/735-net-ethernet-mtk_eth_soc-fix-memory-corruption-durin.patch new file mode 100644 index 00000000000000..5d7902b1cf796a --- /dev/null +++ b/target/linux/generic/pending-6.6/735-net-ethernet-mtk_eth_soc-fix-memory-corruption-durin.patch @@ -0,0 +1,24 @@ +From: Felix Fietkau +Date: Tue, 15 Oct 2024 10:13:55 +0200 +Subject: [PATCH] net: ethernet: mtk_eth_soc: fix memory corruption during fq + dma init + +The loop responsible for allocating up to MTK_FQ_DMA_LENGTH buffers must +only touch as many descriptors, otherwise it ends up corrupting unrelated +memory. Fix the loop iteration count accordingly. + +Fixes: c57e55819443 ("net: ethernet: mtk_eth_soc: handle dma buffer size soc specific") +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -1172,7 +1172,7 @@ static int mtk_init_fq_dma(struct mtk_et + if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) + return -ENOMEM; + +- for (i = 0; i < cnt; i++) { ++ for (i = 0; i < len; i++) { + struct mtk_tx_dma_v2 *txd; + + txd = eth->scratch_ring + (j * MTK_FQ_DMA_LENGTH + i) * soc->tx.desc_size; From 0a2ed285e4da0d8a58240e35036fa7501179689d Mon Sep 17 00:00:00 2001 From: Stijn Tintel Date: Tue, 15 Oct 2024 12:13:35 +0300 Subject: [PATCH 03/32] qoriq: add squashfs to FEATURES The snapshot builds for qoriq only contain ext4 images. Add squashfs to FEATURES to also have the buildbots build squashfs images. Signed-off-by: Stijn Tintel --- target/linux/qoriq/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/qoriq/Makefile b/target/linux/qoriq/Makefile index 782d2dc6466b3d..6320cdfeb0e4dd 100644 --- a/target/linux/qoriq/Makefile +++ b/target/linux/qoriq/Makefile @@ -8,7 +8,7 @@ ARCH:=powerpc64 BOARD:=qoriq BOARDNAME:=NXP QorIQ (PowerPC) CPU_TYPE:=e5500 -FEATURES:=boot-part ext4 fpu legacy-sdcard powerpc64 ramdisk rootfs-part rtc +FEATURES:=boot-part ext4 fpu legacy-sdcard powerpc64 ramdisk rootfs-part rtc squashfs SUBTARGETS:=generic KERNEL_PATCHVER:=6.6 From ee03a2742ba450409b9d82228064c08b1c35e800 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Fri, 11 Oct 2024 04:42:09 +0100 Subject: [PATCH 04/32] generic: net: phy: be more conservative about MAC interface selection Only add SerDes interface modes at lower speeds to host_interfaces. Fixes: 5281033831 ("generic: net: phy: use all SerDes MAC interface modes") Signed-off-by: Daniel Golle --- ...e-host_interfaces-when-attaching-PHY.patch | 33 +++++++++++++++---- 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/target/linux/generic/pending-6.6/706-net-phy-populate-host_interfaces-when-attaching-PHY.patch b/target/linux/generic/pending-6.6/706-net-phy-populate-host_interfaces-when-attaching-PHY.patch index bd2d015b179d1e..78e0049f05243f 100644 --- a/target/linux/generic/pending-6.6/706-net-phy-populate-host_interfaces-when-attaching-PHY.patch +++ b/target/linux/generic/pending-6.6/706-net-phy-populate-host_interfaces-when-attaching-PHY.patch @@ -1,4 +1,4 @@ -From 9e1a0d2006bc108b239b5bc00b42c2a8cc651217 Mon Sep 17 00:00:00 2001 +From 4e432e530db0056450fbc4a3cee793f16adc39a7 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 8 Oct 2024 23:58:41 +0100 Subject: [PATCH] net: phy: populate host_interfaces when attaching PHY @@ -15,18 +15,39 @@ full-duplex only. Signed-off-by: Daniel Golle --- - drivers/net/phy/phylink.c | 7 +++++++ - 1 file changed, 7 insertions(+) + drivers/net/phy/phylink.c | 21 ++++++++++++++++++++- + 1 file changed, 20 insertions(+), 1 deletion(-) --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c -@@ -2044,6 +2044,13 @@ int phylink_fwnode_phy_connect(struct ph +@@ -2017,7 +2017,7 @@ int phylink_fwnode_phy_connect(struct ph + { + struct fwnode_handle *phy_fwnode; + struct phy_device *phy_dev; +- int ret; ++ int i, ret; + + /* Fixed links and 802.3z are handled without needing a PHY */ + if (pl->cfg_link_an_mode == MLO_AN_FIXED || +@@ -2044,6 +2044,25 @@ int phylink_fwnode_phy_connect(struct ph pl->link_config.interface = pl->link_interface; } -+ /* Assume SerDes interface modes share the same lanes and allow -+ * the PHY to switch between them ++ /* Assume single-lane SerDes interface modes share the same ++ * lanes and allow the PHY to switch to slower also supported modes + */ ++ for (i = ARRAY_SIZE(phylink_sfp_interface_preference) - 1; i >= 0; i--) { ++ /* skip unsupported modes */ ++ if (!test_bit(phylink_sfp_interface_preference[i], pl->config->supported_interfaces)) ++ continue; ++ ++ __set_bit(phylink_sfp_interface_preference[i], phy_dev->host_interfaces); ++ ++ /* skip all faster modes */ ++ if (phylink_sfp_interface_preference[i] == pl->link_interface) ++ break; ++ } ++ + if (test_bit(pl->link_interface, phylink_sfp_interfaces)) + phy_interface_and(phy_dev->host_interfaces, phylink_sfp_interfaces, + pl->config->supported_interfaces); From 8cc049cec244eeeaf6b312e7e5776cdb822a5da2 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 15 Oct 2024 17:39:13 +0100 Subject: [PATCH 05/32] generic: phy: aquantia: move accepted patches to backport-6.6 Move patches accepted upstream from pending-6.6 to backport-6.6. Signed-off-by: Daniel Golle --- ...ia-allow-forcing-order-of-MDI-pairs.patch} | 11 ++++--- ...-fix-return-value-check-in-aqr107_co.patch | 31 +++++++++++++++++++ ...-applying-active_low-bit-after-reset.patch | 4 +-- 3 files changed, 40 insertions(+), 6 deletions(-) rename target/linux/generic/{pending-6.6/752-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch => backport-6.6/837-v6.13-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch} (89%) create mode 100644 target/linux/generic/backport-6.6/838-v6.13-net-phy-aquantia-fix-return-value-check-in-aqr107_co.patch diff --git a/target/linux/generic/pending-6.6/752-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch b/target/linux/generic/backport-6.6/837-v6.13-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch similarity index 89% rename from target/linux/generic/pending-6.6/752-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch rename to target/linux/generic/backport-6.6/837-v6.13-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch index f3ae893b32b99e..9522bcaa4518ff 100644 --- a/target/linux/generic/pending-6.6/752-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch +++ b/target/linux/generic/backport-6.6/837-v6.13-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch @@ -1,6 +1,6 @@ -From 49d46df79404a37685e0f32deb36506f5723e3a0 Mon Sep 17 00:00:00 2001 +From a2e1ba275eae96a8171deb19e9c7c2f5978fee7b Mon Sep 17 00:00:00 2001 From: Daniel Golle -Date: Wed, 28 Aug 2024 23:52:09 +0100 +Date: Fri, 4 Oct 2024 17:18:16 +0100 Subject: [PATCH] net: phy: aquantia: allow forcing order of MDI pairs Despite supporting Auto MDI-X, it looks like Aquantia only supports @@ -35,6 +35,9 @@ Forcing normal pair order is required on the Adtran SDG-8733A Wi-Fi 7 residential gateway. Signed-off-by: Daniel Golle +Reviewed-by: Andrew Lunn +Link: https://patch.msgid.link/9ed760ff87d5fc456f31e407ead548bbb754497d.1728058550.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski --- drivers/net/phy/aquantia/aquantia_main.c | 33 ++++++++++++++++++++++++ 1 file changed, 33 insertions(+) @@ -74,7 +77,7 @@ Signed-off-by: Daniel Golle + ret = of_property_read_u32(np, "marvell,mdi-cfg-order", &mdi_conf); + + /* Do nothing in case property "marvell,mdi-cfg-order" is not present */ -+ if (ret == -EINVAL) ++ if (ret == -ENOENT) + return 0; + + if (ret) @@ -101,4 +104,4 @@ Signed-off-by: Daniel Golle + /* Restore LED polarity state after reset */ for_each_set_bit(led_active_low, &priv->leds_active_low, AQR_MAX_LEDS) { - ret = aqr_phy_led_active_low_set(phydev, led_active_low, true); + ret = aqr_phy_led_active_low_set(phydev, index, led_active_low); diff --git a/target/linux/generic/backport-6.6/838-v6.13-net-phy-aquantia-fix-return-value-check-in-aqr107_co.patch b/target/linux/generic/backport-6.6/838-v6.13-net-phy-aquantia-fix-return-value-check-in-aqr107_co.patch new file mode 100644 index 00000000000000..73be78a0582ebc --- /dev/null +++ b/target/linux/generic/backport-6.6/838-v6.13-net-phy-aquantia-fix-return-value-check-in-aqr107_co.patch @@ -0,0 +1,31 @@ +From ce21b8fb255ebf0b49913fb4c62741d7eb05c6f6 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Fri, 11 Oct 2024 22:28:43 +0100 +Subject: [PATCH] net: phy: aquantia: fix return value check in + aqr107_config_mdi() + +of_property_read_u32() returns -EINVAL in case the property cannot be +found rather than -ENOENT. Fix the check to not abort probing in case +of the property being missing, and also in case CONFIG_OF is not set +which will result in -ENOSYS. + +Fixes: a2e1ba275eae ("net: phy: aquantia: allow forcing order of MDI pairs") +Reported-by: Jon Hunter +Closes: https://lore.kernel.org/all/114b4c03-5d16-42ed-945d-cf78eabea12b@nvidia.com/ +Suggested-by: Hans-Frieder Vogt +Signed-off-by: Daniel Golle +--- + drivers/net/phy/aquantia/aquantia_main.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/phy/aquantia/aquantia_main.c ++++ b/drivers/net/phy/aquantia/aquantia_main.c +@@ -512,7 +512,7 @@ static int aqr107_config_mdi(struct phy_ + ret = of_property_read_u32(np, "marvell,mdi-cfg-order", &mdi_conf); + + /* Do nothing in case property "marvell,mdi-cfg-order" is not present */ +- if (ret == -ENOENT) ++ if (ret == -EINVAL || ret == -ENOSYS) + return 0; + + if (ret) diff --git a/target/linux/generic/pending-6.6/751-net-phy-aquantia-fix-applying-active_low-bit-after-reset.patch b/target/linux/generic/pending-6.6/751-net-phy-aquantia-fix-applying-active_low-bit-after-reset.patch index 5c3494ae331631..6d71b3d7a52f80 100644 --- a/target/linux/generic/pending-6.6/751-net-phy-aquantia-fix-applying-active_low-bit-after-reset.patch +++ b/target/linux/generic/pending-6.6/751-net-phy-aquantia-fix-applying-active_low-bit-after-reset.patch @@ -49,7 +49,7 @@ Reviewed-by: Russell King (Oracle) --- a/drivers/net/phy/aquantia/aquantia_main.c +++ b/drivers/net/phy/aquantia/aquantia_main.c -@@ -501,7 +501,7 @@ static int aqr107_config_init(struct phy +@@ -530,7 +530,7 @@ static int aqr107_config_init(struct phy { struct aqr107_priv *priv = phydev->priv; u32 led_active_low; @@ -58,7 +58,7 @@ Reviewed-by: Russell King (Oracle) /* Check that the PHY interface type is compatible */ if (phydev->interface != PHY_INTERFACE_MODE_SGMII && -@@ -537,10 +537,9 @@ static int aqr107_config_init(struct phy +@@ -570,10 +570,9 @@ static int aqr107_config_init(struct phy /* Restore LED polarity state after reset */ for_each_set_bit(led_active_low, &priv->leds_active_low, AQR_MAX_LEDS) { From 45bad8ba984fdecbd12523b58c2962c1cd4704db Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 5 Oct 2024 22:19:43 +0100 Subject: [PATCH 06/32] generic: phy: aquantia: correctly describe LED polarity Backport newly introduced support for 'active-high' property and use it to correctly implement polarity assignment for Aquantia PHY LEDs. Previously the 'active-low' property was used to switch a LED PIN to active-high ("drive VDD" in Aquantia-speak) mode. Signed-off-by: Daniel Golle --- ...aquantia-fix-setting-active_low-bit.patch} | 0 ...applying-active_low-bit-after-reset.patch} | 0 ...rt-active-high-property-for-PHY-LEDs.patch | 53 +++++++++ ...-correctly-describe-LED-polarity-ove.patch | 108 ++++++++++++++++++ ...hy-aquantia-enable-AQR112-and-AQR412.patch | 4 +- ...ntia-add-PHY_IDs-for-AQR112-variants.patch | 4 +- ...detach-callback-to-struct-phy_driver.patch | 2 +- .../dts/mt7988a-smartrg-mt-stuart.dtsi | 4 +- 8 files changed, 168 insertions(+), 7 deletions(-) rename target/linux/generic/{pending-6.6/750-net-phy-aquantia-fix-setting-active_low-bit.patch => backport-6.6/839-v6.13-net-phy-aquantia-fix-setting-active_low-bit.patch} (100%) rename target/linux/generic/{pending-6.6/751-net-phy-aquantia-fix-applying-active_low-bit-after-reset.patch => backport-6.6/840-v6.13-net-phy-aquantia-fix-applying-active_low-bit-after-reset.patch} (100%) create mode 100644 target/linux/generic/backport-6.6/841-v6.13-net-phy-support-active-high-property-for-PHY-LEDs.patch create mode 100644 target/linux/generic/backport-6.6/842-v6.13-net-phy-aquantia-correctly-describe-LED-polarity-ove.patch diff --git a/target/linux/generic/pending-6.6/750-net-phy-aquantia-fix-setting-active_low-bit.patch b/target/linux/generic/backport-6.6/839-v6.13-net-phy-aquantia-fix-setting-active_low-bit.patch similarity index 100% rename from target/linux/generic/pending-6.6/750-net-phy-aquantia-fix-setting-active_low-bit.patch rename to target/linux/generic/backport-6.6/839-v6.13-net-phy-aquantia-fix-setting-active_low-bit.patch diff --git a/target/linux/generic/pending-6.6/751-net-phy-aquantia-fix-applying-active_low-bit-after-reset.patch b/target/linux/generic/backport-6.6/840-v6.13-net-phy-aquantia-fix-applying-active_low-bit-after-reset.patch similarity index 100% rename from target/linux/generic/pending-6.6/751-net-phy-aquantia-fix-applying-active_low-bit-after-reset.patch rename to target/linux/generic/backport-6.6/840-v6.13-net-phy-aquantia-fix-applying-active_low-bit-after-reset.patch diff --git a/target/linux/generic/backport-6.6/841-v6.13-net-phy-support-active-high-property-for-PHY-LEDs.patch b/target/linux/generic/backport-6.6/841-v6.13-net-phy-support-active-high-property-for-PHY-LEDs.patch new file mode 100644 index 00000000000000..02706ccd3f60c7 --- /dev/null +++ b/target/linux/generic/backport-6.6/841-v6.13-net-phy-support-active-high-property-for-PHY-LEDs.patch @@ -0,0 +1,53 @@ +From a274465cc3bef2dfd9c9ea5100848dda0a8641e1 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 10 Oct 2024 13:54:19 +0100 +Subject: [PATCH 1/4] net: phy: support 'active-high' property for PHY LEDs + +In addition to 'active-low' and 'inactive-high-impedance' also +support 'active-high' property for PHY LED pin configuration. +As only either 'active-high' or 'active-low' can be set at the +same time, WARN and return an error in case both are set. + +Signed-off-by: Daniel Golle +Reviewed-by: Andrew Lunn +Link: https://patch.msgid.link/91598487773d768f254d5faf06cf65b13e972f0e.1728558223.git.daniel@makrotopia.org +Signed-off-by: Paolo Abeni +--- + drivers/net/phy/phy_device.c | 6 ++++++ + include/linux/phy.h | 5 +++-- + 2 files changed, 9 insertions(+), 2 deletions(-) + +--- a/drivers/net/phy/phy_device.c ++++ b/drivers/net/phy/phy_device.c +@@ -3219,11 +3219,17 @@ static int of_phy_led(struct phy_device + if (index > U8_MAX) + return -EINVAL; + ++ if (of_property_read_bool(led, "active-high")) ++ set_bit(PHY_LED_ACTIVE_HIGH, &modes); + if (of_property_read_bool(led, "active-low")) + set_bit(PHY_LED_ACTIVE_LOW, &modes); + if (of_property_read_bool(led, "inactive-high-impedance")) + set_bit(PHY_LED_INACTIVE_HIGH_IMPEDANCE, &modes); + ++ if (WARN_ON(modes & BIT(PHY_LED_ACTIVE_LOW) && ++ modes & BIT(PHY_LED_ACTIVE_HIGH))) ++ return -EINVAL; ++ + if (modes) { + /* Return error if asked to set polarity modes but not supported */ + if (!phydev->drv->led_polarity_set) +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -872,8 +872,9 @@ struct phy_led { + + /* Modes for PHY LED configuration */ + enum phy_led_modes { +- PHY_LED_ACTIVE_LOW = 0, +- PHY_LED_INACTIVE_HIGH_IMPEDANCE = 1, ++ PHY_LED_ACTIVE_HIGH = 0, ++ PHY_LED_ACTIVE_LOW = 1, ++ PHY_LED_INACTIVE_HIGH_IMPEDANCE = 2, + + /* keep it last */ + __PHY_LED_MODES_NUM, diff --git a/target/linux/generic/backport-6.6/842-v6.13-net-phy-aquantia-correctly-describe-LED-polarity-ove.patch b/target/linux/generic/backport-6.6/842-v6.13-net-phy-aquantia-correctly-describe-LED-polarity-ove.patch new file mode 100644 index 00000000000000..f26bb829e45c79 --- /dev/null +++ b/target/linux/generic/backport-6.6/842-v6.13-net-phy-aquantia-correctly-describe-LED-polarity-ove.patch @@ -0,0 +1,108 @@ +From 9d55e68b19f222e6334ef4021c5527998f5ab537 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 10 Oct 2024 13:55:00 +0100 +Subject: [PATCH 2/4] net: phy: aquantia: correctly describe LED polarity + override + +Use newly defined 'active-high' property to set the +VEND1_GLOBAL_LED_DRIVE_VDD bit and let 'active-low' clear that bit. This +reflects the technical reality which was inverted in the previous +description in which the 'active-low' property was used to actually set +the VEND1_GLOBAL_LED_DRIVE_VDD bit, which means that VDD (ie. supply +voltage) of the LED is driven rather than GND. + +Signed-off-by: Daniel Golle +Reviewed-by: Andrew Lunn +Link: https://patch.msgid.link/86a413b4387c42dcb54f587cc2433a06f16aae83.1728558223.git.daniel@makrotopia.org +Signed-off-by: Paolo Abeni +--- + drivers/net/phy/aquantia/aquantia.h | 1 + + drivers/net/phy/aquantia/aquantia_leds.c | 19 ++++++++++++++----- + drivers/net/phy/aquantia/aquantia_main.c | 12 +++++++++--- + 3 files changed, 24 insertions(+), 8 deletions(-) + +--- a/drivers/net/phy/aquantia/aquantia.h ++++ b/drivers/net/phy/aquantia/aquantia.h +@@ -169,6 +169,7 @@ static const struct aqr107_hw_stat aqr10 + struct aqr107_priv { + u64 sgmii_stats[AQR107_SGMII_STAT_SZ]; + unsigned long leds_active_low; ++ unsigned long leds_active_high; + }; + + #if IS_REACHABLE(CONFIG_HWMON) +--- a/drivers/net/phy/aquantia/aquantia_leds.c ++++ b/drivers/net/phy/aquantia/aquantia_leds.c +@@ -121,13 +121,13 @@ int aqr_phy_led_active_low_set(struct ph + { + return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_DRIVE(index), + VEND1_GLOBAL_LED_DRIVE_VDD, +- enable ? VEND1_GLOBAL_LED_DRIVE_VDD : 0); ++ enable ? 0 : VEND1_GLOBAL_LED_DRIVE_VDD); + } + + int aqr_phy_led_polarity_set(struct phy_device *phydev, int index, unsigned long modes) + { ++ bool force_active_low = false, force_active_high = false; + struct aqr107_priv *priv = phydev->priv; +- bool active_low = false; + u32 mode; + + if (index >= AQR_MAX_LEDS) +@@ -136,7 +136,10 @@ int aqr_phy_led_polarity_set(struct phy_ + for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { + switch (mode) { + case PHY_LED_ACTIVE_LOW: +- active_low = true; ++ force_active_low = true; ++ break; ++ case PHY_LED_ACTIVE_HIGH: ++ force_active_high = true; + break; + default: + return -EINVAL; +@@ -144,8 +147,14 @@ int aqr_phy_led_polarity_set(struct phy_ + } + + /* Save LED driver vdd state to restore on SW reset */ +- if (active_low) ++ if (force_active_low) + priv->leds_active_low |= BIT(index); + +- return aqr_phy_led_active_low_set(phydev, index, active_low); ++ if (force_active_high) ++ priv->leds_active_high |= BIT(index); ++ ++ if (force_active_high || force_active_low) ++ return aqr_phy_led_active_low_set(phydev, index, force_active_low); ++ ++ unreachable(); + } +--- a/drivers/net/phy/aquantia/aquantia_main.c ++++ b/drivers/net/phy/aquantia/aquantia_main.c +@@ -529,7 +529,7 @@ static int aqr107_config_mdi(struct phy_ + static int aqr107_config_init(struct phy_device *phydev) + { + struct aqr107_priv *priv = phydev->priv; +- u32 led_active_low; ++ u32 led_idx; + int ret; + + /* Check that the PHY interface type is compatible */ +@@ -569,8 +569,14 @@ static int aqr107_config_init(struct phy + return ret; + + /* Restore LED polarity state after reset */ +- for_each_set_bit(led_active_low, &priv->leds_active_low, AQR_MAX_LEDS) { +- ret = aqr_phy_led_active_low_set(phydev, led_active_low, true); ++ for_each_set_bit(led_idx, &priv->leds_active_low, AQR_MAX_LEDS) { ++ ret = aqr_phy_led_active_low_set(phydev, led_idx, true); ++ if (ret) ++ return ret; ++ } ++ ++ for_each_set_bit(led_idx, &priv->leds_active_high, AQR_MAX_LEDS) { ++ ret = aqr_phy_led_active_low_set(phydev, led_idx, false); + if (ret) + return ret; + } diff --git a/target/linux/generic/hack-6.6/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch b/target/linux/generic/hack-6.6/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch index 4ebddb3b4560af..522dbaf68f4cf8 100644 --- a/target/linux/generic/hack-6.6/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch +++ b/target/linux/generic/hack-6.6/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch @@ -97,7 +97,7 @@ Signed-off-by: Alex Marginean static int aqr_config_intr(struct phy_device *phydev) { bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; -@@ -848,7 +916,7 @@ static struct phy_driver aqr_driver[] = +@@ -854,7 +922,7 @@ static struct phy_driver aqr_driver[] = PHY_ID_MATCH_MODEL(PHY_ID_AQR112), .name = "Aquantia AQR112", .probe = aqr107_probe, @@ -106,7 +106,7 @@ Signed-off-by: Alex Marginean .config_intr = aqr_config_intr, .handle_interrupt = aqr_handle_interrupt, .get_tunable = aqr107_get_tunable, -@@ -871,7 +939,7 @@ static struct phy_driver aqr_driver[] = +@@ -877,7 +945,7 @@ static struct phy_driver aqr_driver[] = PHY_ID_MATCH_MODEL(PHY_ID_AQR412), .name = "Aquantia AQR412", .probe = aqr107_probe, diff --git a/target/linux/generic/hack-6.6/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch b/target/linux/generic/hack-6.6/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch index b3767f13464ecf..ed47187a3e87c2 100644 --- a/target/linux/generic/hack-6.6/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch +++ b/target/linux/generic/hack-6.6/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch @@ -21,7 +21,7 @@ Signed-off-by: Daniel Golle #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) -@@ -1055,6 +1057,30 @@ static struct phy_driver aqr_driver[] = +@@ -1061,6 +1063,30 @@ static struct phy_driver aqr_driver[] = .led_hw_control_get = aqr_phy_led_hw_control_get, .led_polarity_set = aqr_phy_led_polarity_set, }, @@ -52,7 +52,7 @@ Signed-off-by: Daniel Golle }; module_phy_driver(aqr_driver); -@@ -1075,6 +1101,8 @@ static struct mdio_device_id __maybe_unu +@@ -1081,6 +1107,8 @@ static struct mdio_device_id __maybe_unu { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, { PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) }, { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) }, diff --git a/target/linux/generic/pending-6.6/703-phy-add-detach-callback-to-struct-phy_driver.patch b/target/linux/generic/pending-6.6/703-phy-add-detach-callback-to-struct-phy_driver.patch index aa8396826334b5..a556a9cc407149 100644 --- a/target/linux/generic/pending-6.6/703-phy-add-detach-callback-to-struct-phy_driver.patch +++ b/target/linux/generic/pending-6.6/703-phy-add-detach-callback-to-struct-phy_driver.patch @@ -23,7 +23,7 @@ Signed-off-by: Gabor Juhos sysfs_remove_link(&dev->dev.kobj, "phydev"); --- a/include/linux/phy.h +++ b/include/linux/phy.h -@@ -979,6 +979,12 @@ struct phy_driver { +@@ -980,6 +980,12 @@ struct phy_driver { /** @handle_interrupt: Override default interrupt handling */ irqreturn_t (*handle_interrupt)(struct phy_device *phydev); diff --git a/target/linux/mediatek/dts/mt7988a-smartrg-mt-stuart.dtsi b/target/linux/mediatek/dts/mt7988a-smartrg-mt-stuart.dtsi index 93bbd0103bb011..ccf85fc1108757 100644 --- a/target/linux/mediatek/dts/mt7988a-smartrg-mt-stuart.dtsi +++ b/target/linux/mediatek/dts/mt7988a-smartrg-mt-stuart.dtsi @@ -433,7 +433,7 @@ reg = <2>; function = LED_FUNCTION_WAN; color = ; - active-low; + active-high; }; }; }; @@ -467,7 +467,7 @@ reg = <2>; function = LED_FUNCTION_LAN; color = ; - active-low; + active-high; }; }; }; From 5fd518b6e3d5447acb862cc4119425316e22a1ba Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Wed, 2 Oct 2024 00:35:07 +0100 Subject: [PATCH 07/32] generic: net: phy: mxl-gpy: add support for PHY LEDs Add driver support for PHY LEDs for MaxLinear/Intel GPY Ethernet PHYs. Signed-off-by: Daniel Golle --- ...et-phy-mxl-gpy-add-basic-LED-support.patch | 332 ++++++++++++++++++ ...add-missing-support-for-TRIGGER_NETD.patch | 28 ++ ...-gpy-correctly-describe-LED-polarity.patch | 58 +++ .../765-mxl-gpy-control-LED-reg-from-DT.patch | 32 +- ...-don-t-use-SGMII-AN-if-using-phylink.patch | 8 +- 5 files changed, 426 insertions(+), 32 deletions(-) create mode 100644 target/linux/generic/backport-6.6/843-v6.13-net-phy-mxl-gpy-add-basic-LED-support.patch create mode 100644 target/linux/generic/backport-6.6/844-v6.13-net-phy-mxl-gpy-add-missing-support-for-TRIGGER_NETD.patch create mode 100644 target/linux/generic/backport-6.6/845-v6.13-net-phy-mxl-gpy-correctly-describe-LED-polarity.patch diff --git a/target/linux/generic/backport-6.6/843-v6.13-net-phy-mxl-gpy-add-basic-LED-support.patch b/target/linux/generic/backport-6.6/843-v6.13-net-phy-mxl-gpy-add-basic-LED-support.patch new file mode 100644 index 00000000000000..2ceaa0ad3d0b20 --- /dev/null +++ b/target/linux/generic/backport-6.6/843-v6.13-net-phy-mxl-gpy-add-basic-LED-support.patch @@ -0,0 +1,332 @@ +From 78997e9a5e4d8a4df561e083a92c91ae23010e07 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Tue, 1 Oct 2024 01:17:18 +0100 +Subject: [PATCH] net: phy: mxl-gpy: add basic LED support + +Add basic support for LEDs connected to MaxLinear GPY2xx and GPY115 PHYs. +The PHYs allow up to 4 LEDs to be connected. +Implement controlling LEDs in software as well as netdev trigger offloading +and LED polarity setup. + +The hardware claims to support 16 PWM brightness levels but there is no +documentation on how to use that feature, hence this is not supported. + +Signed-off-by: Daniel Golle +Reviewed-by: Andrew Lunn +Link: https://patch.msgid.link/b6ec9050339f8244ff898898a1cecc33b13a48fc.1727741563.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/mxl-gpy.c | 218 ++++++++++++++++++++++++++++++++++++++ + 1 file changed, 218 insertions(+) + +--- a/drivers/net/phy/mxl-gpy.c ++++ b/drivers/net/phy/mxl-gpy.c +@@ -38,6 +38,7 @@ + #define PHY_MIISTAT 0x18 /* MII state */ + #define PHY_IMASK 0x19 /* interrupt mask */ + #define PHY_ISTAT 0x1A /* interrupt status */ ++#define PHY_LED 0x1B /* LEDs */ + #define PHY_FWV 0x1E /* firmware version */ + + #define PHY_MIISTAT_SPD_MASK GENMASK(2, 0) +@@ -61,6 +62,11 @@ + PHY_IMASK_ADSC | \ + PHY_IMASK_ANC) + ++#define GPY_MAX_LEDS 4 ++#define PHY_LED_POLARITY(idx) BIT(12 + (idx)) ++#define PHY_LED_HWCONTROL(idx) BIT(8 + (idx)) ++#define PHY_LED_ON(idx) BIT(idx) ++ + #define PHY_FWV_REL_MASK BIT(15) + #define PHY_FWV_MAJOR_MASK GENMASK(11, 8) + #define PHY_FWV_MINOR_MASK GENMASK(7, 0) +@@ -72,6 +78,23 @@ + #define PHY_MDI_MDI_X_CD 0x1 + #define PHY_MDI_MDI_X_CROSS 0x0 + ++/* LED */ ++#define VSPEC1_LED(idx) (1 + (idx)) ++#define VSPEC1_LED_BLINKS GENMASK(15, 12) ++#define VSPEC1_LED_PULSE GENMASK(11, 8) ++#define VSPEC1_LED_CON GENMASK(7, 4) ++#define VSPEC1_LED_BLINKF GENMASK(3, 0) ++ ++#define VSPEC1_LED_LINK10 BIT(0) ++#define VSPEC1_LED_LINK100 BIT(1) ++#define VSPEC1_LED_LINK1000 BIT(2) ++#define VSPEC1_LED_LINK2500 BIT(3) ++ ++#define VSPEC1_LED_TXACT BIT(0) ++#define VSPEC1_LED_RXACT BIT(1) ++#define VSPEC1_LED_COL BIT(2) ++#define VSPEC1_LED_NO_CON BIT(3) ++ + /* SGMII */ + #define VSPEC1_SGMII_CTRL 0x08 + #define VSPEC1_SGMII_CTRL_ANEN BIT(12) /* Aneg enable */ +@@ -827,6 +850,156 @@ static int gpy115_loopback(struct phy_de + return genphy_soft_reset(phydev); + } + ++static int gpy_led_brightness_set(struct phy_device *phydev, ++ u8 index, enum led_brightness value) ++{ ++ int ret; ++ ++ if (index >= GPY_MAX_LEDS) ++ return -EINVAL; ++ ++ /* clear HWCONTROL and set manual LED state */ ++ ret = phy_modify(phydev, PHY_LED, ++ ((value == LED_OFF) ? PHY_LED_HWCONTROL(index) : 0) | ++ PHY_LED_ON(index), ++ (value == LED_OFF) ? 0 : PHY_LED_ON(index)); ++ if (ret) ++ return ret; ++ ++ /* ToDo: set PWM brightness */ ++ ++ /* clear HW LED setup */ ++ if (value == LED_OFF) ++ return phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index), 0); ++ else ++ return 0; ++} ++ ++static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_LINK) | ++ BIT(TRIGGER_NETDEV_LINK_100) | ++ BIT(TRIGGER_NETDEV_LINK_1000) | ++ BIT(TRIGGER_NETDEV_LINK_2500) | ++ BIT(TRIGGER_NETDEV_RX) | ++ BIT(TRIGGER_NETDEV_TX)); ++ ++static int gpy_led_hw_is_supported(struct phy_device *phydev, u8 index, ++ unsigned long rules) ++{ ++ if (index >= GPY_MAX_LEDS) ++ return -EINVAL; ++ ++ /* All combinations of the supported triggers are allowed */ ++ if (rules & ~supported_triggers) ++ return -EOPNOTSUPP; ++ ++ return 0; ++} ++ ++static int gpy_led_hw_control_get(struct phy_device *phydev, u8 index, ++ unsigned long *rules) ++{ ++ int val; ++ ++ if (index >= GPY_MAX_LEDS) ++ return -EINVAL; ++ ++ val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index)); ++ if (val < 0) ++ return val; ++ ++ if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK10) ++ *rules |= BIT(TRIGGER_NETDEV_LINK_10); ++ ++ if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK100) ++ *rules |= BIT(TRIGGER_NETDEV_LINK_100); ++ ++ if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK1000) ++ *rules |= BIT(TRIGGER_NETDEV_LINK_1000); ++ ++ if (FIELD_GET(VSPEC1_LED_CON, val) & VSPEC1_LED_LINK2500) ++ *rules |= BIT(TRIGGER_NETDEV_LINK_2500); ++ ++ if (FIELD_GET(VSPEC1_LED_CON, val) == (VSPEC1_LED_LINK10 | ++ VSPEC1_LED_LINK100 | ++ VSPEC1_LED_LINK1000 | ++ VSPEC1_LED_LINK2500)) ++ *rules |= BIT(TRIGGER_NETDEV_LINK); ++ ++ if (FIELD_GET(VSPEC1_LED_PULSE, val) & VSPEC1_LED_TXACT) ++ *rules |= BIT(TRIGGER_NETDEV_TX); ++ ++ if (FIELD_GET(VSPEC1_LED_PULSE, val) & VSPEC1_LED_RXACT) ++ *rules |= BIT(TRIGGER_NETDEV_RX); ++ ++ return 0; ++} ++ ++static int gpy_led_hw_control_set(struct phy_device *phydev, u8 index, ++ unsigned long rules) ++{ ++ u16 val = 0; ++ int ret; ++ ++ if (index >= GPY_MAX_LEDS) ++ return -EINVAL; ++ ++ if (rules & BIT(TRIGGER_NETDEV_LINK) || ++ rules & BIT(TRIGGER_NETDEV_LINK_10)) ++ val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK10); ++ ++ if (rules & BIT(TRIGGER_NETDEV_LINK) || ++ rules & BIT(TRIGGER_NETDEV_LINK_100)) ++ val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK100); ++ ++ if (rules & BIT(TRIGGER_NETDEV_LINK) || ++ rules & BIT(TRIGGER_NETDEV_LINK_1000)) ++ val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK1000); ++ ++ if (rules & BIT(TRIGGER_NETDEV_LINK) || ++ rules & BIT(TRIGGER_NETDEV_LINK_2500)) ++ val |= FIELD_PREP(VSPEC1_LED_CON, VSPEC1_LED_LINK2500); ++ ++ if (rules & BIT(TRIGGER_NETDEV_TX)) ++ val |= FIELD_PREP(VSPEC1_LED_PULSE, VSPEC1_LED_TXACT); ++ ++ if (rules & BIT(TRIGGER_NETDEV_RX)) ++ val |= FIELD_PREP(VSPEC1_LED_PULSE, VSPEC1_LED_RXACT); ++ ++ /* allow RX/TX pulse without link indication */ ++ if ((rules & BIT(TRIGGER_NETDEV_TX) || rules & BIT(TRIGGER_NETDEV_RX)) && ++ !(val & VSPEC1_LED_CON)) ++ val |= FIELD_PREP(VSPEC1_LED_PULSE, VSPEC1_LED_NO_CON) | VSPEC1_LED_CON; ++ ++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index), val); ++ if (ret) ++ return ret; ++ ++ return phy_set_bits(phydev, PHY_LED, PHY_LED_HWCONTROL(index)); ++} ++ ++static int gpy_led_polarity_set(struct phy_device *phydev, int index, ++ unsigned long modes) ++{ ++ bool active_low = false; ++ u32 mode; ++ ++ if (index >= GPY_MAX_LEDS) ++ return -EINVAL; ++ ++ for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { ++ switch (mode) { ++ case PHY_LED_ACTIVE_LOW: ++ active_low = true; ++ break; ++ default: ++ return -EINVAL; ++ } ++ } ++ ++ return phy_modify(phydev, PHY_LED, PHY_LED_POLARITY(index), ++ active_low ? 0 : PHY_LED_POLARITY(index)); ++} ++ + static struct phy_driver gpy_drivers[] = { + { + PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx), +@@ -844,6 +1017,11 @@ static struct phy_driver gpy_drivers[] = + .set_wol = gpy_set_wol, + .get_wol = gpy_get_wol, + .set_loopback = gpy_loopback, ++ .led_brightness_set = gpy_led_brightness_set, ++ .led_hw_is_supported = gpy_led_hw_is_supported, ++ .led_hw_control_get = gpy_led_hw_control_get, ++ .led_hw_control_set = gpy_led_hw_control_set, ++ .led_polarity_set = gpy_led_polarity_set, + }, + { + .phy_id = PHY_ID_GPY115B, +@@ -862,6 +1040,11 @@ static struct phy_driver gpy_drivers[] = + .set_wol = gpy_set_wol, + .get_wol = gpy_get_wol, + .set_loopback = gpy115_loopback, ++ .led_brightness_set = gpy_led_brightness_set, ++ .led_hw_is_supported = gpy_led_hw_is_supported, ++ .led_hw_control_get = gpy_led_hw_control_get, ++ .led_hw_control_set = gpy_led_hw_control_set, ++ .led_polarity_set = gpy_led_polarity_set, + }, + { + PHY_ID_MATCH_MODEL(PHY_ID_GPY115C), +@@ -879,6 +1062,11 @@ static struct phy_driver gpy_drivers[] = + .set_wol = gpy_set_wol, + .get_wol = gpy_get_wol, + .set_loopback = gpy115_loopback, ++ .led_brightness_set = gpy_led_brightness_set, ++ .led_hw_is_supported = gpy_led_hw_is_supported, ++ .led_hw_control_get = gpy_led_hw_control_get, ++ .led_hw_control_set = gpy_led_hw_control_set, ++ .led_polarity_set = gpy_led_polarity_set, + }, + { + .phy_id = PHY_ID_GPY211B, +@@ -897,6 +1085,11 @@ static struct phy_driver gpy_drivers[] = + .set_wol = gpy_set_wol, + .get_wol = gpy_get_wol, + .set_loopback = gpy_loopback, ++ .led_brightness_set = gpy_led_brightness_set, ++ .led_hw_is_supported = gpy_led_hw_is_supported, ++ .led_hw_control_get = gpy_led_hw_control_get, ++ .led_hw_control_set = gpy_led_hw_control_set, ++ .led_polarity_set = gpy_led_polarity_set, + }, + { + PHY_ID_MATCH_MODEL(PHY_ID_GPY211C), +@@ -914,6 +1107,11 @@ static struct phy_driver gpy_drivers[] = + .set_wol = gpy_set_wol, + .get_wol = gpy_get_wol, + .set_loopback = gpy_loopback, ++ .led_brightness_set = gpy_led_brightness_set, ++ .led_hw_is_supported = gpy_led_hw_is_supported, ++ .led_hw_control_get = gpy_led_hw_control_get, ++ .led_hw_control_set = gpy_led_hw_control_set, ++ .led_polarity_set = gpy_led_polarity_set, + }, + { + .phy_id = PHY_ID_GPY212B, +@@ -932,6 +1130,11 @@ static struct phy_driver gpy_drivers[] = + .set_wol = gpy_set_wol, + .get_wol = gpy_get_wol, + .set_loopback = gpy_loopback, ++ .led_brightness_set = gpy_led_brightness_set, ++ .led_hw_is_supported = gpy_led_hw_is_supported, ++ .led_hw_control_get = gpy_led_hw_control_get, ++ .led_hw_control_set = gpy_led_hw_control_set, ++ .led_polarity_set = gpy_led_polarity_set, + }, + { + PHY_ID_MATCH_MODEL(PHY_ID_GPY212C), +@@ -949,6 +1152,11 @@ static struct phy_driver gpy_drivers[] = + .set_wol = gpy_set_wol, + .get_wol = gpy_get_wol, + .set_loopback = gpy_loopback, ++ .led_brightness_set = gpy_led_brightness_set, ++ .led_hw_is_supported = gpy_led_hw_is_supported, ++ .led_hw_control_get = gpy_led_hw_control_get, ++ .led_hw_control_set = gpy_led_hw_control_set, ++ .led_polarity_set = gpy_led_polarity_set, + }, + { + .phy_id = PHY_ID_GPY215B, +@@ -967,6 +1175,11 @@ static struct phy_driver gpy_drivers[] = + .set_wol = gpy_set_wol, + .get_wol = gpy_get_wol, + .set_loopback = gpy_loopback, ++ .led_brightness_set = gpy_led_brightness_set, ++ .led_hw_is_supported = gpy_led_hw_is_supported, ++ .led_hw_control_get = gpy_led_hw_control_get, ++ .led_hw_control_set = gpy_led_hw_control_set, ++ .led_polarity_set = gpy_led_polarity_set, + }, + { + PHY_ID_MATCH_MODEL(PHY_ID_GPY215C), +@@ -984,6 +1197,11 @@ static struct phy_driver gpy_drivers[] = + .set_wol = gpy_set_wol, + .get_wol = gpy_get_wol, + .set_loopback = gpy_loopback, ++ .led_brightness_set = gpy_led_brightness_set, ++ .led_hw_is_supported = gpy_led_hw_is_supported, ++ .led_hw_control_get = gpy_led_hw_control_get, ++ .led_hw_control_set = gpy_led_hw_control_set, ++ .led_polarity_set = gpy_led_polarity_set, + }, + { + PHY_ID_MATCH_MODEL(PHY_ID_GPY241B), diff --git a/target/linux/generic/backport-6.6/844-v6.13-net-phy-mxl-gpy-add-missing-support-for-TRIGGER_NETD.patch b/target/linux/generic/backport-6.6/844-v6.13-net-phy-mxl-gpy-add-missing-support-for-TRIGGER_NETD.patch new file mode 100644 index 00000000000000..067c62da11ef81 --- /dev/null +++ b/target/linux/generic/backport-6.6/844-v6.13-net-phy-mxl-gpy-add-missing-support-for-TRIGGER_NETD.patch @@ -0,0 +1,28 @@ +From f95b4725e796b12e5f347a0d161e1d3843142aa8 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Fri, 4 Oct 2024 16:56:35 +0100 +Subject: [PATCH] net: phy: mxl-gpy: add missing support for + TRIGGER_NETDEV_LINK_10 + +The PHY also support 10MBit/s links as well as the corresponding link +indication trigger to be offloaded. Add TRIGGER_NETDEV_LINK_10 to the +supported triggers. + +Signed-off-by: Daniel Golle +Reviewed-by: Andrew Lunn +Link: https://patch.msgid.link/cc5da0a989af8b0d49d823656d88053c4de2ab98.1728057367.git.daniel@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/mxl-gpy.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/net/phy/mxl-gpy.c ++++ b/drivers/net/phy/mxl-gpy.c +@@ -876,6 +876,7 @@ static int gpy_led_brightness_set(struct + } + + static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_LINK) | ++ BIT(TRIGGER_NETDEV_LINK_10) | + BIT(TRIGGER_NETDEV_LINK_100) | + BIT(TRIGGER_NETDEV_LINK_1000) | + BIT(TRIGGER_NETDEV_LINK_2500) | diff --git a/target/linux/generic/backport-6.6/845-v6.13-net-phy-mxl-gpy-correctly-describe-LED-polarity.patch b/target/linux/generic/backport-6.6/845-v6.13-net-phy-mxl-gpy-correctly-describe-LED-polarity.patch new file mode 100644 index 00000000000000..5b88548dd06a3c --- /dev/null +++ b/target/linux/generic/backport-6.6/845-v6.13-net-phy-mxl-gpy-correctly-describe-LED-polarity.patch @@ -0,0 +1,58 @@ +From eb89c79c1b8f17fc1611540768678e60df89ac42 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 10 Oct 2024 13:55:17 +0100 +Subject: [PATCH 3/4] net: phy: mxl-gpy: correctly describe LED polarity + +According the datasheet covering the LED (0x1b) register: +0B Active High LEDx pin driven high when activated +1B Active Low LEDx pin driven low when activated + +Make use of the now available 'active-high' property and correctly +reflect the polarity setting which was previously inverted. + +Signed-off-by: Daniel Golle +Reviewed-by: Andrew Lunn +Link: https://patch.msgid.link/180ccafa837f09908b852a8a874a3808c5ecd2d0.1728558223.git.daniel@makrotopia.org +Signed-off-by: Paolo Abeni +--- + drivers/net/phy/mxl-gpy.c | 16 ++++++++++++---- + 1 file changed, 12 insertions(+), 4 deletions(-) + +--- a/drivers/net/phy/mxl-gpy.c ++++ b/drivers/net/phy/mxl-gpy.c +@@ -981,7 +981,7 @@ static int gpy_led_hw_control_set(struct + static int gpy_led_polarity_set(struct phy_device *phydev, int index, + unsigned long modes) + { +- bool active_low = false; ++ bool force_active_low = false, force_active_high = false; + u32 mode; + + if (index >= GPY_MAX_LEDS) +@@ -990,15 +990,23 @@ static int gpy_led_polarity_set(struct p + for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { + switch (mode) { + case PHY_LED_ACTIVE_LOW: +- active_low = true; ++ force_active_low = true; ++ break; ++ case PHY_LED_ACTIVE_HIGH: ++ force_active_high = true; + break; + default: + return -EINVAL; + } + } + +- return phy_modify(phydev, PHY_LED, PHY_LED_POLARITY(index), +- active_low ? 0 : PHY_LED_POLARITY(index)); ++ if (force_active_low) ++ return phy_set_bits(phydev, PHY_LED, PHY_LED_POLARITY(index)); ++ ++ if (force_active_high) ++ return phy_clear_bits(phydev, PHY_LED, PHY_LED_POLARITY(index)); ++ ++ unreachable(); + } + + static struct phy_driver gpy_drivers[] = { diff --git a/target/linux/generic/hack-6.6/765-mxl-gpy-control-LED-reg-from-DT.patch b/target/linux/generic/hack-6.6/765-mxl-gpy-control-LED-reg-from-DT.patch index fd2a3278114efc..041f05e59b427d 100644 --- a/target/linux/generic/hack-6.6/765-mxl-gpy-control-LED-reg-from-DT.patch +++ b/target/linux/generic/hack-6.6/765-mxl-gpy-control-LED-reg-from-DT.patch @@ -31,45 +31,21 @@ Signed-off-by: David Bauer #include #include #include -@@ -38,6 +39,7 @@ - #define PHY_MIISTAT 0x18 /* MII state */ - #define PHY_IMASK 0x19 /* interrupt mask */ - #define PHY_ISTAT 0x1A /* interrupt status */ -+#define PHY_LED 0x1B /* LED control */ - #define PHY_FWV 0x1E /* firmware version */ - - #define PHY_MIISTAT_SPD_MASK GENMASK(2, 0) -@@ -61,10 +63,15 @@ - PHY_IMASK_ADSC | \ - PHY_IMASK_ANC) - -+#define PHY_LED_NUM_LEDS 4 -+ - #define PHY_FWV_REL_MASK BIT(15) - #define PHY_FWV_MAJOR_MASK GENMASK(11, 8) - #define PHY_FWV_MINOR_MASK GENMASK(7, 0) - -+/* LED */ -+#define VSPEC1_LED(x) (0x1 + x) -+ - #define PHY_PMA_MGBT_POLARITY 0x82 - #define PHY_MDI_MDI_X_MASK GENMASK(1, 0) - #define PHY_MDI_MDI_X_NORMAL 0x3 -@@ -270,10 +277,39 @@ out: +@@ -293,10 +294,39 @@ out: return ret; } +static int gpy_led_write(struct phy_device *phydev) +{ + struct device_node *node = phydev->mdio.dev.of_node; -+ u32 led_regs[PHY_LED_NUM_LEDS]; ++ u32 led_regs[GPY_MAX_LEDS]; + int i, ret; + u16 val = 0xff00; + + if (!IS_ENABLED(CONFIG_OF_MDIO)) + return 0; + -+ if (of_property_read_u32_array(node, "mxl,led-config", led_regs, PHY_LED_NUM_LEDS)) ++ if (of_property_read_u32_array(node, "mxl,led-config", led_regs, GPY_MAX_LEDS)) + return 0; + + if (of_property_read_bool(node, "mxl,led-drive-vdd")) @@ -79,7 +55,7 @@ Signed-off-by: David Bauer + phy_write(phydev, PHY_LED, val); + + /* Write LED register values */ -+ for (i = 0; i < PHY_LED_NUM_LEDS; i++) { ++ for (i = 0; i < GPY_MAX_LEDS; i++) { + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(i), (u16)led_regs[i]); + if (ret < 0) + return ret; diff --git a/target/linux/mediatek/patches-6.6/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch b/target/linux/mediatek/patches-6.6/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch index 99d0a0dbc2022f..252263ad11825d 100644 --- a/target/linux/mediatek/patches-6.6/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch +++ b/target/linux/mediatek/patches-6.6/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch @@ -14,7 +14,7 @@ Signed-off-by: Daniel Golle --- a/drivers/net/phy/mxl-gpy.c +++ b/drivers/net/phy/mxl-gpy.c -@@ -385,8 +385,11 @@ static bool gpy_2500basex_chk(struct phy +@@ -402,8 +402,11 @@ static bool gpy_2500basex_chk(struct phy phydev->speed = SPEED_2500; phydev->interface = PHY_INTERFACE_MODE_2500BASEX; @@ -28,7 +28,7 @@ Signed-off-by: Daniel Golle return true; } -@@ -437,6 +440,14 @@ static int gpy_config_aneg(struct phy_de +@@ -454,6 +457,14 @@ static int gpy_config_aneg(struct phy_de u32 adv; int ret; @@ -43,7 +43,7 @@ Signed-off-by: Daniel Golle if (phydev->autoneg == AUTONEG_DISABLE) { /* Configure half duplex with genphy_setup_forced, * because genphy_c45_pma_setup_forced does not support. -@@ -559,6 +570,8 @@ static int gpy_update_interface(struct p +@@ -576,6 +587,8 @@ static int gpy_update_interface(struct p switch (phydev->speed) { case SPEED_2500: phydev->interface = PHY_INTERFACE_MODE_2500BASEX; @@ -52,7 +52,7 @@ Signed-off-by: Daniel Golle ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, VSPEC1_SGMII_CTRL_ANEN, 0); if (ret < 0) { -@@ -572,7 +585,7 @@ static int gpy_update_interface(struct p +@@ -589,7 +602,7 @@ static int gpy_update_interface(struct p case SPEED_100: case SPEED_10: phydev->interface = PHY_INTERFACE_MODE_SGMII; From 3f3c27e22c75837fd84098743cc265a605f3b05c Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 5 Oct 2024 22:21:17 +0100 Subject: [PATCH 08/32] generic: net: phy: intel-way: add support for PHY LEDs Add driver support for PHY LEDs for MaxLinear/Intel/Lantiq XWAY Ethernet PHYs. Signed-off-by: Daniel Golle --- ...-intel-xway-add-support-for-PHY-LEDs.patch | 379 ++++++++++++++++++ 1 file changed, 379 insertions(+) create mode 100644 target/linux/generic/backport-6.6/846-v6.13-net-phy-intel-xway-add-support-for-PHY-LEDs.patch diff --git a/target/linux/generic/backport-6.6/846-v6.13-net-phy-intel-xway-add-support-for-PHY-LEDs.patch b/target/linux/generic/backport-6.6/846-v6.13-net-phy-intel-xway-add-support-for-PHY-LEDs.patch new file mode 100644 index 00000000000000..c57b5777ad512d --- /dev/null +++ b/target/linux/generic/backport-6.6/846-v6.13-net-phy-intel-xway-add-support-for-PHY-LEDs.patch @@ -0,0 +1,379 @@ +From 1758af47b98c17da464cb45f476875150955dd48 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 10 Oct 2024 13:55:29 +0100 +Subject: [PATCH 4/4] net: phy: intel-xway: add support for PHY LEDs + +The intel-xway PHY driver predates the PHY LED framework and currently +initializes all LED pins to equal default values. + +Add PHY LED functions to the drivers and don't set default values if +LEDs are defined in device tree. + +According the datasheets 3 LEDs are supported on all Intel XWAY PHYs. + +Signed-off-by: Daniel Golle +Reviewed-by: Andrew Lunn +Link: https://patch.msgid.link/81f4717ab9acf38f3239727a4540ae96fd01109b.1728558223.git.daniel@makrotopia.org +Signed-off-by: Paolo Abeni +--- + drivers/net/phy/intel-xway.c | 253 +++++++++++++++++++++++++++++++++-- + 1 file changed, 244 insertions(+), 9 deletions(-) + +--- a/drivers/net/phy/intel-xway.c ++++ b/drivers/net/phy/intel-xway.c +@@ -151,6 +151,13 @@ + #define XWAY_MMD_LED3H 0x01E8 + #define XWAY_MMD_LED3L 0x01E9 + ++#define XWAY_GPHY_MAX_LEDS 3 ++#define XWAY_GPHY_LED_INV(idx) BIT(12 + (idx)) ++#define XWAY_GPHY_LED_EN(idx) BIT(8 + (idx)) ++#define XWAY_GPHY_LED_DA(idx) BIT(idx) ++#define XWAY_MMD_LEDxH(idx) (XWAY_MMD_LED0H + 2 * (idx)) ++#define XWAY_MMD_LEDxL(idx) (XWAY_MMD_LED0L + 2 * (idx)) ++ + #define PHY_ID_PHY11G_1_3 0x030260D1 + #define PHY_ID_PHY22F_1_3 0x030260E1 + #define PHY_ID_PHY11G_1_4 0xD565A400 +@@ -229,20 +236,12 @@ static int xway_gphy_rgmii_init(struct p + XWAY_MDIO_MIICTRL_TXSKEW_MASK, val); + } + +-static int xway_gphy_config_init(struct phy_device *phydev) ++static int xway_gphy_init_leds(struct phy_device *phydev) + { + int err; + u32 ledxh; + u32 ledxl; + +- /* Mask all interrupts */ +- err = phy_write(phydev, XWAY_MDIO_IMASK, 0); +- if (err) +- return err; +- +- /* Clear all pending interrupts */ +- phy_read(phydev, XWAY_MDIO_ISTAT); +- + /* Ensure that integrated led function is enabled for all leds */ + err = phy_write(phydev, XWAY_MDIO_LED, + XWAY_MDIO_LED_LED0_EN | +@@ -276,6 +275,26 @@ static int xway_gphy_config_init(struct + phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh); + phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl); + ++ return 0; ++} ++ ++static int xway_gphy_config_init(struct phy_device *phydev) ++{ ++ struct device_node *np = phydev->mdio.dev.of_node; ++ int err; ++ ++ /* Mask all interrupts */ ++ err = phy_write(phydev, XWAY_MDIO_IMASK, 0); ++ if (err) ++ return err; ++ ++ /* Use default LED configuration if 'leds' node isn't defined */ ++ if (!of_get_child_by_name(np, "leds")) ++ xway_gphy_init_leds(phydev); ++ ++ /* Clear all pending interrupts */ ++ phy_read(phydev, XWAY_MDIO_ISTAT); ++ + err = xway_gphy_rgmii_init(phydev); + if (err) + return err; +@@ -347,6 +366,172 @@ static irqreturn_t xway_gphy_handle_inte + return IRQ_HANDLED; + } + ++static int xway_gphy_led_brightness_set(struct phy_device *phydev, ++ u8 index, enum led_brightness value) ++{ ++ int ret; ++ ++ if (index >= XWAY_GPHY_MAX_LEDS) ++ return -EINVAL; ++ ++ /* clear EN and set manual LED state */ ++ ret = phy_modify(phydev, XWAY_MDIO_LED, ++ ((value == LED_OFF) ? XWAY_GPHY_LED_EN(index) : 0) | ++ XWAY_GPHY_LED_DA(index), ++ (value == LED_OFF) ? 0 : XWAY_GPHY_LED_DA(index)); ++ if (ret) ++ return ret; ++ ++ /* clear HW LED setup */ ++ if (value == LED_OFF) { ++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDxH(index), 0); ++ if (ret) ++ return ret; ++ ++ return phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDxL(index), 0); ++ } else { ++ return 0; ++ } ++} ++ ++static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_LINK) | ++ BIT(TRIGGER_NETDEV_LINK_10) | ++ BIT(TRIGGER_NETDEV_LINK_100) | ++ BIT(TRIGGER_NETDEV_LINK_1000) | ++ BIT(TRIGGER_NETDEV_RX) | ++ BIT(TRIGGER_NETDEV_TX)); ++ ++static int xway_gphy_led_hw_is_supported(struct phy_device *phydev, u8 index, ++ unsigned long rules) ++{ ++ if (index >= XWAY_GPHY_MAX_LEDS) ++ return -EINVAL; ++ ++ /* activity triggers are not possible without combination with a link ++ * trigger. ++ */ ++ if (rules & (BIT(TRIGGER_NETDEV_RX) | BIT(TRIGGER_NETDEV_TX)) && ++ !(rules & (BIT(TRIGGER_NETDEV_LINK) | ++ BIT(TRIGGER_NETDEV_LINK_10) | ++ BIT(TRIGGER_NETDEV_LINK_100) | ++ BIT(TRIGGER_NETDEV_LINK_1000)))) ++ return -EOPNOTSUPP; ++ ++ /* All other combinations of the supported triggers are allowed */ ++ if (rules & ~supported_triggers) ++ return -EOPNOTSUPP; ++ ++ return 0; ++} ++ ++static int xway_gphy_led_hw_control_get(struct phy_device *phydev, u8 index, ++ unsigned long *rules) ++{ ++ int lval, hval; ++ ++ if (index >= XWAY_GPHY_MAX_LEDS) ++ return -EINVAL; ++ ++ hval = phy_read_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDxH(index)); ++ if (hval < 0) ++ return hval; ++ ++ lval = phy_read_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDxL(index)); ++ if (lval < 0) ++ return lval; ++ ++ if (hval & XWAY_MMD_LEDxH_CON_LINK10) ++ *rules |= BIT(TRIGGER_NETDEV_LINK_10); ++ ++ if (hval & XWAY_MMD_LEDxH_CON_LINK100) ++ *rules |= BIT(TRIGGER_NETDEV_LINK_100); ++ ++ if (hval & XWAY_MMD_LEDxH_CON_LINK1000) ++ *rules |= BIT(TRIGGER_NETDEV_LINK_1000); ++ ++ if ((hval & XWAY_MMD_LEDxH_CON_LINK10) && ++ (hval & XWAY_MMD_LEDxH_CON_LINK100) && ++ (hval & XWAY_MMD_LEDxH_CON_LINK1000)) ++ *rules |= BIT(TRIGGER_NETDEV_LINK); ++ ++ if (lval & XWAY_MMD_LEDxL_PULSE_TXACT) ++ *rules |= BIT(TRIGGER_NETDEV_TX); ++ ++ if (lval & XWAY_MMD_LEDxL_PULSE_RXACT) ++ *rules |= BIT(TRIGGER_NETDEV_RX); ++ ++ return 0; ++} ++ ++static int xway_gphy_led_hw_control_set(struct phy_device *phydev, u8 index, ++ unsigned long rules) ++{ ++ u16 hval = 0, lval = 0; ++ int ret; ++ ++ if (index >= XWAY_GPHY_MAX_LEDS) ++ return -EINVAL; ++ ++ if (rules & BIT(TRIGGER_NETDEV_LINK) || ++ rules & BIT(TRIGGER_NETDEV_LINK_10)) ++ hval |= XWAY_MMD_LEDxH_CON_LINK10; ++ ++ if (rules & BIT(TRIGGER_NETDEV_LINK) || ++ rules & BIT(TRIGGER_NETDEV_LINK_100)) ++ hval |= XWAY_MMD_LEDxH_CON_LINK100; ++ ++ if (rules & BIT(TRIGGER_NETDEV_LINK) || ++ rules & BIT(TRIGGER_NETDEV_LINK_1000)) ++ hval |= XWAY_MMD_LEDxH_CON_LINK1000; ++ ++ if (rules & BIT(TRIGGER_NETDEV_TX)) ++ lval |= XWAY_MMD_LEDxL_PULSE_TXACT; ++ ++ if (rules & BIT(TRIGGER_NETDEV_RX)) ++ lval |= XWAY_MMD_LEDxL_PULSE_RXACT; ++ ++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDxH(index), hval); ++ if (ret) ++ return ret; ++ ++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDxL(index), lval); ++ if (ret) ++ return ret; ++ ++ return phy_set_bits(phydev, XWAY_MDIO_LED, XWAY_GPHY_LED_EN(index)); ++} ++ ++static int xway_gphy_led_polarity_set(struct phy_device *phydev, int index, ++ unsigned long modes) ++{ ++ bool force_active_low = false, force_active_high = false; ++ u32 mode; ++ ++ if (index >= XWAY_GPHY_MAX_LEDS) ++ return -EINVAL; ++ ++ for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { ++ switch (mode) { ++ case PHY_LED_ACTIVE_LOW: ++ force_active_low = true; ++ break; ++ case PHY_LED_ACTIVE_HIGH: ++ force_active_high = true; ++ break; ++ default: ++ return -EINVAL; ++ } ++ } ++ ++ if (force_active_low) ++ return phy_set_bits(phydev, XWAY_MDIO_LED, XWAY_GPHY_LED_INV(index)); ++ ++ if (force_active_high) ++ return phy_clear_bits(phydev, XWAY_MDIO_LED, XWAY_GPHY_LED_INV(index)); ++ ++ unreachable(); ++} ++ + static struct phy_driver xway_gphy[] = { + { + .phy_id = PHY_ID_PHY11G_1_3, +@@ -359,6 +544,11 @@ static struct phy_driver xway_gphy[] = { + .config_intr = xway_gphy_config_intr, + .suspend = genphy_suspend, + .resume = genphy_resume, ++ .led_brightness_set = xway_gphy_led_brightness_set, ++ .led_hw_is_supported = xway_gphy_led_hw_is_supported, ++ .led_hw_control_get = xway_gphy_led_hw_control_get, ++ .led_hw_control_set = xway_gphy_led_hw_control_set, ++ .led_polarity_set = xway_gphy_led_polarity_set, + }, { + .phy_id = PHY_ID_PHY22F_1_3, + .phy_id_mask = 0xffffffff, +@@ -370,6 +560,11 @@ static struct phy_driver xway_gphy[] = { + .config_intr = xway_gphy_config_intr, + .suspend = genphy_suspend, + .resume = genphy_resume, ++ .led_brightness_set = xway_gphy_led_brightness_set, ++ .led_hw_is_supported = xway_gphy_led_hw_is_supported, ++ .led_hw_control_get = xway_gphy_led_hw_control_get, ++ .led_hw_control_set = xway_gphy_led_hw_control_set, ++ .led_polarity_set = xway_gphy_led_polarity_set, + }, { + .phy_id = PHY_ID_PHY11G_1_4, + .phy_id_mask = 0xffffffff, +@@ -381,6 +576,11 @@ static struct phy_driver xway_gphy[] = { + .config_intr = xway_gphy_config_intr, + .suspend = genphy_suspend, + .resume = genphy_resume, ++ .led_brightness_set = xway_gphy_led_brightness_set, ++ .led_hw_is_supported = xway_gphy_led_hw_is_supported, ++ .led_hw_control_get = xway_gphy_led_hw_control_get, ++ .led_hw_control_set = xway_gphy_led_hw_control_set, ++ .led_polarity_set = xway_gphy_led_polarity_set, + }, { + .phy_id = PHY_ID_PHY22F_1_4, + .phy_id_mask = 0xffffffff, +@@ -392,6 +592,11 @@ static struct phy_driver xway_gphy[] = { + .config_intr = xway_gphy_config_intr, + .suspend = genphy_suspend, + .resume = genphy_resume, ++ .led_brightness_set = xway_gphy_led_brightness_set, ++ .led_hw_is_supported = xway_gphy_led_hw_is_supported, ++ .led_hw_control_get = xway_gphy_led_hw_control_get, ++ .led_hw_control_set = xway_gphy_led_hw_control_set, ++ .led_polarity_set = xway_gphy_led_polarity_set, + }, { + .phy_id = PHY_ID_PHY11G_1_5, + .phy_id_mask = 0xffffffff, +@@ -402,6 +607,11 @@ static struct phy_driver xway_gphy[] = { + .config_intr = xway_gphy_config_intr, + .suspend = genphy_suspend, + .resume = genphy_resume, ++ .led_brightness_set = xway_gphy_led_brightness_set, ++ .led_hw_is_supported = xway_gphy_led_hw_is_supported, ++ .led_hw_control_get = xway_gphy_led_hw_control_get, ++ .led_hw_control_set = xway_gphy_led_hw_control_set, ++ .led_polarity_set = xway_gphy_led_polarity_set, + }, { + .phy_id = PHY_ID_PHY22F_1_5, + .phy_id_mask = 0xffffffff, +@@ -412,6 +622,11 @@ static struct phy_driver xway_gphy[] = { + .config_intr = xway_gphy_config_intr, + .suspend = genphy_suspend, + .resume = genphy_resume, ++ .led_brightness_set = xway_gphy_led_brightness_set, ++ .led_hw_is_supported = xway_gphy_led_hw_is_supported, ++ .led_hw_control_get = xway_gphy_led_hw_control_get, ++ .led_hw_control_set = xway_gphy_led_hw_control_set, ++ .led_polarity_set = xway_gphy_led_polarity_set, + }, { + .phy_id = PHY_ID_PHY11G_VR9_1_1, + .phy_id_mask = 0xffffffff, +@@ -422,6 +637,11 @@ static struct phy_driver xway_gphy[] = { + .config_intr = xway_gphy_config_intr, + .suspend = genphy_suspend, + .resume = genphy_resume, ++ .led_brightness_set = xway_gphy_led_brightness_set, ++ .led_hw_is_supported = xway_gphy_led_hw_is_supported, ++ .led_hw_control_get = xway_gphy_led_hw_control_get, ++ .led_hw_control_set = xway_gphy_led_hw_control_set, ++ .led_polarity_set = xway_gphy_led_polarity_set, + }, { + .phy_id = PHY_ID_PHY22F_VR9_1_1, + .phy_id_mask = 0xffffffff, +@@ -432,6 +652,11 @@ static struct phy_driver xway_gphy[] = { + .config_intr = xway_gphy_config_intr, + .suspend = genphy_suspend, + .resume = genphy_resume, ++ .led_brightness_set = xway_gphy_led_brightness_set, ++ .led_hw_is_supported = xway_gphy_led_hw_is_supported, ++ .led_hw_control_get = xway_gphy_led_hw_control_get, ++ .led_hw_control_set = xway_gphy_led_hw_control_set, ++ .led_polarity_set = xway_gphy_led_polarity_set, + }, { + .phy_id = PHY_ID_PHY11G_VR9_1_2, + .phy_id_mask = 0xffffffff, +@@ -442,6 +667,11 @@ static struct phy_driver xway_gphy[] = { + .config_intr = xway_gphy_config_intr, + .suspend = genphy_suspend, + .resume = genphy_resume, ++ .led_brightness_set = xway_gphy_led_brightness_set, ++ .led_hw_is_supported = xway_gphy_led_hw_is_supported, ++ .led_hw_control_get = xway_gphy_led_hw_control_get, ++ .led_hw_control_set = xway_gphy_led_hw_control_set, ++ .led_polarity_set = xway_gphy_led_polarity_set, + }, { + .phy_id = PHY_ID_PHY22F_VR9_1_2, + .phy_id_mask = 0xffffffff, +@@ -452,6 +682,11 @@ static struct phy_driver xway_gphy[] = { + .config_intr = xway_gphy_config_intr, + .suspend = genphy_suspend, + .resume = genphy_resume, ++ .led_brightness_set = xway_gphy_led_brightness_set, ++ .led_hw_is_supported = xway_gphy_led_hw_is_supported, ++ .led_hw_control_get = xway_gphy_led_hw_control_get, ++ .led_hw_control_set = xway_gphy_led_hw_control_set, ++ .led_polarity_set = xway_gphy_led_polarity_set, + }, + }; + module_phy_driver(xway_gphy); From 330321421a0a19f1299dc23d57bf884c5b44f7ac Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Fri, 4 Oct 2024 14:04:25 +0100 Subject: [PATCH 09/32] mediatek: mt7622: enable HWMON in kernel config Building HWMON as module prevents some other drivers from getting built into the kernel, e.g. mxl-gpy. Always enable HWMON and also set THERMAL_HWMON. Signed-off-by: Daniel Golle --- target/linux/mediatek/mt7622/config-6.6 | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/linux/mediatek/mt7622/config-6.6 b/target/linux/mediatek/mt7622/config-6.6 index cf445b2b7195aa..e7b6b46c84cf62 100644 --- a/target/linux/mediatek/mt7622/config-6.6 +++ b/target/linux/mediatek/mt7622/config-6.6 @@ -213,6 +213,7 @@ CONFIG_HAS_DMA=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_IOPORT_MAP=y +CONFIG_HWMON=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_MTK=y CONFIG_I2C=y @@ -464,6 +465,7 @@ CONFIG_THERMAL_GOV_BANG_BANG=y CONFIG_THERMAL_GOV_FAIR_SHARE=y CONFIG_THERMAL_GOV_STEP_WISE=y CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_HWMON=y CONFIG_THERMAL_OF=y CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THREAD_INFO_IN_TASK=y From 175bd80349de886d27f79f12cb8e562a807cb5b5 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 5 Oct 2024 21:43:48 +0100 Subject: [PATCH 10/32] mediatek: add driver for Adtran MFGINFO NVMEM layout This driver allows retrieving MAC addresses and other factory information via the NVMEM framework on Adtran devices. Signed-off-by: Daniel Golle --- target/linux/mediatek/filogic/config-6.6 | 1 + target/linux/mediatek/mt7622/config-6.6 | 2 + target/linux/mediatek/mt7623/config-6.6 | 1 + target/linux/mediatek/mt7629/config-6.6 | 1 + ...-nvmem-add-layout-for-Adtran-devices.patch | 191 ++++++++++++++++++ 5 files changed, 196 insertions(+) create mode 100644 target/linux/mediatek/patches-6.6/450-nvmem-add-layout-for-Adtran-devices.patch diff --git a/target/linux/mediatek/filogic/config-6.6 b/target/linux/mediatek/filogic/config-6.6 index 818bcfa081ea76..7cf045ade2a5e2 100644 --- a/target/linux/mediatek/filogic/config-6.6 +++ b/target/linux/mediatek/filogic/config-6.6 @@ -313,6 +313,7 @@ CONFIG_NR_CPUS=4 CONFIG_NVMEM=y CONFIG_NVMEM_BLOCK=y CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_LAYOUT_ADTRAN=y CONFIG_NVMEM_MTK_EFUSE=y CONFIG_NVMEM_SYSFS=y CONFIG_OF=y diff --git a/target/linux/mediatek/mt7622/config-6.6 b/target/linux/mediatek/mt7622/config-6.6 index e7b6b46c84cf62..c18e62476f5277 100644 --- a/target/linux/mediatek/mt7622/config-6.6 +++ b/target/linux/mediatek/mt7622/config-6.6 @@ -314,7 +314,9 @@ CONFIG_NO_HZ_COMMON=y CONFIG_NO_HZ_IDLE=y CONFIG_NR_CPUS=2 CONFIG_NVMEM=y +CONFIG_NVMEM_BLOCK=y CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_LAYOUT_ADTRAN=y CONFIG_NVMEM_MTK_EFUSE=y CONFIG_NVMEM_SYSFS=y CONFIG_OF=y diff --git a/target/linux/mediatek/mt7623/config-6.6 b/target/linux/mediatek/mt7623/config-6.6 index bb00bee8f31407..e34822d9922485 100644 --- a/target/linux/mediatek/mt7623/config-6.6 +++ b/target/linux/mediatek/mt7623/config-6.6 @@ -436,6 +436,7 @@ CONFIG_NO_HZ_IDLE=y CONFIG_NR_CPUS=4 CONFIG_NVMEM=y CONFIG_NVMEM_LAYOUTS=y +# CONFIG_NVMEM_LAYOUT_ADTRAN is not set CONFIG_NVMEM_MTK_EFUSE=y # CONFIG_NVMEM_SPMI_SDAM is not set CONFIG_NVMEM_SYSFS=y diff --git a/target/linux/mediatek/mt7629/config-6.6 b/target/linux/mediatek/mt7629/config-6.6 index 1748efab775fc6..81c07a54922569 100644 --- a/target/linux/mediatek/mt7629/config-6.6 +++ b/target/linux/mediatek/mt7629/config-6.6 @@ -239,6 +239,7 @@ CONFIG_NO_HZ_IDLE=y CONFIG_NR_CPUS=2 CONFIG_NVMEM=y CONFIG_NVMEM_LAYOUTS=y +# CONFIG_NVMEM_LAYOUT_ADTRAN is not set # CONFIG_NVMEM_MTK_EFUSE is not set CONFIG_NVMEM_SYSFS=y CONFIG_OF=y diff --git a/target/linux/mediatek/patches-6.6/450-nvmem-add-layout-for-Adtran-devices.patch b/target/linux/mediatek/patches-6.6/450-nvmem-add-layout-for-Adtran-devices.patch new file mode 100644 index 00000000000000..496fc6c53f752e --- /dev/null +++ b/target/linux/mediatek/patches-6.6/450-nvmem-add-layout-for-Adtran-devices.patch @@ -0,0 +1,191 @@ +From c22bc82183c2dea64919f975473ec518738baa3e Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Wed, 12 Jul 2023 13:38:35 +0100 +Subject: [PATCH] nvmem: add layout for Adtran devices + +Adtran stores unique factory data on GPT partitions on the eMMC. +Using blk-nvmem the 'mfginfo' partition gets exposes as NVMEM provider. + +Add layout driver to parse mfginfo, mainly to provide MAC addresses to +Ethernet and wireless interfaces. + +Variable names are converted to lower-case and '_' is replaced with '-' +in order to comply with the device tree node naming convention. +The main MAC address always ends on a 0 and up to 16 addresses are +alocated for each device to use for various interfaces. + +Implement post-processing function for 'MFG_MAC' variable ('mfg-mac' +node name in device tree) adding the nvmem cell index to the least +significant digit of the MAC address. + +Signed-off-by: Daniel Golle +--- + drivers/nvmem/layouts/Kconfig | 9 +++ + drivers/nvmem/layouts/Makefile | 1 + + drivers/nvmem/layouts/adtran.c | 135 +++++++++++++++++++++++++++++++++ + 3 files changed, 145 insertions(+) + create mode 100644 drivers/nvmem/layouts/adtran.c + +--- a/drivers/nvmem/layouts/Kconfig ++++ b/drivers/nvmem/layouts/Kconfig +@@ -8,6 +8,15 @@ if NVMEM_LAYOUTS + + menu "Layout Types" + ++config NVMEM_LAYOUT_ADTRAN ++ tristate "Adtran mfginfo layout support" ++ select GENERIC_NET_UTILS ++ help ++ Say Y here if you want to support the layout used by Adtran for ++ mfginfo. ++ ++ If unsure, say N. ++ + config NVMEM_LAYOUT_SL28_VPD + tristate "Kontron sl28 VPD layout support" + select CRC8 +--- a/drivers/nvmem/layouts/Makefile ++++ b/drivers/nvmem/layouts/Makefile +@@ -6,3 +6,4 @@ + obj-$(CONFIG_NVMEM_LAYOUT_SL28_VPD) += sl28vpd.o + obj-$(CONFIG_NVMEM_LAYOUT_ONIE_TLV) += onie-tlv.o + obj-$(CONFIG_NVMEM_LAYOUT_U_BOOT_ENV) += u-boot-env.o ++obj-$(CONFIG_NVMEM_LAYOUT_ADTRAN) += adtran.o +--- /dev/null ++++ b/drivers/nvmem/layouts/adtran.c +@@ -0,0 +1,135 @@ ++// SPDX-License-Identifier: GPL-2.0 ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * Adtran devices usually come with a main MAC address ending on 0 and ++ * hence may have up to 16 MAC addresses per device. ++ * The main MAC address is stored as variable MFG_MAC in ASCII format. ++ */ ++static int adtran_mac_address_pp(void *priv, const char *id, int index, ++ unsigned int offset, void *buf, ++ size_t bytes) ++{ ++ u8 mac[ETH_ALEN]; ++ ++ if (WARN_ON(bytes != 3 * ETH_ALEN - 1)) ++ return -EINVAL; ++ ++ if (!mac_pton(buf, mac)) ++ return -EINVAL; ++ ++ if (index) ++ eth_addr_add(mac, index); ++ ++ ether_addr_copy(buf, mac); ++ ++ return 0; ++} ++ ++static int adtran_add_cells(struct nvmem_layout *layout) ++{ ++ struct nvmem_device *nvmem = layout->nvmem; ++ struct nvmem_cell_info info; ++ struct device_node *layout_np; ++ char mfginfo[1024], *c, *t, *p; ++ int ret = -EINVAL; ++ ++ ret = nvmem_device_read(nvmem, 0, sizeof(mfginfo), mfginfo); ++ if (ret < 0) ++ return ret; ++ else if (ret != sizeof(mfginfo)) ++ return -EIO; ++ ++ layout_np = of_nvmem_layout_get_container(nvmem); ++ if (!layout_np) ++ return -ENOENT; ++ ++ c = mfginfo; ++ while (*c != 0xff) { ++ memset(&info, 0, sizeof(info)); ++ if (*c == '#') ++ goto nextline; ++ ++ t = strchr(c, '='); ++ if (!t) ++ goto nextline; ++ ++ *t = '\0'; ++ ++t; ++ info.offset = t - mfginfo; ++ /* process variable name: convert to lower-case, '_' -> '-' */ ++ p = c; ++ do { ++ *p = tolower(*p); ++ if (*p == '_') ++ *p = '-'; ++ } while (*++p); ++ info.name = c; ++ c = strchr(t, 0xa); /* find newline */ ++ if (!c) ++ break; ++ ++ info.bytes = c - t; ++ if (!strcmp(info.name, "mfg-mac")) { ++ info.raw_len = info.bytes; ++ info.bytes = ETH_ALEN; ++ info.read_post_process = adtran_mac_address_pp; ++ } ++ ++ info.np = of_get_child_by_name(layout_np, info.name); ++ ret = nvmem_add_one_cell(nvmem, &info); ++ if (ret) ++ break; ++ ++ ++c; ++ continue; ++ ++nextline: ++ c = strchr(c, 0xa); /* find newline */ ++ if (!c) ++ break; ++ ++c; ++ } ++ ++ of_node_put(layout_np); ++ ++ return ret; ++} ++ ++static int adtran_probe(struct nvmem_layout *layout) ++{ ++ layout->add_cells = adtran_add_cells; ++ ++ return nvmem_layout_register(layout); ++} ++ ++static void adtran_remove(struct nvmem_layout *layout) ++{ ++ nvmem_layout_unregister(layout); ++} ++ ++static const struct of_device_id adtran_of_match_table[] = { ++ { .compatible = "adtran,mfginfo" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, adtran_of_match_table); ++ ++static struct nvmem_layout_driver adtran_layout = { ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "adtran-layout", ++ .of_match_table = adtran_of_match_table, ++ }, ++ .probe = adtran_probe, ++ .remove = adtran_remove, ++}; ++module_nvmem_layout_driver(adtran_layout); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Daniel Golle "); ++MODULE_DESCRIPTION("NVMEM layout driver for Adtran mfginfo"); From b6d82975104a808029737d2e7c2c3d7d6b517f3e Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 5 Oct 2024 18:22:20 +0100 Subject: [PATCH 11/32] mediatek: mt7622: add Adtran SmartRG SDG-841t6 device Specification SoC: MediaTek MT7622A (2x Cortex-A53) RAM: NANYA NT5CC256M16ER-EK (512 MiB) MMC: Kioxia THGBMNG5D1LBAIT (4 GiB) ETH0: Intel/MaxLinear GPY211 (2500M/1000M/100M/10M) ETH1: Lantiq/Intel/MaxLinear PEF7071/GPY111 (1000M/100M/10M) WLAN0: MediaTek MT7915E + MT7975D 2T2R 802.11bgn/ax (2.4G) 2T2R 802.11an/ac/ax (5G L) WLAN1: MediaTek MT7915E + MT7975A 4T4R 802.11an/ac/ax (5G H) BT: BT5 provided by MT7915E+MT7975D (missing firmware) Signed-off-by: Daniel Golle --- .../lib/preinit/05_set_preinit_iface | 1 + .../dts/mt7622-smartrg-SDG-841-t6.dts | 518 ++++++++++++++++++ target/linux/mediatek/image/mt7622.mk | 11 + .../mt7622/base-files/etc/board.d/01_leds | 6 + .../mt7622/base-files/etc/board.d/02_network | 3 + .../mt7622/base-files/lib/upgrade/platform.sh | 9 + target/linux/mediatek/mt7622/config-6.6 | 3 +- 7 files changed, 550 insertions(+), 1 deletion(-) create mode 100644 target/linux/mediatek/dts/mt7622-smartrg-SDG-841-t6.dts diff --git a/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface b/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface index c982a8f1d8fc0c..0deab4248136ec 100644 --- a/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface +++ b/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface @@ -13,6 +13,7 @@ set_preinit_iface() { ip link set eth0 up ifname=eth0 ;; + smartrg,sdg-841-t6|\ smartrg,sdg-8622|\ smartrg,sdg-8632|\ smartrg,sdg-8733a) diff --git a/target/linux/mediatek/dts/mt7622-smartrg-SDG-841-t6.dts b/target/linux/mediatek/dts/mt7622-smartrg-SDG-841-t6.dts new file mode 100644 index 00000000000000..05fd74a7d302bf --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-smartrg-SDG-841-t6.dts @@ -0,0 +1,518 @@ +/* + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + * Copyright (c) 2018-2023 MediaTek Inc. + * Authors: Daniel Golle + * Chad Monroe + * Ryder Lee + * + */ + +/dts-v1/; +#include +#include +#include + +#include "mt7622.dtsi" +#include "mt6380.dtsi" + +/ { + model = "Adtran SmartRG 841-t6"; + compatible = "smartrg,sdg-841-t6", "mediatek,mt7622"; + + aliases { + ethernet0 = &gmac1; + label-mac-device = &gmac0; + led-boot = &sys_status_blue; + led-failsafe = &sys_status_blue; + led-running = &sys_status_white; + led-upgrade = &sys_status_blue; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512 root=PARTLABEL=res1"; + }; + + cpus { + cpu@0 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; + }; + + cpu@1 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&pio 102 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "wps"; + linux,code = ; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + wifi2g { + label = "wifi2g"; + gpios = <&pio 96 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0radio"; + }; + + wifi5g-1 { + label = "wifi5g"; + gpios = <&pio 97 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1radio"; + }; + + wifi5g-2 { + label = "wifi5g2"; + gpios = <&pio 98 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy2radio"; + }; + + wps { + label = "wps"; + gpios = <&pio 99 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + memory { + reg = <0x0 0x40000000 0x0 0x40000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /delete-node/ramoops@42ff0000; + + bootdata@45000000 { + no-map; + reg = <0x0 0x45000000 0x0 0x00001000>; + }; + + ramoops_reserved: ramoops1@45001000 { + no-map; + compatible = "ramoops"; + reg = <0x0 0x45001000 0x0 0x00140000>; + ftrace-size = <0x20000>; + record-size = <0x20000>; + console-size = <0x20000>; + pmsg-size = <0x80000>; + }; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +ð { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + label = "wan"; + + nvmem-cells = <&macaddr 0x0>; + nvmem-cell-names = "mac-address"; + + phy-handle = <&phy5>; + phy-mode = "2500base-x"; + phy-connection-type = "2500base-x"; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + label = "lan"; + + nvmem-cells = <&macaddr 0x1>; + nvmem-cell-names = "mac-address"; + + phy-handle = <&phy0>; + phy-mode = "rgmii-rxid"; + rx-internal-delay-ps = <2000>; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + /* PEF7071 */ + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + }; + }; + }; + + phy5: ethernet-phy@5 { + /* GPY211 */ + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <5>; + + interrupt-parent = <&pio>; + interrupts = <52 IRQ_TYPE_LEVEL_HIGH>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_WAN; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_WAN; + }; + }; + }; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + system-leds@30 { + compatible = "srg,sysled"; + reg = <0x30>; + #address-cells = <1>; + #size-cells = <0>; + + sys_status_blue: system_blue@3 { + label = "blue"; + reg = <3>; + }; + + sys_status_white: system_white@4 { + label = "white"; + reg = <4>; + }; + }; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&emmc_pins_default>; + pinctrl-1 = <&emmc_pins_uhs>; + status = "okay"; + bus-width = <8>; + max-frequency = <50000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; + non-removable; + #address-cells = <1>; + #size-cells = <0>; + + card@0 { + compatible = "mmc-card"; + reg = <0>; + + block { + partitions { + block-partition-nvram { + partnum = <3>; + partname = "nvram"; + + nvmem-layout { + compatible = "u-boot,env"; + }; + }; + + block-partition-rf { + partnum = <4>; + partname = "rf"; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom0: eeprom@0 { + reg = <0x0 0x5000>; + }; + + eeprom1: eeprom@5000 { + reg = <0x5000 0x5000>; + }; + }; + }; + + block-partition-mfginfo { + partnum = <7>; + partname = "mfginfo"; + + nvmem-layout { + compatible = "adtran,mfginfo"; + + macaddr: mfg-mac { + #nvmem-cell-cells = <1>; + }; + }; + }; + }; + }; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +&slot0 { + mt7915@0,0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&eeprom0>; + nvmem-cell-names = "eeprom"; + ieee80211-freq-limit = <2400000 5330000>; + + band@0 { + /* 2.4 GHz */ + reg = <0>; + nvmem-cells = <&macaddr 0x4>; + nvmem-cell-names = "mac-address"; + }; + + band@1 { + /* lower 5 GHz */ + reg = <1>; + nvmem-cells = <&macaddr 0xa>; + nvmem-cell-names = "mac-address"; + }; + }; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "okay"; +}; + +&slot1 { + mt7915@0,0 { + /* upper 5 GHz */ + reg = <0x0000 0 0 0 0>; + nvmem-cells = <&eeprom1>, <&macaddr 0xf>; + nvmem-cell-names = "eeprom", "mac-address"; + ieee80211-freq-limit = <5490000 5835000>; + rdd_antenna = <0x02>; + }; +}; + +&pio { + /* eMMC is shared pin with parallel NAND */ + emmc_pins_default: emmc-pins-default { + mux { + function = "emmc", "emmc_rst"; + groups = "emmc"; + }; + + /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", + * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4, + * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively + */ + conf-cmd-dat { + pins = "NDL0", "NDL1", "NDL2", + "NDL3", "NDL4", "NDL5", + "NDL6", "NDL7", "NRB"; + input-enable; + bias-pull-up; + }; + + conf-clk { + pins = "NCLE"; + bias-pull-down; + }; + }; + + emmc_pins_uhs: emmc-pins-uhs { + mux { + function = "emmc"; + groups = "emmc"; + }; + + conf-cmd-dat { + pins = "NDL0", "NDL1", "NDL2", + "NDL3", "NDL4", "NDL5", + "NDL6", "NDL7", "NRB"; + input-enable; + drive-strength = <4>; + bias-pull-up; + }; + + conf-clk { + pins = "NCLE"; + drive-strength = <4>; + bias-pull-down; + }; + }; + + eth_pins: eth-pins { + mux { + function = "eth"; + groups = "mdc_mdio", "rgmii_via_gmac2"; + }; + }; + + i2c0_pins: i2c0-pins { + mux { + function = "i2c"; + groups = "i2c0"; + }; + }; + + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; + groups = "pcie0_pad_perst", + "pcie0_1_waken", + "pcie0_1_clkreq"; + }; + }; + + pcie1_pins: pcie1-pins { + mux { + function = "pcie"; + groups = "pcie1_pad_perst"; + }; + }; + + pmic_bus_pins: pmic-bus-pins { + mux { + function = "pmic"; + groups = "pmic_bus"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0_0_tx_rx" ; + }; + }; + + uart3_pins: uart3-pins { + mux { + function = "uart"; + groups = "uart3_1_tx_rx" ; + }; + }; + + watchdog_pins: watchdog-pins { + mux { + function = "watchdog"; + groups = "watchdog"; + }; + }; +}; + +&pwrap { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_bus_pins>; + status = "okay"; +}; + +&ssusb { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&u3phy { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart3 { + status = "okay"; + + bluetooth { + compatible = "mediatek,mt7915-bluetooth"; + vcc-supply = <®_5v>; + pinctrl-names = "runtime"; + pinctrl-0 = <&uart3_pins>; + boot-gpios = <&pio 81 GPIO_ACTIVE_LOW>; + current-speed = <921600>; + }; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; + status = "okay"; +}; diff --git a/target/linux/mediatek/image/mt7622.mk b/target/linux/mediatek/image/mt7622.mk index e1d9a09c643a1f..9f5fdc86888521 100644 --- a/target/linux/mediatek/image/mt7622.mk +++ b/target/linux/mediatek/image/mt7622.mk @@ -52,6 +52,17 @@ define Build/mt7622-gpt rm $@.tmp endef +define Device/smartrg_sdg-841-t6 + DEVICE_VENDOR := Adtran + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := e2fsprogs f2fsck mkf2fs + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + DEVICE_MODEL := SDG-841-t6 + DEVICE_DTS := mt7622-smartrg-SDG-841-t6 + DEVICE_PACKAGES += kmod-mt7915e kmod-mt7915-firmware +endef +TARGET_DEVICES += smartrg_sdg-841-t6 + define Device/bananapi_bpi-r64 DEVICE_VENDOR := Bananapi DEVICE_MODEL := BPi-R64 diff --git a/target/linux/mediatek/mt7622/base-files/etc/board.d/01_leds b/target/linux/mediatek/mt7622/base-files/etc/board.d/01_leds index 7cb54186fd1e42..51d483b31fc131 100644 --- a/target/linux/mediatek/mt7622/base-files/etc/board.d/01_leds +++ b/target/linux/mediatek/mt7622/base-files/etc/board.d/01_leds @@ -11,6 +11,12 @@ linksys,e8450-ubi|\ netgear,wax206) ucidef_set_led_netdev "wan" "WAN" "inet:blue" "wan" ;; +smartrg,sdg-841-t6) + ucidef_set_led_netdev "lan-green" "LAN" "mdio-bus:00:green:lan" "lan" "link_1000" + ucidef_set_led_netdev "lan-amber" "LAN" "mdio-bus:00:amber:lan" "lan" "link_10 link_100" + ucidef_set_led_netdev "wan-green" "WAN" "mdio-bus:05:green:wan" "wan" "link_1000 link_2500" + ucidef_set_led_netdev "wan-amber" "WAN" "mdio-bus:05:amber:wan" "wan" "link_10 link_100" + ;; xiaomi,redmi-router-ax6s) ucidef_set_led_netdev "wan" "WAN" "blue:net" "wan" ;; diff --git a/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network b/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network index 6bda6e11f37360..ff4ff0c480c1f5 100644 --- a/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network @@ -20,6 +20,9 @@ mediatek_setup_interfaces() ucidef_add_switch "switch0" \ "0:lan" "1:lan" "2:lan" "3:lan" "4:wan" "6u@eth0" "5u@eth1" ;; + smartrg,sdg-841-t6) + ucidef_set_interfaces_lan_wan lan wan + ;; ubnt,unifi-6-lr*) ucidef_set_interface_lan "eth0" ;; diff --git a/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh index 61025fb380df83..2607f170e0596c 100755 --- a/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh @@ -43,6 +43,11 @@ platform_do_upgrade() { fi default_do_upgrade "$1" ;; + smartrg,sdg-841-t6) + CI_KERNPART="boot" + CI_ROOTPART="res1" + emmc_do_upgrade "$1" + ;; *) default_do_upgrade "$1" ;; @@ -67,6 +72,7 @@ platform_check_image() { elecom,wrc-x3200gst3|\ mediatek,mt7622-rfb1-ubi|\ netgear,wax206|\ + smartrg,sdg-841-t6|\ totolink,a8000ru) nand_do_platform_check "$board" "$1" return $? @@ -90,5 +96,8 @@ platform_copy_config() { emmc_copy_config fi ;; + smartrg,sdg-841-t6) + emmc_copy_config + ;; esac } diff --git a/target/linux/mediatek/mt7622/config-6.6 b/target/linux/mediatek/mt7622/config-6.6 index c18e62476f5277..138eb2aaca0e04 100644 --- a/target/linux/mediatek/mt7622/config-6.6 +++ b/target/linux/mediatek/mt7622/config-6.6 @@ -223,6 +223,7 @@ CONFIG_I2C_MT65XX=y CONFIG_ICPLUS_PHY=y CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 CONFIG_INITRAMFS_SOURCE="" +CONFIG_INTEL_XWAY_PHY=y CONFIG_IRQCHIP=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y @@ -231,7 +232,7 @@ CONFIG_IRQ_TIME_ACCOUNTING=y CONFIG_IRQ_WORK=y CONFIG_JBD2=y CONFIG_JUMP_LABEL=y -# CONFIG_LEDS_SMARTRG_LED is not set +CONFIG_LEDS_SMARTRG_LED=y CONFIG_LIBFDT=y CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_LOCK_SPIN_ON_OWNER=y From 3e6de5d77a8b8cda1e02250179d964b840c203fa Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Mon, 7 Oct 2024 15:33:21 +0100 Subject: [PATCH 12/32] mediatek: use NVMEM framework on all Adtran devices Use NVMEM framework to assign MAC addresses and WiFi EEPROM data on all Adtran SmartRG devices. Signed-off-by: Daniel Golle --- .../dts/mt7986a-smartrg-bonanza-peak.dtsi | 77 +++++++++++++++++-- .../dts/mt7988a-smartrg-mt-stuart.dtsi | 49 +++++++++++- .../dts/mt7988d-smartrg-SDG-8733A.dts | 4 + .../filogic/base-files/etc/board.d/02_network | 10 --- .../etc/hotplug.d/firmware/11-mt76-caldata | 21 ----- .../etc/hotplug.d/ieee80211/11_fix_wifi_mac | 17 ---- .../base-files/lib/preinit/10_fix_eth_mac.sh | 20 ----- 7 files changed, 119 insertions(+), 79 deletions(-) diff --git a/target/linux/mediatek/dts/mt7986a-smartrg-bonanza-peak.dtsi b/target/linux/mediatek/dts/mt7986a-smartrg-bonanza-peak.dtsi index 038a76ad73c44f..deab53dc45f325 100644 --- a/target/linux/mediatek/dts/mt7986a-smartrg-bonanza-peak.dtsi +++ b/target/linux/mediatek/dts/mt7986a-smartrg-bonanza-peak.dtsi @@ -14,8 +14,7 @@ / { aliases { serial0 = &uart0; - ethernet0 = &gmac0; - ethernet1 = &gmac1; + label-mac-device = &gmac1; led-boot = &led_status_green; led-failsafe = &led_status_red; led-running = &led_status_white; @@ -188,16 +187,17 @@ gmac0: mac@0 { compatible = "mediatek,eth-mac"; reg = <0>; - + nvmem-cells = <&macaddr 1>; + nvmem-cell-names = "mac-address"; phy-mode = "2500base-x"; }; gmac1: mac@1 { - label = "wan"; - compatible = "mediatek,eth-mac"; reg = <1>; - + label = "wan"; + nvmem-cells = <&macaddr 0>; + nvmem-cell-names = "mac-address"; phy-mode = "2500base-x"; }; @@ -254,6 +254,47 @@ no-sd; no-sdio; status = "okay"; + + card@0 { + compatible = "mmc-card"; + reg = <0>; + + block { + compatible = "block-device"; + + partitions { + block-partition-factory { + partname = "factory"; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1000>; + }; + + eeprom_factory_a0000: eeprom@a0000 { + reg = <0xa0000 0x1000>; + }; + }; + }; + + block-partition-mfginfo { + partname = "mfginfo"; + + nvmem-layout { + compatible = "adtran,mfginfo"; + + macaddr: mfg-mac { + #nvmem-cell-cells = <1>; + }; + }; + }; + }; + }; + }; }; &pcie { @@ -266,6 +307,9 @@ radio0: mt7915@0,0 { reg = <0x0000 0 0 0 0>; + + nvmem-cells = <&eeprom_factory_a0000>, <&macaddr 4>; + nvmem-cell-names = "eeprom", "mac-address"; }; }; }; @@ -275,9 +319,28 @@ }; &wifi { - status = "okay"; + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; pinctrl-names = "default"; pinctrl-0 = <&wf_2g_5g_pins>; + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + band@0 { + /* 2.4 GHz */ + reg = <0>; + nvmem-cells = <&macaddr 2>; + nvmem-cell-names = "mac-address"; + }; + + band@1 { + /* lower 5 GHz */ + reg = <1>; + nvmem-cells = <&macaddr 3>; + nvmem-cell-names = "mac-address"; + }; }; &pio { diff --git a/target/linux/mediatek/dts/mt7988a-smartrg-mt-stuart.dtsi b/target/linux/mediatek/dts/mt7988a-smartrg-mt-stuart.dtsi index ccf85fc1108757..a3db288d274d39 100644 --- a/target/linux/mediatek/dts/mt7988a-smartrg-mt-stuart.dtsi +++ b/target/linux/mediatek/dts/mt7988a-smartrg-mt-stuart.dtsi @@ -15,8 +15,7 @@ / { aliases { serial0 = &uart0; - ethernet0 = &gmac0; - ethernet1 = &gmac1; + label-mac-device = &gmac1; led-boot = &led_sys_green; led-failsafe = &led_sys_blue; led-running = &led_sys_white; @@ -250,21 +249,30 @@ }; &gmac0 { + nvmem-cells = <&macaddr 1>; + nvmem-cell-names = "mac-address"; + status = "okay"; }; &gmac1 { + nvmem-cells = <&macaddr 0>; + nvmem-cell-names = "mac-address"; label = "wan"; - status = "okay"; phy-mode = "usxgmii"; + + status = "okay"; }; &gmac2 { + nvmem-cells = <&macaddr 1>; + nvmem-cell-names = "mac-address"; label = "lan1"; - status = "okay"; phy-mode = "usxgmii"; phy-connection-type = "usxgmii"; phy = <&phy8>; + + status = "okay"; }; &gsw_phy0 { @@ -513,6 +521,18 @@ }; }; }; + + block-partition-mfginfo { + partname = "mfginfo"; + + nvmem-layout { + compatible = "adtran,mfginfo"; + + macaddr: mfg-mac { + #nvmem-cell-cells = <1>; + }; + }; + }; }; }; }; @@ -532,6 +552,27 @@ nvmem-cells = <&eeprom_factory_0>; nvmem-cell-names = "eeprom"; ieee80211-freq-limit = <2400000 2500000>, <5170000 5835000>, <5945000 7125000>; + + band@0 { + /* 2.4 GHz */ + reg = <0>; + nvmem-cells = <&macaddr 4>; + nvmem-cell-names = "mac-address"; + }; + + band@1 { + /* 5 GHz */ + reg = <1>; + nvmem-cells = <&macaddr 10>; + nvmem-cell-names = "mac-address"; + }; + + band@2 { + /* 6 GHz */ + reg = <2>; + nvmem-cells = <&macaddr 6>; + nvmem-cell-names = "mac-address"; + }; }; }; }; diff --git a/target/linux/mediatek/dts/mt7988d-smartrg-SDG-8733A.dts b/target/linux/mediatek/dts/mt7988d-smartrg-SDG-8733A.dts index 54fbbea0ba4253..b72ef48bea7faf 100644 --- a/target/linux/mediatek/dts/mt7988d-smartrg-SDG-8733A.dts +++ b/target/linux/mediatek/dts/mt7988d-smartrg-SDG-8733A.dts @@ -62,6 +62,8 @@ &gmac1 { label = "lan"; + nvmem-cells = <&macaddr 1>; + nvmem-cell-names = "mac-address"; phy-mode = "internal"; phy-connection-type = "internal"; phy = <&int_2p5g_phy>; @@ -69,6 +71,8 @@ &gmac2 { label = "wan"; + nvmem-cells = <&macaddr 0>; + nvmem-cell-names = "mac-address"; phy-mode = "usxgmii"; phy-connection-type = "usxgmii"; phy = <&phy8>; diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index 74ee571bc02865..d532d75b99ea1e 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -162,16 +162,6 @@ mediatek_setup_macs() wan_mac=$label_mac lan_mac=$(macaddr_add "$label_mac" 1) ;; - smartrg,sdg-8612|\ - smartrg,sdg-8614|\ - smartrg,sdg-8622|\ - smartrg,sdg-8632|\ - smartrg,sdg-8733|\ - smartrg,sdg-8734) - label_mac=$(mmc_get_mac_ascii mfginfo MFG_MAC) - wan_mac=$label_mac - lan_mac=$(macaddr_add "$label_mac" 1) - ;; xiaomi,mi-router-ax3000t|\ xiaomi,mi-router-ax3000t-ubootmod|\ xiaomi,mi-router-wr30u-stock|\ diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata index c6900e6ebd7510..d97e5c8354813d 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata @@ -7,21 +7,6 @@ board=$(board_name) case "$FIRMWARE" in -"mediatek/mt7915_eeprom.bin") - case "$board" in - smartrg,sdg-8622) - caldata_extract_mmc "factory" 0xa0000 0x1000 - ;; - esac - ;; -"mediatek/mt7916_eeprom.bin") - case "$board" in - acer,predator-w6|\ - smartrg,sdg-8632) - caldata_extract_mmc "factory" 0xa0000 0x1000 - ;; - esac - ;; "mediatek/mt7981_eeprom_mt7976_dbdc.bin") case "$board" in ubnt,unifi-6-plus) @@ -36,12 +21,6 @@ case "$FIRMWARE" in ln -sf /tmp/tp_data/MT7986_EEPROM.bin \ /lib/firmware/$FIRMWARE ;; - smartrg,sdg-8612|\ - smartrg,sdg-8614|\ - smartrg,sdg-8622|\ - smartrg,sdg-8632) - caldata_extract_mmc "factory" 0x0 0x1000 - ;; esac ;; "mediatek/mt7986_eeprom_mt7976.bin") diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac index 3600e323409a37..3042858353a7cf 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac @@ -139,23 +139,6 @@ case "$board" in [ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress ;; - smartrg,sdg-8612|\ - smartrg,sdg-8614|\ - smartrg,sdg-8622|\ - smartrg,sdg-8632) - addr=$(mmc_get_mac_ascii mfginfo MFG_MAC) - [ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress - [ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress - [ "$PHYNBR" = "2" ] && macaddr_add $addr 4 > /sys${DEVPATH}/macaddress - ;; - smartrg,sdg-8733|\ - smartrg,sdg-8733a|\ - smartrg,sdg-8734) - addr=$(mmc_get_mac_ascii mfginfo MFG_MAC) - [ "$PHYNBR" = "0" ] && macaddr_add $addr 4 > /sys${DEVPATH}/macaddress - [ "$PHYNBR" = "1" ] && macaddr_add $addr a > /sys${DEVPATH}/macaddress - [ "$PHYNBR" = "2" ] && macaddr_add $addr 6 > /sys${DEVPATH}/macaddress - ;; tplink,tl-xdr4288|\ tplink,tl-xdr6086|\ tplink,tl-xdr6088) diff --git a/target/linux/mediatek/filogic/base-files/lib/preinit/10_fix_eth_mac.sh b/target/linux/mediatek/filogic/base-files/lib/preinit/10_fix_eth_mac.sh index 65bd5178242c1b..0497d7dfa2474f 100644 --- a/target/linux/mediatek/filogic/base-files/lib/preinit/10_fix_eth_mac.sh +++ b/target/linux/mediatek/filogic/base-files/lib/preinit/10_fix_eth_mac.sh @@ -22,26 +22,6 @@ preinit_set_mac_address() { addr=$(get_mac_binary "/tmp/tp_data/default-mac" 0) ip link set dev eth1 address "$(macaddr_add $addr 1)" ;; - smartrg,sdg-8612|\ - smartrg,sdg-8614|\ - smartrg,sdg-8733|\ - smartrg,sdg-8734) - addr=$(mmc_get_mac_ascii mfginfo MFG_MAC) - lan_addr=$(macaddr_add $addr 1) - ip link set dev wan address "$addr" - ip link set dev eth0 address "$lan_addr" - ip link set dev lan1 address "$lan_addr" - ip link set dev lan2 address "$lan_addr" - ip link set dev lan3 address "$lan_addr" - ip link set dev lan4 address "$lan_addr" - ;; - smartrg,sdg-8622|\ - smartrg,sdg-8632|\ - smartrg,sdg-8733a) - addr=$(mmc_get_mac_ascii mfginfo MFG_MAC) - ip link set dev wan address "$addr" - ip link set dev lan address "$(macaddr_add $addr 1)" - ;; *) ;; esac From 4d81f40d630ff3ac38ac6fadeaf815d15abe403a Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 15 Oct 2024 21:15:19 +0100 Subject: [PATCH 13/32] generic: fix kernel version and ordering of Aquantia backports Two patches declared as accepted in v6.13 were already accepted for v6.12. Fix filenames and order of patches applied. Reported-by: Mieczyslaw Nalewaj Fixes: 8cc049cec2 ("generic: phy: aquantia: move accepted patches to backport-6.6") Signed-off-by: Daniel Golle --- ...7-v6.12-net-phy-aquantia-fix-setting-active_low-bit.patch} | 0 ...hy-aquantia-fix-applying-active_low-bit-after-reset.patch} | 4 ++-- ...3-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch} | 2 +- ...et-phy-aquantia-fix-return-value-check-in-aqr107_co.patch} | 0 4 files changed, 3 insertions(+), 3 deletions(-) rename target/linux/generic/backport-6.6/{839-v6.13-net-phy-aquantia-fix-setting-active_low-bit.patch => 837-v6.12-net-phy-aquantia-fix-setting-active_low-bit.patch} (100%) rename target/linux/generic/backport-6.6/{840-v6.13-net-phy-aquantia-fix-applying-active_low-bit-after-reset.patch => 838-v6.12-net-phy-aquantia-fix-applying-active_low-bit-after-reset.patch} (95%) rename target/linux/generic/backport-6.6/{837-v6.13-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch => 839-v6.13-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch} (98%) rename target/linux/generic/backport-6.6/{838-v6.13-net-phy-aquantia-fix-return-value-check-in-aqr107_co.patch => 840-v6.13-net-phy-aquantia-fix-return-value-check-in-aqr107_co.patch} (100%) diff --git a/target/linux/generic/backport-6.6/839-v6.13-net-phy-aquantia-fix-setting-active_low-bit.patch b/target/linux/generic/backport-6.6/837-v6.12-net-phy-aquantia-fix-setting-active_low-bit.patch similarity index 100% rename from target/linux/generic/backport-6.6/839-v6.13-net-phy-aquantia-fix-setting-active_low-bit.patch rename to target/linux/generic/backport-6.6/837-v6.12-net-phy-aquantia-fix-setting-active_low-bit.patch diff --git a/target/linux/generic/backport-6.6/840-v6.13-net-phy-aquantia-fix-applying-active_low-bit-after-reset.patch b/target/linux/generic/backport-6.6/838-v6.12-net-phy-aquantia-fix-applying-active_low-bit-after-reset.patch similarity index 95% rename from target/linux/generic/backport-6.6/840-v6.13-net-phy-aquantia-fix-applying-active_low-bit-after-reset.patch rename to target/linux/generic/backport-6.6/838-v6.12-net-phy-aquantia-fix-applying-active_low-bit-after-reset.patch index 6d71b3d7a52f80..5c3494ae331631 100644 --- a/target/linux/generic/backport-6.6/840-v6.13-net-phy-aquantia-fix-applying-active_low-bit-after-reset.patch +++ b/target/linux/generic/backport-6.6/838-v6.12-net-phy-aquantia-fix-applying-active_low-bit-after-reset.patch @@ -49,7 +49,7 @@ Reviewed-by: Russell King (Oracle) --- a/drivers/net/phy/aquantia/aquantia_main.c +++ b/drivers/net/phy/aquantia/aquantia_main.c -@@ -530,7 +530,7 @@ static int aqr107_config_init(struct phy +@@ -501,7 +501,7 @@ static int aqr107_config_init(struct phy { struct aqr107_priv *priv = phydev->priv; u32 led_active_low; @@ -58,7 +58,7 @@ Reviewed-by: Russell King (Oracle) /* Check that the PHY interface type is compatible */ if (phydev->interface != PHY_INTERFACE_MODE_SGMII && -@@ -570,10 +570,9 @@ static int aqr107_config_init(struct phy +@@ -537,10 +537,9 @@ static int aqr107_config_init(struct phy /* Restore LED polarity state after reset */ for_each_set_bit(led_active_low, &priv->leds_active_low, AQR_MAX_LEDS) { diff --git a/target/linux/generic/backport-6.6/837-v6.13-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch b/target/linux/generic/backport-6.6/839-v6.13-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch similarity index 98% rename from target/linux/generic/backport-6.6/837-v6.13-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch rename to target/linux/generic/backport-6.6/839-v6.13-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch index 9522bcaa4518ff..c1655ce71e74db 100644 --- a/target/linux/generic/backport-6.6/837-v6.13-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch +++ b/target/linux/generic/backport-6.6/839-v6.13-net-phy-aquantia-allow-forcing-order-of-MDI-pairs.patch @@ -104,4 +104,4 @@ Signed-off-by: Jakub Kicinski + /* Restore LED polarity state after reset */ for_each_set_bit(led_active_low, &priv->leds_active_low, AQR_MAX_LEDS) { - ret = aqr_phy_led_active_low_set(phydev, index, led_active_low); + ret = aqr_phy_led_active_low_set(phydev, led_active_low, true); diff --git a/target/linux/generic/backport-6.6/838-v6.13-net-phy-aquantia-fix-return-value-check-in-aqr107_co.patch b/target/linux/generic/backport-6.6/840-v6.13-net-phy-aquantia-fix-return-value-check-in-aqr107_co.patch similarity index 100% rename from target/linux/generic/backport-6.6/838-v6.13-net-phy-aquantia-fix-return-value-check-in-aqr107_co.patch rename to target/linux/generic/backport-6.6/840-v6.13-net-phy-aquantia-fix-return-value-check-in-aqr107_co.patch From 5fd4743d4c4d2f8e0cc92d2397ea94c232ae9a8a Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Thu, 19 Sep 2024 23:10:18 +0800 Subject: [PATCH 14/32] mediatek: filogic: fix network config for mt7986b-rfb Fix the network configuration according to the device tree. Signed-off-by: Chukun Pan --- target/linux/mediatek/filogic/base-files/etc/board.d/02_network | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index d532d75b99ea1e..40d1b504e34f39 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -79,7 +79,7 @@ mediatek_setup_interfaces() ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan6" "eth1 wan" ;; mediatek,mt7986b-rfb) - ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" eth1 + ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3 lan4" eth1 ;; mediatek,mt7988a-rfb) ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3 eth2" eth1 From e98987048ad73012cb29993c39c2de8682d64f9b Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Fri, 20 Sep 2024 23:10:26 +0800 Subject: [PATCH 15/32] mediatek: filogic: reorder alphabetically Reorder scripts to keep alphabetical order. Signed-off-by: Chukun Pan --- .../filogic/base-files/etc/board.d/01_leds | 12 +++--- .../filogic/base-files/etc/board.d/02_network | 40 +++++++++---------- .../base-files/lib/upgrade/platform.sh | 14 +++---- target/linux/mediatek/image/filogic.mk | 9 ++--- 4 files changed, 35 insertions(+), 40 deletions(-) diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds index 1437a120f56ed5..dad5c293dec377 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/01_leds @@ -105,16 +105,16 @@ smartrg,sdg-8733a) ucidef_set_led_netdev "wan-orange" "WAN" "mdio-bus:08:orange:wan" "wan" "link_100 link_1000" ucidef_set_led_netdev "wan-white" "WAN" "mdio-bus:08:white:wan" "wan" "link_10000" ;; -wavlink,wl-wn586x3) - ucidef_set_led_netdev "lan-1" "lan-1" "blue:lan-1" "lan1" "link tx rx" - ucidef_set_led_netdev "lan-2" "lan-2" "blue:lan-2" "lan2" "link tx rx" - ucidef_set_led_netdev "wan" "wan" "blue:wan" "eth1" "link tx rx" - ;; tplink,re6000xd) ucidef_set_led_netdev "lan-1" "lan-1" "blue:lan-0" "lan1" "link tx rx" ucidef_set_led_netdev "lan-2" "lan-2" "blue:lan-1" "lan2" "link tx rx" ucidef_set_led_netdev "eth1" "lan-3" "blue:lan-2" "eth1" "link tx rx" ;; +wavlink,wl-wn586x3) + ucidef_set_led_netdev "lan-1" "lan-1" "blue:lan-1" "lan1" "link tx rx" + ucidef_set_led_netdev "lan-2" "lan-2" "blue:lan-2" "lan2" "link tx rx" + ucidef_set_led_netdev "wan" "wan" "blue:wan" "eth1" "link tx rx" + ;; xiaomi,mi-router-wr30u-stock|\ xiaomi,mi-router-wr30u-ubootmod) ucidef_set_led_netdev "wan" "wan" "blue:wan" "wan" "link tx rx" @@ -132,7 +132,7 @@ zyxel,ex5601-t0-ubootmod) ucidef_set_led_netdev "wan" "WAN" "green:inet" "eth1" "link tx rx" ucidef_set_led_netdev "wifi-24g" "WIFI-2.4G" "green:wifi24g" "phy0-ap0" "link tx rx" ucidef_set_led_netdev "wifi-5g" "WIFI-5G" "green:wifi5g" "phy1-ap0" "link tx rx" - ;; + ;; esac board_config_flush diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index 40d1b504e34f39..af5c4ceafee131 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -8,9 +8,6 @@ mediatek_setup_interfaces() local board="$1" case $board in - acelink,ew-7886cax) - ucidef_set_interface_lan "eth0" "dhcp" - ;; abt,asr3000|\ cmcc,rax3000m|\ h3c,magic-nx30-pro|\ @@ -18,6 +15,9 @@ mediatek_setup_interfaces() zbtlink,zbt-z8103ax) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" eth1 ;; + acelink,ew-7886cax) + ucidef_set_interface_lan "eth0" "dhcp" + ;; acer,predator-w6) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 game" eth1 ;; @@ -36,10 +36,16 @@ mediatek_setup_interfaces() netcore,n60|\ ruijie,rg-x60-pro|\ unielec,u7981-01*|\ - zbtlink,zbt-z8102ax) + zbtlink,zbt-z8102ax|\ + zyxel,ex5601-t0-stock|\ + zyxel,ex5601-t0-ubootmod) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" eth1 ;; - asus,tuf-ax6000) + asus,tuf-ax6000|\ + glinet,gl-mt6000|\ + tplink,tl-xdr4288|\ + tplink,tl-xdr6088|\ + tplink,tl-xtr8488) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5" eth1 ;; bananapi,bpi-r3) @@ -56,6 +62,13 @@ mediatek_setup_interfaces() comfast,cf-e393ax) ucidef_set_interfaces_lan_wan "lan1" eth1 ;; + cudy,ap3000outdoor-v1|\ + cudy,re3000-v1|\ + netgear,wax220|\ + ubnt,unifi-6-plus|\ + zyxel,nwa50ax-pro) + ucidef_set_interface_lan "eth0" + ;; cudy,m3000-v1|\ cudy,tr3000-v1|\ glinet,gl-mt2500|\ @@ -69,12 +82,6 @@ mediatek_setup_interfaces() dlink,aquila-pro-ai-m30-a1) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" internet ;; - glinet,gl-mt6000|\ - tplink,tl-xdr4288|\ - tplink,tl-xdr6088|\ - tplink,tl-xtr8488) - ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5" eth1 - ;; mediatek,mt7986a-rfb) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan6" "eth1 wan" ;; @@ -87,13 +94,6 @@ mediatek_setup_interfaces() mercusys,mr90x-v1) ucidef_set_interfaces_lan_wan "lan0 lan1 lan2" eth1 ;; - cudy,ap3000outdoor-v1|\ - cudy,re3000-v1|\ - netgear,wax220|\ - ubnt,unifi-6-plus|\ - zyxel,nwa50ax-pro) - ucidef_set_interface_lan "eth0" - ;; smartrg,sdg-8622|\ smartrg,sdg-8632|\ smartrg,sdg-8733a|\ @@ -115,10 +115,6 @@ mediatek_setup_interfaces() xiaomi,redmi-router-ax6000-ubootmod) ucidef_set_interfaces_lan_wan "lan2 lan3 lan4" wan ;; - zyxel,ex5601-t0-stock|\ - zyxel,ex5601-t0-ubootmod) - ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" eth1 - ;; *) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" wan ;; diff --git a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh index 429728392a1dbe..edc045656639c2 100755 --- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh @@ -131,13 +131,6 @@ platform_do_upgrade() { EMMC_ROOT_DEV="$(cmdline_get_var root)" emmc_do_upgrade "$1" ;; - xiaomi,mi-router-ax3000t|\ - xiaomi,mi-router-wr30u-stock|\ - xiaomi,redmi-router-ax6000-stock) - CI_KERN_UBIPART=ubi_kernel - CI_ROOT_UBIPART=ubi - nand_do_upgrade "$1" - ;; unielec,u7981-01*) local rootdev="$(cmdline_get_var root)" rootdev="${rootdev##*/}" @@ -155,6 +148,13 @@ platform_do_upgrade() { ;; esac ;; + xiaomi,mi-router-ax3000t|\ + xiaomi,mi-router-wr30u-stock|\ + xiaomi,redmi-router-ax6000-stock) + CI_KERN_UBIPART=ubi_kernel + CI_ROOT_UBIPART=ubi + nand_do_upgrade "$1" + ;; *) nand_do_upgrade "$1" ;; diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index 3e10003e4c2b73..83f1336444d8c6 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -83,6 +83,10 @@ define Build/append-gl-metadata } endef +define Build/append-openwrt-one-eeprom + dd if=$(STAGING_DIR_IMAGE)/mt7981_eeprom_mt7976_dbdc.bin >> $@ +endef + define Build/zyxel-nwa-fit-filogic $(TOPDIR)/scripts/mkits-zyxel-fit-filogic.sh \ $@.its $@ "80 e1 ff ff ff ff ff ff ff ff" @@ -1047,10 +1051,6 @@ define Device/openembed_som7981 endef TARGET_DEVICES += openembed_som7981 -define Build/append-openwrt-one-eeprom - dd if=$(STAGING_DIR_IMAGE)/mt7981_eeprom_mt7976_dbdc.bin >> $@ -endef - define Device/openwrt_one DEVICE_VENDOR := OpenWrt DEVICE_MODEL := One @@ -1404,7 +1404,6 @@ define Device/yuncore_ax835 endef TARGET_DEVICES += yuncore_ax835 - define Device/zbtlink_zbt-z8102ax DEVICE_VENDOR := Zbtlink DEVICE_MODEL := ZBT-Z8102AX From 7e51d6a4c85de575654c49f410ce3e173176d1a9 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Wed, 16 Oct 2024 00:10:28 +0100 Subject: [PATCH 16/32] mediatek: mt7622: add netdev rename preinit script Add preinit script to rename network interfaces according to the label provided in Device Tree. Fixes: b6d8297510 ("mediatek: mt7622: add Adtran SmartRG SDG-841t6 device") Signed-off-by: Daniel Golle --- .../base-files/lib/preinit/04_set_netdev_label | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 target/linux/mediatek/mt7622/base-files/lib/preinit/04_set_netdev_label diff --git a/target/linux/mediatek/mt7622/base-files/lib/preinit/04_set_netdev_label b/target/linux/mediatek/mt7622/base-files/lib/preinit/04_set_netdev_label new file mode 100644 index 00000000000000..110e023b962d3d --- /dev/null +++ b/target/linux/mediatek/mt7622/base-files/lib/preinit/04_set_netdev_label @@ -0,0 +1,15 @@ +set_netdev_labels() { + local dir + local label + local netdev + + for dir in /sys/class/net/*; do + [ -r "$dir/of_node/label" ] || continue + read -r label < "$dir/of_node/label" + netdev="${dir##*/}" + [ "$netdev" = "$label" ] && continue + ip link set "$netdev" name "$label" + done +} + +boot_hook_add preinit_main set_netdev_labels From 92ca322dd1f48158b8829fec59319a12e4ae4295 Mon Sep 17 00:00:00 2001 From: Jonas Jelonek Date: Tue, 15 Oct 2024 20:52:35 +0200 Subject: [PATCH 17/32] uboot-mediatek: add noncached_set_region prototype to fix build Building uboot-mediatek fails with GCC-14, uboot v2024.10 and CONFIG_SYS_NONCACHED_MEMORY defined with error: cmd/cache.c: In function 'do_dcache': cmd/cache.c:57:25: error: implicit declaration of function 'noncached_set_region' [-Wimplicit-function-declaration] This is caused by upstream commit 7d6cee2cd0e2e2507aca1e3a6fe0e2cb241a116e ("cmd: cache: Remove weak functions") as this removes weak functions in favor of arch-specific definitions. This patch adds the function prototype for `noncached_set_region` to arch-specific header for ARM. It also adds an include in cmd/cache.c to make the function available there. Fixes: #16697 Fixes: f8c22c9bff ("uboot-mediatek: update to U-Boot 2024.10") Signed-off-by: Jonas Jelonek [@dangowrt refreshed patch] Signed-off-by: Daniel Golle --- ...ed_set_region-prototype-to-fix-build.patch | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 package/boot/uboot-mediatek/patches/455-arm-provide-noncached_set_region-prototype-to-fix-build.patch diff --git a/package/boot/uboot-mediatek/patches/455-arm-provide-noncached_set_region-prototype-to-fix-build.patch b/package/boot/uboot-mediatek/patches/455-arm-provide-noncached_set_region-prototype-to-fix-build.patch new file mode 100644 index 00000000000000..ba04f608b45eca --- /dev/null +++ b/package/boot/uboot-mediatek/patches/455-arm-provide-noncached_set_region-prototype-to-fix-build.patch @@ -0,0 +1,43 @@ +From aab8e6cf7afbbcef60593c6b1795fa5d8e78e597 Mon Sep 17 00:00:00 2001 +From: Jonas Jelonek +Date: Tue, 15 Oct 2024 20:02:25 +0200 +Subject: [PATCH] arm: provide noncached_set_region prototype to fix build + +Due to the removal of weak functions in 7d6cee2cd0 ("cmd: cache: Remove +weak function"), uboot fails to compile after updating to v2024.10 for +mediatek target in OpenWrt with GCC-14 with error: +cmd/cache.c: In function 'do_dcache': +cmd/cache.c:57:25: error: implicit declaration of function + 'noncached_set_region' [-Wimplicit-function-declaration] + +Thus, provide a prototype in arm's include/asm/system.h to fix a build +error in cmd/cache.c, since related prototypes are also located there. +Also add an include of asm/system.h in cmd/cache.c have the function +available there. + +Signed-off-by: Jonas Jelonek +--- + arch/arm/include/asm/system.h | 1 + + cmd/cache.c | 1 + + 2 files changed, 2 insertions(+) + +--- a/arch/arm/include/asm/system.h ++++ b/arch/arm/include/asm/system.h +@@ -658,6 +658,7 @@ void mmu_set_region_dcache_behaviour(phy + * Return: 0 if OK + */ + int noncached_init(void); ++void noncached_set_region(void); + + phys_addr_t noncached_alloc(size_t size, size_t align); + #endif /* CONFIG_SYS_NONCACHED_MEMORY */ +--- a/cmd/cache.c ++++ b/cmd/cache.c +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + + static int parse_argv(const char *); + From 74238413b13dbf58d9da6836f9a41179d6bcb02e Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Wed, 16 Oct 2024 09:55:18 +0200 Subject: [PATCH 18/32] ramips: disable CONFIG_LIST_HARDENED on MT7620 In #16396, crashes were reported on MT7620, which were introduced by enabling CONFIG_LIST_HARDENED. The cause seems to be random memory corruption somewhere in the kernel. Unfortunately the crash traces do not point to the real cause of the crash in any way. Since MT7620 is really ancient hardware that likely only has few users left, I don't expect that anybody will invest a significant amount of time to track down the real cause. Because of that, let's disable CONFIG_LIST_HARDENED on this target only, and leave it enabled on all other platforms. Fixes: #16396 Signed-off-by: Felix Fietkau --- target/linux/ramips/mt7620/config-6.6 | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/ramips/mt7620/config-6.6 b/target/linux/ramips/mt7620/config-6.6 index 20bba0c5a47dcf..606fc51eefc8b7 100644 --- a/target/linux/ramips/mt7620/config-6.6 +++ b/target/linux/ramips/mt7620/config-6.6 @@ -102,6 +102,7 @@ CONFIG_IRQ_INTC=y CONFIG_IRQ_MIPS_CPU=y CONFIG_IRQ_WORK=y CONFIG_LIBFDT=y +# CONFIG_LIST_HARDENED is not set CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_MARVELL_PHY=y CONFIG_MDIO_BUS=y From f20893a6bcf75268e4548fb73c23f956f3843764 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Wed, 16 Oct 2024 11:14:54 +0200 Subject: [PATCH 19/32] opkg: update to Git HEAD (2024-10-16) 38eccbb1fd69 libopkg: allow install package from https and ftps Link: https://github.com/openwrt/openwrt/pull/16715 Signed-off-by: Robert Marko --- package/system/opkg/Makefile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/package/system/opkg/Makefile b/package/system/opkg/Makefile index 047d7237508e9d..9fea969ae96e0b 100644 --- a/package/system/opkg/Makefile +++ b/package/system/opkg/Makefile @@ -7,14 +7,14 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk PKG_NAME:=opkg -PKG_RELEASE:=2 +PKG_RELEASE:=1 PKG_FLAGS:=essential PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/opkg-lede.git -PKG_SOURCE_DATE:=2022-02-24 -PKG_SOURCE_VERSION:=d038e5b6d155784575f62a66a8bb7e874173e92e -PKG_MIRROR_HASH:=6889f7d322996f9291f42d7d6a5877d256b91d4a01d6015cebaae9227702eb43 +PKG_SOURCE_DATE:=2024-10-16 +PKG_SOURCE_VERSION:=38eccbb1fd694d4798ac1baf88f9ba83d1eac616 +PKG_MIRROR_HASH:=de58ff1c99c14789f9ba8946623c8c1e58d022e7e2a659d6f97c6fde54f2c4f4 PKG_LICENSE:=GPL-2.0 PKG_LICENSE_FILES:=COPYING From bf059f7108e75fdec618a272ab8c52d4780aafed Mon Sep 17 00:00:00 2001 From: Paul Spooren Date: Sat, 17 Aug 2024 16:23:54 +0200 Subject: [PATCH 20/32] prereq-build: add Python 3.12 support This reverts commit 09b7e1955c92e0b05197174b7bd4aef2c4073a35. Signed-off-by: Paul Spooren Link: https://github.com/openwrt/openwrt/pull/16699 Signed-off-by: Robert Marko --- include/prereq-build.mk | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/prereq-build.mk b/include/prereq-build.mk index 49340ce3e441cc..2378f5ad90c961 100644 --- a/include/prereq-build.mk +++ b/include/prereq-build.mk @@ -182,6 +182,7 @@ $(eval $(call SetupHostCommand,perl,Please install Perl 5.x, \ perl --version | grep "perl.*v5")) $(eval $(call SetupHostCommand,python,Please install Python >= 3.7, \ + python3.12 -V 2>&1 | grep 'Python 3', \ python3.11 -V 2>&1 | grep 'Python 3', \ python3.10 -V 2>&1 | grep 'Python 3', \ python3.9 -V 2>&1 | grep 'Python 3', \ @@ -190,6 +191,7 @@ $(eval $(call SetupHostCommand,python,Please install Python >= 3.7, \ python3 -V 2>&1 | grep -E 'Python 3\.([7-9]|[0-9][0-9])\.?')) $(eval $(call SetupHostCommand,python3,Please install Python >= 3.7, \ + python3.12 -V 2>&1 | grep 'Python 3', \ python3.11 -V 2>&1 | grep 'Python 3', \ python3.10 -V 2>&1 | grep 'Python 3', \ python3.9 -V 2>&1 | grep 'Python 3', \ From 8191c8980f04087eaf2921dc327fff219999bd55 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Mon, 9 Jan 2023 16:38:05 +0100 Subject: [PATCH 21/32] prereq-build: limit python distutils check to Link: https://github.com/openwrt/openwrt/pull/16699 Signed-off-by: Robert Marko --- include/prereq-build.mk | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/prereq-build.mk b/include/prereq-build.mk index 2378f5ad90c961..8b138cfc44e98a 100644 --- a/include/prereq-build.mk +++ b/include/prereq-build.mk @@ -201,7 +201,8 @@ $(eval $(call SetupHostCommand,python3,Please install Python >= 3.7, \ $(eval $(call TestHostCommand,python3-distutils, \ Please install the Python3 distutils module, \ - $(STAGING_DIR_HOST)/bin/python3 -c 'from distutils import util')) + printf 'from sys import version_info\nif version_info < (3, 12):\n\tfrom distutils import util' | \ + $(STAGING_DIR_HOST)/bin/python3 -)) $(eval $(call TestHostCommand,python3-stdlib, \ Please install the Python3 stdlib module, \ From 7ae883c29da8b3efc2528d10e1db271dc05e1923 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Wed, 9 Oct 2024 23:10:26 +0800 Subject: [PATCH 22/32] linux-firmware: update Realtek RTW89 firmware Add RealTek RTL8922AE firmware package. The rtw89 driver uses rtw8852b_fw-1.bin starting from kernel 6.4[1], remove the old one. Also note that in the kernel 6.12, rtw8852c and rtw8922a should use fw-1.bin [2][3]. [1] https://github.com/torvalds/linux/commit/ffde7f3476 [2] https://github.com/torvalds/linux/commit/45ae0e8cf8 [3] https://github.com/torvalds/linux/commit/6ca6b918f2 Signed-off-by: Chukun Pan Suggested-by: Hauke Mehrtens Link: https://github.com/openwrt/openwrt/pull/16700 Signed-off-by: Hauke Mehrtens --- package/firmware/linux-firmware/realtek.mk | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/package/firmware/linux-firmware/realtek.mk b/package/firmware/linux-firmware/realtek.mk index 5ba679d404922d..0889796a1282d2 100644 --- a/package/firmware/linux-firmware/realtek.mk +++ b/package/firmware/linux-firmware/realtek.mk @@ -180,7 +180,6 @@ $(eval $(call BuildPackage,rtl8852ae-firmware)) Package/rtl8852be-firmware = $(call Package/firmware-default,RealTek RTL8852BE firmware) define Package/rtl8852be-firmware/install $(INSTALL_DIR) $(1)/lib/firmware/rtw89 - $(INSTALL_DATA) $(PKG_BUILD_DIR)/rtw89/rtw8852b_fw.bin $(1)/lib/firmware/rtw89 $(INSTALL_DATA) $(PKG_BUILD_DIR)/rtw89/rtw8852b_fw-1.bin $(1)/lib/firmware/rtw89 endef $(eval $(call BuildPackage,rtl8852be-firmware)) @@ -191,3 +190,10 @@ define Package/rtl8852ce-firmware/install $(INSTALL_DATA) $(PKG_BUILD_DIR)/rtw89/rtw8852c_fw.bin $(1)/lib/firmware/rtw89 endef $(eval $(call BuildPackage,rtl8852ce-firmware)) + +Package/rtl8922ae-firmware = $(call Package/firmware-default,RealTek RTL8922AE firmware) +define Package/rtl8922ae-firmware/install + $(INSTALL_DIR) $(1)/lib/firmware/rtw89 + $(INSTALL_DATA) $(PKG_BUILD_DIR)/rtw89/rtw8922a_fw.bin $(1)/lib/firmware/rtw89 +endef +$(eval $(call BuildPackage,rtl8922ae-firmware)) From 84e47e9cc7085262f309eb0870f0041bbf181404 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Thu, 10 Oct 2024 23:10:28 +0800 Subject: [PATCH 23/32] mac80211: realtek: rtw89: add RTL8922AE support Add the Realtek RTL8922AE support to rtw89 package. The 8922A is a 802.11be chip that can support 2/5/6GHz 160MHz. Signed-off-by: Chukun Pan Link: https://github.com/openwrt/openwrt/pull/16700 Signed-off-by: Hauke Mehrtens --- package/kernel/mac80211/realtek.mk | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/package/kernel/mac80211/realtek.mk b/package/kernel/mac80211/realtek.mk index 5aeddb99bc073d..2eaed210e1cae1 100644 --- a/package/kernel/mac80211/realtek.mk +++ b/package/kernel/mac80211/realtek.mk @@ -4,7 +4,8 @@ PKG_DRIVERS += \ rtl8xxxu rtw88 rtw88-pci rtw88-usb rtw88-sdio rtw88-8821c rtw88-8822b rtw88-8822c \ rtw88-8723x rtw88-8723d rtw88-8821ce rtw88-8821cu rtw88-8822be rtw88-8822bu \ rtw88-8822ce rtw88-8822cu rtw88-8723de rtw88-8723ds rtw88-8723du \ - rtw89 rtw89-pci rtw89-8851be rtw89-8852ae rtw89-8852b-common rtw89-8852be rtw89-8852ce + rtw89 rtw89-pci rtw89-8851be rtw89-8852ae rtw89-8852b-common \ + rtw89-8852be rtw89-8852ce rtw89-8922ae config-$(call config_package,rtlwifi) += RTL_CARDS RTLWIFI config-$(call config_package,rtlwifi-pci) += RTLWIFI_PCI @@ -56,6 +57,7 @@ config-$(call config_package,rtw89-8852ae) += RTW89_8852A RTW89_8852AE config-$(call config_package,rtw89-8852b-common) += RTW89_8852B_COMMON config-$(call config_package,rtw89-8852be) += RTW89_8852B RTW89_8852BE config-$(call config_package,rtw89-8852ce) += RTW89_8852C RTW89_8852CE +config-$(call config_package,rtw89-8922ae) += RTW89_8922A RTW89_8922AE config-$(CONFIG_PACKAGE_RTW89_DEBUG) += RTW89_DEBUG config-$(CONFIG_PACKAGE_RTW89_DEBUGFS) += RTW89_DEBUGFS config-$(CONFIG_PACKAGE_RTW89_DEBUGMSG) += RTW89_DEBUGMSG @@ -480,3 +482,13 @@ define KernelPackage/rtw89-8852ce $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw89/rtw89_8852ce.ko AUTOLOAD:=$(call AutoProbe,rtw89_8852ce) endef + +define KernelPackage/rtw89-8922ae + $(call KernelPackage/mac80211/Default) + TITLE:=Realtek RTL8922AE support + DEPENDS+= +kmod-rtw89-pci +rtl8922ae-firmware +@DRIVER_11BE_SUPPORT + FILES:= \ + $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw89/rtw89_8922a.ko \ + $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw89/rtw89_8922ae.ko + AUTOLOAD:=$(call AutoProbe,rtw89_8922ae) +endef From a475171e07c3eae99a4621762192e3f44622b6c7 Mon Sep 17 00:00:00 2001 From: INAGAKI Hiroshi Date: Mon, 14 Oct 2024 00:31:43 +0900 Subject: [PATCH 24/32] uboot-ath79: update to U-Boot v2024.10 Update uboot-ath79 package to U-Boot v2024.10. Signed-off-by: INAGAKI Hiroshi Link: https://github.com/openwrt/openwrt/pull/16703 Signed-off-by: Hauke Mehrtens --- package/boot/uboot-ath79/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/package/boot/uboot-ath79/Makefile b/package/boot/uboot-ath79/Makefile index d19f5615769dd6..9e64f680b7f606 100644 --- a/package/boot/uboot-ath79/Makefile +++ b/package/boot/uboot-ath79/Makefile @@ -1,8 +1,8 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2024.07 -PKG_HASH:=f591da9ab90ef3d6b3d173766d0ddff90c4ed7330680897486117df390d83c8f +PKG_VERSION:=2024.10 +PKG_HASH:=b28daf4ac17e43156363078bf510297584137f6df50fced9b12df34f61a92fb0 UBOOT_USE_INTREE_DTC:=1 From 0506dd393c744b0e4895ee8597325961e68d8c56 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Wed, 16 Oct 2024 15:31:20 -0700 Subject: [PATCH 25/32] mpc85xx: p1010: fix NAND devices Upstream commit 9ba0cae3cac07c21c583f9ff194f74043f90d29c made FSL_IFC visible and selectable, which means that in order for MTD_NAND_FSL_IFC to work, it needs these two extra CONFIG options. Signed-off-by: Rosen Penev Link: https://github.com/openwrt/openwrt/pull/16717 Signed-off-by: Robert Marko --- target/linux/mpc85xx/p1010/config-default | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/linux/mpc85xx/p1010/config-default b/target/linux/mpc85xx/p1010/config-default index afa930f4b4c039..1cd84b52cadb91 100644 --- a/target/linux/mpc85xx/p1010/config-default +++ b/target/linux/mpc85xx/p1010/config-default @@ -2,7 +2,9 @@ CONFIG_BR200_WP=y CONFIG_CMDLINE_OVERRIDE=y CONFIG_FIREBOX_T10=y # CONFIG_FSL_CORENET_CF is not set +CONFIG_FSL_IFC=y CONFIG_GPIO_74X164=y +CONFIG_MEMORY=y CONFIG_MTD_CFI=y CONFIG_MTD_NAND_FSL_IFC=y CONFIG_MTD_PHYSMAP=y From e2f64ce5926118bf1c65d53d06560726e85ac9b3 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Wed, 22 Nov 2023 02:45:13 +0100 Subject: [PATCH 26/32] mpc85xx: convert Watchguard T10 mac-assignment to NVMEM MAC-addresses are stored with colons, thus they can now be referenced using NVMEM. Signed-off-by: David Bauer Signed-off-by: Rosen Penev Link: https://github.com/openwrt/openwrt/pull/16310 Signed-off-by: Robert Marko --- .../base-files/lib/preinit/10_fix_eth_mac.sh | 5 --- .../arch/powerpc/boot/dts/firebox-t10.dts | 36 +++++++++++++++++++ 2 files changed, 36 insertions(+), 5 deletions(-) diff --git a/target/linux/mpc85xx/base-files/lib/preinit/10_fix_eth_mac.sh b/target/linux/mpc85xx/base-files/lib/preinit/10_fix_eth_mac.sh index fc4beaef1a8cc0..23d20ed08cf611 100644 --- a/target/linux/mpc85xx/base-files/lib/preinit/10_fix_eth_mac.sh +++ b/target/linux/mpc85xx/base-files/lib/preinit/10_fix_eth_mac.sh @@ -11,11 +11,6 @@ preinit_set_mac_address() { ip link set dev eth0 address $(mtd_get_mac_ascii cfg1 ethaddr) ip link set dev eth1 address $(mtd_get_mac_ascii cfg1 eth1addr) ;; - watchguard,firebox-t10) - ip link set dev eth0 address "$(mtd_get_mac_text "device_id" 0x1830)" - ip link set dev eth1 address "$(mtd_get_mac_text "device_id" 0x1844)" - ip link set dev eth2 address "$(mtd_get_mac_text "device_id" 0x1858)" - ;; esac } diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/firebox-t10.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/firebox-t10.dts index 087138bbc2fc62..7f6235ad35ab94 100644 --- a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/firebox-t10.dts +++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/firebox-t10.dts @@ -21,6 +21,9 @@ led-failsafe = &led_failover; led-running = &led_mode; led-upgrade = &led_attention; + /delete-property/ ethernet0; + /delete-property/ ethernet1; + /delete-property/ ethernet2; }; memory { @@ -105,6 +108,30 @@ reg = <0xc0000 0x40000>; label = "device_id"; read-only; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_device_id_1830: mac-address@1830 { + compatible = "mac-base"; + reg = <0x1830 0x11>; + #nvmem-cell-cells = <1>; + }; + + macaddr_device_id_1844: mac-address@1844 { + compatible = "mac-base"; + reg = <0x1844 0x11>; + #nvmem-cell-cells = <1>; + }; + + macaddr_device_id_1858: mac-address@1858 { + compatible = "mac-base"; + reg = <0x1858 0x11>; + #nvmem-cell-cells = <1>; + }; + }; }; }; }; @@ -149,18 +176,27 @@ enet0: ethernet@b0000 { phy-handle = <&phy1>; phy-connection-type = "rgmii-id"; + + nvmem-cells = <&macaddr_device_id_1830 0>; + nvmem-cell-names = "mac-address"; }; enet1: ethernet@b1000 { tbi-handle = <&tbi_phy1>; phy-handle = <&phy2>; phy-connection-type = "sgmii"; + + nvmem-cells = <&macaddr_device_id_1844 0>; + nvmem-cell-names = "mac-address"; }; enet2: ethernet@b2000 { tbi-handle = <&tbi_phy2>; phy-handle = <&phy3>; phy-connection-type = "sgmii"; + + nvmem-cells = <&macaddr_device_id_1858 0>; + nvmem-cell-names = "mac-address"; }; sdhc@2e000 { From abda39d86d8f8a48b6fc324a5e2eebe3e8387c2e Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Thu, 17 Oct 2024 13:33:18 +0100 Subject: [PATCH 27/32] generic: import and move accepted RealTek PHY patches Import commits from upstream Linux and move/rename existing patches which have been acceped. Signed-off-by: Daniel Golle --- ...Check-the-index-value-in-led_hw_cont.patch | 32 +++++++++ ...Fix-MMD-access-on-RTL8126A-integrate.patch | 67 +++++++++++++++++++ ...ead-duplex-and-gbit-master-from-PHY.patch} | 49 ++++++-------- ...hange-order-of-calls-in-C22-read_st.patch} | 11 +-- ...lear-1000Base-T-link-partner-advert.patch} | 10 +-- ...-use-genphy_soft_reset-for-2.5G-PHYs.patch | 16 ++--- ...sable-SGMII-in-band-AN-for-2-5G-PHYs.patch | 4 +- ...make-sure-paged-read-is-protected-by.patch | 2 +- ...-phy-realtek-introduce-rtl822x_probe.patch | 20 +++--- ...tek-detect-early-version-of-RTL8221B.patch | 2 +- ...ealtek-support-interrupt-of-RTL8221B.patch | 10 +-- 11 files changed, 158 insertions(+), 65 deletions(-) create mode 100644 target/linux/generic/backport-6.6/781-13-v6.12-net-phy-realtek-Check-the-index-value-in-led_hw_cont.patch create mode 100644 target/linux/generic/backport-6.6/781-14-v6.12-net-phy-realtek-Fix-MMD-access-on-RTL8126A-integrate.patch rename target/linux/generic/{pending-6.6/720-07-net-phy-realtek-read-duplex-and-gbit-master-from-PHY.patch => backport-6.6/781-15-v6.13-net-phy-realtek-read-duplex-and-gbit-master-from-PHY.patch} (71%) rename target/linux/generic/{pending-6.6/720-08-net-phy-realtek-change-order-of-calls-in-C22-read_st.patch => backport-6.6/781-16-v6.13-net-phy-realtek-change-order-of-calls-in-C22-read_st.patch} (74%) rename target/linux/generic/{pending-6.6/720-09-net-phy-realtek-clear-1000Base-T-link-partner-advert.patch => backport-6.6/781-17-v6.13-net-phy-realtek-clear-1000Base-T-link-partner-advert.patch} (66%) diff --git a/target/linux/generic/backport-6.6/781-13-v6.12-net-phy-realtek-Check-the-index-value-in-led_hw_cont.patch b/target/linux/generic/backport-6.6/781-13-v6.12-net-phy-realtek-Check-the-index-value-in-led_hw_cont.patch new file mode 100644 index 00000000000000..a6f8b6d1c51a42 --- /dev/null +++ b/target/linux/generic/backport-6.6/781-13-v6.12-net-phy-realtek-Check-the-index-value-in-led_hw_cont.patch @@ -0,0 +1,32 @@ +From c283782fc5d60c4d8169137c6f955aa3553d3b3d Mon Sep 17 00:00:00 2001 +From: Hui Wang +Date: Fri, 27 Sep 2024 19:46:10 +0800 +Subject: [PATCH] net: phy: realtek: Check the index value in + led_hw_control_get + +Just like rtl8211f_led_hw_is_supported() and +rtl8211f_led_hw_control_set(), the rtl8211f_led_hw_control_get() also +needs to check the index value, otherwise the caller is likely to get +an incorrect rules. + +Fixes: 17784801d888 ("net: phy: realtek: Add support for PHY LEDs on RTL8211F") +Signed-off-by: Hui Wang +Reviewed-by: Marek Vasut +Link: https://patch.msgid.link/20240927114610.1278935-1-hui.wang@canonical.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/phy/realtek.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/net/phy/realtek.c ++++ b/drivers/net/phy/realtek.c +@@ -527,6 +527,9 @@ static int rtl8211f_led_hw_control_get(s + { + int val; + ++ if (index >= RTL8211F_LED_COUNT) ++ return -EINVAL; ++ + val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR); + if (val < 0) + return val; diff --git a/target/linux/generic/backport-6.6/781-14-v6.12-net-phy-realtek-Fix-MMD-access-on-RTL8126A-integrate.patch b/target/linux/generic/backport-6.6/781-14-v6.12-net-phy-realtek-Fix-MMD-access-on-RTL8126A-integrate.patch new file mode 100644 index 00000000000000..b50e133a670182 --- /dev/null +++ b/target/linux/generic/backport-6.6/781-14-v6.12-net-phy-realtek-Fix-MMD-access-on-RTL8126A-integrate.patch @@ -0,0 +1,67 @@ +From a6ad589c1d118f9d5b1bc4c6888d42919f830340 Mon Sep 17 00:00:00 2001 +From: Heiner Kallweit +Date: Mon, 7 Oct 2024 11:57:41 +0200 +Subject: [PATCH] net: phy: realtek: Fix MMD access on RTL8126A-integrated PHY + +All MMD reads return 0 for the RTL8126A-integrated PHY. Therefore phylib +assumes it doesn't support EEE, what results in higher power consumption, +and a significantly higher chip temperature in my case. +To fix this split out the PHY driver for the RTL8126A-integrated PHY +and set the read_mmd/write_mmd callbacks to read from vendor-specific +registers. + +Fixes: 5befa3728b85 ("net: phy: realtek: add support for RTL8126A-integrated 5Gbps PHY") +Cc: stable@vger.kernel.org +Signed-off-by: Heiner Kallweit +Signed-off-by: David S. Miller +--- + drivers/net/phy/realtek.c | 24 +++++++++++++++++++++++- + 1 file changed, 23 insertions(+), 1 deletion(-) + +--- a/drivers/net/phy/realtek.c ++++ b/drivers/net/phy/realtek.c +@@ -1081,6 +1081,16 @@ static int rtl8221b_vn_cg_c45_match_phy_ + return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true); + } + ++static int rtl8251b_c22_match_phy_device(struct phy_device *phydev) ++{ ++ return rtlgen_is_c45_match(phydev, RTL_8251B, false); ++} ++ ++static int rtl8251b_c45_match_phy_device(struct phy_device *phydev) ++{ ++ return rtlgen_is_c45_match(phydev, RTL_8251B, true); ++} ++ + static int rtlgen_resume(struct phy_device *phydev) + { + int ret = genphy_resume(phydev); +@@ -1418,7 +1428,7 @@ static struct phy_driver realtek_drvs[] + .suspend = genphy_c45_pma_suspend, + .resume = rtlgen_c45_resume, + }, { +- PHY_ID_MATCH_EXACT(0x001cc862), ++ .match_phy_device = rtl8251b_c45_match_phy_device, + .name = "RTL8251B 5Gbps PHY", + .get_features = rtl822x_get_features, + .config_aneg = rtl822x_config_aneg, +@@ -1428,6 +1438,18 @@ static struct phy_driver realtek_drvs[] + .read_page = rtl821x_read_page, + .write_page = rtl821x_write_page, + }, { ++ .match_phy_device = rtl8251b_c22_match_phy_device, ++ .name = "RTL8126A-internal 5Gbps PHY", ++ .get_features = rtl822x_get_features, ++ .config_aneg = rtl822x_config_aneg, ++ .read_status = rtl822x_read_status, ++ .suspend = genphy_suspend, ++ .resume = rtlgen_resume, ++ .read_page = rtl821x_read_page, ++ .write_page = rtl821x_write_page, ++ .read_mmd = rtl822x_read_mmd, ++ .write_mmd = rtl822x_write_mmd, ++ }, { + PHY_ID_MATCH_EXACT(0x001ccad0), + .name = "RTL8224 2.5Gbps PHY", + .get_features = rtl822x_c45_get_features, diff --git a/target/linux/generic/pending-6.6/720-07-net-phy-realtek-read-duplex-and-gbit-master-from-PHY.patch b/target/linux/generic/backport-6.6/781-15-v6.13-net-phy-realtek-read-duplex-and-gbit-master-from-PHY.patch similarity index 71% rename from target/linux/generic/pending-6.6/720-07-net-phy-realtek-read-duplex-and-gbit-master-from-PHY.patch rename to target/linux/generic/backport-6.6/781-15-v6.13-net-phy-realtek-read-duplex-and-gbit-master-from-PHY.patch index d609d596afe57a..e15218b169ea33 100644 --- a/target/linux/generic/pending-6.6/720-07-net-phy-realtek-read-duplex-and-gbit-master-from-PHY.patch +++ b/target/linux/generic/backport-6.6/781-15-v6.13-net-phy-realtek-read-duplex-and-gbit-master-from-PHY.patch @@ -1,51 +1,46 @@ -From 66d82d3f04623e9c096e12c10ca51141c345ee84 Mon Sep 17 00:00:00 2001 +From 081c9c0265c91b8333165aa6230c20bcbc6f7cbf Mon Sep 17 00:00:00 2001 From: Daniel Golle -Date: Tue, 8 Oct 2024 20:59:51 +0100 -Subject: [PATCH] net: phy: realtek: read duplex and gbit master from PHYSR +Date: Thu, 10 Oct 2024 14:07:16 +0100 +Subject: [PATCH 3/5] net: phy: realtek: read duplex and gbit master from PHYSR register The PHYSR MMD register is present and defined equally for all RTL82xx Ethernet PHYs. -Read duplex and gbit master bits from rtlgen_decode_speed() and rename +Read duplex and Gbit master bits from rtlgen_decode_speed() and rename it to rtlgen_decode_physr(). Signed-off-by: Daniel Golle +Link: https://patch.msgid.link/b9a76341da851a18c985bc4774fa295babec79bb.1728565530.git.daniel@makrotopia.org +Signed-off-by: Paolo Abeni --- - drivers/net/phy/realtek.c | 48 ++++++++++++++++++++++++++++++++------- - 1 file changed, 40 insertions(+), 8 deletions(-) + drivers/net/phy/realtek.c | 41 +++++++++++++++++++++++++++++++-------- + 1 file changed, 33 insertions(+), 8 deletions(-) --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c -@@ -80,20 +80,24 @@ +@@ -80,15 +80,18 @@ #define RTL822X_VND2_GANLPAR 0xa414 -#define RTL822X_VND2_PHYSR 0xa434 - - #define RTL8221B_PHYCR1 0xa430 - #define RTL8221B_PHYCR1_ALDPS_EN BIT(2) - #define RTL8221B_PHYCR1_ALDPS_XTAL_OFF_EN BIT(12) + #define RTL8366RB_POWER_SAVE 0x15 + #define RTL8366RB_POWER_SAVE_ON BIT(12) + + #define RTL9000A_GINMR 0x14 + #define RTL9000A_GINMR_LINK_STATUS BIT(4) +-#define RTLGEN_SPEED_MASK 0x0630 +#define RTL_VND2_PHYSR 0xa434 -+#define RTL_VND2_PHYSR_LINK BIT(2) +#define RTL_VND2_PHYSR_DUPLEX BIT(3) +#define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4) +#define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9) +#define RTL_VND2_PHYSR_MASTER BIT(11) +#define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH) -+ - #define RTL8366RB_POWER_SAVE 0x15 - #define RTL8366RB_POWER_SAVE_ON BIT(12) - - #define RTL9000A_GINMR 0x14 - #define RTL9000A_GINMR_LINK_STATUS BIT(4) --#define RTLGEN_SPEED_MASK 0x0630 -- #define RTL_GENERIC_PHYID 0x001cc800 #define RTL_8211FVD_PHYID 0x001cc878 - #define RTL_8221B_VB_CG 0x001cc849 -@@ -661,9 +665,24 @@ static int rtl8366rb_config_init(struct +@@ -660,9 +663,18 @@ static int rtl8366rb_config_init(struct } /* get actual speed to cover the downshift case */ @@ -53,12 +48,6 @@ Signed-off-by: Daniel Golle +static void rtlgen_decode_physr(struct phy_device *phydev, int val) { - switch (val & RTLGEN_SPEED_MASK) { -+ /* bit 2 -+ * 0: Link not OK -+ * 1: Link OK -+ */ -+ phydev->link = !!(val & RTL_VND2_PHYSR_LINK); -+ + /* bit 3 + * 0: Half Duplex + * 1: Full Duplex @@ -72,7 +61,7 @@ Signed-off-by: Daniel Golle case 0x0000: phydev->speed = SPEED_10; break; -@@ -685,6 +704,19 @@ static void rtlgen_decode_speed(struct p +@@ -684,6 +696,19 @@ static void rtlgen_decode_speed(struct p default: break; } @@ -92,7 +81,7 @@ Signed-off-by: Daniel Golle } static int rtlgen_read_status(struct phy_device *phydev) -@@ -702,7 +734,7 @@ static int rtlgen_read_status(struct phy +@@ -701,7 +726,7 @@ static int rtlgen_read_status(struct phy if (val < 0) return val; @@ -101,7 +90,7 @@ Signed-off-by: Daniel Golle return 0; } -@@ -1030,11 +1062,11 @@ static int rtl822x_c45_read_status(struc +@@ -1007,11 +1032,11 @@ static int rtl822x_c45_read_status(struc return 0; /* Read actual speed from vendor register. */ diff --git a/target/linux/generic/pending-6.6/720-08-net-phy-realtek-change-order-of-calls-in-C22-read_st.patch b/target/linux/generic/backport-6.6/781-16-v6.13-net-phy-realtek-change-order-of-calls-in-C22-read_st.patch similarity index 74% rename from target/linux/generic/pending-6.6/720-08-net-phy-realtek-change-order-of-calls-in-C22-read_st.patch rename to target/linux/generic/backport-6.6/781-16-v6.13-net-phy-realtek-change-order-of-calls-in-C22-read_st.patch index 8a7ad8afa8cc5e..be7136b375154e 100644 --- a/target/linux/generic/pending-6.6/720-08-net-phy-realtek-change-order-of-calls-in-C22-read_st.patch +++ b/target/linux/generic/backport-6.6/781-16-v6.13-net-phy-realtek-change-order-of-calls-in-C22-read_st.patch @@ -1,7 +1,7 @@ -From eaca24de0c0e64145c130759207da32594d2e5d1 Mon Sep 17 00:00:00 2001 +From 68d5cd09e8919679ce13b85950debea4b2e98e04 Mon Sep 17 00:00:00 2001 From: Daniel Golle -Date: Tue, 8 Oct 2024 21:05:47 +0100 -Subject: [PATCH 2/3] net: phy: realtek: change order of calls in C22 +Date: Thu, 10 Oct 2024 14:07:26 +0100 +Subject: [PATCH 4/5] net: phy: realtek: change order of calls in C22 read_status() Always call rtlgen_read_status() first, so genphy_read_status() which @@ -9,14 +9,17 @@ is called by it clears bits in case auto-negotiation has not completed. Also clear 10GBT link-partner advertisement bits in case auto-negotiation is disabled or has not completed. +Suggested-by: Russell King (Oracle) Signed-off-by: Daniel Golle +Link: https://patch.msgid.link/b15929a41621d215c6b2b57393368086589569ec.1728565530.git.daniel@makrotopia.org +Signed-off-by: Paolo Abeni --- drivers/net/phy/realtek.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c -@@ -979,17 +979,25 @@ static void rtl822xb_update_interface(st +@@ -949,17 +949,25 @@ static void rtl822xb_update_interface(st static int rtl822x_read_status(struct phy_device *phydev) { diff --git a/target/linux/generic/pending-6.6/720-09-net-phy-realtek-clear-1000Base-T-link-partner-advert.patch b/target/linux/generic/backport-6.6/781-17-v6.13-net-phy-realtek-clear-1000Base-T-link-partner-advert.patch similarity index 66% rename from target/linux/generic/pending-6.6/720-09-net-phy-realtek-clear-1000Base-T-link-partner-advert.patch rename to target/linux/generic/backport-6.6/781-17-v6.13-net-phy-realtek-clear-1000Base-T-link-partner-advert.patch index 824be84c687a8b..3847d5803a00f4 100644 --- a/target/linux/generic/pending-6.6/720-09-net-phy-realtek-clear-1000Base-T-link-partner-advert.patch +++ b/target/linux/generic/backport-6.6/781-17-v6.13-net-phy-realtek-clear-1000Base-T-link-partner-advert.patch @@ -1,7 +1,7 @@ -From 8b137d1e405dc90300ba577db44c70f0e026636e Mon Sep 17 00:00:00 2001 +From 5cb409b3960e75467cbb0a8e1e5596b4490570e3 Mon Sep 17 00:00:00 2001 From: Daniel Golle -Date: Tue, 8 Oct 2024 21:09:19 +0100 -Subject: [PATCH 3/3] net: phy: realtek: clear 1000Base-T link partner +Date: Thu, 10 Oct 2024 14:07:39 +0100 +Subject: [PATCH 5/5] net: phy: realtek: clear 1000Base-T link partner advertisement Clear 1000Base-T link partner advertisement bits in Clause-45 @@ -9,13 +9,15 @@ read_status() function in case auto-negotiation is disabled or has not been completed. Signed-off-by: Daniel Golle +Link: https://patch.msgid.link/9dc9b47b2d675708afef3ad366bfd78eb584d958.1728565530.git.daniel@makrotopia.org +Signed-off-by: Paolo Abeni --- drivers/net/phy/realtek.c | 4 ++++ 1 file changed, 4 insertions(+) --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c -@@ -1056,6 +1056,10 @@ static int rtl822x_c45_read_status(struc +@@ -1026,6 +1026,10 @@ static int rtl822x_c45_read_status(struc if (ret < 0) return ret; diff --git a/target/linux/generic/pending-6.6/720-01-net-phy-realtek-use-genphy_soft_reset-for-2.5G-PHYs.patch b/target/linux/generic/pending-6.6/720-01-net-phy-realtek-use-genphy_soft_reset-for-2.5G-PHYs.patch index fe8ee7b5fa1435..2b77b6e02f9881 100644 --- a/target/linux/generic/pending-6.6/720-01-net-phy-realtek-use-genphy_soft_reset-for-2.5G-PHYs.patch +++ b/target/linux/generic/pending-6.6/720-01-net-phy-realtek-use-genphy_soft_reset-for-2.5G-PHYs.patch @@ -15,7 +15,7 @@ Signed-off-by: Daniel Golle --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c -@@ -1325,6 +1325,7 @@ static struct phy_driver realtek_drvs[] +@@ -1375,6 +1375,7 @@ static struct phy_driver realtek_drvs[] }, { .name = "RTL8226 2.5Gbps PHY", .match_phy_device = rtl8226_match_phy_device, @@ -23,7 +23,7 @@ Signed-off-by: Daniel Golle .get_features = rtl822x_get_features, .config_aneg = rtl822x_config_aneg, .read_status = rtl822x_read_status, -@@ -1337,6 +1338,7 @@ static struct phy_driver realtek_drvs[] +@@ -1387,6 +1388,7 @@ static struct phy_driver realtek_drvs[] }, { PHY_ID_MATCH_EXACT(0x001cc840), .name = "RTL8226B_RTL8221B 2.5Gbps PHY", @@ -31,7 +31,7 @@ Signed-off-by: Daniel Golle .get_features = rtl822x_get_features, .config_aneg = rtl822x_config_aneg, .config_init = rtl822xb_config_init, -@@ -1351,6 +1353,7 @@ static struct phy_driver realtek_drvs[] +@@ -1401,6 +1403,7 @@ static struct phy_driver realtek_drvs[] }, { PHY_ID_MATCH_EXACT(0x001cc838), .name = "RTL8226-CG 2.5Gbps PHY", @@ -39,7 +39,7 @@ Signed-off-by: Daniel Golle .get_features = rtl822x_get_features, .config_aneg = rtl822x_config_aneg, .read_status = rtl822x_read_status, -@@ -1361,6 +1364,7 @@ static struct phy_driver realtek_drvs[] +@@ -1411,6 +1414,7 @@ static struct phy_driver realtek_drvs[] }, { PHY_ID_MATCH_EXACT(0x001cc848), .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", @@ -47,7 +47,7 @@ Signed-off-by: Daniel Golle .get_features = rtl822x_get_features, .config_aneg = rtl822x_config_aneg, .config_init = rtl822xb_config_init, -@@ -1373,6 +1377,7 @@ static struct phy_driver realtek_drvs[] +@@ -1423,6 +1427,7 @@ static struct phy_driver realtek_drvs[] }, { .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device, .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)", @@ -55,7 +55,7 @@ Signed-off-by: Daniel Golle .get_features = rtl822x_get_features, .config_aneg = rtl822x_config_aneg, .config_init = rtl822xb_config_init, -@@ -1385,6 +1390,7 @@ static struct phy_driver realtek_drvs[] +@@ -1435,6 +1440,7 @@ static struct phy_driver realtek_drvs[] }, { .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device, .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)", @@ -63,7 +63,7 @@ Signed-off-by: Daniel Golle .config_init = rtl822xb_config_init, .get_rate_matching = rtl822xb_get_rate_matching, .get_features = rtl822x_c45_get_features, -@@ -1395,6 +1401,7 @@ static struct phy_driver realtek_drvs[] +@@ -1445,6 +1451,7 @@ static struct phy_driver realtek_drvs[] }, { .match_phy_device = rtl8221b_vn_cg_c22_match_phy_device, .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)", @@ -71,7 +71,7 @@ Signed-off-by: Daniel Golle .get_features = rtl822x_get_features, .config_aneg = rtl822x_config_aneg, .config_init = rtl822xb_config_init, -@@ -1407,6 +1414,7 @@ static struct phy_driver realtek_drvs[] +@@ -1457,6 +1464,7 @@ static struct phy_driver realtek_drvs[] }, { .match_phy_device = rtl8221b_vn_cg_c45_match_phy_device, .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)", diff --git a/target/linux/generic/pending-6.6/720-02-net-phy-realtek-disable-SGMII-in-band-AN-for-2-5G-PHYs.patch b/target/linux/generic/pending-6.6/720-02-net-phy-realtek-disable-SGMII-in-band-AN-for-2-5G-PHYs.patch index 0c729acb7fe792..cbef74d317b0e5 100644 --- a/target/linux/generic/pending-6.6/720-02-net-phy-realtek-disable-SGMII-in-band-AN-for-2-5G-PHYs.patch +++ b/target/linux/generic/pending-6.6/720-02-net-phy-realtek-disable-SGMII-in-band-AN-for-2-5G-PHYs.patch @@ -20,7 +20,7 @@ Signed-off-by: Daniel Golle --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c -@@ -786,8 +786,8 @@ static int rtl822x_write_mmd(struct phy_ +@@ -814,8 +814,8 @@ static int rtl822x_write_mmd(struct phy_ static int rtl822xb_config_init(struct phy_device *phydev) { bool has_2500, has_sgmii; @@ -30,7 +30,7 @@ Signed-off-by: Daniel Golle has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->host_interfaces) || -@@ -837,7 +837,29 @@ static int rtl822xb_config_init(struct p +@@ -865,7 +865,29 @@ static int rtl822xb_config_init(struct p if (ret < 0) return ret; diff --git a/target/linux/generic/pending-6.6/720-03-net-phy-realtek-make-sure-paged-read-is-protected-by.patch b/target/linux/generic/pending-6.6/720-03-net-phy-realtek-make-sure-paged-read-is-protected-by.patch index 8b8dca8f2780cf..216fa918e1f670 100644 --- a/target/linux/generic/pending-6.6/720-03-net-phy-realtek-make-sure-paged-read-is-protected-by.patch +++ b/target/linux/generic/pending-6.6/720-03-net-phy-realtek-make-sure-paged-read-is-protected-by.patch @@ -18,7 +18,7 @@ Signed-off-by: Daniel Golle --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c -@@ -1052,9 +1052,11 @@ static bool rtlgen_supports_2_5gbps(stru +@@ -1092,9 +1092,11 @@ static bool rtlgen_supports_2_5gbps(stru { int val; diff --git a/target/linux/generic/pending-6.6/720-04-net-phy-realtek-introduce-rtl822x_probe.patch b/target/linux/generic/pending-6.6/720-04-net-phy-realtek-introduce-rtl822x_probe.patch index 7350d3affcc60b..08c13f34e44097 100644 --- a/target/linux/generic/pending-6.6/720-04-net-phy-realtek-introduce-rtl822x_probe.patch +++ b/target/linux/generic/pending-6.6/720-04-net-phy-realtek-introduce-rtl822x_probe.patch @@ -13,9 +13,9 @@ Signed-off-by: Daniel Golle --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c -@@ -82,6 +82,10 @@ +@@ -80,6 +80,10 @@ - #define RTL822X_VND2_PHYSR 0xa434 + #define RTL822X_VND2_GANLPAR 0xa414 +#define RTL8221B_PHYCR1 0xa430 +#define RTL8221B_PHYCR1_ALDPS_EN BIT(2) @@ -24,8 +24,8 @@ Signed-off-by: Daniel Golle #define RTL8366RB_POWER_SAVE 0x15 #define RTL8366RB_POWER_SAVE_ON BIT(12) -@@ -1102,6 +1106,25 @@ static int rtl8221b_vn_cg_c45_match_phy_ - return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true); +@@ -1152,6 +1156,25 @@ static int rtl8251b_c45_match_phy_device + return rtlgen_is_c45_match(phydev, RTL_8251B, true); } +static int rtl822x_probe(struct phy_device *phydev) @@ -50,7 +50,7 @@ Signed-off-by: Daniel Golle static int rtlgen_resume(struct phy_device *phydev) { int ret = genphy_resume(phydev); -@@ -1377,6 +1400,7 @@ static struct phy_driver realtek_drvs[] +@@ -1427,6 +1450,7 @@ static struct phy_driver realtek_drvs[] }, { PHY_ID_MATCH_EXACT(0x001cc838), .name = "RTL8226-CG 2.5Gbps PHY", @@ -58,7 +58,7 @@ Signed-off-by: Daniel Golle .soft_reset = genphy_soft_reset, .get_features = rtl822x_get_features, .config_aneg = rtl822x_config_aneg, -@@ -1388,6 +1412,7 @@ static struct phy_driver realtek_drvs[] +@@ -1438,6 +1462,7 @@ static struct phy_driver realtek_drvs[] }, { PHY_ID_MATCH_EXACT(0x001cc848), .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", @@ -66,7 +66,7 @@ Signed-off-by: Daniel Golle .soft_reset = genphy_soft_reset, .get_features = rtl822x_get_features, .config_aneg = rtl822x_config_aneg, -@@ -1401,6 +1426,7 @@ static struct phy_driver realtek_drvs[] +@@ -1451,6 +1476,7 @@ static struct phy_driver realtek_drvs[] }, { .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device, .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)", @@ -74,7 +74,7 @@ Signed-off-by: Daniel Golle .soft_reset = genphy_soft_reset, .get_features = rtl822x_get_features, .config_aneg = rtl822x_config_aneg, -@@ -1414,6 +1440,7 @@ static struct phy_driver realtek_drvs[] +@@ -1464,6 +1490,7 @@ static struct phy_driver realtek_drvs[] }, { .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device, .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)", @@ -82,7 +82,7 @@ Signed-off-by: Daniel Golle .soft_reset = genphy_soft_reset, .config_init = rtl822xb_config_init, .get_rate_matching = rtl822xb_get_rate_matching, -@@ -1425,6 +1452,7 @@ static struct phy_driver realtek_drvs[] +@@ -1475,6 +1502,7 @@ static struct phy_driver realtek_drvs[] }, { .match_phy_device = rtl8221b_vn_cg_c22_match_phy_device, .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)", @@ -90,7 +90,7 @@ Signed-off-by: Daniel Golle .soft_reset = genphy_soft_reset, .get_features = rtl822x_get_features, .config_aneg = rtl822x_config_aneg, -@@ -1438,6 +1466,7 @@ static struct phy_driver realtek_drvs[] +@@ -1488,6 +1516,7 @@ static struct phy_driver realtek_drvs[] }, { .match_phy_device = rtl8221b_vn_cg_c45_match_phy_device, .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)", diff --git a/target/linux/generic/pending-6.6/720-05-net-phy-realtek-detect-early-version-of-RTL8221B.patch b/target/linux/generic/pending-6.6/720-05-net-phy-realtek-detect-early-version-of-RTL8221B.patch index 204d7a041404b0..6938552d14df12 100644 --- a/target/linux/generic/pending-6.6/720-05-net-phy-realtek-detect-early-version-of-RTL8221B.patch +++ b/target/linux/generic/pending-6.6/720-05-net-phy-realtek-detect-early-version-of-RTL8221B.patch @@ -14,7 +14,7 @@ Signed-off-by: Daniel Golle Signed-off-by: Mieczyslaw Nalewaj --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c -@@ -1080,10 +1080,32 @@ static int rtl8226_match_phy_device(stru +@@ -1120,10 +1120,32 @@ static int rtl8226_match_phy_device(stru static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id, bool is_c45) { diff --git a/target/linux/generic/pending-6.6/720-06-net-phy-realtek-support-interrupt-of-RTL8221B.patch b/target/linux/generic/pending-6.6/720-06-net-phy-realtek-support-interrupt-of-RTL8221B.patch index 0ae7b385cd6213..a796b8f011d5fb 100644 --- a/target/linux/generic/pending-6.6/720-06-net-phy-realtek-support-interrupt-of-RTL8221B.patch +++ b/target/linux/generic/pending-6.6/720-06-net-phy-realtek-support-interrupt-of-RTL8221B.patch @@ -12,7 +12,7 @@ Signed-off-by: Jianhui Zhao --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c -@@ -1282,6 +1282,51 @@ static irqreturn_t rtl9000a_handle_inter +@@ -1332,6 +1332,51 @@ static irqreturn_t rtl9000a_handle_inter return IRQ_HANDLED; } @@ -64,7 +64,7 @@ Signed-off-by: Jianhui Zhao static struct phy_driver realtek_drvs[] = { { PHY_ID_MATCH_EXACT(0x00008201), -@@ -1448,6 +1493,8 @@ static struct phy_driver realtek_drvs[] +@@ -1498,6 +1543,8 @@ static struct phy_driver realtek_drvs[] }, { .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device, .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)", @@ -73,7 +73,7 @@ Signed-off-by: Jianhui Zhao .probe = rtl822x_probe, .soft_reset = genphy_soft_reset, .get_features = rtl822x_get_features, -@@ -1462,6 +1509,8 @@ static struct phy_driver realtek_drvs[] +@@ -1512,6 +1559,8 @@ static struct phy_driver realtek_drvs[] }, { .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device, .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)", @@ -82,7 +82,7 @@ Signed-off-by: Jianhui Zhao .probe = rtl822x_probe, .soft_reset = genphy_soft_reset, .config_init = rtl822xb_config_init, -@@ -1474,6 +1523,8 @@ static struct phy_driver realtek_drvs[] +@@ -1524,6 +1573,8 @@ static struct phy_driver realtek_drvs[] }, { .match_phy_device = rtl8221b_vn_cg_c22_match_phy_device, .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)", @@ -91,7 +91,7 @@ Signed-off-by: Jianhui Zhao .probe = rtl822x_probe, .soft_reset = genphy_soft_reset, .get_features = rtl822x_get_features, -@@ -1488,6 +1539,8 @@ static struct phy_driver realtek_drvs[] +@@ -1538,6 +1589,8 @@ static struct phy_driver realtek_drvs[] }, { .match_phy_device = rtl8221b_vn_cg_c45_match_phy_device, .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)", From 172ccf73811eb5aa3177d274952c3f2a19890fe5 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Thu, 17 Oct 2024 14:27:04 +0200 Subject: [PATCH 28/32] ath11k-firmware: update IPQ8074 and QCN9074 to 2.9.0.1-02146 After a long time QCA has pushed an updated release of 2.9.0.1 firmware for IPQ8074 and QCN9074, so lets update to 2.9.0.1-02146. Sadly, still nothing new for IPQ6018. QCA has also moved the repository where they will be posting firmware to their CodeLinaro instance, so we move to using that and it allows us to remove the manual download of QCN9074 board-2.bin. Link: https://github.com/openwrt/openwrt/pull/16720 Signed-off-by: Robert Marko --- package/firmware/ath11k-firmware/Makefile | 29 +++++++---------------- 1 file changed, 9 insertions(+), 20 deletions(-) diff --git a/package/firmware/ath11k-firmware/Makefile b/package/firmware/ath11k-firmware/Makefile index 85cbfa87c3cb3c..0acc3f9f1a4565 100644 --- a/package/firmware/ath11k-firmware/Makefile +++ b/package/firmware/ath11k-firmware/Makefile @@ -8,13 +8,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=ath11k-firmware -PKG_SOURCE_DATE:=2024-03-14 -PKG_SOURCE_VERSION:=795809c7041582bd51bdfaa1f548b916ae8d4382 -PKG_MIRROR_HASH:=d93edc651b641a97ec4f5ed329e15ac110928f863b4afbaae7fcb25953d04544 -PKG_RELEASE:=2 +PKG_SOURCE_DATE:=2024-10-14 +PKG_SOURCE_VERSION:=15f050122da5ef5bef2cc8c7c19dfb7f98060a49 +PKG_MIRROR_HASH:=e7a89d1570f32552ade539376181494724b5eafb31d00451ff2dcf5a2922a0cb +PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git -PKG_SOURCE_URL:=https://github.com/quic/upstream-wifi-fw.git +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/ath-firmware/ath11k-firmware.git PKG_LICENSE_FILES:=LICENSE.qca_firmware @@ -51,38 +51,27 @@ define Build/Compile endef -QCN9074_BOARD_REV:=8e140c65f36137714b6d8934e09dcd73cb05c2f6 -QCN9074_BOARD_FILE:=board-2.bin.$(QCN9074_BOARD_REV) - -define Download/qcn9074-board - URL:=https://git.codelinaro.org/clo/ath-firmware/ath11k-firmware/-/raw/main/QCN9074/hw1.0/ - URL_FILE:=board-2.bin - FILE:=$(QCN9074_BOARD_FILE) - HASH:=dbf0ca14aa1229eccd48f26f1026901b9718b143bd30b51b8ea67c84ba6207f1 -endef -$(eval $(call Download,qcn9074-board)) - define Package/ath11k-firmware-ipq6018/install $(INSTALL_DIR) $(1)/lib/firmware/IPQ6018 $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/ath11k-firmware/IPQ6018/hw1.0/2.5.0.1/WLAN.HK.2.5.0.1-03982-QCAHKSWPL_SILICONZ-3/* \ + $(PKG_BUILD_DIR)/IPQ6018/hw1.0/2.5.0.1/WLAN.HK.2.5.0.1-03982-QCAHKSWPL_SILICONZ-3/* \ $(1)/lib/firmware/IPQ6018/ endef define Package/ath11k-firmware-ipq8074/install $(INSTALL_DIR) $(1)/lib/firmware/IPQ8074 $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/ath11k-firmware/IPQ8074/hw2.0/2.9.0.1/WLAN.HK.2.9.0.1-01977-QCAHKSWPL_SILICONZ-1/* \ + $(PKG_BUILD_DIR)/IPQ8074/hw2.0/2.9.0.1/WLAN.HK.2.9.0.1-02146-QCAHKSWPL_SILICONZ-1/* \ $(1)/lib/firmware/IPQ8074/ endef define Package/ath11k-firmware-qcn9074/install $(INSTALL_DIR) $(1)/lib/firmware/ath11k/QCN9074/hw1.0 $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/ath11k-firmware/QCN9074/hw1.0/2.9.0.1/WLAN.HK.2.9.0.1-01977-QCAHKSWPL_SILICONZ-1/* \ + $(PKG_BUILD_DIR)/QCN9074/hw1.0/2.9.0.1/WLAN.HK.2.9.0.1-02146-QCAHKSWPL_SILICONZ-1/* \ $(1)/lib/firmware/ath11k/QCN9074/hw1.0/ $(INSTALL_BIN) \ - $(DL_DIR)/$(QCN9074_BOARD_FILE) $(1)/lib/firmware/ath11k/QCN9074/hw1.0/board-2.bin + $(PKG_BUILD_DIR)/QCN9074/hw1.0/board-2.bin $(1)/lib/firmware/ath11k/QCN9074/hw1.0/board-2.bin endef $(eval $(call BuildPackage,ath11k-firmware-ipq6018)) From 5004f3780de581c7d67c4be0a57833ca1423a021 Mon Sep 17 00:00:00 2001 From: Hannu Nyman Date: Wed, 16 Oct 2024 22:03:34 +0300 Subject: [PATCH 29/32] base-files: Increase failsafe trigger wait time from 2 to 4 sec Increase the failsafe waiting timeout period from 2 seconds to 4 seconds. Since commit 29207748b in 2015 we have had a rapid LED blinking indication for the failsafe triggering period. But the really short timeout of 2 seconds requires snappy reaction time from the user to notice the LED blinking and to push button inside the short window. Relax the timeout to 4 seconds, which more easily allows to notice the change in LED blinking and push a button. Signed-off-by: Hannu Nyman Link: https://github.com/openwrt/openwrt/pull/11852 Signed-off-by: Robert Marko --- package/base-files/Makefile | 2 +- package/base-files/image-config.in | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/package/base-files/Makefile b/package/base-files/Makefile index 313bf377b492fe..4da50a27362dce 100644 --- a/package/base-files/Makefile +++ b/package/base-files/Makefile @@ -77,7 +77,7 @@ endef define ImageConfigOptions mkdir -p $(1)/lib/preinit echo 'pi_suppress_stderr="$(CONFIG_TARGET_PREINIT_SUPPRESS_STDERR)"' >$(1)/lib/preinit/00_preinit.conf - echo 'fs_failsafe_wait_timeout=$(if $(CONFIG_TARGET_PREINIT_TIMEOUT),$(CONFIG_TARGET_PREINIT_TIMEOUT),2)' >>$(1)/lib/preinit/00_preinit.conf + echo 'fs_failsafe_wait_timeout=$(if $(CONFIG_TARGET_PREINIT_TIMEOUT),$(CONFIG_TARGET_PREINIT_TIMEOUT),4)' >>$(1)/lib/preinit/00_preinit.conf echo 'pi_init_path="$(TARGET_INIT_PATH)"' >>$(1)/lib/preinit/00_preinit.conf echo 'pi_init_env=$(if $(CONFIG_TARGET_INIT_ENV),$(CONFIG_TARGET_INIT_ENV),"")' >>$(1)/lib/preinit/00_preinit.conf echo 'pi_init_cmd=$(if $(CONFIG_TARGET_INIT_CMD),$(CONFIG_TARGET_INIT_CMD),"/sbin/init")' >>$(1)/lib/preinit/00_preinit.conf diff --git a/package/base-files/image-config.in b/package/base-files/image-config.in index 2de2130b8490d9..dee06e9b864b78 100644 --- a/package/base-files/image-config.in +++ b/package/base-files/image-config.in @@ -44,7 +44,7 @@ config TARGET_PREINIT_DISABLE_FAILSAFE config TARGET_PREINIT_TIMEOUT int prompt "Failsafe/Debug wait timeout" if PREINITOPT - default 2 + default 4 help How long to wait for failsafe mode to be entered or for a debug option to be pressed before continuing with a From 494349f2298b01be66ceccc2d46fdc5cae958f96 Mon Sep 17 00:00:00 2001 From: Jack Sun Date: Thu, 17 Oct 2024 19:37:38 +0800 Subject: [PATCH 30/32] package: busybox: update download link MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is no file named busybox-1.36.1.tar.bz2 in the root directory of the website The actual download link is “https://sources.buildroot.net/busybox/busybox-1.36.1.tar.bz2” Signed-off-by: Jack Sun Link: https://github.com/openwrt/openwrt/pull/16719 Signed-off-by: Robert Marko --- package/utils/busybox/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/utils/busybox/Makefile b/package/utils/busybox/Makefile index bf3e8e2f75f944..4ef470df755890 100644 --- a/package/utils/busybox/Makefile +++ b/package/utils/busybox/Makefile @@ -11,7 +11,7 @@ PKG_FLAGS:=essential PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 PKG_SOURCE_URL:=https://www.busybox.net/downloads \ - http://sources.buildroot.net + https://sources.buildroot.net/$(PKG_NAME) PKG_HASH:=b8cc24c9574d809e7279c3be349795c5d5ceb6fdf19ca709f80cde50e47de314 PKG_BUILD_DEPENDS:=BUSYBOX_CONFIG_PAM:libpam From 1d98363bd20c2632a555c9661c8470d1a83c861e Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Thu, 17 Oct 2024 18:37:27 +0200 Subject: [PATCH 31/32] realtek: refresh patches CI says that they need to be refreshed, so do so. Link: https://github.com/openwrt/openwrt/pull/16722 Signed-off-by: Robert Marko --- .../706-include-linux-add-phy-ops-for-rtl838x.patch | 2 +- .../708-drivers-net-phy-eee-support-for-rtl838x.patch | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/linux/realtek/patches-6.6/706-include-linux-add-phy-ops-for-rtl838x.patch b/target/linux/realtek/patches-6.6/706-include-linux-add-phy-ops-for-rtl838x.patch index 2a799551d604a5..09255c572147ef 100644 --- a/target/linux/realtek/patches-6.6/706-include-linux-add-phy-ops-for-rtl838x.patch +++ b/target/linux/realtek/patches-6.6/706-include-linux-add-phy-ops-for-rtl838x.patch @@ -21,7 +21,7 @@ Submitted-by: John Crispin --- a/include/linux/phy.h +++ b/include/linux/phy.h -@@ -1180,6 +1180,10 @@ struct phy_driver { +@@ -1181,6 +1181,10 @@ struct phy_driver { */ int (*led_polarity_set)(struct phy_device *dev, int index, unsigned long modes); diff --git a/target/linux/realtek/patches-6.6/708-drivers-net-phy-eee-support-for-rtl838x.patch b/target/linux/realtek/patches-6.6/708-drivers-net-phy-eee-support-for-rtl838x.patch index 89a1d9583fe547..a92045ba8a7b0b 100644 --- a/target/linux/realtek/patches-6.6/708-drivers-net-phy-eee-support-for-rtl838x.patch +++ b/target/linux/realtek/patches-6.6/708-drivers-net-phy-eee-support-for-rtl838x.patch @@ -21,7 +21,7 @@ Submitted-by: John Crispin --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c -@@ -2491,6 +2491,11 @@ int phylink_ethtool_ksettings_set(struct +@@ -2503,6 +2503,11 @@ int phylink_ethtool_ksettings_set(struct * the presence of a PHY, this should not be changed as that * should be determined from the media side advertisement. */ @@ -33,7 +33,7 @@ Submitted-by: John Crispin return phy_ethtool_ksettings_set(pl->phydev, &phy_kset); } -@@ -2793,8 +2798,11 @@ int phylink_ethtool_get_eee(struct phyli +@@ -2805,8 +2810,11 @@ int phylink_ethtool_get_eee(struct phyli ASSERT_RTNL(); @@ -46,7 +46,7 @@ Submitted-by: John Crispin return ret; } -@@ -2811,8 +2819,11 @@ int phylink_ethtool_set_eee(struct phyli +@@ -2823,8 +2831,11 @@ int phylink_ethtool_set_eee(struct phyli ASSERT_RTNL(); From caf5caae44f54855b6630d90e99a3e861cf77995 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Thu, 17 Oct 2024 18:37:47 +0200 Subject: [PATCH 32/32] lantiq: refresh patches CI says that they need to be refreshed, so do so. Link: https://github.com/openwrt/openwrt/pull/16722 Signed-off-by: Robert Marko --- .../0023-NET-PHY-add-led-support-for-intel-xway.patch | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/linux/lantiq/patches-6.6/0023-NET-PHY-add-led-support-for-intel-xway.patch b/target/linux/lantiq/patches-6.6/0023-NET-PHY-add-led-support-for-intel-xway.patch index fcc760b911ae22..a6a517dbf60559 100644 --- a/target/linux/lantiq/patches-6.6/0023-NET-PHY-add-led-support-for-intel-xway.patch +++ b/target/linux/lantiq/patches-6.6/0023-NET-PHY-add-led-support-for-intel-xway.patch @@ -13,8 +13,8 @@ Signed-off-by: John Crispin --- a/drivers/net/phy/intel-xway.c +++ b/drivers/net/phy/intel-xway.c -@@ -229,6 +229,51 @@ static int xway_gphy_rgmii_init(struct p - XWAY_MDIO_MIICTRL_TXSKEW_MASK, val); +@@ -278,6 +278,51 @@ static int xway_gphy_init_leds(struct ph + return 0; } +#if IS_ENABLED(CONFIG_OF_MDIO) @@ -64,8 +64,8 @@ Signed-off-by: John Crispin + static int xway_gphy_config_init(struct phy_device *phydev) { - int err; -@@ -280,6 +325,7 @@ static int xway_gphy_config_init(struct + struct device_node *np = phydev->mdio.dev.of_node; +@@ -299,6 +344,7 @@ static int xway_gphy_config_init(struct if (err) return err;