New prof: Felipe de Souza Marques, UFPEL

aserg-ufmg · Nov 11, 2021 · f8f9703 · f8f9703
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diff --git a/data/all-researchers.csv b/data/all-researchers.csv
@@ -1163,4 +1163,5 @@ Zanoni Dias,UNICAMP,93/6090
 Zhao Liang,FFCLRP/USP,63/5422-1
 Fabio Gomes Rocha,UNIT,246/8332
 Pedro Henrique Bugatti,UTFPR,13/4202
-Janio Carlos Nascimento Silva,IFTO,273/2402
+Janio Carlos Nascimento Silva,IFTO,273/2402
+Felipe de Souza Marques,UFPEL,28/3459
diff --git a/data/hardware-out-journals.csv b/data/hardware-out-journals.csv
@@ -1,7 +1,7 @@
 IEEE TCAS,17
 IEEE TCAD,15
 IEEE Trans. Computers,12
-ACM TODAES,3
+ACM TODAES,4
 IEEE TVLSI,3
 JETCAS,1
 J. Solid-State Circuits,0
diff --git a/data/hardware-out-papers.csv b/data/hardware-out-papers.csv
@@ -1,3 +1,4 @@
+2021,ACM TODAES,"SmartDR: Algorithms and Techniques for Fast Detailed Routing with Good Design Rule Handling.",UFPEL,Stephano Machado Moreira Goncalves; Leomar S. da Rosa Jr.; Felipe S. Marques,https://doi.org/10.1145/3417133,top,J,no_arxiv,0
 2021,ASP-DAC,"Exploiting HLS-Generated Multi-Version Kernels to Improve CPU-FPGA Cloud Systems.",UFRGS,Bernardo Neuhaus Lignati; Michael Guilherme Jordan; Guilherme Korol; Mateus Beck Rutzig; Antonio Carlos Schneider Beck,https://doi.org/10.1145/3394885.3431557,null,C,no_arxiv,0
 2021,ASP-DAC,"Providing Plug N' Play for Processing-in-Memory Accelerators.",UFRGS,Paulo C. Santos 0001; Bruno E. Forlin; Luigi Carro,https://doi.org/10.1145/3394885.3431527,null,C,no_arxiv,0
 2021,DATE,"Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization.",FURG; UFPEL; UFRGS,Shubham Rai; Walter Lau Neto; Yukio Miyasaka; Xinpei Zhang; Mingfei Yu; Qingyang Yi; Masahiro Fujita; Guilherme B. Manske; Matheus F. Pontes; Leomar S. da Rosa; Marilton S. de Aguiar; Paulo F. Butzen; Po-Chun Chien; Yu-Shan Huang; Hoa-Ren Wang; Jie-Hong R. Jiang; Jiaqi Gu; Zheng Zhao; Zixuan Jiang; David Z. Pan; Brunno A. Abreu; Isac de Souza Campos; Augusto Andre Souza Berndt; Cristina Meinhardt; Jonata T. Carvalho; Mateus Grellert; Sergio Bampi; Aditya Lohana; Akash Kumar 0001; Wei Zeng 0015; Azadeh Davoodi; Rasit Onur Topaloglu; Yuan Zhou; Jordan Dotzel; Yichi Zhang; Hanyu Wang; Zhiru Zhang; Valerio Tenace; Pierre-Emmanuel Gaillardon; Alan Mishchenko; Satrajit Chatterjee,https://doi.org/10.23919/DATE51398.2021.9473972,null,C,http://arxiv.org/abs/2012.02530v2,0
@@ -58,7 +59,7 @@
 2017,DATE,"An energy-efficient memory hierarchy for multi-issue processors.",UFRGS,Tiago T. Jost; Gabriel L. Nazar; Luigi Carro,https://doi.org/10.23919/DATE.2017.7927018,null,C,no_arxiv,0
 2017,DATE,"Operand size reconfiguration for big data processing in memory.",UFPR; UFRGS,Paulo C. Santos 0001; Geraldo F. Oliveira; Diego G. Tomé; Marco A. Z. Alves; Eduardo Cunha de Almeida; Luigi Carro,https://doi.org/10.23919/DATE.2017.7927081,null,C,no_arxiv,0
 2017,IEEE TCAD,"Incremental Layer Assignment Driven by an External Signoff Timing Engine.",UFSC,Vinicius S. Livramento; Derong Liu 0002; Salim Chowdhury; Bei Yu 0001; Xiaoqing Xu; David Z. Pan; José Luís Almada Güntzel; Luiz C. V. dos Santos,https://doi.org/10.1109/TCAD.2016.2638450,null,J,no_arxiv,0
-2017,IEEE TCAD,"Transistor Count Optimization in IG FinFET Network Design.",UFRGS,Vinicius N. Possani; André Inácio Reis; Renato P. Ribas; Felipe S. Marques; Leomar S. da Rosa Jr.,https://doi.org/10.1109/TCAD.2016.2629451,null,J,no_arxiv,0
+2017,IEEE TCAD,"Transistor Count Optimization in IG FinFET Network Design.",UFRGS; UFPEL,Vinicius N. Possani; André Inácio Reis; Renato P. Ribas; Felipe S. Marques; Leomar S. da Rosa Jr.,https://doi.org/10.1109/TCAD.2016.2629451,null,J,no_arxiv,0
 2017,IEEE TCAS,"Picowatt, 0.45-0.6 V Self-Biased Subthreshold CMOS Voltage Reference.",UFRGS,Arthur Campos de Oliveira; David Cordova; Hamilton Klimach; Sergio Bampi,https://doi.org/10.1109/TCSI.2017.2754644,top,J,no_arxiv,0
 2017,IEEE TCAS,"Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design.",UFRGS,Bianca Silveira; Guilherme Paim; Brunno Abreu; Mateus Grellert; Cláudio Machado Diniz; Eduardo A. C. da Costa; Sergio Bampi,https://doi.org/10.1109/TCSI.2017.2728802,top,J,no_arxiv,0
 2017,IEEE Trans. Computers,"Application-Guided Power-Efficient Fault Tolerance for H.264 Context Adaptive Variable Length Coding.",UFPEL,Muhammad Shafique 0001; Semeen Rehman; Florian Kriebel; Muhammad Usman Karim Khan; Bruno Zatt; Arun Subramaniyan 0001; Bruno Boessio Vizzotto; Jörg Henkel,https://doi.org/10.1109/TC.2016.2616313,null,J,no_arxiv,0
@@ -72,7 +73,7 @@
 2016,IEEE TCAD,"Formal Verification of Arithmetic Circuits by Function Extraction.",UNESP,Cunxi Yu; Walter Brown; Duo Liu; André Rossi; Maciej J. Ciesielski,https://doi.org/10.1109/TCAD.2016.2547898,null,J,no_arxiv,0
 2016,IEEE TCAD,"USE: A Universal, Scalable, and Efficient Clocking Scheme for QCA.",UFMG,Caio Araujo T. Campos; Abner Luis Panho Marciano; Omar P. Vilela Neto; Frank Sill Torres,https://doi.org/10.1109/TCAD.2015.2471996,null,J,no_arxiv,0
 2016,IEEE TCAS,"Testable MUTEX Design.",PUC-RS,Yang Zhang 0014; Leandro S. Heck; Matheus T. Moreira; David Zar; Melvin A. Breuer; Ney Laert Vilar Calazans; Peter A. Beerel,https://doi.org/10.1109/TCSI.2016.2561906,top,J,no_arxiv,0
-2016,IEEE TVLSI,"Graph-Based Transistor Network Generation Method for Supergate Design.",UFRGS,Vinicius Neves Possani; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas; Felipe de Souza Marques; Leomar Soares da Rosa Jr.,https://doi.org/10.1109/TVLSI.2015.2410764,null,J,no_arxiv,0
+2016,IEEE TVLSI,"Graph-Based Transistor Network Generation Method for Supergate Design.",UFRGS; UFPEL,Vinicius Neves Possani; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas; Felipe de Souza Marques; Leomar Soares da Rosa Jr.,https://doi.org/10.1109/TVLSI.2015.2410764,null,J,no_arxiv,0
 2016,IEEE Trans. Computers,"A Decentralized Damage Detection System for Wireless Sensor and Actuator Networks.",DCC/UFRJ; NCE/UFRJ,Igor Leão dos Santos; Luci Pirmez; Luiz F. R. C. Carmo; Paulo F. Pires; Flávia Coimbra Delicato; Samee Ullah Khan; Albert Y. Zomaya,https://doi.org/10.1109/TC.2015.2479608,null,J,no_arxiv,0
 2016,IEEE Trans. Computers,"Evaluation and Mitigation of Radiation-Induced Soft Errors in Graphics Processing Units.",UFSC; UFRGS,Daniel Alfonso Gonçalves de Oliveira; Laércio Lima Pilla; Thiago Santini; Paolo Rech,https://doi.org/10.1109/TC.2015.2444855,null,J,no_arxiv,0
 2016,IEEE Trans. Computers,"Geographic and Opportunistic Routing for Underwater Sensor Networks.",UFMG,Rodolfo Wanderson Lima Coutinho; Azzedine Boukerche; Luiz Filipe Menezes Vieira; Antonio Alfredo Ferreira Loureiro,https://doi.org/10.1109/TC.2015.2423677,null,J,no_arxiv,0

diff --git a/data/hardware-out-profs-list.csv b/data/hardware-out-profs-list.csv
@@ -7,6 +7,7 @@ Bruno Zatt,UFPEL
 Cristina Meinhardt,FURG
 Eduardo Cunha de Almeida,UFPR
 Felipe Franca,COPPE/UFRJ
+Felipe de Souza Marques,UFPEL
 Flavia Delicato,DCC/UFRJ
 Gabriel Luca Nazar,UFRGS
 Javam Machado,UFC

diff --git a/data/hardware-out-scores.csv b/data/hardware-out-scores.csv
@@ -1,6 +1,6 @@
 UFRGS,33.41
 UFSC,5.26
-UFPEL,2.73
+UFPEL,4.53
 FURG,2.33
 PUC-RS,2.0
 UFPR,1.39

diff --git a/data/profs/all-authors.csv b/data/profs/all-authors.csv
@@ -330,6 +330,7 @@ Fabricio Olivetti de Franca
 Fatima Nunes
 Felipe Franca
 Felipe Meneguzzi
+Felipe de Souza Marques
 Fernanda Baiao
 Fernanda Campos
 Fernando Castor

diff --git a/data/profs/search/Felipe-de-Souza-Marques.csv b/data/profs/search/Felipe-de-Souza-Marques.csv
@@ -0,0 +1,3 @@
+2021,ACM TODAES,"SmartDR: Algorithms and Techniques for Fast Detailed Routing with Good Design Rule Handling.",Stephano Machado Moreira Goncalves; Leomar S. da Rosa Jr.; Felipe S. Marques,https://doi.org/10.1145/3417133,top,J,no_arxiv,0
+2017,IEEE TCAD,"Transistor Count Optimization in IG FinFET Network Design.",Vinicius N. Possani; André Inácio Reis; Renato P. Ribas; Felipe S. Marques; Leomar S. da Rosa Jr.,https://doi.org/10.1109/TCAD.2016.2629451,null,J,no_arxiv,0
+2016,IEEE TVLSI,"Graph-Based Transistor Network Generation Method for Supergate Design.",Vinicius Neves Possani; Vinicius Callegaro; André Inácio Reis; Renato P. Ribas; Felipe de Souza Marques; Leomar Soares da Rosa Jr.,https://doi.org/10.1109/TVLSI.2015.2410764,null,J,no_arxiv,0