From 0a6c6641e8e0e9d40b0bca194211bc95080d4c9f Mon Sep 17 00:00:00 2001 From: Terry Bai Date: Mon, 18 Nov 2024 16:35:08 +1100 Subject: [PATCH] clk: fix style and data types This commit replaces all platform-dependent data types with fix-sized types, and unifies the return values of interfaces as signed integers. The return value 0 indicates the success on the request to clock driver, and negative values indicate the failure reasons. Signed-off-by: Terry Bai --- drivers/clk/clk-operations.c | 41 +-- drivers/clk/clk-operations.h | 44 ++- drivers/clk/clk.h | 38 +-- drivers/clk/imx/clk-imx.c | 87 ++---- drivers/clk/imx/clk-imx8mq.c | 236 ++++++--------- drivers/clk/imx/clk.c | 29 +- drivers/clk/imx/include/clk-imx.h | 27 +- drivers/clk/meson/clk-measure.c | 3 +- drivers/clk/meson/clk-meson.c | 193 +++++-------- drivers/clk/meson/clk.c | 33 ++- drivers/clk/meson/sm1-clk.c | 463 +++++++++++------------------- examples/clk/client.c | 66 ++++- include/sddf/clk/client.h | 21 +- 13 files changed, 479 insertions(+), 802 deletions(-) diff --git a/drivers/clk/clk-operations.c b/drivers/clk/clk-operations.c index 6fe7167ab..885138b5e 100644 --- a/drivers/clk/clk-operations.c +++ b/drivers/clk/clk-operations.c @@ -122,13 +122,11 @@ const struct clk_ops clk_gate_ro_ops = { .is_enabled = clk_gate_is_enabled, }; -static inline unsigned long clk_div_recalc_rate(const struct clk *clk, - unsigned long prate) +static inline uint64_t clk_div_recalc_rate(const struct clk *clk, uint64_t prate) { struct clk_div_data *data = (struct clk_div_data *)(clk->data); - uint32_t div = regmap_read_bits(clk->base, data->offset, data->shift, - data->width); + uint32_t div = regmap_read_bits(clk->base, data->offset, data->shift, data->width); /* TODO: Need to verify the following cases */ if (data->flags & CLK_DIVIDER_ONE_BASED) { @@ -144,8 +142,7 @@ static inline unsigned long clk_div_recalc_rate(const struct clk *clk, return DIV_ROUND_UP_ULL((uint64_t)prate, div); } -static inline int clk_div_set_rate(const struct clk *clk, uint32_t rate, - uint32_t parent_rate) +static inline int clk_div_set_rate(const struct clk *clk, uint64_t rate, uint64_t parent_rate) { struct clk_div_data *data = (struct clk_div_data *)(clk->data); uint32_t div = DIV_ROUND_UP(parent_rate, rate); @@ -160,8 +157,7 @@ static inline int clk_div_set_rate(const struct clk *clk, uint32_t rate, } else { div -= 1; } - return regmap_update_bits(clk->base, data->offset, data->shift, data->width, - div); + return regmap_update_bits(clk->base, data->offset, data->shift, data->width, div); } const struct clk_ops clk_divider_ops = { @@ -180,8 +176,7 @@ static inline uint8_t clk_mux_get_parent(const struct clk *clk) { struct clk_mux_data *data = (struct clk_mux_data *)(clk->data); uint32_t num_parents = clk->hw.init->num_parents; - uint32_t val = regmap_mux_read_bits(clk->base, data->offset, data->shift, - data->mask); + uint32_t val = regmap_mux_read_bits(clk->base, data->offset, data->shift, data->mask); if (data->table) { int i; @@ -212,12 +207,10 @@ static inline int clk_mux_set_parent(struct clk *clk, uint8_t index) struct clk_mux_data *data = (struct clk_mux_data *)(clk->data); if (data->table) { - unsigned int val = data->table[index]; - regmap_mux_update_bits(clk->base, data->offset, data->shift, data->mask, - val); + uint32_t val = data->table[index]; + regmap_mux_update_bits(clk->base, data->offset, data->shift, data->mask, val); } - regmap_mux_update_bits(clk->base, data->offset, data->shift, data->mask, - index); + regmap_mux_update_bits(clk->base, data->offset, data->shift, data->mask, index); return 0; } @@ -231,16 +224,14 @@ const struct clk_ops clk_mux_ro_ops = { .get_parent = clk_mux_get_parent, }; -static inline unsigned long clk_factor_recalc_rate(const struct clk *clk, - unsigned long parent_rate) +static inline uint64_t clk_factor_recalc_rate(const struct clk *clk, uint64_t parent_rate) { - struct clk_fixed_factor_data *data = - (struct clk_fixed_factor_data *)(clk->data); - unsigned long long int rate; + struct clk_fixed_factor_data *data = (struct clk_fixed_factor_data *)(clk->data); + uint64_t rate; - rate = (unsigned long long int)parent_rate * data->mult; + rate = (uint64_t)parent_rate * data->mult; do_div(rate, data->div); - return (unsigned long)rate; + return (uint64_t)rate; } const struct clk_ops clk_fixed_factor_ops = { @@ -250,8 +241,7 @@ const struct clk_ops clk_fixed_factor_ops = { /* .recalc_accuracy = clk_factor_recalc_accuracy, */ }; -static inline int clk_source_set_rate(const struct clk *clk, uint32_t rate, - uint32_t parent_rate) +static inline int clk_source_set_rate(const struct clk *clk, uint64_t rate, uint64_t parent_rate) { struct clk_source_data *data = (struct clk_source_data *)(clk->data); data->rate = rate; @@ -259,8 +249,7 @@ static inline int clk_source_set_rate(const struct clk *clk, uint32_t rate, return 0; } -static inline unsigned long clk_source_get_rate(const struct clk *clk, - unsigned long prate) +static inline uint64_t clk_source_get_rate(const struct clk *clk, uint64_t prate) { struct clk_source_data *data = (struct clk_source_data *)(clk->data); diff --git a/drivers/clk/clk-operations.h b/drivers/clk/clk-operations.h index beccd73c8..2dc02a301 100644 --- a/drivers/clk/clk-operations.h +++ b/drivers/clk/clk-operations.h @@ -8,11 +8,11 @@ #include #include -#define CLK_INCORRECT_ARGS 1 -#define CLK_INVALID_OP 2 -#define CLK_INVALID_ID 3 -#define CLK_UNKNOWN_REQ 4 -#define CLK_UNKNOWN_TARGET 5 +#define CLK_INCORRECT_ARGS -1 +#define CLK_INVALID_OP -2 +#define CLK_INVALID_ID -3 +#define CLK_UNKNOWN_REQ -4 +#define CLK_UNKNOWN_TARGET -5 static inline int reg_write(uint64_t base, uint32_t offset, uint32_t val) { @@ -22,8 +22,7 @@ static inline int reg_write(uint64_t base, uint32_t offset, uint32_t val) return 0; } -static inline int regmap_update_bits(uint64_t base, uint32_t offset, - uint8_t shift, uint8_t width, uint32_t val) +static inline int regmap_update_bits(uint64_t base, uint32_t offset, uint8_t shift, uint8_t width, uint32_t val) { volatile uint32_t *clk_reg = ((void *)base + offset); uint32_t reg_val = *clk_reg; @@ -36,8 +35,7 @@ static inline int regmap_update_bits(uint64_t base, uint32_t offset, return 0; } -static inline uint32_t regmap_read_bits(uint64_t base, uint32_t offset, - uint8_t shift, uint8_t width) +static inline uint32_t regmap_read_bits(uint64_t base, uint32_t offset, uint8_t shift, uint8_t width) { volatile uint32_t *clk_reg = ((void *)base + offset); uint32_t reg_val = *clk_reg; @@ -48,9 +46,7 @@ static inline uint32_t regmap_read_bits(uint64_t base, uint32_t offset, return reg_val; } -static inline int regmap_mux_update_bits(uint64_t base, uint32_t offset, - uint8_t shift, uint32_t mask, - uint32_t val) +static inline int regmap_mux_update_bits(uint64_t base, uint32_t offset, uint8_t shift, uint32_t mask, uint32_t val) { volatile uint32_t *clk_reg = ((void *)base + offset); uint32_t reg_val = *clk_reg; @@ -63,8 +59,7 @@ static inline int regmap_mux_update_bits(uint64_t base, uint32_t offset, return 0; } -static inline uint32_t regmap_mux_read_bits(uint64_t base, uint32_t offset, - uint8_t shift, uint32_t mask) +static inline uint32_t regmap_mux_read_bits(uint64_t base, uint32_t offset, uint8_t shift, uint32_t mask) { volatile uint32_t *clk_reg = ((void *)base + offset); uint32_t reg_val = *clk_reg; @@ -84,8 +79,7 @@ extern const struct clk_ops clk_mux_ro_ops; extern const struct clk_ops clk_gate_ops; extern const struct clk_ops clk_gate_ro_ops; -#define CLK_FIXED_FACTOR(_name, _mult, _div, _data_flags, _parent_clks, \ - _num_parents, _init_flags) \ +#define CLK_FIXED_FACTOR(_name, _mult, _div, _data_flags, _parent_clks, _num_parents, _init_flags) \ struct clk _name = { \ .data = &(struct clk_fixed_factor_data) { \ .mult = (_mult), \ @@ -101,8 +95,7 @@ struct clk _name = { \ }, \ } -#define CLK_GATE(_name, _offset, _bit, _data_flags, _parent_clks, \ - _num_parents, _init_flags) \ +#define CLK_GATE(_name, _offset, _bit, _data_flags, _parent_clks, _num_parents, _init_flags) \ struct clk _name = { \ .data = &(struct clk_gate_data) { \ .offset = (_offset), \ @@ -118,8 +111,7 @@ struct clk _name = { \ }, \ } -#define CLK_GATE_RO(_name, _offset, _bit, _data_flags, _parent_clks, \ - _num_parents, _init_flags) \ +#define CLK_GATE_RO(_name, _offset, _bit, _data_flags, _parent_clks, _num_parents, _init_flags) \ struct clk _name = { \ .data = &(struct clk_gate_data) { \ .offset = (_offset), \ @@ -135,8 +127,7 @@ struct clk _name = { \ }, \ } -#define CLK_MUX(_name, _offset, _mask, _shift, _table, _data_flags, \ - _parent_data, _num_parents, _init_flags) \ +#define CLK_MUX(_name, _offset, _mask, _shift, _table, _data_flags, _parent_data, _num_parents, _init_flags) \ struct clk _name = { \ .data = &(struct clk_mux_data) { \ .offset = (_offset), \ @@ -154,8 +145,7 @@ struct clk _name = { \ }, \ } -#define CLK_MUX_RO(_name, _offset, _mask, _shift, _table, _data_flags, \ - _parent_data, _num_parents, _init_flags) \ +#define CLK_MUX_RO(_name, _offset, _mask, _shift, _table, _data_flags, _parent_data, _num_parents, _init_flags) \ struct clk _name = { \ .data = &(struct clk_mux_data) { \ .offset = (_offset), \ @@ -173,8 +163,7 @@ struct clk _name = { \ }, \ } -#define CLK_DIV(_name, _offset, _shift, _width, _data_flags, _parent_clks, \ - _num_parents, _init_flags) \ +#define CLK_DIV(_name, _offset, _shift, _width, _data_flags, _parent_clks, _num_parents, _init_flags) \ struct clk _name = { \ .data = &(struct clk_div_data) { \ .offset = (_offset), \ @@ -191,8 +180,7 @@ struct clk _name = { \ }, \ } -#define CLK_DIV_RO(_name, _offset, _shift, _width, _data_flags, _parent_clks, \ - _num_parents, _init_flags) \ +#define CLK_DIV_RO(_name, _offset, _shift, _width, _data_flags, _parent_clks, _num_parents, _init_flags) \ struct clk _name = { \ .data = &(struct clk_div_data) { \ .offset = (_offset), \ diff --git a/drivers/clk/clk.h b/drivers/clk/clk.h index 60bfd0485..f73d2b98e 100644 --- a/drivers/clk/clk.h +++ b/drivers/clk/clk.h @@ -70,8 +70,7 @@ struct clk_init_data; * clk_foo's clk_ops * * @init: pointer to struct clk_init_data that contains the init data shared - * with the common clock framework. This pointer will be set to NULL once - * a clk_register() variant is called on this clk_hw pointer. + * with the common clock framework. */ struct clk_hw { struct clk *clk; @@ -83,20 +82,6 @@ struct clk_hw { * be provided by the clock implementation, and will be called by drivers * through the clk_* api. * - * @prepare: Prepare the clock for enabling. This must not return until - * the clock is fully prepared, and it's safe to call clk_enable. - * This callback is intended to allow clock implementations to - * do any initialisation that may sleep. Called with - * prepare_lock held. - * - * @unprepare: Release the clock from its prepared state. This will typically - * undo any work done in the @prepare callback. Called with - * prepare_lock held. - * - * @is_prepared: Queries the hardware to determine if the clock is prepared. - * This function is allowed to sleep. Optional, if this op is not - * set then the prepare count will be used. - * * @enable: Enable the clock atomically. This must not return until the * clock is generating a valid clock signal, usable by consumer * devices. Called with enable_lock held. This function must not @@ -109,11 +94,6 @@ struct clk_hw { * This function must not sleep. Optional, if this op is not * set then the enable count will be used. * - * @disable_unused: Disable the clock atomically. Only called from - * clk_disable_unused for gate clocks with special needs. - * Called with enable_lock held. This function must not - * sleep. - * * @recalc_rate: Recalculate the rate of this clock, by querying hardware. The * parent rate is an input parameter. It is up to the caller to * ensure that the prepare_mutex is held across this call. If the @@ -165,9 +145,8 @@ struct clk_hw { struct clk_ops { uint8_t (*get_parent)(const struct clk *clk); int (*set_parent)(struct clk *clk, uint8_t index); - unsigned long (*recalc_rate)(const struct clk *clk, - unsigned long parent_rate); - int (*set_rate)(const struct clk *clk, uint32_t rate, uint32_t parent_rate); + uint64_t (*recalc_rate)(const struct clk *clk, uint64_t parent_rate); + int (*set_rate)(const struct clk *clk, uint64_t rate, uint64_t parent_rate); void (*init)(struct clk *clk); int (*enable)(struct clk *clk); int (*disable)(struct clk *clk); @@ -334,9 +313,6 @@ struct clk_fixed_factor_data { * .get_parent clk_op. * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired * frequency. - * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for - * the mux register. Setting this flag makes the register accesses big - * endian. */ struct clk_mux_data { uint32_t offset; @@ -368,21 +344,21 @@ const struct clk *get_parent(const struct clk *clk); * @clk: pointer to the current clk * */ -uint32_t clk_get_rate(const struct clk *clk, uint64_t *rate); +int clk_get_rate(const struct clk *clk, uint64_t *rate); /** * function clk_enable() - enable the target clock signal * * @clk: pointer to the current clk */ -uint32_t clk_enable(struct clk *clk); +int clk_enable(struct clk *clk); /** * function clk_disable() - disable the target clock signal * * @clk: pointer to the current clk */ -uint32_t clk_disable(struct clk *clk); +int clk_disable(struct clk *clk); /** * function clk_set_rate() - set the nearest rate to the requested rate for @@ -392,4 +368,4 @@ uint32_t clk_disable(struct clk *clk); * @req_rate: request rate * @rate: pointer to result variable */ -uint32_t clk_set_rate(struct clk *clk, uint64_t req_rate, uint64_t *rate); +int clk_set_rate(struct clk *clk, uint64_t req_rate, uint64_t *rate); diff --git a/drivers/clk/imx/clk-imx.c b/drivers/clk/imx/clk-imx.c index ab3ccb801..e188cf72d 100644 --- a/drivers/clk/imx/clk-imx.c +++ b/drivers/clk/imx/clk-imx.c @@ -69,8 +69,7 @@ const struct clk_ops clk_gate2_ops = { .is_enabled = clk_gate2_is_enabled, }; -static unsigned long clk_pll_recalc_rate(const struct clk *clk, - unsigned long prate) +static uint64_t clk_pll_recalc_rate(const struct clk *clk, uint64_t prate) { /* TODO: This function is derived from Linux codebase, but seems wrong * according to the datasheet as PLL_REFCLK_DIV_VAL[5:10] is never used. */ @@ -83,12 +82,10 @@ static unsigned long clk_pll_recalc_rate(const struct clk *clk, output_div_val = (output_div_val + 1) * 2; /* Valid Frac Divider value is 1 to 2^24 */ - uint32_t frac_div_val = regmap_read_bits(clk->base, data->offset + 0x4, 7, - 24); + uint32_t frac_div_val = regmap_read_bits(clk->base, data->offset + 0x4, 7, 24); /* Valid Int Divider value is 1 to 32 */ - uint32_t int_div_val = regmap_read_bits(clk->base, data->offset + 0x4, 0, - 7); + uint32_t int_div_val = regmap_read_bits(clk->base, data->offset + 0x4, 0, 7); temp_rate *= prate; temp_rate *= frac_div_val; @@ -112,8 +109,7 @@ const struct clk_ops clk_frac_pll_ops = { /* .set_rate = clk_pll_set_rate, */ }; -static unsigned long clk_sscg_pll_recalc_rate(const struct clk *clk, - unsigned long prate) +static uint64_t clk_sscg_pll_recalc_rate(const struct clk *clk, uint64_t prate) { struct clk_sscg_pll_data *data = (struct clk_sscg_pll_data *)(clk->data); uint64_t temp_rate = prate; @@ -173,26 +169,21 @@ const struct clk_ops clk_sscg_pll_ops = { /* .determine_rate = clk_sscg_pll_determine_rate, */ }; -static unsigned long imx8m_clk_core_slice_recalc_rate(const struct clk *clk, - unsigned long prate) +static uint64_t imx8m_clk_core_slice_recalc_rate(const struct clk *clk, uint64_t prate) { - struct clk_core_slice_data *data = - (struct clk_core_slice_data *)(clk->data); + struct clk_core_slice_data *data = (struct clk_core_slice_data *)(clk->data); - uint32_t div_val = regmap_read_bits(clk->base, data->offset, - data->div_shift, data->div_width); + uint32_t div_val = regmap_read_bits(clk->base, data->offset, data->div_shift, data->div_width); /* Divider value is n+1 */ return DIV_ROUND_UP_ULL((uint64_t)prate, div_val + 1); } static uint8_t imx8m_clk_core_slice_get_parent(const struct clk *clk) { - struct clk_core_slice_data *data = - (struct clk_core_slice_data *)(clk->data); + struct clk_core_slice_data *data = (struct clk_core_slice_data *)(clk->data); uint32_t num_parents = clk->hw.init->num_parents; - uint32_t val = regmap_mux_read_bits(clk->base, data->offset, - data->mux_shift, data->mux_mask); + uint32_t val = regmap_mux_read_bits(clk->base, data->offset, data->mux_shift, data->mux_mask); if (val >= num_parents) return -1; @@ -202,17 +193,14 @@ static uint8_t imx8m_clk_core_slice_get_parent(const struct clk *clk) static int imx8m_clk_core_slice_set_parent(struct clk *clk, uint8_t index) { - struct clk_core_slice_data *data = - (struct clk_core_slice_data *)(clk->data); + struct clk_core_slice_data *data = (struct clk_core_slice_data *)(clk->data); /* * write twice to make sure non-target interface * SEL_A/B point the same clk input. */ - regmap_mux_update_bits(clk->base, data->offset, data->mux_shift, - data->mux_mask, index); - regmap_mux_update_bits(clk->base, data->offset, data->mux_shift, - data->mux_mask, index); + regmap_mux_update_bits(clk->base, data->offset, data->mux_shift, data->mux_mask, index); + regmap_mux_update_bits(clk->base, data->offset, data->mux_shift, data->mux_mask, index); return 0; } @@ -226,32 +214,25 @@ const struct clk_ops clk_core_slice_ops = { .set_parent = imx8m_clk_core_slice_set_parent, }; -static unsigned long imx8m_clk_common_slice_recalc_rate(const struct clk *clk, - unsigned long prate) +static uint64_t imx8m_clk_common_slice_recalc_rate(const struct clk *clk, uint64_t prate) { - struct clk_common_slice_data *data = - (struct clk_common_slice_data *)(clk->data); + struct clk_common_slice_data *data = (struct clk_common_slice_data *)(clk->data); - uint32_t prediv_val = regmap_read_bits( - clk->base, data->offset, data->prevdiv_shift, data->prevdiv_width); + uint32_t prediv_val = regmap_read_bits(clk->base, data->offset, data->prevdiv_shift, data->prevdiv_width); /* Divider value is n+1 */ - unsigned long prediv_rate = DIV_ROUND_UP_ULL((uint64_t)prate, - prediv_val + 1); + uint64_t prediv_rate = DIV_ROUND_UP_ULL((uint64_t)prate, prediv_val + 1); - uint32_t postdiv_val = regmap_read_bits( - clk->base, data->offset, data->postdiv_shift, data->postdiv_width); + uint32_t postdiv_val = regmap_read_bits(clk->base, data->offset, data->postdiv_shift, data->postdiv_width); /* Divider value is n+1 */ return DIV_ROUND_UP_ULL((uint64_t)prediv_rate, postdiv_val + 1); } static uint8_t imx8m_clk_common_slice_get_parent(const struct clk *clk) { - struct clk_common_slice_data *data = - (struct clk_common_slice_data *)(clk->data); + struct clk_common_slice_data *data = (struct clk_common_slice_data *)(clk->data); uint32_t num_parents = clk->hw.init->num_parents; - uint32_t val = regmap_mux_read_bits(clk->base, data->offset, - data->mux_shift, data->mux_mask); + uint32_t val = regmap_mux_read_bits(clk->base, data->offset, data->mux_shift, data->mux_mask); if (val >= num_parents) return -1; @@ -261,17 +242,14 @@ static uint8_t imx8m_clk_common_slice_get_parent(const struct clk *clk) static int imx8m_clk_common_slice_set_parent(struct clk *clk, uint8_t index) { - struct clk_common_slice_data *data = - (struct clk_common_slice_data *)(clk->data); + struct clk_common_slice_data *data = (struct clk_common_slice_data *)(clk->data); /* * write twice to make sure non-target interface * SEL_A/B point the same clk input. */ - regmap_mux_update_bits(clk->base, data->offset, data->mux_shift, - data->mux_mask, index); - regmap_mux_update_bits(clk->base, data->offset, data->mux_shift, - data->mux_mask, index); + regmap_mux_update_bits(clk->base, data->offset, data->mux_shift, data->mux_mask, index); + regmap_mux_update_bits(clk->base, data->offset, data->mux_shift, data->mux_mask, index); return 0; } @@ -285,19 +263,15 @@ const struct clk_ops clk_common_slice_ops = { .set_parent = imx8m_clk_common_slice_set_parent, }; -static unsigned long imx8m_clk_bus_slice_recalc_rate(const struct clk *clk, - unsigned long prate) +static uint64_t imx8m_clk_bus_slice_recalc_rate(const struct clk *clk, uint64_t prate) { struct clk_bus_slice_data *data = (struct clk_bus_slice_data *)(clk->data); - uint32_t prediv_val = regmap_read_bits( - clk->base, data->offset, data->prevdiv_shift, data->prevdiv_width); + uint32_t prediv_val = regmap_read_bits(clk->base, data->offset, data->prevdiv_shift, data->prevdiv_width); /* Divider value is n+1 */ - unsigned long prediv_rate = DIV_ROUND_UP_ULL((uint64_t)prate, - prediv_val + 1); + uint64_t prediv_rate = DIV_ROUND_UP_ULL((uint64_t)prate, prediv_val + 1); - uint32_t postdiv_val = regmap_read_bits( - clk->base, data->offset, data->postdiv_shift, data->postdiv_width); + uint32_t postdiv_val = regmap_read_bits(clk->base, data->offset, data->postdiv_shift, data->postdiv_width); /* Divider value is n+1 */ return DIV_ROUND_UP_ULL((uint64_t)prediv_rate, postdiv_val + 1); } @@ -307,8 +281,7 @@ static uint8_t imx8m_clk_bus_slice_get_parent(const struct clk *clk) struct clk_bus_slice_data *data = (struct clk_bus_slice_data *)(clk->data); uint32_t num_parents = clk->hw.init->num_parents; - uint32_t val = regmap_mux_read_bits(clk->base, data->offset, - data->mux_shift, data->mux_mask); + uint32_t val = regmap_mux_read_bits(clk->base, data->offset, data->mux_shift, data->mux_mask); if (val >= num_parents) return -1; @@ -324,10 +297,8 @@ static int imx8m_clk_bus_slice_set_parent(struct clk *clk, uint8_t index) * write twice to make sure non-target interface * SEL_A/B point the same clk input. */ - regmap_mux_update_bits(clk->base, data->offset, data->mux_shift, - data->mux_mask, index); - regmap_mux_update_bits(clk->base, data->offset, data->mux_shift, - data->mux_mask, index); + regmap_mux_update_bits(clk->base, data->offset, data->mux_shift, data->mux_mask, index); + regmap_mux_update_bits(clk->base, data->offset, data->mux_shift, data->mux_mask, index); return 0; } diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 78a3807b6..0bf1d4cd6 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -2382,88 +2382,58 @@ static IMX_CLK_SOURCE(clk_ext2, 0x7ed6b40); static IMX_CLK_SOURCE(clk_ext3, 0x7ed6b40); static IMX_CLK_SOURCE(clk_ext4, 0x7ed6b40); -static IMX_CLK_MUX(arm_pll_ref_sel, CCM_ANALOG_BASE, 0x28, 16, 2, pll_ref_sels, - ARRAY_SIZE(pll_ref_sels)); -static IMX_CLK_MUX(gpu_pll_ref_sel, CCM_ANALOG_BASE, 0x18, 16, 2, pll_ref_sels, - ARRAY_SIZE(pll_ref_sels)); -static IMX_CLK_MUX(vpu_pll_ref_sel, CCM_ANALOG_BASE, 0x20, 16, 2, pll_ref_sels, - ARRAY_SIZE(pll_ref_sels)); -static IMX_CLK_MUX(audio_pll1_ref_sel, CCM_ANALOG_BASE, 0x0, 16, 2, - pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); -static IMX_CLK_MUX(audio_pll2_ref_sel, CCM_ANALOG_BASE, 0x8, 16, 2, - pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); -static IMX_CLK_MUX(video_pll1_ref_sel, CCM_ANALOG_BASE, 0x10, 16, 2, - pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); -static IMX_CLK_MUX(sys3_pll1_ref_sel, CCM_ANALOG_BASE, 0x48, 0, 2, pll_ref_sels, - ARRAY_SIZE(pll_ref_sels)); -static IMX_CLK_MUX(dram_pll1_ref_sel, CCM_ANALOG_BASE, 0x60, 0, 2, pll_ref_sels, - ARRAY_SIZE(pll_ref_sels)); -static IMX_CLK_MUX(video2_pll1_ref_sel, CCM_ANALOG_BASE, 0x54, 0, 2, - pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - -static IMX_CLK_DIV(arm_pll_ref_div, { &arm_pll_ref_sel }, CCM_ANALOG_BASE, 0x28, - 5, 6); -static IMX_CLK_DIV(gpu_pll_ref_div, { &gpu_pll_ref_sel }, CCM_ANALOG_BASE, 0x18, - 5, 6); -static IMX_CLK_DIV(vpu_pll_ref_div, { &vpu_pll_ref_sel }, CCM_ANALOG_BASE, 0x20, - 5, 6); -static IMX_CLK_DIV(audio_pll1_ref_div, { &audio_pll1_ref_sel }, CCM_ANALOG_BASE, - 0x0, 5, 6); -static IMX_CLK_DIV(audio_pll2_ref_div, { &audio_pll2_ref_sel }, CCM_ANALOG_BASE, - 0x8, 5, 6); -static IMX_CLK_DIV(video_pll1_ref_div, { &video_pll1_ref_sel }, CCM_ANALOG_BASE, - 0x10, 5, 6); +static IMX_CLK_MUX(arm_pll_ref_sel, CCM_ANALOG_BASE, 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); +static IMX_CLK_MUX(gpu_pll_ref_sel, CCM_ANALOG_BASE, 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); +static IMX_CLK_MUX(vpu_pll_ref_sel, CCM_ANALOG_BASE, 0x20, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); +static IMX_CLK_MUX(audio_pll1_ref_sel, CCM_ANALOG_BASE, 0x0, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); +static IMX_CLK_MUX(audio_pll2_ref_sel, CCM_ANALOG_BASE, 0x8, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); +static IMX_CLK_MUX(video_pll1_ref_sel, CCM_ANALOG_BASE, 0x10, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); +static IMX_CLK_MUX(sys3_pll1_ref_sel, CCM_ANALOG_BASE, 0x48, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); +static IMX_CLK_MUX(dram_pll1_ref_sel, CCM_ANALOG_BASE, 0x60, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); +static IMX_CLK_MUX(video2_pll1_ref_sel, CCM_ANALOG_BASE, 0x54, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + +static IMX_CLK_DIV(arm_pll_ref_div, { &arm_pll_ref_sel }, CCM_ANALOG_BASE, 0x28, 5, 6); +static IMX_CLK_DIV(gpu_pll_ref_div, { &gpu_pll_ref_sel }, CCM_ANALOG_BASE, 0x18, 5, 6); +static IMX_CLK_DIV(vpu_pll_ref_div, { &vpu_pll_ref_sel }, CCM_ANALOG_BASE, 0x20, 5, 6); +static IMX_CLK_DIV(audio_pll1_ref_div, { &audio_pll1_ref_sel }, CCM_ANALOG_BASE, 0x0, 5, 6); +static IMX_CLK_DIV(audio_pll2_ref_div, { &audio_pll2_ref_sel }, CCM_ANALOG_BASE, 0x8, 5, 6); +static IMX_CLK_DIV(video_pll1_ref_div, { &video_pll1_ref_sel }, CCM_ANALOG_BASE, 0x10, 5, 6); static IMX_CLK_FRAC_PLL(arm_pll, { &arm_pll_ref_div }, CCM_ANALOG_BASE, 0x28); static IMX_CLK_FRAC_PLL(gpu_pll, { &gpu_pll_ref_div }, CCM_ANALOG_BASE, 0x18); static IMX_CLK_FRAC_PLL(vpu_pll, { &vpu_pll_ref_div }, CCM_ANALOG_BASE, 0x20); -static IMX_CLK_FRAC_PLL(audio_pll1, { &audio_pll1_ref_div }, CCM_ANALOG_BASE, - 0x0); -static IMX_CLK_FRAC_PLL(audio_pll2, { &audio_pll2_ref_div }, CCM_ANALOG_BASE, - 0x8); -static IMX_CLK_FRAC_PLL(video_pll1, { &video_pll1_ref_div }, CCM_ANALOG_BASE, - 0x10); +static IMX_CLK_FRAC_PLL(audio_pll1, { &audio_pll1_ref_div }, CCM_ANALOG_BASE, 0x0); +static IMX_CLK_FRAC_PLL(audio_pll2, { &audio_pll2_ref_div }, CCM_ANALOG_BASE, 0x8); +static IMX_CLK_FRAC_PLL(video_pll1, { &video_pll1_ref_div }, CCM_ANALOG_BASE, 0x10); /* PLL bypass out */ -static IMX_CLK_MUX_FLAGS(arm_pll_bypass, CCM_ANALOG_BASE, 0x28, 14, 1, - arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), - CLK_SET_RATE_PARENT); -static IMX_CLK_MUX(gpu_pll_bypass, CCM_ANALOG_BASE, 0x18, 14, 1, - gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels)); -static IMX_CLK_MUX(vpu_pll_bypass, CCM_ANALOG_BASE, 0x20, 14, 1, - vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels)); -static IMX_CLK_MUX(audio_pll1_bypass, CCM_ANALOG_BASE, 0x0, 14, 1, - audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels)); -static IMX_CLK_MUX(audio_pll2_bypass, CCM_ANALOG_BASE, 0x8, 14, 1, - audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels)); -static IMX_CLK_MUX(video_pll1_bypass, CCM_ANALOG_BASE, 0x10, 14, 1, - video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels)); +static IMX_CLK_MUX_FLAGS(arm_pll_bypass, CCM_ANALOG_BASE, 0x28, 14, 1, arm_pll_bypass_sels, + ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT); +static IMX_CLK_MUX(gpu_pll_bypass, CCM_ANALOG_BASE, 0x18, 14, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels)); +static IMX_CLK_MUX(vpu_pll_bypass, CCM_ANALOG_BASE, 0x20, 14, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels)); +static IMX_CLK_MUX(audio_pll1_bypass, CCM_ANALOG_BASE, 0x0, 14, 1, audio_pll1_bypass_sels, + ARRAY_SIZE(audio_pll1_bypass_sels)); +static IMX_CLK_MUX(audio_pll2_bypass, CCM_ANALOG_BASE, 0x8, 14, 1, audio_pll2_bypass_sels, + ARRAY_SIZE(audio_pll2_bypass_sels)); +static IMX_CLK_MUX(video_pll1_bypass, CCM_ANALOG_BASE, 0x10, 14, 1, video_pll1_bypass_sels, + ARRAY_SIZE(video_pll1_bypass_sels)); /* PLL OUT GATE */ -static IMX_CLK_GATE(arm_pll_out, { &arm_pll_bypass }, CCM_ANALOG_BASE, 0x28, - 21); -static IMX_CLK_GATE(gpu_pll_out, { &gpu_pll_bypass }, CCM_ANALOG_BASE, 0x18, - 21); -static IMX_CLK_GATE(vpu_pll_out, { &vpu_pll_bypass }, CCM_ANALOG_BASE, 0x20, - 21); -static IMX_CLK_GATE(audio_pll1_out, { &audio_pll1_bypass }, CCM_ANALOG_BASE, - 0x0, 21); -static IMX_CLK_GATE(audio_pll2_out, { &audio_pll2_bypass }, CCM_ANALOG_BASE, - 0x8, 21); -static IMX_CLK_GATE(video_pll1_out, { &video_pll1_bypass }, CCM_ANALOG_BASE, - 0x10, 21); +static IMX_CLK_GATE(arm_pll_out, { &arm_pll_bypass }, CCM_ANALOG_BASE, 0x28, 21); +static IMX_CLK_GATE(gpu_pll_out, { &gpu_pll_bypass }, CCM_ANALOG_BASE, 0x18, 21); +static IMX_CLK_GATE(vpu_pll_out, { &vpu_pll_bypass }, CCM_ANALOG_BASE, 0x20, 21); +static IMX_CLK_GATE(audio_pll1_out, { &audio_pll1_bypass }, CCM_ANALOG_BASE, 0x0, 21); +static IMX_CLK_GATE(audio_pll2_out, { &audio_pll2_bypass }, CCM_ANALOG_BASE, 0x8, 21); +static IMX_CLK_GATE(video_pll1_out, { &video_pll1_bypass }, CCM_ANALOG_BASE, 0x10, 21); static IMX_CLK_FIXED(sys1_pll_out, 800000000); static IMX_CLK_FIXED(sys2_pll_out, 1000000000); -static IMX_CLK_SSCG_PLL(sys3_pll_out, sys3_pll_out_sels, - ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 0, CCM_ANALOG_BASE, - 0x48, CLK_IS_CRITICAL); -static IMX_CLK_SSCG_PLL(dram_pll_out, dram_pll_out_sels, - ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, CCM_ANALOG_BASE, - 0x60, CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE); -static IMX_CLK_SSCG_PLL(video2_pll_out, video2_pll_out_sels, - ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, - CCM_ANALOG_BASE, 0x54, 0); +static IMX_CLK_SSCG_PLL(sys3_pll_out, sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 0, CCM_ANALOG_BASE, 0x48, + CLK_IS_CRITICAL); +static IMX_CLK_SSCG_PLL(dram_pll_out, dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, CCM_ANALOG_BASE, 0x60, + CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE); +static IMX_CLK_SSCG_PLL(video2_pll_out, video2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, CCM_ANALOG_BASE, + 0x54, 0); /* SYS PLL1 fixed output */ static IMX_CLK_FIXED_FACTOR(sys1_pll_40m, { &sys1_pll_out }, 1, 20); @@ -2487,56 +2457,40 @@ static IMX_CLK_FIXED_FACTOR(sys2_pll_333m, { &sys2_pll_out }, 1, 3); static IMX_CLK_FIXED_FACTOR(sys2_pll_500m, { &sys2_pll_out }, 1, 2); static IMX_CLK_FIXED_FACTOR(sys2_pll_1000m, { &sys2_pll_out }, 1, 1); -static IMX_CLK_DIV(audio_pll1_out_monitor, { &audio_pll1_bypass }, - CCM_ANALOG_BASE, 0x78, 0, 3); -static IMX_CLK_DIV(audio_pll2_out_monitor, { &audio_pll2_bypass }, - CCM_ANALOG_BASE, 0x78, 4, 3); -static IMX_CLK_DIV(video_pll1_out_monitor, { &video_pll1_bypass }, - CCM_ANALOG_BASE, 0x78, 8, 3); -static IMX_CLK_DIV(gpu_pll_out_monitor, { &gpu_pll_bypass }, CCM_ANALOG_BASE, - 0x78, 12, 3); -static IMX_CLK_DIV(vpu_pll_out_monitor, { &vpu_pll_bypass }, CCM_ANALOG_BASE, - 0x78, 16, 3); -static IMX_CLK_DIV(arm_pll_out_monitor, { &arm_pll_bypass }, CCM_ANALOG_BASE, - 0x78, 20, 3); -static IMX_CLK_DIV(sys_pll1_out_monitor, { &sys1_pll_out }, CCM_ANALOG_BASE, - 0x7c, 0, 3); -static IMX_CLK_DIV(sys_pll2_out_monitor, { &sys2_pll_out }, CCM_ANALOG_BASE, - 0x7c, 4, 3); -static IMX_CLK_DIV(sys_pll3_out_monitor, { &sys3_pll_out }, CCM_ANALOG_BASE, - 0x7c, 8, 3); -static IMX_CLK_DIV(dram_pll_out_monitor, { &dram_pll_out }, CCM_ANALOG_BASE, - 0x7c, 12, 3); -static IMX_CLK_DIV(video_pll2_out_monitor, { &video2_pll_out }, CCM_ANALOG_BASE, - 0x7c, 16, 3); -static IMX_CLK_MUX(pllout_monitor_sel, CCM_ANALOG_BASE, 0x74, 0, 4, - pllout_monitor_sels, ARRAY_SIZE(pllout_monitor_sels)); -static IMX_CLK_GATE(pllout_monitor_clk2, { &pllout_monitor_sel }, - CCM_ANALOG_BASE, 0x74, 4); +static IMX_CLK_DIV(audio_pll1_out_monitor, { &audio_pll1_bypass }, CCM_ANALOG_BASE, 0x78, 0, 3); +static IMX_CLK_DIV(audio_pll2_out_monitor, { &audio_pll2_bypass }, CCM_ANALOG_BASE, 0x78, 4, 3); +static IMX_CLK_DIV(video_pll1_out_monitor, { &video_pll1_bypass }, CCM_ANALOG_BASE, 0x78, 8, 3); +static IMX_CLK_DIV(gpu_pll_out_monitor, { &gpu_pll_bypass }, CCM_ANALOG_BASE, 0x78, 12, 3); +static IMX_CLK_DIV(vpu_pll_out_monitor, { &vpu_pll_bypass }, CCM_ANALOG_BASE, 0x78, 16, 3); +static IMX_CLK_DIV(arm_pll_out_monitor, { &arm_pll_bypass }, CCM_ANALOG_BASE, 0x78, 20, 3); +static IMX_CLK_DIV(sys_pll1_out_monitor, { &sys1_pll_out }, CCM_ANALOG_BASE, 0x7c, 0, 3); +static IMX_CLK_DIV(sys_pll2_out_monitor, { &sys2_pll_out }, CCM_ANALOG_BASE, 0x7c, 4, 3); +static IMX_CLK_DIV(sys_pll3_out_monitor, { &sys3_pll_out }, CCM_ANALOG_BASE, 0x7c, 8, 3); +static IMX_CLK_DIV(dram_pll_out_monitor, { &dram_pll_out }, CCM_ANALOG_BASE, 0x7c, 12, 3); +static IMX_CLK_DIV(video_pll2_out_monitor, { &video2_pll_out }, CCM_ANALOG_BASE, 0x7c, 16, 3); +static IMX_CLK_MUX(pllout_monitor_sel, CCM_ANALOG_BASE, 0x74, 0, 4, pllout_monitor_sels, + ARRAY_SIZE(pllout_monitor_sels)); +static IMX_CLK_GATE(pllout_monitor_clk2, { &pllout_monitor_sel }, CCM_ANALOG_BASE, 0x74, 4); /* CORE */ static IMX_CLK_COMPOSITE_CORE(arm_a53_div, imx8mq_a53_sels, CCM_BASE, 0x8000); -static IMX_CLK_COMPOSITE_CORE(arm_m4_core, imx8mq_arm_m4_sels, CCM_BASE, - 0x8080); +static IMX_CLK_COMPOSITE_CORE(arm_m4_core, imx8mq_arm_m4_sels, CCM_BASE, 0x8080); static IMX_CLK_COMPOSITE_CORE(vpu_core, imx8mq_vpu_sels, CCM_BASE, 0x8100); static IMX_CLK_COMPOSITE_CORE(gpu_core, imx8mq_gpu_core_sels, CCM_BASE, 0x8180); static IMX_CLK_COMPOSITE(gpu_shader, imx8mq_gpu_shader_sels, CCM_BASE, 0x8200); /* CORE SEL */ -static IMX_CLK_MUX2(arm_a53_core, CCM_BASE, 0x9880, 24, 1, imx8mq_a53_core_sels, - ARRAY_SIZE(imx8mq_a53_core_sels)); +static IMX_CLK_MUX2(arm_a53_core, CCM_BASE, 0x9880, 24, 1, imx8mq_a53_core_sels, ARRAY_SIZE(imx8mq_a53_core_sels)); /* BUS */ static IMX_CLK_COMPOSITE_BUS(main_axi, imx8mq_main_axi_sels, CCM_BASE, 0x8800); static IMX_CLK_COMPOSITE_BUS(enet_axi, imx8mq_enet_axi_sels, CCM_BASE, 0x8880); -static IMX_CLK_COMPOSITE_BUS(nand_usdhc_bus, imx8mq_nand_usdhc_sels, CCM_BASE, - 0x8900); +static IMX_CLK_COMPOSITE_BUS(nand_usdhc_bus, imx8mq_nand_usdhc_sels, CCM_BASE, 0x8900); static IMX_CLK_COMPOSITE_BUS(vpu_bus, imx8mq_vpu_bus_sels, CCM_BASE, 0x8980); static IMX_CLK_COMPOSITE_BUS(disp_axi, imx8mq_disp_axi_sels, CCM_BASE, 0x8a00); static IMX_CLK_COMPOSITE_BUS(disp_apb, imx8mq_disp_apb_sels, CCM_BASE, 0x8a80); -static IMX_CLK_COMPOSITE_BUS(disp_rtrm, imx8mq_disp_rtrm_sels, CCM_BASE, - 0x8b00); +static IMX_CLK_COMPOSITE_BUS(disp_rtrm, imx8mq_disp_rtrm_sels, CCM_BASE, 0x8b00); static IMX_CLK_COMPOSITE_BUS(usb_bus, imx8mq_usb_bus_sels, CCM_BASE, 0x8b80); static IMX_CLK_COMPOSITE_BUS(gpu_axi, imx8mq_gpu_axi_sels, CCM_BASE, 0x8c00); static IMX_CLK_COMPOSITE_BUS(gpu_ahb, imx8mq_gpu_ahb_sels, CCM_BASE, 0x8c80); @@ -2546,8 +2500,7 @@ static IMX_CLK_COMPOSITE_BUS(noc_apb, imx8mq_noc_apb_sels, CCM_BASE, 0x8d80); /* AHB */ /* AHB clock is used by the AHB bus therefore marked as critical */ static IMX_CLK_COMPOSITE_BUS(ahb, imx8mq_ahb_sels, CCM_BASE, 0x9000); -static IMX_CLK_COMPOSITE_BUS(audio_ahb, imx8mq_audio_ahb_sels, CCM_BASE, - 0x9100); +static IMX_CLK_COMPOSITE_BUS(audio_ahb, imx8mq_audio_ahb_sels, CCM_BASE, 0x9100); /* IPG */ static IMX_CLK_DIV2(ipg_root, { &ahb }, CCM_BASE, 0x9080, 0, 1); @@ -2558,26 +2511,21 @@ static IMX_CLK_DIV2(ipg_audio_root, { &audio_ahb }, CCM_BASE, 0x9180, 0, 1); * The fw_managed helper sets GET_RATE_NOCACHE and clears SET_PARENT_GATE * as div value should always be read from hardware */ -static IMX_CLK_MUX2_FLAGS(dram_core_clk, CCM_BASE, 0x9800, 24, 1, - imx8mq_dram_core_sels, +static IMX_CLK_MUX2_FLAGS(dram_core_clk, CCM_BASE, 0x9800, 24, 1, imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels), CLK_IS_CRITICAL); -static IMX_CLK_COMPOSITE_FW_MANAGED(dram_alt, imx8mq_dram_alt_sels, CCM_BASE, - 0xa000); -static IMX_CLK_COMPOSITE_FW_MANAGED_CRITICAL(dram_apb, imx8mq_dram_apb_sels, - CCM_BASE, 0xa080); +static IMX_CLK_COMPOSITE_FW_MANAGED(dram_alt, imx8mq_dram_alt_sels, CCM_BASE, 0xa000); +static IMX_CLK_COMPOSITE_FW_MANAGED_CRITICAL(dram_apb, imx8mq_dram_apb_sels, CCM_BASE, 0xa080); /* IP */ static IMX_CLK_COMPOSITE(vpu_g1, imx8mq_vpu_g1_sels, CCM_BASE, 0xa100); static IMX_CLK_COMPOSITE(vpu_g2, imx8mq_vpu_g2_sels, CCM_BASE, 0xa180); static IMX_CLK_COMPOSITE(disp_dtrc, imx8mq_disp_dtrc_sels, CCM_BASE, 0xa200); -static IMX_CLK_COMPOSITE(disp_dc8000, imx8mq_disp_dc8000_sels, CCM_BASE, - 0xa280); +static IMX_CLK_COMPOSITE(disp_dc8000, imx8mq_disp_dc8000_sels, CCM_BASE, 0xa280); static IMX_CLK_COMPOSITE(pcie1_ctrl, imx8mq_pcie1_ctrl_sels, CCM_BASE, 0xa300); static IMX_CLK_COMPOSITE(pcie1_phy, imx8mq_pcie1_phy_sels, CCM_BASE, 0xa380); static IMX_CLK_COMPOSITE(pcie1_aux, imx8mq_pcie1_aux_sels, CCM_BASE, 0xa400); static IMX_CLK_COMPOSITE(dc_pixel, imx8mq_dc_pixel_sels, CCM_BASE, 0xa480); -static IMX_CLK_COMPOSITE(lcdif_pixel, imx8mq_lcdif_pixel_sels, CCM_BASE, - 0xa500); +static IMX_CLK_COMPOSITE(lcdif_pixel, imx8mq_lcdif_pixel_sels, CCM_BASE, 0xa500); static IMX_CLK_COMPOSITE(sai1, imx8mq_sai1_sels, CCM_BASE, 0xa580); static IMX_CLK_COMPOSITE(sai2, imx8mq_sai2_sels, CCM_BASE, 0xa600); static IMX_CLK_COMPOSITE(sai3, imx8mq_sai3_sels, CCM_BASE, 0xa680); @@ -2656,34 +2604,20 @@ static IMX_CLK_GATE4(pwm3_root_clk, { &pwm3 }, CCM_BASE, 0x42a0, 0); static IMX_CLK_GATE4(pwm4_root_clk, { &pwm4 }, CCM_BASE, 0x42b0, 0); static IMX_CLK_GATE4(qspi_root_clk, { &qspi }, CCM_BASE, 0x42f0, 0); -static IMX_CLK_GATE2_SHARED2(nand_root_clk, { &nand }, CCM_BASE, 0x4300, 0, - &share_count_nand); -static IMX_CLK_GATE2_SHARED2(nand_usdhc_rawnand_clk, { &nand_usdhc_bus }, - CCM_BASE, 0x4300, 0, &share_count_nand); -static IMX_CLK_GATE2_SHARED2(sai1_root_clk, { &sai1 }, CCM_BASE, 0x4330, 0, - &share_count_sai1); -static IMX_CLK_GATE2_SHARED2(sai1_ipg_clk, { &ipg_audio_root }, CCM_BASE, - 0x4330, 0, &share_count_sai1); -static IMX_CLK_GATE2_SHARED2(sai2_root_clk, { &sai2 }, CCM_BASE, 0x4340, 0, - &share_count_sai2); -static IMX_CLK_GATE2_SHARED2(sai2_ipg_clk, { &ipg_root }, CCM_BASE, 0x4340, 0, - &share_count_sai2); -static IMX_CLK_GATE2_SHARED2(sai3_root_clk, { &sai3 }, CCM_BASE, 0x4350, 0, - &share_count_sai3); -static IMX_CLK_GATE2_SHARED2(sai3_ipg_clk, { &ipg_root }, CCM_BASE, 0x4350, 0, - &share_count_sai3); -static IMX_CLK_GATE2_SHARED2(sai4_root_clk, { &sai4 }, CCM_BASE, 0x4360, 0, - &share_count_sai4); -static IMX_CLK_GATE2_SHARED2(sai4_ipg_clk, { &ipg_audio_root }, CCM_BASE, - 0x4360, 0, &share_count_sai4); -static IMX_CLK_GATE2_SHARED2(sai5_root_clk, { &sai5 }, CCM_BASE, 0x4370, 0, - &share_count_sai5); -static IMX_CLK_GATE2_SHARED2(sai5_ipg_clk, { &ipg_audio_root }, CCM_BASE, - 0x4370, 0, &share_count_sai5); -static IMX_CLK_GATE2_SHARED2(sai6_root_clk, { &sai6 }, CCM_BASE, 0x4380, 0, - &share_count_sai6); -static IMX_CLK_GATE2_SHARED2(sai6_ipg_clk, { &ipg_audio_root }, CCM_BASE, - 0x4380, 0, &share_count_sai6); +static IMX_CLK_GATE2_SHARED2(nand_root_clk, { &nand }, CCM_BASE, 0x4300, 0, &share_count_nand); +static IMX_CLK_GATE2_SHARED2(nand_usdhc_rawnand_clk, { &nand_usdhc_bus }, CCM_BASE, 0x4300, 0, &share_count_nand); +static IMX_CLK_GATE2_SHARED2(sai1_root_clk, { &sai1 }, CCM_BASE, 0x4330, 0, &share_count_sai1); +static IMX_CLK_GATE2_SHARED2(sai1_ipg_clk, { &ipg_audio_root }, CCM_BASE, 0x4330, 0, &share_count_sai1); +static IMX_CLK_GATE2_SHARED2(sai2_root_clk, { &sai2 }, CCM_BASE, 0x4340, 0, &share_count_sai2); +static IMX_CLK_GATE2_SHARED2(sai2_ipg_clk, { &ipg_root }, CCM_BASE, 0x4340, 0, &share_count_sai2); +static IMX_CLK_GATE2_SHARED2(sai3_root_clk, { &sai3 }, CCM_BASE, 0x4350, 0, &share_count_sai3); +static IMX_CLK_GATE2_SHARED2(sai3_ipg_clk, { &ipg_root }, CCM_BASE, 0x4350, 0, &share_count_sai3); +static IMX_CLK_GATE2_SHARED2(sai4_root_clk, { &sai4 }, CCM_BASE, 0x4360, 0, &share_count_sai4); +static IMX_CLK_GATE2_SHARED2(sai4_ipg_clk, { &ipg_audio_root }, CCM_BASE, 0x4360, 0, &share_count_sai4); +static IMX_CLK_GATE2_SHARED2(sai5_root_clk, { &sai5 }, CCM_BASE, 0x4370, 0, &share_count_sai5); +static IMX_CLK_GATE2_SHARED2(sai5_ipg_clk, { &ipg_audio_root }, CCM_BASE, 0x4370, 0, &share_count_sai5); +static IMX_CLK_GATE2_SHARED2(sai6_root_clk, { &sai6 }, CCM_BASE, 0x4380, 0, &share_count_sai6); +static IMX_CLK_GATE2_SHARED2(sai6_ipg_clk, { &ipg_audio_root }, CCM_BASE, 0x4380, 0, &share_count_sai6); static IMX_CLK_GATE4(uart1_root_clk, { &uart1 }, CCM_BASE, 0x4490, 0); static IMX_CLK_GATE4(uart2_root_clk, { &uart2 }, CCM_BASE, 0x44a0, 0); static IMX_CLK_GATE4(uart3_root_clk, { &uart3 }, CCM_BASE, 0x44b0, 0); @@ -2702,14 +2636,10 @@ static IMX_CLK_GATE2_FLAGS(vpu_g1_root_clk, { &vpu_g1 }, CCM_BASE, 0x4560, 0, static IMX_CLK_GATE4(gpu_root_clk, { &gpu_core }, CCM_BASE, 0x4570, 0); static IMX_CLK_GATE2_FLAGS(vpu_g2_root_clk, { &vpu_g2 }, CCM_BASE, 0x45a0, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); -static IMX_CLK_GATE2_SHARED2(disp_root_clk, { &disp_dc8000 }, CCM_BASE, 0x45d0, - 0, &share_count_dcss); -static IMX_CLK_GATE2_SHARED2(disp_axi_root_clk, { &disp_axi }, CCM_BASE, 0x45d0, - 0, &share_count_dcss); -static IMX_CLK_GATE2_SHARED2(disp_apb_root_clk, { &disp_apb }, CCM_BASE, 0x45d0, - 0, &share_count_dcss); -static IMX_CLK_GATE2_SHARED2(disp_rtrm_root_clk, { &disp_rtrm }, CCM_BASE, - 0x45d0, 0, &share_count_dcss); +static IMX_CLK_GATE2_SHARED2(disp_root_clk, { &disp_dc8000 }, CCM_BASE, 0x45d0, 0, &share_count_dcss); +static IMX_CLK_GATE2_SHARED2(disp_axi_root_clk, { &disp_axi }, CCM_BASE, 0x45d0, 0, &share_count_dcss); +static IMX_CLK_GATE2_SHARED2(disp_apb_root_clk, { &disp_apb }, CCM_BASE, 0x45d0, 0, &share_count_dcss); +static IMX_CLK_GATE2_SHARED2(disp_rtrm_root_clk, { &disp_rtrm }, CCM_BASE, 0x45d0, 0, &share_count_dcss); static IMX_CLK_GATE4(tmu_root_clk, { &ipg_root }, CCM_BASE, 0x4620, 0); static IMX_CLK_GATE2_FLAGS(vpu_dec_root_clk, { &vpu_bus }, CCM_BASE, 0x4630, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c index d17b3cae9..f05e2babf 100644 --- a/drivers/clk/imx/clk.c +++ b/drivers/clk/imx/clk.c @@ -98,14 +98,14 @@ const struct clk *get_parent(const struct clk *clk) /* TODO: Should be just read from the structure, but need to update everytime when */ /* related clocks are modified */ -uint32_t clk_get_rate(const struct clk *clk, uint64_t *rate) +int clk_get_rate(const struct clk *clk, uint64_t *rate) { if (!clk) return CLK_UNKNOWN_TARGET; const struct clk_init_data *init = (struct clk_init_data *)clk->hw.init; uint64_t parent_rate = 0; - uint32_t err = 0; + int err = 0; const struct clk *parent_clk = get_parent(clk); @@ -124,7 +124,7 @@ uint32_t clk_get_rate(const struct clk *clk, uint64_t *rate) return 0; } -uint32_t clk_enable(struct clk *clk) +int clk_enable(struct clk *clk) { if (!clk) return CLK_UNKNOWN_TARGET; @@ -136,7 +136,7 @@ uint32_t clk_enable(struct clk *clk) return CLK_INVALID_OP; } -uint32_t clk_disable(struct clk *clk) +int clk_disable(struct clk *clk) { if (!clk) return CLK_UNKNOWN_TARGET; @@ -148,7 +148,7 @@ uint32_t clk_disable(struct clk *clk) return CLK_INVALID_OP; } -uint32_t clk_set_rate(struct clk *clk, uint64_t req_rate, uint64_t *rate) +int clk_set_rate(struct clk *clk, uint64_t req_rate, uint64_t *rate) { if (!clk) return CLK_UNKNOWN_TARGET; @@ -161,7 +161,7 @@ uint32_t clk_set_rate(struct clk *clk, uint64_t req_rate, uint64_t *rate) const struct clk *pclk = get_parent(clk); uint64_t prate = 0; - uint32_t err = clk_get_rate(pclk, &prate); + int err = clk_get_rate(pclk, &prate); if (err) { LOG_DRIVER_ERR("Failed to get parent clock's rate\n"); return err; @@ -174,7 +174,7 @@ uint32_t clk_set_rate(struct clk *clk, uint64_t req_rate, uint64_t *rate) if (pclk && pclk->hw.init->ops->set_rate) { const struct clk *ppclk = get_parent(pclk); uint64_t pprate = 0; - uint32_t err = clk_get_rate(ppclk, &pprate); + int err = clk_get_rate(ppclk, &pprate); if (!err) { pclk->hw.init->ops->set_rate(pclk, prate, pprate); return 0; @@ -190,18 +190,17 @@ int clk_msr_stat() #ifdef DEBUG_DRIVER int i; uint64_t rate = 0; - uint32_t err; + int err; LOG_DRIVER("-------Expected clock rates------\n"); for (i = 0; i < NUM_CLK_LIST; i++) { if (clk_list[i]) { err = clk_get_rate(clk_list[i], &rate); if (err) { - LOG_DRIVER_ERR("Failed to get rate of %s: -%u\n", - clk_list[i]->hw.init->name, err); + LOG_DRIVER_ERR("Failed to get rate of %s: -%u\n", clk_list[i]->hw.init->name, err); + return err; } - LOG_DRIVER("[%4d][%10luHz] %s\n", i, rate, - clk_list[i]->hw.init->name); + LOG_DRIVER("[%4d][%10luHz] %s\n", i, rate, clk_list[i]->hw.init->name); } } LOG_DRIVER("-----------------------------\n"); @@ -244,7 +243,7 @@ void init(void) microkit_msginfo protected(microkit_channel ch, microkit_msginfo msginfo) { - uint32_t err = 0; + int err = 0; uint32_t argc = microkit_msginfo_get_count(msginfo); /* TODO: Check if the channel is valid */ @@ -296,8 +295,8 @@ microkit_msginfo protected(microkit_channel ch, microkit_msginfo msginfo) break; } default: - LOG_DRIVER_ERR("Unknown request %lu to clockk driver from channel %u\n", - microkit_msginfo_get_label(msginfo), ch); + LOG_DRIVER_ERR("Unknown request %lu to clockk driver from channel %u\n", microkit_msginfo_get_label(msginfo), + ch); err = CLK_UNKNOWN_REQ; } return microkit_msginfo_new(err, 0); diff --git a/drivers/clk/imx/include/clk-imx.h b/drivers/clk/imx/include/clk-imx.h index db012ba42..3fd64c125 100644 --- a/drivers/clk/imx/include/clk-imx.h +++ b/drivers/clk/imx/include/clk-imx.h @@ -154,8 +154,7 @@ struct clk _name = { \ #define IMX_CLK_FIXED(_name, _rate) \ IMX_CLK_SOURCE(_name, _rate) -#define IMX_CLK_MUX_FLAGS(_name, _base, _offset, _shift, _width, _parent_data, \ - _num_parents, _init_flags) \ +#define IMX_CLK_MUX_FLAGS(_name, _base, _offset, _shift, _width, _parent_data, _num_parents, _init_flags) \ struct clk _name = { \ .base = (_base), \ .data = &(struct clk_mux_data) { \ @@ -172,23 +171,19 @@ struct clk _name = { \ }, \ } -#define IMX_CLK_MUX(_name, _base, _offset, _shift, _width, _parent_data, \ - _num_parents) \ +#define IMX_CLK_MUX(_name, _base, _offset, _shift, _width, _parent_data, _num_parents) \ IMX_CLK_MUX_FLAGS(_name, _base, _offset, _shift, _width, \ _parent_data, _num_parents, 0) -#define IMX_CLK_MUX2(_name, _base, _offset, _shift, _width, _parent_data, \ - _num_parents) \ +#define IMX_CLK_MUX2(_name, _base, _offset, _shift, _width, _parent_data, _num_parents) \ IMX_CLK_MUX_FLAGS(_name, _base, _offset, _shift, _width, \ _parent_data, _num_parents, CLK_OPS_PARENT_ENABLE) -#define IMX_CLK_MUX2_FLAGS(_name, _base, _offset, _shift, _width, \ - _parent_data, _num_parents, _flags) \ +#define IMX_CLK_MUX2_FLAGS(_name, _base, _offset, _shift, _width, _parent_data, _num_parents, _flags) \ IMX_CLK_MUX_FLAGS(_name, _base, _offset, _shift, _width, \ _parent_data, _num_parents, _flags | CLK_OPS_PARENT_ENABLE) -#define IMX_CLK_DIV_FLAGS(_name, _parent_clks, _base, _offset, _shift, _width, \ - _flags) \ +#define IMX_CLK_DIV_FLAGS(_name, _parent_clks, _base, _offset, _shift, _width, _flags) \ struct clk _name = { \ .base = (_base), \ .data = &(struct clk_div_data) { \ @@ -244,8 +239,7 @@ struct clk _name = { \ }, \ } -#define IMX_CLK_GATE2_FLAGS(_name, _parent_clks, _base, _offset, _shift, \ - _flags) \ +#define IMX_CLK_GATE2_FLAGS(_name, _parent_clks, _base, _offset, _shift, _flags) \ struct clk _name = { \ .base = (_base), \ .data = &(struct clk_gate_data) { \ @@ -260,8 +254,7 @@ struct clk _name = { \ }, \ } -#define IMX_CLK_GATE2_SHARED2(_name, _parent_clks, _base, _offset, _shift, \ - _shared_count) \ +#define IMX_CLK_GATE2_SHARED2(_name, _parent_clks, _base, _offset, _shift, _shared_count) \ IMX_CLK_GATE2_FLAGS(_name, _parent_clks, _base, _offset, _shift, 0) #define IMX_CLK_GATE4(_name, _parent_clks, _base, _offset, _shift) \ @@ -270,8 +263,7 @@ IMX_CLK_GATE2_FLAGS(_name, _parent_clks, _base, _offset, _shift, 0) #define IMX_CLK_FIXED_FACTOR(_name, _parent_clks, _mult, _div) \ CLK_FIXED_FACTOR(_name, _mult, _div, 0, _parent_clks, 1, CLK_SET_RATE_PARENT) -#define IMX_CLK_SSCG_PLL(_name, _parent_data, _num_parents, _parent, _bypass1, \ - _bypass2, _base, _offset, _flags) \ +#define IMX_CLK_SSCG_PLL(_name, _parent_data, _num_parents, _parent, _bypass1, _bypass2, _base, _offset, _flags) \ struct clk _name = { \ .base = (_base), \ .data = &(struct clk_sscg_pll_data) { \ @@ -369,8 +361,7 @@ IMX_CLK_COMPOSITE_FLAGS(_name, _parent_data, _base, _offset, \ (CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE \ | CLK_GET_RATE_NOCACHE)) -#define IMX_CLK_COMPOSITE_FW_MANAGED_CRITICAL(_name, _parent_data, _base, \ - _offset) \ +#define IMX_CLK_COMPOSITE_FW_MANAGED_CRITICAL(_name, _parent_data, _base, _offset) \ IMX_CLK_COMPOSITE_FLAGS(_name, _parent_data, _base, _offset, \ (CLK_SET_RATE_NO_REPARENT | \ CLK_OPS_PARENT_ENABLE | \ diff --git a/drivers/clk/meson/clk-measure.c b/drivers/clk/meson/clk-measure.c index 5513fa288..a58d4fbb1 100644 --- a/drivers/clk/meson/clk-measure.c +++ b/drivers/clk/meson/clk-measure.c @@ -221,8 +221,7 @@ unsigned long clk_msr(unsigned long clk_mux) uint32_t msr_val = *mclk_reg2; - return DIV_ROUND_CLOSEST_ULL((msr_val & ((1 << 19) - 1)) * 1000000ULL, - duration); + return DIV_ROUND_CLOSEST_ULL((msr_val & ((1 << 19) - 1)) * 1000000ULL, duration); } const char *const *get_msr_clk_list(void) diff --git a/drivers/clk/meson/clk-meson.c b/drivers/clk/meson/clk-meson.c index 990cc2242..3cfa687fd 100644 --- a/drivers/clk/meson/clk-meson.c +++ b/drivers/clk/meson/clk-meson.c @@ -93,8 +93,7 @@ void delay_us(uint32_t us) } } -int regmap_multi_reg_write(uint64_t base, const struct reg_sequence *regs, - int num_regs) +int regmap_multi_reg_write(uint64_t base, const struct reg_sequence *regs, int num_regs) { int i; for (i = 0; i < num_regs; i++) { @@ -109,41 +108,32 @@ int regmap_multi_reg_write(uint64_t base, const struct reg_sequence *regs, static void meson_clk_pll_init(struct clk *clk) { struct meson_clk_pll_data *data = (struct meson_clk_pll_data *)(clk->data); - if ((data->flags & CLK_MESON_PLL_NOINIT_ENABLED) - && clk->hw.init->ops->is_enabled(clk)) + if ((data->flags & CLK_MESON_PLL_NOINIT_ENABLED) && clk->hw.init->ops->is_enabled(clk)) return; if (data->init_count) { /* Set the reset bit */ - regmap_update_bits(clk->base, data->rst.reg_off, data->rst.shift, - data->rst.width, 1); + regmap_update_bits(clk->base, data->rst.reg_off, data->rst.shift, data->rst.width, 1); regmap_multi_reg_write(clk->base, data->init_regs, data->init_count); /* Clear the reset bit */ - regmap_update_bits(clk->base, data->rst.reg_off, data->rst.shift, - data->rst.width, 0); + regmap_update_bits(clk->base, data->rst.reg_off, data->rst.shift, data->rst.width, 0); } } -static unsigned long meson_clk_pll_recalc_rate(const struct clk *clk, - unsigned long parent_rate) +static unsigned long meson_clk_pll_recalc_rate(const struct clk *clk, unsigned long parent_rate) { struct meson_clk_pll_data *data = (struct meson_clk_pll_data *)(clk->data); uint32_t n, m, frac; - n = regmap_read_bits(clk->base, data->n.reg_off, data->n.shift, - data->n.width); + n = regmap_read_bits(clk->base, data->n.reg_off, data->n.shift, data->n.width); if (n == 0) return 0; - m = regmap_read_bits(clk->base, data->m.reg_off, data->m.shift, - data->m.width); + m = regmap_read_bits(clk->base, data->m.reg_off, data->m.shift, data->m.width); - frac = data->frac.width - ? regmap_read_bits(clk->base, data->frac.reg_off, data->frac.shift, - data->frac.width) - : 0; + frac = data->frac.width ? regmap_read_bits(clk->base, data->frac.reg_off, data->frac.shift, data->frac.width) : 0; uint64_t rate = (uint64_t)parent_rate * m; @@ -163,8 +153,7 @@ static int meson_clk_pll_is_enabled(struct clk *clk) return 0; } - if (!meson_parm_read(clk->base, data->en) - || !meson_parm_read(clk->base, data->l)) { + if (!meson_parm_read(clk->base, data->en) || !meson_parm_read(clk->base, data->l)) { return 0; } @@ -178,15 +167,11 @@ static int meson_clk_pll_enable(struct clk *clk) if (meson_clk_pll_is_enabled(clk)) return 0; - regmap_update_bits(clk->base, data->rst.reg_off, data->rst.shift, - data->rst.width, 1); - regmap_update_bits(clk->base, data->en.reg_off, data->en.shift, - data->en.width, 1); - regmap_update_bits(clk->base, data->rst.reg_off, data->rst.shift, - data->rst.width, 1); + regmap_update_bits(clk->base, data->rst.reg_off, data->rst.shift, data->rst.width, 1); + regmap_update_bits(clk->base, data->en.reg_off, data->en.shift, data->en.width, 1); + regmap_update_bits(clk->base, data->rst.reg_off, data->rst.shift, data->rst.width, 1); - regmap_update_bits(clk->base, data->current_en.reg_off, - data->current_en.shift, data->current_en.width, 1); + regmap_update_bits(clk->base, data->current_en.reg_off, data->current_en.shift, data->current_en.width, 1); return 0; } @@ -194,22 +179,18 @@ static int meson_clk_pll_disable(struct clk *clk) { struct meson_clk_pll_data *data = (struct meson_clk_pll_data *)(clk->data); - regmap_update_bits(clk->base, data->rst.reg_off, data->rst.shift, - data->rst.width, 1); - regmap_update_bits(clk->base, data->en.reg_off, data->en.shift, - data->en.width, 0); + regmap_update_bits(clk->base, data->rst.reg_off, data->rst.shift, data->rst.width, 1); + regmap_update_bits(clk->base, data->en.reg_off, data->en.shift, data->en.width, 0); return 0; } -const struct clk_ops meson_clk_pll_ops = { - .init = meson_clk_pll_init, - .recalc_rate = meson_clk_pll_recalc_rate, +const struct clk_ops meson_clk_pll_ops = { .init = meson_clk_pll_init, + .recalc_rate = meson_clk_pll_recalc_rate, /* .determine_rate = meson_clk_pll_determine_rate, */ /* .set_rate = meson_clk_pll_set_rate, */ - .is_enabled = meson_clk_pll_is_enabled, - .enable = meson_clk_pll_enable, - .disable = meson_clk_pll_disable -}; + .is_enabled = meson_clk_pll_is_enabled, + .enable = meson_clk_pll_enable, + .disable = meson_clk_pll_disable }; const struct clk_ops meson_clk_pll_ro_ops = { .recalc_rate = meson_clk_pll_recalc_rate, @@ -220,17 +201,13 @@ const struct clk_ops meson_clk_pll_ro_ops = { #define N2_MIN 4 #define N2_MAX 511 -static unsigned long mpll_recalc_rate(const struct clk *clk, - unsigned long prate) +static uint64_t mpll_recalc_rate(const struct clk *clk, uint64_t prate) { - struct meson_clk_mpll_data *data = - (struct meson_clk_mpll_data *)(clk->data); + struct meson_clk_mpll_data *data = (struct meson_clk_mpll_data *)(clk->data); uint32_t sdm, n2; - sdm = regmap_read_bits(clk->base, data->sdm.reg_off, data->sdm.shift, - data->sdm.width); - n2 = regmap_read_bits(clk->base, data->n2.reg_off, data->n2.shift, - data->n2.width); + sdm = regmap_read_bits(clk->base, data->sdm.reg_off, data->sdm.shift, data->sdm.width); + n2 = regmap_read_bits(clk->base, data->n2.reg_off, data->n2.shift, data->n2.width); uint32_t divisor = (SDM_DEN * n2) + sdm; if (n2 < N2_MIN) @@ -239,11 +216,9 @@ static unsigned long mpll_recalc_rate(const struct clk *clk, return DIV_ROUND_UP_ULL((uint64_t)prate * SDM_DEN, divisor); } -static int mpll_set_rate(const struct clk *clk, uint32_t rate, - uint32_t parent_rate) +static int mpll_set_rate(const struct clk *clk, uint64_t rate, uint64_t parent_rate) { - struct meson_clk_mpll_data *data = - (struct meson_clk_mpll_data *)(clk->data); + struct meson_clk_mpll_data *data = (struct meson_clk_mpll_data *)(clk->data); uint64_t div = parent_rate; uint64_t frac = do_div(div, rate); uint32_t sdm, n2; @@ -270,30 +245,25 @@ static int mpll_set_rate(const struct clk *clk, uint32_t rate, n2 = div; } - regmap_update_bits(clk->base, data->sdm.reg_off, data->sdm.shift, - data->sdm.width, sdm); - regmap_update_bits(clk->base, data->n2.reg_off, data->n2.shift, - data->n2.width, n2); + regmap_update_bits(clk->base, data->sdm.reg_off, data->sdm.shift, data->sdm.width, sdm); + regmap_update_bits(clk->base, data->n2.reg_off, data->n2.shift, data->n2.width, n2); return 0; } static void mpll_init(struct clk *clk) { - struct meson_clk_mpll_data *data = - (struct meson_clk_mpll_data *)(clk->data); + struct meson_clk_mpll_data *data = (struct meson_clk_mpll_data *)(clk->data); if (data->init_count) { regmap_multi_reg_write(clk->base, data->init_regs, data->init_count); } /* Enable the fractional part */ - regmap_update_bits(clk->base, data->sdm_en.reg_off, data->sdm_en.shift, - data->sdm_en.width, 1); + regmap_update_bits(clk->base, data->sdm_en.reg_off, data->sdm_en.shift, data->sdm_en.width, 1); /* Set spread spectrum if possible */ - unsigned int ss = data->flags & CLK_MESON_MPLL_SPREAD_SPECTRUM ? 1 : 0; - regmap_update_bits(clk->base, data->ssen.reg_off, data->ssen.shift, - data->ssen.width, ss); + uint32_t ss = data->flags & CLK_MESON_MPLL_SPREAD_SPECTRUM ? 1 : 0; + regmap_update_bits(clk->base, data->ssen.reg_off, data->ssen.shift, data->ssen.width, ss); } const struct clk_ops meson_clk_mpll_ops = { @@ -322,14 +292,12 @@ static int meson_clk_pcie_pll_enable(struct clk *clk) return -1; } -const struct clk_ops meson_clk_pcie_pll_ops = { - .init = meson_clk_pll_init, - .recalc_rate = meson_clk_pll_recalc_rate, +const struct clk_ops meson_clk_pcie_pll_ops = { .init = meson_clk_pll_init, + .recalc_rate = meson_clk_pll_recalc_rate, /* .determine_rate = meson_clk_pll_determine_rate, */ - .is_enabled = meson_clk_pll_is_enabled, - .enable = meson_clk_pcie_pll_enable, - .disable = meson_clk_pll_disable -}; + .is_enabled = meson_clk_pll_is_enabled, + .enable = meson_clk_pcie_pll_enable, + .disable = meson_clk_pll_disable }; struct vid_pll_div { unsigned int shift_val; @@ -363,24 +331,19 @@ static const struct vid_pll_div vid_pll_div_table[] = { VID_PLL_DIV(0x7f80, 2, 15, 1), /* 15/1 => /15 */ }; -static unsigned long meson_vid_pll_div_recalc_rate(const struct clk *clk, - unsigned long prate) +static unsigned long meson_vid_pll_div_recalc_rate(const struct clk *clk, unsigned long prate) { - struct meson_vid_pll_div_data *data = - (struct meson_vid_pll_div_data *)(clk->data); + struct meson_vid_pll_div_data *data = (struct meson_vid_pll_div_data *)(clk->data); const struct vid_pll_div *div; uint32_t shift_val, shift_sel; - shift_val = regmap_read_bits(clk->base, data->val.reg_off, data->val.shift, - data->val.width); - shift_sel = regmap_read_bits(clk->base, data->sel.reg_off, data->sel.shift, - data->sel.width); + shift_val = regmap_read_bits(clk->base, data->val.reg_off, data->val.shift, data->val.width); + shift_sel = regmap_read_bits(clk->base, data->sel.reg_off, data->sel.shift, data->sel.width); int i; for (i = 0; i < ARRAY_SIZE(vid_pll_div_table); ++i) { - if (vid_pll_div_table[i].shift_val == shift_val - && vid_pll_div_table[i].shift_sel == shift_sel) { + if (vid_pll_div_table[i].shift_val == shift_val && vid_pll_div_table[i].shift_sel == shift_sel) { div = &vid_pll_div_table[i]; return DIV_ROUND_UP_ULL(prate * div->multiplier, div->divider); } @@ -396,37 +359,29 @@ const struct clk_ops meson_vid_pll_div_ro_ops = { static int meson_vclk_gate_enable(struct clk *clk) { - struct meson_vclk_gate_data *data = - (struct meson_vclk_gate_data *)(clk->data); + struct meson_vclk_gate_data *data = (struct meson_vclk_gate_data *)(clk->data); - regmap_update_bits(clk->base, data->enable.reg_off, data->enable.shift, - data->enable.width, 1); + regmap_update_bits(clk->base, data->enable.reg_off, data->enable.shift, data->enable.width, 1); /* Do a reset pulse */ - regmap_update_bits(clk->base, data->reset.reg_off, data->reset.shift, - data->reset.width, 1); - regmap_update_bits(clk->base, data->reset.reg_off, data->reset.shift, - data->reset.width, 0); + regmap_update_bits(clk->base, data->reset.reg_off, data->reset.shift, data->reset.width, 1); + regmap_update_bits(clk->base, data->reset.reg_off, data->reset.shift, data->reset.width, 0); return 0; } static int meson_vclk_gate_disable(struct clk *clk) { - struct meson_vclk_gate_data *data = - (struct meson_vclk_gate_data *)(clk->data); + struct meson_vclk_gate_data *data = (struct meson_vclk_gate_data *)(clk->data); - regmap_update_bits(clk->base, data->enable.reg_off, data->enable.shift, - data->enable.width, 0); + regmap_update_bits(clk->base, data->enable.reg_off, data->enable.shift, data->enable.width, 0); return 0; } static int meson_vclk_gate_is_enabled(struct clk *clk) { - struct meson_vclk_gate_data *data = - (struct meson_vclk_gate_data *)(clk->data); - return regmap_read_bits(clk->base, data->enable.reg_off, data->enable.shift, - data->enable.width); + struct meson_vclk_gate_data *data = (struct meson_vclk_gate_data *)(clk->data); + return regmap_read_bits(clk->base, data->enable.reg_off, data->enable.shift, data->enable.width); } const struct clk_ops meson_vclk_gate_ops = { @@ -435,13 +390,10 @@ const struct clk_ops meson_vclk_gate_ops = { .is_enabled = meson_vclk_gate_is_enabled, }; -static unsigned long meson_vclk_div_recalc_rate(const struct clk *clk, - unsigned long prate) +static unsigned long meson_vclk_div_recalc_rate(const struct clk *clk, unsigned long prate) { - struct meson_vclk_div_data *data = - (struct meson_vclk_div_data *)(clk->data); - uint32_t div = regmap_read_bits(clk->base, data->div.reg_off, - data->div.shift, data->div.width); + struct meson_vclk_div_data *data = (struct meson_vclk_div_data *)(clk->data); + uint32_t div = regmap_read_bits(clk->base, data->div.reg_off, data->div.shift, data->div.width); /* TODO: Need to verify the following cases */ if (data->flags & CLK_DIVIDER_ONE_BASED) { @@ -457,11 +409,9 @@ static unsigned long meson_vclk_div_recalc_rate(const struct clk *clk, return DIV_ROUND_UP_ULL((uint64_t)prate, div); } -static int meson_vclk_div_set_rate(const struct clk *clk, uint32_t rate, - uint32_t parent_rate) +static int meson_vclk_div_set_rate(const struct clk *clk, uint64_t rate, uint64_t parent_rate) { - struct meson_vclk_div_data *data = - (struct meson_vclk_div_data *)(clk->data); + struct meson_vclk_div_data *data = (struct meson_vclk_div_data *)(clk->data); uint32_t div = DIV_ROUND_UP(parent_rate, rate); @@ -475,41 +425,32 @@ static int meson_vclk_div_set_rate(const struct clk *clk, uint32_t rate, } else { div -= 1; } - return regmap_update_bits(clk->base, data->div.reg_off, data->div.shift, - data->div.width, div); + return regmap_update_bits(clk->base, data->div.reg_off, data->div.shift, data->div.width, div); } static int meson_vclk_div_enable(struct clk *clk) { - struct meson_vclk_div_data *data = - (struct meson_vclk_div_data *)(clk->data); + struct meson_vclk_div_data *data = (struct meson_vclk_div_data *)(clk->data); - regmap_update_bits(clk->base, data->reset.reg_off, data->reset.shift, - data->reset.width, 0); - regmap_update_bits(clk->base, data->enable.reg_off, data->enable.shift, - data->enable.width, 1); + regmap_update_bits(clk->base, data->reset.reg_off, data->reset.shift, data->reset.width, 0); + regmap_update_bits(clk->base, data->enable.reg_off, data->enable.shift, data->enable.width, 1); return 0; } static int meson_vclk_div_disable(struct clk *clk) { - struct meson_vclk_div_data *data = - (struct meson_vclk_div_data *)(clk->data); + struct meson_vclk_div_data *data = (struct meson_vclk_div_data *)(clk->data); - regmap_update_bits(clk->base, data->enable.reg_off, data->enable.shift, - data->enable.width, 0); - regmap_update_bits(clk->base, data->reset.reg_off, data->reset.shift, - data->reset.width, 1); + regmap_update_bits(clk->base, data->enable.reg_off, data->enable.shift, data->enable.width, 0); + regmap_update_bits(clk->base, data->reset.reg_off, data->reset.shift, data->reset.width, 1); return 0; } static int meson_vclk_div_is_enabled(struct clk *clk) { - struct meson_vclk_div_data *data = - (struct meson_vclk_div_data *)(clk->data); - return regmap_read_bits(clk->base, data->enable.reg_off, data->enable.shift, - data->enable.width); + struct meson_vclk_div_data *data = (struct meson_vclk_div_data *)(clk->data); + return regmap_read_bits(clk->base, data->enable.reg_off, data->enable.shift, data->enable.width); } const struct clk_ops meson_vclk_div_ops = { @@ -521,11 +462,9 @@ const struct clk_ops meson_vclk_div_ops = { .is_enabled = meson_vclk_div_is_enabled, }; -static unsigned long meson_clk_cpu_dyndiv_recalc_rate(const struct clk *clk, - unsigned long prate) +static unsigned long meson_clk_cpu_dyndiv_recalc_rate(const struct clk *clk, unsigned long prate) { - struct meson_clk_cpu_dyndiv_data *data = - (struct meson_clk_cpu_dyndiv_data *)(clk->data); + struct meson_clk_cpu_dyndiv_data *data = (struct meson_clk_cpu_dyndiv_data *)(clk->data); uint32_t div = meson_parm_read(clk->base, data->div); div += 1; diff --git a/drivers/clk/meson/clk.c b/drivers/clk/meson/clk.c index 3f303882c..23ed849de 100644 --- a/drivers/clk/meson/clk.c +++ b/drivers/clk/meson/clk.c @@ -90,14 +90,14 @@ const struct clk *get_parent(const struct clk *clk) /* TODO: Should be just read from the structure, but need to update everytime when */ /* related clocks are modified */ -uint32_t clk_get_rate(const struct clk *clk, unsigned long *rate) +int clk_get_rate(const struct clk *clk, uint64_t *rate) { if (!clk) return CLK_UNKNOWN_TARGET; const struct clk_init_data *init = (struct clk_init_data *)clk->hw.init; - unsigned long parent_rate = 0; - uint32_t err = 0; + uint64_t parent_rate = 0; + int err = 0; const struct clk *parent_clk = get_parent(clk); if (parent_clk) { @@ -115,7 +115,7 @@ uint32_t clk_get_rate(const struct clk *clk, unsigned long *rate) return 0; } -uint32_t clk_enable(struct clk *clk) +int clk_enable(struct clk *clk) { if (!clk) return CLK_UNKNOWN_TARGET; @@ -127,7 +127,7 @@ uint32_t clk_enable(struct clk *clk) return CLK_INVALID_OP; } -uint32_t clk_disable(struct clk *clk) +int clk_disable(struct clk *clk) { if (!clk) return CLK_UNKNOWN_TARGET; @@ -139,7 +139,7 @@ uint32_t clk_disable(struct clk *clk) return CLK_INVALID_OP; } -uint32_t clk_set_rate(struct clk *clk, uint64_t req_rate, uint64_t *rate) +int clk_set_rate(struct clk *clk, uint64_t req_rate, uint64_t *rate) { if (!clk) return CLK_UNKNOWN_TARGET; @@ -152,7 +152,7 @@ uint32_t clk_set_rate(struct clk *clk, uint64_t req_rate, uint64_t *rate) const struct clk *pclk = get_parent(clk); uint64_t prate = 0; - uint32_t err = clk_get_rate(pclk, &prate); + int err = clk_get_rate(pclk, &prate); if (err) { LOG_DRIVER_ERR("Failed to get parent clock's rate\n"); return err; @@ -166,7 +166,7 @@ uint32_t clk_set_rate(struct clk *clk, uint64_t req_rate, uint64_t *rate) if (pclk->hw.init->ops->set_rate) { const struct clk *ppclk = get_parent(pclk); uint64_t pprate = 0; - uint32_t err = clk_get_rate(ppclk, &pprate); + int err = clk_get_rate(ppclk, &pprate); if (!err) { pclk->hw.init->ops->set_rate(pclk, prate, pprate); *rate = req_rate; @@ -184,7 +184,7 @@ int clk_msr_stat() unsigned long clk_freq; int i = 0; uint64_t rate = 0; - uint32_t err; + int err; const char *const *clk_msr_list = get_msr_clk_list(); @@ -192,8 +192,7 @@ int clk_msr_stat() for (i = 0; i < NUM_CLK_LIST; i++) { err = clk_get_rate(clk_list[i], &rate); if (err) { - LOG_DRIVER("Failed to get rate of %s: -%u\n", - clk_list[i]->hw.init->name, err); + LOG_DRIVER("Failed to get rate of %s: -%u\n", clk_list[i]->hw.init->name, err); } LOG_DRIVER("[%4d][%4luHz] %s\n", i, rate, clk_list[i]->hw.init->name); } @@ -234,10 +233,10 @@ void init(void) /* Set rate for the target clock */ if (clk_configs[i].frequency > 0) { uint64_t rate = 0; - uint32_t err = clk_set_rate(clk, clk_configs[i].frequency, &rate); + int err = clk_set_rate(clk, clk_configs[i].frequency, &rate); if (err) { - LOG_DRIVER_ERR("Failed to set rate [%d] for clk_id: %d\n", - clk_configs[i].frequency, clk_configs[i].clk_id); + LOG_DRIVER_ERR("Failed to set rate [%d] for clk_id: %d\n", clk_configs[i].frequency, + clk_configs[i].clk_id); } } } @@ -245,7 +244,7 @@ void init(void) microkit_msginfo protected(microkit_channel ch, microkit_msginfo msginfo) { - uint32_t err = 0; + int err = 0; uint32_t ret_num = 0; uint32_t argc = microkit_msginfo_get_count(msginfo); @@ -302,8 +301,8 @@ microkit_msginfo protected(microkit_channel ch, microkit_msginfo msginfo) break; } default: - LOG_DRIVER_ERR("Unknown request %lu to clockk driver from channel %u\n", - microkit_msginfo_get_label(msginfo), ch); + LOG_DRIVER_ERR("Unknown request %lu to clockk driver from channel %u\n", microkit_msginfo_get_label(msginfo), + ch); err = CLK_UNKNOWN_REQ; } return microkit_msginfo_new(err, ret_num); diff --git a/drivers/clk/meson/sm1-clk.c b/drivers/clk/meson/sm1-clk.c index 07924ecea..97069e87b 100644 --- a/drivers/clk/meson/sm1-clk.c +++ b/drivers/clk/meson/sm1-clk.c @@ -71,8 +71,7 @@ static struct clk g12a_fixed_pll_dco = { .num_parents = 1, }, }; -static CLK_DIV_RO(g12a_fixed_pll, HHI_FIX_PLL_CNTL0, 16, 2, - CLK_DIVIDER_POWER_OF_TWO, { &g12a_fixed_pll_dco }, 1, 0); +static CLK_DIV_RO(g12a_fixed_pll, HHI_FIX_PLL_CNTL0, 16, 2, CLK_DIVIDER_POWER_OF_TWO, { &g12a_fixed_pll_dco }, 1, 0); static struct clk g12a_sys_pll_dco = { .data = &(struct meson_clk_pll_data){ .en = { @@ -114,18 +113,13 @@ static struct clk g12a_sys_pll_dco = { .flags = CLK_IS_CRITICAL, }, }; -static CLK_DIV(g12a_sys_pll, HHI_SYS_PLL_CNTL0, 16, 3, CLK_DIVIDER_POWER_OF_TWO, - { &g12a_sys_pll_dco }, 1, 0); -static CLK_GATE_RO(g12a_sys_pll_div16_en, HHI_SYS_CPU_CLK_CNTL1, 24, 0, - { &g12a_sys_pll }, 1, 0); -static CLK_FIXED_FACTOR(g12a_sys_pll_div16, 1, 16, 0, - { &g12a_sys_pll_div16_en }, 1, 0); +static CLK_DIV(g12a_sys_pll, HHI_SYS_PLL_CNTL0, 16, 3, CLK_DIVIDER_POWER_OF_TWO, { &g12a_sys_pll_dco }, 1, 0); +static CLK_GATE_RO(g12a_sys_pll_div16_en, HHI_SYS_CPU_CLK_CNTL1, 24, 0, { &g12a_sys_pll }, 1, 0); +static CLK_FIXED_FACTOR(g12a_sys_pll_div16, 1, 16, 0, { &g12a_sys_pll_div16_en }, 1, 0); static CLK_FIXED_FACTOR(g12a_fclk_div2_div, 1, 2, 0, { &g12a_fixed_pll }, 1, 0); -static CLK_GATE(g12a_fclk_div2, HHI_FIX_PLL_CNTL1, 24, 0, - { &g12a_fclk_div2_div }, 1, 0); +static CLK_GATE(g12a_fclk_div2, HHI_FIX_PLL_CNTL1, 24, 0, { &g12a_fclk_div2_div }, 1, 0); static CLK_FIXED_FACTOR(g12a_fclk_div3_div, 1, 3, 0, { &g12a_fixed_pll }, 1, 0); -static CLK_GATE(g12a_fclk_div3, HHI_FIX_PLL_CNTL1, 20, 0, - { &g12a_fclk_div3_div }, 1, 0); +static CLK_GATE(g12a_fclk_div3, HHI_FIX_PLL_CNTL1, 20, 0, { &g12a_fclk_div3_div }, 1, 0); const struct clk_parent_data g12a_cpu_clk_premux0_parent_table[] = { { .name = "xtal", @@ -133,8 +127,8 @@ const struct clk_parent_data g12a_cpu_clk_premux0_parent_table[] = { { .clk = &g12a_fclk_div2 }, { .clk = &g12a_fclk_div3 }, }; -static CLK_MUX(g12a_cpu_clk_premux0, HHI_SYS_CPU_CLK_CNTL0, 0x3, 0, 0, - CLK_MUX_ROUND_CLOSEST, g12a_cpu_clk_premux0_parent_table, 3, 0); +static CLK_MUX(g12a_cpu_clk_premux0, HHI_SYS_CPU_CLK_CNTL0, 0x3, 0, 0, CLK_MUX_ROUND_CLOSEST, + g12a_cpu_clk_premux0_parent_table, 3, 0); const struct clk_parent_data g12a_cpu_clk_premux1_parent_table[] = { { .name = "xtal", @@ -142,8 +136,7 @@ const struct clk_parent_data g12a_cpu_clk_premux1_parent_table[] = { { .clk = &g12a_fclk_div2 }, { .clk = &g12a_fclk_div3 }, }; -static CLK_MUX(g12a_cpu_clk_premux1, HHI_SYS_CPU_CLK_CNTL0, 0x3, 16, 0, 0, - g12a_cpu_clk_premux1_parent_table, 3, 0); +static CLK_MUX(g12a_cpu_clk_premux1, HHI_SYS_CPU_CLK_CNTL0, 0x3, 16, 0, 0, g12a_cpu_clk_premux1_parent_table, 3, 0); static struct clk g12a_cpu_clk_mux0_div = { .data = &(struct meson_clk_cpu_dyndiv_data){ .div = { @@ -171,36 +164,30 @@ const struct clk_parent_data g12a_cpu_clk_postmux0_parent_table[] = { { .clk = &g12a_cpu_clk_premux0 }, { .clk = &g12a_cpu_clk_mux0_div }, }; -static CLK_MUX(g12a_cpu_clk_postmux0, HHI_SYS_CPU_CLK_CNTL0, 0x1, 2, 0, - CLK_MUX_ROUND_CLOSEST, g12a_cpu_clk_postmux0_parent_table, 2, 0); -static CLK_DIV_RO(g12a_cpu_clk_mux1_div, HHI_SYS_CPU_CLK_CNTL0, 20, 6, 0, - { &g12a_cpu_clk_premux1 }, 1, 0); +static CLK_MUX(g12a_cpu_clk_postmux0, HHI_SYS_CPU_CLK_CNTL0, 0x1, 2, 0, CLK_MUX_ROUND_CLOSEST, + g12a_cpu_clk_postmux0_parent_table, 2, 0); +static CLK_DIV_RO(g12a_cpu_clk_mux1_div, HHI_SYS_CPU_CLK_CNTL0, 20, 6, 0, { &g12a_cpu_clk_premux1 }, 1, 0); const struct clk_parent_data g12a_cpu_clk_postmux1_parent_table[] = { { .clk = &g12a_cpu_clk_premux1 }, { .clk = &g12a_cpu_clk_mux1_div }, }; -static CLK_MUX(g12a_cpu_clk_postmux1, HHI_SYS_CPU_CLK_CNTL0, 0x1, 18, 0, 0, - g12a_cpu_clk_postmux1_parent_table, 2, 0); +static CLK_MUX(g12a_cpu_clk_postmux1, HHI_SYS_CPU_CLK_CNTL0, 0x1, 18, 0, 0, g12a_cpu_clk_postmux1_parent_table, 2, 0); const struct clk_parent_data g12a_cpu_clk_dyn_parent_table[] = { { .clk = &g12a_cpu_clk_postmux0 }, { .clk = &g12a_cpu_clk_postmux1 }, }; -static CLK_MUX(g12a_cpu_clk_dyn, HHI_SYS_CPU_CLK_CNTL0, 0x1, 10, 0, - CLK_MUX_ROUND_CLOSEST, g12a_cpu_clk_dyn_parent_table, 2, 0); +static CLK_MUX(g12a_cpu_clk_dyn, HHI_SYS_CPU_CLK_CNTL0, 0x1, 10, 0, CLK_MUX_ROUND_CLOSEST, + g12a_cpu_clk_dyn_parent_table, 2, 0); const struct clk_parent_data g12a_cpu_clk_parent_table[] = { { .clk = &g12a_cpu_clk_dyn }, { .clk = &g12a_sys_pll }, }; -static CLK_MUX(g12a_cpu_clk, HHI_SYS_CPU_CLK_CNTL0, 0x1, 11, 0, - CLK_MUX_ROUND_CLOSEST, g12a_cpu_clk_parent_table, 2, 0); +static CLK_MUX(g12a_cpu_clk, HHI_SYS_CPU_CLK_CNTL0, 0x1, 11, 0, CLK_MUX_ROUND_CLOSEST, g12a_cpu_clk_parent_table, 2, 0); static const struct reg_sequence g12a_gp0_init_regs[] = { - { .reg = HHI_GP0_PLL_CNTL1, .def = 0x00000000 }, - { .reg = HHI_GP0_PLL_CNTL2, .def = 0x00000000 }, - { .reg = HHI_GP0_PLL_CNTL3, .def = 0x48681c00 }, - { .reg = HHI_GP0_PLL_CNTL4, .def = 0x33771290 }, - { .reg = HHI_GP0_PLL_CNTL5, .def = 0x39272000 }, - { .reg = HHI_GP0_PLL_CNTL6, .def = 0x56540000 }, + { .reg = HHI_GP0_PLL_CNTL1, .def = 0x00000000 }, { .reg = HHI_GP0_PLL_CNTL2, .def = 0x00000000 }, + { .reg = HHI_GP0_PLL_CNTL3, .def = 0x48681c00 }, { .reg = HHI_GP0_PLL_CNTL4, .def = 0x33771290 }, + { .reg = HHI_GP0_PLL_CNTL5, .def = 0x39272000 }, { .reg = HHI_GP0_PLL_CNTL6, .def = 0x56540000 }, }; static struct clk g12a_gp0_pll_dco = { .data = &(struct meson_clk_pll_data){ @@ -248,8 +235,7 @@ static struct clk g12a_gp0_pll_dco = { .num_parents = 1, }, }; -static CLK_DIV(g12a_gp0_pll, HHI_GP0_PLL_CNTL0, 16, 3, - (CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_ROUND_CLOSEST), +static CLK_DIV(g12a_gp0_pll, HHI_GP0_PLL_CNTL0, 16, 3, (CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_ROUND_CLOSEST), { &g12a_gp0_pll_dco }, 1, 0); static struct clk sm1_gp1_pll_dco = { .data = &(struct meson_clk_pll_data){ @@ -295,8 +281,7 @@ static struct clk sm1_gp1_pll_dco = { .flags = CLK_IS_CRITICAL, }, }; -static CLK_DIV_RO(sm1_gp1_pll, HHI_GP1_PLL_CNTL0, 16, 3, - (CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_ROUND_CLOSEST), +static CLK_DIV_RO(sm1_gp1_pll, HHI_GP1_PLL_CNTL0, 16, 3, (CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_ROUND_CLOSEST), { &sm1_gp1_pll_dco }, 1, 0); const struct clk_parent_data sm1_dsu_clk_premux0_parent_table[] = { @@ -307,8 +292,7 @@ const struct clk_parent_data sm1_dsu_clk_premux0_parent_table[] = { { .clk = &g12a_fclk_div3 }, { .clk = &sm1_gp1_pll }, }; -static CLK_MUX_RO(sm1_dsu_clk_premux0, HHI_SYS_CPU_CLK_CNTL5, 0x3, 0, 0, 0, - sm1_dsu_clk_premux0_parent_table, 4, 0); +static CLK_MUX_RO(sm1_dsu_clk_premux0, HHI_SYS_CPU_CLK_CNTL5, 0x3, 0, 0, 0, sm1_dsu_clk_premux0_parent_table, 4, 0); const struct clk_parent_data sm1_dsu_clk_premux1_parent_table[] = { { .name = "xtal", @@ -317,20 +301,16 @@ const struct clk_parent_data sm1_dsu_clk_premux1_parent_table[] = { { .clk = &g12a_fclk_div3 }, { .clk = &sm1_gp1_pll }, }; -static CLK_MUX_RO(sm1_dsu_clk_premux1, HHI_SYS_CPU_CLK_CNTL5, 0x3, 16, 0, 0, - sm1_dsu_clk_premux1_parent_table, 4, 0); -static CLK_DIV_RO(sm1_dsu_clk_mux0_div, HHI_SYS_CPU_CLK_CNTL5, 4, 6, 0, - { &sm1_dsu_clk_premux0 }, 1, 0); +static CLK_MUX_RO(sm1_dsu_clk_premux1, HHI_SYS_CPU_CLK_CNTL5, 0x3, 16, 0, 0, sm1_dsu_clk_premux1_parent_table, 4, 0); +static CLK_DIV_RO(sm1_dsu_clk_mux0_div, HHI_SYS_CPU_CLK_CNTL5, 4, 6, 0, { &sm1_dsu_clk_premux0 }, 1, 0); const struct clk_parent_data sm1_dsu_clk_postmux0_parent_table[] = { { .clk = &sm1_dsu_clk_premux0, }, { .clk = &sm1_dsu_clk_mux0_div }, }; -static CLK_MUX_RO(sm1_dsu_clk_postmux0, HHI_SYS_CPU_CLK_CNTL5, 0x1, 2, 0, 0, - sm1_dsu_clk_postmux0_parent_table, 2, 0); -static CLK_DIV_RO(sm1_dsu_clk_mux1_div, HHI_SYS_CPU_CLK_CNTL5, 20, 6, 0, - { &sm1_dsu_clk_premux1 }, 1, 0); +static CLK_MUX_RO(sm1_dsu_clk_postmux0, HHI_SYS_CPU_CLK_CNTL5, 0x1, 2, 0, 0, sm1_dsu_clk_postmux0_parent_table, 2, 0); +static CLK_DIV_RO(sm1_dsu_clk_mux1_div, HHI_SYS_CPU_CLK_CNTL5, 20, 6, 0, { &sm1_dsu_clk_premux1 }, 1, 0); const struct clk_parent_data sm1_dsu_clk_postmux1_parent_table[] = { { @@ -338,8 +318,7 @@ const struct clk_parent_data sm1_dsu_clk_postmux1_parent_table[] = { }, { .clk = &sm1_dsu_clk_mux1_div }, }; -static CLK_MUX_RO(sm1_dsu_clk_postmux1, HHI_SYS_CPU_CLK_CNTL5, 0x1, 18, 0, 0, - sm1_dsu_clk_postmux1_parent_table, 2, 0); +static CLK_MUX_RO(sm1_dsu_clk_postmux1, HHI_SYS_CPU_CLK_CNTL5, 0x1, 18, 0, 0, sm1_dsu_clk_postmux1_parent_table, 2, 0); const struct clk_parent_data sm1_dsu_clk_dyn_parent_table[] = { { .clk = &sm1_dsu_clk_premux0, @@ -348,8 +327,7 @@ const struct clk_parent_data sm1_dsu_clk_dyn_parent_table[] = { .clk = &sm1_dsu_clk_postmux1, }, }; -static CLK_MUX_RO(sm1_dsu_clk_dyn, HHI_SYS_CPU_CLK_CNTL5, 0x1, 10, 0, 0, - sm1_dsu_clk_dyn_parent_table, 2, 0); +static CLK_MUX_RO(sm1_dsu_clk_dyn, HHI_SYS_CPU_CLK_CNTL5, 0x1, 10, 0, 0, sm1_dsu_clk_dyn_parent_table, 2, 0); const struct clk_parent_data sm1_dsu_final_clk_parent_table[] = { { .clk = &sm1_dsu_clk_dyn, @@ -358,19 +336,15 @@ const struct clk_parent_data sm1_dsu_final_clk_parent_table[] = { .clk = &g12a_sys_pll, }, }; -static CLK_MUX_RO(sm1_dsu_final_clk, HHI_SYS_CPU_CLK_CNTL5, 0x1, 11, 0, 0, - sm1_dsu_final_clk_parent_table, 2, 0); +static CLK_MUX_RO(sm1_dsu_final_clk, HHI_SYS_CPU_CLK_CNTL5, 0x1, 11, 0, 0, sm1_dsu_final_clk_parent_table, 2, 0); const struct clk_parent_data sm1_cpu_clk_parent_table[] = { { .clk = &g12a_cpu_clk, }, }; -static CLK_MUX_RO(sm1_cpu1_clk, HHI_SYS_CPU_CLK_CNTL6, 0x1, 24, 0, 0, - sm1_cpu_clk_parent_table, 1, 0); -static CLK_MUX_RO(sm1_cpu2_clk, HHI_SYS_CPU_CLK_CNTL6, 0x1, 25, 0, 0, - sm1_cpu_clk_parent_table, 1, 0); -static CLK_MUX_RO(sm1_cpu3_clk, HHI_SYS_CPU_CLK_CNTL6, 0x1, 26, 0, 0, - sm1_cpu_clk_parent_table, 1, 0); +static CLK_MUX_RO(sm1_cpu1_clk, HHI_SYS_CPU_CLK_CNTL6, 0x1, 24, 0, 0, sm1_cpu_clk_parent_table, 1, 0); +static CLK_MUX_RO(sm1_cpu2_clk, HHI_SYS_CPU_CLK_CNTL6, 0x1, 25, 0, 0, sm1_cpu_clk_parent_table, 1, 0); +static CLK_MUX_RO(sm1_cpu3_clk, HHI_SYS_CPU_CLK_CNTL6, 0x1, 26, 0, 0, sm1_cpu_clk_parent_table, 1, 0); const struct clk_parent_data sm1_dsu_clk_parent_table[] = { { .clk = &g12a_cpu_clk, @@ -379,37 +353,23 @@ const struct clk_parent_data sm1_dsu_clk_parent_table[] = { .clk = &sm1_dsu_final_clk, }, }; -static CLK_MUX_RO(sm1_dsu_clk, HHI_SYS_CPU_CLK_CNTL6, 0x1, 27, 0, 0, - sm1_dsu_clk_parent_table, 2, 0); -static CLK_GATE_RO(g12a_cpu_clk_div16_en, HHI_SYS_CPU_CLK_CNTL1, 1, 0, - { &g12a_cpu_clk }, 1, 0); -static CLK_FIXED_FACTOR(g12a_cpu_clk_div16, 1, 16, 0, - { &g12a_cpu_clk_div16_en }, 1, 0); -static CLK_DIV_RO(g12a_cpu_clk_apb_div, HHI_SYS_CPU_CLK_CNTL1, 3, 3, - CLK_DIVIDER_POWER_OF_TWO, { &g12a_cpu_clk }, 1, 0); -static CLK_GATE_RO(g12a_cpu_clk_apb, HHI_SYS_CPU_CLK_CNTL1, 1, 0, - { &g12a_cpu_clk_apb_div }, 1, 0); -static CLK_DIV_RO(g12a_cpu_clk_atb_div, HHI_SYS_CPU_CLK_CNTL1, 6, 3, - CLK_DIVIDER_POWER_OF_TWO, { &g12a_cpu_clk }, 1, 0); -static CLK_GATE_RO(g12a_cpu_clk_atb, HHI_SYS_CPU_CLK_CNTL1, 17, 0, - { &g12a_cpu_clk_atb_div }, 1, 0); -static CLK_DIV_RO(g12a_cpu_clk_axi_div, HHI_SYS_CPU_CLK_CNTL1, 9, 3, - CLK_DIVIDER_POWER_OF_TWO, { &g12a_cpu_clk }, 1, 0); -static CLK_GATE_RO(g12a_cpu_clk_axi, HHI_SYS_CPU_CLK_CNTL1, 18, 0, - { &g12a_cpu_clk_axi_div }, 1, 0); +static CLK_MUX_RO(sm1_dsu_clk, HHI_SYS_CPU_CLK_CNTL6, 0x1, 27, 0, 0, sm1_dsu_clk_parent_table, 2, 0); +static CLK_GATE_RO(g12a_cpu_clk_div16_en, HHI_SYS_CPU_CLK_CNTL1, 1, 0, { &g12a_cpu_clk }, 1, 0); +static CLK_FIXED_FACTOR(g12a_cpu_clk_div16, 1, 16, 0, { &g12a_cpu_clk_div16_en }, 1, 0); +static CLK_DIV_RO(g12a_cpu_clk_apb_div, HHI_SYS_CPU_CLK_CNTL1, 3, 3, CLK_DIVIDER_POWER_OF_TWO, { &g12a_cpu_clk }, 1, 0); +static CLK_GATE_RO(g12a_cpu_clk_apb, HHI_SYS_CPU_CLK_CNTL1, 1, 0, { &g12a_cpu_clk_apb_div }, 1, 0); +static CLK_DIV_RO(g12a_cpu_clk_atb_div, HHI_SYS_CPU_CLK_CNTL1, 6, 3, CLK_DIVIDER_POWER_OF_TWO, { &g12a_cpu_clk }, 1, 0); +static CLK_GATE_RO(g12a_cpu_clk_atb, HHI_SYS_CPU_CLK_CNTL1, 17, 0, { &g12a_cpu_clk_atb_div }, 1, 0); +static CLK_DIV_RO(g12a_cpu_clk_axi_div, HHI_SYS_CPU_CLK_CNTL1, 9, 3, CLK_DIVIDER_POWER_OF_TWO, { &g12a_cpu_clk }, 1, 0); +static CLK_GATE_RO(g12a_cpu_clk_axi, HHI_SYS_CPU_CLK_CNTL1, 18, 0, { &g12a_cpu_clk_axi_div }, 1, 0); /* TODO: special case, ignore its parent clk at the moment */ -static CLK_DIV_RO(g12a_cpu_clk_trace_div, HHI_SYS_CPU_CLK_CNTL1, 20, 3, - CLK_DIVIDER_POWER_OF_TWO, {}, 0, 0); -static CLK_GATE_RO(g12a_cpu_clk_trace, HHI_SYS_CPU_CLK_CNTL1, 23, 0, - { &g12a_cpu_clk_trace_div }, 1, 0); +static CLK_DIV_RO(g12a_cpu_clk_trace_div, HHI_SYS_CPU_CLK_CNTL1, 20, 3, CLK_DIVIDER_POWER_OF_TWO, {}, 0, 0); +static CLK_GATE_RO(g12a_cpu_clk_trace, HHI_SYS_CPU_CLK_CNTL1, 23, 0, { &g12a_cpu_clk_trace_div }, 1, 0); static const struct reg_sequence g12a_hifi_init_regs[] = { - { .reg = HHI_HIFI_PLL_CNTL1, .def = 0x00000000 }, - { .reg = HHI_HIFI_PLL_CNTL2, .def = 0x00000000 }, - { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x6a285c00 }, - { .reg = HHI_HIFI_PLL_CNTL4, .def = 0x65771290 }, - { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x39272000 }, - { .reg = HHI_HIFI_PLL_CNTL6, .def = 0x56540000 }, + { .reg = HHI_HIFI_PLL_CNTL1, .def = 0x00000000 }, { .reg = HHI_HIFI_PLL_CNTL2, .def = 0x00000000 }, + { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x6a285c00 }, { .reg = HHI_HIFI_PLL_CNTL4, .def = 0x65771290 }, + { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x39272000 }, { .reg = HHI_HIFI_PLL_CNTL6, .def = 0x56540000 }, }; static struct clk g12a_hifi_pll_dco = { @@ -459,8 +419,7 @@ static struct clk g12a_hifi_pll_dco = { .num_parents = 1, }, }; -static CLK_DIV(g12a_hifi_pll, HHI_HIFI_PLL_CNTL0, 16, 2, - (CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_ROUND_CLOSEST), +static CLK_DIV(g12a_hifi_pll, HHI_HIFI_PLL_CNTL0, 16, 2, (CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_ROUND_CLOSEST), { &g12a_hifi_pll_dco }, 1, 0); /* @@ -532,12 +491,10 @@ static struct clk g12a_pcie_pll_dco = { .num_parents = 1, }, }; -static CLK_FIXED_FACTOR(g12a_pcie_pll_dco_div2, 1, 2, 0, { &g12a_pcie_pll_dco }, - 1, 0); +static CLK_FIXED_FACTOR(g12a_pcie_pll_dco_div2, 1, 2, 0, { &g12a_pcie_pll_dco }, 1, 0); static CLK_DIV(g12a_pcie_pll_od, HHI_PCIE_PLL_CNTL0, 16, 5, - CLK_DIVIDER_ROUND_CLOSEST | CLK_DIVIDER_ONE_BASED - | CLK_DIVIDER_ALLOW_ZERO, - { &g12a_pcie_pll_dco_div2 }, 1, 0); + CLK_DIVIDER_ROUND_CLOSEST | CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, { &g12a_pcie_pll_dco_div2 }, + 1, 0); static CLK_FIXED_FACTOR(g12a_pcie_pll, 1, 2, 0, { &g12a_pcie_pll_od }, 1, 0); static struct clk g12a_hdmi_pll_dco = { .data = &(struct meson_clk_pll_data){ @@ -586,37 +543,26 @@ static struct clk g12a_hdmi_pll_dco = { .flags = CLK_GET_RATE_NOCACHE, }, }; -static CLK_DIV_RO(g12a_hdmi_pll_od, HHI_HDMI_PLL_CNTL0, 16, 2, - CLK_DIVIDER_POWER_OF_TWO, { &g12a_hdmi_pll_dco }, 1, 0); -static CLK_DIV_RO(g12a_hdmi_pll_od2, HHI_HDMI_PLL_CNTL0, 18, 2, - CLK_DIVIDER_POWER_OF_TWO, { &g12a_hdmi_pll_od }, 1, 0); -static CLK_DIV_RO(g12a_hdmi_pll, HHI_HDMI_PLL_CNTL0, 20, 2, - CLK_DIVIDER_POWER_OF_TWO, { &g12a_hdmi_pll_od2 }, 1, 0); +static CLK_DIV_RO(g12a_hdmi_pll_od, HHI_HDMI_PLL_CNTL0, 16, 2, CLK_DIVIDER_POWER_OF_TWO, { &g12a_hdmi_pll_dco }, 1, 0); +static CLK_DIV_RO(g12a_hdmi_pll_od2, HHI_HDMI_PLL_CNTL0, 18, 2, CLK_DIVIDER_POWER_OF_TWO, { &g12a_hdmi_pll_od }, 1, 0); +static CLK_DIV_RO(g12a_hdmi_pll, HHI_HDMI_PLL_CNTL0, 20, 2, CLK_DIVIDER_POWER_OF_TWO, { &g12a_hdmi_pll_od2 }, 1, 0); static CLK_FIXED_FACTOR(g12a_fclk_div4_div, 1, 4, 0, { &g12a_fixed_pll }, 1, 0); -static CLK_GATE(g12a_fclk_div4, HHI_FIX_PLL_CNTL1, 21, 0, - { &g12a_fclk_div4_div }, 1, 0); +static CLK_GATE(g12a_fclk_div4, HHI_FIX_PLL_CNTL1, 21, 0, { &g12a_fclk_div4_div }, 1, 0); static CLK_FIXED_FACTOR(g12a_fclk_div5_div, 1, 5, 0, { &g12a_fixed_pll }, 1, 0); -static CLK_GATE(g12a_fclk_div5, HHI_FIX_PLL_CNTL1, 22, 0, - { &g12a_fclk_div5_div }, 1, 0); +static CLK_GATE(g12a_fclk_div5, HHI_FIX_PLL_CNTL1, 22, 0, { &g12a_fclk_div5_div }, 1, 0); static CLK_FIXED_FACTOR(g12a_fclk_div7_div, 1, 7, 0, { &g12a_fixed_pll }, 1, 0); -static CLK_GATE(g12a_fclk_div7, HHI_FIX_PLL_CNTL1, 23, 0, - { &g12a_fclk_div7_div }, 1, 0); -static CLK_FIXED_FACTOR(g12a_fclk_div2p5_div, 1, 5, 0, { &g12a_fixed_pll_dco }, - 1, 0); -static CLK_GATE(g12a_fclk_div2p5, HHI_FIX_PLL_CNTL1, 25, 0, - { &g12a_fclk_div2p5_div }, 1, 0); -static CLK_FIXED_FACTOR(g12a_mpll_50m_div, 1, 80, 0, { &g12a_fixed_pll_dco }, 1, - 0); +static CLK_GATE(g12a_fclk_div7, HHI_FIX_PLL_CNTL1, 23, 0, { &g12a_fclk_div7_div }, 1, 0); +static CLK_FIXED_FACTOR(g12a_fclk_div2p5_div, 1, 5, 0, { &g12a_fixed_pll_dco }, 1, 0); +static CLK_GATE(g12a_fclk_div2p5, HHI_FIX_PLL_CNTL1, 25, 0, { &g12a_fclk_div2p5_div }, 1, 0); +static CLK_FIXED_FACTOR(g12a_mpll_50m_div, 1, 80, 0, { &g12a_fixed_pll_dco }, 1, 0); const static struct clk_parent_data g12a_mpll_50m_parent_table[] = { { .name = "xtal", }, { .clk = &g12a_mpll_50m_div }, }; -static CLK_MUX_RO(g12a_mpll_50m, HHI_FIX_PLL_CNTL3, 0x1, 5, 0, 0, - g12a_mpll_50m_parent_table, 2, 0); -static CLK_FIXED_FACTOR(g12a_mpll_prediv, 1, 2, 0, { &g12a_fixed_pll_dco }, 1, - 0); +static CLK_MUX_RO(g12a_mpll_50m, HHI_FIX_PLL_CNTL3, 0x1, 5, 0, 0, g12a_mpll_50m_parent_table, 2, 0); +static CLK_FIXED_FACTOR(g12a_mpll_prediv, 1, 2, 0, { &g12a_fixed_pll_dco }, 1, 0); static const struct reg_sequence g12a_mpll0_init_regs[] = { { .reg = HHI_MPLL_CNTL2, .def = 0x40000033 }, @@ -787,13 +733,10 @@ static const struct clk_parent_data clk81_parent_data[] = { { .clk = &g12a_fclk_div3 }, { .clk = &g12a_fclk_div5 }, }; -static CLK_MUX_RO(g12a_mpeg_clk_sel, HHI_MPEG_CLK_CNTL, 0x7, 12, - mux_table_clk81, 0, clk81_parent_data, +static CLK_MUX_RO(g12a_mpeg_clk_sel, HHI_MPEG_CLK_CNTL, 0x7, 12, mux_table_clk81, 0, clk81_parent_data, ARRAY_SIZE(clk81_parent_data), 0); -static CLK_DIV(g12a_mpeg_clk_div, HHI_MPEG_CLK_CNTL, 0, 7, 0, - { &g12a_mpeg_clk_sel }, 1, 0); -static CLK_GATE(g12a_clk81, HHI_MPEG_CLK_CNTL, 7, 0, { &g12a_mpeg_clk_div }, 1, - 0); +static CLK_DIV(g12a_mpeg_clk_div, HHI_MPEG_CLK_CNTL, 0, 7, 0, { &g12a_mpeg_clk_sel }, 1, 0); +static CLK_GATE(g12a_clk81, HHI_MPEG_CLK_CNTL, 7, 0, { &g12a_mpeg_clk_div }, 1, 0); static const struct clk_parent_data g12a_sd_emmc_clk0_parent_data[] = { { .name = "xtal", @@ -803,24 +746,18 @@ static const struct clk_parent_data g12a_sd_emmc_clk0_parent_data[] = { { .clk = &g12a_fclk_div5 }, { .clk = &g12a_fclk_div7 }, }; -static CLK_MUX(g12a_sd_emmc_a_clk0_sel, HHI_SD_EMMC_CLK_CNTL, 0x7, 9, 0, 0, - g12a_sd_emmc_clk0_parent_data, 0, CLK_SET_RATE_PARENT); -static CLK_DIV(g12a_sd_emmc_a_clk0_div, HHI_SD_EMMC_CLK_CNTL, 0, 7, 0, - { &g12a_sd_emmc_a_clk0_sel }, 1, 0); -static CLK_GATE(g12a_sd_emmc_a_clk0, HHI_SD_EMMC_CLK_CNTL, 7, 0, - { &g12a_sd_emmc_a_clk0_div }, 1, 0); -static CLK_MUX(g12a_sd_emmc_b_clk0_sel, HHI_SD_EMMC_CLK_CNTL, 0x7, 25, 0, 0, - g12a_sd_emmc_clk0_parent_data, 0, CLK_SET_RATE_PARENT); -static CLK_DIV(g12a_sd_emmc_b_clk0_div, HHI_SD_EMMC_CLK_CNTL, 16, 7, 0, - { &g12a_sd_emmc_b_clk0_sel }, 1, 0); -static CLK_GATE(g12a_sd_emmc_b_clk0, HHI_SD_EMMC_CLK_CNTL, 23, 0, - { &g12a_sd_emmc_b_clk0_div }, 1, 0); -static CLK_MUX(g12a_sd_emmc_c_clk0_sel, HHI_NAND_CLK_CNTL, 0x7, 9, 0, 0, - g12a_sd_emmc_clk0_parent_data, 0, CLK_SET_RATE_PARENT); -static CLK_DIV(g12a_sd_emmc_c_clk0_div, HHI_NAND_CLK_CNTL, 0, 7, 0, - { &g12a_sd_emmc_c_clk0_sel }, 1, 0); -static CLK_GATE(g12a_sd_emmc_c_clk0, HHI_NAND_CLK_CNTL, 7, 0, - { &g12a_sd_emmc_c_clk0_div }, 1, 0); +static CLK_MUX(g12a_sd_emmc_a_clk0_sel, HHI_SD_EMMC_CLK_CNTL, 0x7, 9, 0, 0, g12a_sd_emmc_clk0_parent_data, 0, + CLK_SET_RATE_PARENT); +static CLK_DIV(g12a_sd_emmc_a_clk0_div, HHI_SD_EMMC_CLK_CNTL, 0, 7, 0, { &g12a_sd_emmc_a_clk0_sel }, 1, 0); +static CLK_GATE(g12a_sd_emmc_a_clk0, HHI_SD_EMMC_CLK_CNTL, 7, 0, { &g12a_sd_emmc_a_clk0_div }, 1, 0); +static CLK_MUX(g12a_sd_emmc_b_clk0_sel, HHI_SD_EMMC_CLK_CNTL, 0x7, 25, 0, 0, g12a_sd_emmc_clk0_parent_data, 0, + CLK_SET_RATE_PARENT); +static CLK_DIV(g12a_sd_emmc_b_clk0_div, HHI_SD_EMMC_CLK_CNTL, 16, 7, 0, { &g12a_sd_emmc_b_clk0_sel }, 1, 0); +static CLK_GATE(g12a_sd_emmc_b_clk0, HHI_SD_EMMC_CLK_CNTL, 23, 0, { &g12a_sd_emmc_b_clk0_div }, 1, 0); +static CLK_MUX(g12a_sd_emmc_c_clk0_sel, HHI_NAND_CLK_CNTL, 0x7, 9, 0, 0, g12a_sd_emmc_clk0_parent_data, 0, + CLK_SET_RATE_PARENT); +static CLK_DIV(g12a_sd_emmc_c_clk0_div, HHI_NAND_CLK_CNTL, 0, 7, 0, { &g12a_sd_emmc_c_clk0_sel }, 1, 0); +static CLK_GATE(g12a_sd_emmc_c_clk0, HHI_NAND_CLK_CNTL, 7, 0, { &g12a_sd_emmc_c_clk0_div }, 1, 0); static struct clk g12a_vid_pll_div = { .data = &(struct meson_vid_pll_div_data){ .val = { @@ -851,11 +788,9 @@ static const struct clk_parent_data g12a_vid_pll_parent_table[] = { }, }; -static CLK_MUX(g12a_vid_pll_sel, HHI_VID_PLL_CLK_DIV, 0x1, 18, 0, 0, - g12a_vid_pll_parent_table, 0, +static CLK_MUX(g12a_vid_pll_sel, HHI_VID_PLL_CLK_DIV, 0x1, 18, 0, 0, g12a_vid_pll_parent_table, 0, CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE); -static CLK_GATE(g12a_vid_pll, HHI_VID_PLL_CLK_DIV, 19, 0, { &g12a_vid_pll_sel }, - 1, 0); +static CLK_GATE(g12a_vid_pll, HHI_VID_PLL_CLK_DIV, 19, 0, { &g12a_vid_pll_sel }, 1, 0); const static struct clk_parent_data g12a_vpu_sel_parent_table[] = { { .clk = &g12a_fclk_div3, @@ -882,22 +817,17 @@ const static struct clk_parent_data g12a_vpu_sel_parent_table[] = { .clk = &g12a_gp0_pll, }, }; -static CLK_MUX(g12a_vpu_0_sel, HHI_VPU_CLK_CNTL, 0x7, 9, 0, 0, - g12a_vpu_sel_parent_table, 0, CLK_SET_RATE_NO_REPARENT); -static CLK_DIV(g12a_vpu_0_div, HHI_VPU_CLK_CNTL, 0, 7, 0, { &g12a_vpu_0_sel }, - 1, 0); +static CLK_MUX(g12a_vpu_0_sel, HHI_VPU_CLK_CNTL, 0x7, 9, 0, 0, g12a_vpu_sel_parent_table, 0, CLK_SET_RATE_NO_REPARENT); +static CLK_DIV(g12a_vpu_0_div, HHI_VPU_CLK_CNTL, 0, 7, 0, { &g12a_vpu_0_sel }, 1, 0); static CLK_GATE(g12a_vpu_0, HHI_VPU_CLK_CNTL, 8, 0, { &g12a_vpu_0_div }, 1, 0); -static CLK_MUX(g12a_vpu_1_sel, HHI_VPU_CLK_CNTL, 0x7, 25, 0, 0, - g12a_vpu_sel_parent_table, 0, CLK_SET_RATE_NO_REPARENT); -static CLK_DIV(g12a_vpu_1_div, HHI_VPU_CLK_CNTL, 16, 7, 0, { &g12a_vpu_1_sel }, - 1, 0); +static CLK_MUX(g12a_vpu_1_sel, HHI_VPU_CLK_CNTL, 0x7, 25, 0, 0, g12a_vpu_sel_parent_table, 0, CLK_SET_RATE_NO_REPARENT); +static CLK_DIV(g12a_vpu_1_div, HHI_VPU_CLK_CNTL, 16, 7, 0, { &g12a_vpu_1_sel }, 1, 0); static CLK_GATE(g12a_vpu_1, HHI_VPU_CLK_CNTL, 24, 0, { &g12a_vpu_1_div }, 1, 0); const struct clk_parent_data g12a_vpu_parent_table[] = { { .clk = &g12a_vpu_0 }, { .clk = &g12a_vpu_1 }, }; -static CLK_MUX(g12a_vpu, HHI_VPU_CLK_CNTL, 1, 31, 0, 0, g12a_vpu_parent_table, - 2, 0); +static CLK_MUX(g12a_vpu, HHI_VPU_CLK_CNTL, 1, 31, 0, 0, g12a_vpu_parent_table, 2, 0); static const struct clk_parent_data g12a_vdec_parent_table[] = { { .clk = &g12a_fclk_div2p5, @@ -922,27 +852,19 @@ static const struct clk_parent_data g12a_vdec_parent_table[] = { }, }; -static CLK_MUX(g12a_vdec_1_sel, HHI_VDEC_CLK_CNTL, 0x7, 9, 0, - CLK_MUX_ROUND_CLOSEST, g12a_vdec_parent_table, 0, +static CLK_MUX(g12a_vdec_1_sel, HHI_VDEC_CLK_CNTL, 0x7, 9, 0, CLK_MUX_ROUND_CLOSEST, g12a_vdec_parent_table, 0, CLK_SET_RATE_PARENT); -static CLK_DIV(g12a_vdec_1_div, HHI_VDEC_CLK_CNTL, 0, 7, - CLK_DIVIDER_ROUND_CLOSEST, { &g12a_vdec_1_sel }, 1, 0); -static CLK_GATE(g12a_vdec_1, HHI_VDEC_CLK_CNTL, 8, 0, { &g12a_vdec_1_div }, 1, - 0); -static CLK_MUX(g12a_vdec_hevcf_sel, HHI_VDEC2_CLK_CNTL, 0x7, 9, 0, - CLK_MUX_ROUND_CLOSEST, g12a_vdec_parent_table, 0, +static CLK_DIV(g12a_vdec_1_div, HHI_VDEC_CLK_CNTL, 0, 7, CLK_DIVIDER_ROUND_CLOSEST, { &g12a_vdec_1_sel }, 1, 0); +static CLK_GATE(g12a_vdec_1, HHI_VDEC_CLK_CNTL, 8, 0, { &g12a_vdec_1_div }, 1, 0); +static CLK_MUX(g12a_vdec_hevcf_sel, HHI_VDEC2_CLK_CNTL, 0x7, 9, 0, CLK_MUX_ROUND_CLOSEST, g12a_vdec_parent_table, 0, CLK_SET_RATE_PARENT); -static CLK_DIV(g12a_vdec_hevcf_div, HHI_VDEC2_CLK_CNTL, 0, 7, - CLK_DIVIDER_ROUND_CLOSEST, { &g12a_vdec_hevcf_sel }, 1, 0); -static CLK_GATE(g12a_vdec_hevcf, HHI_VDEC2_CLK_CNTL, 8, 0, - { &g12a_vdec_hevcf_div }, 1, 0); -static CLK_MUX(g12a_vdec_hevc_sel, HHI_VDEC2_CLK_CNTL, 0x7, 25, 0, - CLK_MUX_ROUND_CLOSEST, g12a_vdec_parent_table, 0, +static CLK_DIV(g12a_vdec_hevcf_div, HHI_VDEC2_CLK_CNTL, 0, 7, CLK_DIVIDER_ROUND_CLOSEST, { &g12a_vdec_hevcf_sel }, 1, + 0); +static CLK_GATE(g12a_vdec_hevcf, HHI_VDEC2_CLK_CNTL, 8, 0, { &g12a_vdec_hevcf_div }, 1, 0); +static CLK_MUX(g12a_vdec_hevc_sel, HHI_VDEC2_CLK_CNTL, 0x7, 25, 0, CLK_MUX_ROUND_CLOSEST, g12a_vdec_parent_table, 0, CLK_SET_RATE_PARENT); -static CLK_DIV(g12a_vdec_hevc_div, HHI_VDEC2_CLK_CNTL, 16, 7, - CLK_DIVIDER_ROUND_CLOSEST, { &g12a_vdec_hevc_sel }, 1, 0); -static CLK_GATE(g12a_vdec_hevc, HHI_VDEC2_CLK_CNTL, 24, 0, - { &g12a_vdec_hevc_div }, 1, 0); +static CLK_DIV(g12a_vdec_hevc_div, HHI_VDEC2_CLK_CNTL, 16, 7, CLK_DIVIDER_ROUND_CLOSEST, { &g12a_vdec_hevc_sel }, 1, 0); +static CLK_GATE(g12a_vdec_hevc, HHI_VDEC2_CLK_CNTL, 24, 0, { &g12a_vdec_hevc_div }, 1, 0); static const struct clk_parent_data g12a_vapb_parent_table[] = { { .clk = &g12a_fclk_div4, @@ -969,24 +891,17 @@ static const struct clk_parent_data g12a_vapb_parent_table[] = { .clk = &g12a_fclk_div2p5, }, }; -static CLK_MUX(g12a_vapb_0_sel, HHI_VAPBCLK_CNTL, 0x3, 9, 0, 0, - g12a_vapb_parent_table, 0, CLK_SET_RATE_NO_REPARENT); -static CLK_DIV(g12a_vapb_0_div, HHI_VAPBCLK_CNTL, 0, 7, 0, { &g12a_vapb_0_sel }, - 1, 0); -static CLK_GATE(g12a_vapb_0, HHI_VAPBCLK_CNTL, 8, 0, { &g12a_vapb_0_div }, 1, - 0); -static CLK_MUX(g12a_vapb_1_sel, HHI_VAPBCLK_CNTL, 0x3, 25, 0, 0, - g12a_vapb_parent_table, 0, CLK_SET_RATE_NO_REPARENT); -static CLK_DIV(g12a_vapb_1_div, HHI_VAPBCLK_CNTL, 16, 7, 0, - { &g12a_vapb_1_sel }, 1, 0); -static CLK_GATE(g12a_vapb_1, HHI_VAPBCLK_CNTL, 24, 0, { &g12a_vapb_1_div }, 1, - 0); +static CLK_MUX(g12a_vapb_0_sel, HHI_VAPBCLK_CNTL, 0x3, 9, 0, 0, g12a_vapb_parent_table, 0, CLK_SET_RATE_NO_REPARENT); +static CLK_DIV(g12a_vapb_0_div, HHI_VAPBCLK_CNTL, 0, 7, 0, { &g12a_vapb_0_sel }, 1, 0); +static CLK_GATE(g12a_vapb_0, HHI_VAPBCLK_CNTL, 8, 0, { &g12a_vapb_0_div }, 1, 0); +static CLK_MUX(g12a_vapb_1_sel, HHI_VAPBCLK_CNTL, 0x3, 25, 0, 0, g12a_vapb_parent_table, 0, CLK_SET_RATE_NO_REPARENT); +static CLK_DIV(g12a_vapb_1_div, HHI_VAPBCLK_CNTL, 16, 7, 0, { &g12a_vapb_1_sel }, 1, 0); +static CLK_GATE(g12a_vapb_1, HHI_VAPBCLK_CNTL, 24, 0, { &g12a_vapb_1_div }, 1, 0); const struct clk_parent_data g12a_vapb_sel_parent_table[] = { { .clk = &g12a_vapb_0 }, { .clk = &g12a_vapb_1 }, }; -static CLK_MUX(g12a_vapb_sel, HHI_VAPBCLK_CNTL, 1, 31, 0, 0, - g12a_vapb_sel_parent_table, 2, 0); +static CLK_MUX(g12a_vapb_sel, HHI_VAPBCLK_CNTL, 1, 31, 0, 0, g12a_vapb_sel_parent_table, 2, 0); static CLK_GATE(g12a_vapb, HHI_VAPBCLK_CNTL, 30, 0, { &g12a_vapb_sel }, 1, 0); static const struct clk_parent_data g12a_vclk_parent_table[] = { { @@ -1014,17 +929,12 @@ static const struct clk_parent_data g12a_vclk_parent_table[] = { .clk = &g12a_fclk_div7, }, }; -static CLK_MUX(g12a_vclk_sel, HHI_VID_CLK_CNTL, 0x7, 16, 0, 0, - g12a_vclk_parent_table, 0, +static CLK_MUX(g12a_vclk_sel, HHI_VID_CLK_CNTL, 0x7, 16, 0, 0, g12a_vclk_parent_table, 0, CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE); -static CLK_MUX(g12a_vclk2_sel, HHI_VIID_CLK_CNTL, 0x7, 16, 0, 0, - g12a_vclk_parent_table, 0, CLK_SET_RATE_NO_REPARENT); -static CLK_GATE(g12a_vclk_input, HHI_VID_CLK_DIV, 16, 0, { &g12a_vclk_sel }, 1, - 0); -static CLK_GATE(g12a_vclk2_input, HHI_VIID_CLK_DIV, 16, 0, { &g12a_vclk2_sel }, - 1, 0); -static CLK_DIV(g12a_vclk_div, HHI_VID_CLK_DIV, 0, 8, 0, { &g12a_vclk_input }, 1, - 0); +static CLK_MUX(g12a_vclk2_sel, HHI_VIID_CLK_CNTL, 0x7, 16, 0, 0, g12a_vclk_parent_table, 0, CLK_SET_RATE_NO_REPARENT); +static CLK_GATE(g12a_vclk_input, HHI_VID_CLK_DIV, 16, 0, { &g12a_vclk_sel }, 1, 0); +static CLK_GATE(g12a_vclk2_input, HHI_VIID_CLK_DIV, 16, 0, { &g12a_vclk2_sel }, 1, 0); +static CLK_DIV(g12a_vclk_div, HHI_VID_CLK_DIV, 0, 8, 0, { &g12a_vclk_input }, 1, 0); static struct clk g12a_vclk2_div = { .data = &(struct meson_vclk_div_data){ .div = { @@ -1077,37 +987,23 @@ static struct clk g12a_vclk2 = { }, }; static CLK_GATE(g12a_vclk_div1, HHI_VID_CLK_CNTL, 0, 0, { &g12a_vclk }, 1, 0); -static CLK_GATE(g12a_vclk_div2_en, HHI_VID_CLK_CNTL, 1, 0, { &g12a_vclk }, 1, - 0); -static CLK_GATE(g12a_vclk_div4_en, HHI_VID_CLK_CNTL, 2, 0, { &g12a_vclk }, 1, - 0); -static CLK_GATE(g12a_vclk_div6_en, HHI_VID_CLK_CNTL, 3, 0, { &g12a_vclk }, 1, - 0); -static CLK_GATE(g12a_vclk_div12_en, HHI_VID_CLK_CNTL, 4, 0, { &g12a_vclk }, 1, - 0); -static CLK_GATE(g12a_vclk2_div1, HHI_VIID_CLK_CNTL, 0, 0, { &g12a_vclk2 }, 1, - 0); -static CLK_GATE(g12a_vclk2_div2_en, HHI_VIID_CLK_CNTL, 1, 0, { &g12a_vclk2 }, 1, - 0); -static CLK_GATE(g12a_vclk2_div4_en, HHI_VIID_CLK_CNTL, 2, 0, { &g12a_vclk2 }, 1, - 0); -static CLK_GATE(g12a_vclk2_div6_en, HHI_VIID_CLK_CNTL, 3, 0, { &g12a_vclk2 }, 1, - 0); -static CLK_GATE(g12a_vclk2_div12_en, HHI_VIID_CLK_CNTL, 4, 0, { &g12a_vclk2 }, - 1, 0); +static CLK_GATE(g12a_vclk_div2_en, HHI_VID_CLK_CNTL, 1, 0, { &g12a_vclk }, 1, 0); +static CLK_GATE(g12a_vclk_div4_en, HHI_VID_CLK_CNTL, 2, 0, { &g12a_vclk }, 1, 0); +static CLK_GATE(g12a_vclk_div6_en, HHI_VID_CLK_CNTL, 3, 0, { &g12a_vclk }, 1, 0); +static CLK_GATE(g12a_vclk_div12_en, HHI_VID_CLK_CNTL, 4, 0, { &g12a_vclk }, 1, 0); +static CLK_GATE(g12a_vclk2_div1, HHI_VIID_CLK_CNTL, 0, 0, { &g12a_vclk2 }, 1, 0); +static CLK_GATE(g12a_vclk2_div2_en, HHI_VIID_CLK_CNTL, 1, 0, { &g12a_vclk2 }, 1, 0); +static CLK_GATE(g12a_vclk2_div4_en, HHI_VIID_CLK_CNTL, 2, 0, { &g12a_vclk2 }, 1, 0); +static CLK_GATE(g12a_vclk2_div6_en, HHI_VIID_CLK_CNTL, 3, 0, { &g12a_vclk2 }, 1, 0); +static CLK_GATE(g12a_vclk2_div12_en, HHI_VIID_CLK_CNTL, 4, 0, { &g12a_vclk2 }, 1, 0); static CLK_FIXED_FACTOR(g12a_vclk_div2, 1, 2, 0, { &g12a_vclk_div2_en }, 1, 0); static CLK_FIXED_FACTOR(g12a_vclk_div4, 1, 4, 0, { &g12a_vclk_div4_en }, 1, 0); static CLK_FIXED_FACTOR(g12a_vclk_div6, 1, 6, 0, { &g12a_vclk_div6_en }, 1, 0); -static CLK_FIXED_FACTOR(g12a_vclk_div12, 1, 12, 0, { &g12a_vclk_div12_en }, 1, - 0); -static CLK_FIXED_FACTOR(g12a_vclk2_div2, 1, 2, 0, { &g12a_vclk2_div2_en }, 1, - 0); -static CLK_FIXED_FACTOR(g12a_vclk2_div4, 1, 4, 0, { &g12a_vclk2_div4_en }, 1, - 0); -static CLK_FIXED_FACTOR(g12a_vclk2_div6, 1, 6, 0, { &g12a_vclk2_div6_en }, 1, - 0); -static CLK_FIXED_FACTOR(g12a_vclk2_div12, 1, 12, 0, { &g12a_vclk2_div12_en }, 1, - 0); +static CLK_FIXED_FACTOR(g12a_vclk_div12, 1, 12, 0, { &g12a_vclk_div12_en }, 1, 0); +static CLK_FIXED_FACTOR(g12a_vclk2_div2, 1, 2, 0, { &g12a_vclk2_div2_en }, 1, 0); +static CLK_FIXED_FACTOR(g12a_vclk2_div4, 1, 4, 0, { &g12a_vclk2_div4_en }, 1, 0); +static CLK_FIXED_FACTOR(g12a_vclk2_div6, 1, 6, 0, { &g12a_vclk2_div6_en }, 1, 0); +static CLK_FIXED_FACTOR(g12a_vclk2_div12, 1, 12, 0, { &g12a_vclk2_div12_en }, 1, 0); static uint32_t mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; static const struct clk_parent_data g12a_cts_parent_table[] = { { @@ -1141,18 +1037,14 @@ static const struct clk_parent_data g12a_cts_parent_table[] = { .clk = &g12a_vclk2_div12, }, }; -static CLK_MUX(g12a_cts_enci_sel, HHI_VID_CLK_DIV, 0xf, 28, mux_table_cts_sel, - 0, g12a_cts_parent_table, ARRAY_SIZE(g12a_cts_parent_table), - CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE); -static CLK_MUX(g12a_cts_encp_sel, HHI_VID_CLK_DIV, 0xf, 20, mux_table_cts_sel, - 0, g12a_cts_parent_table, ARRAY_SIZE(g12a_cts_parent_table), - CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE); -static CLK_MUX(g12a_cts_encl_sel, HHI_VIID_CLK_DIV, 0xf, 12, mux_table_cts_sel, - 0, g12a_cts_parent_table, ARRAY_SIZE(g12a_cts_parent_table), - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT); -static CLK_MUX(g12a_cts_vdac_sel, HHI_VIID_CLK_DIV, 0xf, 28, mux_table_cts_sel, - 0, g12a_cts_parent_table, ARRAY_SIZE(g12a_cts_parent_table), - CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE); +static CLK_MUX(g12a_cts_enci_sel, HHI_VID_CLK_DIV, 0xf, 28, mux_table_cts_sel, 0, g12a_cts_parent_table, + ARRAY_SIZE(g12a_cts_parent_table), CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE); +static CLK_MUX(g12a_cts_encp_sel, HHI_VID_CLK_DIV, 0xf, 20, mux_table_cts_sel, 0, g12a_cts_parent_table, + ARRAY_SIZE(g12a_cts_parent_table), CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE); +static CLK_MUX(g12a_cts_encl_sel, HHI_VIID_CLK_DIV, 0xf, 12, mux_table_cts_sel, 0, g12a_cts_parent_table, + ARRAY_SIZE(g12a_cts_parent_table), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT); +static CLK_MUX(g12a_cts_vdac_sel, HHI_VIID_CLK_DIV, 0xf, 28, mux_table_cts_sel, 0, g12a_cts_parent_table, + ARRAY_SIZE(g12a_cts_parent_table), CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE); static uint32_t mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; static const struct clk_parent_data g12a_cts_hdmi_tx_parent_table[] = { { @@ -1186,20 +1078,13 @@ static const struct clk_parent_data g12a_cts_hdmi_tx_parent_table[] = { .clk = &g12a_vclk2_div12, }, }; -static CLK_MUX(g12a_hdmi_tx_sel, HHI_HDMI_CLK_CNTL, 0xf, 16, - mux_table_hdmi_tx_sel, 0, g12a_cts_hdmi_tx_parent_table, - ARRAY_SIZE(g12a_cts_hdmi_tx_parent_table), - CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE); -static CLK_GATE(g12a_cts_enci, HHI_VID_CLK_CNTL2, 0, 0, { &g12a_cts_enci_sel }, - 1, 0); -static CLK_GATE(g12a_cts_encp, HHI_VID_CLK_CNTL2, 2, 0, { &g12a_cts_encp_sel }, - 1, 0); -static CLK_GATE(g12a_cts_encl, HHI_VID_CLK_CNTL2, 3, 0, { &g12a_cts_encl_sel }, - 1, 0); -static CLK_GATE(g12a_cts_vdac, HHI_VID_CLK_CNTL2, 4, 0, { &g12a_cts_vdac_sel }, - 1, 0); -static CLK_GATE(g12a_hdmi_tx, HHI_VID_CLK_CNTL2, 5, 0, { &g12a_hdmi_tx_sel }, 1, - 0); +static CLK_MUX(g12a_hdmi_tx_sel, HHI_HDMI_CLK_CNTL, 0xf, 16, mux_table_hdmi_tx_sel, 0, g12a_cts_hdmi_tx_parent_table, + ARRAY_SIZE(g12a_cts_hdmi_tx_parent_table), CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE); +static CLK_GATE(g12a_cts_enci, HHI_VID_CLK_CNTL2, 0, 0, { &g12a_cts_enci_sel }, 1, 0); +static CLK_GATE(g12a_cts_encp, HHI_VID_CLK_CNTL2, 2, 0, { &g12a_cts_encp_sel }, 1, 0); +static CLK_GATE(g12a_cts_encl, HHI_VID_CLK_CNTL2, 3, 0, { &g12a_cts_encl_sel }, 1, 0); +static CLK_GATE(g12a_cts_vdac, HHI_VID_CLK_CNTL2, 4, 0, { &g12a_cts_vdac_sel }, 1, 0); +static CLK_GATE(g12a_hdmi_tx, HHI_VID_CLK_CNTL2, 5, 0, { &g12a_hdmi_tx_sel }, 1, 0); static const struct clk_parent_data g12a_mipi_dsi_pxclk_parent_table[] = { { .clk = &g12a_vid_pll, @@ -1226,14 +1111,11 @@ static const struct clk_parent_data g12a_mipi_dsi_pxclk_parent_table[] = { .clk = &g12a_fclk_div7, }, }; -static CLK_MUX(g12a_mipi_dsi_pxclk_sel, HHI_MIPIDSI_PHY_CLK_CNTL, 0x7, 12, 0, - CLK_MUX_ROUND_CLOSEST, g12a_mipi_dsi_pxclk_parent_table, - ARRAY_SIZE(g12a_mipi_dsi_pxclk_parent_table), +static CLK_MUX(g12a_mipi_dsi_pxclk_sel, HHI_MIPIDSI_PHY_CLK_CNTL, 0x7, 12, 0, CLK_MUX_ROUND_CLOSEST, + g12a_mipi_dsi_pxclk_parent_table, ARRAY_SIZE(g12a_mipi_dsi_pxclk_parent_table), CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT); -static CLK_DIV(g12a_mipi_dsi_pxclk_div, HHI_MIPIDSI_PHY_CLK_CNTL, 0, 7, 0, - { &g12a_mipi_dsi_pxclk_sel }, 1, 0); -static CLK_GATE(g12a_mipi_dsi_pxclk, HHI_MIPIDSI_PHY_CLK_CNTL, 8, 0, - { &g12a_mipi_dsi_pxclk_div }, 1, 0); +static CLK_DIV(g12a_mipi_dsi_pxclk_div, HHI_MIPIDSI_PHY_CLK_CNTL, 0, 7, 0, { &g12a_mipi_dsi_pxclk_sel }, 1, 0); +static CLK_GATE(g12a_mipi_dsi_pxclk, HHI_MIPIDSI_PHY_CLK_CNTL, 8, 0, { &g12a_mipi_dsi_pxclk_div }, 1, 0); static const struct clk_parent_data g12a_hdmi_parent_table[] = { { .name = "xtal", @@ -1242,12 +1124,9 @@ static const struct clk_parent_data g12a_hdmi_parent_table[] = { { .clk = &g12a_fclk_div3 }, { .clk = &g12a_fclk_div5 }, }; -static CLK_MUX(g12a_hdmi_sel, HHI_HDMI_CLK_CNTL, 0x3, 9, 0, - CLK_MUX_ROUND_CLOSEST, g12a_hdmi_parent_table, - ARRAY_SIZE(g12a_hdmi_parent_table), - CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE); -static CLK_DIV(g12a_hdmi_div, HHI_HDMI_CLK_CNTL, 0, 7, 0, { &g12a_hdmi_sel }, 1, - 0); +static CLK_MUX(g12a_hdmi_sel, HHI_HDMI_CLK_CNTL, 0x3, 9, 0, CLK_MUX_ROUND_CLOSEST, g12a_hdmi_parent_table, + ARRAY_SIZE(g12a_hdmi_parent_table), CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE); +static CLK_DIV(g12a_hdmi_div, HHI_HDMI_CLK_CNTL, 0, 7, 0, { &g12a_hdmi_sel }, 1, 0); static CLK_GATE(g12a_hdmi, HHI_HDMI_CLK_CNTL, 8, 0, { &g12a_hdmi_div }, 1, 0); static const struct clk_parent_data g12a_mali_0_1_parent_data[] = { { @@ -1261,18 +1140,12 @@ static const struct clk_parent_data g12a_mali_0_1_parent_data[] = { { .clk = &g12a_fclk_div5 }, { .clk = &g12a_fclk_div7 }, }; -static CLK_MUX(g12a_mali_0_sel, HHI_MALI_CLK_CNTL, 0x7, 9, 0, 0, - g12a_mali_0_1_parent_data, 8, 0); -static CLK_DIV(g12a_mali_0_div, HHI_MALI_CLK_CNTL, 0, 7, 0, - { &g12a_mali_0_sel }, 1, 0); -static CLK_GATE(g12a_mali_0, HHI_MALI_CLK_CNTL, 8, 0, { &g12a_mali_0_div }, 1, - 0); -static CLK_MUX(g12a_mali_1_sel, HHI_MALI_CLK_CNTL, 0x7, 25, 0, 0, - g12a_mali_0_1_parent_data, 8, 0); -static CLK_DIV(g12a_mali_1_div, HHI_MALI_CLK_CNTL, 16, 7, 0, - { &g12a_mali_1_sel }, 1, 0); -static CLK_GATE(g12a_mali_1, HHI_MALI_CLK_CNTL, 24, 0, { &g12a_mali_1_div }, 1, - 0); +static CLK_MUX(g12a_mali_0_sel, HHI_MALI_CLK_CNTL, 0x7, 9, 0, 0, g12a_mali_0_1_parent_data, 8, 0); +static CLK_DIV(g12a_mali_0_div, HHI_MALI_CLK_CNTL, 0, 7, 0, { &g12a_mali_0_sel }, 1, 0); +static CLK_GATE(g12a_mali_0, HHI_MALI_CLK_CNTL, 8, 0, { &g12a_mali_0_div }, 1, 0); +static CLK_MUX(g12a_mali_1_sel, HHI_MALI_CLK_CNTL, 0x7, 25, 0, 0, g12a_mali_0_1_parent_data, 8, 0); +static CLK_DIV(g12a_mali_1_div, HHI_MALI_CLK_CNTL, 16, 7, 0, { &g12a_mali_1_sel }, 1, 0); +static CLK_GATE(g12a_mali_1, HHI_MALI_CLK_CNTL, 24, 0, { &g12a_mali_1_div }, 1, 0); static const struct clk_parent_data g12a_mali_parent_table[] = { { .clk = &g12a_mali_0, @@ -1281,10 +1154,8 @@ static const struct clk_parent_data g12a_mali_parent_table[] = { .clk = &g12a_mali_1, }, }; -static CLK_MUX(g12a_mali, HHI_MALI_CLK_CNTL, 1, 31, 0, 0, - g12a_mali_parent_table, 2, CLK_SET_RATE_PARENT); -static CLK_DIV_RO(g12a_ts_div, HHI_TS_CLK_CNTL, 0, 8, 0, { &g12a_ts_div }, 1, - 0); +static CLK_MUX(g12a_mali, HHI_MALI_CLK_CNTL, 1, 31, 0, 0, g12a_mali_parent_table, 2, CLK_SET_RATE_PARENT); +static CLK_DIV_RO(g12a_ts_div, HHI_TS_CLK_CNTL, 0, 8, 0, { &g12a_ts_div }, 1, 0); static CLK_GATE(g12a_ts, HHI_TS_CLK_CNTL, 8, 0, { &g12a_ts_div }, 1, 0); static const struct clk_parent_data spicc_sclk_parent_data[] = { { @@ -1297,18 +1168,12 @@ static const struct clk_parent_data spicc_sclk_parent_data[] = { { .clk = &g12a_fclk_div7 }, }; -static CLK_MUX(g12a_spicc0_sclk_sel, HHI_SPICC_CLK_CNTL, 7, 7, 0, 0, - spicc_sclk_parent_data, 0, 0); -static CLK_DIV(g12a_spicc0_sclk_div, HHI_SPICC_CLK_CNTL, 0, 6, 0, - { &g12a_spicc0_sclk_sel }, 1, 0); -static CLK_GATE(g12a_spicc0_sclk, HHI_SPICC_CLK_CNTL, 6, 0, - { &g12a_spicc0_sclk_div }, 1, 0); -static CLK_MUX(g12a_spicc1_sclk_sel, HHI_SPICC_CLK_CNTL, 7, 23, 0, 0, - spicc_sclk_parent_data, 0, 0); -static CLK_DIV(g12a_spicc1_sclk_div, HHI_SPICC_CLK_CNTL, 16, 6, 0, - { &g12a_spicc1_sclk_sel }, 1, 0); -static CLK_GATE(g12a_spicc1_sclk, HHI_SPICC_CLK_CNTL, 22, 0, - { &g12a_spicc1_sclk_div }, 1, 0); +static CLK_MUX(g12a_spicc0_sclk_sel, HHI_SPICC_CLK_CNTL, 7, 7, 0, 0, spicc_sclk_parent_data, 0, 0); +static CLK_DIV(g12a_spicc0_sclk_div, HHI_SPICC_CLK_CNTL, 0, 6, 0, { &g12a_spicc0_sclk_sel }, 1, 0); +static CLK_GATE(g12a_spicc0_sclk, HHI_SPICC_CLK_CNTL, 6, 0, { &g12a_spicc0_sclk_div }, 1, 0); +static CLK_MUX(g12a_spicc1_sclk_sel, HHI_SPICC_CLK_CNTL, 7, 23, 0, 0, spicc_sclk_parent_data, 0, 0); +static CLK_DIV(g12a_spicc1_sclk_div, HHI_SPICC_CLK_CNTL, 16, 6, 0, { &g12a_spicc1_sclk_sel }, 1, 0); +static CLK_GATE(g12a_spicc1_sclk, HHI_SPICC_CLK_CNTL, 22, 0, { &g12a_spicc1_sclk_div }, 1, 0); static const struct clk_parent_data nna_clk_parent_data[] = { { .name = "xtal", @@ -1333,18 +1198,12 @@ static const struct clk_parent_data nna_clk_parent_data[] = { }, { .clk = &g12a_fclk_div7 }, }; -static CLK_MUX(sm1_nna_axi_clk_sel, HHI_NNA_CLK_CNTL, 7, 9, 0, 0, - nna_clk_parent_data, 0, 0); -static CLK_DIV(sm1_nna_axi_clk_div, HHI_NNA_CLK_CNTL, 0, 7, 0, - { &sm1_nna_axi_clk_sel }, 1, 0); -static CLK_GATE(sm1_nna_axi_clk, HHI_NNA_CLK_CNTL, 8, 0, - { &sm1_nna_axi_clk_div }, 1, 0); -static CLK_MUX(sm1_nna_core_clk_sel, HHI_NNA_CLK_CNTL, 7, 25, 0, 0, - nna_clk_parent_data, 0, 0); -static CLK_DIV(sm1_nna_core_clk_div, HHI_NNA_CLK_CNTL, 16, 7, 0, - { &sm1_nna_core_clk_sel }, 1, 0); -static CLK_GATE(sm1_nna_core_clk, HHI_NNA_CLK_CNTL, 24, 0, - { &sm1_nna_core_clk_div }, 1, 0); +static CLK_MUX(sm1_nna_axi_clk_sel, HHI_NNA_CLK_CNTL, 7, 9, 0, 0, nna_clk_parent_data, 0, 0); +static CLK_DIV(sm1_nna_axi_clk_div, HHI_NNA_CLK_CNTL, 0, 7, 0, { &sm1_nna_axi_clk_sel }, 1, 0); +static CLK_GATE(sm1_nna_axi_clk, HHI_NNA_CLK_CNTL, 8, 0, { &sm1_nna_axi_clk_div }, 1, 0); +static CLK_MUX(sm1_nna_core_clk_sel, HHI_NNA_CLK_CNTL, 7, 25, 0, 0, nna_clk_parent_data, 0, 0); +static CLK_DIV(sm1_nna_core_clk_div, HHI_NNA_CLK_CNTL, 16, 7, 0, { &sm1_nna_core_clk_sel }, 1, 0); +static CLK_GATE(sm1_nna_core_clk, HHI_NNA_CLK_CNTL, 24, 0, { &sm1_nna_core_clk_div }, 1, 0); /* Everything Else (EE) domain gates */ static MESON_CLK81_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0); diff --git a/examples/clk/client.c b/examples/clk/client.c index e9d66036f..0fef03106 100644 --- a/examples/clk/client.c +++ b/examples/clk/client.c @@ -19,27 +19,69 @@ void init(void) #ifdef TEST_BOARD_odroidc4 sddf_dprintf("Test board: odroidc4\n"); - uint32_t ret = sddf_clk_enable(CLK_DRIVER_CH, 10); - sddf_dprintf("ret_val: %x\n", ret); + /** + * CLKID_CLK81 = 10 + * CLKID_I2C = 24 + * CLKID_CPU_CLK = 187 + * + * see `sddf/drivers/clk/meson/include/g12a-bindings.h` for more clock indices. + * + **/ + uint32_t clk_id_to_enable = 10; + int ret = sddf_clk_enable(CLK_DRIVER_CH, clk_id_to_enable); + if (ret) { + sddf_dprintf("Failed to enable clock %u: err - %d\n", clk_id_to_enable, ret); + } else { + sddf_dprintf("Successfully enabled clock %u\n", clk_id_to_enable); + } - ret = sddf_clk_disable(CLK_DRIVER_CH, 24); - sddf_dprintf("ret_val: %x\n", ret); + uint32_t clk_id_to_disable = 24; + ret = sddf_clk_disable(CLK_DRIVER_CH, clk_id_to_disable); + if (ret) { + sddf_dprintf("Failed to disable clock %u: err - %d\n", clk_id_to_enable, ret); + } else { + sddf_dprintf("Successfully disabled clock %u\n", clk_id_to_enable); + } uint64_t rate = 0; - ret = sddf_clk_get_rate(CLK_DRIVER_CH, 10, &rate); - sddf_dprintf("err: %d rate: %lu\n", ret, rate); + uint32_t clk_id_to_set_rate = 10; + ret = sddf_clk_get_rate(CLK_DRIVER_CH, clk_id_to_set_rate, &rate); + if (ret) { + sddf_dprintf("Failed to get the rate of clock %u: err - %d\n", clk_id_to_set_rate, ret); + } else { + sddf_dprintf("The rate of clock %u: %lu\n", clk_id_to_set_rate, rate); + } - ret = sddf_clk_set_rate(CLK_DRIVER_CH, 10, 150000000, &rate); - sddf_dprintf("err: %d, rate: %lu\n", ret, rate); + ret = sddf_clk_set_rate(CLK_DRIVER_CH, clk_id_to_set_rate, 150000000, &rate); + if (ret) { + sddf_dprintf("Failed to set the rate of clock %u: err - %d\n", clk_id_to_set_rate, ret); + } else { + sddf_dprintf("Set the rate of clock %u to %lu\n", ret, rate); + } - ret = sddf_clk_get_rate(CLK_DRIVER_CH, 187, &rate); - sddf_dprintf("err: %d, rate: %lu\n", ret, rate); + uint32_t clk_id_to_get_rate = 187; + ret = sddf_clk_get_rate(CLK_DRIVER_CH, clk_id_to_get_rate, &rate); + if (ret) { + sddf_dprintf("Failed to get the rate of clock %u: err - %d\n", clk_id_to_get_rate, ret); + } else { + sddf_dprintf("The rate of clock %u: %lu\n", clk_id_to_get_rate, rate); + } #elif TEST_BOARD_maaxboard sddf_dprintf("Test board: maaxboard\n"); - uint32_t ret = sddf_clk_enable(CLK_DRIVER_CH, 196); - sddf_dprintf("ret_val: %x\n", ret); + /** + * IMX8MQ_CLK_SAI1_ROOT = 196 + * + * see `sddf/drivers/clk/imx/include/imx8mq-bindings.h` for more clock indices. + * */ + uint32_t clk_id_to_enable = 196; + int ret = sddf_clk_enable(CLK_DRIVER_CH, clk_id_to_enable); + if (ret) { + sddf_dprintf("Failed to enable clock %u: err - %d\n", clk_id_to_enable, ret); + } else { + sddf_dprintf("Successfully enabled clock %u\n", clk_id_to_enable); + } #else sddf_dprintf("No tests for the target board\n", ret); diff --git a/include/sddf/clk/client.h b/include/sddf/clk/client.h index d5dc3e937..21c1f3336 100644 --- a/include/sddf/clk/client.h +++ b/include/sddf/clk/client.h @@ -16,15 +16,14 @@ * @param channel of clock driver. * @param identifier of target clock. */ -static inline uint32_t sddf_clk_enable(microkit_channel channel, - uint32_t clk_id) +static inline int sddf_clk_enable(microkit_channel channel, uint32_t clk_id) { microkit_msginfo msginfo = microkit_msginfo_new(SDDF_CLK_ENABLE, 1); microkit_mr_set(SDDF_CLK_PARAM_ID, clk_id); msginfo = microkit_ppcall(channel, msginfo); - return (uint32_t)microkit_msginfo_get_label(msginfo); + return (int)microkit_msginfo_get_label(msginfo); } /** @@ -33,15 +32,14 @@ static inline uint32_t sddf_clk_enable(microkit_channel channel, * @param channel of clock driver. * @param identifier of target clock. */ -static inline uint32_t sddf_clk_disable(microkit_channel channel, - uint32_t clk_id) +static inline int sddf_clk_disable(microkit_channel channel, uint32_t clk_id) { microkit_msginfo msginfo = microkit_msginfo_new(SDDF_CLK_DISABLE, 1); microkit_mr_set(SDDF_CLK_PARAM_ID, clk_id); msginfo = microkit_ppcall(channel, msginfo); - return (uint32_t)microkit_msginfo_get_label(msginfo); + return (int)microkit_msginfo_get_label(msginfo); } /** @@ -51,8 +49,7 @@ static inline uint32_t sddf_clk_disable(microkit_channel channel, * @param identifier of target clock. * @param pointer to result variable. */ -static inline uint32_t sddf_clk_get_rate(microkit_channel channel, - uint32_t clk_id, uint64_t *rate) +static inline int sddf_clk_get_rate(microkit_channel channel, uint32_t clk_id, uint64_t *rate) { microkit_msginfo msginfo = microkit_msginfo_new(SDDF_CLK_GET_RATE, 1); microkit_mr_set(SDDF_CLK_PARAM_ID, clk_id); @@ -60,7 +57,7 @@ static inline uint32_t sddf_clk_get_rate(microkit_channel channel, msginfo = microkit_ppcall(channel, msginfo); *rate = microkit_mr_get(0); - return (uint32_t)microkit_msginfo_get_label(msginfo); + return (int)microkit_msginfo_get_label(msginfo); } /** @@ -71,9 +68,7 @@ static inline uint32_t sddf_clk_get_rate(microkit_channel channel, * @param target clock frequency. * @param pointer to result variable. */ -static inline uint32_t sddf_clk_set_rate(microkit_channel channel, - uint32_t clk_id, uint64_t req_rate, - uint64_t *rate) +static inline int sddf_clk_set_rate(microkit_channel channel, uint32_t clk_id, uint64_t req_rate, uint64_t *rate) { microkit_msginfo msginfo = microkit_msginfo_new(SDDF_CLK_SET_RATE, 2); microkit_mr_set(SDDF_CLK_PARAM_ID, clk_id); @@ -82,5 +77,5 @@ static inline uint32_t sddf_clk_set_rate(microkit_channel channel, msginfo = microkit_ppcall(channel, msginfo); *rate = microkit_mr_get(0); - return (uint32_t)microkit_msginfo_get_label(msginfo); + return (int)microkit_msginfo_get_label(msginfo); }