diff --git a/LICENSES/GPL-2.0-only.txt b/LICENSES/GPL-2.0-only.txt new file mode 100644 index 000000000..17cb28643 --- /dev/null +++ b/LICENSES/GPL-2.0-only.txt @@ -0,0 +1,117 @@ +GNU GENERAL PUBLIC LICENSE +Version 2, June 1991 + +Copyright (C) 1989, 1991 Free Software Foundation, Inc. +51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + +Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. + +Preamble + +The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users. This General Public License applies to most of the Free Software Foundation's software and to any other program whose authors commit to using it. (Some other Free Software Foundation software is covered by the GNU Lesser General Public License instead.) You can apply it to your programs, too. + +When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs; and that you know you can do these things. + +To protect your rights, we need to make restrictions that forbid anyone to deny you these rights or to ask you to surrender the rights. These restrictions translate to certain responsibilities for you if you distribute copies of the software, or if you modify it. + +For example, if you distribute copies of such a program, whether gratis or for a fee, you must give the recipients all the rights that you have. You must make sure that they, too, receive or can get the source code. And you must show them these terms so they know their rights. + +We protect your rights with two steps: (1) copyright the software, and (2) offer you this license which gives you legal permission to copy, distribute and/or modify the software. + +Also, for each author's protection and ours, we want to make certain that everyone understands that there is no warranty for this free software. If the software is modified by someone else and passed on, we want its recipients to know that what they have is not the original, so that any problems introduced by others will not reflect on the original authors' reputations. + +Finally, any free program is threatened constantly by software patents. We wish to avoid the danger that redistributors of a free program will individually obtain patent licenses, in effect making the program proprietary. To prevent this, we have made it clear that any patent must be licensed for everyone's free use or not licensed at all. + +The precise terms and conditions for copying, distribution and modification follow. + +TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + +0. This License applies to any program or other work which contains a notice placed by the copyright holder saying it may be distributed under the terms of this General Public License. The "Program", below, refers to any such program or work, and a "work based on the Program" means either the Program or any derivative work under copyright law: that is to say, a work containing the Program or a portion of it, either verbatim or with modifications and/or translated into another language. (Hereinafter, translation is included without limitation in the term "modification".) Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not covered by this License; they are outside its scope. The act of running the Program is not restricted, and the output from the Program is covered only if its contents constitute a work based on the Program (independent of having been made by running the Program). Whether that is true depends on what the Program does. + +1. You may copy and distribute verbatim copies of the Program's source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and disclaimer of warranty; keep intact all the notices that refer to this License and to the absence of any warranty; and give any other recipients of the Program a copy of this License along with the Program. + +You may charge a fee for the physical act of transferring a copy, and you may at your option offer warranty protection in exchange for a fee. + +2. You may modify your copy or copies of the Program or any portion of it, thus forming a work based on the Program, and copy and distribute such modifications or work under the terms of Section 1 above, provided that you also meet all of these conditions: + + a) You must cause the modified files to carry prominent notices stating that you changed the files and the date of any change. + + b) You must cause any work that you distribute or publish, that in whole or in part contains or is derived from the Program or any part thereof, to be licensed as a whole at no charge to all third parties under the terms of this License. + + c) If the modified program normally reads commands interactively when run, you must cause it, when started running for such interactive use in the most ordinary way, to print or display an announcement including an appropriate copyright notice and a notice that there is no warranty (or else, saying that you provide a warranty) and that users may redistribute the program under these conditions, and telling the user how to view a copy of this License. (Exception: if the Program itself is interactive but does not normally print such an announcement, your work based on the Program is not required to print an announcement.) + +These requirements apply to the modified work as a whole. If identifiable sections of that work are not derived from the Program, and can be reasonably considered independent and separate works in themselves, then this License, and its terms, do not apply to those sections when you distribute them as separate works. But when you distribute the same sections as part of a whole which is a work based on the Program, the distribution of the whole must be on the terms of this License, whose permissions for other licensees extend to the entire whole, and thus to each and every part regardless of who wrote it. + +Thus, it is not the intent of this section to claim rights or contest your rights to work written entirely by you; rather, the intent is to exercise the right to control the distribution of derivative or collective works based on the Program. + +In addition, mere aggregation of another work not based on the Program with the Program (or with a work based on the Program) on a volume of a storage or distribution medium does not bring the other work under the scope of this License. + +3. You may copy and distribute the Program (or a work based on it, under Section 2) in object code or executable form under the terms of Sections 1 and 2 above provided that you also do one of the following: + + a) Accompany it with the complete corresponding machine-readable source code, which must be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, + + b) Accompany it with a written offer, valid for at least three years, to give any third party, for a charge no more than your cost of physically performing source distribution, a complete machine-readable copy of the corresponding source code, to be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, + + c) Accompany it with the information you received as to the offer to distribute corresponding source code. (This alternative is allowed only for noncommercial distribution and only if you received the program in object code or executable form with such an offer, in accord with Subsection b above.) + +The source code for a work means the preferred form of the work for making modifications to it. For an executable work, complete source code means all the source code for all modules it contains, plus any associated interface definition files, plus the scripts used to control compilation and installation of the executable. However, as a special exception, the source code distributed need not include anything that is normally distributed (in either source or binary form) with the major components (compiler, kernel, and so on) of the operating system on which the executable runs, unless that component itself accompanies the executable. + +If distribution of executable or object code is made by offering access to copy from a designated place, then offering equivalent access to copy the source code from the same place counts as distribution of the source code, even though third parties are not compelled to copy the source along with the object code. + +4. You may not copy, modify, sublicense, or distribute the Program except as expressly provided under this License. Any attempt otherwise to copy, modify, sublicense or distribute the Program is void, and will automatically terminate your rights under this License. However, parties who have received copies, or rights, from you under this License will not have their licenses terminated so long as such parties remain in full compliance. + +5. You are not required to accept this License, since you have not signed it. However, nothing else grants you permission to modify or distribute the Program or its derivative works. These actions are prohibited by law if you do not accept this License. Therefore, by modifying or distributing the Program (or any work based on the Program), you indicate your acceptance of this License to do so, and all its terms and conditions for copying, distributing or modifying the Program or works based on it. + +6. Each time you redistribute the Program (or any work based on the Program), the recipient automatically receives a license from the original licensor to copy, distribute or modify the Program subject to these terms and conditions. You may not impose any further restrictions on the recipients' exercise of the rights granted herein. You are not responsible for enforcing compliance by third parties to this License. + +7. If, as a consequence of a court judgment or allegation of patent infringement or for any other reason (not limited to patent issues), conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot distribute so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not distribute the Program at all. For example, if a patent license would not permit royalty-free redistribution of the Program by all those who receive copies directly or indirectly through you, then the only way you could satisfy both it and this License would be to refrain entirely from distribution of the Program. + +If any portion of this section is held invalid or unenforceable under any particular circumstance, the balance of the section is intended to apply and the section as a whole is intended to apply in other circumstances. + +It is not the purpose of this section to induce you to infringe any patents or other property right claims or to contest validity of any such claims; this section has the sole purpose of protecting the integrity of the free software distribution system, which is implemented by public license practices. Many people have made generous contributions to the wide range of software distributed through that system in reliance on consistent application of that system; it is up to the author/donor to decide if he or she is willing to distribute software through any other system and a licensee cannot impose that choice. + +This section is intended to make thoroughly clear what is believed to be a consequence of the rest of this License. + +8. If the distribution and/or use of the Program is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder who places the Program under this License may add an explicit geographical distribution limitation excluding those countries, so that distribution is permitted only in or among countries not thus excluded. In such case, this License incorporates the limitation as if written in the body of this License. + +9. The Free Software Foundation may publish revised and/or new versions of the General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. + +Each version is given a distinguishing version number. If the Program specifies a version number of this License which applies to it and "any later version", you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of this License, you may choose any version ever published by the Free Software Foundation. + +10. If you wish to incorporate parts of the Program into other free programs whose distribution conditions are different, write to the author to ask for permission. For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this. Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally. + +NO WARRANTY + +11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. + +12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + +END OF TERMS AND CONDITIONS + +How to Apply These Terms to Your New Programs + +If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms. + +To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively convey the exclusion of warranty; and each file should have at least the "copyright" line and a pointer to where the full notice is found. + + one line to give the program's name and an idea of what it does. Copyright (C) yyyy name of author + + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, the commands you use may be called something other than `show w' and `show c'; they could even be mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your school, if any, to sign a "copyright disclaimer" for the program, if necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program `Gnomovision' (which makes passes at compilers) written by James Hacker. + +signature of Ty Coon, 1 April 1989 Ty Coon, President of Vice diff --git a/LICENSES/GPL-2.0-or-later.txt b/LICENSES/GPL-2.0-or-later.txt new file mode 100644 index 000000000..17cb28643 --- /dev/null +++ b/LICENSES/GPL-2.0-or-later.txt @@ -0,0 +1,117 @@ +GNU GENERAL PUBLIC LICENSE +Version 2, June 1991 + +Copyright (C) 1989, 1991 Free Software Foundation, Inc. +51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + +Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. + +Preamble + +The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users. This General Public License applies to most of the Free Software Foundation's software and to any other program whose authors commit to using it. (Some other Free Software Foundation software is covered by the GNU Lesser General Public License instead.) You can apply it to your programs, too. + +When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs; and that you know you can do these things. + +To protect your rights, we need to make restrictions that forbid anyone to deny you these rights or to ask you to surrender the rights. These restrictions translate to certain responsibilities for you if you distribute copies of the software, or if you modify it. + +For example, if you distribute copies of such a program, whether gratis or for a fee, you must give the recipients all the rights that you have. You must make sure that they, too, receive or can get the source code. And you must show them these terms so they know their rights. + +We protect your rights with two steps: (1) copyright the software, and (2) offer you this license which gives you legal permission to copy, distribute and/or modify the software. + +Also, for each author's protection and ours, we want to make certain that everyone understands that there is no warranty for this free software. If the software is modified by someone else and passed on, we want its recipients to know that what they have is not the original, so that any problems introduced by others will not reflect on the original authors' reputations. + +Finally, any free program is threatened constantly by software patents. We wish to avoid the danger that redistributors of a free program will individually obtain patent licenses, in effect making the program proprietary. To prevent this, we have made it clear that any patent must be licensed for everyone's free use or not licensed at all. + +The precise terms and conditions for copying, distribution and modification follow. + +TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + +0. This License applies to any program or other work which contains a notice placed by the copyright holder saying it may be distributed under the terms of this General Public License. The "Program", below, refers to any such program or work, and a "work based on the Program" means either the Program or any derivative work under copyright law: that is to say, a work containing the Program or a portion of it, either verbatim or with modifications and/or translated into another language. (Hereinafter, translation is included without limitation in the term "modification".) Each licensee is addressed as "you". + +Activities other than copying, distribution and modification are not covered by this License; they are outside its scope. The act of running the Program is not restricted, and the output from the Program is covered only if its contents constitute a work based on the Program (independent of having been made by running the Program). Whether that is true depends on what the Program does. + +1. You may copy and distribute verbatim copies of the Program's source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and disclaimer of warranty; keep intact all the notices that refer to this License and to the absence of any warranty; and give any other recipients of the Program a copy of this License along with the Program. + +You may charge a fee for the physical act of transferring a copy, and you may at your option offer warranty protection in exchange for a fee. + +2. You may modify your copy or copies of the Program or any portion of it, thus forming a work based on the Program, and copy and distribute such modifications or work under the terms of Section 1 above, provided that you also meet all of these conditions: + + a) You must cause the modified files to carry prominent notices stating that you changed the files and the date of any change. + + b) You must cause any work that you distribute or publish, that in whole or in part contains or is derived from the Program or any part thereof, to be licensed as a whole at no charge to all third parties under the terms of this License. + + c) If the modified program normally reads commands interactively when run, you must cause it, when started running for such interactive use in the most ordinary way, to print or display an announcement including an appropriate copyright notice and a notice that there is no warranty (or else, saying that you provide a warranty) and that users may redistribute the program under these conditions, and telling the user how to view a copy of this License. (Exception: if the Program itself is interactive but does not normally print such an announcement, your work based on the Program is not required to print an announcement.) + +These requirements apply to the modified work as a whole. If identifiable sections of that work are not derived from the Program, and can be reasonably considered independent and separate works in themselves, then this License, and its terms, do not apply to those sections when you distribute them as separate works. But when you distribute the same sections as part of a whole which is a work based on the Program, the distribution of the whole must be on the terms of this License, whose permissions for other licensees extend to the entire whole, and thus to each and every part regardless of who wrote it. + +Thus, it is not the intent of this section to claim rights or contest your rights to work written entirely by you; rather, the intent is to exercise the right to control the distribution of derivative or collective works based on the Program. + +In addition, mere aggregation of another work not based on the Program with the Program (or with a work based on the Program) on a volume of a storage or distribution medium does not bring the other work under the scope of this License. + +3. You may copy and distribute the Program (or a work based on it, under Section 2) in object code or executable form under the terms of Sections 1 and 2 above provided that you also do one of the following: + + a) Accompany it with the complete corresponding machine-readable source code, which must be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, + + b) Accompany it with a written offer, valid for at least three years, to give any third party, for a charge no more than your cost of physically performing source distribution, a complete machine-readable copy of the corresponding source code, to be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, + + c) Accompany it with the information you received as to the offer to distribute corresponding source code. (This alternative is allowed only for noncommercial distribution and only if you received the program in object code or executable form with such an offer, in accord with Subsection b above.) + +The source code for a work means the preferred form of the work for making modifications to it. For an executable work, complete source code means all the source code for all modules it contains, plus any associated interface definition files, plus the scripts used to control compilation and installation of the executable. However, as a special exception, the source code distributed need not include anything that is normally distributed (in either source or binary form) with the major components (compiler, kernel, and so on) of the operating system on which the executable runs, unless that component itself accompanies the executable. + +If distribution of executable or object code is made by offering access to copy from a designated place, then offering equivalent access to copy the source code from the same place counts as distribution of the source code, even though third parties are not compelled to copy the source along with the object code. + +4. You may not copy, modify, sublicense, or distribute the Program except as expressly provided under this License. Any attempt otherwise to copy, modify, sublicense or distribute the Program is void, and will automatically terminate your rights under this License. However, parties who have received copies, or rights, from you under this License will not have their licenses terminated so long as such parties remain in full compliance. + +5. You are not required to accept this License, since you have not signed it. However, nothing else grants you permission to modify or distribute the Program or its derivative works. These actions are prohibited by law if you do not accept this License. Therefore, by modifying or distributing the Program (or any work based on the Program), you indicate your acceptance of this License to do so, and all its terms and conditions for copying, distributing or modifying the Program or works based on it. + +6. Each time you redistribute the Program (or any work based on the Program), the recipient automatically receives a license from the original licensor to copy, distribute or modify the Program subject to these terms and conditions. You may not impose any further restrictions on the recipients' exercise of the rights granted herein. You are not responsible for enforcing compliance by third parties to this License. + +7. If, as a consequence of a court judgment or allegation of patent infringement or for any other reason (not limited to patent issues), conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot distribute so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not distribute the Program at all. For example, if a patent license would not permit royalty-free redistribution of the Program by all those who receive copies directly or indirectly through you, then the only way you could satisfy both it and this License would be to refrain entirely from distribution of the Program. + +If any portion of this section is held invalid or unenforceable under any particular circumstance, the balance of the section is intended to apply and the section as a whole is intended to apply in other circumstances. + +It is not the purpose of this section to induce you to infringe any patents or other property right claims or to contest validity of any such claims; this section has the sole purpose of protecting the integrity of the free software distribution system, which is implemented by public license practices. Many people have made generous contributions to the wide range of software distributed through that system in reliance on consistent application of that system; it is up to the author/donor to decide if he or she is willing to distribute software through any other system and a licensee cannot impose that choice. + +This section is intended to make thoroughly clear what is believed to be a consequence of the rest of this License. + +8. If the distribution and/or use of the Program is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder who places the Program under this License may add an explicit geographical distribution limitation excluding those countries, so that distribution is permitted only in or among countries not thus excluded. In such case, this License incorporates the limitation as if written in the body of this License. + +9. The Free Software Foundation may publish revised and/or new versions of the General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. + +Each version is given a distinguishing version number. If the Program specifies a version number of this License which applies to it and "any later version", you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of this License, you may choose any version ever published by the Free Software Foundation. + +10. If you wish to incorporate parts of the Program into other free programs whose distribution conditions are different, write to the author to ask for permission. For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this. Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally. + +NO WARRANTY + +11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. + +12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + +END OF TERMS AND CONDITIONS + +How to Apply These Terms to Your New Programs + +If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms. + +To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively convey the exclusion of warranty; and each file should have at least the "copyright" line and a pointer to where the full notice is found. + + one line to give the program's name and an idea of what it does. Copyright (C) yyyy name of author + + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, the commands you use may be called something other than `show w' and `show c'; they could even be mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your school, if any, to sign a "copyright disclaimer" for the program, if necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program `Gnomovision' (which makes passes at compilers) written by James Hacker. + +signature of Ty Coon, 1 April 1989 Ty Coon, President of Vice diff --git a/drivers/clk/clk-operations.c b/drivers/clk/clk-operations.c index c3af46ded..828f03ac4 100644 --- a/drivers/clk/clk-operations.c +++ b/drivers/clk/clk-operations.c @@ -83,14 +83,14 @@ #include #include -static int clk_gate_enable(struct clk *clk) +static inline int clk_gate_enable(struct clk *clk) { struct clk_gate_data *data = (struct clk_gate_data *)(clk->data); return regmap_update_bits(clk->base, data->offset, data->bit_idx, 1, 1); } -static int clk_gate_disable(struct clk *clk) +static inline int clk_gate_disable(struct clk *clk) { struct clk_gate_data *data = (struct clk_gate_data *)(clk->data); @@ -98,7 +98,7 @@ static int clk_gate_disable(struct clk *clk) return 0; } -static int clk_gate_is_enabled(struct clk *clk) +static inline int clk_gate_is_enabled(struct clk *clk) { struct clk_gate_data *data = (struct clk_gate_data *)(clk->data); @@ -122,7 +122,7 @@ const struct clk_ops clk_gate_ro_ops = { .is_enabled = clk_gate_is_enabled, }; -static unsigned long clk_div_recalc_rate(const struct clk *clk, +static inline unsigned long clk_div_recalc_rate(const struct clk *clk, unsigned long prate) { @@ -144,7 +144,7 @@ static unsigned long clk_div_recalc_rate(const struct clk *clk, return DIV_ROUND_UP_ULL((uint64_t)prate, div); } -static int clk_div_set_rate(const struct clk *clk, uint32_t rate, +static inline int clk_div_set_rate(const struct clk *clk, uint32_t rate, uint32_t parent_rate) { struct clk_div_data *data = (struct clk_div_data *)(clk->data); @@ -160,8 +160,8 @@ static int clk_div_set_rate(const struct clk *clk, uint32_t rate, } else { div -= 1; } - return regmap_update_bits(clk->base, data->offset, data->shift, - data->width, div); + return regmap_update_bits(clk->base, data->offset, data->shift, data->width, + div); } const struct clk_ops clk_divider_ops = { @@ -176,12 +176,12 @@ const struct clk_ops clk_divider_ro_ops = { /* .determine_rate = clk_div_determine_rate, */ }; -static uint8_t clk_mux_get_parent(const struct clk *clk) +static inline uint8_t clk_mux_get_parent(const struct clk *clk) { struct clk_mux_data *data = (struct clk_mux_data *)(clk->data); uint32_t num_parents = clk->hw.init->num_parents; - uint32_t val = regmap_mux_read_bits(clk->base, data->offset, - data->shift, data->mask); + uint32_t val = regmap_mux_read_bits(clk->base, data->offset, data->shift, + data->mask); if (data->table) { int i; @@ -207,16 +207,17 @@ static uint8_t clk_mux_get_parent(const struct clk *clk) return 0; } -static int clk_mux_set_parent(struct clk *clk, uint8_t index) +static inline int clk_mux_set_parent(struct clk *clk, uint8_t index) { struct clk_mux_data *data = (struct clk_mux_data *)(clk->data); if (data->table) { unsigned int val = data->table[index]; - regmap_mux_update_bits(clk->base, data->offset, data->shift, - data->mask, val); + regmap_mux_update_bits(clk->base, data->offset, data->shift, data->mask, + val); } - /* TODO: handle cases without table given */ + regmap_mux_update_bits(clk->base, data->offset, data->shift, data->mask, + index); return 0; } @@ -230,7 +231,7 @@ const struct clk_ops clk_mux_ro_ops = { .get_parent = clk_mux_get_parent, }; -static unsigned long clk_factor_recalc_rate(const struct clk *clk, +static inline unsigned long clk_factor_recalc_rate(const struct clk *clk, unsigned long parent_rate) { struct clk_fixed_factor_data *data = @@ -249,7 +250,7 @@ const struct clk_ops clk_fixed_factor_ops = { /* .recalc_accuracy = clk_factor_recalc_accuracy, */ }; -static int clk_source_set_rate(const struct clk *clk, uint32_t rate, +static inline int clk_source_set_rate(const struct clk *clk, uint32_t rate, uint32_t parent_rate) { struct clk_source_data *data = (struct clk_source_data *)(clk->data); @@ -258,7 +259,7 @@ static int clk_source_set_rate(const struct clk *clk, uint32_t rate, return 0; } -static unsigned long clk_source_get_rate(const struct clk *clk, +static inline unsigned long clk_source_get_rate(const struct clk *clk, unsigned long prate) { struct clk_source_data *data = (struct clk_source_data *)(clk->data); diff --git a/drivers/clk/clk-operations.h b/drivers/clk/clk-operations.h index b15e18210..b419000f4 100644 --- a/drivers/clk/clk-operations.h +++ b/drivers/clk/clk-operations.h @@ -14,7 +14,7 @@ #define CLK_UNKNOWN_REQ 4 #define CLK_UNKNOWN_TARGET 5 -static inline uint32_t reg_write(uint64_t base, uint32_t offset, uint32_t val) +static inline int reg_write(uint64_t base, uint32_t offset, uint32_t val) { volatile uint32_t *clk_reg = ((void *)base + offset); *clk_reg = val; @@ -22,9 +22,9 @@ static inline uint32_t reg_write(uint64_t base, uint32_t offset, uint32_t val) return 0; } -static inline uint32_t regmap_update_bits(uint64_t base, uint32_t offset, - uint8_t shift, uint8_t width, - uint32_t val) +static inline int regmap_update_bits(uint64_t base, uint32_t offset, + uint8_t shift, uint8_t width, + uint32_t val) { volatile uint32_t *clk_reg = ((void *)base + offset); uint32_t reg_val = *clk_reg; @@ -34,8 +34,6 @@ static inline uint32_t regmap_update_bits(uint64_t base, uint32_t offset, *clk_reg = reg_val; - /* TODO: Check if the register has been updated correctly */ - return 0; } @@ -51,9 +49,9 @@ static inline uint32_t regmap_read_bits(uint64_t base, uint32_t offset, return reg_val; } -static inline uint32_t regmap_mux_update_bits(uint64_t base, uint32_t offset, - uint8_t shift, uint32_t mask, - uint32_t val) +static inline int regmap_mux_update_bits(uint64_t base, uint32_t offset, + uint8_t shift, uint32_t mask, + uint32_t val) { volatile uint32_t *clk_reg = ((void *)base + offset); uint32_t reg_val = *clk_reg; @@ -63,8 +61,6 @@ static inline uint32_t regmap_mux_update_bits(uint64_t base, uint32_t offset, *clk_reg = reg_val; - /* TODO: Check if the register has been updated correctly */ - return 0; } @@ -196,8 +192,8 @@ struct clk _name = { \ }, \ } -#define CLK_DIV_RO(_name, _offset, _shift, _width, _data_flags, \ - _parent_clks, _num_parents, _init_flags) \ +#define CLK_DIV_RO(_name, _offset, _shift, _width, _data_flags, _parent_clks, \ + _num_parents, _init_flags) \ struct clk _name = { \ .data = &(struct clk_div_data) { \ .offset = (_offset), \ diff --git a/drivers/clk/clk.h b/drivers/clk/clk.h index 4ce35155b..60bfd0485 100644 --- a/drivers/clk/clk.h +++ b/drivers/clk/clk.h @@ -165,7 +165,8 @@ struct clk_hw { struct clk_ops { uint8_t (*get_parent)(const struct clk *clk); int (*set_parent)(struct clk *clk, uint8_t index); - unsigned long (*recalc_rate)(const struct clk *clk, unsigned long parent_rate); + unsigned long (*recalc_rate)(const struct clk *clk, + unsigned long parent_rate); int (*set_rate)(const struct clk *clk, uint32_t rate, uint32_t parent_rate); void (*init)(struct clk *clk); int (*enable)(struct clk *clk); @@ -237,9 +238,6 @@ struct clk_source_data { * of this register, and mask of gate bits are in higher 16-bit of this * register. While setting the gate bits, higher 16-bit should also be * updated to indicate changing gate bits. - * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for - * the gate register. Setting this flag makes the register accesses big - * endian. */ struct clk_gate_data { uint32_t offset; @@ -282,9 +280,6 @@ struct clk_gate_data { * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED * except when the value read from the register is zero, the divisor is * 2^width of the field. - * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used - * for the divider register. Setting this flag makes the register accesses - * big endian. */ struct clk_div_data { uint32_t offset; diff --git a/drivers/clk/imx/clk-imx.c b/drivers/clk/imx/clk-imx.c index 7fe1d9764..ab3ccb801 100644 --- a/drivers/clk/imx/clk-imx.c +++ b/drivers/clk/imx/clk-imx.c @@ -79,17 +79,16 @@ static unsigned long clk_pll_recalc_rate(const struct clk *clk, uint64_t rate; /* Output Divider value is (n + 1) * 2 */ - uint32_t output_div_val = regmap_read_bits(clk->base, data->offset, - 0, 5); + uint32_t output_div_val = regmap_read_bits(clk->base, data->offset, 0, 5); output_div_val = (output_div_val + 1) * 2; /* Valid Frac Divider value is 1 to 2^24 */ - uint32_t frac_div_val = regmap_read_bits(clk->base, data->offset + 0x4, - 7, 24); + uint32_t frac_div_val = regmap_read_bits(clk->base, data->offset + 0x4, 7, + 24); /* Valid Int Divider value is 1 to 32 */ - uint32_t int_div_val = regmap_read_bits(clk->base, data->offset + 0x4, - 0, 7); + uint32_t int_div_val = regmap_read_bits(clk->base, data->offset + 0x4, 0, + 7); temp_rate *= prate; temp_rate *= frac_div_val; @@ -203,7 +202,8 @@ static uint8_t imx8m_clk_core_slice_get_parent(const struct clk *clk) static int imx8m_clk_core_slice_set_parent(struct clk *clk, uint8_t index) { - struct clk_core_slice_data *data = (struct clk_core_slice_data *)(clk->data); + struct clk_core_slice_data *data = + (struct clk_core_slice_data *)(clk->data); /* * write twice to make sure non-target interface @@ -232,16 +232,14 @@ static unsigned long imx8m_clk_common_slice_recalc_rate(const struct clk *clk, struct clk_common_slice_data *data = (struct clk_common_slice_data *)(clk->data); - uint32_t prediv_val = regmap_read_bits(clk->base, data->offset, - data->prevdiv_shift, - data->prevdiv_width); + uint32_t prediv_val = regmap_read_bits( + clk->base, data->offset, data->prevdiv_shift, data->prevdiv_width); /* Divider value is n+1 */ unsigned long prediv_rate = DIV_ROUND_UP_ULL((uint64_t)prate, prediv_val + 1); - uint32_t postdiv_val = regmap_read_bits(clk->base, data->offset, - data->postdiv_shift, - data->postdiv_width); + uint32_t postdiv_val = regmap_read_bits( + clk->base, data->offset, data->postdiv_shift, data->postdiv_width); /* Divider value is n+1 */ return DIV_ROUND_UP_ULL((uint64_t)prediv_rate, postdiv_val + 1); } @@ -292,14 +290,14 @@ static unsigned long imx8m_clk_bus_slice_recalc_rate(const struct clk *clk, { struct clk_bus_slice_data *data = (struct clk_bus_slice_data *)(clk->data); - uint32_t prediv_val = regmap_read_bits(clk->base, data->offset, - data->prevdiv_shift, data->prevdiv_width); + uint32_t prediv_val = regmap_read_bits( + clk->base, data->offset, data->prevdiv_shift, data->prevdiv_width); /* Divider value is n+1 */ unsigned long prediv_rate = DIV_ROUND_UP_ULL((uint64_t)prate, prediv_val + 1); - uint32_t postdiv_val = regmap_read_bits(clk->base, data->offset, - data->postdiv_shift, data->postdiv_width); + uint32_t postdiv_val = regmap_read_bits( + clk->base, data->offset, data->postdiv_shift, data->postdiv_width); /* Divider value is n+1 */ return DIV_ROUND_UP_ULL((uint64_t)prediv_rate, postdiv_val + 1); } diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 0bf1d4cd6..78a3807b6 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -2382,58 +2382,88 @@ static IMX_CLK_SOURCE(clk_ext2, 0x7ed6b40); static IMX_CLK_SOURCE(clk_ext3, 0x7ed6b40); static IMX_CLK_SOURCE(clk_ext4, 0x7ed6b40); -static IMX_CLK_MUX(arm_pll_ref_sel, CCM_ANALOG_BASE, 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); -static IMX_CLK_MUX(gpu_pll_ref_sel, CCM_ANALOG_BASE, 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); -static IMX_CLK_MUX(vpu_pll_ref_sel, CCM_ANALOG_BASE, 0x20, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); -static IMX_CLK_MUX(audio_pll1_ref_sel, CCM_ANALOG_BASE, 0x0, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); -static IMX_CLK_MUX(audio_pll2_ref_sel, CCM_ANALOG_BASE, 0x8, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); -static IMX_CLK_MUX(video_pll1_ref_sel, CCM_ANALOG_BASE, 0x10, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); -static IMX_CLK_MUX(sys3_pll1_ref_sel, CCM_ANALOG_BASE, 0x48, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); -static IMX_CLK_MUX(dram_pll1_ref_sel, CCM_ANALOG_BASE, 0x60, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); -static IMX_CLK_MUX(video2_pll1_ref_sel, CCM_ANALOG_BASE, 0x54, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - -static IMX_CLK_DIV(arm_pll_ref_div, { &arm_pll_ref_sel }, CCM_ANALOG_BASE, 0x28, 5, 6); -static IMX_CLK_DIV(gpu_pll_ref_div, { &gpu_pll_ref_sel }, CCM_ANALOG_BASE, 0x18, 5, 6); -static IMX_CLK_DIV(vpu_pll_ref_div, { &vpu_pll_ref_sel }, CCM_ANALOG_BASE, 0x20, 5, 6); -static IMX_CLK_DIV(audio_pll1_ref_div, { &audio_pll1_ref_sel }, CCM_ANALOG_BASE, 0x0, 5, 6); -static IMX_CLK_DIV(audio_pll2_ref_div, { &audio_pll2_ref_sel }, CCM_ANALOG_BASE, 0x8, 5, 6); -static IMX_CLK_DIV(video_pll1_ref_div, { &video_pll1_ref_sel }, CCM_ANALOG_BASE, 0x10, 5, 6); +static IMX_CLK_MUX(arm_pll_ref_sel, CCM_ANALOG_BASE, 0x28, 16, 2, pll_ref_sels, + ARRAY_SIZE(pll_ref_sels)); +static IMX_CLK_MUX(gpu_pll_ref_sel, CCM_ANALOG_BASE, 0x18, 16, 2, pll_ref_sels, + ARRAY_SIZE(pll_ref_sels)); +static IMX_CLK_MUX(vpu_pll_ref_sel, CCM_ANALOG_BASE, 0x20, 16, 2, pll_ref_sels, + ARRAY_SIZE(pll_ref_sels)); +static IMX_CLK_MUX(audio_pll1_ref_sel, CCM_ANALOG_BASE, 0x0, 16, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); +static IMX_CLK_MUX(audio_pll2_ref_sel, CCM_ANALOG_BASE, 0x8, 16, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); +static IMX_CLK_MUX(video_pll1_ref_sel, CCM_ANALOG_BASE, 0x10, 16, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); +static IMX_CLK_MUX(sys3_pll1_ref_sel, CCM_ANALOG_BASE, 0x48, 0, 2, pll_ref_sels, + ARRAY_SIZE(pll_ref_sels)); +static IMX_CLK_MUX(dram_pll1_ref_sel, CCM_ANALOG_BASE, 0x60, 0, 2, pll_ref_sels, + ARRAY_SIZE(pll_ref_sels)); +static IMX_CLK_MUX(video2_pll1_ref_sel, CCM_ANALOG_BASE, 0x54, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + +static IMX_CLK_DIV(arm_pll_ref_div, { &arm_pll_ref_sel }, CCM_ANALOG_BASE, 0x28, + 5, 6); +static IMX_CLK_DIV(gpu_pll_ref_div, { &gpu_pll_ref_sel }, CCM_ANALOG_BASE, 0x18, + 5, 6); +static IMX_CLK_DIV(vpu_pll_ref_div, { &vpu_pll_ref_sel }, CCM_ANALOG_BASE, 0x20, + 5, 6); +static IMX_CLK_DIV(audio_pll1_ref_div, { &audio_pll1_ref_sel }, CCM_ANALOG_BASE, + 0x0, 5, 6); +static IMX_CLK_DIV(audio_pll2_ref_div, { &audio_pll2_ref_sel }, CCM_ANALOG_BASE, + 0x8, 5, 6); +static IMX_CLK_DIV(video_pll1_ref_div, { &video_pll1_ref_sel }, CCM_ANALOG_BASE, + 0x10, 5, 6); static IMX_CLK_FRAC_PLL(arm_pll, { &arm_pll_ref_div }, CCM_ANALOG_BASE, 0x28); static IMX_CLK_FRAC_PLL(gpu_pll, { &gpu_pll_ref_div }, CCM_ANALOG_BASE, 0x18); static IMX_CLK_FRAC_PLL(vpu_pll, { &vpu_pll_ref_div }, CCM_ANALOG_BASE, 0x20); -static IMX_CLK_FRAC_PLL(audio_pll1, { &audio_pll1_ref_div }, CCM_ANALOG_BASE, 0x0); -static IMX_CLK_FRAC_PLL(audio_pll2, { &audio_pll2_ref_div }, CCM_ANALOG_BASE, 0x8); -static IMX_CLK_FRAC_PLL(video_pll1, { &video_pll1_ref_div }, CCM_ANALOG_BASE, 0x10); +static IMX_CLK_FRAC_PLL(audio_pll1, { &audio_pll1_ref_div }, CCM_ANALOG_BASE, + 0x0); +static IMX_CLK_FRAC_PLL(audio_pll2, { &audio_pll2_ref_div }, CCM_ANALOG_BASE, + 0x8); +static IMX_CLK_FRAC_PLL(video_pll1, { &video_pll1_ref_div }, CCM_ANALOG_BASE, + 0x10); /* PLL bypass out */ -static IMX_CLK_MUX_FLAGS(arm_pll_bypass, CCM_ANALOG_BASE, 0x28, 14, 1, arm_pll_bypass_sels, - ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT); -static IMX_CLK_MUX(gpu_pll_bypass, CCM_ANALOG_BASE, 0x18, 14, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels)); -static IMX_CLK_MUX(vpu_pll_bypass, CCM_ANALOG_BASE, 0x20, 14, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels)); -static IMX_CLK_MUX(audio_pll1_bypass, CCM_ANALOG_BASE, 0x0, 14, 1, audio_pll1_bypass_sels, - ARRAY_SIZE(audio_pll1_bypass_sels)); -static IMX_CLK_MUX(audio_pll2_bypass, CCM_ANALOG_BASE, 0x8, 14, 1, audio_pll2_bypass_sels, - ARRAY_SIZE(audio_pll2_bypass_sels)); -static IMX_CLK_MUX(video_pll1_bypass, CCM_ANALOG_BASE, 0x10, 14, 1, video_pll1_bypass_sels, - ARRAY_SIZE(video_pll1_bypass_sels)); +static IMX_CLK_MUX_FLAGS(arm_pll_bypass, CCM_ANALOG_BASE, 0x28, 14, 1, + arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), + CLK_SET_RATE_PARENT); +static IMX_CLK_MUX(gpu_pll_bypass, CCM_ANALOG_BASE, 0x18, 14, 1, + gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels)); +static IMX_CLK_MUX(vpu_pll_bypass, CCM_ANALOG_BASE, 0x20, 14, 1, + vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels)); +static IMX_CLK_MUX(audio_pll1_bypass, CCM_ANALOG_BASE, 0x0, 14, 1, + audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels)); +static IMX_CLK_MUX(audio_pll2_bypass, CCM_ANALOG_BASE, 0x8, 14, 1, + audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels)); +static IMX_CLK_MUX(video_pll1_bypass, CCM_ANALOG_BASE, 0x10, 14, 1, + video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels)); /* PLL OUT GATE */ -static IMX_CLK_GATE(arm_pll_out, { &arm_pll_bypass }, CCM_ANALOG_BASE, 0x28, 21); -static IMX_CLK_GATE(gpu_pll_out, { &gpu_pll_bypass }, CCM_ANALOG_BASE, 0x18, 21); -static IMX_CLK_GATE(vpu_pll_out, { &vpu_pll_bypass }, CCM_ANALOG_BASE, 0x20, 21); -static IMX_CLK_GATE(audio_pll1_out, { &audio_pll1_bypass }, CCM_ANALOG_BASE, 0x0, 21); -static IMX_CLK_GATE(audio_pll2_out, { &audio_pll2_bypass }, CCM_ANALOG_BASE, 0x8, 21); -static IMX_CLK_GATE(video_pll1_out, { &video_pll1_bypass }, CCM_ANALOG_BASE, 0x10, 21); +static IMX_CLK_GATE(arm_pll_out, { &arm_pll_bypass }, CCM_ANALOG_BASE, 0x28, + 21); +static IMX_CLK_GATE(gpu_pll_out, { &gpu_pll_bypass }, CCM_ANALOG_BASE, 0x18, + 21); +static IMX_CLK_GATE(vpu_pll_out, { &vpu_pll_bypass }, CCM_ANALOG_BASE, 0x20, + 21); +static IMX_CLK_GATE(audio_pll1_out, { &audio_pll1_bypass }, CCM_ANALOG_BASE, + 0x0, 21); +static IMX_CLK_GATE(audio_pll2_out, { &audio_pll2_bypass }, CCM_ANALOG_BASE, + 0x8, 21); +static IMX_CLK_GATE(video_pll1_out, { &video_pll1_bypass }, CCM_ANALOG_BASE, + 0x10, 21); static IMX_CLK_FIXED(sys1_pll_out, 800000000); static IMX_CLK_FIXED(sys2_pll_out, 1000000000); -static IMX_CLK_SSCG_PLL(sys3_pll_out, sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 0, CCM_ANALOG_BASE, 0x48, - CLK_IS_CRITICAL); -static IMX_CLK_SSCG_PLL(dram_pll_out, dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, CCM_ANALOG_BASE, 0x60, - CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE); -static IMX_CLK_SSCG_PLL(video2_pll_out, video2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, CCM_ANALOG_BASE, - 0x54, 0); +static IMX_CLK_SSCG_PLL(sys3_pll_out, sys3_pll_out_sels, + ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 0, CCM_ANALOG_BASE, + 0x48, CLK_IS_CRITICAL); +static IMX_CLK_SSCG_PLL(dram_pll_out, dram_pll_out_sels, + ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, CCM_ANALOG_BASE, + 0x60, CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE); +static IMX_CLK_SSCG_PLL(video2_pll_out, video2_pll_out_sels, + ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, + CCM_ANALOG_BASE, 0x54, 0); /* SYS PLL1 fixed output */ static IMX_CLK_FIXED_FACTOR(sys1_pll_40m, { &sys1_pll_out }, 1, 20); @@ -2457,40 +2487,56 @@ static IMX_CLK_FIXED_FACTOR(sys2_pll_333m, { &sys2_pll_out }, 1, 3); static IMX_CLK_FIXED_FACTOR(sys2_pll_500m, { &sys2_pll_out }, 1, 2); static IMX_CLK_FIXED_FACTOR(sys2_pll_1000m, { &sys2_pll_out }, 1, 1); -static IMX_CLK_DIV(audio_pll1_out_monitor, { &audio_pll1_bypass }, CCM_ANALOG_BASE, 0x78, 0, 3); -static IMX_CLK_DIV(audio_pll2_out_monitor, { &audio_pll2_bypass }, CCM_ANALOG_BASE, 0x78, 4, 3); -static IMX_CLK_DIV(video_pll1_out_monitor, { &video_pll1_bypass }, CCM_ANALOG_BASE, 0x78, 8, 3); -static IMX_CLK_DIV(gpu_pll_out_monitor, { &gpu_pll_bypass }, CCM_ANALOG_BASE, 0x78, 12, 3); -static IMX_CLK_DIV(vpu_pll_out_monitor, { &vpu_pll_bypass }, CCM_ANALOG_BASE, 0x78, 16, 3); -static IMX_CLK_DIV(arm_pll_out_monitor, { &arm_pll_bypass }, CCM_ANALOG_BASE, 0x78, 20, 3); -static IMX_CLK_DIV(sys_pll1_out_monitor, { &sys1_pll_out }, CCM_ANALOG_BASE, 0x7c, 0, 3); -static IMX_CLK_DIV(sys_pll2_out_monitor, { &sys2_pll_out }, CCM_ANALOG_BASE, 0x7c, 4, 3); -static IMX_CLK_DIV(sys_pll3_out_monitor, { &sys3_pll_out }, CCM_ANALOG_BASE, 0x7c, 8, 3); -static IMX_CLK_DIV(dram_pll_out_monitor, { &dram_pll_out }, CCM_ANALOG_BASE, 0x7c, 12, 3); -static IMX_CLK_DIV(video_pll2_out_monitor, { &video2_pll_out }, CCM_ANALOG_BASE, 0x7c, 16, 3); -static IMX_CLK_MUX(pllout_monitor_sel, CCM_ANALOG_BASE, 0x74, 0, 4, pllout_monitor_sels, - ARRAY_SIZE(pllout_monitor_sels)); -static IMX_CLK_GATE(pllout_monitor_clk2, { &pllout_monitor_sel }, CCM_ANALOG_BASE, 0x74, 4); +static IMX_CLK_DIV(audio_pll1_out_monitor, { &audio_pll1_bypass }, + CCM_ANALOG_BASE, 0x78, 0, 3); +static IMX_CLK_DIV(audio_pll2_out_monitor, { &audio_pll2_bypass }, + CCM_ANALOG_BASE, 0x78, 4, 3); +static IMX_CLK_DIV(video_pll1_out_monitor, { &video_pll1_bypass }, + CCM_ANALOG_BASE, 0x78, 8, 3); +static IMX_CLK_DIV(gpu_pll_out_monitor, { &gpu_pll_bypass }, CCM_ANALOG_BASE, + 0x78, 12, 3); +static IMX_CLK_DIV(vpu_pll_out_monitor, { &vpu_pll_bypass }, CCM_ANALOG_BASE, + 0x78, 16, 3); +static IMX_CLK_DIV(arm_pll_out_monitor, { &arm_pll_bypass }, CCM_ANALOG_BASE, + 0x78, 20, 3); +static IMX_CLK_DIV(sys_pll1_out_monitor, { &sys1_pll_out }, CCM_ANALOG_BASE, + 0x7c, 0, 3); +static IMX_CLK_DIV(sys_pll2_out_monitor, { &sys2_pll_out }, CCM_ANALOG_BASE, + 0x7c, 4, 3); +static IMX_CLK_DIV(sys_pll3_out_monitor, { &sys3_pll_out }, CCM_ANALOG_BASE, + 0x7c, 8, 3); +static IMX_CLK_DIV(dram_pll_out_monitor, { &dram_pll_out }, CCM_ANALOG_BASE, + 0x7c, 12, 3); +static IMX_CLK_DIV(video_pll2_out_monitor, { &video2_pll_out }, CCM_ANALOG_BASE, + 0x7c, 16, 3); +static IMX_CLK_MUX(pllout_monitor_sel, CCM_ANALOG_BASE, 0x74, 0, 4, + pllout_monitor_sels, ARRAY_SIZE(pllout_monitor_sels)); +static IMX_CLK_GATE(pllout_monitor_clk2, { &pllout_monitor_sel }, + CCM_ANALOG_BASE, 0x74, 4); /* CORE */ static IMX_CLK_COMPOSITE_CORE(arm_a53_div, imx8mq_a53_sels, CCM_BASE, 0x8000); -static IMX_CLK_COMPOSITE_CORE(arm_m4_core, imx8mq_arm_m4_sels, CCM_BASE, 0x8080); +static IMX_CLK_COMPOSITE_CORE(arm_m4_core, imx8mq_arm_m4_sels, CCM_BASE, + 0x8080); static IMX_CLK_COMPOSITE_CORE(vpu_core, imx8mq_vpu_sels, CCM_BASE, 0x8100); static IMX_CLK_COMPOSITE_CORE(gpu_core, imx8mq_gpu_core_sels, CCM_BASE, 0x8180); static IMX_CLK_COMPOSITE(gpu_shader, imx8mq_gpu_shader_sels, CCM_BASE, 0x8200); /* CORE SEL */ -static IMX_CLK_MUX2(arm_a53_core, CCM_BASE, 0x9880, 24, 1, imx8mq_a53_core_sels, ARRAY_SIZE(imx8mq_a53_core_sels)); +static IMX_CLK_MUX2(arm_a53_core, CCM_BASE, 0x9880, 24, 1, imx8mq_a53_core_sels, + ARRAY_SIZE(imx8mq_a53_core_sels)); /* BUS */ static IMX_CLK_COMPOSITE_BUS(main_axi, imx8mq_main_axi_sels, CCM_BASE, 0x8800); static IMX_CLK_COMPOSITE_BUS(enet_axi, imx8mq_enet_axi_sels, CCM_BASE, 0x8880); -static IMX_CLK_COMPOSITE_BUS(nand_usdhc_bus, imx8mq_nand_usdhc_sels, CCM_BASE, 0x8900); +static IMX_CLK_COMPOSITE_BUS(nand_usdhc_bus, imx8mq_nand_usdhc_sels, CCM_BASE, + 0x8900); static IMX_CLK_COMPOSITE_BUS(vpu_bus, imx8mq_vpu_bus_sels, CCM_BASE, 0x8980); static IMX_CLK_COMPOSITE_BUS(disp_axi, imx8mq_disp_axi_sels, CCM_BASE, 0x8a00); static IMX_CLK_COMPOSITE_BUS(disp_apb, imx8mq_disp_apb_sels, CCM_BASE, 0x8a80); -static IMX_CLK_COMPOSITE_BUS(disp_rtrm, imx8mq_disp_rtrm_sels, CCM_BASE, 0x8b00); +static IMX_CLK_COMPOSITE_BUS(disp_rtrm, imx8mq_disp_rtrm_sels, CCM_BASE, + 0x8b00); static IMX_CLK_COMPOSITE_BUS(usb_bus, imx8mq_usb_bus_sels, CCM_BASE, 0x8b80); static IMX_CLK_COMPOSITE_BUS(gpu_axi, imx8mq_gpu_axi_sels, CCM_BASE, 0x8c00); static IMX_CLK_COMPOSITE_BUS(gpu_ahb, imx8mq_gpu_ahb_sels, CCM_BASE, 0x8c80); @@ -2500,7 +2546,8 @@ static IMX_CLK_COMPOSITE_BUS(noc_apb, imx8mq_noc_apb_sels, CCM_BASE, 0x8d80); /* AHB */ /* AHB clock is used by the AHB bus therefore marked as critical */ static IMX_CLK_COMPOSITE_BUS(ahb, imx8mq_ahb_sels, CCM_BASE, 0x9000); -static IMX_CLK_COMPOSITE_BUS(audio_ahb, imx8mq_audio_ahb_sels, CCM_BASE, 0x9100); +static IMX_CLK_COMPOSITE_BUS(audio_ahb, imx8mq_audio_ahb_sels, CCM_BASE, + 0x9100); /* IPG */ static IMX_CLK_DIV2(ipg_root, { &ahb }, CCM_BASE, 0x9080, 0, 1); @@ -2511,21 +2558,26 @@ static IMX_CLK_DIV2(ipg_audio_root, { &audio_ahb }, CCM_BASE, 0x9180, 0, 1); * The fw_managed helper sets GET_RATE_NOCACHE and clears SET_PARENT_GATE * as div value should always be read from hardware */ -static IMX_CLK_MUX2_FLAGS(dram_core_clk, CCM_BASE, 0x9800, 24, 1, imx8mq_dram_core_sels, +static IMX_CLK_MUX2_FLAGS(dram_core_clk, CCM_BASE, 0x9800, 24, 1, + imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels), CLK_IS_CRITICAL); -static IMX_CLK_COMPOSITE_FW_MANAGED(dram_alt, imx8mq_dram_alt_sels, CCM_BASE, 0xa000); -static IMX_CLK_COMPOSITE_FW_MANAGED_CRITICAL(dram_apb, imx8mq_dram_apb_sels, CCM_BASE, 0xa080); +static IMX_CLK_COMPOSITE_FW_MANAGED(dram_alt, imx8mq_dram_alt_sels, CCM_BASE, + 0xa000); +static IMX_CLK_COMPOSITE_FW_MANAGED_CRITICAL(dram_apb, imx8mq_dram_apb_sels, + CCM_BASE, 0xa080); /* IP */ static IMX_CLK_COMPOSITE(vpu_g1, imx8mq_vpu_g1_sels, CCM_BASE, 0xa100); static IMX_CLK_COMPOSITE(vpu_g2, imx8mq_vpu_g2_sels, CCM_BASE, 0xa180); static IMX_CLK_COMPOSITE(disp_dtrc, imx8mq_disp_dtrc_sels, CCM_BASE, 0xa200); -static IMX_CLK_COMPOSITE(disp_dc8000, imx8mq_disp_dc8000_sels, CCM_BASE, 0xa280); +static IMX_CLK_COMPOSITE(disp_dc8000, imx8mq_disp_dc8000_sels, CCM_BASE, + 0xa280); static IMX_CLK_COMPOSITE(pcie1_ctrl, imx8mq_pcie1_ctrl_sels, CCM_BASE, 0xa300); static IMX_CLK_COMPOSITE(pcie1_phy, imx8mq_pcie1_phy_sels, CCM_BASE, 0xa380); static IMX_CLK_COMPOSITE(pcie1_aux, imx8mq_pcie1_aux_sels, CCM_BASE, 0xa400); static IMX_CLK_COMPOSITE(dc_pixel, imx8mq_dc_pixel_sels, CCM_BASE, 0xa480); -static IMX_CLK_COMPOSITE(lcdif_pixel, imx8mq_lcdif_pixel_sels, CCM_BASE, 0xa500); +static IMX_CLK_COMPOSITE(lcdif_pixel, imx8mq_lcdif_pixel_sels, CCM_BASE, + 0xa500); static IMX_CLK_COMPOSITE(sai1, imx8mq_sai1_sels, CCM_BASE, 0xa580); static IMX_CLK_COMPOSITE(sai2, imx8mq_sai2_sels, CCM_BASE, 0xa600); static IMX_CLK_COMPOSITE(sai3, imx8mq_sai3_sels, CCM_BASE, 0xa680); @@ -2604,20 +2656,34 @@ static IMX_CLK_GATE4(pwm3_root_clk, { &pwm3 }, CCM_BASE, 0x42a0, 0); static IMX_CLK_GATE4(pwm4_root_clk, { &pwm4 }, CCM_BASE, 0x42b0, 0); static IMX_CLK_GATE4(qspi_root_clk, { &qspi }, CCM_BASE, 0x42f0, 0); -static IMX_CLK_GATE2_SHARED2(nand_root_clk, { &nand }, CCM_BASE, 0x4300, 0, &share_count_nand); -static IMX_CLK_GATE2_SHARED2(nand_usdhc_rawnand_clk, { &nand_usdhc_bus }, CCM_BASE, 0x4300, 0, &share_count_nand); -static IMX_CLK_GATE2_SHARED2(sai1_root_clk, { &sai1 }, CCM_BASE, 0x4330, 0, &share_count_sai1); -static IMX_CLK_GATE2_SHARED2(sai1_ipg_clk, { &ipg_audio_root }, CCM_BASE, 0x4330, 0, &share_count_sai1); -static IMX_CLK_GATE2_SHARED2(sai2_root_clk, { &sai2 }, CCM_BASE, 0x4340, 0, &share_count_sai2); -static IMX_CLK_GATE2_SHARED2(sai2_ipg_clk, { &ipg_root }, CCM_BASE, 0x4340, 0, &share_count_sai2); -static IMX_CLK_GATE2_SHARED2(sai3_root_clk, { &sai3 }, CCM_BASE, 0x4350, 0, &share_count_sai3); -static IMX_CLK_GATE2_SHARED2(sai3_ipg_clk, { &ipg_root }, CCM_BASE, 0x4350, 0, &share_count_sai3); -static IMX_CLK_GATE2_SHARED2(sai4_root_clk, { &sai4 }, CCM_BASE, 0x4360, 0, &share_count_sai4); -static IMX_CLK_GATE2_SHARED2(sai4_ipg_clk, { &ipg_audio_root }, CCM_BASE, 0x4360, 0, &share_count_sai4); -static IMX_CLK_GATE2_SHARED2(sai5_root_clk, { &sai5 }, CCM_BASE, 0x4370, 0, &share_count_sai5); -static IMX_CLK_GATE2_SHARED2(sai5_ipg_clk, { &ipg_audio_root }, CCM_BASE, 0x4370, 0, &share_count_sai5); -static IMX_CLK_GATE2_SHARED2(sai6_root_clk, { &sai6 }, CCM_BASE, 0x4380, 0, &share_count_sai6); -static IMX_CLK_GATE2_SHARED2(sai6_ipg_clk, { &ipg_audio_root }, CCM_BASE, 0x4380, 0, &share_count_sai6); +static IMX_CLK_GATE2_SHARED2(nand_root_clk, { &nand }, CCM_BASE, 0x4300, 0, + &share_count_nand); +static IMX_CLK_GATE2_SHARED2(nand_usdhc_rawnand_clk, { &nand_usdhc_bus }, + CCM_BASE, 0x4300, 0, &share_count_nand); +static IMX_CLK_GATE2_SHARED2(sai1_root_clk, { &sai1 }, CCM_BASE, 0x4330, 0, + &share_count_sai1); +static IMX_CLK_GATE2_SHARED2(sai1_ipg_clk, { &ipg_audio_root }, CCM_BASE, + 0x4330, 0, &share_count_sai1); +static IMX_CLK_GATE2_SHARED2(sai2_root_clk, { &sai2 }, CCM_BASE, 0x4340, 0, + &share_count_sai2); +static IMX_CLK_GATE2_SHARED2(sai2_ipg_clk, { &ipg_root }, CCM_BASE, 0x4340, 0, + &share_count_sai2); +static IMX_CLK_GATE2_SHARED2(sai3_root_clk, { &sai3 }, CCM_BASE, 0x4350, 0, + &share_count_sai3); +static IMX_CLK_GATE2_SHARED2(sai3_ipg_clk, { &ipg_root }, CCM_BASE, 0x4350, 0, + &share_count_sai3); +static IMX_CLK_GATE2_SHARED2(sai4_root_clk, { &sai4 }, CCM_BASE, 0x4360, 0, + &share_count_sai4); +static IMX_CLK_GATE2_SHARED2(sai4_ipg_clk, { &ipg_audio_root }, CCM_BASE, + 0x4360, 0, &share_count_sai4); +static IMX_CLK_GATE2_SHARED2(sai5_root_clk, { &sai5 }, CCM_BASE, 0x4370, 0, + &share_count_sai5); +static IMX_CLK_GATE2_SHARED2(sai5_ipg_clk, { &ipg_audio_root }, CCM_BASE, + 0x4370, 0, &share_count_sai5); +static IMX_CLK_GATE2_SHARED2(sai6_root_clk, { &sai6 }, CCM_BASE, 0x4380, 0, + &share_count_sai6); +static IMX_CLK_GATE2_SHARED2(sai6_ipg_clk, { &ipg_audio_root }, CCM_BASE, + 0x4380, 0, &share_count_sai6); static IMX_CLK_GATE4(uart1_root_clk, { &uart1 }, CCM_BASE, 0x4490, 0); static IMX_CLK_GATE4(uart2_root_clk, { &uart2 }, CCM_BASE, 0x44a0, 0); static IMX_CLK_GATE4(uart3_root_clk, { &uart3 }, CCM_BASE, 0x44b0, 0); @@ -2636,10 +2702,14 @@ static IMX_CLK_GATE2_FLAGS(vpu_g1_root_clk, { &vpu_g1 }, CCM_BASE, 0x4560, 0, static IMX_CLK_GATE4(gpu_root_clk, { &gpu_core }, CCM_BASE, 0x4570, 0); static IMX_CLK_GATE2_FLAGS(vpu_g2_root_clk, { &vpu_g2 }, CCM_BASE, 0x45a0, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); -static IMX_CLK_GATE2_SHARED2(disp_root_clk, { &disp_dc8000 }, CCM_BASE, 0x45d0, 0, &share_count_dcss); -static IMX_CLK_GATE2_SHARED2(disp_axi_root_clk, { &disp_axi }, CCM_BASE, 0x45d0, 0, &share_count_dcss); -static IMX_CLK_GATE2_SHARED2(disp_apb_root_clk, { &disp_apb }, CCM_BASE, 0x45d0, 0, &share_count_dcss); -static IMX_CLK_GATE2_SHARED2(disp_rtrm_root_clk, { &disp_rtrm }, CCM_BASE, 0x45d0, 0, &share_count_dcss); +static IMX_CLK_GATE2_SHARED2(disp_root_clk, { &disp_dc8000 }, CCM_BASE, 0x45d0, + 0, &share_count_dcss); +static IMX_CLK_GATE2_SHARED2(disp_axi_root_clk, { &disp_axi }, CCM_BASE, 0x45d0, + 0, &share_count_dcss); +static IMX_CLK_GATE2_SHARED2(disp_apb_root_clk, { &disp_apb }, CCM_BASE, 0x45d0, + 0, &share_count_dcss); +static IMX_CLK_GATE2_SHARED2(disp_rtrm_root_clk, { &disp_rtrm }, CCM_BASE, + 0x45d0, 0, &share_count_dcss); static IMX_CLK_GATE4(tmu_root_clk, { &ipg_root }, CCM_BASE, 0x4620, 0); static IMX_CLK_GATE2_FLAGS(vpu_dec_root_clk, { &vpu_bus }, CCM_BASE, 0x4630, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c index 12eda8131..d17b3cae9 100644 --- a/drivers/clk/imx/clk.c +++ b/drivers/clk/imx/clk.c @@ -83,7 +83,8 @@ const struct clk *get_parent(const struct clk *clk) if (parent_data.clk) { return parent_data.clk; - } else if (parent_data.name) { + } + if (parent_data.name) { return get_clk_by_name(parent_data.name); } } @@ -169,7 +170,8 @@ uint32_t clk_set_rate(struct clk *clk, uint64_t req_rate, uint64_t *rate) if (clk->hw.init->ops->set_rate) { *rate = clk->hw.init->ops->set_rate(clk, req_rate, prate); return 0; - } else if (pclk && pclk->hw.init->ops->set_rate) { + } + if (pclk && pclk->hw.init->ops->set_rate) { const struct clk *ppclk = get_parent(pclk); uint64_t pprate = 0; uint32_t err = clk_get_rate(ppclk, &pprate); @@ -195,9 +197,11 @@ int clk_msr_stat() if (clk_list[i]) { err = clk_get_rate(clk_list[i], &rate); if (err) { - LOG_DRIVER_ERR("Failed to get rate of %s: -%u\n", clk_list[i]->hw.init->name, err); + LOG_DRIVER_ERR("Failed to get rate of %s: -%u\n", + clk_list[i]->hw.init->name, err); } - LOG_DRIVER("[%4d][%10luHz] %s\n", i, rate, clk_list[i]->hw.init->name); + LOG_DRIVER("[%4d][%10luHz] %s\n", i, rate, + clk_list[i]->hw.init->name); } } LOG_DRIVER("-----------------------------\n"); @@ -292,8 +296,8 @@ microkit_msginfo protected(microkit_channel ch, microkit_msginfo msginfo) break; } default: - LOG_DRIVER_ERR("Unknown request %lu to clockk driver from channel %u\n", microkit_msginfo_get_label(msginfo), - ch); + LOG_DRIVER_ERR("Unknown request %lu to clockk driver from channel %u\n", + microkit_msginfo_get_label(msginfo), ch); err = CLK_UNKNOWN_REQ; } return microkit_msginfo_new(err, 0); diff --git a/drivers/clk/imx/clk_driver.mk b/drivers/clk/imx/clk_driver.mk index bfb9012fd..b4d906d8e 100644 --- a/drivers/clk/imx/clk_driver.mk +++ b/drivers/clk/imx/clk_driver.mk @@ -24,7 +24,7 @@ $(CLK_DRIVER_OBJS): ${CLK_DRIVER_COMMON_DIR}/*.c ${CLK_DRIVER_DIR}/*.c $(CLK_CON -I${UART_DRIVER_DIR}/include \ -I${CLK_DRIVER_COMMON_DIR} $^ -$(CLK_CONFIG_HEADER): $(DTS_FILE) +$(CLK_CONFIG_HEADER): $(DTS_FILE) $(CLK_DRIVER_COMMON_DIR)/create_clk_config.py $(PYTHON) $(CLK_DRIVER_COMMON_DIR)/create_clk_config.py $(DTS_FILE) $(BUILD_DIR) clean:: diff --git a/drivers/clk/imx/include/clk-imx.h b/drivers/clk/imx/include/clk-imx.h index 56af8b030..66d02876d 100644 --- a/drivers/clk/imx/include/clk-imx.h +++ b/drivers/clk/imx/include/clk-imx.h @@ -1,4 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2010-2011 Canonical Ltd + * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd + * + * Gated clock implementation + * Source: https://github.com/torvalds/linux/blob/ + * cfaaa7d010d1fc58f9717fcc8591201e741d2d49/drivers/clk/imx/clk-gate2.c + */ + +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2018 NXP. + * + * Source: https://github.com/torvalds/linux/blob/ + * cfaaa7d010d1fc58f9717fcc8591201e741d2d49/drivers/clk/imx/clk-frac-pll.c + */ + +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright 2018 NXP. + * + * Source: https://github.com/torvalds/linux/blob/ + * cfaaa7d010d1fc58f9717fcc8591201e741d2d49/drivers/clk/imx/clk-sscg-pll.c + */ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2018 NXP + * + * Source: https://github.com/torvalds/linux/blob/ + * cfaaa7d010d1fc58f9717fcc8591201e741d2d49/drivers/clk/imx/clk-composite-8m.c + */ #pragma once #include @@ -122,8 +154,8 @@ struct clk _name = { \ #define IMX_CLK_FIXED(_name, _rate) \ IMX_CLK_SOURCE(_name, _rate) -#define IMX_CLK_MUX_FLAGS(_name, _base, _offset, _shift, _width, \ - _parent_data, _num_parents, _init_flags) \ +#define IMX_CLK_MUX_FLAGS(_name, _base, _offset, _shift, _width, _parent_data, \ + _num_parents, _init_flags) \ struct clk _name = { \ .base = (_base), \ .data = &(struct clk_mux_data) { \ @@ -140,23 +172,23 @@ struct clk _name = { \ }, \ } -#define IMX_CLK_MUX(_name, _base, _offset, _shift, _width, \ - _parent_data,_num_parents) \ +#define IMX_CLK_MUX(_name, _base, _offset, _shift, _width, _parent_data, \ + _num_parents) \ IMX_CLK_MUX_FLAGS(_name, _base, _offset, _shift, _width, \ _parent_data, _num_parents, 0) -#define IMX_CLK_MUX2(_name, _base, _offset, _shift, _width, \ - _parent_data, _num_parents) \ +#define IMX_CLK_MUX2(_name, _base, _offset, _shift, _width, _parent_data, \ + _num_parents) \ IMX_CLK_MUX_FLAGS(_name, _base, _offset, _shift, _width, \ _parent_data, _num_parents, CLK_OPS_PARENT_ENABLE) -#define IMX_CLK_MUX2_FLAGS(_name, _base, _offset, _shift, _width, \ +#define IMX_CLK_MUX2_FLAGS(_name, _base, _offset, _shift, _width, \ _parent_data, _num_parents, _flags) \ IMX_CLK_MUX_FLAGS(_name, _base, _offset, _shift, _width, \ _parent_data, _num_parents, _flags | CLK_OPS_PARENT_ENABLE) -#define IMX_CLK_DIV_FLAGS(_name, _parent_clks, _base, \ - _offset, _shift, _width, _flags) \ +#define IMX_CLK_DIV_FLAGS(_name, _parent_clks, _base, _offset, _shift, _width, \ + _flags) \ struct clk _name = { \ .base = (_base), \ .data = &(struct clk_div_data) { \ @@ -212,8 +244,7 @@ struct clk _name = { \ }, \ } -#define IMX_CLK_GATE2_FLAGS(_name, _parent_clks, _base, _offset, \ - _shift, _flags) \ +#define IMX_CLK_GATE2_FLAGS(_name, _parent_clks, _base, _offset, _shift, _flags) \ struct clk _name = { \ .base = (_base), \ .data = &(struct clk_gate_data) { \ @@ -228,18 +259,18 @@ struct clk _name = { \ }, \ } -#define IMX_CLK_GATE2_SHARED2(_name, _parent_clks, _base, _offset, \ - _shift, _shared_count) \ +#define IMX_CLK_GATE2_SHARED2(_name, _parent_clks, _base, _offset, _shift, \ + _shared_count) \ IMX_CLK_GATE2_FLAGS(_name, _parent_clks, _base, _offset, _shift, 0) -#define IMX_CLK_GATE4(_name, _parent_clks, _base, _offset, _shift) \ +#define IMX_CLK_GATE4(_name, _parent_clks, _base, _offset, _shift) \ IMX_CLK_GATE2_FLAGS(_name, _parent_clks, _base, _offset, _shift, 0) #define IMX_CLK_FIXED_FACTOR(_name, _parent_clks, _mult, _div) \ CLK_FIXED_FACTOR(_name, _mult, _div, 0, _parent_clks, 1, CLK_SET_RATE_PARENT) -#define IMX_CLK_SSCG_PLL(_name, _parent_data, _num_parents, _parent,\ - _bypass1, _bypass2, _base, _offset, _flags)\ +#define IMX_CLK_SSCG_PLL(_name, _parent_data, _num_parents, _parent, _bypass1, \ + _bypass2, _base, _offset, _flags) \ struct clk _name = { \ .base = (_base), \ .data = &(struct clk_sscg_pll_data) { \ @@ -303,8 +334,7 @@ struct clk _name = { \ }, \ } -#define IMX_CLK_COMPOSITE_FLAGS(_name, _parent_data, _base, _offset,\ - _flags) \ +#define IMX_CLK_COMPOSITE_FLAGS(_name, _parent_data, _base, _offset, _flags) \ struct clk _name = { \ .base = (_base), \ .data = &(struct clk_common_slice_data) { \ @@ -338,9 +368,9 @@ IMX_CLK_COMPOSITE_FLAGS(_name, _parent_data, _base, _offset, \ (CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE \ | CLK_GET_RATE_NOCACHE)) -#define IMX_CLK_COMPOSITE_FW_MANAGED_CRITICAL(_name, _parent_data, \ - _base, _offset) \ -IMX_CLK_COMPOSITE_FLAGS(_name, _parent_data, _base, _offset, \ - (CLK_SET_RATE_NO_REPARENT | \ - CLK_OPS_PARENT_ENABLE | \ +#define IMX_CLK_COMPOSITE_FW_MANAGED_CRITICAL(_name, _parent_data, _base, \ + _offset) \ +IMX_CLK_COMPOSITE_FLAGS(_name, _parent_data, _base, _offset, \ + (CLK_SET_RATE_NO_REPARENT | \ + CLK_OPS_PARENT_ENABLE | \ CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL)) diff --git a/drivers/clk/meson/clk-measure.c b/drivers/clk/meson/clk-measure.c index 028448040..5513fa288 100644 --- a/drivers/clk/meson/clk-measure.c +++ b/drivers/clk/meson/clk-measure.c @@ -185,14 +185,14 @@ unsigned long clk_msr(unsigned long clk_mux) /* Disable interrupts */ *mclk_reg0 = regval; - regval |= duration; /* 64uS is enough for measure the frequence? */ + regval |= duration; /* 64uS is enough for measure the frequence? */ *mclk_reg0 = regval; - regval |= (clk_mux << 20); /* Select MUX */ + regval |= (clk_mux << 20); /* Select MUX */ *mclk_reg0 = regval; - regval |= (1 << 19); /* enable the clock */ - regval |= (1 << 16); /* enable measuring */ + regval |= (1 << 19); /* enable the clock */ + regval |= (1 << 16); /* enable measuring */ *mclk_reg0 = regval; regval = *mclk_reg0; @@ -202,7 +202,7 @@ unsigned long clk_msr(unsigned long clk_mux) /* TODO: Check the busy bit */ /* if (regval & (1 << 31)) */ - /* sddf_dprintf("CLK | ERR: The clock measure logic is busy\n"); */ + /* sddf_dprintf("CLK | ERR: The clock measure logic is busy\n"); */ /* Wait for the measurement to be done */ while (true) { @@ -213,15 +213,16 @@ unsigned long clk_msr(unsigned long clk_mux) } /* TODO: Could be optimised via timeouts */ /* if (sleep_us) */ - /* udelay(sleep_us); */ + /* udelay(sleep_us); */ } - regval &= ~(1 << 16); /* disable measuring */ + regval &= ~(1 << 16); /* disable measuring */ *mclk_reg0 = regval; uint32_t msr_val = *mclk_reg2; - return DIV_ROUND_CLOSEST_ULL((msr_val & ((1 << 19) - 1)) * 1000000ULL, duration); + return DIV_ROUND_CLOSEST_ULL((msr_val & ((1 << 19) - 1)) * 1000000ULL, + duration); } const char *const *get_msr_clk_list(void) diff --git a/drivers/clk/meson/clk-meson.c b/drivers/clk/meson/clk-meson.c index 9799d6ad5..990cc2242 100644 --- a/drivers/clk/meson/clk-meson.c +++ b/drivers/clk/meson/clk-meson.c @@ -93,12 +93,12 @@ void delay_us(uint32_t us) } } -int regmap_multi_reg_write(uint64_t base, const struct reg_sequence *regs, int num_regs) +int regmap_multi_reg_write(uint64_t base, const struct reg_sequence *regs, + int num_regs) { int i; for (i = 0; i < num_regs; i++) { reg_write(base, regs[i].reg, regs[i].def); - /* TODO: delay is needed */ if (regs[i].delay_us) { delay_us(regs[i].delay_us); } @@ -109,32 +109,41 @@ int regmap_multi_reg_write(uint64_t base, const struct reg_sequence *regs, int n static void meson_clk_pll_init(struct clk *clk) { struct meson_clk_pll_data *data = (struct meson_clk_pll_data *)(clk->data); - if ((data->flags & CLK_MESON_PLL_NOINIT_ENABLED) && clk->hw.init->ops->is_enabled(clk)) + if ((data->flags & CLK_MESON_PLL_NOINIT_ENABLED) + && clk->hw.init->ops->is_enabled(clk)) return; if (data->init_count) { /* Set the reset bit */ - regmap_update_bits(clk->base, data->rst.reg_off, data->rst.shift, data->rst.width, 1); + regmap_update_bits(clk->base, data->rst.reg_off, data->rst.shift, + data->rst.width, 1); regmap_multi_reg_write(clk->base, data->init_regs, data->init_count); /* Clear the reset bit */ - regmap_update_bits(clk->base, data->rst.reg_off, data->rst.shift, data->rst.width, 0); + regmap_update_bits(clk->base, data->rst.reg_off, data->rst.shift, + data->rst.width, 0); } } -static unsigned long meson_clk_pll_recalc_rate(const struct clk *clk, unsigned long parent_rate) +static unsigned long meson_clk_pll_recalc_rate(const struct clk *clk, + unsigned long parent_rate) { struct meson_clk_pll_data *data = (struct meson_clk_pll_data *)(clk->data); uint32_t n, m, frac; - n = regmap_read_bits(clk->base, data->n.reg_off, data->n.shift, data->n.width); + n = regmap_read_bits(clk->base, data->n.reg_off, data->n.shift, + data->n.width); if (n == 0) return 0; - m = regmap_read_bits(clk->base, data->m.reg_off, data->m.shift, data->m.width); + m = regmap_read_bits(clk->base, data->m.reg_off, data->m.shift, + data->m.width); - frac = data->frac.width ? regmap_read_bits(clk->base, data->frac.reg_off, data->frac.shift, data->frac.width) : 0; + frac = data->frac.width + ? regmap_read_bits(clk->base, data->frac.reg_off, data->frac.shift, + data->frac.width) + : 0; uint64_t rate = (uint64_t)parent_rate * m; @@ -154,7 +163,8 @@ static int meson_clk_pll_is_enabled(struct clk *clk) return 0; } - if (!meson_parm_read(clk->base, data->en) || !meson_parm_read(clk->base, data->l)) { + if (!meson_parm_read(clk->base, data->en) + || !meson_parm_read(clk->base, data->l)) { return 0; } @@ -168,11 +178,15 @@ static int meson_clk_pll_enable(struct clk *clk) if (meson_clk_pll_is_enabled(clk)) return 0; - regmap_update_bits(clk->base, data->rst.reg_off, data->rst.shift, data->rst.width, 1); - regmap_update_bits(clk->base, data->en.reg_off, data->en.shift, data->en.width, 1); - regmap_update_bits(clk->base, data->rst.reg_off, data->rst.shift, data->rst.width, 1); + regmap_update_bits(clk->base, data->rst.reg_off, data->rst.shift, + data->rst.width, 1); + regmap_update_bits(clk->base, data->en.reg_off, data->en.shift, + data->en.width, 1); + regmap_update_bits(clk->base, data->rst.reg_off, data->rst.shift, + data->rst.width, 1); - regmap_update_bits(clk->base, data->current_en.reg_off, data->current_en.shift, data->current_en.width, 1); + regmap_update_bits(clk->base, data->current_en.reg_off, + data->current_en.shift, data->current_en.width, 1); return 0; } @@ -180,18 +194,22 @@ static int meson_clk_pll_disable(struct clk *clk) { struct meson_clk_pll_data *data = (struct meson_clk_pll_data *)(clk->data); - regmap_update_bits(clk->base, data->rst.reg_off, data->rst.shift, data->rst.width, 1); - regmap_update_bits(clk->base, data->en.reg_off, data->en.shift, data->en.width, 0); + regmap_update_bits(clk->base, data->rst.reg_off, data->rst.shift, + data->rst.width, 1); + regmap_update_bits(clk->base, data->en.reg_off, data->en.shift, + data->en.width, 0); return 0; } -const struct clk_ops meson_clk_pll_ops = { .init = meson_clk_pll_init, - .recalc_rate = meson_clk_pll_recalc_rate, +const struct clk_ops meson_clk_pll_ops = { + .init = meson_clk_pll_init, + .recalc_rate = meson_clk_pll_recalc_rate, /* .determine_rate = meson_clk_pll_determine_rate, */ /* .set_rate = meson_clk_pll_set_rate, */ - .is_enabled = meson_clk_pll_is_enabled, - .enable = meson_clk_pll_enable, - .disable = meson_clk_pll_disable }; + .is_enabled = meson_clk_pll_is_enabled, + .enable = meson_clk_pll_enable, + .disable = meson_clk_pll_disable +}; const struct clk_ops meson_clk_pll_ro_ops = { .recalc_rate = meson_clk_pll_recalc_rate, @@ -202,13 +220,17 @@ const struct clk_ops meson_clk_pll_ro_ops = { #define N2_MIN 4 #define N2_MAX 511 -static unsigned long mpll_recalc_rate(const struct clk *clk, unsigned long prate) +static unsigned long mpll_recalc_rate(const struct clk *clk, + unsigned long prate) { - struct meson_clk_mpll_data *data = (struct meson_clk_mpll_data *)(clk->data); + struct meson_clk_mpll_data *data = + (struct meson_clk_mpll_data *)(clk->data); uint32_t sdm, n2; - sdm = regmap_read_bits(clk->base, data->sdm.reg_off, data->sdm.shift, data->sdm.width); - n2 = regmap_read_bits(clk->base, data->n2.reg_off, data->n2.shift, data->n2.width); + sdm = regmap_read_bits(clk->base, data->sdm.reg_off, data->sdm.shift, + data->sdm.width); + n2 = regmap_read_bits(clk->base, data->n2.reg_off, data->n2.shift, + data->n2.width); uint32_t divisor = (SDM_DEN * n2) + sdm; if (n2 < N2_MIN) @@ -217,9 +239,11 @@ static unsigned long mpll_recalc_rate(const struct clk *clk, unsigned long prate return DIV_ROUND_UP_ULL((uint64_t)prate * SDM_DEN, divisor); } -static int mpll_set_rate(const struct clk *clk, uint32_t rate, uint32_t parent_rate) +static int mpll_set_rate(const struct clk *clk, uint32_t rate, + uint32_t parent_rate) { - struct meson_clk_mpll_data *data = (struct meson_clk_mpll_data *)(clk->data); + struct meson_clk_mpll_data *data = + (struct meson_clk_mpll_data *)(clk->data); uint64_t div = parent_rate; uint64_t frac = do_div(div, rate); uint32_t sdm, n2; @@ -246,27 +270,30 @@ static int mpll_set_rate(const struct clk *clk, uint32_t rate, uint32_t parent_r n2 = div; } - regmap_update_bits(clk->base, data->sdm.reg_off, data->sdm.shift, data->sdm.width, sdm); - regmap_update_bits(clk->base, data->n2.reg_off, data->n2.shift, data->n2.width, n2); - - /* volatile uint32_t *clk_reg = ((void *)clk_base + data->sdm.reg_off); */ + regmap_update_bits(clk->base, data->sdm.reg_off, data->sdm.shift, + data->sdm.width, sdm); + regmap_update_bits(clk->base, data->n2.reg_off, data->n2.shift, + data->n2.width, n2); return 0; } static void mpll_init(struct clk *clk) { - struct meson_clk_mpll_data *data = (struct meson_clk_mpll_data *)(clk->data); + struct meson_clk_mpll_data *data = + (struct meson_clk_mpll_data *)(clk->data); if (data->init_count) { regmap_multi_reg_write(clk->base, data->init_regs, data->init_count); } /* Enable the fractional part */ - regmap_update_bits(clk->base, data->sdm_en.reg_off, data->sdm_en.shift, data->sdm_en.width, 1); + regmap_update_bits(clk->base, data->sdm_en.reg_off, data->sdm_en.shift, + data->sdm_en.width, 1); /* Set spread spectrum if possible */ unsigned int ss = data->flags & CLK_MESON_MPLL_SPREAD_SPECTRUM ? 1 : 0; - regmap_update_bits(clk->base, data->ssen.reg_off, data->ssen.shift, data->ssen.width, ss); + regmap_update_bits(clk->base, data->ssen.reg_off, data->ssen.shift, + data->ssen.width, ss); } const struct clk_ops meson_clk_mpll_ops = { @@ -295,12 +322,14 @@ static int meson_clk_pcie_pll_enable(struct clk *clk) return -1; } -const struct clk_ops meson_clk_pcie_pll_ops = { .init = meson_clk_pll_init, - .recalc_rate = meson_clk_pll_recalc_rate, +const struct clk_ops meson_clk_pcie_pll_ops = { + .init = meson_clk_pll_init, + .recalc_rate = meson_clk_pll_recalc_rate, /* .determine_rate = meson_clk_pll_determine_rate, */ - .is_enabled = meson_clk_pll_is_enabled, - .enable = meson_clk_pcie_pll_enable, - .disable = meson_clk_pll_disable }; + .is_enabled = meson_clk_pll_is_enabled, + .enable = meson_clk_pcie_pll_enable, + .disable = meson_clk_pll_disable +}; struct vid_pll_div { unsigned int shift_val; @@ -318,35 +347,40 @@ struct vid_pll_div { } static const struct vid_pll_div vid_pll_div_table[] = { - VID_PLL_DIV(0x0aaa, 0, 2, 1), /* 2/1 => /2 */ - VID_PLL_DIV(0x5294, 2, 5, 2), /* 5/2 => /2.5 */ - VID_PLL_DIV(0x0db6, 0, 3, 1), /* 3/1 => /3 */ - VID_PLL_DIV(0x36cc, 1, 7, 2), /* 7/2 => /3.5 */ - VID_PLL_DIV(0x6666, 2, 15, 4), /* 15/4 => /3.75 */ - VID_PLL_DIV(0x0ccc, 0, 4, 1), /* 4/1 => /4 */ - VID_PLL_DIV(0x739c, 2, 5, 1), /* 5/1 => /5 */ - VID_PLL_DIV(0x0e38, 0, 6, 1), /* 6/1 => /6 */ - VID_PLL_DIV(0x0000, 3, 25, 4), /* 25/4 => /6.25 */ - VID_PLL_DIV(0x3c78, 1, 7, 1), /* 7/1 => /7 */ - VID_PLL_DIV(0x78f0, 2, 15, 2), /* 15/2 => /7.5 */ - VID_PLL_DIV(0x0fc0, 0, 12, 1), /* 12/1 => /12 */ - VID_PLL_DIV(0x3f80, 1, 14, 1), /* 14/1 => /14 */ - VID_PLL_DIV(0x7f80, 2, 15, 1), /* 15/1 => /15 */ + VID_PLL_DIV(0x0aaa, 0, 2, 1), /* 2/1 => /2 */ + VID_PLL_DIV(0x5294, 2, 5, 2), /* 5/2 => /2.5 */ + VID_PLL_DIV(0x0db6, 0, 3, 1), /* 3/1 => /3 */ + VID_PLL_DIV(0x36cc, 1, 7, 2), /* 7/2 => /3.5 */ + VID_PLL_DIV(0x6666, 2, 15, 4), /* 15/4 => /3.75 */ + VID_PLL_DIV(0x0ccc, 0, 4, 1), /* 4/1 => /4 */ + VID_PLL_DIV(0x739c, 2, 5, 1), /* 5/1 => /5 */ + VID_PLL_DIV(0x0e38, 0, 6, 1), /* 6/1 => /6 */ + VID_PLL_DIV(0x0000, 3, 25, 4), /* 25/4 => /6.25 */ + VID_PLL_DIV(0x3c78, 1, 7, 1), /* 7/1 => /7 */ + VID_PLL_DIV(0x78f0, 2, 15, 2), /* 15/2 => /7.5 */ + VID_PLL_DIV(0x0fc0, 0, 12, 1), /* 12/1 => /12 */ + VID_PLL_DIV(0x3f80, 1, 14, 1), /* 14/1 => /14 */ + VID_PLL_DIV(0x7f80, 2, 15, 1), /* 15/1 => /15 */ }; -static unsigned long meson_vid_pll_div_recalc_rate(const struct clk *clk, unsigned long prate) +static unsigned long meson_vid_pll_div_recalc_rate(const struct clk *clk, + unsigned long prate) { - struct meson_vid_pll_div_data *data = (struct meson_vid_pll_div_data *)(clk->data); + struct meson_vid_pll_div_data *data = + (struct meson_vid_pll_div_data *)(clk->data); const struct vid_pll_div *div; uint32_t shift_val, shift_sel; - shift_val = regmap_read_bits(clk->base, data->val.reg_off, data->val.shift, data->val.width); - shift_sel = regmap_read_bits(clk->base, data->sel.reg_off, data->sel.shift, data->sel.width); + shift_val = regmap_read_bits(clk->base, data->val.reg_off, data->val.shift, + data->val.width); + shift_sel = regmap_read_bits(clk->base, data->sel.reg_off, data->sel.shift, + data->sel.width); int i; for (i = 0; i < ARRAY_SIZE(vid_pll_div_table); ++i) { - if (vid_pll_div_table[i].shift_val == shift_val && vid_pll_div_table[i].shift_sel == shift_sel) { + if (vid_pll_div_table[i].shift_val == shift_val + && vid_pll_div_table[i].shift_sel == shift_sel) { div = &vid_pll_div_table[i]; return DIV_ROUND_UP_ULL(prate * div->multiplier, div->divider); } @@ -362,29 +396,37 @@ const struct clk_ops meson_vid_pll_div_ro_ops = { static int meson_vclk_gate_enable(struct clk *clk) { - struct meson_vclk_gate_data *data = (struct meson_vclk_gate_data *)(clk->data); + struct meson_vclk_gate_data *data = + (struct meson_vclk_gate_data *)(clk->data); - regmap_update_bits(clk->base, data->enable.reg_off, data->enable.shift, data->enable.width, 1); + regmap_update_bits(clk->base, data->enable.reg_off, data->enable.shift, + data->enable.width, 1); /* Do a reset pulse */ - regmap_update_bits(clk->base, data->reset.reg_off, data->reset.shift, data->reset.width, 1); - regmap_update_bits(clk->base, data->reset.reg_off, data->reset.shift, data->reset.width, 0); + regmap_update_bits(clk->base, data->reset.reg_off, data->reset.shift, + data->reset.width, 1); + regmap_update_bits(clk->base, data->reset.reg_off, data->reset.shift, + data->reset.width, 0); return 0; } static int meson_vclk_gate_disable(struct clk *clk) { - struct meson_vclk_gate_data *data = (struct meson_vclk_gate_data *)(clk->data); + struct meson_vclk_gate_data *data = + (struct meson_vclk_gate_data *)(clk->data); - regmap_update_bits(clk->base, data->enable.reg_off, data->enable.shift, data->enable.width, 0); + regmap_update_bits(clk->base, data->enable.reg_off, data->enable.shift, + data->enable.width, 0); return 0; } static int meson_vclk_gate_is_enabled(struct clk *clk) { - struct meson_vclk_gate_data *data = (struct meson_vclk_gate_data *)(clk->data); - return regmap_read_bits(clk->base, data->enable.reg_off, data->enable.shift, data->enable.width); + struct meson_vclk_gate_data *data = + (struct meson_vclk_gate_data *)(clk->data); + return regmap_read_bits(clk->base, data->enable.reg_off, data->enable.shift, + data->enable.width); } const struct clk_ops meson_vclk_gate_ops = { @@ -393,10 +435,13 @@ const struct clk_ops meson_vclk_gate_ops = { .is_enabled = meson_vclk_gate_is_enabled, }; -static unsigned long meson_vclk_div_recalc_rate(const struct clk *clk, unsigned long prate) +static unsigned long meson_vclk_div_recalc_rate(const struct clk *clk, + unsigned long prate) { - struct meson_vclk_div_data *data = (struct meson_vclk_div_data *)(clk->data); - uint32_t div = regmap_read_bits(clk->base, data->div.reg_off, data->div.shift, data->div.width); + struct meson_vclk_div_data *data = + (struct meson_vclk_div_data *)(clk->data); + uint32_t div = regmap_read_bits(clk->base, data->div.reg_off, + data->div.shift, data->div.width); /* TODO: Need to verify the following cases */ if (data->flags & CLK_DIVIDER_ONE_BASED) { @@ -412,9 +457,11 @@ static unsigned long meson_vclk_div_recalc_rate(const struct clk *clk, unsigned return DIV_ROUND_UP_ULL((uint64_t)prate, div); } -static int meson_vclk_div_set_rate(const struct clk *clk, uint32_t rate, uint32_t parent_rate) +static int meson_vclk_div_set_rate(const struct clk *clk, uint32_t rate, + uint32_t parent_rate) { - struct meson_vclk_div_data *data = (struct meson_vclk_div_data *)(clk->data); + struct meson_vclk_div_data *data = + (struct meson_vclk_div_data *)(clk->data); uint32_t div = DIV_ROUND_UP(parent_rate, rate); @@ -428,32 +475,41 @@ static int meson_vclk_div_set_rate(const struct clk *clk, uint32_t rate, uint32_ } else { div -= 1; } - return regmap_update_bits(clk->base, data->div.reg_off, data->div.shift, data->div.width, div); + return regmap_update_bits(clk->base, data->div.reg_off, data->div.shift, + data->div.width, div); } static int meson_vclk_div_enable(struct clk *clk) { - struct meson_vclk_div_data *data = (struct meson_vclk_div_data *)(clk->data); + struct meson_vclk_div_data *data = + (struct meson_vclk_div_data *)(clk->data); - regmap_update_bits(clk->base, data->reset.reg_off, data->reset.shift, data->reset.width, 0); - regmap_update_bits(clk->base, data->enable.reg_off, data->enable.shift, data->enable.width, 1); + regmap_update_bits(clk->base, data->reset.reg_off, data->reset.shift, + data->reset.width, 0); + regmap_update_bits(clk->base, data->enable.reg_off, data->enable.shift, + data->enable.width, 1); return 0; } static int meson_vclk_div_disable(struct clk *clk) { - struct meson_vclk_div_data *data = (struct meson_vclk_div_data *)(clk->data); + struct meson_vclk_div_data *data = + (struct meson_vclk_div_data *)(clk->data); - regmap_update_bits(clk->base, data->enable.reg_off, data->enable.shift, data->enable.width, 0); - regmap_update_bits(clk->base, data->reset.reg_off, data->reset.shift, data->reset.width, 1); + regmap_update_bits(clk->base, data->enable.reg_off, data->enable.shift, + data->enable.width, 0); + regmap_update_bits(clk->base, data->reset.reg_off, data->reset.shift, + data->reset.width, 1); return 0; } static int meson_vclk_div_is_enabled(struct clk *clk) { - struct meson_vclk_div_data *data = (struct meson_vclk_div_data *)(clk->data); - return regmap_read_bits(clk->base, data->enable.reg_off, data->enable.shift, data->enable.width); + struct meson_vclk_div_data *data = + (struct meson_vclk_div_data *)(clk->data); + return regmap_read_bits(clk->base, data->enable.reg_off, data->enable.shift, + data->enable.width); } const struct clk_ops meson_vclk_div_ops = { @@ -465,9 +521,11 @@ const struct clk_ops meson_vclk_div_ops = { .is_enabled = meson_vclk_div_is_enabled, }; -static unsigned long meson_clk_cpu_dyndiv_recalc_rate(const struct clk *clk, unsigned long prate) +static unsigned long meson_clk_cpu_dyndiv_recalc_rate(const struct clk *clk, + unsigned long prate) { - struct meson_clk_cpu_dyndiv_data *data = (struct meson_clk_cpu_dyndiv_data *)(clk->data); + struct meson_clk_cpu_dyndiv_data *data = + (struct meson_clk_cpu_dyndiv_data *)(clk->data); uint32_t div = meson_parm_read(clk->base, data->div); div += 1; diff --git a/drivers/clk/meson/clk.c b/drivers/clk/meson/clk.c index 058565de0..3f303882c 100644 --- a/drivers/clk/meson/clk.c +++ b/drivers/clk/meson/clk.c @@ -15,10 +15,10 @@ #include /* common definitions and interfaces */ #include /* ops of common clocks e.g., div, mux, fixed factor, and gate*/ -#include /* implementation of clock measurements */ -#include /* operations for meson-specific clocks */ -#include /* offsets of control registers */ -#include /* clock id bindings*/ +#include /* implementation of clock measurements */ +#include /* operations for meson-specific clocks */ +#include /* offsets of control registers */ +#include /* clock id bindings*/ // Logging /* #define DEBUG_DRIVER */ @@ -162,18 +162,17 @@ uint32_t clk_set_rate(struct clk *clk, uint64_t req_rate, uint64_t *rate) clk->hw.init->ops->set_rate(clk, req_rate, prate); *rate = req_rate; return 0; - } else { - if (pclk->hw.init->ops->set_rate) { - const struct clk *ppclk = get_parent(pclk); - uint64_t pprate = 0; - uint32_t err = clk_get_rate(ppclk, &pprate); - if (!err) { - pclk->hw.init->ops->set_rate(pclk, prate, pprate); - *rate = req_rate; - return 0; - } - return err; + } + if (pclk->hw.init->ops->set_rate) { + const struct clk *ppclk = get_parent(pclk); + uint64_t pprate = 0; + uint32_t err = clk_get_rate(ppclk, &pprate); + if (!err) { + pclk->hw.init->ops->set_rate(pclk, prate, pprate); + *rate = req_rate; + return 0; } + return err; } return CLK_INVALID_OP; @@ -193,7 +192,8 @@ int clk_msr_stat() for (i = 0; i < NUM_CLK_LIST; i++) { err = clk_get_rate(clk_list[i], &rate); if (err) { - LOG_DRIVER("Failed to get rate of %s: -%u\n", clk_list[i]->hw.init->name, err); + LOG_DRIVER("Failed to get rate of %s: -%u\n", + clk_list[i]->hw.init->name, err); } LOG_DRIVER("[%4d][%4luHz] %s\n", i, rate, clk_list[i]->hw.init->name); } @@ -236,8 +236,8 @@ void init(void) uint64_t rate = 0; uint32_t err = clk_set_rate(clk, clk_configs[i].frequency, &rate); if (err) { - LOG_DRIVER_ERR("Failed to set rate [%d] for clk_id: %d\n", clk_configs[i].frequency, - clk_configs[i].clk_id); + LOG_DRIVER_ERR("Failed to set rate [%d] for clk_id: %d\n", + clk_configs[i].frequency, clk_configs[i].clk_id); } } } @@ -302,8 +302,8 @@ microkit_msginfo protected(microkit_channel ch, microkit_msginfo msginfo) break; } default: - LOG_DRIVER_ERR("Unknown request %lu to clockk driver from channel %u\n", microkit_msginfo_get_label(msginfo), - ch); + LOG_DRIVER_ERR("Unknown request %lu to clockk driver from channel %u\n", + microkit_msginfo_get_label(msginfo), ch); err = CLK_UNKNOWN_REQ; } return microkit_msginfo_new(err, ret_num); diff --git a/drivers/clk/meson/clk_driver.mk b/drivers/clk/meson/clk_driver.mk index 6aff1dbb2..379d43454 100644 --- a/drivers/clk/meson/clk_driver.mk +++ b/drivers/clk/meson/clk_driver.mk @@ -22,7 +22,7 @@ $(CLK_DRIVER_OBJS): ${CLK_DRIVER_COMMON_DIR}/*.c ${CLK_DRIVER_DIR}/*.c $(CLK_CON -I${UART_DRIVER_DIR}/include \ -I${CLK_DRIVER_COMMON_DIR} $^ -$(CLK_CONFIG_HEADER): $(DTS_FILE) +$(CLK_CONFIG_HEADER): $(DTS_FILE) $(CLK_DRIVER_COMMON_DIR)/create_clk_config.py $(PYTHON) $(CLK_DRIVER_COMMON_DIR)/create_clk_config.py $(DTS_FILE) $(BUILD_DIR) clean:: diff --git a/drivers/clk/meson/sm1-clk.c b/drivers/clk/meson/sm1-clk.c index 97069e87b..07924ecea 100644 --- a/drivers/clk/meson/sm1-clk.c +++ b/drivers/clk/meson/sm1-clk.c @@ -71,7 +71,8 @@ static struct clk g12a_fixed_pll_dco = { .num_parents = 1, }, }; -static CLK_DIV_RO(g12a_fixed_pll, HHI_FIX_PLL_CNTL0, 16, 2, CLK_DIVIDER_POWER_OF_TWO, { &g12a_fixed_pll_dco }, 1, 0); +static CLK_DIV_RO(g12a_fixed_pll, HHI_FIX_PLL_CNTL0, 16, 2, + CLK_DIVIDER_POWER_OF_TWO, { &g12a_fixed_pll_dco }, 1, 0); static struct clk g12a_sys_pll_dco = { .data = &(struct meson_clk_pll_data){ .en = { @@ -113,13 +114,18 @@ static struct clk g12a_sys_pll_dco = { .flags = CLK_IS_CRITICAL, }, }; -static CLK_DIV(g12a_sys_pll, HHI_SYS_PLL_CNTL0, 16, 3, CLK_DIVIDER_POWER_OF_TWO, { &g12a_sys_pll_dco }, 1, 0); -static CLK_GATE_RO(g12a_sys_pll_div16_en, HHI_SYS_CPU_CLK_CNTL1, 24, 0, { &g12a_sys_pll }, 1, 0); -static CLK_FIXED_FACTOR(g12a_sys_pll_div16, 1, 16, 0, { &g12a_sys_pll_div16_en }, 1, 0); +static CLK_DIV(g12a_sys_pll, HHI_SYS_PLL_CNTL0, 16, 3, CLK_DIVIDER_POWER_OF_TWO, + { &g12a_sys_pll_dco }, 1, 0); +static CLK_GATE_RO(g12a_sys_pll_div16_en, HHI_SYS_CPU_CLK_CNTL1, 24, 0, + { &g12a_sys_pll }, 1, 0); +static CLK_FIXED_FACTOR(g12a_sys_pll_div16, 1, 16, 0, + { &g12a_sys_pll_div16_en }, 1, 0); static CLK_FIXED_FACTOR(g12a_fclk_div2_div, 1, 2, 0, { &g12a_fixed_pll }, 1, 0); -static CLK_GATE(g12a_fclk_div2, HHI_FIX_PLL_CNTL1, 24, 0, { &g12a_fclk_div2_div }, 1, 0); +static CLK_GATE(g12a_fclk_div2, HHI_FIX_PLL_CNTL1, 24, 0, + { &g12a_fclk_div2_div }, 1, 0); static CLK_FIXED_FACTOR(g12a_fclk_div3_div, 1, 3, 0, { &g12a_fixed_pll }, 1, 0); -static CLK_GATE(g12a_fclk_div3, HHI_FIX_PLL_CNTL1, 20, 0, { &g12a_fclk_div3_div }, 1, 0); +static CLK_GATE(g12a_fclk_div3, HHI_FIX_PLL_CNTL1, 20, 0, + { &g12a_fclk_div3_div }, 1, 0); const struct clk_parent_data g12a_cpu_clk_premux0_parent_table[] = { { .name = "xtal", @@ -127,8 +133,8 @@ const struct clk_parent_data g12a_cpu_clk_premux0_parent_table[] = { { .clk = &g12a_fclk_div2 }, { .clk = &g12a_fclk_div3 }, }; -static CLK_MUX(g12a_cpu_clk_premux0, HHI_SYS_CPU_CLK_CNTL0, 0x3, 0, 0, CLK_MUX_ROUND_CLOSEST, - g12a_cpu_clk_premux0_parent_table, 3, 0); +static CLK_MUX(g12a_cpu_clk_premux0, HHI_SYS_CPU_CLK_CNTL0, 0x3, 0, 0, + CLK_MUX_ROUND_CLOSEST, g12a_cpu_clk_premux0_parent_table, 3, 0); const struct clk_parent_data g12a_cpu_clk_premux1_parent_table[] = { { .name = "xtal", @@ -136,7 +142,8 @@ const struct clk_parent_data g12a_cpu_clk_premux1_parent_table[] = { { .clk = &g12a_fclk_div2 }, { .clk = &g12a_fclk_div3 }, }; -static CLK_MUX(g12a_cpu_clk_premux1, HHI_SYS_CPU_CLK_CNTL0, 0x3, 16, 0, 0, g12a_cpu_clk_premux1_parent_table, 3, 0); +static CLK_MUX(g12a_cpu_clk_premux1, HHI_SYS_CPU_CLK_CNTL0, 0x3, 16, 0, 0, + g12a_cpu_clk_premux1_parent_table, 3, 0); static struct clk g12a_cpu_clk_mux0_div = { .data = &(struct meson_clk_cpu_dyndiv_data){ .div = { @@ -164,30 +171,36 @@ const struct clk_parent_data g12a_cpu_clk_postmux0_parent_table[] = { { .clk = &g12a_cpu_clk_premux0 }, { .clk = &g12a_cpu_clk_mux0_div }, }; -static CLK_MUX(g12a_cpu_clk_postmux0, HHI_SYS_CPU_CLK_CNTL0, 0x1, 2, 0, CLK_MUX_ROUND_CLOSEST, - g12a_cpu_clk_postmux0_parent_table, 2, 0); -static CLK_DIV_RO(g12a_cpu_clk_mux1_div, HHI_SYS_CPU_CLK_CNTL0, 20, 6, 0, { &g12a_cpu_clk_premux1 }, 1, 0); +static CLK_MUX(g12a_cpu_clk_postmux0, HHI_SYS_CPU_CLK_CNTL0, 0x1, 2, 0, + CLK_MUX_ROUND_CLOSEST, g12a_cpu_clk_postmux0_parent_table, 2, 0); +static CLK_DIV_RO(g12a_cpu_clk_mux1_div, HHI_SYS_CPU_CLK_CNTL0, 20, 6, 0, + { &g12a_cpu_clk_premux1 }, 1, 0); const struct clk_parent_data g12a_cpu_clk_postmux1_parent_table[] = { { .clk = &g12a_cpu_clk_premux1 }, { .clk = &g12a_cpu_clk_mux1_div }, }; -static CLK_MUX(g12a_cpu_clk_postmux1, HHI_SYS_CPU_CLK_CNTL0, 0x1, 18, 0, 0, g12a_cpu_clk_postmux1_parent_table, 2, 0); +static CLK_MUX(g12a_cpu_clk_postmux1, HHI_SYS_CPU_CLK_CNTL0, 0x1, 18, 0, 0, + g12a_cpu_clk_postmux1_parent_table, 2, 0); const struct clk_parent_data g12a_cpu_clk_dyn_parent_table[] = { { .clk = &g12a_cpu_clk_postmux0 }, { .clk = &g12a_cpu_clk_postmux1 }, }; -static CLK_MUX(g12a_cpu_clk_dyn, HHI_SYS_CPU_CLK_CNTL0, 0x1, 10, 0, CLK_MUX_ROUND_CLOSEST, - g12a_cpu_clk_dyn_parent_table, 2, 0); +static CLK_MUX(g12a_cpu_clk_dyn, HHI_SYS_CPU_CLK_CNTL0, 0x1, 10, 0, + CLK_MUX_ROUND_CLOSEST, g12a_cpu_clk_dyn_parent_table, 2, 0); const struct clk_parent_data g12a_cpu_clk_parent_table[] = { { .clk = &g12a_cpu_clk_dyn }, { .clk = &g12a_sys_pll }, }; -static CLK_MUX(g12a_cpu_clk, HHI_SYS_CPU_CLK_CNTL0, 0x1, 11, 0, CLK_MUX_ROUND_CLOSEST, g12a_cpu_clk_parent_table, 2, 0); +static CLK_MUX(g12a_cpu_clk, HHI_SYS_CPU_CLK_CNTL0, 0x1, 11, 0, + CLK_MUX_ROUND_CLOSEST, g12a_cpu_clk_parent_table, 2, 0); static const struct reg_sequence g12a_gp0_init_regs[] = { - { .reg = HHI_GP0_PLL_CNTL1, .def = 0x00000000 }, { .reg = HHI_GP0_PLL_CNTL2, .def = 0x00000000 }, - { .reg = HHI_GP0_PLL_CNTL3, .def = 0x48681c00 }, { .reg = HHI_GP0_PLL_CNTL4, .def = 0x33771290 }, - { .reg = HHI_GP0_PLL_CNTL5, .def = 0x39272000 }, { .reg = HHI_GP0_PLL_CNTL6, .def = 0x56540000 }, + { .reg = HHI_GP0_PLL_CNTL1, .def = 0x00000000 }, + { .reg = HHI_GP0_PLL_CNTL2, .def = 0x00000000 }, + { .reg = HHI_GP0_PLL_CNTL3, .def = 0x48681c00 }, + { .reg = HHI_GP0_PLL_CNTL4, .def = 0x33771290 }, + { .reg = HHI_GP0_PLL_CNTL5, .def = 0x39272000 }, + { .reg = HHI_GP0_PLL_CNTL6, .def = 0x56540000 }, }; static struct clk g12a_gp0_pll_dco = { .data = &(struct meson_clk_pll_data){ @@ -235,7 +248,8 @@ static struct clk g12a_gp0_pll_dco = { .num_parents = 1, }, }; -static CLK_DIV(g12a_gp0_pll, HHI_GP0_PLL_CNTL0, 16, 3, (CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_ROUND_CLOSEST), +static CLK_DIV(g12a_gp0_pll, HHI_GP0_PLL_CNTL0, 16, 3, + (CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_ROUND_CLOSEST), { &g12a_gp0_pll_dco }, 1, 0); static struct clk sm1_gp1_pll_dco = { .data = &(struct meson_clk_pll_data){ @@ -281,7 +295,8 @@ static struct clk sm1_gp1_pll_dco = { .flags = CLK_IS_CRITICAL, }, }; -static CLK_DIV_RO(sm1_gp1_pll, HHI_GP1_PLL_CNTL0, 16, 3, (CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_ROUND_CLOSEST), +static CLK_DIV_RO(sm1_gp1_pll, HHI_GP1_PLL_CNTL0, 16, 3, + (CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_ROUND_CLOSEST), { &sm1_gp1_pll_dco }, 1, 0); const struct clk_parent_data sm1_dsu_clk_premux0_parent_table[] = { @@ -292,7 +307,8 @@ const struct clk_parent_data sm1_dsu_clk_premux0_parent_table[] = { { .clk = &g12a_fclk_div3 }, { .clk = &sm1_gp1_pll }, }; -static CLK_MUX_RO(sm1_dsu_clk_premux0, HHI_SYS_CPU_CLK_CNTL5, 0x3, 0, 0, 0, sm1_dsu_clk_premux0_parent_table, 4, 0); +static CLK_MUX_RO(sm1_dsu_clk_premux0, HHI_SYS_CPU_CLK_CNTL5, 0x3, 0, 0, 0, + sm1_dsu_clk_premux0_parent_table, 4, 0); const struct clk_parent_data sm1_dsu_clk_premux1_parent_table[] = { { .name = "xtal", @@ -301,16 +317,20 @@ const struct clk_parent_data sm1_dsu_clk_premux1_parent_table[] = { { .clk = &g12a_fclk_div3 }, { .clk = &sm1_gp1_pll }, }; -static CLK_MUX_RO(sm1_dsu_clk_premux1, HHI_SYS_CPU_CLK_CNTL5, 0x3, 16, 0, 0, sm1_dsu_clk_premux1_parent_table, 4, 0); -static CLK_DIV_RO(sm1_dsu_clk_mux0_div, HHI_SYS_CPU_CLK_CNTL5, 4, 6, 0, { &sm1_dsu_clk_premux0 }, 1, 0); +static CLK_MUX_RO(sm1_dsu_clk_premux1, HHI_SYS_CPU_CLK_CNTL5, 0x3, 16, 0, 0, + sm1_dsu_clk_premux1_parent_table, 4, 0); +static CLK_DIV_RO(sm1_dsu_clk_mux0_div, HHI_SYS_CPU_CLK_CNTL5, 4, 6, 0, + { &sm1_dsu_clk_premux0 }, 1, 0); const struct clk_parent_data sm1_dsu_clk_postmux0_parent_table[] = { { .clk = &sm1_dsu_clk_premux0, }, { .clk = &sm1_dsu_clk_mux0_div }, }; -static CLK_MUX_RO(sm1_dsu_clk_postmux0, HHI_SYS_CPU_CLK_CNTL5, 0x1, 2, 0, 0, sm1_dsu_clk_postmux0_parent_table, 2, 0); -static CLK_DIV_RO(sm1_dsu_clk_mux1_div, HHI_SYS_CPU_CLK_CNTL5, 20, 6, 0, { &sm1_dsu_clk_premux1 }, 1, 0); +static CLK_MUX_RO(sm1_dsu_clk_postmux0, HHI_SYS_CPU_CLK_CNTL5, 0x1, 2, 0, 0, + sm1_dsu_clk_postmux0_parent_table, 2, 0); +static CLK_DIV_RO(sm1_dsu_clk_mux1_div, HHI_SYS_CPU_CLK_CNTL5, 20, 6, 0, + { &sm1_dsu_clk_premux1 }, 1, 0); const struct clk_parent_data sm1_dsu_clk_postmux1_parent_table[] = { { @@ -318,7 +338,8 @@ const struct clk_parent_data sm1_dsu_clk_postmux1_parent_table[] = { }, { .clk = &sm1_dsu_clk_mux1_div }, }; -static CLK_MUX_RO(sm1_dsu_clk_postmux1, HHI_SYS_CPU_CLK_CNTL5, 0x1, 18, 0, 0, sm1_dsu_clk_postmux1_parent_table, 2, 0); +static CLK_MUX_RO(sm1_dsu_clk_postmux1, HHI_SYS_CPU_CLK_CNTL5, 0x1, 18, 0, 0, + sm1_dsu_clk_postmux1_parent_table, 2, 0); const struct clk_parent_data sm1_dsu_clk_dyn_parent_table[] = { { .clk = &sm1_dsu_clk_premux0, @@ -327,7 +348,8 @@ const struct clk_parent_data sm1_dsu_clk_dyn_parent_table[] = { .clk = &sm1_dsu_clk_postmux1, }, }; -static CLK_MUX_RO(sm1_dsu_clk_dyn, HHI_SYS_CPU_CLK_CNTL5, 0x1, 10, 0, 0, sm1_dsu_clk_dyn_parent_table, 2, 0); +static CLK_MUX_RO(sm1_dsu_clk_dyn, HHI_SYS_CPU_CLK_CNTL5, 0x1, 10, 0, 0, + sm1_dsu_clk_dyn_parent_table, 2, 0); const struct clk_parent_data sm1_dsu_final_clk_parent_table[] = { { .clk = &sm1_dsu_clk_dyn, @@ -336,15 +358,19 @@ const struct clk_parent_data sm1_dsu_final_clk_parent_table[] = { .clk = &g12a_sys_pll, }, }; -static CLK_MUX_RO(sm1_dsu_final_clk, HHI_SYS_CPU_CLK_CNTL5, 0x1, 11, 0, 0, sm1_dsu_final_clk_parent_table, 2, 0); +static CLK_MUX_RO(sm1_dsu_final_clk, HHI_SYS_CPU_CLK_CNTL5, 0x1, 11, 0, 0, + sm1_dsu_final_clk_parent_table, 2, 0); const struct clk_parent_data sm1_cpu_clk_parent_table[] = { { .clk = &g12a_cpu_clk, }, }; -static CLK_MUX_RO(sm1_cpu1_clk, HHI_SYS_CPU_CLK_CNTL6, 0x1, 24, 0, 0, sm1_cpu_clk_parent_table, 1, 0); -static CLK_MUX_RO(sm1_cpu2_clk, HHI_SYS_CPU_CLK_CNTL6, 0x1, 25, 0, 0, sm1_cpu_clk_parent_table, 1, 0); -static CLK_MUX_RO(sm1_cpu3_clk, HHI_SYS_CPU_CLK_CNTL6, 0x1, 26, 0, 0, sm1_cpu_clk_parent_table, 1, 0); +static CLK_MUX_RO(sm1_cpu1_clk, HHI_SYS_CPU_CLK_CNTL6, 0x1, 24, 0, 0, + sm1_cpu_clk_parent_table, 1, 0); +static CLK_MUX_RO(sm1_cpu2_clk, HHI_SYS_CPU_CLK_CNTL6, 0x1, 25, 0, 0, + sm1_cpu_clk_parent_table, 1, 0); +static CLK_MUX_RO(sm1_cpu3_clk, HHI_SYS_CPU_CLK_CNTL6, 0x1, 26, 0, 0, + sm1_cpu_clk_parent_table, 1, 0); const struct clk_parent_data sm1_dsu_clk_parent_table[] = { { .clk = &g12a_cpu_clk, @@ -353,23 +379,37 @@ const struct clk_parent_data sm1_dsu_clk_parent_table[] = { .clk = &sm1_dsu_final_clk, }, }; -static CLK_MUX_RO(sm1_dsu_clk, HHI_SYS_CPU_CLK_CNTL6, 0x1, 27, 0, 0, sm1_dsu_clk_parent_table, 2, 0); -static CLK_GATE_RO(g12a_cpu_clk_div16_en, HHI_SYS_CPU_CLK_CNTL1, 1, 0, { &g12a_cpu_clk }, 1, 0); -static CLK_FIXED_FACTOR(g12a_cpu_clk_div16, 1, 16, 0, { &g12a_cpu_clk_div16_en }, 1, 0); -static CLK_DIV_RO(g12a_cpu_clk_apb_div, HHI_SYS_CPU_CLK_CNTL1, 3, 3, CLK_DIVIDER_POWER_OF_TWO, { &g12a_cpu_clk }, 1, 0); -static CLK_GATE_RO(g12a_cpu_clk_apb, HHI_SYS_CPU_CLK_CNTL1, 1, 0, { &g12a_cpu_clk_apb_div }, 1, 0); -static CLK_DIV_RO(g12a_cpu_clk_atb_div, HHI_SYS_CPU_CLK_CNTL1, 6, 3, CLK_DIVIDER_POWER_OF_TWO, { &g12a_cpu_clk }, 1, 0); -static CLK_GATE_RO(g12a_cpu_clk_atb, HHI_SYS_CPU_CLK_CNTL1, 17, 0, { &g12a_cpu_clk_atb_div }, 1, 0); -static CLK_DIV_RO(g12a_cpu_clk_axi_div, HHI_SYS_CPU_CLK_CNTL1, 9, 3, CLK_DIVIDER_POWER_OF_TWO, { &g12a_cpu_clk }, 1, 0); -static CLK_GATE_RO(g12a_cpu_clk_axi, HHI_SYS_CPU_CLK_CNTL1, 18, 0, { &g12a_cpu_clk_axi_div }, 1, 0); +static CLK_MUX_RO(sm1_dsu_clk, HHI_SYS_CPU_CLK_CNTL6, 0x1, 27, 0, 0, + sm1_dsu_clk_parent_table, 2, 0); +static CLK_GATE_RO(g12a_cpu_clk_div16_en, HHI_SYS_CPU_CLK_CNTL1, 1, 0, + { &g12a_cpu_clk }, 1, 0); +static CLK_FIXED_FACTOR(g12a_cpu_clk_div16, 1, 16, 0, + { &g12a_cpu_clk_div16_en }, 1, 0); +static CLK_DIV_RO(g12a_cpu_clk_apb_div, HHI_SYS_CPU_CLK_CNTL1, 3, 3, + CLK_DIVIDER_POWER_OF_TWO, { &g12a_cpu_clk }, 1, 0); +static CLK_GATE_RO(g12a_cpu_clk_apb, HHI_SYS_CPU_CLK_CNTL1, 1, 0, + { &g12a_cpu_clk_apb_div }, 1, 0); +static CLK_DIV_RO(g12a_cpu_clk_atb_div, HHI_SYS_CPU_CLK_CNTL1, 6, 3, + CLK_DIVIDER_POWER_OF_TWO, { &g12a_cpu_clk }, 1, 0); +static CLK_GATE_RO(g12a_cpu_clk_atb, HHI_SYS_CPU_CLK_CNTL1, 17, 0, + { &g12a_cpu_clk_atb_div }, 1, 0); +static CLK_DIV_RO(g12a_cpu_clk_axi_div, HHI_SYS_CPU_CLK_CNTL1, 9, 3, + CLK_DIVIDER_POWER_OF_TWO, { &g12a_cpu_clk }, 1, 0); +static CLK_GATE_RO(g12a_cpu_clk_axi, HHI_SYS_CPU_CLK_CNTL1, 18, 0, + { &g12a_cpu_clk_axi_div }, 1, 0); /* TODO: special case, ignore its parent clk at the moment */ -static CLK_DIV_RO(g12a_cpu_clk_trace_div, HHI_SYS_CPU_CLK_CNTL1, 20, 3, CLK_DIVIDER_POWER_OF_TWO, {}, 0, 0); -static CLK_GATE_RO(g12a_cpu_clk_trace, HHI_SYS_CPU_CLK_CNTL1, 23, 0, { &g12a_cpu_clk_trace_div }, 1, 0); +static CLK_DIV_RO(g12a_cpu_clk_trace_div, HHI_SYS_CPU_CLK_CNTL1, 20, 3, + CLK_DIVIDER_POWER_OF_TWO, {}, 0, 0); +static CLK_GATE_RO(g12a_cpu_clk_trace, HHI_SYS_CPU_CLK_CNTL1, 23, 0, + { &g12a_cpu_clk_trace_div }, 1, 0); static const struct reg_sequence g12a_hifi_init_regs[] = { - { .reg = HHI_HIFI_PLL_CNTL1, .def = 0x00000000 }, { .reg = HHI_HIFI_PLL_CNTL2, .def = 0x00000000 }, - { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x6a285c00 }, { .reg = HHI_HIFI_PLL_CNTL4, .def = 0x65771290 }, - { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x39272000 }, { .reg = HHI_HIFI_PLL_CNTL6, .def = 0x56540000 }, + { .reg = HHI_HIFI_PLL_CNTL1, .def = 0x00000000 }, + { .reg = HHI_HIFI_PLL_CNTL2, .def = 0x00000000 }, + { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x6a285c00 }, + { .reg = HHI_HIFI_PLL_CNTL4, .def = 0x65771290 }, + { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x39272000 }, + { .reg = HHI_HIFI_PLL_CNTL6, .def = 0x56540000 }, }; static struct clk g12a_hifi_pll_dco = { @@ -419,7 +459,8 @@ static struct clk g12a_hifi_pll_dco = { .num_parents = 1, }, }; -static CLK_DIV(g12a_hifi_pll, HHI_HIFI_PLL_CNTL0, 16, 2, (CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_ROUND_CLOSEST), +static CLK_DIV(g12a_hifi_pll, HHI_HIFI_PLL_CNTL0, 16, 2, + (CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_ROUND_CLOSEST), { &g12a_hifi_pll_dco }, 1, 0); /* @@ -491,10 +532,12 @@ static struct clk g12a_pcie_pll_dco = { .num_parents = 1, }, }; -static CLK_FIXED_FACTOR(g12a_pcie_pll_dco_div2, 1, 2, 0, { &g12a_pcie_pll_dco }, 1, 0); +static CLK_FIXED_FACTOR(g12a_pcie_pll_dco_div2, 1, 2, 0, { &g12a_pcie_pll_dco }, + 1, 0); static CLK_DIV(g12a_pcie_pll_od, HHI_PCIE_PLL_CNTL0, 16, 5, - CLK_DIVIDER_ROUND_CLOSEST | CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, { &g12a_pcie_pll_dco_div2 }, - 1, 0); + CLK_DIVIDER_ROUND_CLOSEST | CLK_DIVIDER_ONE_BASED + | CLK_DIVIDER_ALLOW_ZERO, + { &g12a_pcie_pll_dco_div2 }, 1, 0); static CLK_FIXED_FACTOR(g12a_pcie_pll, 1, 2, 0, { &g12a_pcie_pll_od }, 1, 0); static struct clk g12a_hdmi_pll_dco = { .data = &(struct meson_clk_pll_data){ @@ -543,26 +586,37 @@ static struct clk g12a_hdmi_pll_dco = { .flags = CLK_GET_RATE_NOCACHE, }, }; -static CLK_DIV_RO(g12a_hdmi_pll_od, HHI_HDMI_PLL_CNTL0, 16, 2, CLK_DIVIDER_POWER_OF_TWO, { &g12a_hdmi_pll_dco }, 1, 0); -static CLK_DIV_RO(g12a_hdmi_pll_od2, HHI_HDMI_PLL_CNTL0, 18, 2, CLK_DIVIDER_POWER_OF_TWO, { &g12a_hdmi_pll_od }, 1, 0); -static CLK_DIV_RO(g12a_hdmi_pll, HHI_HDMI_PLL_CNTL0, 20, 2, CLK_DIVIDER_POWER_OF_TWO, { &g12a_hdmi_pll_od2 }, 1, 0); +static CLK_DIV_RO(g12a_hdmi_pll_od, HHI_HDMI_PLL_CNTL0, 16, 2, + CLK_DIVIDER_POWER_OF_TWO, { &g12a_hdmi_pll_dco }, 1, 0); +static CLK_DIV_RO(g12a_hdmi_pll_od2, HHI_HDMI_PLL_CNTL0, 18, 2, + CLK_DIVIDER_POWER_OF_TWO, { &g12a_hdmi_pll_od }, 1, 0); +static CLK_DIV_RO(g12a_hdmi_pll, HHI_HDMI_PLL_CNTL0, 20, 2, + CLK_DIVIDER_POWER_OF_TWO, { &g12a_hdmi_pll_od2 }, 1, 0); static CLK_FIXED_FACTOR(g12a_fclk_div4_div, 1, 4, 0, { &g12a_fixed_pll }, 1, 0); -static CLK_GATE(g12a_fclk_div4, HHI_FIX_PLL_CNTL1, 21, 0, { &g12a_fclk_div4_div }, 1, 0); +static CLK_GATE(g12a_fclk_div4, HHI_FIX_PLL_CNTL1, 21, 0, + { &g12a_fclk_div4_div }, 1, 0); static CLK_FIXED_FACTOR(g12a_fclk_div5_div, 1, 5, 0, { &g12a_fixed_pll }, 1, 0); -static CLK_GATE(g12a_fclk_div5, HHI_FIX_PLL_CNTL1, 22, 0, { &g12a_fclk_div5_div }, 1, 0); +static CLK_GATE(g12a_fclk_div5, HHI_FIX_PLL_CNTL1, 22, 0, + { &g12a_fclk_div5_div }, 1, 0); static CLK_FIXED_FACTOR(g12a_fclk_div7_div, 1, 7, 0, { &g12a_fixed_pll }, 1, 0); -static CLK_GATE(g12a_fclk_div7, HHI_FIX_PLL_CNTL1, 23, 0, { &g12a_fclk_div7_div }, 1, 0); -static CLK_FIXED_FACTOR(g12a_fclk_div2p5_div, 1, 5, 0, { &g12a_fixed_pll_dco }, 1, 0); -static CLK_GATE(g12a_fclk_div2p5, HHI_FIX_PLL_CNTL1, 25, 0, { &g12a_fclk_div2p5_div }, 1, 0); -static CLK_FIXED_FACTOR(g12a_mpll_50m_div, 1, 80, 0, { &g12a_fixed_pll_dco }, 1, 0); +static CLK_GATE(g12a_fclk_div7, HHI_FIX_PLL_CNTL1, 23, 0, + { &g12a_fclk_div7_div }, 1, 0); +static CLK_FIXED_FACTOR(g12a_fclk_div2p5_div, 1, 5, 0, { &g12a_fixed_pll_dco }, + 1, 0); +static CLK_GATE(g12a_fclk_div2p5, HHI_FIX_PLL_CNTL1, 25, 0, + { &g12a_fclk_div2p5_div }, 1, 0); +static CLK_FIXED_FACTOR(g12a_mpll_50m_div, 1, 80, 0, { &g12a_fixed_pll_dco }, 1, + 0); const static struct clk_parent_data g12a_mpll_50m_parent_table[] = { { .name = "xtal", }, { .clk = &g12a_mpll_50m_div }, }; -static CLK_MUX_RO(g12a_mpll_50m, HHI_FIX_PLL_CNTL3, 0x1, 5, 0, 0, g12a_mpll_50m_parent_table, 2, 0); -static CLK_FIXED_FACTOR(g12a_mpll_prediv, 1, 2, 0, { &g12a_fixed_pll_dco }, 1, 0); +static CLK_MUX_RO(g12a_mpll_50m, HHI_FIX_PLL_CNTL3, 0x1, 5, 0, 0, + g12a_mpll_50m_parent_table, 2, 0); +static CLK_FIXED_FACTOR(g12a_mpll_prediv, 1, 2, 0, { &g12a_fixed_pll_dco }, 1, + 0); static const struct reg_sequence g12a_mpll0_init_regs[] = { { .reg = HHI_MPLL_CNTL2, .def = 0x40000033 }, @@ -733,10 +787,13 @@ static const struct clk_parent_data clk81_parent_data[] = { { .clk = &g12a_fclk_div3 }, { .clk = &g12a_fclk_div5 }, }; -static CLK_MUX_RO(g12a_mpeg_clk_sel, HHI_MPEG_CLK_CNTL, 0x7, 12, mux_table_clk81, 0, clk81_parent_data, +static CLK_MUX_RO(g12a_mpeg_clk_sel, HHI_MPEG_CLK_CNTL, 0x7, 12, + mux_table_clk81, 0, clk81_parent_data, ARRAY_SIZE(clk81_parent_data), 0); -static CLK_DIV(g12a_mpeg_clk_div, HHI_MPEG_CLK_CNTL, 0, 7, 0, { &g12a_mpeg_clk_sel }, 1, 0); -static CLK_GATE(g12a_clk81, HHI_MPEG_CLK_CNTL, 7, 0, { &g12a_mpeg_clk_div }, 1, 0); +static CLK_DIV(g12a_mpeg_clk_div, HHI_MPEG_CLK_CNTL, 0, 7, 0, + { &g12a_mpeg_clk_sel }, 1, 0); +static CLK_GATE(g12a_clk81, HHI_MPEG_CLK_CNTL, 7, 0, { &g12a_mpeg_clk_div }, 1, + 0); static const struct clk_parent_data g12a_sd_emmc_clk0_parent_data[] = { { .name = "xtal", @@ -746,18 +803,24 @@ static const struct clk_parent_data g12a_sd_emmc_clk0_parent_data[] = { { .clk = &g12a_fclk_div5 }, { .clk = &g12a_fclk_div7 }, }; -static CLK_MUX(g12a_sd_emmc_a_clk0_sel, HHI_SD_EMMC_CLK_CNTL, 0x7, 9, 0, 0, g12a_sd_emmc_clk0_parent_data, 0, - CLK_SET_RATE_PARENT); -static CLK_DIV(g12a_sd_emmc_a_clk0_div, HHI_SD_EMMC_CLK_CNTL, 0, 7, 0, { &g12a_sd_emmc_a_clk0_sel }, 1, 0); -static CLK_GATE(g12a_sd_emmc_a_clk0, HHI_SD_EMMC_CLK_CNTL, 7, 0, { &g12a_sd_emmc_a_clk0_div }, 1, 0); -static CLK_MUX(g12a_sd_emmc_b_clk0_sel, HHI_SD_EMMC_CLK_CNTL, 0x7, 25, 0, 0, g12a_sd_emmc_clk0_parent_data, 0, - CLK_SET_RATE_PARENT); -static CLK_DIV(g12a_sd_emmc_b_clk0_div, HHI_SD_EMMC_CLK_CNTL, 16, 7, 0, { &g12a_sd_emmc_b_clk0_sel }, 1, 0); -static CLK_GATE(g12a_sd_emmc_b_clk0, HHI_SD_EMMC_CLK_CNTL, 23, 0, { &g12a_sd_emmc_b_clk0_div }, 1, 0); -static CLK_MUX(g12a_sd_emmc_c_clk0_sel, HHI_NAND_CLK_CNTL, 0x7, 9, 0, 0, g12a_sd_emmc_clk0_parent_data, 0, - CLK_SET_RATE_PARENT); -static CLK_DIV(g12a_sd_emmc_c_clk0_div, HHI_NAND_CLK_CNTL, 0, 7, 0, { &g12a_sd_emmc_c_clk0_sel }, 1, 0); -static CLK_GATE(g12a_sd_emmc_c_clk0, HHI_NAND_CLK_CNTL, 7, 0, { &g12a_sd_emmc_c_clk0_div }, 1, 0); +static CLK_MUX(g12a_sd_emmc_a_clk0_sel, HHI_SD_EMMC_CLK_CNTL, 0x7, 9, 0, 0, + g12a_sd_emmc_clk0_parent_data, 0, CLK_SET_RATE_PARENT); +static CLK_DIV(g12a_sd_emmc_a_clk0_div, HHI_SD_EMMC_CLK_CNTL, 0, 7, 0, + { &g12a_sd_emmc_a_clk0_sel }, 1, 0); +static CLK_GATE(g12a_sd_emmc_a_clk0, HHI_SD_EMMC_CLK_CNTL, 7, 0, + { &g12a_sd_emmc_a_clk0_div }, 1, 0); +static CLK_MUX(g12a_sd_emmc_b_clk0_sel, HHI_SD_EMMC_CLK_CNTL, 0x7, 25, 0, 0, + g12a_sd_emmc_clk0_parent_data, 0, CLK_SET_RATE_PARENT); +static CLK_DIV(g12a_sd_emmc_b_clk0_div, HHI_SD_EMMC_CLK_CNTL, 16, 7, 0, + { &g12a_sd_emmc_b_clk0_sel }, 1, 0); +static CLK_GATE(g12a_sd_emmc_b_clk0, HHI_SD_EMMC_CLK_CNTL, 23, 0, + { &g12a_sd_emmc_b_clk0_div }, 1, 0); +static CLK_MUX(g12a_sd_emmc_c_clk0_sel, HHI_NAND_CLK_CNTL, 0x7, 9, 0, 0, + g12a_sd_emmc_clk0_parent_data, 0, CLK_SET_RATE_PARENT); +static CLK_DIV(g12a_sd_emmc_c_clk0_div, HHI_NAND_CLK_CNTL, 0, 7, 0, + { &g12a_sd_emmc_c_clk0_sel }, 1, 0); +static CLK_GATE(g12a_sd_emmc_c_clk0, HHI_NAND_CLK_CNTL, 7, 0, + { &g12a_sd_emmc_c_clk0_div }, 1, 0); static struct clk g12a_vid_pll_div = { .data = &(struct meson_vid_pll_div_data){ .val = { @@ -788,9 +851,11 @@ static const struct clk_parent_data g12a_vid_pll_parent_table[] = { }, }; -static CLK_MUX(g12a_vid_pll_sel, HHI_VID_PLL_CLK_DIV, 0x1, 18, 0, 0, g12a_vid_pll_parent_table, 0, +static CLK_MUX(g12a_vid_pll_sel, HHI_VID_PLL_CLK_DIV, 0x1, 18, 0, 0, + g12a_vid_pll_parent_table, 0, CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE); -static CLK_GATE(g12a_vid_pll, HHI_VID_PLL_CLK_DIV, 19, 0, { &g12a_vid_pll_sel }, 1, 0); +static CLK_GATE(g12a_vid_pll, HHI_VID_PLL_CLK_DIV, 19, 0, { &g12a_vid_pll_sel }, + 1, 0); const static struct clk_parent_data g12a_vpu_sel_parent_table[] = { { .clk = &g12a_fclk_div3, @@ -817,17 +882,22 @@ const static struct clk_parent_data g12a_vpu_sel_parent_table[] = { .clk = &g12a_gp0_pll, }, }; -static CLK_MUX(g12a_vpu_0_sel, HHI_VPU_CLK_CNTL, 0x7, 9, 0, 0, g12a_vpu_sel_parent_table, 0, CLK_SET_RATE_NO_REPARENT); -static CLK_DIV(g12a_vpu_0_div, HHI_VPU_CLK_CNTL, 0, 7, 0, { &g12a_vpu_0_sel }, 1, 0); +static CLK_MUX(g12a_vpu_0_sel, HHI_VPU_CLK_CNTL, 0x7, 9, 0, 0, + g12a_vpu_sel_parent_table, 0, CLK_SET_RATE_NO_REPARENT); +static CLK_DIV(g12a_vpu_0_div, HHI_VPU_CLK_CNTL, 0, 7, 0, { &g12a_vpu_0_sel }, + 1, 0); static CLK_GATE(g12a_vpu_0, HHI_VPU_CLK_CNTL, 8, 0, { &g12a_vpu_0_div }, 1, 0); -static CLK_MUX(g12a_vpu_1_sel, HHI_VPU_CLK_CNTL, 0x7, 25, 0, 0, g12a_vpu_sel_parent_table, 0, CLK_SET_RATE_NO_REPARENT); -static CLK_DIV(g12a_vpu_1_div, HHI_VPU_CLK_CNTL, 16, 7, 0, { &g12a_vpu_1_sel }, 1, 0); +static CLK_MUX(g12a_vpu_1_sel, HHI_VPU_CLK_CNTL, 0x7, 25, 0, 0, + g12a_vpu_sel_parent_table, 0, CLK_SET_RATE_NO_REPARENT); +static CLK_DIV(g12a_vpu_1_div, HHI_VPU_CLK_CNTL, 16, 7, 0, { &g12a_vpu_1_sel }, + 1, 0); static CLK_GATE(g12a_vpu_1, HHI_VPU_CLK_CNTL, 24, 0, { &g12a_vpu_1_div }, 1, 0); const struct clk_parent_data g12a_vpu_parent_table[] = { { .clk = &g12a_vpu_0 }, { .clk = &g12a_vpu_1 }, }; -static CLK_MUX(g12a_vpu, HHI_VPU_CLK_CNTL, 1, 31, 0, 0, g12a_vpu_parent_table, 2, 0); +static CLK_MUX(g12a_vpu, HHI_VPU_CLK_CNTL, 1, 31, 0, 0, g12a_vpu_parent_table, + 2, 0); static const struct clk_parent_data g12a_vdec_parent_table[] = { { .clk = &g12a_fclk_div2p5, @@ -852,19 +922,27 @@ static const struct clk_parent_data g12a_vdec_parent_table[] = { }, }; -static CLK_MUX(g12a_vdec_1_sel, HHI_VDEC_CLK_CNTL, 0x7, 9, 0, CLK_MUX_ROUND_CLOSEST, g12a_vdec_parent_table, 0, +static CLK_MUX(g12a_vdec_1_sel, HHI_VDEC_CLK_CNTL, 0x7, 9, 0, + CLK_MUX_ROUND_CLOSEST, g12a_vdec_parent_table, 0, CLK_SET_RATE_PARENT); -static CLK_DIV(g12a_vdec_1_div, HHI_VDEC_CLK_CNTL, 0, 7, CLK_DIVIDER_ROUND_CLOSEST, { &g12a_vdec_1_sel }, 1, 0); -static CLK_GATE(g12a_vdec_1, HHI_VDEC_CLK_CNTL, 8, 0, { &g12a_vdec_1_div }, 1, 0); -static CLK_MUX(g12a_vdec_hevcf_sel, HHI_VDEC2_CLK_CNTL, 0x7, 9, 0, CLK_MUX_ROUND_CLOSEST, g12a_vdec_parent_table, 0, +static CLK_DIV(g12a_vdec_1_div, HHI_VDEC_CLK_CNTL, 0, 7, + CLK_DIVIDER_ROUND_CLOSEST, { &g12a_vdec_1_sel }, 1, 0); +static CLK_GATE(g12a_vdec_1, HHI_VDEC_CLK_CNTL, 8, 0, { &g12a_vdec_1_div }, 1, + 0); +static CLK_MUX(g12a_vdec_hevcf_sel, HHI_VDEC2_CLK_CNTL, 0x7, 9, 0, + CLK_MUX_ROUND_CLOSEST, g12a_vdec_parent_table, 0, CLK_SET_RATE_PARENT); -static CLK_DIV(g12a_vdec_hevcf_div, HHI_VDEC2_CLK_CNTL, 0, 7, CLK_DIVIDER_ROUND_CLOSEST, { &g12a_vdec_hevcf_sel }, 1, - 0); -static CLK_GATE(g12a_vdec_hevcf, HHI_VDEC2_CLK_CNTL, 8, 0, { &g12a_vdec_hevcf_div }, 1, 0); -static CLK_MUX(g12a_vdec_hevc_sel, HHI_VDEC2_CLK_CNTL, 0x7, 25, 0, CLK_MUX_ROUND_CLOSEST, g12a_vdec_parent_table, 0, +static CLK_DIV(g12a_vdec_hevcf_div, HHI_VDEC2_CLK_CNTL, 0, 7, + CLK_DIVIDER_ROUND_CLOSEST, { &g12a_vdec_hevcf_sel }, 1, 0); +static CLK_GATE(g12a_vdec_hevcf, HHI_VDEC2_CLK_CNTL, 8, 0, + { &g12a_vdec_hevcf_div }, 1, 0); +static CLK_MUX(g12a_vdec_hevc_sel, HHI_VDEC2_CLK_CNTL, 0x7, 25, 0, + CLK_MUX_ROUND_CLOSEST, g12a_vdec_parent_table, 0, CLK_SET_RATE_PARENT); -static CLK_DIV(g12a_vdec_hevc_div, HHI_VDEC2_CLK_CNTL, 16, 7, CLK_DIVIDER_ROUND_CLOSEST, { &g12a_vdec_hevc_sel }, 1, 0); -static CLK_GATE(g12a_vdec_hevc, HHI_VDEC2_CLK_CNTL, 24, 0, { &g12a_vdec_hevc_div }, 1, 0); +static CLK_DIV(g12a_vdec_hevc_div, HHI_VDEC2_CLK_CNTL, 16, 7, + CLK_DIVIDER_ROUND_CLOSEST, { &g12a_vdec_hevc_sel }, 1, 0); +static CLK_GATE(g12a_vdec_hevc, HHI_VDEC2_CLK_CNTL, 24, 0, + { &g12a_vdec_hevc_div }, 1, 0); static const struct clk_parent_data g12a_vapb_parent_table[] = { { .clk = &g12a_fclk_div4, @@ -891,17 +969,24 @@ static const struct clk_parent_data g12a_vapb_parent_table[] = { .clk = &g12a_fclk_div2p5, }, }; -static CLK_MUX(g12a_vapb_0_sel, HHI_VAPBCLK_CNTL, 0x3, 9, 0, 0, g12a_vapb_parent_table, 0, CLK_SET_RATE_NO_REPARENT); -static CLK_DIV(g12a_vapb_0_div, HHI_VAPBCLK_CNTL, 0, 7, 0, { &g12a_vapb_0_sel }, 1, 0); -static CLK_GATE(g12a_vapb_0, HHI_VAPBCLK_CNTL, 8, 0, { &g12a_vapb_0_div }, 1, 0); -static CLK_MUX(g12a_vapb_1_sel, HHI_VAPBCLK_CNTL, 0x3, 25, 0, 0, g12a_vapb_parent_table, 0, CLK_SET_RATE_NO_REPARENT); -static CLK_DIV(g12a_vapb_1_div, HHI_VAPBCLK_CNTL, 16, 7, 0, { &g12a_vapb_1_sel }, 1, 0); -static CLK_GATE(g12a_vapb_1, HHI_VAPBCLK_CNTL, 24, 0, { &g12a_vapb_1_div }, 1, 0); +static CLK_MUX(g12a_vapb_0_sel, HHI_VAPBCLK_CNTL, 0x3, 9, 0, 0, + g12a_vapb_parent_table, 0, CLK_SET_RATE_NO_REPARENT); +static CLK_DIV(g12a_vapb_0_div, HHI_VAPBCLK_CNTL, 0, 7, 0, { &g12a_vapb_0_sel }, + 1, 0); +static CLK_GATE(g12a_vapb_0, HHI_VAPBCLK_CNTL, 8, 0, { &g12a_vapb_0_div }, 1, + 0); +static CLK_MUX(g12a_vapb_1_sel, HHI_VAPBCLK_CNTL, 0x3, 25, 0, 0, + g12a_vapb_parent_table, 0, CLK_SET_RATE_NO_REPARENT); +static CLK_DIV(g12a_vapb_1_div, HHI_VAPBCLK_CNTL, 16, 7, 0, + { &g12a_vapb_1_sel }, 1, 0); +static CLK_GATE(g12a_vapb_1, HHI_VAPBCLK_CNTL, 24, 0, { &g12a_vapb_1_div }, 1, + 0); const struct clk_parent_data g12a_vapb_sel_parent_table[] = { { .clk = &g12a_vapb_0 }, { .clk = &g12a_vapb_1 }, }; -static CLK_MUX(g12a_vapb_sel, HHI_VAPBCLK_CNTL, 1, 31, 0, 0, g12a_vapb_sel_parent_table, 2, 0); +static CLK_MUX(g12a_vapb_sel, HHI_VAPBCLK_CNTL, 1, 31, 0, 0, + g12a_vapb_sel_parent_table, 2, 0); static CLK_GATE(g12a_vapb, HHI_VAPBCLK_CNTL, 30, 0, { &g12a_vapb_sel }, 1, 0); static const struct clk_parent_data g12a_vclk_parent_table[] = { { @@ -929,12 +1014,17 @@ static const struct clk_parent_data g12a_vclk_parent_table[] = { .clk = &g12a_fclk_div7, }, }; -static CLK_MUX(g12a_vclk_sel, HHI_VID_CLK_CNTL, 0x7, 16, 0, 0, g12a_vclk_parent_table, 0, +static CLK_MUX(g12a_vclk_sel, HHI_VID_CLK_CNTL, 0x7, 16, 0, 0, + g12a_vclk_parent_table, 0, CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE); -static CLK_MUX(g12a_vclk2_sel, HHI_VIID_CLK_CNTL, 0x7, 16, 0, 0, g12a_vclk_parent_table, 0, CLK_SET_RATE_NO_REPARENT); -static CLK_GATE(g12a_vclk_input, HHI_VID_CLK_DIV, 16, 0, { &g12a_vclk_sel }, 1, 0); -static CLK_GATE(g12a_vclk2_input, HHI_VIID_CLK_DIV, 16, 0, { &g12a_vclk2_sel }, 1, 0); -static CLK_DIV(g12a_vclk_div, HHI_VID_CLK_DIV, 0, 8, 0, { &g12a_vclk_input }, 1, 0); +static CLK_MUX(g12a_vclk2_sel, HHI_VIID_CLK_CNTL, 0x7, 16, 0, 0, + g12a_vclk_parent_table, 0, CLK_SET_RATE_NO_REPARENT); +static CLK_GATE(g12a_vclk_input, HHI_VID_CLK_DIV, 16, 0, { &g12a_vclk_sel }, 1, + 0); +static CLK_GATE(g12a_vclk2_input, HHI_VIID_CLK_DIV, 16, 0, { &g12a_vclk2_sel }, + 1, 0); +static CLK_DIV(g12a_vclk_div, HHI_VID_CLK_DIV, 0, 8, 0, { &g12a_vclk_input }, 1, + 0); static struct clk g12a_vclk2_div = { .data = &(struct meson_vclk_div_data){ .div = { @@ -987,23 +1077,37 @@ static struct clk g12a_vclk2 = { }, }; static CLK_GATE(g12a_vclk_div1, HHI_VID_CLK_CNTL, 0, 0, { &g12a_vclk }, 1, 0); -static CLK_GATE(g12a_vclk_div2_en, HHI_VID_CLK_CNTL, 1, 0, { &g12a_vclk }, 1, 0); -static CLK_GATE(g12a_vclk_div4_en, HHI_VID_CLK_CNTL, 2, 0, { &g12a_vclk }, 1, 0); -static CLK_GATE(g12a_vclk_div6_en, HHI_VID_CLK_CNTL, 3, 0, { &g12a_vclk }, 1, 0); -static CLK_GATE(g12a_vclk_div12_en, HHI_VID_CLK_CNTL, 4, 0, { &g12a_vclk }, 1, 0); -static CLK_GATE(g12a_vclk2_div1, HHI_VIID_CLK_CNTL, 0, 0, { &g12a_vclk2 }, 1, 0); -static CLK_GATE(g12a_vclk2_div2_en, HHI_VIID_CLK_CNTL, 1, 0, { &g12a_vclk2 }, 1, 0); -static CLK_GATE(g12a_vclk2_div4_en, HHI_VIID_CLK_CNTL, 2, 0, { &g12a_vclk2 }, 1, 0); -static CLK_GATE(g12a_vclk2_div6_en, HHI_VIID_CLK_CNTL, 3, 0, { &g12a_vclk2 }, 1, 0); -static CLK_GATE(g12a_vclk2_div12_en, HHI_VIID_CLK_CNTL, 4, 0, { &g12a_vclk2 }, 1, 0); +static CLK_GATE(g12a_vclk_div2_en, HHI_VID_CLK_CNTL, 1, 0, { &g12a_vclk }, 1, + 0); +static CLK_GATE(g12a_vclk_div4_en, HHI_VID_CLK_CNTL, 2, 0, { &g12a_vclk }, 1, + 0); +static CLK_GATE(g12a_vclk_div6_en, HHI_VID_CLK_CNTL, 3, 0, { &g12a_vclk }, 1, + 0); +static CLK_GATE(g12a_vclk_div12_en, HHI_VID_CLK_CNTL, 4, 0, { &g12a_vclk }, 1, + 0); +static CLK_GATE(g12a_vclk2_div1, HHI_VIID_CLK_CNTL, 0, 0, { &g12a_vclk2 }, 1, + 0); +static CLK_GATE(g12a_vclk2_div2_en, HHI_VIID_CLK_CNTL, 1, 0, { &g12a_vclk2 }, 1, + 0); +static CLK_GATE(g12a_vclk2_div4_en, HHI_VIID_CLK_CNTL, 2, 0, { &g12a_vclk2 }, 1, + 0); +static CLK_GATE(g12a_vclk2_div6_en, HHI_VIID_CLK_CNTL, 3, 0, { &g12a_vclk2 }, 1, + 0); +static CLK_GATE(g12a_vclk2_div12_en, HHI_VIID_CLK_CNTL, 4, 0, { &g12a_vclk2 }, + 1, 0); static CLK_FIXED_FACTOR(g12a_vclk_div2, 1, 2, 0, { &g12a_vclk_div2_en }, 1, 0); static CLK_FIXED_FACTOR(g12a_vclk_div4, 1, 4, 0, { &g12a_vclk_div4_en }, 1, 0); static CLK_FIXED_FACTOR(g12a_vclk_div6, 1, 6, 0, { &g12a_vclk_div6_en }, 1, 0); -static CLK_FIXED_FACTOR(g12a_vclk_div12, 1, 12, 0, { &g12a_vclk_div12_en }, 1, 0); -static CLK_FIXED_FACTOR(g12a_vclk2_div2, 1, 2, 0, { &g12a_vclk2_div2_en }, 1, 0); -static CLK_FIXED_FACTOR(g12a_vclk2_div4, 1, 4, 0, { &g12a_vclk2_div4_en }, 1, 0); -static CLK_FIXED_FACTOR(g12a_vclk2_div6, 1, 6, 0, { &g12a_vclk2_div6_en }, 1, 0); -static CLK_FIXED_FACTOR(g12a_vclk2_div12, 1, 12, 0, { &g12a_vclk2_div12_en }, 1, 0); +static CLK_FIXED_FACTOR(g12a_vclk_div12, 1, 12, 0, { &g12a_vclk_div12_en }, 1, + 0); +static CLK_FIXED_FACTOR(g12a_vclk2_div2, 1, 2, 0, { &g12a_vclk2_div2_en }, 1, + 0); +static CLK_FIXED_FACTOR(g12a_vclk2_div4, 1, 4, 0, { &g12a_vclk2_div4_en }, 1, + 0); +static CLK_FIXED_FACTOR(g12a_vclk2_div6, 1, 6, 0, { &g12a_vclk2_div6_en }, 1, + 0); +static CLK_FIXED_FACTOR(g12a_vclk2_div12, 1, 12, 0, { &g12a_vclk2_div12_en }, 1, + 0); static uint32_t mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; static const struct clk_parent_data g12a_cts_parent_table[] = { { @@ -1037,14 +1141,18 @@ static const struct clk_parent_data g12a_cts_parent_table[] = { .clk = &g12a_vclk2_div12, }, }; -static CLK_MUX(g12a_cts_enci_sel, HHI_VID_CLK_DIV, 0xf, 28, mux_table_cts_sel, 0, g12a_cts_parent_table, - ARRAY_SIZE(g12a_cts_parent_table), CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE); -static CLK_MUX(g12a_cts_encp_sel, HHI_VID_CLK_DIV, 0xf, 20, mux_table_cts_sel, 0, g12a_cts_parent_table, - ARRAY_SIZE(g12a_cts_parent_table), CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE); -static CLK_MUX(g12a_cts_encl_sel, HHI_VIID_CLK_DIV, 0xf, 12, mux_table_cts_sel, 0, g12a_cts_parent_table, - ARRAY_SIZE(g12a_cts_parent_table), CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT); -static CLK_MUX(g12a_cts_vdac_sel, HHI_VIID_CLK_DIV, 0xf, 28, mux_table_cts_sel, 0, g12a_cts_parent_table, - ARRAY_SIZE(g12a_cts_parent_table), CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE); +static CLK_MUX(g12a_cts_enci_sel, HHI_VID_CLK_DIV, 0xf, 28, mux_table_cts_sel, + 0, g12a_cts_parent_table, ARRAY_SIZE(g12a_cts_parent_table), + CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE); +static CLK_MUX(g12a_cts_encp_sel, HHI_VID_CLK_DIV, 0xf, 20, mux_table_cts_sel, + 0, g12a_cts_parent_table, ARRAY_SIZE(g12a_cts_parent_table), + CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE); +static CLK_MUX(g12a_cts_encl_sel, HHI_VIID_CLK_DIV, 0xf, 12, mux_table_cts_sel, + 0, g12a_cts_parent_table, ARRAY_SIZE(g12a_cts_parent_table), + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT); +static CLK_MUX(g12a_cts_vdac_sel, HHI_VIID_CLK_DIV, 0xf, 28, mux_table_cts_sel, + 0, g12a_cts_parent_table, ARRAY_SIZE(g12a_cts_parent_table), + CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE); static uint32_t mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; static const struct clk_parent_data g12a_cts_hdmi_tx_parent_table[] = { { @@ -1078,13 +1186,20 @@ static const struct clk_parent_data g12a_cts_hdmi_tx_parent_table[] = { .clk = &g12a_vclk2_div12, }, }; -static CLK_MUX(g12a_hdmi_tx_sel, HHI_HDMI_CLK_CNTL, 0xf, 16, mux_table_hdmi_tx_sel, 0, g12a_cts_hdmi_tx_parent_table, - ARRAY_SIZE(g12a_cts_hdmi_tx_parent_table), CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE); -static CLK_GATE(g12a_cts_enci, HHI_VID_CLK_CNTL2, 0, 0, { &g12a_cts_enci_sel }, 1, 0); -static CLK_GATE(g12a_cts_encp, HHI_VID_CLK_CNTL2, 2, 0, { &g12a_cts_encp_sel }, 1, 0); -static CLK_GATE(g12a_cts_encl, HHI_VID_CLK_CNTL2, 3, 0, { &g12a_cts_encl_sel }, 1, 0); -static CLK_GATE(g12a_cts_vdac, HHI_VID_CLK_CNTL2, 4, 0, { &g12a_cts_vdac_sel }, 1, 0); -static CLK_GATE(g12a_hdmi_tx, HHI_VID_CLK_CNTL2, 5, 0, { &g12a_hdmi_tx_sel }, 1, 0); +static CLK_MUX(g12a_hdmi_tx_sel, HHI_HDMI_CLK_CNTL, 0xf, 16, + mux_table_hdmi_tx_sel, 0, g12a_cts_hdmi_tx_parent_table, + ARRAY_SIZE(g12a_cts_hdmi_tx_parent_table), + CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE); +static CLK_GATE(g12a_cts_enci, HHI_VID_CLK_CNTL2, 0, 0, { &g12a_cts_enci_sel }, + 1, 0); +static CLK_GATE(g12a_cts_encp, HHI_VID_CLK_CNTL2, 2, 0, { &g12a_cts_encp_sel }, + 1, 0); +static CLK_GATE(g12a_cts_encl, HHI_VID_CLK_CNTL2, 3, 0, { &g12a_cts_encl_sel }, + 1, 0); +static CLK_GATE(g12a_cts_vdac, HHI_VID_CLK_CNTL2, 4, 0, { &g12a_cts_vdac_sel }, + 1, 0); +static CLK_GATE(g12a_hdmi_tx, HHI_VID_CLK_CNTL2, 5, 0, { &g12a_hdmi_tx_sel }, 1, + 0); static const struct clk_parent_data g12a_mipi_dsi_pxclk_parent_table[] = { { .clk = &g12a_vid_pll, @@ -1111,11 +1226,14 @@ static const struct clk_parent_data g12a_mipi_dsi_pxclk_parent_table[] = { .clk = &g12a_fclk_div7, }, }; -static CLK_MUX(g12a_mipi_dsi_pxclk_sel, HHI_MIPIDSI_PHY_CLK_CNTL, 0x7, 12, 0, CLK_MUX_ROUND_CLOSEST, - g12a_mipi_dsi_pxclk_parent_table, ARRAY_SIZE(g12a_mipi_dsi_pxclk_parent_table), +static CLK_MUX(g12a_mipi_dsi_pxclk_sel, HHI_MIPIDSI_PHY_CLK_CNTL, 0x7, 12, 0, + CLK_MUX_ROUND_CLOSEST, g12a_mipi_dsi_pxclk_parent_table, + ARRAY_SIZE(g12a_mipi_dsi_pxclk_parent_table), CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT); -static CLK_DIV(g12a_mipi_dsi_pxclk_div, HHI_MIPIDSI_PHY_CLK_CNTL, 0, 7, 0, { &g12a_mipi_dsi_pxclk_sel }, 1, 0); -static CLK_GATE(g12a_mipi_dsi_pxclk, HHI_MIPIDSI_PHY_CLK_CNTL, 8, 0, { &g12a_mipi_dsi_pxclk_div }, 1, 0); +static CLK_DIV(g12a_mipi_dsi_pxclk_div, HHI_MIPIDSI_PHY_CLK_CNTL, 0, 7, 0, + { &g12a_mipi_dsi_pxclk_sel }, 1, 0); +static CLK_GATE(g12a_mipi_dsi_pxclk, HHI_MIPIDSI_PHY_CLK_CNTL, 8, 0, + { &g12a_mipi_dsi_pxclk_div }, 1, 0); static const struct clk_parent_data g12a_hdmi_parent_table[] = { { .name = "xtal", @@ -1124,9 +1242,12 @@ static const struct clk_parent_data g12a_hdmi_parent_table[] = { { .clk = &g12a_fclk_div3 }, { .clk = &g12a_fclk_div5 }, }; -static CLK_MUX(g12a_hdmi_sel, HHI_HDMI_CLK_CNTL, 0x3, 9, 0, CLK_MUX_ROUND_CLOSEST, g12a_hdmi_parent_table, - ARRAY_SIZE(g12a_hdmi_parent_table), CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE); -static CLK_DIV(g12a_hdmi_div, HHI_HDMI_CLK_CNTL, 0, 7, 0, { &g12a_hdmi_sel }, 1, 0); +static CLK_MUX(g12a_hdmi_sel, HHI_HDMI_CLK_CNTL, 0x3, 9, 0, + CLK_MUX_ROUND_CLOSEST, g12a_hdmi_parent_table, + ARRAY_SIZE(g12a_hdmi_parent_table), + CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE); +static CLK_DIV(g12a_hdmi_div, HHI_HDMI_CLK_CNTL, 0, 7, 0, { &g12a_hdmi_sel }, 1, + 0); static CLK_GATE(g12a_hdmi, HHI_HDMI_CLK_CNTL, 8, 0, { &g12a_hdmi_div }, 1, 0); static const struct clk_parent_data g12a_mali_0_1_parent_data[] = { { @@ -1140,12 +1261,18 @@ static const struct clk_parent_data g12a_mali_0_1_parent_data[] = { { .clk = &g12a_fclk_div5 }, { .clk = &g12a_fclk_div7 }, }; -static CLK_MUX(g12a_mali_0_sel, HHI_MALI_CLK_CNTL, 0x7, 9, 0, 0, g12a_mali_0_1_parent_data, 8, 0); -static CLK_DIV(g12a_mali_0_div, HHI_MALI_CLK_CNTL, 0, 7, 0, { &g12a_mali_0_sel }, 1, 0); -static CLK_GATE(g12a_mali_0, HHI_MALI_CLK_CNTL, 8, 0, { &g12a_mali_0_div }, 1, 0); -static CLK_MUX(g12a_mali_1_sel, HHI_MALI_CLK_CNTL, 0x7, 25, 0, 0, g12a_mali_0_1_parent_data, 8, 0); -static CLK_DIV(g12a_mali_1_div, HHI_MALI_CLK_CNTL, 16, 7, 0, { &g12a_mali_1_sel }, 1, 0); -static CLK_GATE(g12a_mali_1, HHI_MALI_CLK_CNTL, 24, 0, { &g12a_mali_1_div }, 1, 0); +static CLK_MUX(g12a_mali_0_sel, HHI_MALI_CLK_CNTL, 0x7, 9, 0, 0, + g12a_mali_0_1_parent_data, 8, 0); +static CLK_DIV(g12a_mali_0_div, HHI_MALI_CLK_CNTL, 0, 7, 0, + { &g12a_mali_0_sel }, 1, 0); +static CLK_GATE(g12a_mali_0, HHI_MALI_CLK_CNTL, 8, 0, { &g12a_mali_0_div }, 1, + 0); +static CLK_MUX(g12a_mali_1_sel, HHI_MALI_CLK_CNTL, 0x7, 25, 0, 0, + g12a_mali_0_1_parent_data, 8, 0); +static CLK_DIV(g12a_mali_1_div, HHI_MALI_CLK_CNTL, 16, 7, 0, + { &g12a_mali_1_sel }, 1, 0); +static CLK_GATE(g12a_mali_1, HHI_MALI_CLK_CNTL, 24, 0, { &g12a_mali_1_div }, 1, + 0); static const struct clk_parent_data g12a_mali_parent_table[] = { { .clk = &g12a_mali_0, @@ -1154,8 +1281,10 @@ static const struct clk_parent_data g12a_mali_parent_table[] = { .clk = &g12a_mali_1, }, }; -static CLK_MUX(g12a_mali, HHI_MALI_CLK_CNTL, 1, 31, 0, 0, g12a_mali_parent_table, 2, CLK_SET_RATE_PARENT); -static CLK_DIV_RO(g12a_ts_div, HHI_TS_CLK_CNTL, 0, 8, 0, { &g12a_ts_div }, 1, 0); +static CLK_MUX(g12a_mali, HHI_MALI_CLK_CNTL, 1, 31, 0, 0, + g12a_mali_parent_table, 2, CLK_SET_RATE_PARENT); +static CLK_DIV_RO(g12a_ts_div, HHI_TS_CLK_CNTL, 0, 8, 0, { &g12a_ts_div }, 1, + 0); static CLK_GATE(g12a_ts, HHI_TS_CLK_CNTL, 8, 0, { &g12a_ts_div }, 1, 0); static const struct clk_parent_data spicc_sclk_parent_data[] = { { @@ -1168,12 +1297,18 @@ static const struct clk_parent_data spicc_sclk_parent_data[] = { { .clk = &g12a_fclk_div7 }, }; -static CLK_MUX(g12a_spicc0_sclk_sel, HHI_SPICC_CLK_CNTL, 7, 7, 0, 0, spicc_sclk_parent_data, 0, 0); -static CLK_DIV(g12a_spicc0_sclk_div, HHI_SPICC_CLK_CNTL, 0, 6, 0, { &g12a_spicc0_sclk_sel }, 1, 0); -static CLK_GATE(g12a_spicc0_sclk, HHI_SPICC_CLK_CNTL, 6, 0, { &g12a_spicc0_sclk_div }, 1, 0); -static CLK_MUX(g12a_spicc1_sclk_sel, HHI_SPICC_CLK_CNTL, 7, 23, 0, 0, spicc_sclk_parent_data, 0, 0); -static CLK_DIV(g12a_spicc1_sclk_div, HHI_SPICC_CLK_CNTL, 16, 6, 0, { &g12a_spicc1_sclk_sel }, 1, 0); -static CLK_GATE(g12a_spicc1_sclk, HHI_SPICC_CLK_CNTL, 22, 0, { &g12a_spicc1_sclk_div }, 1, 0); +static CLK_MUX(g12a_spicc0_sclk_sel, HHI_SPICC_CLK_CNTL, 7, 7, 0, 0, + spicc_sclk_parent_data, 0, 0); +static CLK_DIV(g12a_spicc0_sclk_div, HHI_SPICC_CLK_CNTL, 0, 6, 0, + { &g12a_spicc0_sclk_sel }, 1, 0); +static CLK_GATE(g12a_spicc0_sclk, HHI_SPICC_CLK_CNTL, 6, 0, + { &g12a_spicc0_sclk_div }, 1, 0); +static CLK_MUX(g12a_spicc1_sclk_sel, HHI_SPICC_CLK_CNTL, 7, 23, 0, 0, + spicc_sclk_parent_data, 0, 0); +static CLK_DIV(g12a_spicc1_sclk_div, HHI_SPICC_CLK_CNTL, 16, 6, 0, + { &g12a_spicc1_sclk_sel }, 1, 0); +static CLK_GATE(g12a_spicc1_sclk, HHI_SPICC_CLK_CNTL, 22, 0, + { &g12a_spicc1_sclk_div }, 1, 0); static const struct clk_parent_data nna_clk_parent_data[] = { { .name = "xtal", @@ -1198,12 +1333,18 @@ static const struct clk_parent_data nna_clk_parent_data[] = { }, { .clk = &g12a_fclk_div7 }, }; -static CLK_MUX(sm1_nna_axi_clk_sel, HHI_NNA_CLK_CNTL, 7, 9, 0, 0, nna_clk_parent_data, 0, 0); -static CLK_DIV(sm1_nna_axi_clk_div, HHI_NNA_CLK_CNTL, 0, 7, 0, { &sm1_nna_axi_clk_sel }, 1, 0); -static CLK_GATE(sm1_nna_axi_clk, HHI_NNA_CLK_CNTL, 8, 0, { &sm1_nna_axi_clk_div }, 1, 0); -static CLK_MUX(sm1_nna_core_clk_sel, HHI_NNA_CLK_CNTL, 7, 25, 0, 0, nna_clk_parent_data, 0, 0); -static CLK_DIV(sm1_nna_core_clk_div, HHI_NNA_CLK_CNTL, 16, 7, 0, { &sm1_nna_core_clk_sel }, 1, 0); -static CLK_GATE(sm1_nna_core_clk, HHI_NNA_CLK_CNTL, 24, 0, { &sm1_nna_core_clk_div }, 1, 0); +static CLK_MUX(sm1_nna_axi_clk_sel, HHI_NNA_CLK_CNTL, 7, 9, 0, 0, + nna_clk_parent_data, 0, 0); +static CLK_DIV(sm1_nna_axi_clk_div, HHI_NNA_CLK_CNTL, 0, 7, 0, + { &sm1_nna_axi_clk_sel }, 1, 0); +static CLK_GATE(sm1_nna_axi_clk, HHI_NNA_CLK_CNTL, 8, 0, + { &sm1_nna_axi_clk_div }, 1, 0); +static CLK_MUX(sm1_nna_core_clk_sel, HHI_NNA_CLK_CNTL, 7, 25, 0, 0, + nna_clk_parent_data, 0, 0); +static CLK_DIV(sm1_nna_core_clk_div, HHI_NNA_CLK_CNTL, 16, 7, 0, + { &sm1_nna_core_clk_sel }, 1, 0); +static CLK_GATE(sm1_nna_core_clk, HHI_NNA_CLK_CNTL, 24, 0, + { &sm1_nna_core_clk_div }, 1, 0); /* Everything Else (EE) domain gates */ static MESON_CLK81_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0); diff --git a/include/sddf/clk/client.h b/include/sddf/clk/client.h index 8d0d51e6c..d5dc3e937 100644 --- a/include/sddf/clk/client.h +++ b/include/sddf/clk/client.h @@ -16,7 +16,8 @@ * @param channel of clock driver. * @param identifier of target clock. */ -static inline uint32_t sddf_clk_enable(microkit_channel channel, uint32_t clk_id) +static inline uint32_t sddf_clk_enable(microkit_channel channel, + uint32_t clk_id) { microkit_msginfo msginfo = microkit_msginfo_new(SDDF_CLK_ENABLE, 1); microkit_mr_set(SDDF_CLK_PARAM_ID, clk_id); @@ -32,7 +33,8 @@ static inline uint32_t sddf_clk_enable(microkit_channel channel, uint32_t clk_id * @param channel of clock driver. * @param identifier of target clock. */ -static inline uint32_t sddf_clk_disable(microkit_channel channel, uint32_t clk_id) +static inline uint32_t sddf_clk_disable(microkit_channel channel, + uint32_t clk_id) { microkit_msginfo msginfo = microkit_msginfo_new(SDDF_CLK_DISABLE, 1); microkit_mr_set(SDDF_CLK_PARAM_ID, clk_id); @@ -49,7 +51,8 @@ static inline uint32_t sddf_clk_disable(microkit_channel channel, uint32_t clk_i * @param identifier of target clock. * @param pointer to result variable. */ -static inline uint32_t sddf_clk_get_rate(microkit_channel channel, uint32_t clk_id, uint64_t *rate) +static inline uint32_t sddf_clk_get_rate(microkit_channel channel, + uint32_t clk_id, uint64_t *rate) { microkit_msginfo msginfo = microkit_msginfo_new(SDDF_CLK_GET_RATE, 1); microkit_mr_set(SDDF_CLK_PARAM_ID, clk_id); @@ -68,7 +71,9 @@ static inline uint32_t sddf_clk_get_rate(microkit_channel channel, uint32_t clk_ * @param target clock frequency. * @param pointer to result variable. */ -static inline uint32_t sddf_clk_set_rate(microkit_channel channel, uint32_t clk_id, uint64_t req_rate, uint64_t *rate) +static inline uint32_t sddf_clk_set_rate(microkit_channel channel, + uint32_t clk_id, uint64_t req_rate, + uint64_t *rate) { microkit_msginfo msginfo = microkit_msginfo_new(SDDF_CLK_SET_RATE, 2); microkit_mr_set(SDDF_CLK_PARAM_ID, clk_id);