From cb538f0d8a08fdecc38282214877a406338574bd Mon Sep 17 00:00:00 2001 From: Derek Hower <134728312+dhower-qc@users.noreply.github.com> Date: Tue, 22 Oct 2024 15:49:50 -0700 Subject: [PATCH] Remove extra sail() property in inst yaml (#162) --- arch/inst/A/amoadd.d.yaml | 92 ------------------------------------- arch/inst/A/amoadd.w.yaml | 92 ------------------------------------- arch/inst/A/amoand.d.yaml | 92 ------------------------------------- arch/inst/A/amoand.w.yaml | 92 ------------------------------------- arch/inst/A/amomax.d.yaml | 92 ------------------------------------- arch/inst/A/amomax.w.yaml | 92 ------------------------------------- arch/inst/A/amomaxu.d.yaml | 92 ------------------------------------- arch/inst/A/amomaxu.w.yaml | 92 ------------------------------------- arch/inst/A/amomin.d.yaml | 92 ------------------------------------- arch/inst/A/amomin.w.yaml | 92 ------------------------------------- arch/inst/A/amominu.d.yaml | 92 ------------------------------------- arch/inst/A/amominu.w.yaml | 92 ------------------------------------- arch/inst/A/amoor.d.yaml | 92 ------------------------------------- arch/inst/A/amoor.w.yaml | 92 ------------------------------------- arch/inst/A/amoswap.d.yaml | 92 ------------------------------------- arch/inst/A/amoswap.w.yaml | 92 ------------------------------------- arch/inst/A/amoxor.d.yaml | 92 ------------------------------------- arch/inst/A/amoxor.w.yaml | 92 ------------------------------------- arch/inst/A/lr.d.yaml | 44 ------------------ arch/inst/A/lr.w.yaml | 44 ------------------ arch/inst/A/sc.d.yaml | 78 ------------------------------- arch/inst/A/sc.w.yaml | 78 ------------------------------- arch/inst/B/add.uw.yaml | 16 ------- arch/inst/B/andn.yaml | 24 ---------- arch/inst/B/bclr.yaml | 18 -------- arch/inst/B/bclri.yaml | 17 ------- arch/inst/B/bext.yaml | 18 -------- arch/inst/B/bexti.yaml | 17 ------- arch/inst/B/binv.yaml | 18 -------- arch/inst/B/binvi.yaml | 17 ------- arch/inst/B/bset.yaml | 18 -------- arch/inst/B/bseti.yaml | 17 ------- arch/inst/B/clmul.yaml | 12 ----- arch/inst/B/clmulh.yaml | 12 ----- arch/inst/B/clmulr.yaml | 12 ----- arch/inst/B/clz.yaml | 14 ------ arch/inst/B/clzw.yaml | 14 ------ arch/inst/B/cpop.yaml | 11 ----- arch/inst/B/cpopw.yaml | 11 ----- arch/inst/B/ctz.yaml | 14 ------ arch/inst/B/ctzw.yaml | 14 ------ arch/inst/B/max.yaml | 24 ---------- arch/inst/B/maxu.yaml | 24 ---------- arch/inst/B/min.yaml | 24 ---------- arch/inst/B/minu.yaml | 24 ---------- arch/inst/B/orc.b.yaml | 13 ------ arch/inst/B/orn.yaml | 24 ---------- arch/inst/B/rev8.yaml | 11 ----- arch/inst/B/rol.yaml | 24 ---------- arch/inst/B/rolw.yaml | 13 ------ arch/inst/B/ror.yaml | 24 ---------- arch/inst/B/rori.yaml | 11 ----- arch/inst/B/roriw.yaml | 9 ---- arch/inst/B/rorw.yaml | 13 ------ arch/inst/B/sext.b.yaml | 13 ------ arch/inst/B/sext.h.yaml | 13 ------ arch/inst/B/sh1add.uw.yaml | 16 ------- arch/inst/B/sh1add.yaml | 15 ------ arch/inst/B/sh2add.uw.yaml | 16 ------- arch/inst/B/sh2add.yaml | 15 ------ arch/inst/B/sh3add.uw.yaml | 16 ------- arch/inst/B/sh3add.yaml | 15 ------ arch/inst/B/slli.uw.yaml | 9 ---- arch/inst/B/xnor.yaml | 24 ---------- arch/inst/B/zext.h.yaml | 13 ------ arch/inst/F/fadd.s.yaml | 22 --------- arch/inst/F/fclass.s.yaml | 9 ---- arch/inst/F/fcvt.l.s.yaml | 18 -------- arch/inst/F/fcvt.lu.s.yaml | 18 -------- arch/inst/F/fcvt.s.l.yaml | 18 -------- arch/inst/F/fcvt.s.lu.yaml | 18 -------- arch/inst/F/fcvt.s.w.yaml | 18 -------- arch/inst/F/fcvt.s.wu.yaml | 18 -------- arch/inst/F/fcvt.w.s.yaml | 18 -------- arch/inst/F/fcvt.wu.s.yaml | 18 -------- arch/inst/F/fdiv.s.yaml | 22 --------- arch/inst/F/feq.s.yaml | 14 ------ arch/inst/F/fle.s.yaml | 14 ------ arch/inst/F/fleq.s.yaml | 14 ------ arch/inst/F/fli.s.yaml | 41 ----------------- arch/inst/F/flt.s.yaml | 14 ------ arch/inst/F/fltq.s.yaml | 14 ------ arch/inst/F/flw.yaml | 30 ------------ arch/inst/F/fmadd.s.yaml | 24 ---------- arch/inst/F/fmax.s.yaml | 14 ------ arch/inst/F/fmaxm.s.yaml | 20 -------- arch/inst/F/fmin.s.yaml | 14 ------ arch/inst/F/fminm.s.yaml | 20 -------- arch/inst/F/fmsub.s.yaml | 24 ---------- arch/inst/F/fmul.s.yaml | 22 --------- arch/inst/F/fmv.w.x.yaml | 9 ---- arch/inst/F/fmv.x.w.yaml | 9 ---- arch/inst/F/fnmadd.s.yaml | 24 ---------- arch/inst/F/fnmsub.s.yaml | 24 ---------- arch/inst/F/fround.s.yaml | 18 -------- arch/inst/F/froundnx.s.yaml | 18 -------- arch/inst/F/fsgnj.s.yaml | 14 ------ arch/inst/F/fsgnjn.s.yaml | 14 ------ arch/inst/F/fsgnjx.s.yaml | 14 ------ arch/inst/F/fsqrt.s.yaml | 18 -------- arch/inst/F/fsub.s.yaml | 22 --------- arch/inst/F/fsw.yaml | 40 ---------------- arch/inst/I/add.yaml | 27 ----------- arch/inst/I/addi.yaml | 17 ------- arch/inst/I/addiw.yaml | 8 ---- arch/inst/I/addw.yaml | 16 ------- arch/inst/I/and.yaml | 27 ----------- arch/inst/I/andi.yaml | 17 ------- arch/inst/I/beq.yaml | 34 -------------- arch/inst/I/bge.yaml | 34 -------------- arch/inst/I/bgeu.yaml | 34 -------------- arch/inst/I/blt.yaml | 34 -------------- arch/inst/I/bltu.yaml | 34 -------------- arch/inst/I/bne.yaml | 34 -------------- arch/inst/I/ebreak.yaml | 7 --- arch/inst/I/ecall.yaml | 15 ------ arch/inst/I/fence.yaml | 28 ----------- arch/inst/I/jal.yaml | 25 ---------- arch/inst/I/jalr.yaml | 30 ------------ arch/inst/I/lb.yaml | 29 ------------ arch/inst/I/lbu.yaml | 29 ------------ arch/inst/I/ld.yaml | 29 ------------ arch/inst/I/lh.yaml | 29 ------------ arch/inst/I/lhu.yaml | 29 ------------ arch/inst/I/lui.yaml | 12 ----- arch/inst/I/lw.yaml | 29 ------------ arch/inst/I/lwu.yaml | 29 ------------ arch/inst/I/mret.yaml | 13 ------ arch/inst/I/or.yaml | 27 ----------- arch/inst/I/ori.yaml | 17 ------- arch/inst/I/sb.yaml | 44 ------------------ arch/inst/I/sd.yaml | 44 ------------------ arch/inst/I/sh.yaml | 44 ------------------ arch/inst/I/sll.yaml | 27 ----------- arch/inst/I/slli.yaml | 20 -------- arch/inst/I/slliw.yaml | 13 ------ arch/inst/I/sllw.yaml | 16 ------- arch/inst/I/slt.yaml | 27 ----------- arch/inst/I/slti.yaml | 17 ------- arch/inst/I/sltiu.yaml | 17 ------- arch/inst/I/sltu.yaml | 27 ----------- arch/inst/I/sra.yaml | 27 ----------- arch/inst/I/srai.yaml | 20 -------- arch/inst/I/sraiw.yaml | 13 ------ arch/inst/I/sraw.yaml | 16 ------- arch/inst/I/srl.yaml | 27 ----------- arch/inst/I/srli.yaml | 20 -------- arch/inst/I/srliw.yaml | 13 ------ arch/inst/I/srlw.yaml | 16 ------- arch/inst/I/sub.yaml | 27 ----------- arch/inst/I/subw.yaml | 16 ------- arch/inst/I/sw.yaml | 44 ------------------ arch/inst/I/wfi.yaml | 10 ---- arch/inst/I/xor.yaml | 27 ----------- arch/inst/I/xori.yaml | 17 ------- arch/inst/M/div.yaml | 19 -------- arch/inst/M/divu.yaml | 19 -------- arch/inst/M/divuw.yaml | 19 -------- arch/inst/M/divw.yaml | 19 -------- arch/inst/M/mul.yaml | 20 -------- arch/inst/M/mulh.yaml | 20 -------- arch/inst/M/mulhsu.yaml | 20 -------- arch/inst/M/mulhu.yaml | 20 -------- arch/inst/M/mulw.yaml | 19 -------- arch/inst/M/rem.yaml | 18 -------- arch/inst/M/remu.yaml | 18 -------- arch/inst/M/remuw.yaml | 18 -------- arch/inst/M/remw.yaml | 18 -------- arch/inst/S/sfence.vma.yaml | 16 ------- arch/inst/S/sret.yaml | 18 -------- arch/inst/V/vsetvli.yaml | 71 ---------------------------- arch/inst/Zfh/fcvt.h.s.yaml | 18 -------- arch/inst/Zfh/fcvt.s.h.yaml | 18 -------- arch/inst/Zfh/flh.yaml | 30 ------------ arch/inst/Zfh/fmv.h.x.yaml | 9 ---- arch/inst/Zfh/fmv.x.h.yaml | 9 ---- arch/inst/Zfh/fsh.yaml | 40 ---------------- arch/inst/Zicsr/csrrs.yaml | 27 ----------- arch/inst/Zicsr/csrrw.yaml | 27 ----------- arch/inst/Zicsr/csrrwi.yaml | 27 ----------- 180 files changed, 5136 deletions(-) diff --git a/arch/inst/A/amoadd.d.yaml b/arch/inst/A/amoadd.d.yaml index e3a32f25b..a14aa88fe 100644 --- a/arch/inst/A/amoadd.d.yaml +++ b/arch/inst/A/amoadd.d.yaml @@ -138,95 +138,3 @@ amoadd.d: - sail(): | - { - if extension("A") then { - /* Get the address, X(rs1) (no offset). - * Some extensions perform additional checks on address validity. - */ - match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => { - match translateAddr(vaddr, ReadWrite(Data, Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => { - let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), - (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), - (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), - (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - let is_unsigned : bool = match op { - AMOMINU => true, - AMOMAXU => true, - _ => false - }; - let rs2_val : xlenbits = match width { - BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), - HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), - WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), - DOUBLE => X(rs2) - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { - (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), - (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), - (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), - (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (mval) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(loaded) => { - let result : xlenbits = - match op { - AMOSWAP => rs2_val, - AMOADD => rs2_val + loaded, - AMOXOR => rs2_val ^ loaded, - AMOAND => rs2_val & loaded, - AMOOR => rs2_val | loaded, - - /* These operations convert bitvectors to integer values using [un]signed, - * and back using to_bits(). - */ - AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), - AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), - AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), - AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) - }; - let rval : xlenbits = match width { - BYTE => sign_extend(loaded[7..0]), - HALF => sign_extend(loaded[15..0]), - WORD => sign_extend(loaded[31..0]), - DOUBLE => loaded - }; - let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), - (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), - (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), - (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (wval) { - MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, - MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } - } - } - } - } - } - } - } - } - } - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/A/amoadd.w.yaml b/arch/inst/A/amoadd.w.yaml index 9e77dfc98..6080ae954 100644 --- a/arch/inst/A/amoadd.w.yaml +++ b/arch/inst/A/amoadd.w.yaml @@ -137,95 +137,3 @@ amoadd.w: - sail(): | - { - if extension("A") then { - /* Get the address, X(rs1) (no offset). - * Some extensions perform additional checks on address validity. - */ - match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => { - match translateAddr(vaddr, ReadWrite(Data, Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => { - let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), - (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), - (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), - (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - let is_unsigned : bool = match op { - AMOMINU => true, - AMOMAXU => true, - _ => false - }; - let rs2_val : xlenbits = match width { - BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), - HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), - WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), - DOUBLE => X(rs2) - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { - (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), - (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), - (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), - (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (mval) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(loaded) => { - let result : xlenbits = - match op { - AMOSWAP => rs2_val, - AMOADD => rs2_val + loaded, - AMOXOR => rs2_val ^ loaded, - AMOAND => rs2_val & loaded, - AMOOR => rs2_val | loaded, - - /* These operations convert bitvectors to integer values using [un]signed, - * and back using to_bits(). - */ - AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), - AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), - AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), - AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) - }; - let rval : xlenbits = match width { - BYTE => sign_extend(loaded[7..0]), - HALF => sign_extend(loaded[15..0]), - WORD => sign_extend(loaded[31..0]), - DOUBLE => loaded - }; - let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), - (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), - (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), - (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (wval) { - MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, - MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } - } - } - } - } - } - } - } - } - } - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/A/amoand.d.yaml b/arch/inst/A/amoand.d.yaml index 17612756c..5c8742375 100644 --- a/arch/inst/A/amoand.d.yaml +++ b/arch/inst/A/amoand.d.yaml @@ -138,95 +138,3 @@ amoand.d: - sail(): | - { - if extension("A") then { - /* Get the address, X(rs1) (no offset). - * Some extensions perform additional checks on address validity. - */ - match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => { - match translateAddr(vaddr, ReadWrite(Data, Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => { - let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), - (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), - (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), - (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - let is_unsigned : bool = match op { - AMOMINU => true, - AMOMAXU => true, - _ => false - }; - let rs2_val : xlenbits = match width { - BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), - HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), - WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), - DOUBLE => X(rs2) - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { - (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), - (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), - (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), - (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (mval) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(loaded) => { - let result : xlenbits = - match op { - AMOSWAP => rs2_val, - AMOADD => rs2_val + loaded, - AMOXOR => rs2_val ^ loaded, - AMOAND => rs2_val & loaded, - AMOOR => rs2_val | loaded, - - /* These operations convert bitvectors to integer values using [un]signed, - * and back using to_bits(). - */ - AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), - AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), - AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), - AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) - }; - let rval : xlenbits = match width { - BYTE => sign_extend(loaded[7..0]), - HALF => sign_extend(loaded[15..0]), - WORD => sign_extend(loaded[31..0]), - DOUBLE => loaded - }; - let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), - (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), - (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), - (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (wval) { - MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, - MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } - } - } - } - } - } - } - } - } - } - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/A/amoand.w.yaml b/arch/inst/A/amoand.w.yaml index 3f4dc1c12..35c15e393 100644 --- a/arch/inst/A/amoand.w.yaml +++ b/arch/inst/A/amoand.w.yaml @@ -137,95 +137,3 @@ amoand.w: - sail(): | - { - if extension("A") then { - /* Get the address, X(rs1) (no offset). - * Some extensions perform additional checks on address validity. - */ - match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => { - match translateAddr(vaddr, ReadWrite(Data, Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => { - let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), - (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), - (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), - (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - let is_unsigned : bool = match op { - AMOMINU => true, - AMOMAXU => true, - _ => false - }; - let rs2_val : xlenbits = match width { - BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), - HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), - WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), - DOUBLE => X(rs2) - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { - (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), - (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), - (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), - (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (mval) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(loaded) => { - let result : xlenbits = - match op { - AMOSWAP => rs2_val, - AMOADD => rs2_val + loaded, - AMOXOR => rs2_val ^ loaded, - AMOAND => rs2_val & loaded, - AMOOR => rs2_val | loaded, - - /* These operations convert bitvectors to integer values using [un]signed, - * and back using to_bits(). - */ - AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), - AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), - AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), - AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) - }; - let rval : xlenbits = match width { - BYTE => sign_extend(loaded[7..0]), - HALF => sign_extend(loaded[15..0]), - WORD => sign_extend(loaded[31..0]), - DOUBLE => loaded - }; - let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), - (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), - (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), - (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (wval) { - MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, - MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } - } - } - } - } - } - } - } - } - } - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/A/amomax.d.yaml b/arch/inst/A/amomax.d.yaml index 5fa5e1a0e..2d5af2619 100644 --- a/arch/inst/A/amomax.d.yaml +++ b/arch/inst/A/amomax.d.yaml @@ -138,95 +138,3 @@ amomax.d: - sail(): | - { - if extension("A") then { - /* Get the address, X(rs1) (no offset). - * Some extensions perform additional checks on address validity. - */ - match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => { - match translateAddr(vaddr, ReadWrite(Data, Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => { - let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), - (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), - (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), - (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - let is_unsigned : bool = match op { - AMOMINU => true, - AMOMAXU => true, - _ => false - }; - let rs2_val : xlenbits = match width { - BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), - HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), - WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), - DOUBLE => X(rs2) - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { - (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), - (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), - (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), - (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (mval) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(loaded) => { - let result : xlenbits = - match op { - AMOSWAP => rs2_val, - AMOADD => rs2_val + loaded, - AMOXOR => rs2_val ^ loaded, - AMOAND => rs2_val & loaded, - AMOOR => rs2_val | loaded, - - /* These operations convert bitvectors to integer values using [un]signed, - * and back using to_bits(). - */ - AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), - AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), - AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), - AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) - }; - let rval : xlenbits = match width { - BYTE => sign_extend(loaded[7..0]), - HALF => sign_extend(loaded[15..0]), - WORD => sign_extend(loaded[31..0]), - DOUBLE => loaded - }; - let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), - (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), - (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), - (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (wval) { - MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, - MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } - } - } - } - } - } - } - } - } - } - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/A/amomax.w.yaml b/arch/inst/A/amomax.w.yaml index 1ef3fd3a0..6cdf9bbbb 100644 --- a/arch/inst/A/amomax.w.yaml +++ b/arch/inst/A/amomax.w.yaml @@ -137,95 +137,3 @@ amomax.w: - sail(): | - { - if extension("A") then { - /* Get the address, X(rs1) (no offset). - * Some extensions perform additional checks on address validity. - */ - match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => { - match translateAddr(vaddr, ReadWrite(Data, Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => { - let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), - (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), - (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), - (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - let is_unsigned : bool = match op { - AMOMINU => true, - AMOMAXU => true, - _ => false - }; - let rs2_val : xlenbits = match width { - BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), - HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), - WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), - DOUBLE => X(rs2) - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { - (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), - (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), - (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), - (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (mval) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(loaded) => { - let result : xlenbits = - match op { - AMOSWAP => rs2_val, - AMOADD => rs2_val + loaded, - AMOXOR => rs2_val ^ loaded, - AMOAND => rs2_val & loaded, - AMOOR => rs2_val | loaded, - - /* These operations convert bitvectors to integer values using [un]signed, - * and back using to_bits(). - */ - AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), - AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), - AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), - AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) - }; - let rval : xlenbits = match width { - BYTE => sign_extend(loaded[7..0]), - HALF => sign_extend(loaded[15..0]), - WORD => sign_extend(loaded[31..0]), - DOUBLE => loaded - }; - let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), - (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), - (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), - (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (wval) { - MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, - MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } - } - } - } - } - } - } - } - } - } - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/A/amomaxu.d.yaml b/arch/inst/A/amomaxu.d.yaml index a6b0a1c3a..783696bf0 100644 --- a/arch/inst/A/amomaxu.d.yaml +++ b/arch/inst/A/amomaxu.d.yaml @@ -137,95 +137,3 @@ amomaxu.d: - sail(): | - { - if extension("A") then { - /* Get the address, X(rs1) (no offset). - * Some extensions perform additional checks on address validity. - */ - match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => { - match translateAddr(vaddr, ReadWrite(Data, Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => { - let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), - (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), - (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), - (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - let is_unsigned : bool = match op { - AMOMINU => true, - AMOMAXU => true, - _ => false - }; - let rs2_val : xlenbits = match width { - BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), - HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), - WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), - DOUBLE => X(rs2) - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { - (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), - (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), - (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), - (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (mval) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(loaded) => { - let result : xlenbits = - match op { - AMOSWAP => rs2_val, - AMOADD => rs2_val + loaded, - AMOXOR => rs2_val ^ loaded, - AMOAND => rs2_val & loaded, - AMOOR => rs2_val | loaded, - - /* These operations convert bitvectors to integer values using [un]signed, - * and back using to_bits(). - */ - AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), - AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), - AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), - AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) - }; - let rval : xlenbits = match width { - BYTE => sign_extend(loaded[7..0]), - HALF => sign_extend(loaded[15..0]), - WORD => sign_extend(loaded[31..0]), - DOUBLE => loaded - }; - let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), - (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), - (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), - (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (wval) { - MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, - MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } - } - } - } - } - } - } - } - } - } - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/A/amomaxu.w.yaml b/arch/inst/A/amomaxu.w.yaml index 3d8ff3f38..6ff880c59 100644 --- a/arch/inst/A/amomaxu.w.yaml +++ b/arch/inst/A/amomaxu.w.yaml @@ -137,95 +137,3 @@ amomaxu.w: - sail(): | - { - if extension("A") then { - /* Get the address, X(rs1) (no offset). - * Some extensions perform additional checks on address validity. - */ - match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => { - match translateAddr(vaddr, ReadWrite(Data, Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => { - let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), - (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), - (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), - (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - let is_unsigned : bool = match op { - AMOMINU => true, - AMOMAXU => true, - _ => false - }; - let rs2_val : xlenbits = match width { - BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), - HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), - WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), - DOUBLE => X(rs2) - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { - (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), - (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), - (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), - (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (mval) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(loaded) => { - let result : xlenbits = - match op { - AMOSWAP => rs2_val, - AMOADD => rs2_val + loaded, - AMOXOR => rs2_val ^ loaded, - AMOAND => rs2_val & loaded, - AMOOR => rs2_val | loaded, - - /* These operations convert bitvectors to integer values using [un]signed, - * and back using to_bits(). - */ - AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), - AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), - AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), - AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) - }; - let rval : xlenbits = match width { - BYTE => sign_extend(loaded[7..0]), - HALF => sign_extend(loaded[15..0]), - WORD => sign_extend(loaded[31..0]), - DOUBLE => loaded - }; - let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), - (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), - (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), - (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (wval) { - MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, - MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } - } - } - } - } - } - } - } - } - } - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/A/amomin.d.yaml b/arch/inst/A/amomin.d.yaml index d526fb423..2efad276b 100644 --- a/arch/inst/A/amomin.d.yaml +++ b/arch/inst/A/amomin.d.yaml @@ -138,95 +138,3 @@ amomin.d: - sail(): | - { - if extension("A") then { - /* Get the address, X(rs1) (no offset). - * Some extensions perform additional checks on address validity. - */ - match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => { - match translateAddr(vaddr, ReadWrite(Data, Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => { - let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), - (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), - (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), - (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - let is_unsigned : bool = match op { - AMOMINU => true, - AMOMAXU => true, - _ => false - }; - let rs2_val : xlenbits = match width { - BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), - HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), - WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), - DOUBLE => X(rs2) - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { - (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), - (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), - (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), - (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (mval) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(loaded) => { - let result : xlenbits = - match op { - AMOSWAP => rs2_val, - AMOADD => rs2_val + loaded, - AMOXOR => rs2_val ^ loaded, - AMOAND => rs2_val & loaded, - AMOOR => rs2_val | loaded, - - /* These operations convert bitvectors to integer values using [un]signed, - * and back using to_bits(). - */ - AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), - AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), - AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), - AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) - }; - let rval : xlenbits = match width { - BYTE => sign_extend(loaded[7..0]), - HALF => sign_extend(loaded[15..0]), - WORD => sign_extend(loaded[31..0]), - DOUBLE => loaded - }; - let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), - (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), - (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), - (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (wval) { - MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, - MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } - } - } - } - } - } - } - } - } - } - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/A/amomin.w.yaml b/arch/inst/A/amomin.w.yaml index 5cae94ff1..e614e863e 100644 --- a/arch/inst/A/amomin.w.yaml +++ b/arch/inst/A/amomin.w.yaml @@ -137,95 +137,3 @@ amomin.w: - sail(): | - { - if extension("A") then { - /* Get the address, X(rs1) (no offset). - * Some extensions perform additional checks on address validity. - */ - match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => { - match translateAddr(vaddr, ReadWrite(Data, Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => { - let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), - (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), - (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), - (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - let is_unsigned : bool = match op { - AMOMINU => true, - AMOMAXU => true, - _ => false - }; - let rs2_val : xlenbits = match width { - BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), - HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), - WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), - DOUBLE => X(rs2) - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { - (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), - (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), - (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), - (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (mval) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(loaded) => { - let result : xlenbits = - match op { - AMOSWAP => rs2_val, - AMOADD => rs2_val + loaded, - AMOXOR => rs2_val ^ loaded, - AMOAND => rs2_val & loaded, - AMOOR => rs2_val | loaded, - - /* These operations convert bitvectors to integer values using [un]signed, - * and back using to_bits(). - */ - AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), - AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), - AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), - AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) - }; - let rval : xlenbits = match width { - BYTE => sign_extend(loaded[7..0]), - HALF => sign_extend(loaded[15..0]), - WORD => sign_extend(loaded[31..0]), - DOUBLE => loaded - }; - let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), - (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), - (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), - (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (wval) { - MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, - MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } - } - } - } - } - } - } - } - } - } - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/A/amominu.d.yaml b/arch/inst/A/amominu.d.yaml index ae3ca6254..d83baf6e2 100644 --- a/arch/inst/A/amominu.d.yaml +++ b/arch/inst/A/amominu.d.yaml @@ -138,95 +138,3 @@ amominu.d: - sail(): | - { - if extension("A") then { - /* Get the address, X(rs1) (no offset). - * Some extensions perform additional checks on address validity. - */ - match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => { - match translateAddr(vaddr, ReadWrite(Data, Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => { - let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), - (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), - (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), - (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - let is_unsigned : bool = match op { - AMOMINU => true, - AMOMAXU => true, - _ => false - }; - let rs2_val : xlenbits = match width { - BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), - HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), - WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), - DOUBLE => X(rs2) - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { - (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), - (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), - (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), - (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (mval) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(loaded) => { - let result : xlenbits = - match op { - AMOSWAP => rs2_val, - AMOADD => rs2_val + loaded, - AMOXOR => rs2_val ^ loaded, - AMOAND => rs2_val & loaded, - AMOOR => rs2_val | loaded, - - /* These operations convert bitvectors to integer values using [un]signed, - * and back using to_bits(). - */ - AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), - AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), - AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), - AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) - }; - let rval : xlenbits = match width { - BYTE => sign_extend(loaded[7..0]), - HALF => sign_extend(loaded[15..0]), - WORD => sign_extend(loaded[31..0]), - DOUBLE => loaded - }; - let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), - (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), - (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), - (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (wval) { - MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, - MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } - } - } - } - } - } - } - } - } - } - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/A/amominu.w.yaml b/arch/inst/A/amominu.w.yaml index c30420551..e292c16a4 100644 --- a/arch/inst/A/amominu.w.yaml +++ b/arch/inst/A/amominu.w.yaml @@ -137,95 +137,3 @@ amominu.w: - sail(): | - { - if extension("A") then { - /* Get the address, X(rs1) (no offset). - * Some extensions perform additional checks on address validity. - */ - match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => { - match translateAddr(vaddr, ReadWrite(Data, Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => { - let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), - (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), - (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), - (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - let is_unsigned : bool = match op { - AMOMINU => true, - AMOMAXU => true, - _ => false - }; - let rs2_val : xlenbits = match width { - BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), - HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), - WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), - DOUBLE => X(rs2) - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { - (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), - (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), - (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), - (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (mval) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(loaded) => { - let result : xlenbits = - match op { - AMOSWAP => rs2_val, - AMOADD => rs2_val + loaded, - AMOXOR => rs2_val ^ loaded, - AMOAND => rs2_val & loaded, - AMOOR => rs2_val | loaded, - - /* These operations convert bitvectors to integer values using [un]signed, - * and back using to_bits(). - */ - AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), - AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), - AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), - AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) - }; - let rval : xlenbits = match width { - BYTE => sign_extend(loaded[7..0]), - HALF => sign_extend(loaded[15..0]), - WORD => sign_extend(loaded[31..0]), - DOUBLE => loaded - }; - let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), - (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), - (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), - (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (wval) { - MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, - MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } - } - } - } - } - } - } - } - } - } - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/A/amoor.d.yaml b/arch/inst/A/amoor.d.yaml index 17f7393dd..c3e2cb048 100644 --- a/arch/inst/A/amoor.d.yaml +++ b/arch/inst/A/amoor.d.yaml @@ -138,95 +138,3 @@ amoor.d: - sail(): | - { - if extension("A") then { - /* Get the address, X(rs1) (no offset). - * Some extensions perform additional checks on address validity. - */ - match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => { - match translateAddr(vaddr, ReadWrite(Data, Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => { - let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), - (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), - (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), - (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - let is_unsigned : bool = match op { - AMOMINU => true, - AMOMAXU => true, - _ => false - }; - let rs2_val : xlenbits = match width { - BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), - HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), - WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), - DOUBLE => X(rs2) - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { - (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), - (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), - (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), - (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (mval) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(loaded) => { - let result : xlenbits = - match op { - AMOSWAP => rs2_val, - AMOADD => rs2_val + loaded, - AMOXOR => rs2_val ^ loaded, - AMOAND => rs2_val & loaded, - AMOOR => rs2_val | loaded, - - /* These operations convert bitvectors to integer values using [un]signed, - * and back using to_bits(). - */ - AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), - AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), - AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), - AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) - }; - let rval : xlenbits = match width { - BYTE => sign_extend(loaded[7..0]), - HALF => sign_extend(loaded[15..0]), - WORD => sign_extend(loaded[31..0]), - DOUBLE => loaded - }; - let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), - (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), - (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), - (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (wval) { - MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, - MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } - } - } - } - } - } - } - } - } - } - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/A/amoor.w.yaml b/arch/inst/A/amoor.w.yaml index 8da1177db..208f5489c 100644 --- a/arch/inst/A/amoor.w.yaml +++ b/arch/inst/A/amoor.w.yaml @@ -137,95 +137,3 @@ amoor.w: - sail(): | - { - if extension("A") then { - /* Get the address, X(rs1) (no offset). - * Some extensions perform additional checks on address validity. - */ - match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => { - match translateAddr(vaddr, ReadWrite(Data, Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => { - let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), - (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), - (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), - (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - let is_unsigned : bool = match op { - AMOMINU => true, - AMOMAXU => true, - _ => false - }; - let rs2_val : xlenbits = match width { - BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), - HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), - WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), - DOUBLE => X(rs2) - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { - (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), - (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), - (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), - (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (mval) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(loaded) => { - let result : xlenbits = - match op { - AMOSWAP => rs2_val, - AMOADD => rs2_val + loaded, - AMOXOR => rs2_val ^ loaded, - AMOAND => rs2_val & loaded, - AMOOR => rs2_val | loaded, - - /* These operations convert bitvectors to integer values using [un]signed, - * and back using to_bits(). - */ - AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), - AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), - AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), - AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) - }; - let rval : xlenbits = match width { - BYTE => sign_extend(loaded[7..0]), - HALF => sign_extend(loaded[15..0]), - WORD => sign_extend(loaded[31..0]), - DOUBLE => loaded - }; - let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), - (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), - (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), - (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (wval) { - MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, - MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } - } - } - } - } - } - } - } - } - } - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/A/amoswap.d.yaml b/arch/inst/A/amoswap.d.yaml index 5f7fffb55..e7c3990a8 100644 --- a/arch/inst/A/amoswap.d.yaml +++ b/arch/inst/A/amoswap.d.yaml @@ -137,95 +137,3 @@ amoswap.d: - sail(): | - { - if extension("A") then { - /* Get the address, X(rs1) (no offset). - * Some extensions perform additional checks on address validity. - */ - match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => { - match translateAddr(vaddr, ReadWrite(Data, Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => { - let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), - (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), - (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), - (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - let is_unsigned : bool = match op { - AMOMINU => true, - AMOMAXU => true, - _ => false - }; - let rs2_val : xlenbits = match width { - BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), - HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), - WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), - DOUBLE => X(rs2) - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { - (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), - (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), - (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), - (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (mval) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(loaded) => { - let result : xlenbits = - match op { - AMOSWAP => rs2_val, - AMOADD => rs2_val + loaded, - AMOXOR => rs2_val ^ loaded, - AMOAND => rs2_val & loaded, - AMOOR => rs2_val | loaded, - - /* These operations convert bitvectors to integer values using [un]signed, - * and back using to_bits(). - */ - AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), - AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), - AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), - AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) - }; - let rval : xlenbits = match width { - BYTE => sign_extend(loaded[7..0]), - HALF => sign_extend(loaded[15..0]), - WORD => sign_extend(loaded[31..0]), - DOUBLE => loaded - }; - let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), - (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), - (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), - (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (wval) { - MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, - MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } - } - } - } - } - } - } - } - } - } - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/A/amoswap.w.yaml b/arch/inst/A/amoswap.w.yaml index 34e25a927..0fc4bbcdb 100644 --- a/arch/inst/A/amoswap.w.yaml +++ b/arch/inst/A/amoswap.w.yaml @@ -136,95 +136,3 @@ amoswap.w: - sail(): | - { - if extension("A") then { - /* Get the address, X(rs1) (no offset). - * Some extensions perform additional checks on address validity. - */ - match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => { - match translateAddr(vaddr, ReadWrite(Data, Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => { - let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), - (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), - (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), - (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - let is_unsigned : bool = match op { - AMOMINU => true, - AMOMAXU => true, - _ => false - }; - let rs2_val : xlenbits = match width { - BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), - HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), - WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), - DOUBLE => X(rs2) - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { - (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), - (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), - (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), - (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (mval) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(loaded) => { - let result : xlenbits = - match op { - AMOSWAP => rs2_val, - AMOADD => rs2_val + loaded, - AMOXOR => rs2_val ^ loaded, - AMOAND => rs2_val & loaded, - AMOOR => rs2_val | loaded, - - /* These operations convert bitvectors to integer values using [un]signed, - * and back using to_bits(). - */ - AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), - AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), - AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), - AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) - }; - let rval : xlenbits = match width { - BYTE => sign_extend(loaded[7..0]), - HALF => sign_extend(loaded[15..0]), - WORD => sign_extend(loaded[31..0]), - DOUBLE => loaded - }; - let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), - (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), - (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), - (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (wval) { - MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, - MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } - } - } - } - } - } - } - } - } - } - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/A/amoxor.d.yaml b/arch/inst/A/amoxor.d.yaml index 75f70cc1a..7050c9146 100644 --- a/arch/inst/A/amoxor.d.yaml +++ b/arch/inst/A/amoxor.d.yaml @@ -138,95 +138,3 @@ amoxor.d: - sail(): | - { - if extension("A") then { - /* Get the address, X(rs1) (no offset). - * Some extensions perform additional checks on address validity. - */ - match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => { - match translateAddr(vaddr, ReadWrite(Data, Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => { - let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), - (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), - (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), - (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - let is_unsigned : bool = match op { - AMOMINU => true, - AMOMAXU => true, - _ => false - }; - let rs2_val : xlenbits = match width { - BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), - HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), - WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), - DOUBLE => X(rs2) - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { - (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), - (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), - (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), - (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (mval) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(loaded) => { - let result : xlenbits = - match op { - AMOSWAP => rs2_val, - AMOADD => rs2_val + loaded, - AMOXOR => rs2_val ^ loaded, - AMOAND => rs2_val & loaded, - AMOOR => rs2_val | loaded, - - /* These operations convert bitvectors to integer values using [un]signed, - * and back using to_bits(). - */ - AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), - AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), - AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), - AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) - }; - let rval : xlenbits = match width { - BYTE => sign_extend(loaded[7..0]), - HALF => sign_extend(loaded[15..0]), - WORD => sign_extend(loaded[31..0]), - DOUBLE => loaded - }; - let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), - (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), - (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), - (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (wval) { - MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, - MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } - } - } - } - } - } - } - } - } - } - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/A/amoxor.w.yaml b/arch/inst/A/amoxor.w.yaml index 5f8f3d26b..ba8eeaea4 100644 --- a/arch/inst/A/amoxor.w.yaml +++ b/arch/inst/A/amoxor.w.yaml @@ -137,95 +137,3 @@ amoxor.w: - sail(): | - { - if extension("A") then { - /* Get the address, X(rs1) (no offset). - * Some extensions perform additional checks on address validity. - */ - match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => { - match translateAddr(vaddr, ReadWrite(Data, Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => { - let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), - (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), - (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), - (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - let is_unsigned : bool = match op { - AMOMINU => true, - AMOMAXU => true, - _ => false - }; - let rs2_val : xlenbits = match width { - BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), - HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), - WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), - DOUBLE => X(rs2) - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { - (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), - (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), - (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), - (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (mval) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(loaded) => { - let result : xlenbits = - match op { - AMOSWAP => rs2_val, - AMOADD => rs2_val + loaded, - AMOXOR => rs2_val ^ loaded, - AMOAND => rs2_val & loaded, - AMOOR => rs2_val | loaded, - - /* These operations convert bitvectors to integer values using [un]signed, - * and back using to_bits(). - */ - AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), - AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), - AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), - AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) - }; - let rval : xlenbits = match width { - BYTE => sign_extend(loaded[7..0]), - HALF => sign_extend(loaded[15..0]), - WORD => sign_extend(loaded[31..0]), - DOUBLE => loaded - }; - let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), - (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), - (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), - (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - }; - match (wval) { - MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, - MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } - } - } - } - } - } - } - } - } - } - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/A/lr.d.yaml b/arch/inst/A/lr.d.yaml index f1a43c89e..ac83deb23 100644 --- a/arch/inst/A/lr.d.yaml +++ b/arch/inst/A/lr.d.yaml @@ -137,47 +137,3 @@ lr.d: - sail(): | - { - if extension("A") then { - /* Get the address, X(rs1) (no offset). - * Extensions might perform additional checks on address validity. - */ - match ext_data_get_addr(rs1, zeros(), Read(Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => { - let aligned : bool = - /* BYTE and HALF would only occur due to invalid decodes, but it doesn't hurt - * to treat them as valid here; otherwise we'd need to throw an internal_error. - */ - match width { - BYTE => true, - HALF => vaddr[0..0] == 0b0, - WORD => vaddr[1..0] == 0b00, - DOUBLE => vaddr[2..0] == 0b000 - }; - /* "LR faults like a normal load, even though it's in the AMO major opcode space." - * - Andrew Waterman, isa-dev, 10 Jul 2018. - */ - if not(aligned) - then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } - else match translateAddr(vaddr, Read(Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => - match (width, sizeof(xlen)) { - (BYTE, _) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 1, aq, aq & rl, true), false), - (HALF, _) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 2, aq, aq & rl, true), false), - (WORD, _) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 4, aq, aq & rl, true), false), - (DOUBLE, 64) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 8, aq, aq & rl, true), false), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - } - } - } - } - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/A/lr.w.yaml b/arch/inst/A/lr.w.yaml index 8ec845316..9df0a62cf 100644 --- a/arch/inst/A/lr.w.yaml +++ b/arch/inst/A/lr.w.yaml @@ -145,47 +145,3 @@ lr.w: - sail(): | - { - if extension("A") then { - /* Get the address, X(rs1) (no offset). - * Extensions might perform additional checks on address validity. - */ - match ext_data_get_addr(rs1, zeros(), Read(Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => { - let aligned : bool = - /* BYTE and HALF would only occur due to invalid decodes, but it doesn't hurt - * to treat them as valid here; otherwise we'd need to throw an internal_error. - */ - match width { - BYTE => true, - HALF => vaddr[0..0] == 0b0, - WORD => vaddr[1..0] == 0b00, - DOUBLE => vaddr[2..0] == 0b000 - }; - /* "LR faults like a normal load, even though it's in the AMO major opcode space." - * - Andrew Waterman, isa-dev, 10 Jul 2018. - */ - if not(aligned) - then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } - else match translateAddr(vaddr, Read(Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => - match (width, sizeof(xlen)) { - (BYTE, _) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 1, aq, aq & rl, true), false), - (HALF, _) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 2, aq, aq & rl, true), false), - (WORD, _) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 4, aq, aq & rl, true), false), - (DOUBLE, 64) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 8, aq, aq & rl, true), false), - _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") - } - } - } - } - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/A/sc.d.yaml b/arch/inst/A/sc.d.yaml index 3c7d96e67..2a692b823 100644 --- a/arch/inst/A/sc.d.yaml +++ b/arch/inst/A/sc.d.yaml @@ -229,81 +229,3 @@ sc.d: - sail(): | - { - if speculate_conditional () == false then { - /* should only happen in rmem - * rmem: allow SC to fail very early - */ - X(rd) = zero_extend(0b1); RETIRE_SUCCESS - } else { - if extension("A") then { - /* normal non-rmem case - * rmem: SC is allowed to succeed (but might fail later) - */ - /* Get the address, X(rs1) (no offset). - * Extensions might perform additional checks on address validity. - */ - match ext_data_get_addr(rs1, zeros(), Write(Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => { - let aligned : bool = - /* BYTE and HALF would only occur due to invalid decodes, but it doesn't hurt - * to treat them as valid here; otherwise we'd need to throw an internal_error. - */ - match width { - BYTE => true, - HALF => vaddr[0..0] == 0b0, - WORD => vaddr[1..0] == 0b00, - DOUBLE => vaddr[2..0] == 0b000 - }; - if not(aligned) - then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL } - else { - if match_reservation(vaddr) == false then { - /* cannot happen in rmem */ - X(rd) = zero_extend(0b1); cancel_reservation(); RETIRE_SUCCESS - } else { - match translateAddr(vaddr, Write(Data)) { /* Write and ReadWrite are equivalent here: - * both result in a SAMO exception */ - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => { - let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), - (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), - (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), - (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "STORECON expected word or double") - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - rs2_val = X(rs2); - let res : MemoryOpResult(bool) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_value(addr, 1, rs2_val[7..0], aq & rl, rl, true), - (HALF, _) => mem_write_value(addr, 2, rs2_val[15..0], aq & rl, rl, true), - (WORD, _) => mem_write_value(addr, 4, rs2_val[31..0], aq & rl, rl, true), - (DOUBLE, 64) => mem_write_value(addr, 8, rs2_val, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "STORECON expected word or double") - }; - match (res) { - MemValue(true) => { X(rd) = zero_extend(0b0); cancel_reservation(); RETIRE_SUCCESS }, - MemValue(false) => { X(rd) = zero_extend(0b1); cancel_reservation(); RETIRE_SUCCESS }, - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } - } - } - } - } - } - } - } - } - } - } else { - handle_illegal(); - RETIRE_FAIL - } - } - } - - \ No newline at end of file diff --git a/arch/inst/A/sc.w.yaml b/arch/inst/A/sc.w.yaml index dcabced5f..94fd254dc 100644 --- a/arch/inst/A/sc.w.yaml +++ b/arch/inst/A/sc.w.yaml @@ -235,81 +235,3 @@ sc.w: - sail(): | - { - if speculate_conditional () == false then { - /* should only happen in rmem - * rmem: allow SC to fail very early - */ - X(rd) = zero_extend(0b1); RETIRE_SUCCESS - } else { - if extension("A") then { - /* normal non-rmem case - * rmem: SC is allowed to succeed (but might fail later) - */ - /* Get the address, X(rs1) (no offset). - * Extensions might perform additional checks on address validity. - */ - match ext_data_get_addr(rs1, zeros(), Write(Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => { - let aligned : bool = - /* BYTE and HALF would only occur due to invalid decodes, but it doesn't hurt - * to treat them as valid here; otherwise we'd need to throw an internal_error. - */ - match width { - BYTE => true, - HALF => vaddr[0..0] == 0b0, - WORD => vaddr[1..0] == 0b00, - DOUBLE => vaddr[2..0] == 0b000 - }; - if not(aligned) - then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL } - else { - if match_reservation(vaddr) == false then { - /* cannot happen in rmem */ - X(rd) = zero_extend(0b1); cancel_reservation(); RETIRE_SUCCESS - } else { - match translateAddr(vaddr, Write(Data)) { /* Write and ReadWrite are equivalent here: - * both result in a SAMO exception */ - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => { - let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), - (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), - (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), - (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "STORECON expected word or double") - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - rs2_val = X(rs2); - let res : MemoryOpResult(bool) = match (width, sizeof(xlen)) { - (BYTE, _) => mem_write_value(addr, 1, rs2_val[7..0], aq & rl, rl, true), - (HALF, _) => mem_write_value(addr, 2, rs2_val[15..0], aq & rl, rl, true), - (WORD, _) => mem_write_value(addr, 4, rs2_val[31..0], aq & rl, rl, true), - (DOUBLE, 64) => mem_write_value(addr, 8, rs2_val, aq & rl, rl, true), - _ => internal_error(__FILE__, __LINE__, "STORECON expected word or double") - }; - match (res) { - MemValue(true) => { X(rd) = zero_extend(0b0); cancel_reservation(); RETIRE_SUCCESS }, - MemValue(false) => { X(rd) = zero_extend(0b1); cancel_reservation(); RETIRE_SUCCESS }, - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } - } - } - } - } - } - } - } - } - } - } else { - handle_illegal(); - RETIRE_FAIL - } - } - } - - \ No newline at end of file diff --git a/arch/inst/B/add.uw.yaml b/arch/inst/B/add.uw.yaml index dc8a91ab0..305153b64 100644 --- a/arch/inst/B/add.uw.yaml +++ b/arch/inst/B/add.uw.yaml @@ -53,19 +53,3 @@ add.uw: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let shamt : bits(2) = match op { - RISCV_ADDUW => 0b00, - RISCV_SH1ADDUW => 0b01, - RISCV_SH2ADDUW => 0b10, - RISCV_SH3ADDUW => 0b11 - }; - let result : xlenbits = (zero_extend(rs1_val[31..0]) << shamt) + rs2_val; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/andn.yaml b/arch/inst/B/andn.yaml index 029412ff2..82978d32a 100644 --- a/arch/inst/B/andn.yaml +++ b/arch/inst/B/andn.yaml @@ -58,27 +58,3 @@ andn: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let result : xlenbits = match op { - RISCV_ANDN => rs1_val & ~(rs2_val), - RISCV_ORN => rs1_val | ~(rs2_val), - RISCV_XNOR => ~(rs1_val ^ rs2_val), - RISCV_MAX => to_bits(sizeof(xlen), max(signed(rs1_val), signed(rs2_val))), - RISCV_MAXU => to_bits(sizeof(xlen), max(unsigned(rs1_val), unsigned(rs2_val))), - RISCV_MIN => to_bits(sizeof(xlen), min(signed(rs1_val), signed(rs2_val))), - RISCV_MINU => to_bits(sizeof(xlen), min(unsigned(rs1_val), unsigned(rs2_val))), - RISCV_ROL => if sizeof(xlen) == 32 - then rs1_val <<< rs2_val[4..0] - else rs1_val <<< rs2_val[5..0], - RISCV_ROR => if sizeof(xlen) == 32 - then rs1_val >>> rs2_val[4..0] - else rs1_val >>> rs2_val[5..0] - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/bclr.yaml b/arch/inst/B/bclr.yaml index 96781ea2b..57c8e6b9d 100644 --- a/arch/inst/B/bclr.yaml +++ b/arch/inst/B/bclr.yaml @@ -52,21 +52,3 @@ bclr: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let mask : xlenbits = if sizeof(xlen) == 32 - then zero_extend(0b1) << rs2_val[4..0] - else zero_extend(0b1) << rs2_val[5..0]; - let result : xlenbits = match op { - RISCV_BCLR => rs1_val & ~(mask), - RISCV_BEXT => zero_extend(bool_to_bits((rs1_val & mask) != zeros())), - RISCV_BINV => rs1_val ^ mask, - RISCV_BSET => rs1_val | mask - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/bclri.yaml b/arch/inst/B/bclri.yaml index adce4ab2f..b776689cc 100644 --- a/arch/inst/B/bclri.yaml +++ b/arch/inst/B/bclri.yaml @@ -62,20 +62,3 @@ bclri: - sail(): | - { - let rs1_val = X(rs1); - let mask : xlenbits = if sizeof(xlen) == 32 - then zero_extend(0b1) << shamt[4..0] - else zero_extend(0b1) << shamt; - let result : xlenbits = match op { - RISCV_BCLRI => rs1_val & ~(mask), - RISCV_BEXTI => zero_extend(bool_to_bits((rs1_val & mask) != zeros())), - RISCV_BINVI => rs1_val ^ mask, - RISCV_BSETI => rs1_val | mask - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/bext.yaml b/arch/inst/B/bext.yaml index 2e4f42142..bd14665ea 100644 --- a/arch/inst/B/bext.yaml +++ b/arch/inst/B/bext.yaml @@ -52,21 +52,3 @@ bext: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let mask : xlenbits = if sizeof(xlen) == 32 - then zero_extend(0b1) << rs2_val[4..0] - else zero_extend(0b1) << rs2_val[5..0]; - let result : xlenbits = match op { - RISCV_BCLR => rs1_val & ~(mask), - RISCV_BEXT => zero_extend(bool_to_bits((rs1_val & mask) != zeros())), - RISCV_BINV => rs1_val ^ mask, - RISCV_BSET => rs1_val | mask - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/bexti.yaml b/arch/inst/B/bexti.yaml index 71e8d1122..fff79a4d0 100644 --- a/arch/inst/B/bexti.yaml +++ b/arch/inst/B/bexti.yaml @@ -62,20 +62,3 @@ bexti: - sail(): | - { - let rs1_val = X(rs1); - let mask : xlenbits = if sizeof(xlen) == 32 - then zero_extend(0b1) << shamt[4..0] - else zero_extend(0b1) << shamt; - let result : xlenbits = match op { - RISCV_BCLRI => rs1_val & ~(mask), - RISCV_BEXTI => zero_extend(bool_to_bits((rs1_val & mask) != zeros())), - RISCV_BINVI => rs1_val ^ mask, - RISCV_BSETI => rs1_val | mask - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/binv.yaml b/arch/inst/B/binv.yaml index 94b24c781..45d4d59e0 100644 --- a/arch/inst/B/binv.yaml +++ b/arch/inst/B/binv.yaml @@ -52,21 +52,3 @@ binv: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let mask : xlenbits = if sizeof(xlen) == 32 - then zero_extend(0b1) << rs2_val[4..0] - else zero_extend(0b1) << rs2_val[5..0]; - let result : xlenbits = match op { - RISCV_BCLR => rs1_val & ~(mask), - RISCV_BEXT => zero_extend(bool_to_bits((rs1_val & mask) != zeros())), - RISCV_BINV => rs1_val ^ mask, - RISCV_BSET => rs1_val | mask - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/binvi.yaml b/arch/inst/B/binvi.yaml index cf9f6434b..4c9c5bb07 100644 --- a/arch/inst/B/binvi.yaml +++ b/arch/inst/B/binvi.yaml @@ -62,20 +62,3 @@ binvi: - sail(): | - { - let rs1_val = X(rs1); - let mask : xlenbits = if sizeof(xlen) == 32 - then zero_extend(0b1) << shamt[4..0] - else zero_extend(0b1) << shamt; - let result : xlenbits = match op { - RISCV_BCLRI => rs1_val & ~(mask), - RISCV_BEXTI => zero_extend(bool_to_bits((rs1_val & mask) != zeros())), - RISCV_BINVI => rs1_val ^ mask, - RISCV_BSETI => rs1_val | mask - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/bset.yaml b/arch/inst/B/bset.yaml index f2eb0d51e..072b8605e 100644 --- a/arch/inst/B/bset.yaml +++ b/arch/inst/B/bset.yaml @@ -52,21 +52,3 @@ bset: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let mask : xlenbits = if sizeof(xlen) == 32 - then zero_extend(0b1) << rs2_val[4..0] - else zero_extend(0b1) << rs2_val[5..0]; - let result : xlenbits = match op { - RISCV_BCLR => rs1_val & ~(mask), - RISCV_BEXT => zero_extend(bool_to_bits((rs1_val & mask) != zeros())), - RISCV_BINV => rs1_val ^ mask, - RISCV_BSET => rs1_val | mask - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/bseti.yaml b/arch/inst/B/bseti.yaml index 039aed7a0..f938dcb42 100644 --- a/arch/inst/B/bseti.yaml +++ b/arch/inst/B/bseti.yaml @@ -62,20 +62,3 @@ bseti: - sail(): | - { - let rs1_val = X(rs1); - let mask : xlenbits = if sizeof(xlen) == 32 - then zero_extend(0b1) << shamt[4..0] - else zero_extend(0b1) << shamt; - let result : xlenbits = match op { - RISCV_BCLRI => rs1_val & ~(mask), - RISCV_BEXTI => zero_extend(bool_to_bits((rs1_val & mask) != zeros())), - RISCV_BINVI => rs1_val ^ mask, - RISCV_BSETI => rs1_val | mask - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/clmul.yaml b/arch/inst/B/clmul.yaml index 6584dbf8a..7d99b1537 100644 --- a/arch/inst/B/clmul.yaml +++ b/arch/inst/B/clmul.yaml @@ -55,15 +55,3 @@ clmul: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - result : xlenbits = zeros(); - foreach (i from 0 to (xlen_val - 1)) - if rs2_val[i] == bitone then result = result ^ (rs1_val << i); - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/clmulh.yaml b/arch/inst/B/clmulh.yaml index 25e6cd691..f82e70ddc 100644 --- a/arch/inst/B/clmulh.yaml +++ b/arch/inst/B/clmulh.yaml @@ -55,15 +55,3 @@ clmulh: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - result : xlenbits = zeros(); - foreach (i from 0 to (xlen_val - 1)) - if rs2_val[i] == bitone then result = result ^ (rs1_val >> (xlen_val - i)); - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/clmulr.yaml b/arch/inst/B/clmulr.yaml index 83f2f09b9..03c632d05 100644 --- a/arch/inst/B/clmulr.yaml +++ b/arch/inst/B/clmulr.yaml @@ -54,15 +54,3 @@ clmulr: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - result : xlenbits = zeros(); - foreach (i from 0 to (xlen_val - 1)) - if rs2_val[i] == bitone then result = result ^ (rs1_val >> (xlen_val - i - 1)); - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/clz.yaml b/arch/inst/B/clz.yaml index 0f439781d..506895312 100644 --- a/arch/inst/B/clz.yaml +++ b/arch/inst/B/clz.yaml @@ -47,17 +47,3 @@ clz: - sail(): | - { - let rs1_val = X(rs1); - result : nat = 0; - done : bool = false; - foreach (i from (sizeof(xlen) - 1) downto 0) - if not(done) then if rs1_val[i] == bitzero - then result = result + 1 - else done = true; - X(rd) = to_bits(sizeof(xlen), result); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/clzw.yaml b/arch/inst/B/clzw.yaml index ae5b07c91..dd945ad17 100644 --- a/arch/inst/B/clzw.yaml +++ b/arch/inst/B/clzw.yaml @@ -47,17 +47,3 @@ clzw: - sail(): | - { - let rs1_val = X(rs1); - result : nat = 0; - done : bool = false; - foreach (i from 31 downto 0) - if not(done) then if rs1_val[i] == bitzero - then result = result + 1 - else done = true; - X(rd) = to_bits(sizeof(xlen), result); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/cpop.yaml b/arch/inst/B/cpop.yaml index 3511dc1bc..74951f0f3 100644 --- a/arch/inst/B/cpop.yaml +++ b/arch/inst/B/cpop.yaml @@ -62,14 +62,3 @@ cpop: - sail(): | - { - let rs1_val = X(rs1); - result : nat = 0; - foreach (i from 0 to (xlen_val - 1)) - if rs1_val[i] == bitone then result = result + 1; - X(rd) = to_bits(sizeof(xlen), result); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/cpopw.yaml b/arch/inst/B/cpopw.yaml index 20a842ddd..5a75bfdf5 100644 --- a/arch/inst/B/cpopw.yaml +++ b/arch/inst/B/cpopw.yaml @@ -63,14 +63,3 @@ cpopw: - sail(): | - { - let rs1_val = X(rs1); - result : nat = 0; - foreach (i from 0 to 31) - if rs1_val[i] == bitone then result = result + 1; - X(rd) = to_bits(sizeof(xlen), result); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/ctz.yaml b/arch/inst/B/ctz.yaml index 5aafdda0a..fcd2e296e 100644 --- a/arch/inst/B/ctz.yaml +++ b/arch/inst/B/ctz.yaml @@ -48,17 +48,3 @@ ctz: - sail(): | - { - let rs1_val = X(rs1); - result : nat = 0; - done : bool = false; - foreach (i from 0 to (sizeof(xlen) - 1)) - if not(done) then if rs1_val[i] == bitzero - then result = result + 1 - else done = true; - X(rd) = to_bits(sizeof(xlen), result); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/ctzw.yaml b/arch/inst/B/ctzw.yaml index d68b216b3..88bc86bb1 100644 --- a/arch/inst/B/ctzw.yaml +++ b/arch/inst/B/ctzw.yaml @@ -49,17 +49,3 @@ ctzw: - sail(): | - { - let rs1_val = X(rs1); - result : nat = 0; - done : bool = false; - foreach (i from 0 to 31) - if not(done) then if rs1_val[i] == bitzero - then result = result + 1 - else done = true; - X(rd) = to_bits(sizeof(xlen), result); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/max.yaml b/arch/inst/B/max.yaml index 3aebd065c..5256e0c0b 100644 --- a/arch/inst/B/max.yaml +++ b/arch/inst/B/max.yaml @@ -64,27 +64,3 @@ max: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let result : xlenbits = match op { - RISCV_ANDN => rs1_val & ~(rs2_val), - RISCV_ORN => rs1_val | ~(rs2_val), - RISCV_XNOR => ~(rs1_val ^ rs2_val), - RISCV_MAX => to_bits(sizeof(xlen), max(signed(rs1_val), signed(rs2_val))), - RISCV_MAXU => to_bits(sizeof(xlen), max(unsigned(rs1_val), unsigned(rs2_val))), - RISCV_MIN => to_bits(sizeof(xlen), min(signed(rs1_val), signed(rs2_val))), - RISCV_MINU => to_bits(sizeof(xlen), min(unsigned(rs1_val), unsigned(rs2_val))), - RISCV_ROL => if sizeof(xlen) == 32 - then rs1_val <<< rs2_val[4..0] - else rs1_val <<< rs2_val[5..0], - RISCV_ROR => if sizeof(xlen) == 32 - then rs1_val >>> rs2_val[4..0] - else rs1_val >>> rs2_val[5..0] - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/maxu.yaml b/arch/inst/B/maxu.yaml index d8d3af4e5..ea196055d 100644 --- a/arch/inst/B/maxu.yaml +++ b/arch/inst/B/maxu.yaml @@ -56,27 +56,3 @@ maxu: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let result : xlenbits = match op { - RISCV_ANDN => rs1_val & ~(rs2_val), - RISCV_ORN => rs1_val | ~(rs2_val), - RISCV_XNOR => ~(rs1_val ^ rs2_val), - RISCV_MAX => to_bits(sizeof(xlen), max(signed(rs1_val), signed(rs2_val))), - RISCV_MAXU => to_bits(sizeof(xlen), max(unsigned(rs1_val), unsigned(rs2_val))), - RISCV_MIN => to_bits(sizeof(xlen), min(signed(rs1_val), signed(rs2_val))), - RISCV_MINU => to_bits(sizeof(xlen), min(unsigned(rs1_val), unsigned(rs2_val))), - RISCV_ROL => if sizeof(xlen) == 32 - then rs1_val <<< rs2_val[4..0] - else rs1_val <<< rs2_val[5..0], - RISCV_ROR => if sizeof(xlen) == 32 - then rs1_val >>> rs2_val[4..0] - else rs1_val >>> rs2_val[5..0] - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/min.yaml b/arch/inst/B/min.yaml index 5885af9b4..4161ddfdc 100644 --- a/arch/inst/B/min.yaml +++ b/arch/inst/B/min.yaml @@ -56,27 +56,3 @@ min: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let result : xlenbits = match op { - RISCV_ANDN => rs1_val & ~(rs2_val), - RISCV_ORN => rs1_val | ~(rs2_val), - RISCV_XNOR => ~(rs1_val ^ rs2_val), - RISCV_MAX => to_bits(sizeof(xlen), max(signed(rs1_val), signed(rs2_val))), - RISCV_MAXU => to_bits(sizeof(xlen), max(unsigned(rs1_val), unsigned(rs2_val))), - RISCV_MIN => to_bits(sizeof(xlen), min(signed(rs1_val), signed(rs2_val))), - RISCV_MINU => to_bits(sizeof(xlen), min(unsigned(rs1_val), unsigned(rs2_val))), - RISCV_ROL => if sizeof(xlen) == 32 - then rs1_val <<< rs2_val[4..0] - else rs1_val <<< rs2_val[5..0], - RISCV_ROR => if sizeof(xlen) == 32 - then rs1_val >>> rs2_val[4..0] - else rs1_val >>> rs2_val[5..0] - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/minu.yaml b/arch/inst/B/minu.yaml index 963080d6a..dfe214bd5 100644 --- a/arch/inst/B/minu.yaml +++ b/arch/inst/B/minu.yaml @@ -56,27 +56,3 @@ minu: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let result : xlenbits = match op { - RISCV_ANDN => rs1_val & ~(rs2_val), - RISCV_ORN => rs1_val | ~(rs2_val), - RISCV_XNOR => ~(rs1_val ^ rs2_val), - RISCV_MAX => to_bits(sizeof(xlen), max(signed(rs1_val), signed(rs2_val))), - RISCV_MAXU => to_bits(sizeof(xlen), max(unsigned(rs1_val), unsigned(rs2_val))), - RISCV_MIN => to_bits(sizeof(xlen), min(signed(rs1_val), signed(rs2_val))), - RISCV_MINU => to_bits(sizeof(xlen), min(unsigned(rs1_val), unsigned(rs2_val))), - RISCV_ROL => if sizeof(xlen) == 32 - then rs1_val <<< rs2_val[4..0] - else rs1_val <<< rs2_val[5..0], - RISCV_ROR => if sizeof(xlen) == 32 - then rs1_val >>> rs2_val[4..0] - else rs1_val >>> rs2_val[5..0] - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/orc.b.yaml b/arch/inst/B/orc.b.yaml index 7d888a4b6..195af23b1 100644 --- a/arch/inst/B/orc.b.yaml +++ b/arch/inst/B/orc.b.yaml @@ -52,16 +52,3 @@ orc.b: - sail(): | - { - let rs1_val = X(rs1); - result : xlenbits = zeros(); - foreach (i from 0 to (sizeof(xlen) - 8) by 8) - result[(i + 7) .. i] = if rs1_val[(i + 7) .. i] == zeros() - then 0x00 - else 0xFF; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/orn.yaml b/arch/inst/B/orn.yaml index d9b1c0305..9fd1ef345 100644 --- a/arch/inst/B/orn.yaml +++ b/arch/inst/B/orn.yaml @@ -57,27 +57,3 @@ orn: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let result : xlenbits = match op { - RISCV_ANDN => rs1_val & ~(rs2_val), - RISCV_ORN => rs1_val | ~(rs2_val), - RISCV_XNOR => ~(rs1_val ^ rs2_val), - RISCV_MAX => to_bits(sizeof(xlen), max(signed(rs1_val), signed(rs2_val))), - RISCV_MAXU => to_bits(sizeof(xlen), max(unsigned(rs1_val), unsigned(rs2_val))), - RISCV_MIN => to_bits(sizeof(xlen), min(signed(rs1_val), signed(rs2_val))), - RISCV_MINU => to_bits(sizeof(xlen), min(unsigned(rs1_val), unsigned(rs2_val))), - RISCV_ROL => if sizeof(xlen) == 32 - then rs1_val <<< rs2_val[4..0] - else rs1_val <<< rs2_val[5..0], - RISCV_ROR => if sizeof(xlen) == 32 - then rs1_val >>> rs2_val[4..0] - else rs1_val >>> rs2_val[5..0] - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/rev8.yaml b/arch/inst/B/rev8.yaml index 0d5b23d53..34b61ec3c 100644 --- a/arch/inst/B/rev8.yaml +++ b/arch/inst/B/rev8.yaml @@ -68,14 +68,3 @@ rev8: - sail(): | - { - let rs1_val = X(rs1); - result : xlenbits = zeros(); - foreach (i from 0 to (sizeof(xlen) - 8) by 8) - result[(i + 7) .. i] = rs1_val[(sizeof(xlen) - i - 1) .. (sizeof(xlen) - i - 8)]; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/rol.yaml b/arch/inst/B/rol.yaml index e2148b7f2..882272194 100644 --- a/arch/inst/B/rol.yaml +++ b/arch/inst/B/rol.yaml @@ -59,27 +59,3 @@ rol: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let result : xlenbits = match op { - RISCV_ANDN => rs1_val & ~(rs2_val), - RISCV_ORN => rs1_val | ~(rs2_val), - RISCV_XNOR => ~(rs1_val ^ rs2_val), - RISCV_MAX => to_bits(sizeof(xlen), max(signed(rs1_val), signed(rs2_val))), - RISCV_MAXU => to_bits(sizeof(xlen), max(unsigned(rs1_val), unsigned(rs2_val))), - RISCV_MIN => to_bits(sizeof(xlen), min(signed(rs1_val), signed(rs2_val))), - RISCV_MINU => to_bits(sizeof(xlen), min(unsigned(rs1_val), unsigned(rs2_val))), - RISCV_ROL => if sizeof(xlen) == 32 - then rs1_val <<< rs2_val[4..0] - else rs1_val <<< rs2_val[5..0], - RISCV_ROR => if sizeof(xlen) == 32 - then rs1_val >>> rs2_val[4..0] - else rs1_val >>> rs2_val[5..0] - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/rolw.yaml b/arch/inst/B/rolw.yaml index c9df59d63..ee2264e57 100644 --- a/arch/inst/B/rolw.yaml +++ b/arch/inst/B/rolw.yaml @@ -53,16 +53,3 @@ rolw: - sail(): | - { - let rs1_val = (X(rs1))[31..0]; - let shamt = (X(rs2))[4..0]; - let result : bits(32) = match op { - RISCV_ROLW => rs1_val <<< shamt, - RISCV_RORW => rs1_val >>> shamt - }; - X(rd) = sign_extend(result); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/ror.yaml b/arch/inst/B/ror.yaml index 958d4e9b3..603a6c964 100644 --- a/arch/inst/B/ror.yaml +++ b/arch/inst/B/ror.yaml @@ -59,27 +59,3 @@ ror: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let result : xlenbits = match op { - RISCV_ANDN => rs1_val & ~(rs2_val), - RISCV_ORN => rs1_val | ~(rs2_val), - RISCV_XNOR => ~(rs1_val ^ rs2_val), - RISCV_MAX => to_bits(sizeof(xlen), max(signed(rs1_val), signed(rs2_val))), - RISCV_MAXU => to_bits(sizeof(xlen), max(unsigned(rs1_val), unsigned(rs2_val))), - RISCV_MIN => to_bits(sizeof(xlen), min(signed(rs1_val), signed(rs2_val))), - RISCV_MINU => to_bits(sizeof(xlen), min(unsigned(rs1_val), unsigned(rs2_val))), - RISCV_ROL => if sizeof(xlen) == 32 - then rs1_val <<< rs2_val[4..0] - else rs1_val <<< rs2_val[5..0], - RISCV_ROR => if sizeof(xlen) == 32 - then rs1_val >>> rs2_val[4..0] - else rs1_val >>> rs2_val[5..0] - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/rori.yaml b/arch/inst/B/rori.yaml index 51c076667..b59bc31d5 100644 --- a/arch/inst/B/rori.yaml +++ b/arch/inst/B/rori.yaml @@ -57,14 +57,3 @@ rori: - sail(): | - { - let rs1_val = X(rs1); - let result : xlenbits = if sizeof(xlen) == 32 - then rs1_val >>> shamt[4..0] - else rs1_val >>> shamt; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/roriw.yaml b/arch/inst/B/roriw.yaml index c437420a5..4d7796ff9 100644 --- a/arch/inst/B/roriw.yaml +++ b/arch/inst/B/roriw.yaml @@ -48,12 +48,3 @@ roriw: - sail(): | - { - let rs1_val = (X(rs1))[31..0]; - let result : xlenbits = sign_extend(rs1_val >>> shamt); - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/rorw.yaml b/arch/inst/B/rorw.yaml index 7730dab58..3bba7f966 100644 --- a/arch/inst/B/rorw.yaml +++ b/arch/inst/B/rorw.yaml @@ -53,16 +53,3 @@ rorw: - sail(): | - { - let rs1_val = (X(rs1))[31..0]; - let shamt = (X(rs2))[4..0]; - let result : bits(32) = match op { - RISCV_ROLW => rs1_val <<< shamt, - RISCV_RORW => rs1_val >>> shamt - }; - X(rd) = sign_extend(result); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/sext.b.yaml b/arch/inst/B/sext.b.yaml index be6b9c575..1bb3625fe 100644 --- a/arch/inst/B/sext.b.yaml +++ b/arch/inst/B/sext.b.yaml @@ -48,16 +48,3 @@ sext.b: - sail(): | - { - let rs1_val = X(rs1); - let result : xlenbits = match op { - RISCV_SEXTB => sign_extend(rs1_val[7..0]), - RISCV_SEXTH => sign_extend(rs1_val[15..0]), - RISCV_ZEXTH => zero_extend(rs1_val[15..0]) - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/sext.h.yaml b/arch/inst/B/sext.h.yaml index 1b2f6fc49..88027697b 100644 --- a/arch/inst/B/sext.h.yaml +++ b/arch/inst/B/sext.h.yaml @@ -48,16 +48,3 @@ sext.h: - sail(): | - { - let rs1_val = X(rs1); - let result : xlenbits = match op { - RISCV_SEXTB => sign_extend(rs1_val[7..0]), - RISCV_SEXTH => sign_extend(rs1_val[15..0]), - RISCV_ZEXTH => zero_extend(rs1_val[15..0]) - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/sh1add.uw.yaml b/arch/inst/B/sh1add.uw.yaml index 8436d1a90..a4dbe0955 100644 --- a/arch/inst/B/sh1add.uw.yaml +++ b/arch/inst/B/sh1add.uw.yaml @@ -51,19 +51,3 @@ sh1add.uw: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let shamt : bits(2) = match op { - RISCV_ADDUW => 0b00, - RISCV_SH1ADDUW => 0b01, - RISCV_SH2ADDUW => 0b10, - RISCV_SH3ADDUW => 0b11 - }; - let result : xlenbits = (zero_extend(rs1_val[31..0]) << shamt) + rs2_val; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/sh1add.yaml b/arch/inst/B/sh1add.yaml index 207de32ea..d57daa99b 100644 --- a/arch/inst/B/sh1add.yaml +++ b/arch/inst/B/sh1add.yaml @@ -47,18 +47,3 @@ sh1add: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let shamt : bits(2) = match op { - RISCV_SH1ADD => 0b01, - RISCV_SH2ADD => 0b10, - RISCV_SH3ADD => 0b11 - }; - let result : xlenbits = (rs1_val << shamt) + rs2_val; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/sh2add.uw.yaml b/arch/inst/B/sh2add.uw.yaml index 0676b3f6d..1d1f0964f 100644 --- a/arch/inst/B/sh2add.uw.yaml +++ b/arch/inst/B/sh2add.uw.yaml @@ -51,19 +51,3 @@ sh2add.uw: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let shamt : bits(2) = match op { - RISCV_ADDUW => 0b00, - RISCV_SH1ADDUW => 0b01, - RISCV_SH2ADDUW => 0b10, - RISCV_SH3ADDUW => 0b11 - }; - let result : xlenbits = (zero_extend(rs1_val[31..0]) << shamt) + rs2_val; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/sh2add.yaml b/arch/inst/B/sh2add.yaml index beb8e8a5a..f7bd06c57 100644 --- a/arch/inst/B/sh2add.yaml +++ b/arch/inst/B/sh2add.yaml @@ -47,18 +47,3 @@ sh2add: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let shamt : bits(2) = match op { - RISCV_SH1ADD => 0b01, - RISCV_SH2ADD => 0b10, - RISCV_SH3ADD => 0b11 - }; - let result : xlenbits = (rs1_val << shamt) + rs2_val; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/sh3add.uw.yaml b/arch/inst/B/sh3add.uw.yaml index 8a2ca3f3b..88fef5a70 100644 --- a/arch/inst/B/sh3add.uw.yaml +++ b/arch/inst/B/sh3add.uw.yaml @@ -51,19 +51,3 @@ sh3add.uw: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let shamt : bits(2) = match op { - RISCV_ADDUW => 0b00, - RISCV_SH1ADDUW => 0b01, - RISCV_SH2ADDUW => 0b10, - RISCV_SH3ADDUW => 0b11 - }; - let result : xlenbits = (zero_extend(rs1_val[31..0]) << shamt) + rs2_val; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/sh3add.yaml b/arch/inst/B/sh3add.yaml index 57996faaf..cac8ecb02 100644 --- a/arch/inst/B/sh3add.yaml +++ b/arch/inst/B/sh3add.yaml @@ -47,18 +47,3 @@ sh3add: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let shamt : bits(2) = match op { - RISCV_SH1ADD => 0b01, - RISCV_SH2ADD => 0b10, - RISCV_SH3ADD => 0b11 - }; - let result : xlenbits = (rs1_val << shamt) + rs2_val; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/slli.uw.yaml b/arch/inst/B/slli.uw.yaml index c0109055d..cdb848ae6 100644 --- a/arch/inst/B/slli.uw.yaml +++ b/arch/inst/B/slli.uw.yaml @@ -46,12 +46,3 @@ slli.uw: - sail(): | - { - let rs1_val = X(rs1); - let result : xlenbits = zero_extend(rs1_val[31..0]) << shamt; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/xnor.yaml b/arch/inst/B/xnor.yaml index d3bd0972b..498c9fc63 100644 --- a/arch/inst/B/xnor.yaml +++ b/arch/inst/B/xnor.yaml @@ -57,27 +57,3 @@ xnor: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let result : xlenbits = match op { - RISCV_ANDN => rs1_val & ~(rs2_val), - RISCV_ORN => rs1_val | ~(rs2_val), - RISCV_XNOR => ~(rs1_val ^ rs2_val), - RISCV_MAX => to_bits(sizeof(xlen), max(signed(rs1_val), signed(rs2_val))), - RISCV_MAXU => to_bits(sizeof(xlen), max(unsigned(rs1_val), unsigned(rs2_val))), - RISCV_MIN => to_bits(sizeof(xlen), min(signed(rs1_val), signed(rs2_val))), - RISCV_MINU => to_bits(sizeof(xlen), min(unsigned(rs1_val), unsigned(rs2_val))), - RISCV_ROL => if sizeof(xlen) == 32 - then rs1_val <<< rs2_val[4..0] - else rs1_val <<< rs2_val[5..0], - RISCV_ROR => if sizeof(xlen) == 32 - then rs1_val >>> rs2_val[4..0] - else rs1_val >>> rs2_val[5..0] - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/B/zext.h.yaml b/arch/inst/B/zext.h.yaml index 28ff37096..b6cdb1cc0 100644 --- a/arch/inst/B/zext.h.yaml +++ b/arch/inst/B/zext.h.yaml @@ -59,16 +59,3 @@ zext.h: - sail(): | - { - let rs1_val = X(rs1); - let result : xlenbits = match op { - RISCV_SEXTB => sign_extend(rs1_val[7..0]), - RISCV_SEXTH => sign_extend(rs1_val[15..0]), - RISCV_ZEXTH => zero_extend(rs1_val[15..0]) - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/F/fadd.s.yaml b/arch/inst/F/fadd.s.yaml index 1a9a31f42..5fe6701c4 100644 --- a/arch/inst/F/fadd.s.yaml +++ b/arch/inst/F/fadd.s.yaml @@ -52,25 +52,3 @@ fadd.s: - sail(): | - { - let rs1_val_32b = F_or_X_S(rs1); - let rs2_val_32b = F_or_X_S(rs2); - match (select_instr_or_fcsr_rm (rm)) { - None() => { handle_illegal(); RETIRE_FAIL }, - Some(rm') => { - let rm_3b = encdec_rounding_mode(rm'); - let (fflags, rd_val_32b) : (bits(5), bits(32)) = match op { - FADD_S => riscv_f32Add (rm_3b, rs1_val_32b, rs2_val_32b), - FSUB_S => riscv_f32Sub (rm_3b, rs1_val_32b, rs2_val_32b), - FMUL_S => riscv_f32Mul (rm_3b, rs1_val_32b, rs2_val_32b), - FDIV_S => riscv_f32Div (rm_3b, rs1_val_32b, rs2_val_32b) - }; - accrue_fflags(fflags); - F_or_X_S(rd) = rd_val_32b; - RETIRE_SUCCESS - } - } - } - - \ No newline at end of file diff --git a/arch/inst/F/fclass.s.yaml b/arch/inst/F/fclass.s.yaml index c772e3436..cd74d7745 100644 --- a/arch/inst/F/fclass.s.yaml +++ b/arch/inst/F/fclass.s.yaml @@ -85,12 +85,3 @@ fclass.s: - sail(): | - { - let rs1_val_X = X(rs1); - let rd_val_S = rs1_val_X [31..0]; - F(rd) = nan_box (rd_val_S); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/F/fcvt.l.s.yaml b/arch/inst/F/fcvt.l.s.yaml index 2a8ec5314..b554cad42 100644 --- a/arch/inst/F/fcvt.l.s.yaml +++ b/arch/inst/F/fcvt.l.s.yaml @@ -47,21 +47,3 @@ fcvt.l.s: - sail(): | - { - assert(sizeof(xlen) >= 64); - let rs1_val_LU = X(rs1)[63..0]; - match (select_instr_or_fcsr_rm (rm)) { - None() => { handle_illegal(); RETIRE_FAIL }, - Some(rm') => { - let rm_3b = encdec_rounding_mode(rm'); - let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - - accrue_fflags(fflags); - F_or_X_S(rd) = rd_val_S; - RETIRE_SUCCESS - } - } - } - - \ No newline at end of file diff --git a/arch/inst/F/fcvt.lu.s.yaml b/arch/inst/F/fcvt.lu.s.yaml index 5c0c60665..08aea300d 100644 --- a/arch/inst/F/fcvt.lu.s.yaml +++ b/arch/inst/F/fcvt.lu.s.yaml @@ -47,21 +47,3 @@ fcvt.lu.s: - sail(): | - { - assert(sizeof(xlen) >= 64); - let rs1_val_LU = X(rs1)[63..0]; - match (select_instr_or_fcsr_rm (rm)) { - None() => { handle_illegal(); RETIRE_FAIL }, - Some(rm') => { - let rm_3b = encdec_rounding_mode(rm'); - let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - - accrue_fflags(fflags); - F_or_X_S(rd) = rd_val_S; - RETIRE_SUCCESS - } - } - } - - \ No newline at end of file diff --git a/arch/inst/F/fcvt.s.l.yaml b/arch/inst/F/fcvt.s.l.yaml index 9a41e41ce..c8b44f540 100644 --- a/arch/inst/F/fcvt.s.l.yaml +++ b/arch/inst/F/fcvt.s.l.yaml @@ -47,21 +47,3 @@ fcvt.s.l: - sail(): | - { - assert(sizeof(xlen) >= 64); - let rs1_val_LU = X(rs1)[63..0]; - match (select_instr_or_fcsr_rm (rm)) { - None() => { handle_illegal(); RETIRE_FAIL }, - Some(rm') => { - let rm_3b = encdec_rounding_mode(rm'); - let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - - accrue_fflags(fflags); - F_or_X_S(rd) = rd_val_S; - RETIRE_SUCCESS - } - } - } - - \ No newline at end of file diff --git a/arch/inst/F/fcvt.s.lu.yaml b/arch/inst/F/fcvt.s.lu.yaml index 9e1bd3c69..4b4c584b9 100644 --- a/arch/inst/F/fcvt.s.lu.yaml +++ b/arch/inst/F/fcvt.s.lu.yaml @@ -47,21 +47,3 @@ fcvt.s.lu: - sail(): | - { - assert(sizeof(xlen) >= 64); - let rs1_val_LU = X(rs1)[63..0]; - match (select_instr_or_fcsr_rm (rm)) { - None() => { handle_illegal(); RETIRE_FAIL }, - Some(rm') => { - let rm_3b = encdec_rounding_mode(rm'); - let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - - accrue_fflags(fflags); - F_or_X_S(rd) = rd_val_S; - RETIRE_SUCCESS - } - } - } - - \ No newline at end of file diff --git a/arch/inst/F/fcvt.s.w.yaml b/arch/inst/F/fcvt.s.w.yaml index 4dbb1291e..494042765 100644 --- a/arch/inst/F/fcvt.s.w.yaml +++ b/arch/inst/F/fcvt.s.w.yaml @@ -71,21 +71,3 @@ fcvt.s.w: - sail(): | - { - assert(sizeof(xlen) >= 64); - let rs1_val_LU = X(rs1)[63..0]; - match (select_instr_or_fcsr_rm (rm)) { - None() => { handle_illegal(); RETIRE_FAIL }, - Some(rm') => { - let rm_3b = encdec_rounding_mode(rm'); - let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - - accrue_fflags(fflags); - F_or_X_S(rd) = rd_val_S; - RETIRE_SUCCESS - } - } - } - - \ No newline at end of file diff --git a/arch/inst/F/fcvt.s.wu.yaml b/arch/inst/F/fcvt.s.wu.yaml index 4d5b8c8f8..27a205b3b 100644 --- a/arch/inst/F/fcvt.s.wu.yaml +++ b/arch/inst/F/fcvt.s.wu.yaml @@ -46,21 +46,3 @@ fcvt.s.wu: - sail(): | - { - assert(sizeof(xlen) >= 64); - let rs1_val_LU = X(rs1)[63..0]; - match (select_instr_or_fcsr_rm (rm)) { - None() => { handle_illegal(); RETIRE_FAIL }, - Some(rm') => { - let rm_3b = encdec_rounding_mode(rm'); - let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - - accrue_fflags(fflags); - F_or_X_S(rd) = rd_val_S; - RETIRE_SUCCESS - } - } - } - - \ No newline at end of file diff --git a/arch/inst/F/fcvt.w.s.yaml b/arch/inst/F/fcvt.w.s.yaml index 62f28c3af..e8a8f9f97 100644 --- a/arch/inst/F/fcvt.w.s.yaml +++ b/arch/inst/F/fcvt.w.s.yaml @@ -101,21 +101,3 @@ fcvt.w.s: - sail(): | - { - assert(sizeof(xlen) >= 64); - let rs1_val_LU = X(rs1)[63..0]; - match (select_instr_or_fcsr_rm (rm)) { - None() => { handle_illegal(); RETIRE_FAIL }, - Some(rm') => { - let rm_3b = encdec_rounding_mode(rm'); - let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - - accrue_fflags(fflags); - F_or_X_S(rd) = rd_val_S; - RETIRE_SUCCESS - } - } - } - - \ No newline at end of file diff --git a/arch/inst/F/fcvt.wu.s.yaml b/arch/inst/F/fcvt.wu.s.yaml index 30cdc6871..0c559f711 100644 --- a/arch/inst/F/fcvt.wu.s.yaml +++ b/arch/inst/F/fcvt.wu.s.yaml @@ -46,21 +46,3 @@ fcvt.wu.s: - sail(): | - { - assert(sizeof(xlen) >= 64); - let rs1_val_LU = X(rs1)[63..0]; - match (select_instr_or_fcsr_rm (rm)) { - None() => { handle_illegal(); RETIRE_FAIL }, - Some(rm') => { - let rm_3b = encdec_rounding_mode(rm'); - let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - - accrue_fflags(fflags); - F_or_X_S(rd) = rd_val_S; - RETIRE_SUCCESS - } - } - } - - \ No newline at end of file diff --git a/arch/inst/F/fdiv.s.yaml b/arch/inst/F/fdiv.s.yaml index ba9d7e8d3..9ea50b9be 100644 --- a/arch/inst/F/fdiv.s.yaml +++ b/arch/inst/F/fdiv.s.yaml @@ -52,25 +52,3 @@ fdiv.s: - sail(): | - { - let rs1_val_32b = F_or_X_S(rs1); - let rs2_val_32b = F_or_X_S(rs2); - match (select_instr_or_fcsr_rm (rm)) { - None() => { handle_illegal(); RETIRE_FAIL }, - Some(rm') => { - let rm_3b = encdec_rounding_mode(rm'); - let (fflags, rd_val_32b) : (bits(5), bits(32)) = match op { - FADD_S => riscv_f32Add (rm_3b, rs1_val_32b, rs2_val_32b), - FSUB_S => riscv_f32Sub (rm_3b, rs1_val_32b, rs2_val_32b), - FMUL_S => riscv_f32Mul (rm_3b, rs1_val_32b, rs2_val_32b), - FDIV_S => riscv_f32Div (rm_3b, rs1_val_32b, rs2_val_32b) - }; - accrue_fflags(fflags); - F_or_X_S(rd) = rd_val_32b; - RETIRE_SUCCESS - } - } - } - - \ No newline at end of file diff --git a/arch/inst/F/feq.s.yaml b/arch/inst/F/feq.s.yaml index 9030a6d16..dbd9767f5 100644 --- a/arch/inst/F/feq.s.yaml +++ b/arch/inst/F/feq.s.yaml @@ -62,17 +62,3 @@ feq.s: - sail(): | - { - let rs1_val_S = F_or_X_S(rs1); - let rs2_val_S = F_or_X_S(rs2); - - let (fflags, rd_val) : (bits_fflags, bool) = - riscv_f32Le (rs1_val_S, rs2_val_S); - - accrue_fflags(fflags); - X(rd) = zero_extend(bool_to_bits(rd_val)); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/F/fle.s.yaml b/arch/inst/F/fle.s.yaml index 29a8b87f1..0cd959280 100644 --- a/arch/inst/F/fle.s.yaml +++ b/arch/inst/F/fle.s.yaml @@ -63,17 +63,3 @@ fle.s: - sail(): | - { - let rs1_val_S = F_or_X_S(rs1); - let rs2_val_S = F_or_X_S(rs2); - - let (fflags, rd_val) : (bits_fflags, bool) = - riscv_f32Le (rs1_val_S, rs2_val_S); - - accrue_fflags(fflags); - X(rd) = zero_extend(bool_to_bits(rd_val)); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/F/fleq.s.yaml b/arch/inst/F/fleq.s.yaml index d88723a67..f1429b54d 100644 --- a/arch/inst/F/fleq.s.yaml +++ b/arch/inst/F/fleq.s.yaml @@ -42,17 +42,3 @@ fleq.s: - sail(): | - { - let rs1_val_S = F_S(rs1); - let rs2_val_S = F_S(rs2); - - let (fflags, rd_val) : (bits_fflags, bool) = - riscv_f32Le_quiet (rs1_val_S, rs2_val_S); - - accrue_fflags(fflags); - X(rd) = zero_extend(bool_to_bits(rd_val)); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/F/fli.s.yaml b/arch/inst/F/fli.s.yaml index 104ff6461..e863560f7 100644 --- a/arch/inst/F/fli.s.yaml +++ b/arch/inst/F/fli.s.yaml @@ -67,44 +67,3 @@ fli.s: - sail(): | - { - let bits : bits(32) = match constantidx { - 0b00000 => { 0xbf800000 }, /* -1.0 */ - 0b00001 => { 0x00800000 }, /* minimum positive normal */ - 0b00010 => { 0x37800000 }, /* 1.0 * 2^-16 */ - 0b00011 => { 0x38000000 }, /* 1.0 * 2^-15 */ - 0b00100 => { 0x3b800000 }, /* 1.0 * 2^-8 */ - 0b00101 => { 0x3c000000 }, /* 1.0 * 2^-7 */ - 0b00110 => { 0x3d800000 }, /* 1.0 * 2^-4 */ - 0b00111 => { 0x3e000000 }, /* 1.0 * 2^-3 */ - 0b01000 => { 0x3e800000 }, /* 0.25 */ - 0b01001 => { 0x3ea00000 }, /* 0.3125 */ - 0b01010 => { 0x3ec00000 }, /* 0.375 */ - 0b01011 => { 0x3ee00000 }, /* 0.4375 */ - 0b01100 => { 0x3f000000 }, /* 0.5 */ - 0b01101 => { 0x3f200000 }, /* 0.625 */ - 0b01110 => { 0x3f400000 }, /* 0.75 */ - 0b01111 => { 0x3f600000 }, /* 0.875 */ - 0b10000 => { 0x3f800000 }, /* 1.0 */ - 0b10001 => { 0x3fa00000 }, /* 1.25 */ - 0b10010 => { 0x3fc00000 }, /* 1.5 */ - 0b10011 => { 0x3fe00000 }, /* 1.75 */ - 0b10100 => { 0x40000000 }, /* 2.0 */ - 0b10101 => { 0x40200000 }, /* 2.5 */ - 0b10110 => { 0x40400000 }, /* 3 */ - 0b10111 => { 0x40800000 }, /* 4 */ - 0b11000 => { 0x41000000 }, /* 8 */ - 0b11001 => { 0x41800000 }, /* 16 */ - 0b11010 => { 0x43000000 }, /* 2^7 */ - 0b11011 => { 0x43800000 }, /* 2^8 */ - 0b11100 => { 0x47000000 }, /* 2^15 */ - 0b11101 => { 0x47800000 }, /* 2^16 */ - 0b11110 => { 0x7f800000 }, /* +inf */ - 0b11111 => { canonical_NaN_S() }, - }; - F_S(rd) = bits; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/F/flt.s.yaml b/arch/inst/F/flt.s.yaml index 664bf15bd..055870024 100644 --- a/arch/inst/F/flt.s.yaml +++ b/arch/inst/F/flt.s.yaml @@ -65,17 +65,3 @@ flt.s: - sail(): | - { - let rs1_val_S = F_or_X_S(rs1); - let rs2_val_S = F_or_X_S(rs2); - - let (fflags, rd_val) : (bits_fflags, bool) = - riscv_f32Le (rs1_val_S, rs2_val_S); - - accrue_fflags(fflags); - X(rd) = zero_extend(bool_to_bits(rd_val)); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/F/fltq.s.yaml b/arch/inst/F/fltq.s.yaml index 06b7d3643..37a0341cf 100644 --- a/arch/inst/F/fltq.s.yaml +++ b/arch/inst/F/fltq.s.yaml @@ -42,17 +42,3 @@ fltq.s: - sail(): | - { - let rs1_val_S = F_S(rs1); - let rs2_val_S = F_S(rs2); - - let (fflags, rd_val) : (bits_fflags, bool) = - riscv_f32Lt_quiet (rs1_val_S, rs2_val_S); - - accrue_fflags(fflags); - X(rd) = zero_extend(bool_to_bits(rd_val)); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/F/flw.yaml b/arch/inst/F/flw.yaml index acdb98e87..b120cac93 100644 --- a/arch/inst/F/flw.yaml +++ b/arch/inst/F/flw.yaml @@ -72,33 +72,3 @@ flw: - sail(): | - { - let offset : xlenbits = sign_extend(imm); - /* Get the address, X(rs1) + offset. - Some extensions perform additional checks on address validity. */ - match ext_data_get_addr(rs1, offset, Read(Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => - if check_misaligned(vaddr, width) - then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } - else match translateAddr(vaddr, Read(Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => { - let (aq, rl, res) = (false, false, false); - match (width) { - BYTE => { handle_illegal(); RETIRE_FAIL }, - HALF => - process_fload16(rd, vaddr, mem_read(Read(Data), addr, 2, aq, rl, res)), - WORD => - process_fload32(rd, vaddr, mem_read(Read(Data), addr, 4, aq, rl, res)), - DOUBLE if sizeof(flen) >= 64 => - process_fload64(rd, vaddr, mem_read(Read(Data), addr, 8, aq, rl, res)), - _ => report_invalid_width(__FILE__, __LINE__, width, "floating point load"), - } - } - } - } - } - - \ No newline at end of file diff --git a/arch/inst/F/fmadd.s.yaml b/arch/inst/F/fmadd.s.yaml index e4e1bbcee..7a42d5d03 100644 --- a/arch/inst/F/fmadd.s.yaml +++ b/arch/inst/F/fmadd.s.yaml @@ -56,27 +56,3 @@ fmadd.s: - sail(): | - { - let rs1_val_32b = F_or_X_S(rs1); - let rs2_val_32b = F_or_X_S(rs2); - let rs3_val_32b = F_or_X_S(rs3); - match (select_instr_or_fcsr_rm (rm)) { - None() => { handle_illegal(); RETIRE_FAIL }, - Some(rm') => { - let rm_3b = encdec_rounding_mode(rm'); - let (fflags, rd_val_32b) : (bits(5), bits(32)) = - match op { - FMADD_S => riscv_f32MulAdd (rm_3b, rs1_val_32b, rs2_val_32b, rs3_val_32b), - FMSUB_S => riscv_f32MulAdd (rm_3b, rs1_val_32b, rs2_val_32b, negate_S (rs3_val_32b)), - FNMSUB_S => riscv_f32MulAdd (rm_3b, negate_S (rs1_val_32b), rs2_val_32b, rs3_val_32b), - FNMADD_S => riscv_f32MulAdd (rm_3b, negate_S (rs1_val_32b), rs2_val_32b, negate_S (rs3_val_32b)) - }; - accrue_fflags(fflags); - F_or_X_S(rd) = rd_val_32b; - RETIRE_SUCCESS - } - } - } - - \ No newline at end of file diff --git a/arch/inst/F/fmax.s.yaml b/arch/inst/F/fmax.s.yaml index 1847dbb3f..1be7f1646 100644 --- a/arch/inst/F/fmax.s.yaml +++ b/arch/inst/F/fmax.s.yaml @@ -42,17 +42,3 @@ fmax.s: - sail(): | - { - let rs1_val_S = F_or_X_S(rs1); - let rs2_val_S = F_or_X_S(rs2); - - let (fflags, rd_val) : (bits_fflags, bool) = - riscv_f32Le (rs1_val_S, rs2_val_S); - - accrue_fflags(fflags); - X(rd) = zero_extend(bool_to_bits(rd_val)); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/F/fmaxm.s.yaml b/arch/inst/F/fmaxm.s.yaml index dde813501..fb1306aa9 100644 --- a/arch/inst/F/fmaxm.s.yaml +++ b/arch/inst/F/fmaxm.s.yaml @@ -48,23 +48,3 @@ fmaxm.s: - sail(): | - { - let rs1_val_S = F_S(rs1); - let rs2_val_S = F_S(rs2); - - let is_quiet = true; - let (rs2_lt_rs1, fflags) = fle_S (rs2_val_S, rs1_val_S, is_quiet); - - let rd_val_S = if (f_is_NaN_S(rs1_val_S) | f_is_NaN_S(rs2_val_S)) then canonical_NaN_S() - else if (f_is_neg_zero_S(rs1_val_S) & f_is_pos_zero_S(rs2_val_S)) then rs2_val_S - else if (f_is_neg_zero_S(rs2_val_S) & f_is_pos_zero_S(rs1_val_S)) then rs1_val_S - else if rs2_lt_rs1 then rs1_val_S - else /* (not rs2_lt_rs1) */ rs2_val_S; - - accrue_fflags(fflags); - F_S(rd) = rd_val_S; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/F/fmin.s.yaml b/arch/inst/F/fmin.s.yaml index 99d46d86b..ee99b07cc 100644 --- a/arch/inst/F/fmin.s.yaml +++ b/arch/inst/F/fmin.s.yaml @@ -42,17 +42,3 @@ fmin.s: - sail(): | - { - let rs1_val_S = F_or_X_S(rs1); - let rs2_val_S = F_or_X_S(rs2); - - let (fflags, rd_val) : (bits_fflags, bool) = - riscv_f32Le (rs1_val_S, rs2_val_S); - - accrue_fflags(fflags); - X(rd) = zero_extend(bool_to_bits(rd_val)); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/F/fminm.s.yaml b/arch/inst/F/fminm.s.yaml index ff19aeb71..654cd126c 100644 --- a/arch/inst/F/fminm.s.yaml +++ b/arch/inst/F/fminm.s.yaml @@ -48,23 +48,3 @@ fminm.s: - sail(): | - { - let rs1_val_S = F_S(rs1); - let rs2_val_S = F_S(rs2); - - let is_quiet = true; - let (rs1_lt_rs2, fflags) = fle_S (rs1_val_S, rs2_val_S, is_quiet); - - let rd_val_S = if (f_is_NaN_S(rs1_val_S) | f_is_NaN_S(rs2_val_S)) then canonical_NaN_S() - else if (f_is_neg_zero_S(rs1_val_S) & f_is_pos_zero_S(rs2_val_S)) then rs1_val_S - else if (f_is_neg_zero_S(rs2_val_S) & f_is_pos_zero_S(rs1_val_S)) then rs2_val_S - else if rs1_lt_rs2 then rs1_val_S - else /* (not rs1_lt_rs2) */ rs2_val_S; - - accrue_fflags(fflags); - F_S(rd) = rd_val_S; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/F/fmsub.s.yaml b/arch/inst/F/fmsub.s.yaml index 90be8eb14..b8273c830 100644 --- a/arch/inst/F/fmsub.s.yaml +++ b/arch/inst/F/fmsub.s.yaml @@ -56,27 +56,3 @@ fmsub.s: - sail(): | - { - let rs1_val_32b = F_or_X_S(rs1); - let rs2_val_32b = F_or_X_S(rs2); - let rs3_val_32b = F_or_X_S(rs3); - match (select_instr_or_fcsr_rm (rm)) { - None() => { handle_illegal(); RETIRE_FAIL }, - Some(rm') => { - let rm_3b = encdec_rounding_mode(rm'); - let (fflags, rd_val_32b) : (bits(5), bits(32)) = - match op { - FMADD_S => riscv_f32MulAdd (rm_3b, rs1_val_32b, rs2_val_32b, rs3_val_32b), - FMSUB_S => riscv_f32MulAdd (rm_3b, rs1_val_32b, rs2_val_32b, negate_S (rs3_val_32b)), - FNMSUB_S => riscv_f32MulAdd (rm_3b, negate_S (rs1_val_32b), rs2_val_32b, rs3_val_32b), - FNMADD_S => riscv_f32MulAdd (rm_3b, negate_S (rs1_val_32b), rs2_val_32b, negate_S (rs3_val_32b)) - }; - accrue_fflags(fflags); - F_or_X_S(rd) = rd_val_32b; - RETIRE_SUCCESS - } - } - } - - \ No newline at end of file diff --git a/arch/inst/F/fmul.s.yaml b/arch/inst/F/fmul.s.yaml index 567f6fa96..351349e4e 100644 --- a/arch/inst/F/fmul.s.yaml +++ b/arch/inst/F/fmul.s.yaml @@ -52,25 +52,3 @@ fmul.s: - sail(): | - { - let rs1_val_32b = F_or_X_S(rs1); - let rs2_val_32b = F_or_X_S(rs2); - match (select_instr_or_fcsr_rm (rm)) { - None() => { handle_illegal(); RETIRE_FAIL }, - Some(rm') => { - let rm_3b = encdec_rounding_mode(rm'); - let (fflags, rd_val_32b) : (bits(5), bits(32)) = match op { - FADD_S => riscv_f32Add (rm_3b, rs1_val_32b, rs2_val_32b), - FSUB_S => riscv_f32Sub (rm_3b, rs1_val_32b, rs2_val_32b), - FMUL_S => riscv_f32Mul (rm_3b, rs1_val_32b, rs2_val_32b), - FDIV_S => riscv_f32Div (rm_3b, rs1_val_32b, rs2_val_32b) - }; - accrue_fflags(fflags); - F_or_X_S(rd) = rd_val_32b; - RETIRE_SUCCESS - } - } - } - - \ No newline at end of file diff --git a/arch/inst/F/fmv.w.x.yaml b/arch/inst/F/fmv.w.x.yaml index f8d0e7874..2fe7e02b0 100644 --- a/arch/inst/F/fmv.w.x.yaml +++ b/arch/inst/F/fmv.w.x.yaml @@ -48,12 +48,3 @@ fmv.w.x: - sail(): | - { - let rs1_val_X = X(rs1); - let rd_val_S = rs1_val_X [31..0]; - F(rd) = nan_box (rd_val_S); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/F/fmv.x.w.yaml b/arch/inst/F/fmv.x.w.yaml index 8391eae54..70e4e6dae 100644 --- a/arch/inst/F/fmv.x.w.yaml +++ b/arch/inst/F/fmv.x.w.yaml @@ -42,12 +42,3 @@ fmv.x.w: - sail(): | - { - let rs1_val_X = X(rs1); - let rd_val_S = rs1_val_X [31..0]; - F(rd) = nan_box (rd_val_S); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/F/fnmadd.s.yaml b/arch/inst/F/fnmadd.s.yaml index d7931bdb6..b18f52274 100644 --- a/arch/inst/F/fnmadd.s.yaml +++ b/arch/inst/F/fnmadd.s.yaml @@ -56,27 +56,3 @@ fnmadd.s: - sail(): | - { - let rs1_val_32b = F_or_X_S(rs1); - let rs2_val_32b = F_or_X_S(rs2); - let rs3_val_32b = F_or_X_S(rs3); - match (select_instr_or_fcsr_rm (rm)) { - None() => { handle_illegal(); RETIRE_FAIL }, - Some(rm') => { - let rm_3b = encdec_rounding_mode(rm'); - let (fflags, rd_val_32b) : (bits(5), bits(32)) = - match op { - FMADD_S => riscv_f32MulAdd (rm_3b, rs1_val_32b, rs2_val_32b, rs3_val_32b), - FMSUB_S => riscv_f32MulAdd (rm_3b, rs1_val_32b, rs2_val_32b, negate_S (rs3_val_32b)), - FNMSUB_S => riscv_f32MulAdd (rm_3b, negate_S (rs1_val_32b), rs2_val_32b, rs3_val_32b), - FNMADD_S => riscv_f32MulAdd (rm_3b, negate_S (rs1_val_32b), rs2_val_32b, negate_S (rs3_val_32b)) - }; - accrue_fflags(fflags); - F_or_X_S(rd) = rd_val_32b; - RETIRE_SUCCESS - } - } - } - - \ No newline at end of file diff --git a/arch/inst/F/fnmsub.s.yaml b/arch/inst/F/fnmsub.s.yaml index 4e4677a8c..c79919e0c 100644 --- a/arch/inst/F/fnmsub.s.yaml +++ b/arch/inst/F/fnmsub.s.yaml @@ -56,27 +56,3 @@ fnmsub.s: - sail(): | - { - let rs1_val_32b = F_or_X_S(rs1); - let rs2_val_32b = F_or_X_S(rs2); - let rs3_val_32b = F_or_X_S(rs3); - match (select_instr_or_fcsr_rm (rm)) { - None() => { handle_illegal(); RETIRE_FAIL }, - Some(rm') => { - let rm_3b = encdec_rounding_mode(rm'); - let (fflags, rd_val_32b) : (bits(5), bits(32)) = - match op { - FMADD_S => riscv_f32MulAdd (rm_3b, rs1_val_32b, rs2_val_32b, rs3_val_32b), - FMSUB_S => riscv_f32MulAdd (rm_3b, rs1_val_32b, rs2_val_32b, negate_S (rs3_val_32b)), - FNMSUB_S => riscv_f32MulAdd (rm_3b, negate_S (rs1_val_32b), rs2_val_32b, rs3_val_32b), - FNMADD_S => riscv_f32MulAdd (rm_3b, negate_S (rs1_val_32b), rs2_val_32b, negate_S (rs3_val_32b)) - }; - accrue_fflags(fflags); - F_or_X_S(rd) = rd_val_32b; - RETIRE_SUCCESS - } - } - } - - \ No newline at end of file diff --git a/arch/inst/F/fround.s.yaml b/arch/inst/F/fround.s.yaml index 2e0981458..1abaee7cf 100644 --- a/arch/inst/F/fround.s.yaml +++ b/arch/inst/F/fround.s.yaml @@ -46,21 +46,3 @@ fround.s: - sail(): | - { - let rs1_val_S = F_S(rs1); - - match (select_instr_or_fcsr_rm(rm)) { - None() => { handle_illegal(); RETIRE_FAIL }, - Some(rm') => { - let rm_3b = encdec_rounding_mode(rm'); - let (fflags, rd_val_S) = riscv_f32roundToInt(rm_3b, rs1_val_S, false); - - accrue_fflags(fflags); - F_S(rd) = rd_val_S; - RETIRE_SUCCESS - } - } - } - - \ No newline at end of file diff --git a/arch/inst/F/froundnx.s.yaml b/arch/inst/F/froundnx.s.yaml index 9da0a63b9..e2ff58391 100644 --- a/arch/inst/F/froundnx.s.yaml +++ b/arch/inst/F/froundnx.s.yaml @@ -46,21 +46,3 @@ froundnx.s: - sail(): | - { - let rs1_val_S = F_S(rs1); - - match (select_instr_or_fcsr_rm(rm)) { - None() => { handle_illegal(); RETIRE_FAIL }, - Some(rm') => { - let rm_3b = encdec_rounding_mode(rm'); - let (fflags, rd_val_S) = riscv_f32roundToInt(rm_3b, rs1_val_S, true); - - accrue_fflags(fflags); - F_S(rd) = rd_val_S; - RETIRE_SUCCESS - } - } - } - - \ No newline at end of file diff --git a/arch/inst/F/fsgnj.s.yaml b/arch/inst/F/fsgnj.s.yaml index 385b47beb..2e18fada4 100644 --- a/arch/inst/F/fsgnj.s.yaml +++ b/arch/inst/F/fsgnj.s.yaml @@ -59,17 +59,3 @@ fsgnj.s: - sail(): | - { - let rs1_val_S = F_or_X_S(rs1); - let rs2_val_S = F_or_X_S(rs2); - - let (fflags, rd_val) : (bits_fflags, bool) = - riscv_f32Le (rs1_val_S, rs2_val_S); - - accrue_fflags(fflags); - X(rd) = zero_extend(bool_to_bits(rd_val)); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/F/fsgnjn.s.yaml b/arch/inst/F/fsgnjn.s.yaml index 92843466d..e9d9fee17 100644 --- a/arch/inst/F/fsgnjn.s.yaml +++ b/arch/inst/F/fsgnjn.s.yaml @@ -58,17 +58,3 @@ fsgnjn.s: - sail(): | - { - let rs1_val_S = F_or_X_S(rs1); - let rs2_val_S = F_or_X_S(rs2); - - let (fflags, rd_val) : (bits_fflags, bool) = - riscv_f32Le (rs1_val_S, rs2_val_S); - - accrue_fflags(fflags); - X(rd) = zero_extend(bool_to_bits(rd_val)); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/F/fsgnjx.s.yaml b/arch/inst/F/fsgnjx.s.yaml index 59b7aa779..b10b77967 100644 --- a/arch/inst/F/fsgnjx.s.yaml +++ b/arch/inst/F/fsgnjx.s.yaml @@ -57,17 +57,3 @@ fsgnjx.s: - sail(): | - { - let rs1_val_S = F_or_X_S(rs1); - let rs2_val_S = F_or_X_S(rs2); - - let (fflags, rd_val) : (bits_fflags, bool) = - riscv_f32Le (rs1_val_S, rs2_val_S); - - accrue_fflags(fflags); - X(rd) = zero_extend(bool_to_bits(rd_val)); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/F/fsqrt.s.yaml b/arch/inst/F/fsqrt.s.yaml index 5fd0e4da3..7bbf5f9f8 100644 --- a/arch/inst/F/fsqrt.s.yaml +++ b/arch/inst/F/fsqrt.s.yaml @@ -46,21 +46,3 @@ fsqrt.s: - sail(): | - { - assert(sizeof(xlen) >= 64); - let rs1_val_LU = X(rs1)[63..0]; - match (select_instr_or_fcsr_rm (rm)) { - None() => { handle_illegal(); RETIRE_FAIL }, - Some(rm') => { - let rm_3b = encdec_rounding_mode(rm'); - let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); - - accrue_fflags(fflags); - F_or_X_S(rd) = rd_val_S; - RETIRE_SUCCESS - } - } - } - - \ No newline at end of file diff --git a/arch/inst/F/fsub.s.yaml b/arch/inst/F/fsub.s.yaml index 36ddcde5a..3f8787686 100644 --- a/arch/inst/F/fsub.s.yaml +++ b/arch/inst/F/fsub.s.yaml @@ -52,25 +52,3 @@ fsub.s: - sail(): | - { - let rs1_val_32b = F_or_X_S(rs1); - let rs2_val_32b = F_or_X_S(rs2); - match (select_instr_or_fcsr_rm (rm)) { - None() => { handle_illegal(); RETIRE_FAIL }, - Some(rm') => { - let rm_3b = encdec_rounding_mode(rm'); - let (fflags, rd_val_32b) : (bits(5), bits(32)) = match op { - FADD_S => riscv_f32Add (rm_3b, rs1_val_32b, rs2_val_32b), - FSUB_S => riscv_f32Sub (rm_3b, rs1_val_32b, rs2_val_32b), - FMUL_S => riscv_f32Mul (rm_3b, rs1_val_32b, rs2_val_32b), - FDIV_S => riscv_f32Div (rm_3b, rs1_val_32b, rs2_val_32b) - }; - accrue_fflags(fflags); - F_or_X_S(rd) = rd_val_32b; - RETIRE_SUCCESS - } - } - } - - \ No newline at end of file diff --git a/arch/inst/F/fsw.yaml b/arch/inst/F/fsw.yaml index b2b2d514a..f24c2ab7e 100644 --- a/arch/inst/F/fsw.yaml +++ b/arch/inst/F/fsw.yaml @@ -75,43 +75,3 @@ fsw: - sail(): | - { - let offset : xlenbits = sign_extend(imm); - let (aq, rl, con) = (false, false, false); - /* Get the address, X(rs1) + offset. - Some extensions perform additional checks on address validity. */ - match ext_data_get_addr(rs1, offset, Write(Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => - if check_misaligned(vaddr, width) - then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL } - else match translateAddr(vaddr, Write(Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => { - let eares : MemoryOpResult(unit) = match width { - BYTE => MemValue () /* bogus placeholder for illegal size */, - HALF => mem_write_ea(addr, 2, aq, rl, false), - WORD => mem_write_ea(addr, 4, aq, rl, false), - DOUBLE => mem_write_ea(addr, 8, aq, rl, false) - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - let rs2_val = F(rs2); - match (width) { - BYTE => { handle_illegal(); RETIRE_FAIL }, - HALF => process_fstore (vaddr, mem_write_value(addr, 2, rs2_val[15..0], aq, rl, con)), - WORD => process_fstore (vaddr, mem_write_value(addr, 4, rs2_val[31..0], aq, rl, con)), - DOUBLE if sizeof(flen) >= 64 => - process_fstore (vaddr, mem_write_value(addr, 8, rs2_val, aq, rl, con)), - _ => report_invalid_width(__FILE__, __LINE__, width, "floating point store"), - }; - } - } - } - } - } - } - - \ No newline at end of file diff --git a/arch/inst/I/add.yaml b/arch/inst/I/add.yaml index 923a1a026..bfd038c41 100644 --- a/arch/inst/I/add.yaml +++ b/arch/inst/I/add.yaml @@ -55,30 +55,3 @@ add: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let result : xlenbits = match op { - RISCV_ADD => rs1_val + rs2_val, - RISCV_SLT => zero_extend(bool_to_bits(rs1_val <_s rs2_val)), - RISCV_SLTU => zero_extend(bool_to_bits(rs1_val <_u rs2_val)), - RISCV_AND => rs1_val & rs2_val, - RISCV_OR => rs1_val | rs2_val, - RISCV_XOR => rs1_val ^ rs2_val, - RISCV_SLL => if sizeof(xlen) == 32 - then rs1_val << (rs2_val[4..0]) - else rs1_val << (rs2_val[5..0]), - RISCV_SRL => if sizeof(xlen) == 32 - then rs1_val >> (rs2_val[4..0]) - else rs1_val >> (rs2_val[5..0]), - RISCV_SUB => rs1_val - rs2_val, - RISCV_SRA => if sizeof(xlen) == 32 - then shift_right_arith32(rs1_val, rs2_val[4..0]) - else shift_right_arith64(rs1_val, rs2_val[5..0]) - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/addi.yaml b/arch/inst/I/addi.yaml index 57288e9f1..b4d3852ce 100644 --- a/arch/inst/I/addi.yaml +++ b/arch/inst/I/addi.yaml @@ -43,20 +43,3 @@ addi: - sail(): | - { - let rs1_val = X(rs1); - let immext : xlenbits = sign_extend(imm); - let result : xlenbits = match op { - RISCV_ADDI => rs1_val + immext, - RISCV_SLTI => zero_extend(bool_to_bits(rs1_val <_s immext)), - RISCV_SLTIU => zero_extend(bool_to_bits(rs1_val <_u immext)), - RISCV_ANDI => rs1_val & immext, - RISCV_ORI => rs1_val | immext, - RISCV_XORI => rs1_val ^ immext - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/addiw.yaml b/arch/inst/I/addiw.yaml index 59262bdc2..073009c09 100644 --- a/arch/inst/I/addiw.yaml +++ b/arch/inst/I/addiw.yaml @@ -37,11 +37,3 @@ addiw: - sail(): | - { - let result : xlenbits = sign_extend(imm) + X(rs1); - X(rd) = sign_extend(result[31..0]); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/addw.yaml b/arch/inst/I/addw.yaml index 4f3dc835e..da260b449 100644 --- a/arch/inst/I/addw.yaml +++ b/arch/inst/I/addw.yaml @@ -48,19 +48,3 @@ addw: - sail(): | - { - let rs1_val = (X(rs1))[31..0]; - let rs2_val = (X(rs2))[31..0]; - let result : bits(32) = match op { - RISCV_ADDW => rs1_val + rs2_val, - RISCV_SUBW => rs1_val - rs2_val, - RISCV_SLLW => rs1_val << (rs2_val[4..0]), - RISCV_SRLW => rs1_val >> (rs2_val[4..0]), - RISCV_SRAW => shift_right_arith32(rs1_val, rs2_val[4..0]) - }; - X(rd) = sign_extend(result); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/and.yaml b/arch/inst/I/and.yaml index 34215edbc..3f53c135b 100644 --- a/arch/inst/I/and.yaml +++ b/arch/inst/I/and.yaml @@ -53,30 +53,3 @@ and: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let result : xlenbits = match op { - RISCV_ADD => rs1_val + rs2_val, - RISCV_SLT => zero_extend(bool_to_bits(rs1_val <_s rs2_val)), - RISCV_SLTU => zero_extend(bool_to_bits(rs1_val <_u rs2_val)), - RISCV_AND => rs1_val & rs2_val, - RISCV_OR => rs1_val | rs2_val, - RISCV_XOR => rs1_val ^ rs2_val, - RISCV_SLL => if sizeof(xlen) == 32 - then rs1_val << (rs2_val[4..0]) - else rs1_val << (rs2_val[5..0]), - RISCV_SRL => if sizeof(xlen) == 32 - then rs1_val >> (rs2_val[4..0]) - else rs1_val >> (rs2_val[5..0]), - RISCV_SUB => rs1_val - rs2_val, - RISCV_SRA => if sizeof(xlen) == 32 - then shift_right_arith32(rs1_val, rs2_val[4..0]) - else shift_right_arith64(rs1_val, rs2_val[5..0]) - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/andi.yaml b/arch/inst/I/andi.yaml index 966108568..b313d0fc2 100644 --- a/arch/inst/I/andi.yaml +++ b/arch/inst/I/andi.yaml @@ -43,20 +43,3 @@ andi: - sail(): | - { - let rs1_val = X(rs1); - let immext : xlenbits = sign_extend(imm); - let result : xlenbits = match op { - RISCV_ADDI => rs1_val + immext, - RISCV_SLTI => zero_extend(bool_to_bits(rs1_val <_s immext)), - RISCV_SLTIU => zero_extend(bool_to_bits(rs1_val <_u immext)), - RISCV_ANDI => rs1_val & immext, - RISCV_ORI => rs1_val | immext, - RISCV_XORI => rs1_val ^ immext - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/beq.yaml b/arch/inst/I/beq.yaml index 510b8e5bd..e60c670f9 100644 --- a/arch/inst/I/beq.yaml +++ b/arch/inst/I/beq.yaml @@ -69,37 +69,3 @@ beq: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let taken : bool = match op { - RISCV_BEQ => rs1_val == rs2_val, - RISCV_BNE => rs1_val != rs2_val, - RISCV_BLT => rs1_val <_s rs2_val, - RISCV_BGE => rs1_val >=_s rs2_val, - RISCV_BLTU => rs1_val <_u rs2_val, - RISCV_BGEU => rs1_val >=_u rs2_val - }; - let t : xlenbits = PC + sign_extend(imm); - if taken then { - /* Extensions get the first checks on the prospective target address. */ - match ext_control_check_pc(t) { - Ext_ControlAddr_Error(e) => { - ext_handle_control_check_error(e); - RETIRE_FAIL - }, - Ext_ControlAddr_OK(target) => { - if bit_to_bool(target[1]) & not(extension("C")) then { - handle_mem_exception(target, E_Fetch_Addr_Align()); - RETIRE_FAIL; - } else { - set_next_pc(target); - RETIRE_SUCCESS - } - } - } - } else RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/bge.yaml b/arch/inst/I/bge.yaml index 473fba398..614a01512 100644 --- a/arch/inst/I/bge.yaml +++ b/arch/inst/I/bge.yaml @@ -70,37 +70,3 @@ bge: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let taken : bool = match op { - RISCV_BEQ => rs1_val == rs2_val, - RISCV_BNE => rs1_val != rs2_val, - RISCV_BLT => rs1_val <_s rs2_val, - RISCV_BGE => rs1_val >=_s rs2_val, - RISCV_BLTU => rs1_val <_u rs2_val, - RISCV_BGEU => rs1_val >=_u rs2_val - }; - let t : xlenbits = PC + sign_extend(imm); - if taken then { - /* Extensions get the first checks on the prospective target address. */ - match ext_control_check_pc(t) { - Ext_ControlAddr_Error(e) => { - ext_handle_control_check_error(e); - RETIRE_FAIL - }, - Ext_ControlAddr_OK(target) => { - if bit_to_bool(target[1]) & not(extension("C")) then { - handle_mem_exception(target, E_Fetch_Addr_Align()); - RETIRE_FAIL; - } else { - set_next_pc(target); - RETIRE_SUCCESS - } - } - } - } else RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/bgeu.yaml b/arch/inst/I/bgeu.yaml index d8e6b8794..0eb8d060f 100644 --- a/arch/inst/I/bgeu.yaml +++ b/arch/inst/I/bgeu.yaml @@ -70,37 +70,3 @@ bgeu: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let taken : bool = match op { - RISCV_BEQ => rs1_val == rs2_val, - RISCV_BNE => rs1_val != rs2_val, - RISCV_BLT => rs1_val <_s rs2_val, - RISCV_BGE => rs1_val >=_s rs2_val, - RISCV_BLTU => rs1_val <_u rs2_val, - RISCV_BGEU => rs1_val >=_u rs2_val - }; - let t : xlenbits = PC + sign_extend(imm); - if taken then { - /* Extensions get the first checks on the prospective target address. */ - match ext_control_check_pc(t) { - Ext_ControlAddr_Error(e) => { - ext_handle_control_check_error(e); - RETIRE_FAIL - }, - Ext_ControlAddr_OK(target) => { - if bit_to_bool(target[1]) & not(extension("C")) then { - handle_mem_exception(target, E_Fetch_Addr_Align()); - RETIRE_FAIL; - } else { - set_next_pc(target); - RETIRE_SUCCESS - } - } - } - } else RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/blt.yaml b/arch/inst/I/blt.yaml index 5f9231a3e..4f40b831d 100644 --- a/arch/inst/I/blt.yaml +++ b/arch/inst/I/blt.yaml @@ -70,37 +70,3 @@ blt: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let taken : bool = match op { - RISCV_BEQ => rs1_val == rs2_val, - RISCV_BNE => rs1_val != rs2_val, - RISCV_BLT => rs1_val <_s rs2_val, - RISCV_BGE => rs1_val >=_s rs2_val, - RISCV_BLTU => rs1_val <_u rs2_val, - RISCV_BGEU => rs1_val >=_u rs2_val - }; - let t : xlenbits = PC + sign_extend(imm); - if taken then { - /* Extensions get the first checks on the prospective target address. */ - match ext_control_check_pc(t) { - Ext_ControlAddr_Error(e) => { - ext_handle_control_check_error(e); - RETIRE_FAIL - }, - Ext_ControlAddr_OK(target) => { - if bit_to_bool(target[1]) & not(extension("C")) then { - handle_mem_exception(target, E_Fetch_Addr_Align()); - RETIRE_FAIL; - } else { - set_next_pc(target); - RETIRE_SUCCESS - } - } - } - } else RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/bltu.yaml b/arch/inst/I/bltu.yaml index 72fde3ef0..ceed985fa 100644 --- a/arch/inst/I/bltu.yaml +++ b/arch/inst/I/bltu.yaml @@ -70,37 +70,3 @@ bltu: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let taken : bool = match op { - RISCV_BEQ => rs1_val == rs2_val, - RISCV_BNE => rs1_val != rs2_val, - RISCV_BLT => rs1_val <_s rs2_val, - RISCV_BGE => rs1_val >=_s rs2_val, - RISCV_BLTU => rs1_val <_u rs2_val, - RISCV_BGEU => rs1_val >=_u rs2_val - }; - let t : xlenbits = PC + sign_extend(imm); - if taken then { - /* Extensions get the first checks on the prospective target address. */ - match ext_control_check_pc(t) { - Ext_ControlAddr_Error(e) => { - ext_handle_control_check_error(e); - RETIRE_FAIL - }, - Ext_ControlAddr_OK(target) => { - if bit_to_bool(target[1]) & not(extension("C")) then { - handle_mem_exception(target, E_Fetch_Addr_Align()); - RETIRE_FAIL; - } else { - set_next_pc(target); - RETIRE_SUCCESS - } - } - } - } else RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/bne.yaml b/arch/inst/I/bne.yaml index 44a2bd40d..579645344 100644 --- a/arch/inst/I/bne.yaml +++ b/arch/inst/I/bne.yaml @@ -70,37 +70,3 @@ bne: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let taken : bool = match op { - RISCV_BEQ => rs1_val == rs2_val, - RISCV_BNE => rs1_val != rs2_val, - RISCV_BLT => rs1_val <_s rs2_val, - RISCV_BGE => rs1_val >=_s rs2_val, - RISCV_BLTU => rs1_val <_u rs2_val, - RISCV_BGEU => rs1_val >=_u rs2_val - }; - let t : xlenbits = PC + sign_extend(imm); - if taken then { - /* Extensions get the first checks on the prospective target address. */ - match ext_control_check_pc(t) { - Ext_ControlAddr_Error(e) => { - ext_handle_control_check_error(e); - RETIRE_FAIL - }, - Ext_ControlAddr_OK(target) => { - if bit_to_bool(target[1]) & not(extension("C")) then { - handle_mem_exception(target, E_Fetch_Addr_Align()); - RETIRE_FAIL; - } else { - set_next_pc(target); - RETIRE_SUCCESS - } - } - } - } else RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/ebreak.yaml b/arch/inst/I/ebreak.yaml index 33e0be2e6..fe7ae0232 100644 --- a/arch/inst/I/ebreak.yaml +++ b/arch/inst/I/ebreak.yaml @@ -42,10 +42,3 @@ ebreak: - sail(): | - { - handle_mem_exception(PC, E_Breakpoint()); - RETIRE_FAIL - } - - \ No newline at end of file diff --git a/arch/inst/I/ecall.yaml b/arch/inst/I/ecall.yaml index 647e6004e..93c4f1f14 100644 --- a/arch/inst/I/ecall.yaml +++ b/arch/inst/I/ecall.yaml @@ -73,18 +73,3 @@ ecall: - sail(): | - { - let t : sync_exception = - struct { trap = match (cur_privilege) { - User => E_U_EnvCall(), - Supervisor => E_S_EnvCall(), - Machine => E_M_EnvCall() - }, - excinfo = (None() : option(xlenbits)), - ext = None() }; - set_next_pc(exception_handler(cur_privilege, CTL_TRAP(t), PC)); - RETIRE_FAIL - } - - \ No newline at end of file diff --git a/arch/inst/I/fence.yaml b/arch/inst/I/fence.yaml index a070409f7..db74a1e0e 100644 --- a/arch/inst/I/fence.yaml +++ b/arch/inst/I/fence.yaml @@ -238,31 +238,3 @@ fence: - sail(): | - { - // If the FIOM bit in menvcfg/senvcfg is set then the I/O bits can imply R/W. - let fiom = is_fiom_active(); - let pred = effective_fence_set(pred, fiom); - let succ = effective_fence_set(succ, fiom); - - match (pred, succ) { - (_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => __barrier(Barrier_RISCV_rw_rw()), - (_ : bits(2) @ 0b10, _ : bits(2) @ 0b11) => __barrier(Barrier_RISCV_r_rw()), - (_ : bits(2) @ 0b10, _ : bits(2) @ 0b10) => __barrier(Barrier_RISCV_r_r()), - (_ : bits(2) @ 0b11, _ : bits(2) @ 0b01) => __barrier(Barrier_RISCV_rw_w()), - (_ : bits(2) @ 0b01, _ : bits(2) @ 0b01) => __barrier(Barrier_RISCV_w_w()), - (_ : bits(2) @ 0b01, _ : bits(2) @ 0b11) => __barrier(Barrier_RISCV_w_rw()), - (_ : bits(2) @ 0b11, _ : bits(2) @ 0b10) => __barrier(Barrier_RISCV_rw_r()), - (_ : bits(2) @ 0b10, _ : bits(2) @ 0b01) => __barrier(Barrier_RISCV_r_w()), - (_ : bits(2) @ 0b01, _ : bits(2) @ 0b10) => __barrier(Barrier_RISCV_w_r()), - - (_ : bits(4) , _ : bits(2) @ 0b00) => (), - (_ : bits(2) @ 0b00, _ : bits(4) ) => (), - - _ => { print("FIXME: unsupported fence"); - () } - }; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/jal.yaml b/arch/inst/I/jal.yaml index 67c786635..19a28905c 100644 --- a/arch/inst/I/jal.yaml +++ b/arch/inst/I/jal.yaml @@ -56,28 +56,3 @@ jal: - sail(): | - { - let t : xlenbits = PC + sign_extend(imm); - /* Extensions get the first checks on the prospective target address. */ - match ext_control_check_pc(t) { - Ext_ControlAddr_Error(e) => { - ext_handle_control_check_error(e); - RETIRE_FAIL - }, - Ext_ControlAddr_OK(target) => { - /* Perform standard alignment check */ - if bit_to_bool(target[1]) & not(extension("C")) - then { - handle_mem_exception(target, E_Fetch_Addr_Align()); - RETIRE_FAIL - } else { - X(rd) = get_next_pc(); - set_next_pc(target); - RETIRE_SUCCESS - } - } - } - } - - \ No newline at end of file diff --git a/arch/inst/I/jalr.yaml b/arch/inst/I/jalr.yaml index c158b4738..786e3bd2f 100644 --- a/arch/inst/I/jalr.yaml +++ b/arch/inst/I/jalr.yaml @@ -62,33 +62,3 @@ jalr: - sail(): | - { - /* For the sequential model, the memory-model definition doesn't work directly - * if rs1 = rd. We would effectively have to keep a regfile for reads and another for - * writes, and swap on instruction completion. This could perhaps be optimized in - * some manner, but for now, we just keep a reordered definition to improve simulator - * performance. - */ - let t : xlenbits = X(rs1) + sign_extend(imm); - /* Extensions get the first checks on the prospective target address. */ - match ext_control_check_addr(t) { - Ext_ControlAddr_Error(e) => { - ext_handle_control_check_error(e); - RETIRE_FAIL - }, - Ext_ControlAddr_OK(addr) => { - let target = [addr with 0 = bitzero]; /* clear addr[0] */ - if bit_to_bool(target[1]) & not(extension("C")) then { - handle_mem_exception(target, E_Fetch_Addr_Align()); - RETIRE_FAIL - } else { - X(rd) = get_next_pc(); - set_next_pc(target); - RETIRE_SUCCESS - } - } - } - } - - \ No newline at end of file diff --git a/arch/inst/I/lb.yaml b/arch/inst/I/lb.yaml index 7c6fdbebf..6d6c65cde 100644 --- a/arch/inst/I/lb.yaml +++ b/arch/inst/I/lb.yaml @@ -60,32 +60,3 @@ lb: - sail(): | - { - let offset : xlenbits = sign_extend(imm); - /* Get the address, X(rs1) + offset. - Some extensions perform additional checks on address validity. */ - match ext_data_get_addr(rs1, offset, Read(Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => - if check_misaligned(vaddr, width) - then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } - else match translateAddr(vaddr, Read(Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(paddr, _) => - match (width) { - BYTE => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), - HALF => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), - WORD => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), - DOUBLE if sizeof(xlen) >= 64 => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), - _ => report_invalid_width(__FILE__, __LINE__, width, "load") - } - } - } - } - - \ No newline at end of file diff --git a/arch/inst/I/lbu.yaml b/arch/inst/I/lbu.yaml index 97ea975ff..878f399d7 100644 --- a/arch/inst/I/lbu.yaml +++ b/arch/inst/I/lbu.yaml @@ -60,32 +60,3 @@ lbu: - sail(): | - { - let offset : xlenbits = sign_extend(imm); - /* Get the address, X(rs1) + offset. - Some extensions perform additional checks on address validity. */ - match ext_data_get_addr(rs1, offset, Read(Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => - if check_misaligned(vaddr, width) - then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } - else match translateAddr(vaddr, Read(Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(paddr, _) => - match (width) { - BYTE => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), - HALF => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), - WORD => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), - DOUBLE if sizeof(xlen) >= 64 => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), - _ => report_invalid_width(__FILE__, __LINE__, width, "load") - } - } - } - } - - \ No newline at end of file diff --git a/arch/inst/I/ld.yaml b/arch/inst/I/ld.yaml index da4e60602..da51a6f9b 100644 --- a/arch/inst/I/ld.yaml +++ b/arch/inst/I/ld.yaml @@ -60,32 +60,3 @@ ld: - sail(): | - { - let offset : xlenbits = sign_extend(imm); - /* Get the address, X(rs1) + offset. - Some extensions perform additional checks on address validity. */ - match ext_data_get_addr(rs1, offset, Read(Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => - if check_misaligned(vaddr, width) - then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } - else match translateAddr(vaddr, Read(Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(paddr, _) => - match (width) { - BYTE => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), - HALF => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), - WORD => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), - DOUBLE if sizeof(xlen) >= 64 => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), - _ => report_invalid_width(__FILE__, __LINE__, width, "load") - } - } - } - } - - \ No newline at end of file diff --git a/arch/inst/I/lh.yaml b/arch/inst/I/lh.yaml index dc11630e7..a67753f2f 100644 --- a/arch/inst/I/lh.yaml +++ b/arch/inst/I/lh.yaml @@ -60,32 +60,3 @@ lh: - sail(): | - { - let offset : xlenbits = sign_extend(imm); - /* Get the address, X(rs1) + offset. - Some extensions perform additional checks on address validity. */ - match ext_data_get_addr(rs1, offset, Read(Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => - if check_misaligned(vaddr, width) - then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } - else match translateAddr(vaddr, Read(Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(paddr, _) => - match (width) { - BYTE => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), - HALF => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), - WORD => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), - DOUBLE if sizeof(xlen) >= 64 => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), - _ => report_invalid_width(__FILE__, __LINE__, width, "load") - } - } - } - } - - \ No newline at end of file diff --git a/arch/inst/I/lhu.yaml b/arch/inst/I/lhu.yaml index c67a2a5ce..0ffdd8be0 100644 --- a/arch/inst/I/lhu.yaml +++ b/arch/inst/I/lhu.yaml @@ -60,32 +60,3 @@ lhu: - sail(): | - { - let offset : xlenbits = sign_extend(imm); - /* Get the address, X(rs1) + offset. - Some extensions perform additional checks on address validity. */ - match ext_data_get_addr(rs1, offset, Read(Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => - if check_misaligned(vaddr, width) - then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } - else match translateAddr(vaddr, Read(Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(paddr, _) => - match (width) { - BYTE => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), - HALF => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), - WORD => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), - DOUBLE if sizeof(xlen) >= 64 => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), - _ => report_invalid_width(__FILE__, __LINE__, width, "load") - } - } - } - } - - \ No newline at end of file diff --git a/arch/inst/I/lui.yaml b/arch/inst/I/lui.yaml index c21bd9038..3d188e12c 100644 --- a/arch/inst/I/lui.yaml +++ b/arch/inst/I/lui.yaml @@ -37,15 +37,3 @@ lui: - sail(): | - { - let off : xlenbits = sign_extend(imm @ 0x000); - let ret : xlenbits = match op { - RISCV_LUI => off, - RISCV_AUIPC => get_arch_pc() + off - }; - X(rd) = ret; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/lw.yaml b/arch/inst/I/lw.yaml index 294a234db..adb7da679 100644 --- a/arch/inst/I/lw.yaml +++ b/arch/inst/I/lw.yaml @@ -60,32 +60,3 @@ lw: - sail(): | - { - let offset : xlenbits = sign_extend(imm); - /* Get the address, X(rs1) + offset. - Some extensions perform additional checks on address validity. */ - match ext_data_get_addr(rs1, offset, Read(Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => - if check_misaligned(vaddr, width) - then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } - else match translateAddr(vaddr, Read(Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(paddr, _) => - match (width) { - BYTE => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), - HALF => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), - WORD => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), - DOUBLE if sizeof(xlen) >= 64 => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), - _ => report_invalid_width(__FILE__, __LINE__, width, "load") - } - } - } - } - - \ No newline at end of file diff --git a/arch/inst/I/lwu.yaml b/arch/inst/I/lwu.yaml index 14e622f1e..7655d1083 100644 --- a/arch/inst/I/lwu.yaml +++ b/arch/inst/I/lwu.yaml @@ -61,32 +61,3 @@ lwu: - sail(): | - { - let offset : xlenbits = sign_extend(imm); - /* Get the address, X(rs1) + offset. - Some extensions perform additional checks on address validity. */ - match ext_data_get_addr(rs1, offset, Read(Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => - if check_misaligned(vaddr, width) - then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } - else match translateAddr(vaddr, Read(Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(paddr, _) => - match (width) { - BYTE => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), - HALF => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), - WORD => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), - DOUBLE if sizeof(xlen) >= 64 => - process_load(rd, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), - _ => report_invalid_width(__FILE__, __LINE__, width, "load") - } - } - } - } - - \ No newline at end of file diff --git a/arch/inst/I/mret.yaml b/arch/inst/I/mret.yaml index 9f2244f12..a463001a5 100644 --- a/arch/inst/I/mret.yaml +++ b/arch/inst/I/mret.yaml @@ -44,16 +44,3 @@ mret: - sail(): | - { - if cur_privilege != Machine - then { handle_illegal(); RETIRE_FAIL } - else if not(ext_check_xret_priv (Machine)) - then { ext_fail_xret_priv(); RETIRE_FAIL } - else { - set_next_pc(exception_handler(cur_privilege, CTL_MRET(), PC)); - RETIRE_SUCCESS - } - } - - \ No newline at end of file diff --git a/arch/inst/I/or.yaml b/arch/inst/I/or.yaml index 445c3de3d..7bdabd251 100644 --- a/arch/inst/I/or.yaml +++ b/arch/inst/I/or.yaml @@ -53,30 +53,3 @@ or: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let result : xlenbits = match op { - RISCV_ADD => rs1_val + rs2_val, - RISCV_SLT => zero_extend(bool_to_bits(rs1_val <_s rs2_val)), - RISCV_SLTU => zero_extend(bool_to_bits(rs1_val <_u rs2_val)), - RISCV_AND => rs1_val & rs2_val, - RISCV_OR => rs1_val | rs2_val, - RISCV_XOR => rs1_val ^ rs2_val, - RISCV_SLL => if sizeof(xlen) == 32 - then rs1_val << (rs2_val[4..0]) - else rs1_val << (rs2_val[5..0]), - RISCV_SRL => if sizeof(xlen) == 32 - then rs1_val >> (rs2_val[4..0]) - else rs1_val >> (rs2_val[5..0]), - RISCV_SUB => rs1_val - rs2_val, - RISCV_SRA => if sizeof(xlen) == 32 - then shift_right_arith32(rs1_val, rs2_val[4..0]) - else shift_right_arith64(rs1_val, rs2_val[5..0]) - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/ori.yaml b/arch/inst/I/ori.yaml index 47460748c..caaa99ef4 100644 --- a/arch/inst/I/ori.yaml +++ b/arch/inst/I/ori.yaml @@ -68,20 +68,3 @@ ori: - sail(): | - { - let rs1_val = X(rs1); - let immext : xlenbits = sign_extend(imm); - let result : xlenbits = match op { - RISCV_ADDI => rs1_val + immext, - RISCV_SLTI => zero_extend(bool_to_bits(rs1_val <_s immext)), - RISCV_SLTIU => zero_extend(bool_to_bits(rs1_val <_u immext)), - RISCV_ANDI => rs1_val & immext, - RISCV_ORI => rs1_val | immext, - RISCV_XORI => rs1_val ^ immext - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/sb.yaml b/arch/inst/I/sb.yaml index 7afd14682..96f135c98 100644 --- a/arch/inst/I/sb.yaml +++ b/arch/inst/I/sb.yaml @@ -74,47 +74,3 @@ sb: - sail(): | - { - let offset : xlenbits = sign_extend(imm); - /* Get the address, X(rs1) + offset. - Some extensions perform additional checks on address validity. */ - match ext_data_get_addr(rs1, offset, Write(Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => - if check_misaligned(vaddr, width) - then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL } - else match translateAddr(vaddr, Write(Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(paddr, _) => { - let eares : MemoryOpResult(unit) = match width { - BYTE => mem_write_ea(paddr, 1, aq, rl, false), - HALF => mem_write_ea(paddr, 2, aq, rl, false), - WORD => mem_write_ea(paddr, 4, aq, rl, false), - DOUBLE => mem_write_ea(paddr, 8, aq, rl, false) - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - let rs2_val = X(rs2); - let res : MemoryOpResult(bool) = match (width) { - BYTE => mem_write_value(paddr, 1, rs2_val[7..0], aq, rl, false), - HALF => mem_write_value(paddr, 2, rs2_val[15..0], aq, rl, false), - WORD => mem_write_value(paddr, 4, rs2_val[31..0], aq, rl, false), - DOUBLE if sizeof(xlen) >= 64 - => mem_write_value(paddr, 8, rs2_val, aq, rl, false), - _ => report_invalid_width(__FILE__, __LINE__, width, "store"), - }; - match (res) { - MemValue(true) => RETIRE_SUCCESS, - MemValue(false) => internal_error(__FILE__, __LINE__, "store got false from mem_write_value"), - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } - } - } - } - } - } - } - } - - \ No newline at end of file diff --git a/arch/inst/I/sd.yaml b/arch/inst/I/sd.yaml index 24a7af2bc..a1416d8e3 100644 --- a/arch/inst/I/sd.yaml +++ b/arch/inst/I/sd.yaml @@ -76,47 +76,3 @@ sd: - sail(): | - { - let offset : xlenbits = sign_extend(imm); - /* Get the address, X(rs1) + offset. - Some extensions perform additional checks on address validity. */ - match ext_data_get_addr(rs1, offset, Write(Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => - if check_misaligned(vaddr, width) - then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL } - else match translateAddr(vaddr, Write(Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(paddr, _) => { - let eares : MemoryOpResult(unit) = match width { - BYTE => mem_write_ea(paddr, 1, aq, rl, false), - HALF => mem_write_ea(paddr, 2, aq, rl, false), - WORD => mem_write_ea(paddr, 4, aq, rl, false), - DOUBLE => mem_write_ea(paddr, 8, aq, rl, false) - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - let rs2_val = X(rs2); - let res : MemoryOpResult(bool) = match (width) { - BYTE => mem_write_value(paddr, 1, rs2_val[7..0], aq, rl, false), - HALF => mem_write_value(paddr, 2, rs2_val[15..0], aq, rl, false), - WORD => mem_write_value(paddr, 4, rs2_val[31..0], aq, rl, false), - DOUBLE if sizeof(xlen) >= 64 - => mem_write_value(paddr, 8, rs2_val, aq, rl, false), - _ => report_invalid_width(__FILE__, __LINE__, width, "store"), - }; - match (res) { - MemValue(true) => RETIRE_SUCCESS, - MemValue(false) => internal_error(__FILE__, __LINE__, "store got false from mem_write_value"), - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } - } - } - } - } - } - } - } - - \ No newline at end of file diff --git a/arch/inst/I/sh.yaml b/arch/inst/I/sh.yaml index c6dde3fa9..ede6bac64 100644 --- a/arch/inst/I/sh.yaml +++ b/arch/inst/I/sh.yaml @@ -74,47 +74,3 @@ sh: - sail(): | - { - let offset : xlenbits = sign_extend(imm); - /* Get the address, X(rs1) + offset. - Some extensions perform additional checks on address validity. */ - match ext_data_get_addr(rs1, offset, Write(Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => - if check_misaligned(vaddr, width) - then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL } - else match translateAddr(vaddr, Write(Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(paddr, _) => { - let eares : MemoryOpResult(unit) = match width { - BYTE => mem_write_ea(paddr, 1, aq, rl, false), - HALF => mem_write_ea(paddr, 2, aq, rl, false), - WORD => mem_write_ea(paddr, 4, aq, rl, false), - DOUBLE => mem_write_ea(paddr, 8, aq, rl, false) - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - let rs2_val = X(rs2); - let res : MemoryOpResult(bool) = match (width) { - BYTE => mem_write_value(paddr, 1, rs2_val[7..0], aq, rl, false), - HALF => mem_write_value(paddr, 2, rs2_val[15..0], aq, rl, false), - WORD => mem_write_value(paddr, 4, rs2_val[31..0], aq, rl, false), - DOUBLE if sizeof(xlen) >= 64 - => mem_write_value(paddr, 8, rs2_val, aq, rl, false), - _ => report_invalid_width(__FILE__, __LINE__, width, "store"), - }; - match (res) { - MemValue(true) => RETIRE_SUCCESS, - MemValue(false) => internal_error(__FILE__, __LINE__, "store got false from mem_write_value"), - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } - } - } - } - } - } - } - } - - \ No newline at end of file diff --git a/arch/inst/I/sll.yaml b/arch/inst/I/sll.yaml index c9845a265..3f48f4bc5 100644 --- a/arch/inst/I/sll.yaml +++ b/arch/inst/I/sll.yaml @@ -59,30 +59,3 @@ sll: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let result : xlenbits = match op { - RISCV_ADD => rs1_val + rs2_val, - RISCV_SLT => zero_extend(bool_to_bits(rs1_val <_s rs2_val)), - RISCV_SLTU => zero_extend(bool_to_bits(rs1_val <_u rs2_val)), - RISCV_AND => rs1_val & rs2_val, - RISCV_OR => rs1_val | rs2_val, - RISCV_XOR => rs1_val ^ rs2_val, - RISCV_SLL => if sizeof(xlen) == 32 - then rs1_val << (rs2_val[4..0]) - else rs1_val << (rs2_val[5..0]), - RISCV_SRL => if sizeof(xlen) == 32 - then rs1_val >> (rs2_val[4..0]) - else rs1_val >> (rs2_val[5..0]), - RISCV_SUB => rs1_val - rs2_val, - RISCV_SRA => if sizeof(xlen) == 32 - then shift_right_arith32(rs1_val, rs2_val[4..0]) - else shift_right_arith64(rs1_val, rs2_val[5..0]) - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/slli.yaml b/arch/inst/I/slli.yaml index edb37ecc4..3a378fdef 100644 --- a/arch/inst/I/slli.yaml +++ b/arch/inst/I/slli.yaml @@ -58,23 +58,3 @@ slli: - sail(): | - { - let rs1_val = X(rs1); - /* the decoder guard should ensure that shamt[5] = 0 for RV32 */ - let result : xlenbits = match op { - RISCV_SLLI => if sizeof(xlen) == 32 - then rs1_val << shamt[4..0] - else rs1_val << shamt, - RISCV_SRLI => if sizeof(xlen) == 32 - then rs1_val >> shamt[4..0] - else rs1_val >> shamt, - RISCV_SRAI => if sizeof(xlen) == 32 - then shift_right_arith32(rs1_val, shamt[4..0]) - else shift_right_arith64(rs1_val, shamt) - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/slliw.yaml b/arch/inst/I/slliw.yaml index e31d4805f..5e27f42ef 100644 --- a/arch/inst/I/slliw.yaml +++ b/arch/inst/I/slliw.yaml @@ -42,16 +42,3 @@ slliw: - sail(): | - { - let rs1_val = (X(rs1))[31..0]; - let result : bits(32) = match op { - RISCV_SLLIW => rs1_val << shamt, - RISCV_SRLIW => rs1_val >> shamt, - RISCV_SRAIW => shift_right_arith32(rs1_val, shamt) - }; - X(rd) = sign_extend(result); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/sllw.yaml b/arch/inst/I/sllw.yaml index b5300b2a7..e526d6b0f 100644 --- a/arch/inst/I/sllw.yaml +++ b/arch/inst/I/sllw.yaml @@ -44,19 +44,3 @@ sllw: - sail(): | - { - let rs1_val = (X(rs1))[31..0]; - let rs2_val = (X(rs2))[31..0]; - let result : bits(32) = match op { - RISCV_ADDW => rs1_val + rs2_val, - RISCV_SUBW => rs1_val - rs2_val, - RISCV_SLLW => rs1_val << (rs2_val[4..0]), - RISCV_SRLW => rs1_val >> (rs2_val[4..0]), - RISCV_SRAW => shift_right_arith32(rs1_val, rs2_val[4..0]) - }; - X(rd) = sign_extend(result); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/slt.yaml b/arch/inst/I/slt.yaml index e09368f4d..a991006d9 100644 --- a/arch/inst/I/slt.yaml +++ b/arch/inst/I/slt.yaml @@ -59,30 +59,3 @@ slt: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let result : xlenbits = match op { - RISCV_ADD => rs1_val + rs2_val, - RISCV_SLT => zero_extend(bool_to_bits(rs1_val <_s rs2_val)), - RISCV_SLTU => zero_extend(bool_to_bits(rs1_val <_u rs2_val)), - RISCV_AND => rs1_val & rs2_val, - RISCV_OR => rs1_val | rs2_val, - RISCV_XOR => rs1_val ^ rs2_val, - RISCV_SLL => if sizeof(xlen) == 32 - then rs1_val << (rs2_val[4..0]) - else rs1_val << (rs2_val[5..0]), - RISCV_SRL => if sizeof(xlen) == 32 - then rs1_val >> (rs2_val[4..0]) - else rs1_val >> (rs2_val[5..0]), - RISCV_SUB => rs1_val - rs2_val, - RISCV_SRA => if sizeof(xlen) == 32 - then shift_right_arith32(rs1_val, rs2_val[4..0]) - else shift_right_arith64(rs1_val, rs2_val[5..0]) - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/slti.yaml b/arch/inst/I/slti.yaml index 69d6b2c3b..29d9bed7c 100644 --- a/arch/inst/I/slti.yaml +++ b/arch/inst/I/slti.yaml @@ -46,20 +46,3 @@ slti: - sail(): | - { - let rs1_val = X(rs1); - let immext : xlenbits = sign_extend(imm); - let result : xlenbits = match op { - RISCV_ADDI => rs1_val + immext, - RISCV_SLTI => zero_extend(bool_to_bits(rs1_val <_s immext)), - RISCV_SLTIU => zero_extend(bool_to_bits(rs1_val <_u immext)), - RISCV_ANDI => rs1_val & immext, - RISCV_ORI => rs1_val | immext, - RISCV_XORI => rs1_val ^ immext - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/sltiu.yaml b/arch/inst/I/sltiu.yaml index 3ad4165c5..6a7cc4b4a 100644 --- a/arch/inst/I/sltiu.yaml +++ b/arch/inst/I/sltiu.yaml @@ -50,20 +50,3 @@ sltiu: - sail(): | - { - let rs1_val = X(rs1); - let immext : xlenbits = sign_extend(imm); - let result : xlenbits = match op { - RISCV_ADDI => rs1_val + immext, - RISCV_SLTI => zero_extend(bool_to_bits(rs1_val <_s immext)), - RISCV_SLTIU => zero_extend(bool_to_bits(rs1_val <_u immext)), - RISCV_ANDI => rs1_val & immext, - RISCV_ORI => rs1_val | immext, - RISCV_XORI => rs1_val ^ immext - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/sltu.yaml b/arch/inst/I/sltu.yaml index ea3e4294d..eff1b162e 100644 --- a/arch/inst/I/sltu.yaml +++ b/arch/inst/I/sltu.yaml @@ -56,30 +56,3 @@ sltu: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let result : xlenbits = match op { - RISCV_ADD => rs1_val + rs2_val, - RISCV_SLT => zero_extend(bool_to_bits(rs1_val <_s rs2_val)), - RISCV_SLTU => zero_extend(bool_to_bits(rs1_val <_u rs2_val)), - RISCV_AND => rs1_val & rs2_val, - RISCV_OR => rs1_val | rs2_val, - RISCV_XOR => rs1_val ^ rs2_val, - RISCV_SLL => if sizeof(xlen) == 32 - then rs1_val << (rs2_val[4..0]) - else rs1_val << (rs2_val[5..0]), - RISCV_SRL => if sizeof(xlen) == 32 - then rs1_val >> (rs2_val[4..0]) - else rs1_val >> (rs2_val[5..0]), - RISCV_SUB => rs1_val - rs2_val, - RISCV_SRA => if sizeof(xlen) == 32 - then shift_right_arith32(rs1_val, rs2_val[4..0]) - else shift_right_arith64(rs1_val, rs2_val[5..0]) - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/sra.yaml b/arch/inst/I/sra.yaml index 40b942aba..b7a8b3efb 100644 --- a/arch/inst/I/sra.yaml +++ b/arch/inst/I/sra.yaml @@ -59,30 +59,3 @@ sra: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let result : xlenbits = match op { - RISCV_ADD => rs1_val + rs2_val, - RISCV_SLT => zero_extend(bool_to_bits(rs1_val <_s rs2_val)), - RISCV_SLTU => zero_extend(bool_to_bits(rs1_val <_u rs2_val)), - RISCV_AND => rs1_val & rs2_val, - RISCV_OR => rs1_val | rs2_val, - RISCV_XOR => rs1_val ^ rs2_val, - RISCV_SLL => if sizeof(xlen) == 32 - then rs1_val << (rs2_val[4..0]) - else rs1_val << (rs2_val[5..0]), - RISCV_SRL => if sizeof(xlen) == 32 - then rs1_val >> (rs2_val[4..0]) - else rs1_val >> (rs2_val[5..0]), - RISCV_SUB => rs1_val - rs2_val, - RISCV_SRA => if sizeof(xlen) == 32 - then shift_right_arith32(rs1_val, rs2_val[4..0]) - else shift_right_arith64(rs1_val, rs2_val[5..0]) - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/srai.yaml b/arch/inst/I/srai.yaml index 326c5fb54..81333fcf7 100644 --- a/arch/inst/I/srai.yaml +++ b/arch/inst/I/srai.yaml @@ -60,23 +60,3 @@ srai: - sail(): | - { - let rs1_val = X(rs1); - /* the decoder guard should ensure that shamt[5] = 0 for RV32 */ - let result : xlenbits = match op { - RISCV_SLLI => if sizeof(xlen) == 32 - then rs1_val << shamt[4..0] - else rs1_val << shamt, - RISCV_SRLI => if sizeof(xlen) == 32 - then rs1_val >> shamt[4..0] - else rs1_val >> shamt, - RISCV_SRAI => if sizeof(xlen) == 32 - then shift_right_arith32(rs1_val, shamt[4..0]) - else shift_right_arith64(rs1_val, shamt) - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/sraiw.yaml b/arch/inst/I/sraiw.yaml index f57627ec4..490d9a6ab 100644 --- a/arch/inst/I/sraiw.yaml +++ b/arch/inst/I/sraiw.yaml @@ -45,16 +45,3 @@ sraiw: - sail(): | - { - let rs1_val = (X(rs1))[31..0]; - let result : bits(32) = match op { - RISCV_SLLIW => rs1_val << shamt, - RISCV_SRLIW => rs1_val >> shamt, - RISCV_SRAIW => shift_right_arith32(rs1_val, shamt) - }; - X(rd) = sign_extend(result); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/sraw.yaml b/arch/inst/I/sraw.yaml index 37be00d6a..81ed8917b 100644 --- a/arch/inst/I/sraw.yaml +++ b/arch/inst/I/sraw.yaml @@ -47,19 +47,3 @@ sraw: - sail(): | - { - let rs1_val = (X(rs1))[31..0]; - let rs2_val = (X(rs2))[31..0]; - let result : bits(32) = match op { - RISCV_ADDW => rs1_val + rs2_val, - RISCV_SUBW => rs1_val - rs2_val, - RISCV_SLLW => rs1_val << (rs2_val[4..0]), - RISCV_SRLW => rs1_val >> (rs2_val[4..0]), - RISCV_SRAW => shift_right_arith32(rs1_val, rs2_val[4..0]) - }; - X(rd) = sign_extend(result); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/srl.yaml b/arch/inst/I/srl.yaml index ce2ba434d..f83eb90a8 100644 --- a/arch/inst/I/srl.yaml +++ b/arch/inst/I/srl.yaml @@ -59,30 +59,3 @@ srl: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let result : xlenbits = match op { - RISCV_ADD => rs1_val + rs2_val, - RISCV_SLT => zero_extend(bool_to_bits(rs1_val <_s rs2_val)), - RISCV_SLTU => zero_extend(bool_to_bits(rs1_val <_u rs2_val)), - RISCV_AND => rs1_val & rs2_val, - RISCV_OR => rs1_val | rs2_val, - RISCV_XOR => rs1_val ^ rs2_val, - RISCV_SLL => if sizeof(xlen) == 32 - then rs1_val << (rs2_val[4..0]) - else rs1_val << (rs2_val[5..0]), - RISCV_SRL => if sizeof(xlen) == 32 - then rs1_val >> (rs2_val[4..0]) - else rs1_val >> (rs2_val[5..0]), - RISCV_SUB => rs1_val - rs2_val, - RISCV_SRA => if sizeof(xlen) == 32 - then shift_right_arith32(rs1_val, rs2_val[4..0]) - else shift_right_arith64(rs1_val, rs2_val[5..0]) - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/srli.yaml b/arch/inst/I/srli.yaml index 286580a84..692859ed2 100644 --- a/arch/inst/I/srli.yaml +++ b/arch/inst/I/srli.yaml @@ -57,23 +57,3 @@ srli: - sail(): | - { - let rs1_val = X(rs1); - /* the decoder guard should ensure that shamt[5] = 0 for RV32 */ - let result : xlenbits = match op { - RISCV_SLLI => if sizeof(xlen) == 32 - then rs1_val << shamt[4..0] - else rs1_val << shamt, - RISCV_SRLI => if sizeof(xlen) == 32 - then rs1_val >> shamt[4..0] - else rs1_val >> shamt, - RISCV_SRAI => if sizeof(xlen) == 32 - then shift_right_arith32(rs1_val, shamt[4..0]) - else shift_right_arith64(rs1_val, shamt) - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/srliw.yaml b/arch/inst/I/srliw.yaml index 4dacfb1a5..cc02beafe 100644 --- a/arch/inst/I/srliw.yaml +++ b/arch/inst/I/srliw.yaml @@ -44,16 +44,3 @@ srliw: - sail(): | - { - let rs1_val = (X(rs1))[31..0]; - let result : bits(32) = match op { - RISCV_SLLIW => rs1_val << shamt, - RISCV_SRLIW => rs1_val >> shamt, - RISCV_SRAIW => shift_right_arith32(rs1_val, shamt) - }; - X(rd) = sign_extend(result); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/srlw.yaml b/arch/inst/I/srlw.yaml index 43967f0eb..2db8e984a 100644 --- a/arch/inst/I/srlw.yaml +++ b/arch/inst/I/srlw.yaml @@ -44,19 +44,3 @@ srlw: - sail(): | - { - let rs1_val = (X(rs1))[31..0]; - let rs2_val = (X(rs2))[31..0]; - let result : bits(32) = match op { - RISCV_ADDW => rs1_val + rs2_val, - RISCV_SUBW => rs1_val - rs2_val, - RISCV_SLLW => rs1_val << (rs2_val[4..0]), - RISCV_SRLW => rs1_val >> (rs2_val[4..0]), - RISCV_SRAW => shift_right_arith32(rs1_val, rs2_val[4..0]) - }; - X(rd) = sign_extend(result); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/sub.yaml b/arch/inst/I/sub.yaml index 0677ab229..ae5921a27 100644 --- a/arch/inst/I/sub.yaml +++ b/arch/inst/I/sub.yaml @@ -56,30 +56,3 @@ sub: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let result : xlenbits = match op { - RISCV_ADD => rs1_val + rs2_val, - RISCV_SLT => zero_extend(bool_to_bits(rs1_val <_s rs2_val)), - RISCV_SLTU => zero_extend(bool_to_bits(rs1_val <_u rs2_val)), - RISCV_AND => rs1_val & rs2_val, - RISCV_OR => rs1_val | rs2_val, - RISCV_XOR => rs1_val ^ rs2_val, - RISCV_SLL => if sizeof(xlen) == 32 - then rs1_val << (rs2_val[4..0]) - else rs1_val << (rs2_val[5..0]), - RISCV_SRL => if sizeof(xlen) == 32 - then rs1_val >> (rs2_val[4..0]) - else rs1_val >> (rs2_val[5..0]), - RISCV_SUB => rs1_val - rs2_val, - RISCV_SRA => if sizeof(xlen) == 32 - then shift_right_arith32(rs1_val, rs2_val[4..0]) - else shift_right_arith64(rs1_val, rs2_val[5..0]) - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/subw.yaml b/arch/inst/I/subw.yaml index 192eae682..54e0145d7 100644 --- a/arch/inst/I/subw.yaml +++ b/arch/inst/I/subw.yaml @@ -46,19 +46,3 @@ subw: - sail(): | - { - let rs1_val = (X(rs1))[31..0]; - let rs2_val = (X(rs2))[31..0]; - let result : bits(32) = match op { - RISCV_ADDW => rs1_val + rs2_val, - RISCV_SUBW => rs1_val - rs2_val, - RISCV_SLLW => rs1_val << (rs2_val[4..0]), - RISCV_SRLW => rs1_val >> (rs2_val[4..0]), - RISCV_SRAW => shift_right_arith32(rs1_val, rs2_val[4..0]) - }; - X(rd) = sign_extend(result); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/sw.yaml b/arch/inst/I/sw.yaml index f6cc7e6a7..d94501a82 100644 --- a/arch/inst/I/sw.yaml +++ b/arch/inst/I/sw.yaml @@ -74,47 +74,3 @@ sw: - sail(): | - { - let offset : xlenbits = sign_extend(imm); - /* Get the address, X(rs1) + offset. - Some extensions perform additional checks on address validity. */ - match ext_data_get_addr(rs1, offset, Write(Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => - if check_misaligned(vaddr, width) - then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL } - else match translateAddr(vaddr, Write(Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(paddr, _) => { - let eares : MemoryOpResult(unit) = match width { - BYTE => mem_write_ea(paddr, 1, aq, rl, false), - HALF => mem_write_ea(paddr, 2, aq, rl, false), - WORD => mem_write_ea(paddr, 4, aq, rl, false), - DOUBLE => mem_write_ea(paddr, 8, aq, rl, false) - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - let rs2_val = X(rs2); - let res : MemoryOpResult(bool) = match (width) { - BYTE => mem_write_value(paddr, 1, rs2_val[7..0], aq, rl, false), - HALF => mem_write_value(paddr, 2, rs2_val[15..0], aq, rl, false), - WORD => mem_write_value(paddr, 4, rs2_val[31..0], aq, rl, false), - DOUBLE if sizeof(xlen) >= 64 - => mem_write_value(paddr, 8, rs2_val, aq, rl, false), - _ => report_invalid_width(__FILE__, __LINE__, width, "store"), - }; - match (res) { - MemValue(true) => RETIRE_SUCCESS, - MemValue(false) => internal_error(__FILE__, __LINE__, "store got false from mem_write_value"), - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } - } - } - } - } - } - } - } - - \ No newline at end of file diff --git a/arch/inst/I/wfi.yaml b/arch/inst/I/wfi.yaml index a19e368f5..f337fbeb8 100644 --- a/arch/inst/I/wfi.yaml +++ b/arch/inst/I/wfi.yaml @@ -123,13 +123,3 @@ wfi: - sail(): | - match cur_privilege { - Machine => { platform_wfi(); RETIRE_SUCCESS }, - Supervisor => if mstatus.TW() == 0b1 - then { handle_illegal(); RETIRE_FAIL } - else { platform_wfi(); RETIRE_SUCCESS }, - User => { handle_illegal(); RETIRE_FAIL } - } - - \ No newline at end of file diff --git a/arch/inst/I/xor.yaml b/arch/inst/I/xor.yaml index 6fc52bcf0..22f83318c 100644 --- a/arch/inst/I/xor.yaml +++ b/arch/inst/I/xor.yaml @@ -53,30 +53,3 @@ xor: - sail(): | - { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let result : xlenbits = match op { - RISCV_ADD => rs1_val + rs2_val, - RISCV_SLT => zero_extend(bool_to_bits(rs1_val <_s rs2_val)), - RISCV_SLTU => zero_extend(bool_to_bits(rs1_val <_u rs2_val)), - RISCV_AND => rs1_val & rs2_val, - RISCV_OR => rs1_val | rs2_val, - RISCV_XOR => rs1_val ^ rs2_val, - RISCV_SLL => if sizeof(xlen) == 32 - then rs1_val << (rs2_val[4..0]) - else rs1_val << (rs2_val[5..0]), - RISCV_SRL => if sizeof(xlen) == 32 - then rs1_val >> (rs2_val[4..0]) - else rs1_val >> (rs2_val[5..0]), - RISCV_SUB => rs1_val - rs2_val, - RISCV_SRA => if sizeof(xlen) == 32 - then shift_right_arith32(rs1_val, rs2_val[4..0]) - else shift_right_arith64(rs1_val, rs2_val[5..0]) - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/I/xori.yaml b/arch/inst/I/xori.yaml index 768158fbd..655bea5b8 100644 --- a/arch/inst/I/xori.yaml +++ b/arch/inst/I/xori.yaml @@ -43,20 +43,3 @@ xori: - sail(): | - { - let rs1_val = X(rs1); - let immext : xlenbits = sign_extend(imm); - let result : xlenbits = match op { - RISCV_ADDI => rs1_val + immext, - RISCV_SLTI => zero_extend(bool_to_bits(rs1_val <_s immext)), - RISCV_SLTIU => zero_extend(bool_to_bits(rs1_val <_u immext)), - RISCV_ANDI => rs1_val & immext, - RISCV_ORI => rs1_val | immext, - RISCV_XORI => rs1_val ^ immext - }; - X(rd) = result; - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/M/div.yaml b/arch/inst/M/div.yaml index 4e28d2c6a..c1e08f4f6 100644 --- a/arch/inst/M/div.yaml +++ b/arch/inst/M/div.yaml @@ -70,22 +70,3 @@ div: - sail(): | - { - if extension("M") then { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val); - let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val); - let q : int = if rs2_int == 0 then -1 else quot_round_zero(rs1_int, rs2_int); - /* check for signed overflow */ - let q': int = if s & q > xlen_max_signed then xlen_min_signed else q; - X(rd) = to_bits(sizeof(xlen), q'); - RETIRE_SUCCESS - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/M/divu.yaml b/arch/inst/M/divu.yaml index 7fe7b798b..7cdb7718b 100644 --- a/arch/inst/M/divu.yaml +++ b/arch/inst/M/divu.yaml @@ -62,22 +62,3 @@ divu: - sail(): | - { - if extension("M") then { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val); - let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val); - let q : int = if rs2_int == 0 then -1 else quot_round_zero(rs1_int, rs2_int); - /* check for signed overflow */ - let q': int = if s & q > xlen_max_signed then xlen_min_signed else q; - X(rd) = to_bits(sizeof(xlen), q'); - RETIRE_SUCCESS - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/M/divuw.yaml b/arch/inst/M/divuw.yaml index 7925737a3..df01adba3 100644 --- a/arch/inst/M/divuw.yaml +++ b/arch/inst/M/divuw.yaml @@ -68,22 +68,3 @@ divuw: - sail(): | - { - if extension("M") then { - let rs1_val = X(rs1)[31..0]; - let rs2_val = X(rs2)[31..0]; - let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val); - let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val); - let q : int = if rs2_int == 0 then -1 else quot_round_zero(rs1_int, rs2_int); - /* check for signed overflow */ - let q': int = if s & q > (2 ^ 31 - 1) then (0 - 2^31) else q; - X(rd) = sign_extend(to_bits(32, q')); - RETIRE_SUCCESS - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/M/divw.yaml b/arch/inst/M/divw.yaml index 66e3a0145..62b6636d8 100644 --- a/arch/inst/M/divw.yaml +++ b/arch/inst/M/divw.yaml @@ -77,22 +77,3 @@ divw: - sail(): | - { - if extension("M") then { - let rs1_val = X(rs1)[31..0]; - let rs2_val = X(rs2)[31..0]; - let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val); - let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val); - let q : int = if rs2_int == 0 then -1 else quot_round_zero(rs1_int, rs2_int); - /* check for signed overflow */ - let q': int = if s & q > (2 ^ 31 - 1) then (0 - 2^31) else q; - X(rd) = sign_extend(to_bits(32, q')); - RETIRE_SUCCESS - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/M/mul.yaml b/arch/inst/M/mul.yaml index 30be65631..007d1aa1d 100644 --- a/arch/inst/M/mul.yaml +++ b/arch/inst/M/mul.yaml @@ -66,23 +66,3 @@ mul: - sail(): | - { - if extension("M") | haveZmmul() then { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let rs1_int : int = if signed1 then signed(rs1_val) else unsigned(rs1_val); - let rs2_int : int = if signed2 then signed(rs2_val) else unsigned(rs2_val); - let result_wide = to_bits(2 * sizeof(xlen), rs1_int * rs2_int); - let result = if high - then result_wide[(2 * sizeof(xlen) - 1) .. sizeof(xlen)] - else result_wide[(sizeof(xlen) - 1) .. 0]; - X(rd) = result; - RETIRE_SUCCESS - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/M/mulh.yaml b/arch/inst/M/mulh.yaml index cd557a4f8..afca2345a 100644 --- a/arch/inst/M/mulh.yaml +++ b/arch/inst/M/mulh.yaml @@ -71,23 +71,3 @@ mulh: - sail(): | - { - if extension("M") | haveZmmul() then { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let rs1_int : int = if signed1 then signed(rs1_val) else unsigned(rs1_val); - let rs2_int : int = if signed2 then signed(rs2_val) else unsigned(rs2_val); - let result_wide = to_bits(2 * sizeof(xlen), rs1_int * rs2_int); - let result = if high - then result_wide[(2 * sizeof(xlen) - 1) .. sizeof(xlen)] - else result_wide[(sizeof(xlen) - 1) .. 0]; - X(rd) = result; - RETIRE_SUCCESS - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/M/mulhsu.yaml b/arch/inst/M/mulhsu.yaml index 1eab01c0d..32ae229c9 100644 --- a/arch/inst/M/mulhsu.yaml +++ b/arch/inst/M/mulhsu.yaml @@ -67,23 +67,3 @@ mulhsu: - sail(): | - { - if extension("M") | haveZmmul() then { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let rs1_int : int = if signed1 then signed(rs1_val) else unsigned(rs1_val); - let rs2_int : int = if signed2 then signed(rs2_val) else unsigned(rs2_val); - let result_wide = to_bits(2 * sizeof(xlen), rs1_int * rs2_int); - let result = if high - then result_wide[(2 * sizeof(xlen) - 1) .. sizeof(xlen)] - else result_wide[(sizeof(xlen) - 1) .. 0]; - X(rd) = result; - RETIRE_SUCCESS - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/M/mulhu.yaml b/arch/inst/M/mulhu.yaml index 0e156c83a..006815018 100644 --- a/arch/inst/M/mulhu.yaml +++ b/arch/inst/M/mulhu.yaml @@ -66,23 +66,3 @@ mulhu: - sail(): | - { - if extension("M") | haveZmmul() then { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let rs1_int : int = if signed1 then signed(rs1_val) else unsigned(rs1_val); - let rs2_int : int = if signed2 then signed(rs2_val) else unsigned(rs2_val); - let result_wide = to_bits(2 * sizeof(xlen), rs1_int * rs2_int); - let result = if high - then result_wide[(2 * sizeof(xlen) - 1) .. sizeof(xlen)] - else result_wide[(sizeof(xlen) - 1) .. 0]; - X(rd) = result; - RETIRE_SUCCESS - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/M/mulw.yaml b/arch/inst/M/mulw.yaml index 83cc94cf0..073079ef7 100644 --- a/arch/inst/M/mulw.yaml +++ b/arch/inst/M/mulw.yaml @@ -68,22 +68,3 @@ mulw: - sail(): | - { - if extension("M") | haveZmmul() then { - let rs1_val = X(rs1)[31..0]; - let rs2_val = X(rs2)[31..0]; - let rs1_int : int = signed(rs1_val); - let rs2_int : int = signed(rs2_val); - /* to_bits requires expansion to 64 bits followed by truncation */ - let result32 = to_bits(64, rs1_int * rs2_int)[31..0]; - let result : xlenbits = sign_extend(result32); - X(rd) = result; - RETIRE_SUCCESS - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/M/rem.yaml b/arch/inst/M/rem.yaml index 7a07f03d3..da87a828a 100644 --- a/arch/inst/M/rem.yaml +++ b/arch/inst/M/rem.yaml @@ -67,21 +67,3 @@ rem: - sail(): | - { - if extension("M") then { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val); - let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val); - let r : int = if rs2_int == 0 then rs1_int else rem_round_zero(rs1_int, rs2_int); - /* signed overflow case returns zero naturally as required due to -1 divisor */ - X(rd) = to_bits(sizeof(xlen), r); - RETIRE_SUCCESS - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/M/remu.yaml b/arch/inst/M/remu.yaml index f7370f08a..8c067ac62 100644 --- a/arch/inst/M/remu.yaml +++ b/arch/inst/M/remu.yaml @@ -57,21 +57,3 @@ remu: - sail(): | - { - if extension("M") then { - let rs1_val = X(rs1); - let rs2_val = X(rs2); - let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val); - let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val); - let r : int = if rs2_int == 0 then rs1_int else rem_round_zero(rs1_int, rs2_int); - /* signed overflow case returns zero naturally as required due to -1 divisor */ - X(rd) = to_bits(sizeof(xlen), r); - RETIRE_SUCCESS - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/M/remuw.yaml b/arch/inst/M/remuw.yaml index 81bcf227f..368e3be2b 100644 --- a/arch/inst/M/remuw.yaml +++ b/arch/inst/M/remuw.yaml @@ -69,21 +69,3 @@ remuw: - sail(): | - { - if extension("M") then { - let rs1_val = X(rs1)[31..0]; - let rs2_val = X(rs2)[31..0]; - let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val); - let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val); - let r : int = if rs2_int == 0 then rs1_int else rem_round_zero(rs1_int, rs2_int); - /* signed overflow case returns zero naturally as required due to -1 divisor */ - X(rd) = sign_extend(to_bits(32, r)); - RETIRE_SUCCESS - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/M/remw.yaml b/arch/inst/M/remw.yaml index bcd757dba..293d8f167 100644 --- a/arch/inst/M/remw.yaml +++ b/arch/inst/M/remw.yaml @@ -73,21 +73,3 @@ remw: - sail(): | - { - if extension("M") then { - let rs1_val = X(rs1)[31..0]; - let rs2_val = X(rs2)[31..0]; - let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val); - let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val); - let r : int = if rs2_int == 0 then rs1_int else rem_round_zero(rs1_int, rs2_int); - /* signed overflow case returns zero naturally as required due to -1 divisor */ - X(rd) = sign_extend(to_bits(32, r)); - RETIRE_SUCCESS - } else { - handle_illegal(); - RETIRE_FAIL - } - } - - \ No newline at end of file diff --git a/arch/inst/S/sfence.vma.yaml b/arch/inst/S/sfence.vma.yaml index 35cbe3c80..d771cc740 100644 --- a/arch/inst/S/sfence.vma.yaml +++ b/arch/inst/S/sfence.vma.yaml @@ -323,19 +323,3 @@ sfence.vma: - sail(): | - { - let addr : option(xlenbits) = if rs1 == 0b00000 then None() else Some(X(rs1)); - let asid : option(xlenbits) = if rs2 == 0b00000 then None() else Some(X(rs2)); - match cur_privilege { - User => { handle_illegal(); RETIRE_FAIL }, - Supervisor => match (architecture(get_mstatus_SXL(mstatus)), mstatus.TVM()) { - (Some(_), 0b1) => { handle_illegal(); RETIRE_FAIL }, - (Some(_), 0b0) => { flush_TLB(asid, addr); RETIRE_SUCCESS }, - (_, _) => internal_error(__FILE__, __LINE__, "unimplemented sfence architecture") - }, - Machine => { flush_TLB(asid, addr); RETIRE_SUCCESS } - } - } - - \ No newline at end of file diff --git a/arch/inst/S/sret.yaml b/arch/inst/S/sret.yaml index 27f2b003b..1d5dad224 100644 --- a/arch/inst/S/sret.yaml +++ b/arch/inst/S/sret.yaml @@ -145,21 +145,3 @@ sret: - sail(): | - { - let sret_illegal : bool = match cur_privilege { - User => true, - Supervisor => not(haveSupMode ()) | mstatus.TSR() == 0b1, - Machine => not(haveSupMode ()) - }; - if sret_illegal - then { handle_illegal(); RETIRE_FAIL } - else if not(ext_check_xret_priv (Supervisor)) - then { ext_fail_xret_priv(); RETIRE_FAIL } - else { - set_next_pc(exception_handler(cur_privilege, CTL_SRET(), PC)); - RETIRE_SUCCESS - } - } - - \ No newline at end of file diff --git a/arch/inst/V/vsetvli.yaml b/arch/inst/V/vsetvli.yaml index 8279debf7..3cc033558 100644 --- a/arch/inst/V/vsetvli.yaml +++ b/arch/inst/V/vsetvli.yaml @@ -99,74 +99,3 @@ vsetvli: - sail(): | - { - let VLEN_pow = get_vlen_pow(); - let ELEN_pow = get_elen_pow(); - let LMUL_pow_ori = get_lmul_pow(); - let SEW_pow_ori = get_sew_pow(); - let ratio_pow_ori = SEW_pow_ori - LMUL_pow_ori; - - /* set vtype */ - match op { - VSETVLI => { - vtype->bits() = 0b0 @ zeros(sizeof(xlen) - 9) @ ma @ ta @ sew @ lmul - }, - VSETVL => { - let rs2 : regidx = sew[1 .. 0] @ lmul; - vtype->bits() = X(rs2) - } - }; - - /* check legal SEW and LMUL and calculate VLMAX */ - let LMUL_pow_new = get_lmul_pow(); - let SEW_pow_new = get_sew_pow(); - if SEW_pow_new > LMUL_pow_new + ELEN_pow then { - /* Note: Implementations can set vill or trap if the vtype setting is not supported. - * TODO: configuration support for both solutions - */ - vtype->bits() = 0b1 @ zeros(sizeof(xlen) - 1); /* set vtype.vill */ - vl = zeros(); - print_reg("CSR vtype <- " ^ BitStr(vtype.bits())); - print_reg("CSR vl <- " ^ BitStr(vl)); - return RETIRE_SUCCESS - }; - let VLMAX = int_power(2, VLEN_pow + LMUL_pow_new - SEW_pow_new); - - /* set vl according to VLMAX and AVL */ - if (rs1 != 0b00000) then { /* normal stripmining */ - let rs1_val = X(rs1); - let AVL = unsigned(rs1_val); - vl = if AVL <= VLMAX then to_bits(sizeof(xlen), AVL) - else if AVL < 2 * VLMAX then to_bits(sizeof(xlen), (AVL + 1) / 2) - else to_bits(sizeof(xlen), VLMAX); - /* Note: ceil(AVL / 2) <= vl <= VLMAX when VLMAX < AVL < (2 * VLMAX) - * TODO: configuration support for either using ceil(AVL / 2) or VLMAX - */ - X(rd) = vl; - } else if (rd != 0b00000) then { /* set vl to VLMAX */ - let AVL = unsigned(ones(sizeof(xlen))); - vl = to_bits(sizeof(xlen), VLMAX); - X(rd) = vl; - } else { /* keep existing vl */ - let AVL = unsigned(vl); - let ratio_pow_new = SEW_pow_new - LMUL_pow_new; - if (ratio_pow_new != ratio_pow_ori) then { - /* Note: Implementations can set vill or trap if the vtype setting is not supported. - * TODO: configuration support for both solutions - */ - vtype->bits() = 0b1 @ zeros(sizeof(xlen) - 1); /* set vtype.vill */ - vl = zeros(); - } - }; - print_reg("CSR vtype <- " ^ BitStr(vtype.bits())); - print_reg("CSR vl <- " ^ BitStr(vl)); - - /* reset vstart to 0 */ - vstart = zeros(); - print_reg("CSR vstart <- " ^ BitStr(vstart)); - - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/Zfh/fcvt.h.s.yaml b/arch/inst/Zfh/fcvt.h.s.yaml index 6c7f976ba..ac5b65a91 100644 --- a/arch/inst/Zfh/fcvt.h.s.yaml +++ b/arch/inst/Zfh/fcvt.h.s.yaml @@ -85,21 +85,3 @@ fcvt.h.s: - sail(): | - { - assert(sizeof(xlen) >= 64); - let rs1_val_LU = X(rs1)[63..0]; - match (select_instr_or_fcsr_rm (rm)) { - None() => { handle_illegal(); RETIRE_FAIL }, - Some(rm') => { - let rm_3b = encdec_rounding_mode(rm'); - let (fflags, rd_val_H) = riscv_ui64ToF16 (rm_3b, rs1_val_LU); - - accrue_fflags(fflags); - F_or_X_H(rd) = rd_val_H; - RETIRE_SUCCESS - } - } - } - - \ No newline at end of file diff --git a/arch/inst/Zfh/fcvt.s.h.yaml b/arch/inst/Zfh/fcvt.s.h.yaml index af59f1b7a..c974fbbb5 100644 --- a/arch/inst/Zfh/fcvt.s.h.yaml +++ b/arch/inst/Zfh/fcvt.s.h.yaml @@ -82,21 +82,3 @@ fcvt.s.h: - sail(): | - { - assert(sizeof(xlen) >= 64); - let rs1_val_LU = X(rs1)[63..0]; - match (select_instr_or_fcsr_rm (rm)) { - None() => { handle_illegal(); RETIRE_FAIL }, - Some(rm') => { - let rm_3b = encdec_rounding_mode(rm'); - let (fflags, rd_val_H) = riscv_ui64ToF16 (rm_3b, rs1_val_LU); - - accrue_fflags(fflags); - F_or_X_H(rd) = rd_val_H; - RETIRE_SUCCESS - } - } - } - - \ No newline at end of file diff --git a/arch/inst/Zfh/flh.yaml b/arch/inst/Zfh/flh.yaml index 67a77dc79..359476ba4 100644 --- a/arch/inst/Zfh/flh.yaml +++ b/arch/inst/Zfh/flh.yaml @@ -71,33 +71,3 @@ flh: - sail(): | - { - let offset : xlenbits = sign_extend(imm); - /* Get the address, X(rs1) + offset. - Some extensions perform additional checks on address validity. */ - match ext_data_get_addr(rs1, offset, Read(Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => - if check_misaligned(vaddr, width) - then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } - else match translateAddr(vaddr, Read(Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => { - let (aq, rl, res) = (false, false, false); - match (width) { - BYTE => { handle_illegal(); RETIRE_FAIL }, - HALF => - process_fload16(rd, vaddr, mem_read(Read(Data), addr, 2, aq, rl, res)), - WORD => - process_fload32(rd, vaddr, mem_read(Read(Data), addr, 4, aq, rl, res)), - DOUBLE if sizeof(flen) >= 64 => - process_fload64(rd, vaddr, mem_read(Read(Data), addr, 8, aq, rl, res)), - _ => report_invalid_width(__FILE__, __LINE__, width, "floating point load"), - } - } - } - } - } - - \ No newline at end of file diff --git a/arch/inst/Zfh/fmv.h.x.yaml b/arch/inst/Zfh/fmv.h.x.yaml index 26afffd64..b5f9fbca6 100644 --- a/arch/inst/Zfh/fmv.h.x.yaml +++ b/arch/inst/Zfh/fmv.h.x.yaml @@ -42,12 +42,3 @@ fmv.h.x: - sail(): | - { - let rs1_val_X = X(rs1); - let rd_val_H = rs1_val_X [15..0]; - F(rd) = nan_box (rd_val_H); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/Zfh/fmv.x.h.yaml b/arch/inst/Zfh/fmv.x.h.yaml index cc1149496..391b0190a 100644 --- a/arch/inst/Zfh/fmv.x.h.yaml +++ b/arch/inst/Zfh/fmv.x.h.yaml @@ -44,12 +44,3 @@ fmv.x.h: - sail(): | - { - let rs1_val_X = X(rs1); - let rd_val_H = rs1_val_X [15..0]; - F(rd) = nan_box (rd_val_H); - RETIRE_SUCCESS - } - - \ No newline at end of file diff --git a/arch/inst/Zfh/fsh.yaml b/arch/inst/Zfh/fsh.yaml index 0ebc924ce..9295c87ea 100644 --- a/arch/inst/Zfh/fsh.yaml +++ b/arch/inst/Zfh/fsh.yaml @@ -82,43 +82,3 @@ fsh: - sail(): | - { - let offset : xlenbits = sign_extend(imm); - let (aq, rl, con) = (false, false, false); - /* Get the address, X(rs1) + offset. - Some extensions perform additional checks on address validity. */ - match ext_data_get_addr(rs1, offset, Write(Data), width) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => - if check_misaligned(vaddr, width) - then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL } - else match translateAddr(vaddr, Write(Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr, _) => { - let eares : MemoryOpResult(unit) = match width { - BYTE => MemValue () /* bogus placeholder for illegal size */, - HALF => mem_write_ea(addr, 2, aq, rl, false), - WORD => mem_write_ea(addr, 4, aq, rl, false), - DOUBLE => mem_write_ea(addr, 8, aq, rl, false) - }; - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - MemValue(_) => { - let rs2_val = F(rs2); - match (width) { - BYTE => { handle_illegal(); RETIRE_FAIL }, - HALF => process_fstore (vaddr, mem_write_value(addr, 2, rs2_val[15..0], aq, rl, con)), - WORD => process_fstore (vaddr, mem_write_value(addr, 4, rs2_val[31..0], aq, rl, con)), - DOUBLE if sizeof(flen) >= 64 => - process_fstore (vaddr, mem_write_value(addr, 8, rs2_val, aq, rl, con)), - _ => report_invalid_width(__FILE__, __LINE__, width, "floating point store"), - }; - } - } - } - } - } - } - - \ No newline at end of file diff --git a/arch/inst/Zicsr/csrrs.yaml b/arch/inst/Zicsr/csrrs.yaml index 1bb9b5d98..61a18884d 100644 --- a/arch/inst/Zicsr/csrrs.yaml +++ b/arch/inst/Zicsr/csrrs.yaml @@ -70,30 +70,3 @@ csrrs: - sail(): | - { - let rs1_val : xlenbits = if is_imm then zero_extend(rs1) else X(rs1); - let isWrite : bool = match op { - CSRRW => true, - _ => if is_imm then unsigned(rs1_val) != 0 else unsigned(rs1) != 0 - }; - if not(check_CSR(csr, cur_privilege, isWrite)) - then { handle_illegal(); RETIRE_FAIL } - else if not(ext_check_CSR(csr, cur_privilege, isWrite)) - then { ext_check_CSR_fail(); RETIRE_FAIL } - else { - let csr_val = readCSR(csr); /* could have side-effects, so technically shouldn't perform for CSRW[I] with rd == 0 */ - if isWrite then { - let new_val : xlenbits = match op { - CSRRW => rs1_val, - CSRRS => csr_val | rs1_val, - CSRRC => csr_val & ~(rs1_val) - }; - writeCSR(csr, new_val) - }; - X(rd) = csr_val; - RETIRE_SUCCESS - } - } - - \ No newline at end of file diff --git a/arch/inst/Zicsr/csrrw.yaml b/arch/inst/Zicsr/csrrw.yaml index 1a76e18c9..28188e4af 100644 --- a/arch/inst/Zicsr/csrrw.yaml +++ b/arch/inst/Zicsr/csrrw.yaml @@ -66,30 +66,3 @@ csrrw: - sail(): | - { - let rs1_val : xlenbits = if is_imm then zero_extend(rs1) else X(rs1); - let isWrite : bool = match op { - CSRRW => true, - _ => if is_imm then unsigned(rs1_val) != 0 else unsigned(rs1) != 0 - }; - if not(check_CSR(csr, cur_privilege, isWrite)) - then { handle_illegal(); RETIRE_FAIL } - else if not(ext_check_CSR(csr, cur_privilege, isWrite)) - then { ext_check_CSR_fail(); RETIRE_FAIL } - else { - let csr_val = readCSR(csr); /* could have side-effects, so technically shouldn't perform for CSRW[I] with rd == 0 */ - if isWrite then { - let new_val : xlenbits = match op { - CSRRW => rs1_val, - CSRRS => csr_val | rs1_val, - CSRRC => csr_val & ~(rs1_val) - }; - writeCSR(csr, new_val) - }; - X(rd) = csr_val; - RETIRE_SUCCESS - } - } - - \ No newline at end of file diff --git a/arch/inst/Zicsr/csrrwi.yaml b/arch/inst/Zicsr/csrrwi.yaml index 0dba8f39d..72ca7a7cb 100644 --- a/arch/inst/Zicsr/csrrwi.yaml +++ b/arch/inst/Zicsr/csrrwi.yaml @@ -66,30 +66,3 @@ csrrwi: - sail(): | - { - let rs1_val : xlenbits = if is_imm then zero_extend(rs1) else X(rs1); - let isWrite : bool = match op { - CSRRW => true, - _ => if is_imm then unsigned(rs1_val) != 0 else unsigned(rs1) != 0 - }; - if not(check_CSR(csr, cur_privilege, isWrite)) - then { handle_illegal(); RETIRE_FAIL } - else if not(ext_check_CSR(csr, cur_privilege, isWrite)) - then { ext_check_CSR_fail(); RETIRE_FAIL } - else { - let csr_val = readCSR(csr); /* could have side-effects, so technically shouldn't perform for CSRW[I] with rd == 0 */ - if isWrite then { - let new_val : xlenbits = match op { - CSRRW => rs1_val, - CSRRS => csr_val | rs1_val, - CSRRC => csr_val & ~(rs1_val) - }; - writeCSR(csr, new_val) - }; - X(rd) = csr_val; - RETIRE_SUCCESS - } - } - - \ No newline at end of file