HowTo

How to add a shared L3 cache?

1. Set cache properties
   Example: commit b77a4e7
2. Add new options
   Example: commit 2db5be6
   
3. Change cache config
   Example: commit b62d317
   Tips:
   

• We rely on methods in src/cpu/BaseCPU.py. For example, connectAllPorts() is used to connect cached ports of the CPU to the (shared) cache bus, and all uncached ports directly to the memory bus.
  
• The resulting structure is as below.
  

......
cpu[i].toL2Bus
     |(master)
     |(cpu_side)
cpu[i].l2cache
     |(mem_side/cpu[i]._cached_ports)
     |(slave)
system.tol3bus
     |(master)
     |(cpu_side)
system.l3
     |(mem_side)       cpu[i]._uncached_slave/master_ports
     |(slave)                       |(master/slave) 
system.membus-----------------------|