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A small modification #7

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CHENfd515 opened this issue Nov 14, 2024 · 0 comments
Open

A small modification #7

CHENfd515 opened this issue Nov 14, 2024 · 0 comments

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@CHENfd515
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Hi, this is Alex.

I suggest that we replace the expression "wire next_bit = cycle_counter == CYCLES_PER_BIT;" [uart_tx.v (line:92)] with a new one: "wire next_bit = cycle_counter == (CYCLES_PER_BIT >= 1 ? CYCLES_PER_BIT - 1 : 0);".

This change is necessary because when BIT_RATE is equal to CLK_HZ, the module does not transfer data at a rate of one bit per cycle, leading to a redundant cycle. (see below)

before modification: a redundant cycle

After making this modification, the waveform will look like this:

after modification

Best Regards.

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