| Release | Author | Description |
|---|---|---|
| 3.00.XX | Allen Albright | Refactor (Many Changes) |
| 3.01.00 | Allen Albright | First Public Release (Day Zero Update) |
| 3.01.01 | Allen Albright | ULA : Interrupt time in 48K and 128K video frame was off by one cycle ULA+ : Byte read from port 0xff3b incorrectly indicated ula+ was not present AUDIO : Attempt to double volume on 3.5mm jack and internal speaker AY : Implement differences in how AY and YM respond to register reads PORT DECODE : Bit 31 of nextreg 0x89 and 0x85 determines whether the port decodes are soft or hard reset SCANLINES : Change weights to 0, 12.5, 25, 50 COMPATIBILITY : Port decoding style now determined by current video timing rather than static machine type; active ports no longer limited by machine type STICKS : Sinclair 1 and Sinclair 2 joystick types were reversed in the hardware HDMI : Audio stream made signed instead of unsigned NMI : Function key activation now cancels nmi generation so that minimum press time of one second is no longer needed MEMORY : Nextreg 0x8e added to more quickly perform traditional bankswitching normally done through ports 0x1ffd, 0x7ffd, 0xdffd SLU 6 & 7 : Blending updated to be more useful * Nextreg 0x68 bits 6:5 control which of ula or tilemap layer blends with layer 2 * SLU 6 = (U or T)S(T or U)(B+L) colours clamped to [0,7] * SLU 7 = (U or T)S(T or U)(B+L-5) colours clamped to [0,7] In both cases U or T only appear independently if they are not involved in blending |
| 3.01.02 | Allen Albright | DMA : Ports 0x6b and 0x0b (new) both address the dma. When port 0x0b is read or written the dma is placed in z80-dma compatibility mode. When port 0x6b is read or written the dma is placed in its native zxn-dma mode. Nextreg 0x06 bit 6 which used to select dma mode has been removed. PORT DECODE : Nextreg 0x85 and 0x89 have bit 25 added to enable dma port 0x0b EXPANSION BUS : Nextreg 0x8a bit 4 allows propagation of port 0xff io cycles to the expansion bus. AUDIO : Nextreg 0x06 bit 6 chosen to select a new classic audio mode where beep and tape noises are directed to the internal speaker exclusively and other audio is directed to hdmi and the 3.5mm jack. AUDIO : Another adjustment of the internal speaker volume and a different treatment for the classic audio mode that allows beep noises to be louder. |
| 3.01.03 | Allen Albright | AY : Fix bug where the envelope period counter was not reset when register 13 was written. AUDIO : Another adjustment of internal speaker volume with total volume increased at the expense of increased likelihood of clipping and classic mode audio made a little more quiet. EXPANSION BUS : (trial) Introduce a ROMCS rom replacement feature enabled by bits 6 and 2 in nextreg 0x80. External devices can continue to assert /romcs but the next can replace the 16k external rom with divmmc banks 14 and 15 to allow custom code to be written to support external devices more seemlessly. EXPANSION BUS : Nextreg 0x8a defaults to all port propagation disabled on hard reset. Port 0xfe was propagated by default prior to this change. MEMORY : Nextreg 0x8e no longer changes mmu 6/7 when the ram bank is not changed. |
| 3.01.04 | Allen Albright | DMA : The 16-bit byte count now read in the correct endian order through the read register. MULTIFACE : Fix numerous errors in the implementation of the mf128 and mf48. STICKS : Correct md pad state machine that was reading some input at the wrong time. STICKS : The joystick connectors can now be configured as an i/o device with 1 output and up to 12 inputs. Three modes are supported including bit-bang where the state of the output bit is controlled by the program, clock where the output bit is driven by either a slow or a fast clock, and uart where one of the next's two internal uarts can be redirected to the joystick connector. Details can be found in documentation for port 0x37 and nextreg 0x05. STICKS : Button A on md pads now generates an UP direction for non- md pad joystick modes. COMPATIBILITY : Pentagon 512K support is added that is activated when the video timing is set to Pentagon and when bit 7 of port 0xdffd is set to 1. In this mode, port 0xdffd is ignored in banking and instead bits 7:6 of port 0x7ffd extend bits 2:0 of the same port to select a 16K bank. KEYBOARD : It is now possible to read the state of the new composite keys directly instead of indirectly through the key membrane. Details under nextreg 0x68, 0xb0, 0xb1. |
| 3.01.05 | Allen Albright | DISPLAY : A vertical line offset has been introduced in nextreg 0x64. The display continues to use vertical line positions with 0 indicating the first row of the pixel area generated by the ULA. However the copper, line interrupt (nextreg 0x22,0x23) and active video line (nextreg 0x1e,0x1f) have their Y positions offset by this new register. When line 0 of the ULA is reached, the Y position of these other units is set to the vertical line offset. As an example, an offset of 32 would have the copper line position at 32 when the display draws line 0 of the ULA and the copper line position of 0 would correspond to 32 lines earlier where the sprites and tilemap have their Y=0 position. COMPATIBILITY : Bit 7 of port 0xdffd, which selects Pentagon 512k mode, can only be changed when pentagon timing is not active. COMPATIBILITY : All port contention has been disabled for the +3. I2S : I2S master mode has been removed with nextreg 0xa2,0xa3 affected. MOUSE : Mouse dpi and button swap controls have been introduced in nextreg 0x0a. STICKS : Joystick io mode can now be operated the preferred way with io mode selected via port 0x37 before the io mode is enabled on the joysticks via nextreg 0x05. STICKS : Joystick io mode now reads from one joystick only, selected by bit 4 of port 0x37. This was necessary to allow reliable 2Mbps transfer rate in uart mode. The program can still change the active joystick via bit 4 of port 0x37 at any time but for uart mode this should be done during a quiet time in communication. Any output always appears on pin 7 of both joystick connectors. |
| 3.01.06 | Allen Albright | COMPATIBILITY : Pentagon 512, pentagon 1024 and zx profi memory mapping modes added with control through new i/o port 0xeff7 and nextreg 0x8f. These mapping modes can be enabled or disabled at any time and no longer depend on pentagon video timing being active to take effect. STICKS : Correct MD Pad algorithm so that it doesn't toggle the select pin for a few cycles into the rest period. MULTI-CORE : Physical SRAM address pins A10 and A18 were swapped to place FPGA configuration pin HSWAPEN on A18. This restricts SRAM corruption to odd multiples of 256K between core boots. Core sram initialization can safely be done in even multiples of 256K and the initialization program running in standard spectrum memory does not reside in the safe areas so that it does not reduce the amount of initialized sram available to cores. Nextreg 0x04 ram bank has been expanded to seven bits from five so that the entire 2MB of memory is reachable for the sram initializer, making half the zx next's memory accessible to initialization for cores. MULTI-CORE : Move CPU A0 to A19 so that the 16-bit physical sram interface can be used by the core. Even addresses use D7:D0 of the physical sram data bus and odd addresses use D15:D8 of the physical sram data bus. Initializing memory for other 16-bit cores should be made simpler. DISPLAY : All palettes now have two layer priority bits for possible future developments. AUDIO : HDMI audio returned to previous unsigned volume levels as some displays were incapable of rendering full signed 16-bit audio properly. |
| 3.01.07 | Allen Albright | DIVMMMC / MULTIFACE : The internal divmmc and multiface have been made compatible so that both can be enabled at the same time in esxdos. MULTIFACE : All multiface versions are now supported -- mf 1, mf 128 v87.12, mf 128 v87.2 and mf 3. The type is selected at config time from the menu line's mf rom name and is held in nextreg 0x0A. (Until the firmware is updated the multiface type can be changed and must be written to nextreg 0x0A by the user before first use; NextZXOS is unaffected because the default type is mf 3). MOUSE : The mouse button reversal bit in nextreg 0x0A was moved to bit 3. EXPANSION BUS : Nextreg 0x81 bit 5 indicates that nmi debouncing should be disabled. This is required by the Opus Discovery which uses the nmi interrupt to service the floppy controller. This change is made an option as it conflicts with nmi button debouncing required by other peripherals. EXPANSION BUS : Nextreg 0x81 bit 6 allows external peripherals to override the ula on even port address reads from 0x00 to 0x0E. This is required by the Rotronics Wafadrive which overlaps its i/o on the ula's port 0xfe. EXPANSION BUS : New function keys F5 (nmi+5) and F6 (nmi+6) enable and disable the expansion bus respectively by changing bit 7 of nextreg 0x80. This makes it easy to quickly switch between esxdos (when the expansion bus is off) and other mass storage devices (when the expansion bus is on) for transferring files between sd card and microdrive or disk. The switch can be done at any time including from within the multiface nmi menu. |
| 3.01.08 | Allen Albright | CTC : Eight Z80 Counter / Timers are accessible via i/o ports 0x183B through 0x1F3B. These are equivalent to a standard Zilog Z8430 CTC and can be programmed the same way. A pdf is available at http://www.zilog.com/docs/z80/ps0181.pdf . Currently the zc/to flag of CTC (n) is fed as trigger into CTC (n+1) so that counters can be cascaded. If a CTC channel is programmed to generate interrupts (see the pdf and nextreg 0xC6) it will generate an interrupt in the same way as the ULA's. Interrupt handling and the set of hardware signals appearing as triggers to the CTC channels will be addressed in the next core version. The CTC's inclusion is intended to supply timers and interrupt ability for hardware signals. DISPLAY : The tilemap's base address (nextreg 0x6E) and tile definitions address (nextreg 0x6F) can now appear in the first 8K of 16K bank 7 and is indicated by a set bit 7 in the address. Because only 8K of bram is available in bank 7, addresses wrap across 8K boundaries. MULTIFACE : Multiface type is now set at config time according to the filename of the loaded mf rom (requires fw 1.29d or later). EXPANSION BUS : When nextreg 0x81 bit 5 is set (Opus Discovery) allow nmi pulses to be delivered while the multiface is active. Z80 : Correct opcode for undocumented instance of instruction "im 2" (ED 7E). |
OLDER
| Release | Author | Description |
|---|---|---|
| 2.00.00 | Victor Trucco Fabio Belavenuto |
Spectrum Next Core Release |
| 2.00.01 | Garry Lancaster | Peripherals: NextReg 9 bit 2 now completely disables DivMMC SPI ports ($EB and $E7) if set |
| 2.00.02 | Garry Lancaster | Peripherals: Drive button no longer causes a reset if DivMMC auto-paging is disabled |
| 2.00.03 | no valid change | |
| 2.00.04 | Garry Lancaster | Fixed: Timex hi-res is now correctly aligned instead of offset 1 pixel to the left |
| 2.00.05 | Allen Albright | Fixed: Hang on reset caused by some ESP modules |
| 2.00.06 | Garry Lancaster | Peripherals: NextReg 9 bit 2 now also disables DivMMC paging port ($E3) Peripherals: NextReg 9 bit 3 disables Kempston mouse port ($DF) |
| 2.00.07 | Allen Albright | Fixed: Read of nextreg 7 returns actual speed setting Fixed: DMA prescaler internally multiplied by four to reach lower sample rates Fixed: DMA sample rate constant for all CPU speeds |
| 2.00.08 | Allen Albright | Fixed: DMA returns all idle cycles to CPU in burst mode Fixed: DMA implements daisy chain for multiple bus masters |
| 2.00.09 | Allen Albright | Multiple Cores: Allow boot firmware to start a specific core identified by number 0-31 |
| 2.00.10 | Jim Bagley | Video: Layer2 palette bit 15 now acts as high priority bit, bringing Layer2 to the front if set, regardless of SLU setting Video: Added SLU 110: colour=(U+L)>>1 Video: Added SLU 111: colour=(U+L) |
| 2.00.11 | Allen Albright | Fixed: AY zero volume means channel is silent |
| 2.00.12 | Allen Albright | Fixed: Pentagon border timing |
| 2.00.13 | Garry Lancaster | Registers: NextReg 0x03 writes with bit 7 set now accepted in any mode to change timings (bits 6-4) Registers: Read of NextReg 0x3 bit 7 now returns next palette byte to be written (0=RRRGGGBB, 1=B-low) Fixed: NextReg 0x18, 0x19, 0x1A, 0x1C now readable |
| 2.00.14 | Allen Albright | Fixed: Pentagon port decoding on 0x7ffd for "Kpacku Deluxe" Fixed: DMA wait states stretch read/write cycles rather than insert delays between read/write cycles UART: Setting LSB of UART prescalar only affects LSB ExpBus: I/O port decoding raised to top level |
| 2.00.15 | intermediate | |
| 2.00.16 | intermediate | |
| 2.00.17 | Jim Bagley | Video: Modified SLU 110 colour = (U+L) clamped Video: Modified SLU 111 colour = (U+L)-5 Sprites: Fix left border bug Sprites: Raise limit per line to 16 (with caveats) |
| 2.00.18 | Garry Lancaster | Z80N: Added 5 new barrel shift/rotate instructions: ED 28: BSLA DE,B (shift DE left by B places - uses bits 4..0 of B only) ED 29: BSRA DE,B (arithmetic shift right DE by B places - uses bits 4..0 of B only) ED 2A: BSRL DE,B (logical shift right DE by B places - uses bits 4..0 of B only) ED 2B: BSRF DE,B (shift right DE by B places, filling from left with 1s - uses bits 4..0 of B only) ED 2C: BRLC DE,B (rotate DE left by B places - uses bits 3..0 of B only) (to rotate right, use B=16-places) |
| 2.00.19 | Allen Albright Garry Lancaster |
Z80N: ED 98 JP (C) -- PC[13:0] = IN (C) << 6 Fixed: Sprites always appear above the ula border AY: Each AY can be made mono via NextReg 0x09 bits 7:5 |
| 2.00.20 | Allen Albright | Sprites: New module allows all 64 sprites to display on a line |
| 2.00.21 | Allen Albright | Sprites: Fifth attribute byte is present if bit 6 of the fourth attribute byte is set H N6 0 X X Y Y Y8 4-Bit Patterns H = 1 means the sprite uses 4-bit patterns N6 = 0 chooses the top 128 bytes of the 256-byte pattern otherwise the bottom 128 bytes Sprite Scaling XX and YY affect scaling in the X and Y directions 00 = *1 16 pixels 01 = *2 32 pixels 10 = *4 64 pixels 11 = *8 128 pixels Y8 is the ninth bit of the Y coorindate to allow wrapping on the Y axis Sprites: Nextreg 0x15 bit 6 = 1 changes sprite priority so that sprite 0 is on top Sprites: Nextreg 0x15 bit 5 = 1 enables clipping in over border mode Sprites: Writing to port 0x303B with bit 7 set adds an offset of 128 to the pattern index |
| 2.00.22 | Allen Albright | Z80N: Allow the cpu to run at 14MHz all the time if layer 2 is disabled Sprites: When not in over border mode, enforce clipping to display area at minimum Fixed: Sprites over-border clipping right edge adjusted one pixel left Fixed: Detection of too many sprites on a line was flawed Fixed: Sprites status port was always returning zero Fixed: Sprite module was writing vertical line at left edge on HDMI 60Hz |
| 2.00.23 | Allen Albright | Fixed: AY port decoding relaxed to work with sid-type music players Fixed: Clip window for sprites in over-border mode now extends to X2*2+1 instead of X2*2-1Layer 2: Allow 14MHz when outside the layer 2 clip window vertically Sprites: Use coregen memories to reduce size Sprites: Implement relative sprite mode activated when H,N6=01. In this mode an (x,y) coordinate, H bit and visibility bit are inherited from the last non-relative sprite. The inherited (x,y) is added to the sprite's (x,y) to determine position, the inherited H bit together with normally reserved bit 5 determines 4-bit mode and the inherited visibility bit is ANDed with the sprite's visibility bit to determine if the sprite is drawn Sprites: A nexreg mirror is set up on register 0x34 (RW) to select sprite number and registers 0x35-0x39 (W) to directly access the corresponding sprite's attributes. A second set of registers at 0x75-0x79 (W) are identical to 0x34-0x39 but a write to those will auto-increment the sprite number in register 0x34. Sprites: Setting bit 7 of the sprite number in nextreg 0x34 will tie the sprite number used by nextreg and io ports together. |
| 2.00.24 | Allen Albright | Sprites: Increase to 128 sprites from 64 |
| 2.00.25 | Allen Albright | Fixed: CPU slowdown is applied in the active display area when the ULA shadow screen is active Fixed: ULA border colour in ULAnext mode is fetched from paper colours at palette offset 128 ULA: Now scrolls using the LoRes scroll registers; scrolling in the x direction is currently limited to multiples of 8 pixels ULA: Nextreg 0x68 ULA Control added that disables ula output among other things Build: Registers inserted in video path to improve build reliability ExpBus: /RESET signal restored ExpBus: ULA /INT signal propagated to bus Tilemap: A new display mode for tiles in either 40x32 (320x256) or 80x32 (640x256) resolution that occupies the same display area as sprites and shares 16k bank 5 with the ULA for its tilemap and tile definitions. The tilemap consists of an array of 40x32 or 80x32 16-bit tiles with each tile described as follows: bit 15-12 = palette offset bit 11 = X mirror bit 10 = Y mirror bit 9 = rotate bit 8 = ula over tilemap (tile id bit 8 if ula is disabled) bit 7- 0 = tile id Each tile glyph is 8x8 pixels and 32 bytes in size, defined in the same way as 4-bit sprites |
| 2.00.26 | Allen Albright | Tilemap: Obey SLU order in border area Sprites: Lock bit in nextreg 0x34 moved to bit 4 of nextreg 0x09 so that nextreg 0x34 can behave exactly like io port 0x303B when the two are tied |
| 2.00.27 | Allen Albright | ULANext: Paper and border colour for all ink mode now comes from the fallback colour in nextreg 0x4A DMA: Add Z80-DMA compatibility bit in nextreg 0x06. When set, the transfer length is increased by one DMA: Implement the STATUS register returning 00E1101T where E=0 if the entire block has completed transfer at least once and T=1 if at least one byte has been transferred DMA: Implement new commands RESET 0xC3, RESET PORT A TIMING 0xC7, RESET PORT B TIMING 0xCB, READ STATUS BYTE 0xBF, REINITIALIZE STATUS BYTE 0x8B, INITIALIZE READ SEQUENCE 0xA7. These are still being tested. Sprites: Implement a second relative sprite mode - the unified sprite. Relative sprites are rotated and mirrored around the anchor. Tilemap: Make 512 tile mode a separately indicated mode in nextreg 0x6B instead of only being available when the ULA is disabled. Tilemap: Add bit to nextreg 0x6B to force the tilemap over the ULA. ZX48: Correct ram contention for 48k spectrum machine type. ULA: Fix Timex hi-res offset by one pixel bug. |
| 2.00.28 | Allen Albright | Numerous changes. |