cgra_x_heep.core

CAPI=2:

# Copyright 2022 EPFL
# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1

name: eslepfl:systems:cgra-x-heep
description: CGRA X-HEEP Top.

filesets:
  files_rtl_generic:
    depend:
    - x-heep::packages
    - openhwgroup.org:systems:core-v-mini-mcu
    - eslepfl::cgra
    files:
    - hw/rtl/cgra_x_heep_pkg.sv
    - hw/rtl/cgra_x_heep_top.sv
    file_type: systemVerilogSource

  x_heep_system:
    depend:
    - x-heep::packages
    - x-heep:ip:pad_control
    files:
    - hw/vendor/esl_epfl_x_heep/hw/system/x_heep_system.sv
    - hw/vendor/esl_epfl_x_heep/hw/system/pad_ring.sv
    file_type: systemVerilogSource

  tb-harness:
    files:
    - tb/tb_util.svh: {is_include_file: true}
    - tb/testharness.sv
    file_type: systemVerilogSource

  files_verilator_waiver:
    files:
    - tb/tb.vlt
    - hw/rtl/cgra_top.vlt
    file_type: vlt

  systemverilog_only_simjtag:
    depend:
    - pulp-platform.org::pulpissimo_simjtag

  uartdpi:
    depend:
    - lowrisc:dv_dpi:uartdpi

  systemverilog_only_uart:
    files:
    - hw/vendor/esl_epfl_x_heep/hw/vendor/lowrisc_opentitan/hw/dv/dpi/uartdpi/uartdpi.sv
    file_type: systemVerilogSource

  remote_bitbang_dpi:
    depend:
    - pulp-platform.org::pulpissimo_remote_bitbang

  cypress_flash:
    depend:
    - ::spiflash:0

  # Scripts for hooks
  pre_build_remote_bitbang:
    files:
    - scripts/sim/compile_remote_bitbang.sh
    file_type: user

  pre_build_uartdpi:
    files:
    - scripts/sim/compile_uart_dpi.sh
    file_type: user

  pre_patch_modelsim_Makefile:
    files:
    - scripts/sim/modelsim/patch_modelsim_Makefile.py
    file_type: user

  tb-verilator:
    files:
    - tb/tb_top.cpp
    file_type: cppSource

  tb-sv:
    files:
    - tb/tb_top.sv
    file_type: systemVerilogSource

  rtl-fpga:
    files:
    - hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv
    - hw/fpga/sram_wrapper.sv
    - hw/fpga_cgra/cgra_sram_wrapper.sv
    - hw/fpga_cgra/cgra_clock_gate.sv
    - hw/fpga_cgra/xilinx_cgra_x_heep_wrapper.sv
    file_type: systemVerilogSource

  ip-fpga:
    files:
    - hw/fpga/scripts/xilinx_generate_clk_wizard.tcl:  { file_type: tclSource }
    - hw/fpga/scripts/generate_sram.tcl:  { file_type: tclSource }
    - hw/fpga/prim_xilinx_clk.sv:  { file_type: systemVerilogSource } # Here there are the following modules
    - hw/fpga/cve2_xilinx_clock_gate.sv:  { file_type: systemVerilogSource }
    - hw/fpga/pad_cell_input_xilinx.sv:  { file_type: systemVerilogSource }
    - hw/fpga/pad_cell_output_xilinx.sv:  { file_type: systemVerilogSource }
    - hw/fpga/pad_cell_inout_xilinx.sv:  { file_type: systemVerilogSource }
    - hw/fpga/pad_cell_bypass_input_xilinx.sv:  { file_type: systemVerilogSource }
    - hw/fpga/pad_cell_bypass_output_xilinx.sv:  { file_type: systemVerilogSource }

  fpga-arm-emulation:
    depend:
    - pulp-platform.org::axi_spi_slave
    files:
    - linux_femu/scripts/xilinx_generate_processing_system.tcl: {file_type: tclSource}
    - linux_femu/rtl/axi_address_hijacker.v: {file_type: verilogSource}
    - linux_femu/rtl/linux_femu.sv: {file_type: systemVerilogSource}
    - linux_femu/constraints/pin_assign.xdc: {file_type: xdc}
    - linux_femu/constraints/constraints.xdc: {file_type: xdc}

  xdc-fpga-pynq-z2:
    files:
    - hw/fpga_cgra/constraints/pin_assign.xdc
    file_type: xdc

  netlist-fpga:
    files:
    - build/openhwgroup.org_systems_core-v-mini-mcu_0/nexys-a7-100t-vivado/core_v_mini_mcu_xiling_postsynth.v
    file_type: verilogSource  

parameters:
  COREV_PULP:
    datatype: int
    paramtype: vlogparam
    default: 0
  JTAG_DPI:
    datatype: int
    paramtype: vlogparam
    default: 0
  USE_UPF:
    datatype: bool
    paramtype: vlogdefine
    default: false
  SYNTHESIS:
    datatype: bool
    paramtype: vlogdefine
    default: false
  # Make the parameter known to FuseSoC to enable overrides from the
  # command line. If not overwritten, use the generic technology library.
  PRIM_DEFAULT_IMPL:
    datatype: str
    paramtype: vlogdefine
    description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".
    default: prim_pkg::ImplGeneri
scripts:
  pre_build_remote_bitbang:
    cmd:
    - sh
    - ../../../scripts/sim/compile_remote_bitbang.sh
  pre_build_uartdpi:
    cmd:
    - sh
    - ../../../scripts/sim/compile_uart_dpi.sh
  pre_patch_modelsim_Makefile:
    cmd:
    - python
    - ../../../scripts/sim/modelsim/patch_modelsim_Makefile.py

targets:
  default: &default_target
    filesets:
    - files_rtl_generic
    toplevel: [cgra_x_heep_top]

  sim:
    <<: *default_target
    default_tool: modelsim
    filesets_append:
    - tb-harness
    - tool_verilator? (uartdpi)
    - tool_modelsim? (systemverilog_only_uart)
    - tool_vcs? (systemverilog_only_uart)
    - tool_verilator? (files_verilator_waiver)
    - tool_verilator? (remote_bitbang_dpi)
    - tool_modelsim? (systemverilog_only_simjtag)
    - tool_vcs? (systemverilog_only_simjtag)
    - tool_modelsim? (cypress_flash)
    - tool_vcs? (cypress_flash)

    - tool_modelsim? (pre_build_remote_bitbang)
    - tool_modelsim? (pre_build_uartdpi)
    - tool_modelsim? (pre_patch_modelsim_Makefile)
    - tool_vcs? (pre_build_remote_bitbang)
    - tool_vcs? (pre_build_uartdpi)
    - tool_verilator? (tb-verilator)
    - tool_modelsim? (tb-sv)
    - tool_vcs? (tb-sv)
    - "!integrated_heep? (x_heep_system)"
    toplevel:
    - tool_modelsim? (tb_top)
    - tool_vcs? (tb_top)
    - tool_verilator? (testharness)
    hooks:
      pre_build:
        - tool_modelsim? (pre_build_uartdpi)
        - tool_modelsim? (pre_build_remote_bitbang)
        - tool_modelsim? (pre_patch_modelsim_Makefile) # this is required by Questa 2020 on
    parameters:
    - COREV_PULP=0
    - use_jtag_dpi? (JTAG_DPI=1)
    - "!use_jtag_dpi? (JTAG_DPI=0)"
    tools:
      modelsim:
        vlog_options:
        - -override_timescale 1ns/1ps
        - -suppress vlog-2583
        - -suppress vlog-2577
        - -pedanticerrors
        - -define MODELSIM
        vsim_options:
        - -sv_lib ../../../hw/vendor/esl_epfl_x_heep/hw/vendor/lowrisc_opentitan/hw/dv/dpi/uartdpi/uartdpi
        - -sv_lib ../../../hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_pulpissimo/rtl/tb/remote_bitbang/librbs
      vcs:
        vcs_options:
         - -override_timescale=1ns/1ps
         - -assert disable_cover
         - -assert svaext
         - -debug_access+all
         - -fgp
         - -kdb
         - -notice
         - -ntb_opts error
         - -race=all
         - -xlrm uniq_prior_final
         - -CFLAGS "-std=c++14 -pthread"
         - -LDFLAGS "-pthread -lutil"
         - -V
      verilator:
        mode: cc
        verilator_options:
          - '--cc'
          - '--trace'
          - '--trace-fst'
          - '--trace-structs'
          - '--trace-params'
          - '--trace-max-array 1024'
          - '--x-assign unique'
          - '--x-initial unique'
          - '--exe tb_top.cpp'
          - '-CFLAGS "-std=c++11 -Wall -g -fpermissive"'
          - '-LDFLAGS "-pthread -lutil -lelf"'
          - "-Wall"

  pynq-z2:
    <<: *default_target
    default_tool: vivado
    description: TUL Pynq-Z2 Board
    filesets_append:
    - x_heep_system
    - files_rtl_generic # Already added by default? 
    - rtl-fpga
    - ip-fpga
    - xdc-fpga-pynq-z2
    parameters:
    - COREV_PULP=0
    - SYNTHESIS=true
    tools:
      vivado:
        part: xc7z020clg400-1
    toplevel: [xilinx_cgra_x_heep_wrapper]