From 4e2588c9017b19a8d002650904cbb2bdb1909ab1 Mon Sep 17 00:00:00 2001
From: Martijn Bastiaan <martijn@qbaylogic.com>
Date: Thu, 20 Feb 2025 08:42:33 +0100
Subject: [PATCH] Export UGN components, not UGN

---
 .../Bittide/Instances/Hitl/FullMeshSwCc.hs    | 50 ++++++++++++-------
 1 file changed, 32 insertions(+), 18 deletions(-)

diff --git a/bittide-instances/src/Bittide/Instances/Hitl/FullMeshSwCc.hs b/bittide-instances/src/Bittide/Instances/Hitl/FullMeshSwCc.hs
index 9fb38b063..40900f30a 100644
--- a/bittide-instances/src/Bittide/Instances/Hitl/FullMeshSwCc.hs
+++ b/bittide-instances/src/Bittide/Instances/Hitl/FullMeshSwCc.hs
@@ -255,7 +255,7 @@ fullMeshHwTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso =
   txCounters = zipWith txCounter transceivers.txClocks txResets2
   txCounter txClk txRst = result
    where
-    result = register txClk txRst enableGen (0xaabbccddeeff1234 :: BitVector 64) (result + 1)
+    result = register txClk txRst enableGen (0x0 :: BitVector 64) (result + 1)
   -- see NOTE [magic start values]
 
   -- rxFifos :: Vec LinkCount (_, _, _, _, _Signal GthRx (Maybe (BitVector 64)))
@@ -277,10 +277,10 @@ fullMeshHwTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso =
   fifoUnderflowsFree :: Vec LinkCount (Signal Basic125 Underflow)
   fifoUnderflowsFree = zipWith (flip xpmCdcSingle sysClk) transceivers.txClocks fifoUnderflowsTx
 
-  ugns :: Vec LinkCount (Signal GthTx (BitVector 64))
+  ugns :: Vec LinkCount (Signal GthTx (BitVector 64, BitVector 64))
   ugns =
     zipWith
-      (-)
+      (liftA2 (,))
       txCounters
       (map (fmap (fromMaybe 0x1122334411223344)) rxCntrs)
   -- see NOTE [magic start values]
@@ -302,7 +302,7 @@ fullMeshHwTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso =
         clkOut
         noReset
         enableGen
-        (0, 0, False, unpack 0)
+        ((0,0), 0, False, unpack 0)
         (xpmCdcMaybeLossy clkIn clkOut inp)
      where
       fillStat = fillStats clkIn noReset fillLvl
@@ -394,13 +394,20 @@ fullMeshHwTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso =
             :> "probe_nFincs"
             :> "probe_nFdecs"
             :> "probe_net_nFincs"
-            :> "probe_ugn0"
-            :> "probe_ugn1"
-            :> "probe_ugn2"
-            :> "probe_ugn3"
-            :> "probe_ugn4"
-            :> "probe_ugn5"
-            :> "probe_ugn6"
+            :> "probe_tx_ugn0"
+            :> "probe_tx_ugn1"
+            :> "probe_tx_ugn2"
+            :> "probe_tx_ugn3"
+            :> "probe_tx_ugn4"
+            :> "probe_tx_ugn5"
+            :> "probe_tx_ugn6"
+            :> "probe_rx_ugn0"
+            :> "probe_rx_ugn1"
+            :> "probe_rx_ugn2"
+            :> "probe_rx_ugn3"
+            :> "probe_rx_ugn4"
+            :> "probe_rx_ugn5"
+            :> "probe_rx_ugn6"
             :> "probe_fill0"
             :> "probe_fill2"
             :> "probe_fill1"
@@ -456,13 +463,20 @@ fullMeshHwTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso =
         nFincs
         nFdecs
         (fmap unsignedToSigned nFincs - fmap unsignedToSigned nFdecs)
-        ugn0
-        ugn1
-        ugn2
-        ugn3
-        ugn4
-        ugn5
-        ugn6
+        (fst <$> ugn0)
+        (fst <$> ugn1)
+        (fst <$> ugn2)
+        (fst <$> ugn3)
+        (fst <$> ugn4)
+        (fst <$> ugn5)
+        (fst <$> ugn6)
+        (snd <$> ugn0)
+        (snd <$> ugn1)
+        (snd <$> ugn2)
+        (snd <$> ugn3)
+        (snd <$> ugn4)
+        (snd <$> ugn5)
+        (snd <$> ugn6)
         fill0
         fill1
         fill2