From 79be45dd22b393cdda6ed5919e4a9c95968499f3 Mon Sep 17 00:00:00 2001 From: Simone Ballard Date: Mon, 12 Apr 2021 21:19:28 -0600 Subject: [PATCH 1/4] initial look around --- ls8/cpu.py | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/ls8/cpu.py b/ls8/cpu.py index 9a307496e..c0373d28d 100644 --- a/ls8/cpu.py +++ b/ls8/cpu.py @@ -1,13 +1,14 @@ """CPU functionality.""" - +# import sys class CPU: """Main CPU class.""" def __init__(self): - """Construct a new CPU.""" - pass + self.registers = [0] * 8 + self.somethingelse = [0] * 256 + self.pc = 0 def load(self): """Load a program into memory.""" @@ -30,6 +31,15 @@ def load(self): self.ram[address] = instruction address += 1 + def ram_read(self, address): + for value in address: + self.ram[address.value] = value + return value + + def ram_write(newvalue, address): + for value in address: + value.replace(value, newvalue) + return value def alu(self, op, reg_a, reg_b): """ALU operations.""" @@ -61,5 +71,8 @@ def trace(self): print() def run(self): + running = True """Run the CPU.""" - pass + IR = self.ram[pc] + operand_a = self.ram[pc + 1] + operand_b = self.ram[pc + 2] \ No newline at end of file From 552ae6bdff55fbcd5b06d8fe023aa416c8a64de7 Mon Sep 17 00:00:00 2001 From: Simone Ballard Date: Mon, 12 Apr 2021 22:25:55 -0600 Subject: [PATCH 2/4] what I have so far w/o additional notes --- ls8/cpu.py | 47 +++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 41 insertions(+), 6 deletions(-) diff --git a/ls8/cpu.py b/ls8/cpu.py index c0373d28d..c650d9be7 100644 --- a/ls8/cpu.py +++ b/ls8/cpu.py @@ -2,13 +2,20 @@ # import sys +#instruction set: +HLT = 0 +LDI = 0, 8 +PRN = 0 + class CPU: """Main CPU class.""" def __init__(self): self.registers = [0] * 8 - self.somethingelse = [0] * 256 + self.ram = [0] * 256 self.pc = 0 +#not really sure where to put this + running = True def load(self): """Load a program into memory.""" @@ -70,9 +77,37 @@ def trace(self): print() - def run(self): - running = True - """Run the CPU.""" - IR = self.ram[pc] +#From the spec: +#When the LS-8 is booted, the following steps occur: + +#R0-R6 are cleared to 0. +#R7 is set to 0xF4. +#PC and FL registers are cleared to 0. +#RAM is cleared to 0. +#Subsequently, the program can be loaded into RAM starting at address 0x00. + + def run(self, pc): + instruction = self.ram[pc] operand_a = self.ram[pc + 1] - operand_b = self.ram[pc + 2] \ No newline at end of file + operand_b = self.ram[pc + 2] +#potential structure for LDI + if instruction == LDI: + reg_index = operand_a + num = operand_b + num = int(self.registers[reg_index]) + print(num) + pc += 3 +#potential structure for PRN + elif instruction == PRN: + reg_index = operand_a + num = self.registers[reg_index] + print(num) + pc += 2 +#potential structure for HLT + elif instruction == HLT: + running = False + sys.exit(0) + + else: + print("WRONG WAY") + sys.exit(1) \ No newline at end of file From 481a7d428fc141842239a23413ecb4c28eccea4d Mon Sep 17 00:00:00 2001 From: Simone Ballard Date: Wed, 14 Apr 2021 16:14:35 -0600 Subject: [PATCH 3/4] added file loader --- ls8/cpu.py | 110 ++++++++++++++++++++++++++--------------------------- 1 file changed, 53 insertions(+), 57 deletions(-) diff --git a/ls8/cpu.py b/ls8/cpu.py index c650d9be7..cd5ecaf80 100644 --- a/ls8/cpu.py +++ b/ls8/cpu.py @@ -3,9 +3,9 @@ import sys #instruction set: -HLT = 0 -LDI = 0, 8 -PRN = 0 +HLT = 0b00000001 +LDI = 0b10000010 +PRN = 0b01000111 class CPU: """Main CPU class.""" @@ -14,39 +14,34 @@ def __init__(self): self.registers = [0] * 8 self.ram = [0] * 256 self.pc = 0 -#not really sure where to put this - running = True + +#originally this part is `hardcoded` and needs the parser instead - def load(self): + def load(self, filename): """Load a program into memory.""" - - address = 0 - - # For now, we've just hardcoded a program: - - program = [ - # From print8.ls8 - 0b10000010, # LDI R0,8 - 0b00000000, - 0b00001000, - 0b01000111, # PRN R0 - 0b00000000, - 0b00000001, # HLT - ] - - for instruction in program: - self.ram[address] = instruction - address += 1 - + try: + address = 0 #constant ram address + with open(filename) as f: + for line in f: + comment_split = line.split("#") + num = comment_split[0].strip() + if num == '': + continue + + ram[address] = int(num) + address += 1 + + except FileNotFoundError: + print("file not found") + sys.exit(2) + + load(filename) + def ram_read(self, address): - for value in address: - self.ram[address.value] = value - return value + return self.ram[address] - def ram_write(newvalue, address): - for value in address: - value.replace(value, newvalue) - return value + def ram_write(self, newvalue, address): + self.ram[address] = newvalue def alu(self, op, reg_a, reg_b): """ALU operations.""" @@ -86,28 +81,29 @@ def trace(self): #RAM is cleared to 0. #Subsequently, the program can be loaded into RAM starting at address 0x00. - def run(self, pc): - instruction = self.ram[pc] - operand_a = self.ram[pc + 1] - operand_b = self.ram[pc + 2] -#potential structure for LDI - if instruction == LDI: - reg_index = operand_a - num = operand_b - num = int(self.registers[reg_index]) - print(num) - pc += 3 -#potential structure for PRN - elif instruction == PRN: - reg_index = operand_a - num = self.registers[reg_index] - print(num) - pc += 2 -#potential structure for HLT - elif instruction == HLT: - running = False - sys.exit(0) - - else: - print("WRONG WAY") - sys.exit(1) \ No newline at end of file + def run(self): + running = True + while running: + instruction = self.ram[self.pc] + operand_a = self.ram[self.pc + 1] + operand_b = self.ram[self.pc + 2] +# LDI + if instruction == LDI: + reg_index = operand_a + num = operand_b + self.registers[reg_index] = num + self.pc += 3 +# PRN + elif instruction == PRN: + reg_index = operand_a + num = self.registers[reg_index] + print(num) + self.pc += 2 +# HLT + elif instruction == HLT: + running = False + sys.exit(0) + + else: + print("WRONG WAY") + sys.exit(1) \ No newline at end of file From 17ab9a8f6f4436c8f0d5a4b53431ee3ffda76a91 Mon Sep 17 00:00:00 2001 From: Simone Ballard Date: Wed, 14 Apr 2021 17:01:14 -0600 Subject: [PATCH 4/4] MUL added --- ls8/cpu.py | 38 +++++++++++++++++++++++--------------- ls8/ls8.py | 15 ++++++++++++++- 2 files changed, 37 insertions(+), 16 deletions(-) diff --git a/ls8/cpu.py b/ls8/cpu.py index cd5ecaf80..66eb431cb 100644 --- a/ls8/cpu.py +++ b/ls8/cpu.py @@ -6,6 +6,7 @@ HLT = 0b00000001 LDI = 0b10000010 PRN = 0b01000111 +MUL = 0b10100010 class CPU: """Main CPU class.""" @@ -14,22 +15,22 @@ def __init__(self): self.registers = [0] * 8 self.ram = [0] * 256 self.pc = 0 - + #originally this part is `hardcoded` and needs the parser instead def load(self, filename): """Load a program into memory.""" - try: - address = 0 #constant ram address - with open(filename) as f: - for line in f: - comment_split = line.split("#") - num = comment_split[0].strip() - if num == '': - continue - - ram[address] = int(num) - address += 1 + try: + address = 0 #constant ram address + with open(filename) as f: + for line in f: + comment_split = line.split("#") + num = comment_split[0].strip() + if num == '': + continue + + ram[address] = int(num) + address += 1 except FileNotFoundError: print("file not found") @@ -48,9 +49,11 @@ def alu(self, op, reg_a, reg_b): if op == "ADD": self.reg[reg_a] += self.reg[reg_b] - #elif op == "SUB": etc - else: - raise Exception("Unsupported ALU operation") + self.pc += 3 + elif op == "MUL": + self.reg[reg_a] *= self.reg[reg_b] + self.pc += 3 + print() def trace(self): """ @@ -99,6 +102,11 @@ def run(self): num = self.registers[reg_index] print(num) self.pc += 2 +#MUL + elif instruction == MUL: + reg_index = operand_a + reg_index = operand_b + alu("MUL", self.reg_a, self.reg_b) # HLT elif instruction == HLT: running = False diff --git a/ls8/ls8.py b/ls8/ls8.py index 74128d36b..3acd2633c 100755 --- a/ls8/ls8.py +++ b/ls8/ls8.py @@ -5,7 +5,20 @@ import sys from cpu import * +if len(sys.argv) != 2: + print("Usage: python3 fileio.py ") + sys.exit(1) + +try: + with open(sys.argv[1]) as f: + for line in f: + print(int(line)) + +except FileNotFoundError: + print("file not found") + sys.exit(2) + cpu = CPU() -cpu.load() +cpu.load(filename) cpu.run() \ No newline at end of file