- About This Repository
- Lab #A - UG871
- Lab #A - Vitis Tutorials
- Lab #B - PP4 FPGAs
- Lab #C - Vitis Libraries
- Final Projects
- References
This repository is a collection of students' labs and final projects from the course "Application Acceleration with High-Level Synthesis" taught in the Graduate Institute of Electrical Engineering, National Tsing Hua University.
Files in this repository are snapshots of their original repositories at the end of the semester, in case the original links are failed.
See the tables below for the links to their original repositories.
Note: Platforms used by these projects include TUL PYNQ-Z2 and Xilinx Alveo U50.
For Lab #A, students practiced the labs in UG871 [1] and tried to analyze the designs or improve them.
| Topics | Students (Links) |
|---|---|
| Interface Synthesis | 賴聖耘 |
| Design Analysis | 羅允辰 |
| Design Optimization | 許鏡瑋 |
| Using HLS IP in IP Integrator | 周沛毅 |
| Using HLS IP in Zynq SoC Design | 郭柏辰 |
For Lab #A, students practiced the labs in Vitis-Tutorials [2] and tried to analyze the designs or improve them.
| Topics (Links to folders in Xilinx official repository) | Students (Links) |
|---|---|
| Vitis | 馬婕芸 |
| Mixing C++ and RTL Kernels | 徐宜婕 |
| Vitis HLS Analysis and Optimization | 陳成彬 |
| Host Memory Access | 林彥岑 |
| streaming_free_running_k2k | 徐浩庭 |
| loop_reorder | 王睿瑄 |
| systolic_array | 李冠霈 |
| Cholesky Algorithm | 呂政和 |
| Bloom Filter | 林致佑 |
| Convolution Filtering | 呂易縉 |
For Lab #B, students practiced the labs in pp4 fpgas [3] and tried to analyze the designs or improve them.
| Topics | Students (Links) |
|---|---|
| CORDIC | 陳思熙 |
| DFT | 鄧向凱 |
| Matrix Multiplication | 鍾宇騫 |
| Prefix Sum and Histogram | 江威霖 |
| Video System | 呂依凡 |
| Sorting Algorithm | 吳秉豐 |
For Lab #C, students tried out the Vitis Libraries [4] and used them to build an end-to-end application acceleration.
| Topics (Links) | Students |
|---|---|
| Vitis BLAS Library | 呂政和、林致佑、 鄧向凱 |
| Vitis Data Analytics Library | 呂易縉、馬婕芸、 賴聖耘 |
| Vitis Data Compression Library | 鍾宇騫、許鏡瑋 |
| Vitis DSP Library | 周沛毅、徐宜婕、陳成彬 |
| Vitis CODEC Library | 陳思熙、吳秉豐、江威霖 |
| Vitis HPC Library | 郭柏辰 |
| Vitis Quantitative Finance Library | 呂依凡、林彥岑、徐浩庭 |
| Vitis Vision Library | 羅允辰、李冠霈、王睿瑄 |
| Topics (Links) | Students |
|---|---|
| Image Captioner | 呂政和、林致佑、 鄧向凱 |
| Spike Sorting Acceleration Beamforming Acceleration | 呂易縉、馬婕芸、 賴聖耘 |
| 2D Mesh Interconnection Network on Chip | 鍾宇騫、許鏡瑋 |
| OFDM Implemented by HLS | 周沛毅、徐宜婕、陳成彬 |
| Wireless Communication System with Encryption | 陳思熙、吳秉豐、江威霖 |
| Face Detection | 郭柏辰、林彥岑、徐浩庭 |
| Monte Carlo Financial Models on U50 | 呂依凡 |
| Scalable Matrix Multiplication Accelerator | 羅允辰、李冠霈、王睿瑄 |
[1] Xilinx UG871 - Vivado Design Suite Tutorial: High-Level Synthesis
[2] Xilinx Vitis-Tutorials (https://github.com/Xilinx/Vitis-Tutorials)
[3] PP4 FPGAs (https://github.com/KastnerRG/pp4fpgas/tree/master/examples)
[4] Xilinx Vitis Libraries (https://github.com/Xilinx/Vitis_Libraries)