Discusson on Final Project

[boledulab]

We will use this thread of discussion for final project issues
Refer to the attached, I have put few notes about final project.
final-project-note.pptx

In order not to have memory data access become a bottleneck, pipeline memory is needed. I have draft a exmem_pipeline specification to replace Lab4-1 exmem design. A sample design strucure is attachd here (Note: I simply write the code for the purpose to express the design structure, there is no syntax check nor simulation verification.
https://github.com/bol-edu/caravel-soc_fpga-lab/blob/main/lab-wlos_baseline/exmem_pipeline.v

[vic9112]

Attach is the RTL code of pipeline_exmem design, which have finished simulation and fixed syntax error.

`default_nettype wire

module exmem_pipeline #(
    parameter N = 10
)(
    input         clk,
    input         rst,		// active high (from WB)
    input         stb,		// command strobe -request
    input         we,		// 1: write, 0: read
    input  [3:0]  sel,		// byte-enable
    input  [31:0] dat_i,	// data in
    input  [31:0] addr,		// address in
	
    output        ack,		// ready
    output [31:0] dat_o	    	// data out
    );

    // FIFO for shifting WB request
    reg   [67:0] req_fifo[N-1:0];
    reg  [N-1:0] we_fifo;
    reg  [N-1:0] valid_fifo;
    reg          ack;
    
    // Wishbone INPUT request
    wire  [67:0] req_in;
    
    // BRAM byte enable
    wire   [3:0] byte_en;

    `define SEL_POS 3:0
    `define DAT_POS 35:4
    `define ADR_POS 67:36
    `define N       10
    
    // Initalize FIFO, and perform Shift FIFO
    always @(posedge clk or posedge rst) begin
        if (rst) begin
	       valid_fifo <= `N'b0;
	       we_fifo    <= `N'b0;
        end
        else begin
           valid_fifo <= {stb, valid_fifo[N-1:1]};
           we_fifo    <= {we, we_fifo[N-1:1]};
        end
    end
    
    assign req_in = {addr, dat_i, sel};
    
    // Put Wishbone input request into FIFO
    always @(posedge clk) begin
        req_fifo[N-1] <= req_in;
    end
    
    // Shift the FIFO
    integer i;
    // Unroll to N-2, since the FIFO[N-1] has been assign to input request
    always @(posedge clk) begin
        for (i = 0; i < N-2; i = i + 1) begin         
            req_fifo[i] <= req_fifo[i + 1];
        end
    end
    
    // ACK signal is generated 1T after valid_fifo[0] = 1,
    // because BRAM read access takes 1T module bram
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            ack <= 0;
        end
        else begin
            ack <= valid_fifo[0];
        end
    end

    assign byte_en = req_fifo[0][`SEL_POS] & {4{we_fifo[0]}};
    
    bram user_bram (
        .CLK (clk),
        .WE0 (byte_en),
        .EN0 (valid_fifo[0]),
        .Di0 (req_fifo[0][`DAT_POS]),
        .Do0 (dat_o),
        .A0  (req_fifo[0][`ADR_POS])
    );

endmodule

[boledulab]

The dataset for matmul, qsort, and fir are initialized and preloaded into user memory. It needs to change the linker commands script. Those who have made it work, please share it for others to reference.

[long385552]

以counter_la_mm舉例，如果想讓A matrix、B matrix存入mprjram，要分別去firmware資料夾的link_ibex.id和sections.ids把.data(for initialized data)預設dff改至mprjram。

效果如下：

但這樣改到mprjram，我們run_sim會遇到一個問題，目前不知道怎麼解決。

問題如下：存在mprjram時不知道是不是因為cpu要去exmemfir取instruction，然後又要再去exmemfir取A的值，所以導致cpu instruction呈現xxxxxxx的狀況。（左圖是dff，右圖是mprjram）

[boledulab]

@long385552 Can you provide related link files and output assembly code? The data address and instruction address are different. It should not conflict. Also, please check the process of moving instructions and data from spiflash to user memory. It shall give you a better idea of where the problem is.

[jxes993409]

linker的部分我們只有調整sections.lds而已，將.bss跟.data放入all_data中

另外.text section裡的 *(.text .stub .text.* .gnu.linkonce.t.*) 會將gcclib乘法<__mulsi3>放到裡面，導致會花費大量時間存取該function

所以我們照lab-6的sections.lds修改，將 *libgcc.a:*(.text .text.*) 放入mprjram中，可以大幅縮短執行時間

[long385552]

老師好，參考@jxes993409的調整後，目前狀況已解決，謝謝這位同學！

[boledulab]

Encourage two teams collaboratively work on final project.
Due to the amount of effort to optimize the four workload (matmul, qsort, fir, uart), and its memory subsystem. we encourage two teams work together to improve the whole system.

1. Limit on two teams
2. Clearly identify which team does what.
3. Each team presents his part of work
4. For example:
   One team works on accelerator for matmul, qsort, fir
   One team work on memory subsystem and UART FIFO, e.g. Pipeline SDRAM.

[boledulab]

Debugging Procedure for data moved to user memory.
In existing loader setting, the globle data initialized/uninitialized data are in DFF. The DMA designed for accelerators can not access DFF. Thus, we need to move data to user memory. It involves two changes, one is change the loader settings. Another is to move data to user memory. The following is the debugging procedures

1. write verilog code to display messages to a log file
   • all read/write transaction on WB bus including we, wb_addr, and wb_data-in, wb_data_out
   • all the read/writ access to user memory bram
2. Study the assembly code to identify the following address range

• instruction address range
• address range for each data buffer used in the program, e.g. Q array for qsort, A, B, C matrix, FIR input/output buffer
  => if the address range is not in user memory (3800_xxxx), check loader script section.lds

3. Observe the following operation in log file

• instruction is moved from spiflash rom (1000xxxx) to 3800xxxx
• Each data buffer is filled with data into user memory region, check the written data is correct - if not, check Start.s

4. If the data is written correctly when first moved to user memory, but later read incorrectly, the user memory implementation has problem. It is unlikely because the design is proven.

Good luck and share your findings.

[boledulab]

@long385552 you may need to check if the data is copied from spiflash and written to user memory in start-up code.