Final project 是否需要合成 #190
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junshiuanhsieh
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Final project 是否需要合成
#190
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另外 想請問是否能自行新增新的sram，然後delay是否會有限制 |
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同學你好 請同學用這個thread統一針對final project的spec討論。感謝 |
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@junshiuanhsieh lab-sdram 是可以合成在 FPGA 上跑。台大 TA 可以 Comment。 |
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@junshiuanhsieh 同學你好，lab-sdram是使用FPGA的BRAM當作SDRAM的bank，所以是可以合成的 |
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由於final project 規定要使用SDRAM，但lab-sdram是不能合成的，所以想請問final project 是只需要做 rtl simulation 嗎
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