在Jupyter上驗證功能的方法

[Fossum2523]

要如何在Jupyter上測試MM、QS、FIR的輸出資料是否正確呢?

因為在收取online FPGA回傳到Jupyter的資料時會發現很容易掉包，我猜測是因為計算的速度很快，所以Jupyter端去fetch值得時候資料早就換了。

我們在先前Lab 6當中測試功能的時候在每筆資料的輸出後加上延遲，使得Jupyter端可以fetch到資料，如下圖。

但是老師有提到過這算是偷吃步，故想來請教各位是如何驗證的呢?

目前想到的方法是先由Jupyter端打一個要收資料的訊號過去，FPGA收到後再將資料回傳回來，但這方法我一直嘗試不出來。

[billy900812]

我也有想嘗試你的這個方法，但我去看了GPIO的相關資料好像是做不到，如下圖給你參考

[boledulab]

When Caravel SOC is integrated in FPGA, its bidirectional mprj pins are separated into input, output, and output enable signals (figure below) which can be read/write by PS. Refer to the caravel_ps HLS code below. Unlike the bidirectional pin in real chip, it has separate and independent input and output signals. It can be used for Firmware and PS communication.
Firmware can read write mprj registers, and PS can read / write the axilite registers. You may use this to do lock-step operations between firmware and PS. i.e.

1. firmware waits for PS to send a message, then starts computation
2. After the computation is done, send the result back to PS
3. PS read the result, then send a message to the firmware.
4. Repeat 1-3.

Refer to the following for Caravel_PS HLS code. The mprj_in, mprj_out
https://github.com/bol-edu/caravel-soc_fpga-lab/blob/main/labi/vitis_hls_project/hls_caravel_ps/src/caravel_ps.cpp

[CatKingWoof]

老師您好，請問final project有需要驗證workload計算的每個結果是否正確嗎?

[boledulab]

需要！