LAB#C codec library:run makefile fail and run L1 cosim fail

[s095339]

Hello, we are 張耀明 and 陳佳詳, we are students from nthu.
We have been doing Lab-C, Codec vitis library, using the U50_04.
We encountered Two problems：

1. Fail to run jpegdec L1-API cosim.
   We did the following operations before running cosim
   first I configured the environment

cd /Vitis_Libraries/codec/L1/tests/jpegdec
source "/opt/Xilinx/Vitis_HLS/2022.1/settings64.sh"
source "/opt/Xilinx/Vitis/2022.1/settings64.sh"
source "/opt/xilinx/xrt/setup.sh"
export PLATFORM_REPO_PATHS="/opt/xilinx/platforms/xilinx_u50_gen3x16_xdma_5_202210_1/xilinx_u50_gen3x16_xdma_5_202210_1.xpfm"
export DEVICE= xilinx_u50_gen3x16_xdma_5_202210_1
export TARGET=sw_emu

Then I ran the Csim Csynth Cosim

#Csim
make run DEVICE=xilinx_u50_gen3x16_xdma_5_202210_1  CSIM=1
#Csyn
make run DEVICE=xilinx_u50_gen3x16_xdma_5_202210_1  CSYNTH=1
#Cosim
make run DEVICE=xilinx_u50_gen3x16_xdma_5_202210_1  COSIM=1

the Csim and Csyn can work with no error message, but we failed to run Cosim.
Here is the log file generated after running the Cosim.

vitis_hls.log

2. Fail to compile jpegdec L2-api host program

cd /Vitis_Libraries/codec/L2/demos/jpegDec
source "/opt/Xilinx/Vitis_HLS/2022.1/settings64.sh"
source "/opt/Xilinx/Vitis/2022.1/settings64.sh"
make clean
source "/opt/xilinx/xrt/setup.sh"
export PLATFORM_REPO_PATHS="/opt/xilinx/platforms/"
export TARGET=sw_emu
export DEVICE= xilinx_u50_gen3x16_xdma_5_202210_1
make host

it says "cannot find Ip_floating_point_v7_1_bitacc_cmodel" .

I comment it out in the makefile so that the "make host" can be run with no error.

Then I run
make run

Everything looks fine, the .yuv can be successfully generated.

But I am not sure if the result is generated with no problem.
the .yuv image:

[boledulab]

Hi,
The first problem was known offical issue, https://support.xilinx.com/s/article/Use-of-gmp-h-for-Co-simulation
The problem was fixed by (only) adminstrator.
change in /opt/Xilinx/Vitis_HLS/2022.1/include/mpfr.h

//#ifndef __GMP_H__
#include <gmp.h>
#define __gmp_const const
//#endif

co-sim log
offical doc: https://docs.xilinx.com/r/jpiLUWqYENGWAj4YktN~YQ/~8rb6JHOcKsEZ2KdYnULmA

[s095339]

Thanks, I can run it successfully

[boledulab]

For second problem, I successfully run "make host" && "make run" without any change.
Maybe it was fixed by corrected gmp.h issue.

make host && make run log

[s095339]

Sorry, we still can't run due to the same problem.

[kevinjantw]

I passed "make host" && "make run" because I used your test code already removing "-lIp_floating_point_v7_1_bitacc_cmodel".
https://github.com/bol-edu/HLS-Discussions/files/11301085/make-host_make-run.log
In order to resolve second problem you need to setup library from Vivado IDE, please refer the doc chapter 5.
https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/floating_point/v7_1/pg060-floating-point.pdf

From chapter 5@Floating-Point Operator v7.1 LogiCORE IP Product Guide:
The Xilinx® LogiCORE ™ IP Floating-Point Operator core bit accurate C model is a
self-contained, linkable, shared library that models the functionality of this core with finite
precision arithmetic. This model provides a bit accurate representation of the various
modes of the Floating-Point Operator v7.1 core, and it is suitable for inclusion in a larger
framework for system-level simulation or core-specific verification.

The C model is an optional output of the Vivado® Design Suite. For information about
generating IP source outputs, see Vivado Design Suite User Guide: Using the Vivado IDE
(UG893)

[s095339]

Sorry for the delay,
I've check the doc chapter 5.
In the doc, it says:

But I can't find where these .so files are located

[kevinjantw]

Hi,
According 'The C model is an optional output of the Vivado® Design Suite', maybe you can generate C model (*.so) from Vivado.
You can explore Xilinx LogiCORE IP design flow from Xilinx community posts.