- Fill in the form to get future information of Caravel SoC FPGA and FSIC program
- Access BOLEDU online lab facilities (FPGA boards)
Boledu proposed a Caravel SoC FPGA validation platform which was ported from Efabless Caravel harness SoC project (Google Open Source Silicon) and could be ran on Xilinx PYNQ-Z2 FPGA board.
The Boledu Caravel SoC (MPW8-C code base) was removed all SKY PDK dependencies to provide quickly logic simulation for development. Two software debugging enhances were proposed and implemented. Firstly, an open source GDBWave was integrated into Caravel SoC design flow. The GDBWave parses the waveform after RTL simulation to manipulate GDB debugging with VexRiscv CPU. Secondly, a proposed Riscv-Tracer was helped to translate waveform display to RISC-V instructions representation.
The Boledu Caravel SoC FPGA was ported from Caravel SoC with a little SoC system revisions. Caravel users can quickly prototype their user project design on Xilinx FPGA board. The Xilinx Vitis provides Xilinx Vivado Simulator (XSIM) and Xiliinx Vivado hardware block design tool for Caravel SoC FPGA bitstream generation. Finally, Caravel users can continue to validate their design on Boledu online FPGA board with Jupyter Notebook testbench.
To emulate the Efabless Caravel harness SoC simulation environment, we implemented 4 simple designs as in the figure below.
- ResetControl: A memory-mapped-io to control Caravel reset pin.
- read_romcode: read the firmware hex data from PS/DDR memory to FPGA BRAM.
- spiflash: It emulates spiflash device read behavior. It reads data from BRAM.
- caravel_ps: It allows the PS side to use memory-mapped IO to read/write mprj pins.
The Caravel Verilog testbench code can be easily translated to Jupyter Notebook Python testbench code as illustrated in caravel_fpga.ipynb
Any question/idea of Caravel SoC FPGA can be posted in Discussions.
Acknowledgement for Project:
Patrick Lin/patrick-lin-git, Willy Chiang, Tony Ho, Allen Chang, Ian Liu, Bow Chao
Video Demonstration on Youtube
- Ubuntu 20.04+
- Xilinx Vitis 2022.1 (builtin XSIM and Vivado)
- RISC-V GCC Toolchains rv32i-4.0.0
- GTKWave v3.3.103
├── firmware # caravel firmware libraries
├── rtl # caravel rtl designs
│ ├── header # headers
│ ├── soc-efabless # efabless caravel soc
│ ├── soc # boledu revised caravel soc
│ ├── user # user project designs
├── testbench # caravel testbenches
│ ├── counter_la # counter with logic analyzer interface
│ ├── counter_wb # counter with wishbone interface
│ └── gcd_la # gcd with logic analyzer interface
├── vip # caravel verification ip
└── vivado # boledu caravel soc fpga
- Prepare a Xilinx Vitis on Ubuntu Machine
- Setup RISC-V GCC Toolchains and GTKWave
- Git Clone Caravel SoC FPGA
- Run Xilinx Vivado Simulation of Caravel SoC FPGA
- Generate Caravel SoC FPGA Bitstream from Xilinx Vivado
- Test Caravel User Project Design on FPGA Board with Jupyter Notebook
- Appendix: Revision History from Efabless Caravel harness SoC to Caravel SoC FPGA
- Appendix: Boledu Vitis Machine
- Appendix: AWS EC2 Vitis Subscription
- Appendix: Reference Documents
If you want to experience FPGA board validation with prebuilt Caravel counter user project FPGA bitstream and Jupyter Notebook testbench, you can hand-on the last FPGA validation step.
The Xilinx Vitis needs minimum 32 GB system memory (64 GB is recommended). You can in-house setup Vitis on your Ubuntu machine or apply a ready for using Vitis machine from Boledu (free) / AWS EC2 (charge).
In-house setup (deploying with hours)
- The Xilinx Vitis 2022.1 requires roughly 200 GB of disk space to install
- Install necessary dependencies before Vitis installation:
sudo apt install libtinfo5 libncurses5 build-essential -y
- Offical installation guide: https://docs.xilinx.com/r/2022.1-English/ug1400-vitis-embedded/Installation-Requirements
- Add below line to
/home/<user>/.bashrc
after completing Vitis installation
source <Vitis_install_path>/Xilinx/Vitis/2022.1/settings64.sh
Boledu (no deploying)
Boledu lab provides facilities of Vitis machine and PYNQ-Z2 board (limited users)
AWS EC2 Vitis subscription (deploying within minutes but charge)
The detailed subscription diagrams flow are described in Appendix.
$ sudo apt update
$ sudo apt install gtkwave -y
$ sudo wget -O /tmp/riscv32-unknown-elf.gcc-12.1.0.tar.gz https://github.com/stnolting/riscv-gcc-prebuilt/releases/download/rv32i-4.0.0/riscv32-unknown-elf.gcc-12.1.0.tar.gz
$ sudo mkdir /opt/riscv
$ sudo tar -xzf /tmp/riscv32-unknown-elf.gcc-12.1.0.tar.gz -C /opt/riscv
$ echo 'export PATH=$PATH:/opt/riscv/bin' >> ~/.bashrc
$ source ~/.bashrc
$ sudo apt install git -y
$ git clone https://github.com/bol-edu/caravel-soc_fpga ~/caravel-soc_fpga
Caravel users can develop their own user project design integrated with Caraver SoC FPGA and use Xilinx Vivado simulator (XSIM) to validate design's behavior. For counter_la design example, you can find a design file path ../../rtl/user/user_proj_example.counter.v
was listed within include.rtl.list.xsim
. You can change the design file path to your new user project design location, then rewrite reference RISC-V firmware counter_la.c
and Verilog testbench counter_la_tb.v
to test your new user project design. The shell script commands of run_xsim
are also needed to align your rewritten firmware and testbench files which were used in new user project design.
The compiled RISC-V firmwares counter_la.hex, counter_wb.hex and gcd_la.hex were generated while exeuting their run_xsim
. They were separately used by testbenches counter_la_tb.v, counter_wb_tb.v and gcd_la_tb.v. The compiled RISC-V firmwares also can be reused by later Jupyter Notebook testbench running on FPGA board.
- Counter with (LA) logic analyzer interface
Files of counter_la for running Xilinx XSIM:
caravel-soc_fpga/testbench/counter_la/counter_la.c
caravel-soc_fpga/testbench/counter_la/counter_la_tb.v
caravel-soc_fpga/testbench/counter_la/include.rtl.list.xsim
caravel-soc_fpga/testbench/counter_la/run_xsim
Use GTKWave to view simulated counter_la waveform
$ cd ~/caravel-soc_fpga/testbench/counter_la/
$ ./run_xsim
$ gtkwave waveform.gtkw
Detailed counter_la.log of run_xsim
- Counter with (WB) wishbone interface
Files of counter_wb for running Xilinx XSIM:
caravel-soc_fpga/testbench/counter_wb/counter_wb.c
caravel-soc_fpga/testbench/counter_wb/counter_wb_tb.v
caravel-soc_fpga/testbench/counter_wb/include.rtl.list.xsim
caravel-soc_fpga/testbench/counter_wb/run_xsim
Use GTKWave to view simulated counter_wb waveform
$ cd ~/caravel-soc_fpga/testbench/counter_wb/
$ ./run_xsim
$ gtkwave waveform.gtkw
Detailed counter_wb.log of run_xsim
- GCD with (LA) logic analyzer interface
Files of gcd_la for running Xilinx XSIM:
caravel-soc_fpga/testbench/gcd_la/gcd_la.c
caravel-soc_fpga/testbench/gcd_la/gcd_la_tb.v
caravel-soc_fpga/testbench/gcd_la/include.rtl.list.xsim
caravel-soc_fpga/testbench/gcd_la/run_xsim
Use GTKWave to view simulated gcd_la waveform
$ cd ~/caravel-soc_fpga/testbench/gcd_la/
$ ./run_xsim
$ gtkwave waveform.gtkw
Detailed gcd_la.log of run_xsim
After design validation through Vivado simulation, Caraver SoC FPGA and its integrated user project design can be synthesized to FPGA bitstream and continue to be validated on PYNQ-Z2 board with Jupyter Notebook testbench. Before running Xilinx Vivado synthesis , you need to setup PYNQ-Z2 board files.
- In-house Environment
$ sudo wget -O /tmp/pynq-z2.zip https://dpoauwgwqsy2x.cloudfront.net/Download/pynq-z2.zip
$ sudo unzip /tmp/pynq-z2.zip -d <Vitis_install_path>/Xilinx/Vivado/2022.1/data/boards/board_files/
- Boledu Environment
The PYNQ-Z2 board files are already set.
- AWS EC2 Vitis Environment
$ sudo wget -O /tmp/pynq-z2.zip https://dpoauwgwqsy2x.cloudfront.net/Download/pynq-z2.zip
$ sudo unzip /tmp/pynq-z2.zip -d /tools/Xilinx/Vivado/2022.1/data/boards/board_files/
The run_vivado
shell script will build up whole Xilinx Vivado project and generate default Caravel counter user project FPGA bitstream.
$ cd ~/caravel-soc_fpga/vivado
$ ./run_vivado
After finishing run_vivado
, you can see below messages and find generated vivado.log
and timing_report.log
. You also need to check is there any timing violation existence inside timing_report.log
. Default run_vivado
invokes vvd_caravel_fpga_10mhz.tcl
to target 10MHz FPGA synthesis. If you have timing issue or invalid FPGA test result, you can try to tune user project design architecture or change run_vivado
to invoke vvd_caravel_fpga_1mhz.tcl
to target 1MHz FPGA synthesis.
open_run: Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 3493.906 ; gain = 264.785 ; free physical = 56823 ; free virtual = 62238
# report_timing_summary -file timing_report.log
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# exit
INFO: [Common 17-206] Exiting Vivado at Tue May 23 17:31:47 2023...
======================================================================
vivado complete
======================================================================
If needed you can change run_vivado:23 to target 1MHz FPGA synthesis.
vivado -source vvd_caravel_fpga_1mhz.tcl -mode tcl
PYNQ-Z2 FPGA bitstream will be updated in caravel-soc_fpga/vivado/jupyter_notebook/
$ ls -alF jupyter_notebook/
total 4260
drwxrwxr-x 2 hls05 hls05 4096 5 18 06:14 ./
drwxrwxr-x 8 hls05 hls05 4096 5 18 06:31 ../
-rw-rw-r-- 1 hls05 hls05 4045676 5 18 06:34 caravel_fpga.bit
-rw-rw-r-- 1 hls05 hls05 280106 5 18 06:34 caravel_fpga.hwh
-rw-rw-r-- 1 hls05 hls05 10182 5 18 06:14 caravel_fpga.ipynb
caravel_fpga.bit
is FPGA bitstream generated by Vivado after executing run_vivado
caravel_fpga.hwh
is FPGA (HWH) hardware handoff file generated by Vivado after executing run_vivado
caravel_fpga.ipynb
is a Jupyter Notebook testbench example code for counter_la/counter_wb
Copy gcd user project design source to vivado user source directory and export environment variable USER_DESIGN_FILE
. Then, you can re-run run_vivado
to generate Caravel gcd user project FPGA bitstream.
$ cp ~/caravel-soc_fpga/rtl/user/user_proj_example.gcd.v ~/caravel-soc_fpga/vivado/vvd_srcs/caravel_soc/rtl/user
$ export USER_DESIGN_FILE=user_proj_example.gcd.v
Open your Vivado GUI block design created by run_vivado
shell script.
$ cd ~/caravel-soc_fpga/vivado/vvd_caravel_fpga
$ vivado vvd_caravel_fpga.xpr
After loading Vivado project, click Open Block Design in IP INTEGRATOR you can see Diagram window.
Before validating your Caravel user project design on FPGA board with Jupyter Notebook testbench, you should confirm the checklist of (1) compiled RISC-V firmwares, (2) FPGA bitstream, (3) FPGA HWH file and (4) Jupyter Notebook testbench example code.
For (prebuilt) Caravel counter user project:
For Caravel gcd user project:
- gcd_la.hex
- caravel_fpga.bit (follow above instructions to generate)
- caravel_fpga.hwh (follow above instructions to generate)
- caravel_fpga.ipynb (modification from example code)
Modify default counter_la.hex firmware read
fiROM = open("counter_la.hex", "r+")
#fiROM = open("counter_wb.hex", "r+")
to gcd_la.hex firmware read
#fiROM = open("counter_la.hex", "r+")
#fiROM = open("counter_wb.hex", "r+")
fiROM = open("gcd_la.hex", "r+")
You can validate designed Caravel user project on your PYNQ-Z2 board or Boledu presetup one. We demonstrate Boledu PYNQ-Z2 board user flow to explain the validation steps.
- OnlineFPGA login
######################################################
# #
# Welcome to BoLedu's OnlineFPGA service #
# Renting OnlineFPGA from service menu #
# #
# Shutdown: TPE(UTC+8) 6:00am to 7:00am #
# #
# email: [email protected] #
# #
######################################################
[1] login evaluation
[0] exit OnlineFPGA service
please enter your option:
>> 1
please enter your register email:
>> [email protected]
please enter your password:
>> *****
- OnlineFPGA rent - PYNQ-Z2 board
[1] list all online device boards
[2] rent a specified device board
[3] return your rented device board
[0] exit OnlineFPGA service
please enter your option:
>> 1
all online device boards
{'device': 'pynq_01', 'status': 'available'}
{'device': 'pynq_02', 'status': 'unknown'}
{'device': 'pynq_03', 'status': 'available'}
{'device': 'pynq_04', 'status': 'available'}
{'device': 'pynq_05', 'status': 'used'}
{'device': 'pynq_06', 'status': 'available'}
{'device': 'pynq_07', 'status': 'available'}
{'device': 'pynq_09', 'status': 'available'}
{'device': 'pynq_11', 'status': 'available'}
{'device': 'pynq_12', 'status': 'available'}
{'device': 'pynq_13', 'status': 'unknown'}
{'device': 'pynq_14', 'status': 'available'}
{'device': 'pynq_15', 'status': 'available'}
{'device': 'pynq_16', 'status': 'available'}
{'device': 'pynq_17', 'status': 'available'}
{'device': 'pynq_18', 'status': 'available'}
{'device': 'u50_01', 'status': 'available', 'user': 1, 'queue_user': 0, 'u50_board': 0, 'tenant': 9}
{'device': 'u50_02', 'status': 'available', 'user': 0, 'queue_user': 0, 'u50_board': 1, 'tenant': 7}
{'device': 'u50_03', 'status': 'available', 'user': 1, 'queue_user': 1, 'u50_board': 0, 'tenant': 8}
{'device': 'u50_04', 'status': 'available', 'user': 0, 'queue_user': 0, 'u50_board': 1, 'tenant': 7}
[1] list all online device boards
[2] rent a specified device board
[3] return your rented device board
[0] exit OnlineFPGA service
please enter your option:
>> 2
[1] pynq
[2] u50
please enter your option:
>> 1
[1] rent a device board by choice
[2] rent a device board by assignment
please enter your option:
>> 1
all online device boards
{'device': 'pynq_01', 'status': 'available'}
{'device': 'pynq_02', 'status': 'unknown'}
{'device': 'pynq_03', 'status': 'available'}
{'device': 'pynq_04', 'status': 'available'}
{'device': 'pynq_05', 'status': 'used'}
{'device': 'pynq_06', 'status': 'available'}
{'device': 'pynq_07', 'status': 'available'}
{'device': 'pynq_09', 'status': 'available'}
{'device': 'pynq_11', 'status': 'available'}
{'device': 'pynq_12', 'status': 'available'}
{'device': 'pynq_13', 'status': 'unknown'}
{'device': 'pynq_14', 'status': 'available'}
{'device': 'pynq_15', 'status': 'available'}
{'device': 'pynq_16', 'status': 'available'}
{'device': 'pynq_17', 'status': 'available'}
{'device': 'pynq_18', 'status': 'available'}
please enter pynq device name which you want to rent:
>> pynq_15
device pynq_15 is available
do you want to rent this device? (y/n)
>> y
user [email protected] rented device pynq_15 successfully
jupyter web ip port is 218.103.115.199:21500, web passwd is uqcseg and timeup at 05/24/2023 01:46:56
-
New -> Folder -> Rename default
Untitled Folder
Folder ->ipy_fpga
Folder -
Click into
ipy_fpga
Folder -> Upload all tests to wait queue from local -> Click each blue Upload bar to transfer -
Click
caravel_fpga.ipynb
to open new tab and run Jupyter Notebook test -
Run Jupyter Notebook cell-by-cell and use default
counter_la.hex
firmware -
Get final
mprj value = 0xab51
(mapping to 16-bit reg_mprj_datal in counter_la.c:128)
As demonstration, you should able to test Caravel counter with counter_wb.hex firmware, Caravel gcd with gcd_la.hex firmware and even your new Caravel user project design.
In Xilinx FPGA revision stage, we had follow modifications to pass Xilinx compiler check without changing any logic behavior of Caravel.
`default_nettype none to wire (checked by Xilinx xvlog)
- caravel-soc_fpga/vip/tbuart.v:1
- caravel-soc_fpga/vip/spiflash.v:1
- caravel-soc_fpga/rtl/user/user_project_wrapper.v:16
- caravel-soc_fpga/rtl/user/user_proj_example.counter.v:16
- caravel-soc_fpga/rtl/user/user_proj_example.gcd.v:16
- caravel-soc_fpga/rtl/soc/gpio_control_block.v:58
- caravel-soc_fpga/rtl/soc/housekeeping.v:58
- caravel-soc_fpga/rtl/soc/mprj_io.v:58
- caravel-soc_fpga/rtl/soc/housekeeping_spi.v:16
- caravel-soc_fpga/rtl/soc/mgmt_core_wrapper.v:30
- caravel-soc_fpga/rtl/soc/gpio_defaults_block.v:58
redeclaration of ansi port (checked by Xilinx xvlog)
- caravel-soc_fpga/rtl/user/user_proj_example.counter.v
- caravel-soc_fpga/rtl/user/user_proj_example.gcd.v
- caravel-soc_fpga/rtl/soc/gpio_control_block.v
- caravel-soc_fpga/rtl/soc/gpio_defaults_block.v
- caravel-soc_fpga/rtl/soc/housekeeping.v
comment out `timescale 1 ns / 1 ps (checked by Xilinx xelab)
- caravel-soc_fpga/testbench/counter_la_tb.v
- caravel-soc_fpga/testbench/counter_wb_tb.v
- caravel-soc_fpga/testbench/gcd_la_tb.v
- caravel-soc_fpga/vip/tbuart.v
- caravel-soc_fpga/vip/spiflash.v
In first revision stage, we bypassed modules which have SKY PDK dependencies and removed package-facing pins like VDD, VS, VCC. But we had kept the same logic behavior of whole Caravel.
- caravel-soc_fpga/rtl/soc-efabless/caravel.v was modified to caravel-soc_fpga/rtl/soc/caravel.v
- caravel-soc_fpga/rtl/soc-efabless/chip_io.v was modified to caravel-soc_fpga/rtl/soc/chip_io.v
- caravel-soc_fpga/rtl/soc-efabless/gpio_control_block.v was modified to caravel-soc_fpga/rtl/soc/gpio_control_block.v
- caravel-soc_fpga/rtl/soc-efabless/gpio_defaults_block.v was modified to caravel-soc_fpga/rtl/soc/gpio_defaults_block.v
- caravel-soc_fpga/rtl/soc-efabless/mprj_io.v was modified to caravel-soc_fpga/rtl/soc/mprj_io.v
- caravel-soc_fpga/rtl/soc-efabless/housekeeping.v was modified to caravel-soc_fpga/rtl/soc/housekeeping.v
The original Efabless Caravel harness used behavior caravel-soc_fpga/vip/spiflash.v. We rewrote to RTL caravel-soc_fpga/rtl/soc/spiflash.v (FPGA synthesizable) and behavior caravel-soc_fpga/vip/bram.v (needs FPGA BRAM porting). The behavior bram module was also be instantiated in corresponded Caravel testbench.
xvlog -d FUNCTIONAL -d SIM -d DUNIT_DELAY=#1 -d USE_POWER_PINS -f ./include.rtl.list.xsim $design_tb.v
xelab -top $design_tb -snapshot $design_tb_elab
xsim $design_tb_elab -R
Boledu provides presetup Xilinx Vitis Ubuntu machines. The follow Boledu Vitis machine user flow demonstrates the usages of Xilinx Vitis .
- OnlineFPGA login
######################################################
# #
# Welcome to BoLedu's OnlineFPGA service #
# Renting OnlineFPGA from service menu #
# #
# Shutdown: TPE(UTC+8) 6:00am to 7:00am #
# #
# email: [email protected] #
# #
######################################################
[1] login evaluation
[0] exit OnlineFPGA service
please enter your option:
>> 1
please enter your register email:
>> [email protected]
please enter your password:
>> *****
- OnlineFPGA rent - Vitis Machine
[1] list all online device boards
[2] rent a specified device board
[3] return your rented device board
[0] exit OnlineFPGA service
please enter your option:
>> 1
all online device boards
{'device': 'pynq_01', 'status': 'available'}
{'device': 'pynq_02', 'status': 'unknown'}
{'device': 'pynq_03', 'status': 'available'}
{'device': 'pynq_04', 'status': 'available'}
{'device': 'pynq_05', 'status': 'available'}
{'device': 'pynq_06', 'status': 'available'}
{'device': 'pynq_07', 'status': 'available'}
{'device': 'pynq_09', 'status': 'available'}
{'device': 'pynq_11', 'status': 'available'}
{'device': 'pynq_12', 'status': 'available'}
{'device': 'pynq_13', 'status': 'available'}
{'device': 'pynq_14', 'status': 'available'}
{'device': 'pynq_15', 'status': 'available'}
{'device': 'pynq_16', 'status': 'unknown'}
{'device': 'pynq_17', 'status': 'available'}
{'device': 'pynq_18', 'status': 'available'}
{'device': 'u50_01', 'status': 'available', 'user': 0, 'queue_user': 0, 'u50_board': 1, 'tenant': 9}
{'device': 'u50_02', 'status': 'available', 'user': 0, 'queue_user': 0, 'u50_board': 1, 'tenant': 8}
{'device': 'u50_03', 'status': 'available', 'user': 0, 'queue_user': 0, 'u50_board': 1, 'tenant': 8}
{'device': 'u50_04', 'status': 'available', 'user': 0, 'queue_user': 0, 'u50_board': 1, 'tenant': 7}
[1] list all online device boards
[2] rent a specified device board
[3] return your rented device board
[0] exit OnlineFPGA service
please enter your option:
>> 2
[1] pynq
[2] u50
please enter your option:
>> 2
[1] vitis tool
please enter your option:
>> 1
all online device boards
{'device': 'u50_01', 'status': 'available', 'user': 0, 'queue_user': 0, 'u50_board': 1, 'tenant': 9}
{'device': 'u50_02', 'status': 'available', 'user': 0, 'queue_user': 0, 'u50_board': 1, 'tenant': 8}
{'device': 'u50_03', 'status': 'available', 'user': 0, 'queue_user': 0, 'u50_board': 1, 'tenant': 8}
{'device': 'u50_04', 'status': 'available', 'user': 0, 'queue_user': 0, 'u50_board': 1, 'tenant': 7}
please enter u50 device name which you want to rent:
>> u50_02
device u50_02 is available
do you want to rent this device? (y/n)
>> y
user [email protected] rented device u50_02 successfully
ssh ip port is 218.103.115.199:1200, ssh username/passwd is 02.pdhkcv and timeup at 05/25/2023 11:40:30
-
We use MobaXterm to SSH host
218.103.115.199
, port1200
, username02.pdhkcv
and passwd02.pdhkcv
. -
The Boledu OnlineFPGA users don't have sudo permission but they can run all commands used in Caravel SoC FPGA project. We demonstrate usages of
run_xsim
,gtkwave
andrun_vivado
.
02.pdhkcv@HLS02:~$ git clone https://github.com/bol-edu/caravel-soc_fpga
Cloning into 'caravel-soc_fpga'...
remote: Enumerating objects: 1386, done.
remote: Counting objects: 100% (348/348), done.
remote: Compressing objects: 100% (223/223), done.
remote: Total 1386 (delta 242), reused 175 (delta 125), pack-reused 1038
Receiving objects: 100% (1386/1386), 13.37 MiB | 20.34 MiB/s, done.
Resolving deltas: 100% (758/758), done.
Updating files: 100% (570/570), done.
02.pdhkcv@HLS02:~$ cd caravel-soc_fpga/testbench/counter_la/
~/caravel-soc_fpga/testbench/counter_la ~
02.pdhkcv@HLS02:~/caravel-soc_fpga/testbench/counter_la$ ./run_xsim
...
... boledu skip lot of simulation info...
...
LA Test 1 started
LA Test 2 passed
$finish called at time : 974137500 ps : File "/mnt/HLSNAS/02.pdhkcv/caravel-soc_fpga/testbench/counter_la/counter_la_tb.v" Line 164
exit
INFO: [Common 17-206] Exiting xsim at Thu May 25 10:13:18 2023...
02.pdhkcv@HLS02:~/caravel-soc_fpga/testbench/counter_la$ gtkwave waveform.gtkw
GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
[0] start time.
[974125000] end time.
WM Destroy
02.pdhkcv@HLS02:~/caravel-soc_fpga/testbench/counter_la$ cd ~/caravel-soc_fpga/vivado/
~/caravel-soc_fpga/vivado ~/caravel-soc_fpga/testbench/counter_la
02.pdhkcv@HLS02:~/caravel-soc_fpga/vivado$ ./run_vivado
start vivado project
****** Vivado v2022.1 (64-bit)
**** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
**** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
...
... boledu skip lot of simulation info...
...
open_run: Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 3469.965 ; gain = 253.809 ; free physical = 38116 ; free virtual = 75592
# report_timing_summary -file timing_report.log
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# exit
INFO: [Common 17-206] Exiting Vivado at Thu May 25 10:23:31 2023...
======================================================================
vivado complete
======================================================================
02.pdhkcv@HLS02:~/caravel-soc_fpga/vivado$
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The Xilinx Vitis 2022.1 can be found in these regions: us-east-1, us-east-2, us-west-1 and us-west-2
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Create key pair name 'vitis.rsa.key' and key pair file is needed to download to local
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Create security group -> Confirm Summary (Vitis 2022.1 AMI, m5.2xlarge Instance, New security group and 220GiB volume) -> Launch instance
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Click EC2 instance i-00aff7b2ccd9cb2c1 (vitis.server) to find Public IPv4 address '18.207.96.216'
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We use MobaXterm to connect EC2 Ubuntu vitis.server
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While finishing usage of vitis.server, remember go to EC2 console and select Running instance i-00aff7b2ccd9cb2c1 -> Instance state -> Terminate instance