diff --git a/src/memory/mod.rs b/src/memory/mod.rs
index ce76cd8..c9d5d20 100644
--- a/src/memory/mod.rs
+++ b/src/memory/mod.rs
@@ -2,19 +2,16 @@ mod banked;
 mod block;
 mod branch;
 mod logging;
-mod mos6510;
+pub mod mos6510;
 /// The various interface adapters (6520, 6522, 6526) for the MOS 6502 CPU.
 pub mod mos652x;
 mod null;
-mod ports;
 
 pub use banked::BankedMemory;
 pub use block::BlockMemory;
 pub use branch::BranchMemory;
 pub use logging::LoggingMemory;
-pub use mos6510::Mos6510Port;
 pub use null::NullMemory;
-pub use ports::{NullPort, Port};
 
 /// Represents the state of the interrupts on the system.
 #[derive(Debug, PartialEq, Eq)]
diff --git a/src/memory/mos6510.rs b/src/memory/mos6510.rs
index b27b5bc..2c366ba 100644
--- a/src/memory/mos6510.rs
+++ b/src/memory/mos6510.rs
@@ -1,9 +1,15 @@
-use super::{ActiveInterrupt, Memory, Port};
+use super::{ActiveInterrupt, Memory};
+
+pub trait Mos6510PortInterface {
+  fn reset(&mut self);
+  fn read(&mut self) -> u8;
+  fn write(&mut self, value: u8);
+}
 
 /// Represents the port built into a MOS 6510 processor, mapped to memory addresses 0x0000 (for the DDR) and 0x0001 (for the port itself).
 pub struct Mos6510Port {
   /// The port itself.
-  port: Box<dyn Port>,
+  port: Box<dyn Mos6510PortInterface>,
 
   /// If the DDR is write, the current written value.
   writes: u8,
@@ -14,7 +20,7 @@ pub struct Mos6510Port {
 
 impl Mos6510Port {
   /// Create a new MOS 6510 port with the given port.
-  pub fn new(port: Box<dyn Port>) -> Self {
+  pub fn new(port: Box<dyn Mos6510PortInterface>) -> Self {
     Self {
       port,
       writes: 0,
@@ -27,7 +33,7 @@ impl Memory for Mos6510Port {
   fn read(&mut self, address: u16) -> u8 {
     match address % 2 {
       0 => self.ddr,
-      1 => (self.port.read_data() & !self.ddr) | (self.writes & self.ddr),
+      1 => (self.port.read() & !self.ddr) | (self.writes & self.ddr),
       _ => unreachable!(),
     }
   }
@@ -36,11 +42,11 @@ impl Memory for Mos6510Port {
     match address % 2 {
       0 => {
         self.ddr = value;
-        self.port.write_data(self.writes & self.ddr);
+        self.port.write(self.writes & self.ddr);
       }
       1 => {
         self.writes = value;
-        self.port.write_data(value & self.ddr);
+        self.port.write(value & self.ddr);
       }
       _ => unreachable!(),
     }
diff --git a/src/memory/mos652x/cia.rs b/src/memory/mos652x/cia.rs
index 79c40eb..9b0d922 100644
--- a/src/memory/mos652x/cia.rs
+++ b/src/memory/mos652x/cia.rs
@@ -1,6 +1,6 @@
 use crate::memory::{
-  mos652x::{InterruptRegister, PortRegisters, ShiftRegister, Timer},
-  ActiveInterrupt, Memory, Port,
+  mos652x::{InterruptRegister, Port, PortRegisters, ShiftRegister, Timer},
+  ActiveInterrupt, Memory,
 };
 
 struct TimeRegisters {
@@ -234,7 +234,7 @@ impl Memory for Cia {
 
 #[cfg(test)]
 mod tests {
-  use crate::memory::NullPort;
+  use crate::memory::mos652x::NullPort;
 
   use super::*;
 
diff --git a/src/memory/mos652x/mod.rs b/src/memory/mos652x/mod.rs
index e092e63..73466c6 100644
--- a/src/memory/mos652x/mod.rs
+++ b/src/memory/mos652x/mod.rs
@@ -1,13 +1,13 @@
 mod cia;
 mod pia;
+mod port;
 mod via;
 
 pub use cia::Cia;
 pub use pia::Pia;
+pub use port::{NullPort, Port};
 pub use via::Via;
 
-use crate::memory::Port;
-
 #[derive(PartialEq)]
 pub enum ActiveTransition {
   Rising,
diff --git a/src/memory/mos652x/pia.rs b/src/memory/mos652x/pia.rs
index 0630b53..415f501 100644
--- a/src/memory/mos652x/pia.rs
+++ b/src/memory/mos652x/pia.rs
@@ -1,4 +1,4 @@
-use crate::memory::{ActiveInterrupt, Memory, Port};
+use crate::memory::{mos652x::Port, ActiveInterrupt, Memory};
 
 // MOS 6520
 
@@ -180,7 +180,7 @@ impl Memory for Pia {
 
 #[cfg(test)]
 mod tests {
-  use crate::memory::NullPort;
+  use crate::memory::mos652x::NullPort;
 
   use super::*;
 
diff --git a/src/memory/ports.rs b/src/memory/mos652x/port.rs
similarity index 100%
rename from src/memory/ports.rs
rename to src/memory/mos652x/port.rs
diff --git a/src/memory/mos652x/via.rs b/src/memory/mos652x/via.rs
index 42e522c..343ffac 100644
--- a/src/memory/mos652x/via.rs
+++ b/src/memory/mos652x/via.rs
@@ -1,6 +1,6 @@
 use crate::memory::{
-  mos652x::{InterruptRegister, PortRegisters, ShiftRegister, Timer, TimerOutput},
-  ActiveInterrupt, Memory, Port,
+  mos652x::{InterruptRegister, Port, PortRegisters, ShiftRegister, Timer, TimerOutput},
+  ActiveInterrupt, Memory,
 };
 
 use super::ActiveTransition;
@@ -256,7 +256,7 @@ impl Memory for Via {
 
 #[cfg(test)]
 mod tests {
-  use crate::memory::NullPort;
+  use crate::memory::mos652x::NullPort;
 
   use super::*;
 
diff --git a/src/systems/c64/mod.rs b/src/systems/c64/mod.rs
index dbadca7..2eb6550 100644
--- a/src/systems/c64/mod.rs
+++ b/src/systems/c64/mod.rs
@@ -12,7 +12,9 @@ use crate::{
     KeyAdapter, KeyMappingStrategy, SymbolAdapter,
   },
   memory::{
-    mos652x::Cia, BankedMemory, BlockMemory, BranchMemory, Mos6510Port, NullMemory, NullPort, Port,
+    mos6510::{Mos6510Port, Mos6510PortInterface},
+    mos652x::{Cia, NullPort, Port},
+    BankedMemory, BlockMemory, BranchMemory, NullMemory,
   },
   platform::{PlatformProvider, WindowConfig},
   systems::System,
@@ -154,13 +156,13 @@ impl C64BankSwitching {
   }
 }
 
-impl Port for C64BankSwitching {
-  fn read_data(&mut self) -> u8 {
+impl Mos6510PortInterface for C64BankSwitching {
+  fn read(&mut self) -> u8 {
     (self.loram as u8) | (self.hiram as u8) << 1 | (self.charen as u8) << 2
   }
 
   #[allow(clippy::bool_to_int_with_if)]
-  fn write_data(&mut self, value: u8) {
+  fn write(&mut self, value: u8) {
     self.loram = (value & 0b001) != 0;
     self.hiram = (value & 0b010) != 0;
     self.charen = (value & 0b100) != 0;
@@ -192,17 +194,11 @@ impl Port for C64BankSwitching {
     self.selectors[5].set(if !self.hiram { 1 } else { 0 });
   }
 
-  fn read_control(&mut self, _cycles_since_poll: u64, _total_cycle_count: u64) -> (bool, bool) {
-    (false, false)
-  }
-
   fn reset(&mut self) {
     self.hiram = true;
     self.loram = true;
     self.charen = true;
   }
-
-  fn write_cx2(&mut self, _value: bool) {}
 }
 
 /// Configuration for a Commodore 64 system.
diff --git a/src/systems/pet/mod.rs b/src/systems/pet/mod.rs
index 3384bce..6369b50 100644
--- a/src/systems/pet/mod.rs
+++ b/src/systems/pet/mod.rs
@@ -3,8 +3,8 @@ use crate::cpu::{
   Cpu,
 };
 use crate::keyboard::{KeyAdapter, KeyMappingStrategy, SymbolAdapter};
-use crate::memory::mos652x::{Pia, Via};
-use crate::memory::{BlockMemory, BranchMemory, NullMemory, NullPort, Port};
+use crate::memory::mos652x::{NullPort, Pia, Port, Via};
+use crate::memory::{BlockMemory, BranchMemory, NullMemory};
 use crate::platform::{Color, PlatformProvider, WindowConfig};
 use crate::systems::{BuildableSystem, System};
 use instant::Instant;
diff --git a/src/systems/vic/mod.rs b/src/systems/vic/mod.rs
index f235988..9b3149a 100644
--- a/src/systems/vic/mod.rs
+++ b/src/systems/vic/mod.rs
@@ -7,8 +7,8 @@ use crate::keyboard::{
   commodore::{C64KeyboardAdapter, C64SymbolAdapter},
   KeyAdapter, KeyMappingStrategy, SymbolAdapter,
 };
-use crate::memory::mos652x::Via;
-use crate::memory::{BlockMemory, BranchMemory, NullMemory, NullPort, Port};
+use crate::memory::mos652x::{NullPort, Port, Via};
+use crate::memory::{BlockMemory, BranchMemory, NullMemory};
 use crate::platform::{PlatformProvider, WindowConfig};
 use crate::roms::RomFile;
 use crate::systems::System;